From 444053e3c42ace09d21e6eff1b7dcd19804c8640 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 23 Jan 2025 11:39:38 +0100 Subject: [PATCH 01/15] pwm: lpss: Only include where needed MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Among the three files that include pwm-lpss.h only pwm-lpss.c actually needs . So move the #include statement from the former to the latter. Signed-off-by: Uwe Kleine-König Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20250123103939.357160-2-u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-lpss.c | 1 + drivers/pwm/pwm-lpss.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-lpss.c b/drivers/pwm/pwm-lpss.c index 3b99feb3bb49..5accab033b8b 100644 --- a/drivers/pwm/pwm-lpss.c +++ b/drivers/pwm/pwm-lpss.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #define DEFAULT_SYMBOL_NAMESPACE "PWM_LPSS" diff --git a/drivers/pwm/pwm-lpss.h b/drivers/pwm/pwm-lpss.h index b5267ab5193b..60792181401e 100644 --- a/drivers/pwm/pwm-lpss.h +++ b/drivers/pwm/pwm-lpss.h @@ -10,7 +10,6 @@ #ifndef __PWM_LPSS_H #define __PWM_LPSS_H -#include #include #include From d893760cedbfef232b5bbd062ce62893a23eaca6 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Wed, 5 Feb 2025 15:00:47 +0800 Subject: [PATCH 02/15] dt-bindings: pwm: sophgo: add PWM controller for SG2042 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sophgo SG2042 contains a PWM controller, which has 4 channels and can generate PWM waveforms output. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Chen Wang Link: https://lore.kernel.org/r/d739ea5a1bffcf762248efbe25fae9b9fda6f452.1738737617.git.unicorn_wang@outlook.com Signed-off-by: Uwe Kleine-König --- .../bindings/pwm/sophgo,sg2042-pwm.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml b/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml new file mode 100644 index 000000000000..bbb6326d47d7 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/sophgo,sg2042-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PWM controller + +maintainers: + - Chen Wang + +description: + This controller contains 4 channels which can generate PWM waveforms. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: sophgo,sg2042-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + #include + + pwm@7f006000 { + compatible = "sophgo,sg2042-pwm"; + reg = <0x7f006000 0x1000>; + #pwm-cells = <3>; + clocks = <&clock 67>; + clock-names = "apb"; + resets = <&rstgen RST_PWM>; + }; From c98e66144b7d07ee9a3ca8241123b628a8ac0288 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Wed, 5 Feb 2025 15:01:13 +0800 Subject: [PATCH 03/15] pwm: sophgo: add driver for Sophgo SG2042 PWM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a PWM driver for PWM controller in Sophgo SG2042 SoC. Signed-off-by: Sean Young Signed-off-by: Chen Wang Link: https://lore.kernel.org/r/ae8ea1bf0bb0a09336cd8b7f627a994630524bba.1738737617.git.unicorn_wang@outlook.com [ukleinek: Drop unneeded reset_control_assert() from error path] Signed-off-by: Uwe Kleine-König --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sophgo-sg2042.c | 194 ++++++++++++++++++++++++++++++++ 3 files changed, 205 insertions(+) create mode 100644 drivers/pwm/pwm-sophgo-sg2042.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 0915c1e7df16..ec85f3895936 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -584,6 +584,16 @@ config PWM_SL28CPLD To compile this driver as a module, choose M here: the module will be called pwm-sl28cpld. +config PWM_SOPHGO_SG2042 + tristate "Sophgo SG2042 PWM support" + depends on ARCH_SOPHGO || COMPILE_TEST + help + PWM driver for the PWM controller on Sophgo SG2042 SoC. The PWM + controller supports outputing 4 channels of PWM waveforms. + + To compile this driver as a module, choose M here: the module + will be called pwm_sophgo_sg2042. + config PWM_SPEAR tristate "STMicroelectronics SPEAr PWM support" depends on PLAT_SPEAR || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 9081e0c0e9e0..539e0def3f82 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_PWM_RZ_MTU3) += pwm-rz-mtu3.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o +obj-$(CONFIG_PWM_SOPHGO_SG2042) += pwm-sophgo-sg2042.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o obj-$(CONFIG_PWM_STI) += pwm-sti.o diff --git a/drivers/pwm/pwm-sophgo-sg2042.c b/drivers/pwm/pwm-sophgo-sg2042.c new file mode 100644 index 000000000000..ff4639d849ce --- /dev/null +++ b/drivers/pwm/pwm-sophgo-sg2042.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sophgo SG2042 PWM Controller Driver + * + * Copyright (C) 2024 Sophgo Technology Inc. + * Copyright (C) 2024 Chen Wang + * + * Limitations: + * - After reset, the output of the PWM channel is always high. + * The value of HLPERIOD/PERIOD is 0. + * - When HLPERIOD or PERIOD is reconfigured, PWM will start to + * output waveforms with the new configuration after completing + * the running period. + * - When PERIOD and HLPERIOD is set to 0, the PWM wave output will + * be stopped and the output is pulled to high. + * See the datasheet [1] for more details. + * [1]:https://github.com/sophgo/sophgo-doc/tree/main/SG2042/TRM + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Offset RegisterName + * 0x0000 HLPERIOD0 + * 0x0004 PERIOD0 + * 0x0008 HLPERIOD1 + * 0x000C PERIOD1 + * 0x0010 HLPERIOD2 + * 0x0014 PERIOD2 + * 0x0018 HLPERIOD3 + * 0x001C PERIOD3 + * Four groups and every group is composed of HLPERIOD & PERIOD + */ +#define SG2042_PWM_HLPERIOD(chan) ((chan) * 8 + 0) +#define SG2042_PWM_PERIOD(chan) ((chan) * 8 + 4) + +#define SG2042_PWM_CHANNELNUM 4 + +/** + * struct sg2042_pwm_ddata - private driver data + * @base: base address of mapped PWM registers + * @clk_rate_hz: rate of base clock in HZ + */ +struct sg2042_pwm_ddata { + void __iomem *base; + unsigned long clk_rate_hz; +}; + +/* + * period_ticks: PERIOD + * hlperiod_ticks: HLPERIOD + */ +static void pwm_sg2042_config(struct sg2042_pwm_ddata *ddata, unsigned int chan, + u32 period_ticks, u32 hlperiod_ticks) +{ + void __iomem *base = ddata->base; + + writel(period_ticks, base + SG2042_PWM_PERIOD(chan)); + writel(hlperiod_ticks, base + SG2042_PWM_HLPERIOD(chan)); +} + +static int pwm_sg2042_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct sg2042_pwm_ddata *ddata = pwmchip_get_drvdata(chip); + u32 hlperiod_ticks; + u32 period_ticks; + + if (state->polarity == PWM_POLARITY_INVERSED) + return -EINVAL; + + if (!state->enabled) { + pwm_sg2042_config(ddata, pwm->hwpwm, 0, 0); + return 0; + } + + /* + * Duration of High level (duty_cycle) = HLPERIOD x Period_of_input_clk + * Duration of One Cycle (period) = PERIOD x Period_of_input_clk + */ + period_ticks = min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->period, NSEC_PER_SEC), U32_MAX); + hlperiod_ticks = min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->duty_cycle, NSEC_PER_SEC), U32_MAX); + + dev_dbg(pwmchip_parent(chip), "chan[%u]: PERIOD=%u, HLPERIOD=%u\n", + pwm->hwpwm, period_ticks, hlperiod_ticks); + + pwm_sg2042_config(ddata, pwm->hwpwm, period_ticks, hlperiod_ticks); + + return 0; +} + +static int pwm_sg2042_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct sg2042_pwm_ddata *ddata = pwmchip_get_drvdata(chip); + unsigned int chan = pwm->hwpwm; + u32 hlperiod_ticks; + u32 period_ticks; + + period_ticks = readl(ddata->base + SG2042_PWM_PERIOD(chan)); + hlperiod_ticks = readl(ddata->base + SG2042_PWM_HLPERIOD(chan)); + + if (!period_ticks) { + state->enabled = false; + return 0; + } + + if (hlperiod_ticks > period_ticks) + hlperiod_ticks = period_ticks; + + state->enabled = true; + state->period = DIV_ROUND_UP_ULL((u64)period_ticks * NSEC_PER_SEC, ddata->clk_rate_hz); + state->duty_cycle = DIV_ROUND_UP_ULL((u64)hlperiod_ticks * NSEC_PER_SEC, ddata->clk_rate_hz); + state->polarity = PWM_POLARITY_NORMAL; + + return 0; +} + +static const struct pwm_ops pwm_sg2042_ops = { + .apply = pwm_sg2042_apply, + .get_state = pwm_sg2042_get_state, +}; + +static const struct of_device_id sg2042_pwm_ids[] = { + { .compatible = "sophgo,sg2042-pwm" }, + { } +}; +MODULE_DEVICE_TABLE(of, sg2042_pwm_ids); + +static int pwm_sg2042_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sg2042_pwm_ddata *ddata; + struct reset_control *rst; + struct pwm_chip *chip; + struct clk *clk; + int ret; + + chip = devm_pwmchip_alloc(dev, SG2042_PWM_CHANNELNUM, sizeof(*ddata)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + ddata = pwmchip_get_drvdata(chip); + + ddata->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ddata->base)) + return PTR_ERR(ddata->base); + + clk = devm_clk_get_enabled(dev, "apb"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "Failed to get base clk\n"); + + ret = devm_clk_rate_exclusive_get(dev, clk); + if (ret) + return dev_err_probe(dev, ret, "Failed to get exclusive rate\n"); + + ddata->clk_rate_hz = clk_get_rate(clk); + /* period = PERIOD * NSEC_PER_SEC / clk_rate_hz */ + if (!ddata->clk_rate_hz || ddata->clk_rate_hz > NSEC_PER_SEC) + return dev_err_probe(dev, -EINVAL, + "Invalid clock rate: %lu\n", ddata->clk_rate_hz); + + rst = devm_reset_control_get_optional_shared_deasserted(dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset\n"); + + chip->ops = &pwm_sg2042_ops; + chip->atomic = true; + + ret = devm_pwmchip_add(dev, chip); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to register PWM chip\n"); + + return 0; +} + +static struct platform_driver pwm_sg2042_driver = { + .driver = { + .name = "sg2042-pwm", + .of_match_table = sg2042_pwm_ids, + }, + .probe = pwm_sg2042_probe, +}; +module_platform_driver(pwm_sg2042_driver); + +MODULE_AUTHOR("Chen Wang"); +MODULE_DESCRIPTION("Sophgo SG2042 PWM driver"); +MODULE_LICENSE("GPL"); From e320a24059f8fd06c60a5cc295bcc53eff759d30 Mon Sep 17 00:00:00 2001 From: Nam Cao Date: Wed, 5 Feb 2025 11:46:31 +0100 Subject: [PATCH 04/15] pwm: gpio: Switch to use hrtimer_setup() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit hrtimer_setup() takes the callback function pointer as argument and initializes the timer completely. Replace hrtimer_init() and the open coded initialization of hrtimer::function with the new setup mechanism. Acked-by: Zack Rusin Signed-off-by: Nam Cao Link: https://lore.kernel.org/r/7b7115da84372a49e36a0ac1a5ce553129c3ce0b.1738746904.git.namcao@linutronix.de Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-gpio.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-gpio.c b/drivers/pwm/pwm-gpio.c index 9f8884ac7504..5f4edeb394a9 100644 --- a/drivers/pwm/pwm-gpio.c +++ b/drivers/pwm/pwm-gpio.c @@ -207,13 +207,12 @@ static int pwm_gpio_probe(struct platform_device *pdev) chip->ops = &pwm_gpio_ops; chip->atomic = true; - hrtimer_init(&gpwm->gpio_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + hrtimer_setup(&gpwm->gpio_timer, pwm_gpio_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + ret = devm_add_action_or_reset(dev, pwm_gpio_disable_hrtimer, gpwm); if (ret) return ret; - gpwm->gpio_timer.function = pwm_gpio_timer; - ret = pwmchip_add(chip); if (ret < 0) return dev_err_probe(dev, ret, "could not add pwmchip\n"); From 895fe4537cc8586f51abb5c66524efaa42c29883 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 6 Feb 2025 13:06:25 +0100 Subject: [PATCH 05/15] pwm: Add upgrade path to #pwm-cells = <3> for users of of_pwm_single_xlate() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PWM chip on PXA only has a single output. Back when the device tree binding was defined it was considered a good idea to not pass the PWM line index as is done for all other PWM types as it would be always zero anyhow and so doesn't add any value. However for consistency reasons it is nice when all PWMs use the same binding. For that reason let of_pwm_single_xlate() (i.e. the function that implements the PXA behaviour) behave in the same way as of_pwm_xlate_with_flags() for 3 (or more) parameters. With that in place, the pxa-pwm binding can be updated to #pwm-cells = <3> without breaking old device trees that stick to #pwm-cells = <1>. Reviewed-by: Herve Codina Tested-by: Duje Mihanović Reviewed-by: Daniel Mack Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/b33a84d3f073880e94fc303cd32ebe095eb5ce46.1738842938.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/core.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index ccd54c089bab..bc05818fa370 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -1000,11 +1000,27 @@ of_pwm_xlate_with_flags(struct pwm_chip *chip, const struct of_phandle_args *arg } EXPORT_SYMBOL_GPL(of_pwm_xlate_with_flags); +/* + * This callback is used for PXA PWM chips that only have a single PWM line. + * For such chips you could argue that passing the line number (i.e. the first + * parameter in the common case) is useless as it's always zero. So compared to + * the default xlate function of_pwm_xlate_with_flags() the first parameter is + * the default period and the second are flags. + * + * Note that if #pwm-cells = <3>, the semantic is the same as for + * of_pwm_xlate_with_flags() to allow converting the affected driver to + * #pwm-cells = <3> without breaking the legacy binding. + * + * Don't use for new drivers. + */ struct pwm_device * of_pwm_single_xlate(struct pwm_chip *chip, const struct of_phandle_args *args) { struct pwm_device *pwm; + if (args->args_count >= 3) + return of_pwm_xlate_with_flags(chip, args); + pwm = pwm_request_from_chip(chip, 0, NULL); if (IS_ERR(pwm)) return pwm; From 963f117530e0d0526fc54d0e0705c2201e373aca Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Wed, 5 Feb 2025 10:55:42 +0100 Subject: [PATCH 06/15] dt-bindings: pwm: Add support for PWM nexus node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Platforms can have a standardized connector/expansion slot that exposes PWMs signals to expansion boards. A nexus node [1] allows to remap a phandle list in a consumer node through a connector node in a generic way. With this remapping, the consumer node needs to know only about the nexus node. Resources behind the nexus node are decoupled by the nexus node itself. This is particularly useful when this consumer is described in a device-tree overlay. Indeed, to have the exact same overlay reused with several base systems the overlay needs to known only about the connector is going to be applied to without any knowledge of the SoC (or the component providing the resource) available in the system. As an example, suppose 3 PWMs connected to a connector. The connector PWM 0 and 2 comes from the PWM 1 and 3 of the pwm-controller1. The connector PWM 1 comes from the PWM 4 of the pwm-controller2. An expansion device is connected to the connector and uses the connector PMW 1. Nexus node support in PWM allows the following description: soc { soc_pwm1: pwm-controller1 { #pwm-cells = <3>; }; soc_pwm2: pwm-controller2 { #pwm-cells = <3>; }; }; connector: connector { #pwm-cells = <3>; pwm-map = <0 0 0 &soc_pwm1 1 0 0>, <1 0 0 &soc_pwm2 4 0 0>, <2 0 0 &soc_pwm1 3 0 0>; pwm-map-mask = <0xffffffff 0x0 0x0>; pwm-map-pass-thru = <0x0 0xffffffff 0xffffffff>; }; expansion_device { pwms = <&connector 1 57000 0>; }; >From the expansion device point of view, the PWM requested is the PWM 1 available at the connector regardless of the exact PWM wired to this connector PWM 1. Thanks to nexus node remapping described at connector node, this PWM is the PWM 4 of the pwm-controller2. [1] https://github.com/devicetree-org/devicetree-specification/blob/v0.4/source/chapter2-devicetree-basics.rst#nexus-nodes-and-specifier-mapping Signed-off-by: Herve Codina [ukleinek: Make description node use folded style (>) as suggested by Rob] Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250205095547.536083-2-herve.codina@bootlin.com Signed-off-by: Uwe Kleine-König --- .../bindings/pwm/pwm-nexus-node.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-nexus-node.yaml diff --git a/Documentation/devicetree/bindings/pwm/pwm-nexus-node.yaml b/Documentation/devicetree/bindings/pwm/pwm-nexus-node.yaml new file mode 100644 index 000000000000..3b40e271fe8d --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-nexus-node.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-nexus-node.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PWM Nexus node properties + +description: > + Platforms can have a standardized connector/expansion slot that exposes PWMs + signals to expansion boards. + + A nexus node allows to remap a phandle list in a consumer node through a + connector node in a generic way. With this remapping, the consumer node needs + to know only about the nexus node. Resources behind the nexus node are + decoupled by the nexus node itself. + +maintainers: + - Herve Codina + +select: true + +properties: + '#pwm-cells': true + + pwm-map: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + + pwm-map-mask: + $ref: /schemas/types.yaml#/definitions/uint32-array + + pwm-map-pass-thru: + $ref: /schemas/types.yaml#/definitions/uint32-array + +dependentRequired: + pwm-map: ['#pwm-cells'] + pwm-map-mask: [ pwm-map ] + pwm-map-pass-thru: [ pwm-map ] + +additionalProperties: true + +examples: + - | + pwm1: pwm@100 { + reg = <0x100 0x10>; + #pwm-cells = <3>; + }; + + pwm2: pwm@200 { + reg = <0x200 0x10>; + #pwm-cells = <3>; + }; + + connector: connector { + #pwm-cells = <3>; + pwm-map = <0 0 0 &pwm1 1 0 0>, + <1 0 0 &pwm2 4 0 0>, + <2 0 0 &pwm1 3 0 0>; + pwm-map-mask = <0xffffffff 0x0 0x0>; + pwm-map-pass-thru = <0x0 0xffffffff 0xffffffff>; + }; + + device { + pwms = <&connector 1 57000 0>; + }; From e71e46a6f19c46b38983bebde8bfac1c04968fdf Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Wed, 5 Feb 2025 10:55:43 +0100 Subject: [PATCH 07/15] pwm: Add support for pwm nexus dt bindings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Platforms can have a standardized connector/expansion slot that exposes signals like PWMs to expansion boards in an SoC agnostic way. The support for nexus node [1] has been added to handle those cases in commit bd6f2fd5a1d5 ("of: Support parsing phandle argument lists through a nexus node"). This commit introduced of_parse_phandle_with_args_map() to handle nexus nodes in a generic way and the gpio subsystem adopted the support in commit c11e6f0f04db ("gpio: Support gpio nexus dt bindings"). A nexus node allows to remap a phandle list in a consumer node through a connector node in a generic way. With this remapping supported, the consumer node needs to knwow only about the nexus node. Resources behind the nexus node are decoupled by the nexus node itself. This is particularly useful when this consumer is described in a device-tree overlay. Indeed, to have the exact same overlay reused with several base systems the overlay needs to known only about the connector is going to be applied to without any knowledge of the SoC (or the component providing the resource) available in the system. As an example, suppose 3 PWMs connected to a connector. The connector PWM 0 and 2 comes from the PWM 1 and 3 of the pwm-controller1. The connector PWM 1 comes from the PWM 4 of the pwm-controller2. An expansion device is connected to the connector and uses the connector PMW 1. Nexus node support in PWM allows the following description: soc { soc_pwm1: pwm-controller1 { #pwm-cells = <3>; }; soc_pwm2: pwm-controller2 { #pwm-cells = <3>; }; }; connector: connector { #pwm-cells = <3>; pwm-map = <0 0 0 &soc_pwm1 1 0 0>, <1 0 0 &soc_pwm2 4 0 0>, <2 0 0 &soc_pwm1 3 0 0>; pwm-map-mask = <0xffffffff 0x0 0x0>; pwm-map-pass-thru = <0x0 0xffffffff 0xffffffff>; }; expansion_device { pwms = <&connector 1 57000 0>; }; >From the expansion device point of view, the PWM requested is the PWM 1 available at the connector regardless of the exact PWM wired to this connector PWM 1. Thanks to nexus node remapping described at connector node, this PWM is the PWM 4 of the pwm-controller2. The nexus node remapping handling consists in handling #pwm-cells, pwm-map, pwm-map-mask and pwm-map-pass-thru properties. This is already supported by of_parse_phandle_with_args_map() thanks to its stem_name parameter. Add support for nexus node device-tree binding and the related remapping in the PWM subsystem by simply using of_parse_phandle_with_args_map() instead of of_parse_phandle_with_args(). [1] https://github.com/devicetree-org/devicetree-specification/blob/v0.4/source/chapter2-devicetree-basics.rst#nexus-nodes-and-specifier-mapping Signed-off-by: Herve Codina Link: https://lore.kernel.org/r/20250205095547.536083-3-herve.codina@bootlin.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index bc05818fa370..a40c511e0096 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -1732,8 +1732,7 @@ static struct pwm_device *of_pwm_get(struct device *dev, struct device_node *np, return ERR_PTR(index); } - err = of_parse_phandle_with_args(np, "pwms", "#pwm-cells", index, - &args); + err = of_parse_phandle_with_args_map(np, "pwms", "pwm", index, &args); if (err) { pr_err("%s(): can't parse \"pwms\" property\n", __func__); return ERR_PTR(err); From b2693edd0963dc06cb3021f249e3bd8cfc91fdac Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 14 Feb 2025 17:40:31 +0200 Subject: [PATCH 08/15] pwm: pca9685: Drop ACPI_PTR() and of_match_ptr() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop rather useless use of ACPI_PTR() and of_match_ptr(). It also removes the necessity to be dependent acpi.h inclusion. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20250214154031.3395014-1-andriy.shevchenko@linux.intel.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-pca9685.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-pca9685.c b/drivers/pwm/pwm-pca9685.c index 1298b29183e5..5162f3991644 100644 --- a/drivers/pwm/pwm-pca9685.c +++ b/drivers/pwm/pwm-pca9685.c @@ -8,7 +8,6 @@ * based on the pwm-twl-led.c driver */ -#include #include #include #include @@ -639,21 +638,17 @@ static const struct i2c_device_id pca9685_id[] = { }; MODULE_DEVICE_TABLE(i2c, pca9685_id); -#ifdef CONFIG_ACPI static const struct acpi_device_id pca9685_acpi_ids[] = { { "INT3492", 0 }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(acpi, pca9685_acpi_ids); -#endif -#ifdef CONFIG_OF static const struct of_device_id pca9685_dt_ids[] = { { .compatible = "nxp,pca9685-pwm", }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, pca9685_dt_ids); -#endif static const struct dev_pm_ops pca9685_pwm_pm = { SET_RUNTIME_PM_OPS(pca9685_pwm_runtime_suspend, @@ -663,8 +658,8 @@ static const struct dev_pm_ops pca9685_pwm_pm = { static struct i2c_driver pca9685_i2c_driver = { .driver = { .name = "pca9685-pwm", - .acpi_match_table = ACPI_PTR(pca9685_acpi_ids), - .of_match_table = of_match_ptr(pca9685_dt_ids), + .acpi_match_table = pca9685_acpi_ids, + .of_match_table = pca9685_dt_ids, .pm = &pca9685_pwm_pm, }, .probe = pca9685_pwm_probe, From f2037a3ee9b4e3646882e6635ec097c08772a32f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 14 Feb 2025 17:34:42 +0100 Subject: [PATCH 09/15] pwm: clps711x: Drop of_match_ptr() usage for .of_match_table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The pwm-clps711x driver depends on ARCH_CLPS711X || COMPILE_TEST. With the former being an ARCH_MULTI_V4T platform, there is always OF=y when ARCH_CLPS711X=y, so in practise clps711x_pwm_dt_ids[] is always used. (And in the case COMPILE_TEST=y + OF=n this only increases the driver size a bit but still compiles.) So drop the usage of of_match_ptr(). Signed-off-by: Uwe Kleine-König Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20250214163442.192006-2-u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/pwm-clps711x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-clps711x.c b/drivers/pwm/pwm-clps711x.c index c950e1dbd2b8..04559a9de718 100644 --- a/drivers/pwm/pwm-clps711x.c +++ b/drivers/pwm/pwm-clps711x.c @@ -98,7 +98,7 @@ static int clps711x_pwm_probe(struct platform_device *pdev) return devm_pwmchip_add(&pdev->dev, chip); } -static const struct of_device_id __maybe_unused clps711x_pwm_dt_ids[] = { +static const struct of_device_id clps711x_pwm_dt_ids[] = { { .compatible = "cirrus,ep7209-pwm", }, { } }; @@ -107,7 +107,7 @@ MODULE_DEVICE_TABLE(of, clps711x_pwm_dt_ids); static struct platform_driver clps711x_pwm_driver = { .driver = { .name = "clps711x-pwm", - .of_match_table = of_match_ptr(clps711x_pwm_dt_ids), + .of_match_table = clps711x_pwm_dt_ids, }, .probe = clps711x_pwm_probe, }; From e8af7c083520a7b9b027b2bb282464013a96047d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 27 Jan 2025 11:50:01 +0100 Subject: [PATCH 10/15] pwm: Strengthen dependency for PWM_SIFIVE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Back when the sifive pwm driver was added there was no symbol for sifive SoCs yet. Today there is ARCH_SIFIVE however. Let PWM_SIFIVE depend on that to ensure the driver is only build for platforms where there is a chance that the hardware is available. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20250127105001.587610-2-u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index ec85f3895936..63beb0010e3e 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -567,7 +567,7 @@ config PWM_SIFIVE tristate "SiFive PWM support" depends on OF depends on COMMON_CLK && HAS_IOMEM - depends on RISCV || COMPILE_TEST + depends on ARCH_SIFIVE || COMPILE_TEST help Generic PWM framework driver for SiFive SoCs. From 058210e84b48dbb670a6bf72afaed6fbd8043a37 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 27 Feb 2025 19:19:08 +0800 Subject: [PATCH 11/15] dt-bindings: pwm: rockchip: Add rockchip,rk3562-pwm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PWM core on Rockchip's RK3562 is the same as the one already included in RK3328. Extend the binding accordingly to allow compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; Signed-off-by: Kever Yang Acked-by: Uwe Kleine-König Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250227111913.2344207-11-kever.yang@rock-chips.com Signed-off-by: Uwe Kleine-König --- Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml index 65bfb492b3a4..e4e1976c542d 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml @@ -30,6 +30,7 @@ properties: - enum: - rockchip,px30-pwm - rockchip,rk3308-pwm + - rockchip,rk3562-pwm - rockchip,rk3568-pwm - rockchip,rk3588-pwm - rockchip,rv1126-pwm From 4b31eb55dbc64d72ff57a1888f8e4d7996a693bc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 17 Feb 2025 11:25:02 +0100 Subject: [PATCH 12/15] pwm: Check for CONFIG_PWM using IS_REACHABLE() in main header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Preparing CONFIG_PWM becoming tristate the right magic to check for the availability of the pwm functions is using IS_REACHABLE() and not IS_ENABLED(). The latter gives the wrong result for built-in code with CONFIG_PWM=m. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20250217102504.687916-2-u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König --- include/linux/pwm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/pwm.h b/include/linux/pwm.h index a2df509056ac..9ece4e5d3815 100644 --- a/include/linux/pwm.h +++ b/include/linux/pwm.h @@ -379,7 +379,7 @@ static inline void pwmchip_set_drvdata(struct pwm_chip *chip, void *data) dev_set_drvdata(&chip->dev, data); } -#if IS_ENABLED(CONFIG_PWM) +#if IS_REACHABLE(CONFIG_PWM) /* PWM consumer APIs */ int pwm_round_waveform_might_sleep(struct pwm_device *pwm, struct pwm_waveform *wf); @@ -661,7 +661,7 @@ struct pwm_lookup { PWM_LOOKUP_WITH_MODULE(_provider, _index, _dev_id, _con_id, _period, \ _polarity, NULL) -#if IS_ENABLED(CONFIG_PWM) +#if IS_REACHABLE(CONFIG_PWM) void pwm_add_table(struct pwm_lookup *table, size_t num); void pwm_remove_table(struct pwm_lookup *table, size_t num); #else From a2b8191ab695ab4dacd1b923a757e9b548760cec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sat, 15 Feb 2025 15:37:22 +0100 Subject: [PATCH 13/15] pwm: stmpe: Allow to compile as a module MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit pwm-stmpe is the only driver that cannot be built as a module. Add the necessary boilerplate to also make this driver modular. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20250215143723.636591-2-u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König --- drivers/pwm/Kconfig | 2 +- drivers/pwm/pwm-stmpe.c | 25 +++++++++++++++++++++++-- 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 63beb0010e3e..4731d5b90d7e 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -646,7 +646,7 @@ config PWM_STM32_LP will be called pwm-stm32-lp. config PWM_STMPE - bool "STMPE expander PWM export" + tristate "STMPE expander PWM export" depends on MFD_STMPE help This enables support for the PWMs found in the STMPE I/O diff --git a/drivers/pwm/pwm-stmpe.c b/drivers/pwm/pwm-stmpe.c index bb91062d5f1d..73f12843999a 100644 --- a/drivers/pwm/pwm-stmpe.c +++ b/drivers/pwm/pwm-stmpe.c @@ -326,12 +326,33 @@ static int __init stmpe_pwm_probe(struct platform_device *pdev) return ret; } + platform_set_drvdata(pdev, chip); + return 0; } -static struct platform_driver stmpe_pwm_driver = { +static void __exit stmpe_pwm_remove(struct platform_device *pdev) +{ + struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); + struct pwm_chip *chip = platform_get_drvdata(pdev); + + pwmchip_remove(chip); + stmpe_disable(stmpe, STMPE_BLOCK_PWM); +} + +/* + * stmpe_pwm_remove() lives in .exit.text. For drivers registered via + * module_platform_driver_probe() this is ok because they cannot get unbound at + * runtime. So mark the driver struct with __refdata to prevent modpost + * triggering a section mismatch warning. + */ +static struct platform_driver stmpe_pwm_driver __refdata = { .driver = { .name = "stmpe-pwm", }, + .remove = __exit_p(stmpe_pwm_remove), }; -builtin_platform_driver_probe(stmpe_pwm_driver, stmpe_pwm_probe); +module_platform_driver_probe(stmpe_pwm_driver, stmpe_pwm_probe); + +MODULE_DESCRIPTION("STMPE expander PWM"); +MODULE_LICENSE("GPL"); From 20f23ad377592722f7b5a591e4169c0716c51543 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Fri, 7 Mar 2025 20:00:03 +0800 Subject: [PATCH 14/15] dt-bindings: pwm: rockchip: Add rockchip,rk3528-pwm MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document pwm compatible for rk3528 which is fallback compatible of rk3328-pwm group. Signed-off-by: Chukun Pan Acked-by: Conor Dooley Acked-by: Uwe Kleine-König Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250307120004.959980-2-amadeus@jmu.edu.cn Signed-off-by: Uwe Kleine-König --- Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml index e4e1976c542d..c8cdfb723336 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml @@ -30,6 +30,7 @@ properties: - enum: - rockchip,px30-pwm - rockchip,rk3308-pwm + - rockchip,rk3528-pwm - rockchip,rk3562-pwm - rockchip,rk3568-pwm - rockchip,rk3588-pwm From 6df320abbb40654085d7258de33d78481e93ac8d Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 6 Mar 2025 12:08:45 -0500 Subject: [PATCH 15/15] dt-bindings: pwm: imx: Add i.MX93, i.MX94 and i.MX95 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add compatible string "fsl,imx93-pwm", "fsl,imx94-pwm" and "fsl,imx95-pwm", which is backward compatible with i.MX7ULP. Set it to fall back to "fsl,imx7ulp-pwm". Signed-off-by: Frank Li Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250306170845.240555-1-Frank.Li@nxp.com Signed-off-by: Uwe Kleine-König --- .../devicetree/bindings/pwm/imx-tpm-pwm.yaml | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml index ac0a35bf8648..d5a9340ff920 100644 --- a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml @@ -23,8 +23,15 @@ properties: const: 3 compatible: - enum: - - fsl,imx7ulp-pwm + oneOf: + - enum: + - fsl,imx7ulp-pwm + - items: + - enum: + - fsl,imx93-pwm + - fsl,imx94-pwm + - fsl,imx95-pwm + - const: fsl,imx7ulp-pwm reg: maxItems: 1