mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-02 03:57:34 -04:00
Merge branches 'clk-mmp', 'clk-intel', 'clk-ingenic', 'clk-qcom' and 'clk-silabs' into clk-next
- Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs - Add support for X1830 and X1000 Ingenic SoC clk controllers - Add support for Qualcomm's MSM8939 Generic Clock Controller - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver - Enable supply regulators for GPU gdscs on Qualcomm SoCs - Add support for Si5342, Si5344 and Si5345 chips * clk-mmp: clk: mmp2: Add audio clock controller driver dt-bindings: clock: Add Marvell MMP Audio Clock Controller binding clk: mmp2: Add support for power islands dt-bindings: marvell,mmp2: Add ids for the power domains dt-bindings: clock: Make marvell,mmp2-clock a power controller clk: mmp2: Add the audio clock clk: mmp2: Add the I2S clocks clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init() clk: mmp2: Move thermal register defines up a bit dt-bindings: marvell,mmp2: Add clock id for the Audio clock dt-bindings: marvell,mmp2: Add clock id for the I2S clocks clk: mmp: frac: Allow setting bits other than the numerator/denominator clk: mmp: frac: Do not lose last 4 digits of precision * clk-intel: clk: intel: remove redundant initialization of variable rate64 clk: intel: Add CGU clock driver for a new SoC dt-bindings: clk: intel: Add bindings document & header file for CGU * clk-ingenic: clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused clk: X1000: Add FIXDIV for SSI clock of X1000. dt-bindings: clock: Add and reorder ABI for X1000. clk: Ingenic: Add CGU driver for X1830. dt-bindings: clock: Add X1830 clock bindings. clk: Ingenic: Adjust cgu code to make it compatible with X1830. clk: Ingenic: Remove unnecessary spinlock when reading registers. * clk-qcom: clk: qcom: Add missing msm8998 ufs_unipro_core_clk_src dt-bindings: clock: Add YAML schemas for QCOM A53 PLL clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller clk: qcom: gcc: Add support for Secure control source clock dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock ID clk: qcom: gcc: Add support for a new frequency for SC7180 clk: qcom: Add DT bindings for MSM8939 GCC clk: qcom: gcc: Add missing UFS clocks for SM8150 clk: qcom: gcc: Add GPU and NPU clocks for SM8150 clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdsc clk: qcom: gdsc: Handle GDSC regulator supplies clk: qcom: msm8916: Fix the address location of pll->config_reg * clk-silabs: clk: clk-si5341: Add support for the Si5345 series
This commit is contained in:
Stephen Boyd
165
include/dt-bindings/clock/intel,lgm-clk.h
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165
include/dt-bindings/clock/intel,lgm-clk.h
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@@ -0,0 +1,165 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2020 Intel Corporation.
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* Lei Chuanhua <Chuanhua.lei@intel.com>
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* Zhu Yixin <Yixin.zhu@intel.com>
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*/
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#ifndef __INTEL_LGM_CLK_H
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#define __INTEL_LGM_CLK_H
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/* PLL clocks */
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#define LGM_CLK_OSC 1
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#define LGM_CLK_PLLPP 2
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#define LGM_CLK_PLL2 3
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#define LGM_CLK_PLL0CZ 4
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#define LGM_CLK_PLL0B 5
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#define LGM_CLK_PLL1 6
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#define LGM_CLK_LJPLL3 7
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#define LGM_CLK_LJPLL4 8
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#define LGM_CLK_PLL0CM0 9
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#define LGM_CLK_PLL0CM1 10
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/* clocks from PLLs */
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/* ROPLL clocks */
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#define LGM_CLK_PP_HW 15
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#define LGM_CLK_PP_UC 16
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#define LGM_CLK_PP_FXD 17
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#define LGM_CLK_PP_TBM 18
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/* PLL2 clocks */
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#define LGM_CLK_DDR 20
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/* PLL0CZ */
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#define LGM_CLK_CM 25
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#define LGM_CLK_IC 26
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#define LGM_CLK_SDXC3 27
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/* PLL0B */
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#define LGM_CLK_NGI 30
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#define LGM_CLK_NOC4 31
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#define LGM_CLK_SW 32
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#define LGM_CLK_QSPI 33
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#define LGM_CLK_CQEM LGM_CLK_SW
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#define LGM_CLK_EMMC5 LGM_CLK_NOC4
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/* PLL1 */
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#define LGM_CLK_CT 35
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#define LGM_CLK_DSP 36
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#define LGM_CLK_VIF 37
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/* LJPLL3 */
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#define LGM_CLK_CML 40
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#define LGM_CLK_SERDES 41
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#define LGM_CLK_POOL 42
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#define LGM_CLK_PTP 43
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/* LJPLL4 */
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#define LGM_CLK_PCIE 45
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#define LGM_CLK_SATA LGM_CLK_PCIE
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/* PLL0CM0 */
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#define LGM_CLK_CPU0 50
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/* PLL0CM1 */
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#define LGM_CLK_CPU1 55
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/* Miscellaneous clocks */
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#define LGM_CLK_EMMC4 60
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#define LGM_CLK_SDXC2 61
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#define LGM_CLK_EMMC 62
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#define LGM_CLK_SDXC 63
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#define LGM_CLK_SLIC 64
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#define LGM_CLK_DCL 65
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#define LGM_CLK_DOCSIS 66
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#define LGM_CLK_PCM 67
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#define LGM_CLK_DDR_PHY 68
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#define LGM_CLK_PONDEF 69
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#define LGM_CLK_PL25M 70
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#define LGM_CLK_PL10M 71
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#define LGM_CLK_PL1544K 72
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#define LGM_CLK_PL2048K 73
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#define LGM_CLK_PL8K 74
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#define LGM_CLK_PON_NTR 75
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#define LGM_CLK_SYNC0 76
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#define LGM_CLK_SYNC1 77
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#define LGM_CLK_PROGDIV 78
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#define LGM_CLK_OD0 79
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#define LGM_CLK_OD1 80
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#define LGM_CLK_CBPHY0 81
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#define LGM_CLK_CBPHY1 82
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#define LGM_CLK_CBPHY2 83
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#define LGM_CLK_CBPHY3 84
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/* Gate clocks */
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/* Gate CLK0 */
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#define LGM_GCLK_C55 100
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#define LGM_GCLK_QSPI 101
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#define LGM_GCLK_EIP197 102
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#define LGM_GCLK_VAULT 103
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#define LGM_GCLK_TOE 104
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#define LGM_GCLK_SDXC 105
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#define LGM_GCLK_EMMC 106
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#define LGM_GCLK_SPI_DBG 107
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#define LGM_GCLK_DMA3 108
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/* Gate CLK1 */
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#define LGM_GCLK_DMA0 120
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#define LGM_GCLK_LEDC0 121
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#define LGM_GCLK_LEDC1 122
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#define LGM_GCLK_I2S0 123
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#define LGM_GCLK_I2S1 124
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#define LGM_GCLK_EBU 125
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#define LGM_GCLK_PWM 126
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#define LGM_GCLK_I2C0 127
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#define LGM_GCLK_I2C1 128
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#define LGM_GCLK_I2C2 129
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#define LGM_GCLK_I2C3 130
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#define LGM_GCLK_SSC0 131
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#define LGM_GCLK_SSC1 132
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#define LGM_GCLK_SSC2 133
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#define LGM_GCLK_SSC3 134
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#define LGM_GCLK_GPTC0 135
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#define LGM_GCLK_GPTC1 136
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#define LGM_GCLK_GPTC2 137
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#define LGM_GCLK_GPTC3 138
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#define LGM_GCLK_ASC0 139
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#define LGM_GCLK_ASC1 140
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#define LGM_GCLK_ASC2 141
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#define LGM_GCLK_ASC3 142
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#define LGM_GCLK_PCM0 143
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#define LGM_GCLK_PCM1 144
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#define LGM_GCLK_PCM2 145
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/* Gate CLK2 */
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#define LGM_GCLK_PCIE10 150
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#define LGM_GCLK_PCIE11 151
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#define LGM_GCLK_PCIE30 152
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#define LGM_GCLK_PCIE31 153
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#define LGM_GCLK_PCIE20 154
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#define LGM_GCLK_PCIE21 155
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#define LGM_GCLK_PCIE40 156
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#define LGM_GCLK_PCIE41 157
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#define LGM_GCLK_XPCS0 158
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#define LGM_GCLK_XPCS1 159
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#define LGM_GCLK_XPCS2 160
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#define LGM_GCLK_XPCS3 161
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#define LGM_GCLK_SATA0 162
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#define LGM_GCLK_SATA1 163
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#define LGM_GCLK_SATA2 164
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#define LGM_GCLK_SATA3 165
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/* Gate CLK3 */
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#define LGM_GCLK_ARCEM4 170
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#define LGM_GCLK_IDMAR1 171
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#define LGM_GCLK_IDMAT0 172
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#define LGM_GCLK_IDMAT1 173
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#define LGM_GCLK_IDMAT2 174
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#define LGM_GCLK_PPV4 175
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#define LGM_GCLK_GSWIPO 176
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#define LGM_GCLK_CQEM 177
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#define LGM_GCLK_XPCS5 178
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#define LGM_GCLK_USB1 179
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#define LGM_GCLK_USB2 180
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#endif /* __INTEL_LGM_CLK_H */
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10
include/dt-bindings/clock/marvell,mmp2-audio.h
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10
include/dt-bindings/clock/marvell,mmp2-audio.h
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@@ -0,0 +1,10 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */
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#ifndef __DT_BINDINGS_CLOCK_MARVELL_MMP2_AUDIO_H
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#define __DT_BINDINGS_CLOCK_MARVELL_MMP2_AUDIO_H
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#define MMP2_CLK_AUDIO_SYSCLK 0
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#define MMP2_CLK_AUDIO_SSPA0 1
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#define MMP2_CLK_AUDIO_SSPA1 2
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#define MMP2_CLK_AUDIO_NR_CLKS 3
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#endif
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@@ -29,6 +29,8 @@
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#define MMP3_CLK_PLL1_P 28
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#define MMP3_CLK_PLL2_P 29
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#define MMP3_CLK_PLL3 30
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#define MMP2_CLK_I2S0 31
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#define MMP2_CLK_I2S1 32
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/* apb periphrals */
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#define MMP2_CLK_TWSI0 60
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@@ -87,6 +89,7 @@
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#define MMP3_CLK_GPU_3D MMP2_CLK_GPU_3D
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#define MMP3_CLK_GPU_2D 125
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#define MMP3_CLK_SDH4 126
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#define MMP2_CLK_AUDIO 127
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#define MMP2_NR_CLKS 200
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#endif
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206
include/dt-bindings/clock/qcom,gcc-msm8939.h
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206
include/dt-bindings/clock/qcom,gcc-msm8939.h
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@@ -0,0 +1,206 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2020 Linaro Limited
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*/
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#ifndef _DT_BINDINGS_CLK_MSM_GCC_8939_H
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#define _DT_BINDINGS_CLK_MSM_GCC_8939_H
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#define GPLL0 0
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#define GPLL0_VOTE 1
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#define BIMC_PLL 2
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#define BIMC_PLL_VOTE 3
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#define GPLL1 4
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#define GPLL1_VOTE 5
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#define GPLL2 6
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#define GPLL2_VOTE 7
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#define PCNOC_BFDCD_CLK_SRC 8
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#define SYSTEM_NOC_BFDCD_CLK_SRC 9
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#define CAMSS_AHB_CLK_SRC 10
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#define APSS_AHB_CLK_SRC 11
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#define CSI0_CLK_SRC 12
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#define CSI1_CLK_SRC 13
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#define GFX3D_CLK_SRC 14
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#define VFE0_CLK_SRC 15
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23
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#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24
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#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25
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#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26
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#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27
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#define BLSP1_UART1_APPS_CLK_SRC 28
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#define BLSP1_UART2_APPS_CLK_SRC 29
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#define CCI_CLK_SRC 30
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#define CAMSS_GP0_CLK_SRC 31
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#define CAMSS_GP1_CLK_SRC 32
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#define JPEG0_CLK_SRC 33
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#define MCLK0_CLK_SRC 34
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#define MCLK1_CLK_SRC 35
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#define CSI0PHYTIMER_CLK_SRC 36
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#define CSI1PHYTIMER_CLK_SRC 37
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#define CPP_CLK_SRC 38
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#define CRYPTO_CLK_SRC 39
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#define GP1_CLK_SRC 40
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#define GP2_CLK_SRC 41
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#define GP3_CLK_SRC 42
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#define BYTE0_CLK_SRC 43
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#define ESC0_CLK_SRC 44
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#define MDP_CLK_SRC 45
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#define PCLK0_CLK_SRC 46
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#define VSYNC_CLK_SRC 47
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#define PDM2_CLK_SRC 48
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#define SDCC1_APPS_CLK_SRC 49
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#define SDCC2_APPS_CLK_SRC 50
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#define APSS_TCU_CLK_SRC 51
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#define USB_HS_SYSTEM_CLK_SRC 52
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#define VCODEC0_CLK_SRC 53
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#define GCC_BLSP1_AHB_CLK 54
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#define GCC_BLSP1_SLEEP_CLK 55
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63
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#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64
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#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65
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#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66
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#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67
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#define GCC_BLSP1_UART1_APPS_CLK 68
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#define GCC_BLSP1_UART2_APPS_CLK 69
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#define GCC_BOOT_ROM_AHB_CLK 70
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#define GCC_CAMSS_CCI_AHB_CLK 71
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#define GCC_CAMSS_CCI_CLK 72
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#define GCC_CAMSS_CSI0_AHB_CLK 73
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#define GCC_CAMSS_CSI0_CLK 74
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#define GCC_CAMSS_CSI0PHY_CLK 75
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#define GCC_CAMSS_CSI0PIX_CLK 76
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#define GCC_CAMSS_CSI0RDI_CLK 77
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#define GCC_CAMSS_CSI1_AHB_CLK 78
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#define GCC_CAMSS_CSI1_CLK 79
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#define GCC_CAMSS_CSI1PHY_CLK 80
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#define GCC_CAMSS_CSI1PIX_CLK 81
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#define GCC_CAMSS_CSI1RDI_CLK 82
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#define GCC_CAMSS_CSI_VFE0_CLK 83
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#define GCC_CAMSS_GP0_CLK 84
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#define GCC_CAMSS_GP1_CLK 85
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#define GCC_CAMSS_ISPIF_AHB_CLK 86
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#define GCC_CAMSS_JPEG0_CLK 87
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#define GCC_CAMSS_JPEG_AHB_CLK 88
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#define GCC_CAMSS_JPEG_AXI_CLK 89
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#define GCC_CAMSS_MCLK0_CLK 90
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#define GCC_CAMSS_MCLK1_CLK 91
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#define GCC_CAMSS_MICRO_AHB_CLK 92
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#define GCC_CAMSS_CSI0PHYTIMER_CLK 93
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#define GCC_CAMSS_CSI1PHYTIMER_CLK 94
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#define GCC_CAMSS_AHB_CLK 95
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#define GCC_CAMSS_TOP_AHB_CLK 96
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#define GCC_CAMSS_CPP_AHB_CLK 97
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#define GCC_CAMSS_CPP_CLK 98
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#define GCC_CAMSS_VFE0_CLK 99
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#define GCC_CAMSS_VFE_AHB_CLK 100
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#define GCC_CAMSS_VFE_AXI_CLK 101
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#define GCC_CRYPTO_AHB_CLK 102
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#define GCC_CRYPTO_AXI_CLK 103
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#define GCC_CRYPTO_CLK 104
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#define GCC_OXILI_GMEM_CLK 105
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#define GCC_GP1_CLK 106
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#define GCC_GP2_CLK 107
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#define GCC_GP3_CLK 108
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#define GCC_MDSS_AHB_CLK 109
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||||
#define GCC_MDSS_AXI_CLK 110
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#define GCC_MDSS_BYTE0_CLK 111
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#define GCC_MDSS_ESC0_CLK 112
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#define GCC_MDSS_MDP_CLK 113
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#define GCC_MDSS_PCLK0_CLK 114
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#define GCC_MDSS_VSYNC_CLK 115
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#define GCC_MSS_CFG_AHB_CLK 116
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#define GCC_OXILI_AHB_CLK 117
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#define GCC_OXILI_GFX3D_CLK 118
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#define GCC_PDM2_CLK 119
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#define GCC_PDM_AHB_CLK 120
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#define GCC_PRNG_AHB_CLK 121
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#define GCC_SDCC1_AHB_CLK 122
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#define GCC_SDCC1_APPS_CLK 123
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#define GCC_SDCC2_AHB_CLK 124
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||||
#define GCC_SDCC2_APPS_CLK 125
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||||
#define GCC_GTCU_AHB_CLK 126
|
||||
#define GCC_JPEG_TBU_CLK 127
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||||
#define GCC_MDP_TBU_CLK 128
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||||
#define GCC_SMMU_CFG_CLK 129
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#define GCC_VENUS_TBU_CLK 130
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||||
#define GCC_VFE_TBU_CLK 131
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||||
#define GCC_USB2A_PHY_SLEEP_CLK 132
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||||
#define GCC_USB_HS_AHB_CLK 133
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||||
#define GCC_USB_HS_SYSTEM_CLK 134
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||||
#define GCC_VENUS0_AHB_CLK 135
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||||
#define GCC_VENUS0_AXI_CLK 136
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||||
#define GCC_VENUS0_VCODEC0_CLK 137
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||||
#define BIMC_DDR_CLK_SRC 138
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||||
#define GCC_APSS_TCU_CLK 139
|
||||
#define GCC_GFX_TCU_CLK 140
|
||||
#define BIMC_GPU_CLK_SRC 141
|
||||
#define GCC_BIMC_GFX_CLK 142
|
||||
#define GCC_BIMC_GPU_CLK 143
|
||||
#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144
|
||||
#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145
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||||
#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146
|
||||
#define ULTAUDIO_XO_CLK_SRC 147
|
||||
#define ULTAUDIO_AHBFABRIC_CLK_SRC 148
|
||||
#define CODEC_DIGCODEC_CLK_SRC 149
|
||||
#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150
|
||||
#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151
|
||||
#define GCC_ULTAUDIO_AVSYNC_XO_CLK 152
|
||||
#define GCC_ULTAUDIO_STC_XO_CLK 153
|
||||
#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154
|
||||
#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155
|
||||
#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156
|
||||
#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157
|
||||
#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158
|
||||
#define GCC_CODEC_DIGCODEC_CLK 159
|
||||
#define GCC_MSS_Q6_BIMC_AXI_CLK 160
|
||||
#define GPLL3 161
|
||||
#define GPLL3_VOTE 162
|
||||
#define GPLL4 163
|
||||
#define GPLL4_VOTE 164
|
||||
#define GPLL5 165
|
||||
#define GPLL5_VOTE 166
|
||||
#define GPLL6 167
|
||||
#define GPLL6_VOTE 168
|
||||
#define BYTE1_CLK_SRC 169
|
||||
#define GCC_MDSS_BYTE1_CLK 170
|
||||
#define ESC1_CLK_SRC 171
|
||||
#define GCC_MDSS_ESC1_CLK 172
|
||||
#define PCLK1_CLK_SRC 173
|
||||
#define GCC_MDSS_PCLK1_CLK 174
|
||||
#define GCC_GFX_TBU_CLK 175
|
||||
#define GCC_CPP_TBU_CLK 176
|
||||
#define GCC_MDP_RT_TBU_CLK 177
|
||||
#define USB_FS_SYSTEM_CLK_SRC 178
|
||||
#define USB_FS_IC_CLK_SRC 179
|
||||
#define GCC_USB_FS_AHB_CLK 180
|
||||
#define GCC_USB_FS_IC_CLK 181
|
||||
#define GCC_USB_FS_SYSTEM_CLK 182
|
||||
#define GCC_VENUS0_CORE0_VCODEC0_CLK 183
|
||||
#define GCC_VENUS0_CORE1_VCODEC0_CLK 184
|
||||
#define GCC_OXILI_TIMER_CLK 185
|
||||
|
||||
/* Indexes for GDSCs */
|
||||
#define BIMC_GDSC 0
|
||||
#define VENUS_GDSC 1
|
||||
#define MDSS_GDSC 2
|
||||
#define JPEG_GDSC 3
|
||||
#define VFE_GDSC 4
|
||||
#define OXILI_GDSC 5
|
||||
#define VENUS_CORE0_GDSC 6
|
||||
#define VENUS_CORE1_GDSC 7
|
||||
|
||||
#endif
|
||||
@@ -183,6 +183,7 @@
|
||||
#define GCC_MSS_SNOC_AXI_CLK 174
|
||||
#define GCC_MSS_MNOC_BIMC_AXI_CLK 175
|
||||
#define GCC_BIMC_GFX_CLK 176
|
||||
#define UFS_UNIPRO_CORE_CLK_SRC 177
|
||||
|
||||
#define PCIE_0_GDSC 0
|
||||
#define UFS_GDSC 1
|
||||
|
||||
@@ -137,6 +137,7 @@
|
||||
#define GCC_MSS_NAV_AXI_CLK 127
|
||||
#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128
|
||||
#define GCC_MSS_SNOC_AXI_CLK 129
|
||||
#define GCC_SEC_CTRL_CLK_SRC 130
|
||||
|
||||
/* GCC resets */
|
||||
#define GCC_QUSB2PHY_PRIM_BCR 0
|
||||
|
||||
@@ -12,33 +12,41 @@
|
||||
#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
|
||||
#define __DT_BINDINGS_CLOCK_X1000_CGU_H__
|
||||
|
||||
#define X1000_CLK_EXCLK 0
|
||||
#define X1000_CLK_RTCLK 1
|
||||
#define X1000_CLK_APLL 2
|
||||
#define X1000_CLK_MPLL 3
|
||||
#define X1000_CLK_SCLKA 4
|
||||
#define X1000_CLK_CPUMUX 5
|
||||
#define X1000_CLK_CPU 6
|
||||
#define X1000_CLK_L2CACHE 7
|
||||
#define X1000_CLK_AHB0 8
|
||||
#define X1000_CLK_AHB2PMUX 9
|
||||
#define X1000_CLK_AHB2 10
|
||||
#define X1000_CLK_PCLK 11
|
||||
#define X1000_CLK_DDR 12
|
||||
#define X1000_CLK_MAC 13
|
||||
#define X1000_CLK_MSCMUX 14
|
||||
#define X1000_CLK_MSC0 15
|
||||
#define X1000_CLK_MSC1 16
|
||||
#define X1000_CLK_SSIPLL 17
|
||||
#define X1000_CLK_SSIMUX 18
|
||||
#define X1000_CLK_SFC 19
|
||||
#define X1000_CLK_I2C0 20
|
||||
#define X1000_CLK_I2C1 21
|
||||
#define X1000_CLK_I2C2 22
|
||||
#define X1000_CLK_UART0 23
|
||||
#define X1000_CLK_UART1 24
|
||||
#define X1000_CLK_UART2 25
|
||||
#define X1000_CLK_SSI 26
|
||||
#define X1000_CLK_PDMA 27
|
||||
#define X1000_CLK_EXCLK 0
|
||||
#define X1000_CLK_RTCLK 1
|
||||
#define X1000_CLK_APLL 2
|
||||
#define X1000_CLK_MPLL 3
|
||||
#define X1000_CLK_OTGPHY 4
|
||||
#define X1000_CLK_SCLKA 5
|
||||
#define X1000_CLK_CPUMUX 6
|
||||
#define X1000_CLK_CPU 7
|
||||
#define X1000_CLK_L2CACHE 8
|
||||
#define X1000_CLK_AHB0 9
|
||||
#define X1000_CLK_AHB2PMUX 10
|
||||
#define X1000_CLK_AHB2 11
|
||||
#define X1000_CLK_PCLK 12
|
||||
#define X1000_CLK_DDR 13
|
||||
#define X1000_CLK_MAC 14
|
||||
#define X1000_CLK_LCD 15
|
||||
#define X1000_CLK_MSCMUX 16
|
||||
#define X1000_CLK_MSC0 17
|
||||
#define X1000_CLK_MSC1 18
|
||||
#define X1000_CLK_OTG 19
|
||||
#define X1000_CLK_SSIPLL 20
|
||||
#define X1000_CLK_SSIPLL_DIV2 21
|
||||
#define X1000_CLK_SSIMUX 22
|
||||
#define X1000_CLK_EMC 23
|
||||
#define X1000_CLK_EFUSE 24
|
||||
#define X1000_CLK_SFC 25
|
||||
#define X1000_CLK_I2C0 26
|
||||
#define X1000_CLK_I2C1 27
|
||||
#define X1000_CLK_I2C2 28
|
||||
#define X1000_CLK_UART0 29
|
||||
#define X1000_CLK_UART1 30
|
||||
#define X1000_CLK_UART2 31
|
||||
#define X1000_CLK_TCU 32
|
||||
#define X1000_CLK_SSI 33
|
||||
#define X1000_CLK_OST 34
|
||||
#define X1000_CLK_PDMA 35
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
|
||||
|
||||
55
include/dt-bindings/clock/x1830-cgu.h
Normal file
55
include/dt-bindings/clock/x1830-cgu.h
Normal file
@@ -0,0 +1,55 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* This header provides clock numbers for the ingenic,x1830-cgu DT binding.
|
||||
*
|
||||
* They are roughly ordered as:
|
||||
* - external clocks
|
||||
* - PLLs
|
||||
* - muxes/dividers in the order they appear in the x1830 programmers manual
|
||||
* - gates in order of their bit in the CLKGR* registers
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__
|
||||
#define __DT_BINDINGS_CLOCK_X1830_CGU_H__
|
||||
|
||||
#define X1830_CLK_EXCLK 0
|
||||
#define X1830_CLK_RTCLK 1
|
||||
#define X1830_CLK_APLL 2
|
||||
#define X1830_CLK_MPLL 3
|
||||
#define X1830_CLK_EPLL 4
|
||||
#define X1830_CLK_VPLL 5
|
||||
#define X1830_CLK_OTGPHY 6
|
||||
#define X1830_CLK_SCLKA 7
|
||||
#define X1830_CLK_CPUMUX 8
|
||||
#define X1830_CLK_CPU 9
|
||||
#define X1830_CLK_L2CACHE 10
|
||||
#define X1830_CLK_AHB0 11
|
||||
#define X1830_CLK_AHB2PMUX 12
|
||||
#define X1830_CLK_AHB2 13
|
||||
#define X1830_CLK_PCLK 14
|
||||
#define X1830_CLK_DDR 15
|
||||
#define X1830_CLK_MAC 16
|
||||
#define X1830_CLK_LCD 17
|
||||
#define X1830_CLK_MSCMUX 18
|
||||
#define X1830_CLK_MSC0 19
|
||||
#define X1830_CLK_MSC1 20
|
||||
#define X1830_CLK_SSIPLL 21
|
||||
#define X1830_CLK_SSIPLL_DIV2 22
|
||||
#define X1830_CLK_SSIMUX 23
|
||||
#define X1830_CLK_EMC 24
|
||||
#define X1830_CLK_EFUSE 25
|
||||
#define X1830_CLK_OTG 26
|
||||
#define X1830_CLK_SSI0 27
|
||||
#define X1830_CLK_SMB0 28
|
||||
#define X1830_CLK_SMB1 29
|
||||
#define X1830_CLK_SMB2 30
|
||||
#define X1830_CLK_UART0 31
|
||||
#define X1830_CLK_UART1 32
|
||||
#define X1830_CLK_SSI1 33
|
||||
#define X1830_CLK_SFC 34
|
||||
#define X1830_CLK_PDMA 35
|
||||
#define X1830_CLK_TCU 36
|
||||
#define X1830_CLK_DTRNG 37
|
||||
#define X1830_CLK_OST 38
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */
|
||||
11
include/dt-bindings/power/marvell,mmp2.h
Normal file
11
include/dt-bindings/power/marvell,mmp2.h
Normal file
@@ -0,0 +1,11 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __DTS_MARVELL_MMP2_POWER_H
|
||||
#define __DTS_MARVELL_MMP2_POWER_H
|
||||
|
||||
#define MMP2_POWER_DOMAIN_GPU 0
|
||||
#define MMP2_POWER_DOMAIN_AUDIO 1
|
||||
#define MMP3_POWER_DOMAIN_CAMERA 2
|
||||
|
||||
#define MMP2_NR_POWER_DOMAINS 3
|
||||
|
||||
#endif
|
||||
110
include/dt-bindings/reset/qcom,gcc-msm8939.h
Normal file
110
include/dt-bindings/reset/qcom,gcc-msm8939.h
Normal file
@@ -0,0 +1,110 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright 2020 Linaro Limited
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_MSM_GCC_8939_H
|
||||
#define _DT_BINDINGS_RESET_MSM_GCC_8939_H
|
||||
|
||||
#define GCC_BLSP1_BCR 0
|
||||
#define GCC_BLSP1_QUP1_BCR 1
|
||||
#define GCC_BLSP1_UART1_BCR 2
|
||||
#define GCC_BLSP1_QUP2_BCR 3
|
||||
#define GCC_BLSP1_UART2_BCR 4
|
||||
#define GCC_BLSP1_QUP3_BCR 5
|
||||
#define GCC_BLSP1_QUP4_BCR 6
|
||||
#define GCC_BLSP1_QUP5_BCR 7
|
||||
#define GCC_BLSP1_QUP6_BCR 8
|
||||
#define GCC_IMEM_BCR 9
|
||||
#define GCC_SMMU_BCR 10
|
||||
#define GCC_APSS_TCU_BCR 11
|
||||
#define GCC_SMMU_XPU_BCR 12
|
||||
#define GCC_PCNOC_TBU_BCR 13
|
||||
#define GCC_PRNG_BCR 14
|
||||
#define GCC_BOOT_ROM_BCR 15
|
||||
#define GCC_CRYPTO_BCR 16
|
||||
#define GCC_SEC_CTRL_BCR 17
|
||||
#define GCC_AUDIO_CORE_BCR 18
|
||||
#define GCC_ULT_AUDIO_BCR 19
|
||||
#define GCC_DEHR_BCR 20
|
||||
#define GCC_SYSTEM_NOC_BCR 21
|
||||
#define GCC_PCNOC_BCR 22
|
||||
#define GCC_TCSR_BCR 23
|
||||
#define GCC_QDSS_BCR 24
|
||||
#define GCC_DCD_BCR 25
|
||||
#define GCC_MSG_RAM_BCR 26
|
||||
#define GCC_MPM_BCR 27
|
||||
#define GCC_SPMI_BCR 28
|
||||
#define GCC_SPDM_BCR 29
|
||||
#define GCC_MM_SPDM_BCR 30
|
||||
#define GCC_BIMC_BCR 31
|
||||
#define GCC_RBCPR_BCR 32
|
||||
#define GCC_TLMM_BCR 33
|
||||
#define GCC_USB_HS_BCR 34
|
||||
#define GCC_USB2A_PHY_BCR 35
|
||||
#define GCC_SDCC1_BCR 36
|
||||
#define GCC_SDCC2_BCR 37
|
||||
#define GCC_PDM_BCR 38
|
||||
#define GCC_SNOC_BUS_TIMEOUT0_BCR 39
|
||||
#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40
|
||||
#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41
|
||||
#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42
|
||||
#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43
|
||||
#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44
|
||||
#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45
|
||||
#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46
|
||||
#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47
|
||||
#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48
|
||||
#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49
|
||||
#define GCC_MMSS_BCR 50
|
||||
#define GCC_VENUS0_BCR 51
|
||||
#define GCC_MDSS_BCR 52
|
||||
#define GCC_CAMSS_PHY0_BCR 53
|
||||
#define GCC_CAMSS_CSI0_BCR 54
|
||||
#define GCC_CAMSS_CSI0PHY_BCR 55
|
||||
#define GCC_CAMSS_CSI0RDI_BCR 56
|
||||
#define GCC_CAMSS_CSI0PIX_BCR 57
|
||||
#define GCC_CAMSS_PHY1_BCR 58
|
||||
#define GCC_CAMSS_CSI1_BCR 59
|
||||
#define GCC_CAMSS_CSI1PHY_BCR 60
|
||||
#define GCC_CAMSS_CSI1RDI_BCR 61
|
||||
#define GCC_CAMSS_CSI1PIX_BCR 62
|
||||
#define GCC_CAMSS_ISPIF_BCR 63
|
||||
#define GCC_CAMSS_CCI_BCR 64
|
||||
#define GCC_CAMSS_MCLK0_BCR 65
|
||||
#define GCC_CAMSS_MCLK1_BCR 66
|
||||
#define GCC_CAMSS_GP0_BCR 67
|
||||
#define GCC_CAMSS_GP1_BCR 68
|
||||
#define GCC_CAMSS_TOP_BCR 69
|
||||
#define GCC_CAMSS_MICRO_BCR 70
|
||||
#define GCC_CAMSS_JPEG_BCR 71
|
||||
#define GCC_CAMSS_VFE_BCR 72
|
||||
#define GCC_CAMSS_CSI_VFE0_BCR 73
|
||||
#define GCC_OXILI_BCR 74
|
||||
#define GCC_GMEM_BCR 75
|
||||
#define GCC_CAMSS_AHB_BCR 76
|
||||
#define GCC_MDP_TBU_BCR 77
|
||||
#define GCC_GFX_TBU_BCR 78
|
||||
#define GCC_GFX_TCU_BCR 79
|
||||
#define GCC_MSS_TBU_AXI_BCR 80
|
||||
#define GCC_MSS_TBU_GSS_AXI_BCR 81
|
||||
#define GCC_MSS_TBU_Q6_AXI_BCR 82
|
||||
#define GCC_GTCU_AHB_BCR 83
|
||||
#define GCC_SMMU_CFG_BCR 84
|
||||
#define GCC_VFE_TBU_BCR 85
|
||||
#define GCC_VENUS_TBU_BCR 86
|
||||
#define GCC_JPEG_TBU_BCR 87
|
||||
#define GCC_PRONTO_TBU_BCR 88
|
||||
#define GCC_SMMU_CATS_BCR 89
|
||||
#define GCC_BLSP1_UART3_BCR 90
|
||||
#define GCC_CAMSS_CSI2_BCR 91
|
||||
#define GCC_CAMSS_CSI2PHY_BCR 92
|
||||
#define GCC_CAMSS_CSI2RDI_BCR 93
|
||||
#define GCC_CAMSS_CSI2PIX_BCR 94
|
||||
#define GCC_USB_FS_BCR 95
|
||||
#define GCC_BLSP1_QUP4_SPI_APPS_CBCR 96
|
||||
#define GCC_CAMSS_MCLK2_BCR 97
|
||||
#define GCC_CPP_TBU_BCR 98
|
||||
#define GCC_MDP_RT_TBU_BCR 99
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user