From 4604c989004006cc0c08a9cfe8d80e7544b8e808 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 9 Dec 2024 12:29:20 +0100 Subject: [PATCH 01/71] arm64: dts: mediatek: mt8183-kukui: align thermal node names with bindings Bindings expect thermal zones node name to follow certain pattern. This fixes dtbs_check warning: mt8183-kukui-jacuzzi-burnet.dtb: thermal-zones: 'tboard1', 'tboard2' do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,10}-thermal$', 'pinctrl-[0-9]+' Reviewed-by: Chen-Yu Tsai Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20241209112920.70060-1-krzysztof.kozlowski@linaro.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 4b974bb781b1..2828f34949ae 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -944,13 +944,13 @@ &ssusb { }; &thermal_zones { - tboard1 { + tboard1-thermal { polling-delay = <1000>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&tboard_thermistor1>; }; - tboard2 { + tboard2-thermal { polling-delay = <1000>; /* milliseconds */ polling-delay-passive = <0>; /* milliseconds */ thermal-sensors = <&tboard_thermistor2>; From 253b4e96f5783fddede1b82274a7b4e0aa57d761 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Wed, 6 Nov 2024 16:01:45 -0500 Subject: [PATCH 02/71] arm64: dts: mediatek: mt8186: Move wakeup to MTU3 to get working suspend MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The current DT has the wakeup-source and mediatek,syscon-wakeup properties in the XHCI nodes, which configures USB wakeup after powering down the XHCI hardware block. However, since the XHCI controller is behind an MTU3 (USB3 DRD controller), the MTU3 only gets powered down after USB wakeup has been configured, causing the system to detect a wakeup, and results in broken suspend support as the system resumes immediately. Move the wakeup properties to the MTU3 nodes so that USB wakeup is only enabled after the MTU3 has powered down. With this change in place, it is possible to suspend and resume, and also to wakeup through USB, as tested on the Google Steelix (Lenovo 300e Yoga Chromebook Gen 4). Fixes: f6c3e61c5486 ("arm64: dts: mediatek: mt8186: Add MTU3 nodes") Reported-by: Wojciech Macek Suggested-by: AngeloGioacchino Del Regno Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241106-mt8186-suspend-with-usb-wakeup-v1-1-07734a4c8236@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index d3c3c2a40adc..b91f88ffae0e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1577,6 +1577,8 @@ ssusb0: usb@11201000 { #address-cells = <2>; #size-cells = <2>; ranges; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x420 2>; status = "disabled"; usb_host0: usb@11200000 { @@ -1590,8 +1592,6 @@ usb_host0: usb@11200000 { <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; interrupts = ; - mediatek,syscon-wakeup = <&pericfg 0x420 2>; - wakeup-source; status = "disabled"; }; }; @@ -1643,6 +1643,8 @@ ssusb1: usb@11281000 { #address-cells = <2>; #size-cells = <2>; ranges; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x424 2>; status = "disabled"; usb_host1: usb@11280000 { @@ -1656,8 +1658,6 @@ usb_host1: usb@11280000 { <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; interrupts = ; - mediatek,syscon-wakeup = <&pericfg 0x424 2>; - wakeup-source; status = "disabled"; }; }; From 6c379e8b984815fc8f876e4bc78c4d563f13ddae Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Wed, 13 Nov 2024 16:16:53 +0800 Subject: [PATCH 03/71] arm64: dts: mt8183: set DMIC one-wire mode on Damu Sets DMIC one-wire mode on Damu. Fixes: cabc71b08eb5 ("arm64: dts: mt8183: Add kukui-jacuzzi-damu board") Signed-off-by: Hsin-Yi Wang Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsin-Te Yuan Reviewed-by: Matthias Brugger Link: https://lore.kernel.org/r/20241113-damu-v4-1-6911b69610dd@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts index 65860b33c01f..3935d83a047e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts @@ -26,6 +26,10 @@ &touchscreen { hid-descr-addr = <0x0001>; }; +&mt6358codec { + mediatek,dmic-mode = <1>; /* one-wire */ +}; + &qca_wifi { qcom,ath10k-calibration-variant = "GO_DAMU"; }; From 3a11be8938aa7294719c0cf2a4758ed0cf88ab84 Mon Sep 17 00:00:00 2001 From: Fei Shao Date: Sun, 24 Nov 2024 16:52:37 +0800 Subject: [PATCH 04/71] dt-bindings: arm: mediatek: Add MT8188 Lenovo Chromebook Duet (11", 9) Add entries for the MT8188-based Chromebook "Ciri", also known as Lenovo Chromebook Duet (11", 9). This device features a detachable design with touchscreen, detachable keyboard and USI 2.0 Stylus support, and has 8 SKUs to accommodate the combinations of second-source components. Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Fei Shao Link: https://lore.kernel.org/r/20241124085739.290556-2-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 1d4bb50fcd8d..4b68f0baf010 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -307,6 +307,19 @@ properties: - enum: - mediatek,mt8186-evb - const: mediatek,mt8186 + - description: Google Ciri (Lenovo Chromebook Duet (11", 9)) + items: + - enum: + - google,ciri-sku0 + - google,ciri-sku1 + - google,ciri-sku2 + - google,ciri-sku3 + - google,ciri-sku4 + - google,ciri-sku5 + - google,ciri-sku6 + - google,ciri-sku7 + - const: google,ciri + - const: mediatek,mt8188 - items: - enum: - mediatek,mt8188-evb From 5e6af7f5418950d77eb2193ddfb8557458a070b0 Mon Sep 17 00:00:00 2001 From: Fei Shao Date: Sun, 24 Nov 2024 16:52:38 +0800 Subject: [PATCH 05/71] arm64: dts: mediatek: Introduce MT8188 Geralt platform based Ciri Introduce MT8188-based Chromebook Ciri, also known commercially as Lenovo Chromebook Duet (11", 9). Ciri is a detachable device based on the Geralt design, where Geralt is the codename for the MT8188 platform. Ciri offers 8 SKUs to accommodate different combinations of second-source components, including: - audio codecs (RT5682S and ES8326) - speaker amps (TAS2563 and MAX98390) - MIPI-DSI panels (BOE nv110wum-l60 and IVO t109nw41) Signed-off-by: Fei Shao Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241124085739.290556-3-fshao@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 8 + .../dts/mediatek/mt8188-geralt-ciri-sku0.dts | 32 + .../dts/mediatek/mt8188-geralt-ciri-sku1.dts | 59 + .../dts/mediatek/mt8188-geralt-ciri-sku2.dts | 59 + .../dts/mediatek/mt8188-geralt-ciri-sku3.dts | 32 + .../dts/mediatek/mt8188-geralt-ciri-sku4.dts | 48 + .../dts/mediatek/mt8188-geralt-ciri-sku5.dts | 72 + .../dts/mediatek/mt8188-geralt-ciri-sku6.dts | 72 + .../dts/mediatek/mt8188-geralt-ciri-sku7.dts | 48 + .../boot/dts/mediatek/mt8188-geralt-ciri.dtsi | 316 +++++ .../boot/dts/mediatek/mt8188-geralt.dtsi | 1156 +++++++++++++++++ 11 files changed, 1902 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku0.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku1.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku2.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku3.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku4.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku5.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku6.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku7.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 8fd7b2bb7a15..c6c34d99316b 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -69,6 +69,14 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589824.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589825.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku0.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku2.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku3.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r5-sku2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku0.dts new file mode 100644 index 000000000000..79d6d12394b9 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku0.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model = "Google Ciri sku0 board"; + compatible = "google,ciri-sku0", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible = "boe,nv110wum-l60", "himax,hx83102"; +}; + +&sound { + compatible = "mediatek,mt8188-rt5682s"; + model = "mt8188_m98390_5682"; + + audio-routing = + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "IN1P", "Headset Mic", + "Left Spk", "Front Left BE_OUT", + "Right Spk", "Front Right BE_OUT"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku1.dts new file mode 100644 index 000000000000..ef5ea9d12b1d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku1.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model = "Google Ciri sku1 board"; + compatible = "google,ciri-sku1", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible = "ivo,t109nw41", "himax,hx83102"; +}; + +&i2c0 { + /delete-node/ audio-codec@1a; + + es8326: audio-codec@19 { + compatible = "everest,es8326"; + reg = <0x19>; + interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&audio_codec_pins>; + #sound-dai-cells = <0>; + everest,jack-pol = [0e]; + everest,interrupt-clk = [00]; + }; +}; + +&sound { + compatible = "mediatek,mt8188-es8326"; + model = "mt8188_m98390_8326"; + + audio-routing = + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "MIC1", "Headset Mic", + "Left Spk", "Front Left BE_OUT", + "Right Spk", "Front Right BE_OUT"; + + dai-link-2 { + codec { + sound-dai = <&es8326>; + }; + }; + + dai-link-3 { + codec { + sound-dai = <&es8326>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku2.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku2.dts new file mode 100644 index 000000000000..ef56786fc2be --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku2.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model = "Google Ciri sku2 board"; + compatible = "google,ciri-sku2", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible = "boe,nv110wum-l60", "himax,hx83102"; +}; + +&i2c0 { + /delete-node/ audio-codec@1a; + + es8326: audio-codec@19 { + compatible = "everest,es8326"; + reg = <0x19>; + interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&audio_codec_pins>; + #sound-dai-cells = <0>; + everest,jack-pol = [0e]; + everest,interrupt-clk = [00]; + }; +}; + +&sound { + compatible = "mediatek,mt8188-es8326"; + model = "mt8188_m98390_8326"; + + audio-routing = + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "MIC1", "Headset Mic", + "Left Spk", "Front Left BE_OUT", + "Right Spk", "Front Right BE_OUT"; + + dai-link-2 { + codec { + sound-dai = <&es8326>; + }; + }; + + dai-link-3 { + codec { + sound-dai = <&es8326>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku3.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku3.dts new file mode 100644 index 000000000000..524f7f0064c1 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku3.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model = "Google Ciri sku3 board"; + compatible = "google,ciri-sku3", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible = "ivo,t109nw41", "himax,hx83102"; +}; + +&sound { + compatible = "mediatek,mt8188-rt5682s"; + model = "mt8188_m98390_5682"; + + audio-routing = + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "IN1P", "Headset Mic", + "Left Spk", "Front Left BE_OUT", + "Right Spk", "Front Right BE_OUT"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku4.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku4.dts new file mode 100644 index 000000000000..ea953d7e1543 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku4.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model = "Google Ciri sku4 board (rev4)"; + compatible = "google,ciri-sku4", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible = "boe,nv110wum-l60", "himax,hx83102"; +}; + +&i2c0 { + /delete-node/ amplifier@38; + /delete-node/ amplifier@39; + + tas2563: amplifier@4f { + compatible = "ti,tas2563", "ti,tas2781"; + reg = <0x4f>, <0x4c>; /* left / right channel */ + reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; +}; + +&sound { + compatible = "mediatek,mt8188-rt5682s"; + model = "mt8188_tas2563_5682"; + + audio-routing = + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "IN1P", "Headset Mic"; + + dai-link-1 { + codec { + sound-dai = <&tas2563>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku5.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku5.dts new file mode 100644 index 000000000000..bf87201ccf27 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku5.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model = "Google Ciri sku5 board (rev4)"; + compatible = "google,ciri-sku5", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible = "ivo,t109nw41", "himax,hx83102"; +}; + +&i2c0 { + /delete-node/ audio-codec@1a; + /delete-node/ amplifier@38; + /delete-node/ amplifier@39; + + es8326: audio-codec@19 { + compatible = "everest,es8326"; + reg = <0x19>; + interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&audio_codec_pins>; + #sound-dai-cells = <0>; + everest,jack-pol = [0e]; + everest,interrupt-clk = [00]; + }; + + tas2563: amplifier@4f { + compatible = "ti,tas2563", "ti,tas2781"; + reg = <0x4f>, <0x4c>; /* left / right channel */ + reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; +}; + +&sound { + compatible = "mediatek,mt8188-es8326"; + model = "mt8188_tas2563_8326"; + + audio-routing = + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "MIC1", "Headset Mic"; + + dai-link-1 { + codec { + sound-dai = <&tas2563>; + }; + }; + + dai-link-2 { + codec { + sound-dai = <&es8326>; + }; + }; + + dai-link-3 { + codec { + sound-dai = <&es8326>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku6.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku6.dts new file mode 100644 index 000000000000..17d7359dfb6a --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku6.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model = "Google Ciri sku6 board (rev4)"; + compatible = "google,ciri-sku6", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible = "boe,nv110wum-l60", "himax,hx83102"; +}; + +&i2c0 { + /delete-node/ audio-codec@1a; + /delete-node/ amplifier@38; + /delete-node/ amplifier@39; + + es8326: audio-codec@19 { + compatible = "everest,es8326"; + reg = <0x19>; + interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&audio_codec_pins>; + #sound-dai-cells = <0>; + everest,jack-pol = [0e]; + everest,interrupt-clk = [00]; + }; + + tas2563: amplifier@4f { + compatible = "ti,tas2563", "ti,tas2781"; + reg = <0x4f>, <0x4c>; /* left / right channel */ + reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; +}; + +&sound { + compatible = "mediatek,mt8188-es8326"; + model = "mt8188_tas2563_8326"; + + audio-routing = + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "MIC1", "Headset Mic"; + + dai-link-1 { + codec { + sound-dai = <&tas2563>; + }; + }; + + dai-link-2 { + codec { + sound-dai = <&es8326>; + }; + }; + + dai-link-3 { + codec { + sound-dai = <&es8326>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku7.dts b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku7.dts new file mode 100644 index 000000000000..825015b452d5 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku7.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt-ciri.dtsi" + +/ { + model = "Google Ciri sku7 board (rev4)"; + compatible = "google,ciri-sku7", "google,ciri", "mediatek,mt8188"; +}; + +&dsi_panel { + compatible = "ivo,t109nw41", "himax,hx83102"; +}; + +&i2c0 { + /delete-node/ amplifier@38; + /delete-node/ amplifier@39; + + tas2563: amplifier@4f { + compatible = "ti,tas2563", "ti,tas2781"; + reg = <0x4f>, <0x4c>; /* left / right channel */ + reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; +}; + +&sound { + compatible = "mediatek,mt8188-rt5682s"; + model = "mt8188_tas2563_5682"; + + audio-routing = + "ETDM1_OUT", "ETDM_SPK_PIN", + "ETDM2_OUT", "ETDM_HP_PIN", + "ETDM1_IN", "ETDM_SPK_PIN", + "ETDM2_IN", "ETDM_HP_PIN", + "ADDA Capture", "MTKAIF_PIN", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "IN1P", "Headset Mic"; + + dai-link-1 { + codec { + sound-dai = <&tas2563>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri.dtsi new file mode 100644 index 000000000000..6815c435a57e --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri.dtsi @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 Google LLC + */ +/dts-v1/; +#include "mt8188-geralt.dtsi" + +&aud_etdm_hp_on { + pins-mclk { + pinmux = ; + }; +}; + +&aud_etdm_hp_off { + pins-mclk { + pinmux = ; + bias-pull-down; + input-enable; + }; +}; + +&i2c0 { + rt5682s: audio-codec@1a { + compatible = "realtek,rt5682s"; + reg = <0x1a>; + interrupts-extended = <&pio 108 IRQ_TYPE_EDGE_BOTH>; + pinctrl-names = "default"; + pinctrl-0 = <&audio_codec_pins>; + #sound-dai-cells = <1>; + + AVDD-supply = <&mt6359_vio18_ldo_reg>; + DBVDD-supply = <&mt6359_vio18_ldo_reg>; + LDO1-IN-supply = <&mt6359_vio18_ldo_reg>; + MICVDD-supply = <&pp3300_s3>; + realtek,jd-src = <1>; + }; + + max98390_38: amplifier@38 { + compatible = "maxim,max98390"; + reg = <0x38>; + sound-name-prefix = "Front Right"; + reset-gpios = <&pio 118 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&speaker_en>; + #sound-dai-cells = <0>; + }; + + max98390_39: amplifier@39 { + compatible = "maxim,max98390"; + reg = <0x39>; + sound-name-prefix = "Front Left"; + #sound-dai-cells = <0>; + }; +}; + +&i2c_tunnel { + /* + * The virtual battery I2C addr is 0xf on Ciri, so we describe it + * manually instead of including 'arm/cros-ec-sbs.dtsi'. + **/ + battery: sbs-battery@f { + compatible = "sbs,sbs-battery"; + reg = <0xf>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <1>; + }; +}; + +&mipi_tx_config0 { + drive-strength-microamp = <5200>; +}; + +&mt6359_vm18_ldo_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-microvolt-offset = <100000>; +}; + +&sound { + dai-link-0 { + link-name = "ETDM1_IN_BE"; + dai-format = "i2s"; + mediatek,clk-provider = "cpu"; + }; + + dai-link-1 { + link-name = "ETDM1_OUT_BE"; + dai-format = "i2s"; + mediatek,clk-provider = "cpu"; + + codec { + sound-dai = <&max98390_38>, + <&max98390_39>; + }; + }; + + dai-link-2 { + link-name = "ETDM2_IN_BE"; + mediatek,clk-provider = "cpu"; + + codec { + sound-dai = <&rt5682s 0>; + }; + }; + + dai-link-3 { + link-name = "ETDM2_OUT_BE"; + mediatek,clk-provider = "cpu"; + + codec { + sound-dai = <&rt5682s 0>; + }; + }; + + dai-link-4 { + link-name = "DPTX_BE"; + + codec { + sound-dai = <&dp_tx>; + }; + }; +}; + +&pio { + gpio-line-names = + "GSC_AP_INT_ODL", + "AP_DISP_BKLTEN", + "", + "EN_PPVAR_MIPI_DISP", + "EN_PPVAR_MIPI_DISP_150MA", + "TCHSCR_RST_1V8_L", + "", + "", + "", + "", + "", + "I2S_SPKR_DATAOUT", + "EN_PP3300_WLAN_X", + "WIFI_KILL_1V8_L", + "BT_KILL_1V8_L", + "AP_FLASH_WP_L", /* ... is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */ + "", + "", + "WCAM_PWDN_L", + "WCAM_RST_L", + "UCAM_PWDM_L", + "UCAM_RST_L", + "WCAM_24M_CLK", + "UCAM_24M_CLK", + "MT6319_INT", + "DISP_RST_1V8_L", + "DSIO_DSI_TE", + "", + "TP", + "MIPI_BL_PWM_1V8", + "", + "UART_AP_TX_GSC_RX", + "UART_GSC_TX_AP_RX", + "UART_SSPM_TX_DBGCON_RX", + "UART_DBGCON_TX_SSPM_RX", + "UART_ADSP_TX_DBGCON_RX", + "UART_DBGCON_TX_ADSP_RX", + "JTAG_AP_TMS", + "JTAG_AP_TCK", + "JTAG_AP_TDI", + "JTAG_AP_TDO", + "JTAG_AP_TRST", + "AP_KPCOL0", + "TP", + "", + "TP", + "EC_AP_HPD_OD", + "PCIE_WAKE_1V8_ODL", + "PCIE_RST_1V8_L", + "PCIE_CLKREQ_1V8_ODL", + "", + "", + "", + "", + "", + "AP_I2C_AUD_SCL_1V8", + "AP_I2C_AUD_SDA_1V8", + "AP_I2C_TPM_SCL_1V8", + "AP_I2C_TPM_SDA_1V8", + "AP_I2C_TCHSCR_SCL_1V8", + "AP_I2C_TCHSCR_SDA_1V8", + "AP_I2C_PMIC_SAR_SCL_1V8", + "AP_I2C_PMIC_SAR_SDA_1V8", + "AP_I2C_EC_HID_KB_SCL_1V8", + "AP_I2C_EC_HID_KB_SDA_1V8", + "AP_I2C_UCAM_SCL_1V8", + "AP_I2C_UCAM_SDA_1V8", + "AP_I2C_WCAM_SCL_1V8", + "AP_I2C_WCAM_SDA_1V8", + "SPI_AP_CS_EC_L", + "SPI_AP_CLK_EC", + "SPI_AP_DO_EC_DI", + "SPI_AP_DI_EC_DO", + "TP", + "TP", + "SPI_AP_CS_TCHSCR_L", + "SPI_AP_CLK_TCHSCR", + "SPI_AP_DO_TCHSCR_DI", + "SPI_AP_DI_TCHSCR_DO", + "TP", + "TP", + "TP", + "TP", + "", + "", + "", + "TP", + "", + "", + "", + "", + "", + "PWRAP_SPI_CS_L", + "PWRAP_SPI_CK", + "PWRAP_SPI_MOSI", + "PWRAP_SPI_MISO", + "SRCLKENA0", + "SRCLKENA1", + "SCP_VREQ_VAO", + "AP_RTC_CLK32K", + "AP_PMIC_WDTRST_L", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1", + "", + "HP_INT_ODL", + "SPKR_INT_ODL", + "I2S_HP_DATAIN", + "EN_SPKR", + "I2S_SPKR_MCLK", + "I2S_SPKR_BCLK", + "I2S_HP_MCLK", + "I2S_HP_BCLK", + "I2S_HP_LRCK", + "I2S_HP_DATAOUT", + "RST_SPKR_L", + "I2S_SPKR_LRCK", + "I2S_SPKR_DATAIN", + "", + "", + "", + "", + "SPI_AP_CLK_ROM", + "SPI_AP_CS_ROM_L", + "SPI_AP_DO_ROM_DI", + "SPI_AP_DI_ROM_DO", + "TP", + "TP", + "", + "", + "", + "", + "", + "", + "", + "", + "EN_PP2800A_UCAM_X", + "EN_PP1200_UCAM_X", + "EN_PP2800A_WCAM_X", + "EN_PP1100_WCAM_X", + "TCHSCR_INT_1V8_L", + "", + "MT7921_PMU_EN_1V8", + "", + "AP_EC_WARM_RST_REQ", + "EC_AP_HID_INT_ODL", + "EC_AP_INT_ODL", + "AP_XHCI_INIT_DONE", + "EMMC_DAT7", + "EMMC_DAT6", + "EMMC_DAT5", + "EMMC_DAT4", + "EMMC_RST_L", + "EMMC_CMD", + "EMMC_CLK", + "EMMC_DAT3", + "EMMC_DAT2", + "EMMC_DAT1", + "EMMC_DAT0", + "EMMC_DSL", + "", + "", + "", + "", + "", + "", + "", + "", + "USB3_HUB_RST_L", + "EC_AP_RSVD0_ODL", + "", + "", + "SPMI_SCL", + "SPMI_SDA"; + + audio_codec_pins: audio-codec-pins { + pins-hp-int-odl { + pinmux = ; + input-enable; + }; + }; + + speaker_en: speaker-en-pins { + pins-en-spkr { + pinmux = ; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi new file mode 100644 index 000000000000..b6abecbcfa81 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -0,0 +1,1156 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ +/dts-v1/; +#include +#include "mt8188.dtsi" +#include "mt6359.dtsi" + +/ { + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + mmc0 = &mmc0; + serial0 = &uart0; + }; + + backlight_lcd0: backlight-lcd0 { + compatible = "pwm-backlight"; + brightness-levels = <0 1023>; + default-brightness-level = <576>; + enable-gpios = <&pio 1 GPIO_ACTIVE_HIGH>; + num-interpolated-steps = <1023>; + power-supply = <&ppvar_sys>; + pwms = <&disp_pwm0 0 500000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dmic-codec { + compatible = "dmic-codec"; + num-channels = <2>; + wakeup-delay-ms = <100>; + }; + + memory@40000000 { + device_type = "memory"; + /* The size will be filled in by the bootloader */ + reg = <0 0x40000000 0 0>; + }; + + /* system wide LDO 1.8V power rail */ + pp1800_ldo_z1: regulator-pp1800-ldo-z1 { + compatible = "regulator-fixed"; + regulator-name = "pp1800_ldo_z1"; + /* controlled by PP3300_Z1 */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&pp3300_z1>; + }; + + /* separately switched 3.3V power rail */ + pp3300_s3: regulator-pp3300-s3 { + compatible = "regulator-fixed"; + regulator-name = "pp3300_s3"; + /* controlled by PMIC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&pp3300_z1>; + }; + + /* system wide 3.3V power rail */ + pp3300_z1: regulator-pp3300-z1 { + compatible = "regulator-fixed"; + regulator-name = "pp3300_z1"; + /* controlled by PP3300_LDO_Z5 & EN_PWR_Z1 */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&ppvar_sys>; + }; + + pp3300_wlan: regulator-pp3300-wlan { + compatible = "regulator-fixed"; + regulator-name = "pp3300_wlan"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 12 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&wlan_en>; + pinctrl-names = "default"; + vin-supply = <&pp3300_z1>; + }; + + /* system wide 4.2V power rail */ + pp4200_s5: regulator-pp4200-s5 { + compatible = "regulator-fixed"; + regulator-name = "pp4200_s5"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + vin-supply = <&ppvar_sys>; + }; + + /* system wide 5.0V power rail */ + pp5000_z1: regulator-pp5000-z1 { + compatible = "regulator-fixed"; + regulator-name = "pp5000_z1"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&ppvar_sys>; + }; + + pp5000_usb_vbus: regulator-pp5000-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "pp5000_usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pio 150 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp5000_z1>; + }; + + /* system wide semi-regulated power rail from battery or USB */ + ppvar_sys: regulator-ppvar-sys { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + ppvar_mipi_disp_avdd: regulator-ppvar-mipi-disp-avdd { + compatible = "regulator-fixed"; + regulator-name = "ppvar_mipi_disp_avdd"; + enable-active-high; + gpio = <&pio 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipi_disp_avdd_en>; + vin-supply = <&pp5000_z1>; + }; + + ppvar_mipi_disp_avee: regulator-ppvar-mipi-disp-avee { + compatible = "regulator-fixed"; + regulator-name = "ppvar_mipi_disp_avee"; + regulator-enable-ramp-delay = <10000>; + enable-active-high; + gpio = <&pio 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipi_disp_avee_en>; + vin-supply = <&pp5000_z1>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + apu_mem: memory@55000000 { + compatible = "shared-dma-pool"; + reg = <0 0x55000000 0 0x1400000>; + }; + + adsp_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0xf00000>; + no-map; + }; + + afe_dma_mem: memory@60f00000 { + compatible = "shared-dma-pool"; + reg = <0 0x60f00000 0 0x100000>; + no-map; + }; + + adsp_dma_mem: memory@61000000 { + compatible = "shared-dma-pool"; + reg = <0 0x61000000 0 0x100000>; + no-map; + }; + }; +}; + +&adsp { + memory-region = <&adsp_dma_mem>, <&adsp_mem>; + pinctrl-names = "default"; + pinctrl-0 = <&adsp_uart_pins>; + status = "okay"; +}; + +&afe { + memory-region = <&afe_dma_mem>; + mediatek,etdm-out1-cowork-source = <0>; /* in1 */ + mediatek,etdm-in2-cowork-source = <3>; /* out2 */ + status = "okay"; +}; + +&auxadc { + status = "okay"; +}; + +&cam_vcore { + domain-supply = <&mt6359_vproc1_buck_reg>; +}; + +/* + * Geralt is the reference design and doesn't have target TDP. + * Ciri is (currently) the only device following Geralt, and its + * TDP target is 90 degrees. + **/ +&cpu_little0_alert0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; +}; + +&cpu_little1_alert0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; +}; + +&cpu_little2_alert0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; +}; + +&cpu_little3_alert0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; +}; + +&cpu_big0_alert0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; +}; + +&cpu_big1_alert0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; +}; + +&disp_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + dsi_panel: panel@0 { + /* Compatible string for different panels can be found in each device dts */ + reg = <0>; + enable-gpios = <&pio 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipi_dsi_pins>; + + backlight = <&backlight_lcd0>; + avdd-supply = <&ppvar_mipi_disp_avdd>; + avee-supply = <&ppvar_mipi_disp_avee>; + pp1800-supply = <&mt6359_vm18_ldo_reg>; + rotation = <270>; + + status = "okay"; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + + port { + dsi_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; +}; + +&disp_pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pins>; + status = "okay"; +}; + +&disp_pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm1_pins>; +}; + +&dp_intf1 { + status = "okay"; + + port { + dp_intf1_out: endpoint { + remote-endpoint = <&dptx_in>; + }; + }; +}; + +&dp_tx { + pinctrl-names = "default"; + pinctrl-0 = <&dp_tx_hpd>; + #sound-dai-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dptx_in: endpoint { + remote-endpoint = <&dp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dptx_out: endpoint { + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&gpu { + mali-supply = <&mt6359_vproc2_buck_reg>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + status = "okay"; + + tpm@50 { + compatible = "google,cr50"; + reg = <0x50>; + interrupts-extended = <&pio 0 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&gsc_int>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&mfg0 { + domain-supply = <&mt6359_vproc2_buck_reg>; +}; + +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + +&mipi_tx_config0 { + status = "okay"; +}; + +&mmc0 { + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + hs400-ds-delay = <0x1481b>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + supports-cqe; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + status = "okay"; +}; + +&mt6359codec { + mediatek,dmic-mode = <1>; /* one-wire */ + mediatek,mic-type-0 = <2>; /* DMIC */ + mediatek,mic-type-2 = <2>; /* DMIC */ +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_sshub_buck_reg { + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <550000>; + regulator-always-on; +}; + +&mt6359_vio28_ldo_reg { + /delete-property/ regulator-always-on; +}; + +&mt6359_vm18_ldo_reg { + /delete-property/ regulator-always-on; +}; + +&mt6359_vmodem_buck_reg { + regulator-min-microvolt = <775000>; + regulator-max-microvolt = <775000>; +}; + +&mt6359_vpa_buck_reg { + regulator-max-microvolt = <3100000>; +}; + +&mt6359_vproc2_buck_reg { + /* + * Called "ppvar_dvdd_gpu" in the schematic. Renamed to + * "ppvar_dvdd_vgpu" here to match mtk-regulator-coupler requirements. + */ + regulator-name = "ppvar_dvdd_vgpu"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; + regulator-coupled-max-spread = <6250>; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; +}; + +&mt6359_vsram_others_ldo_reg { + regulator-name = "pp0850_dvdd_sram_gpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vproc2_buck_reg>; + regulator-coupled-max-spread = <6250>; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; +}; + +&nor_flash { + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pciephy { + status = "okay"; +}; + +&pio { + gpio-line-names = + "gsc_int", + "AP_DISP_BKLTEN", + "", + "EN_PPVAR_MIPI_DISP", + "EN_PPVAR_MIPI_DISP_150MA", + "TCHSCR_RST_1V8_L", + "TCHSRC_REPORT_DISABLE", + "", + "", + "", + "", + "I2S_SPKR_DATAOUT", + "EN_PP3300_WLAN_X", + "WIFI_KILL_1V8_L", + "BT_KILL_1V8_L", + "AP_FLASH_WP_L", /* ... is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */ + "", + "EDP_HPD_1V8", + "WCAM_PWDN_L", + "WCAM_RST_L", + "UCAM_PWDM_L", + "UCAM_RST_L", + "WCAM_24M_CLK", + "UCAM_24M_CLK", + "MT6319_INT", + "DISP_RST_1V8_L", + "DSIO_DSI_TE", + "EN_PP3300_EDP_DISP_X", + "TP", + "MIPI_BL_PWM_1V8", + "EDP_BL_PWM_1V8", + "UART_AP_TX_GSC_RX", + "UART_GSC_TX_AP_RX", + "UART_SSPM_TX_DBGCON_RX", + "UART_DBGCON_TX_SSPM_RX", + "UART_ADSP_TX_DBGCON_RX", + "UART_DBGCON_TX_ADSP_RX", + "JTAG_AP_TMS", + "JTAG_AP_TCK", + "JTAG_AP_TDI", + "JTAG_AP_TDO", + "JTAG_AP_TRST", + "AP_KPCOL0", + "TP", + "BEEP_ON_OD", + "TP", + "EC_AP_HPD_OD", + "PCIE_WAKE_1V8_ODL", + "PCIE_RST_1V8_L", + "PCIE_CLKREQ_1V8_ODL", + "", + "", + "", + "", + "", + "AP_I2C_AUD_SCL_1V8", + "AP_I2C_AUD_SDA_1V8", + "AP_I2C_TPM_SCL_1V8", + "AP_I2C_TPM_SDA_1V8", + "AP_I2C_TCHSCR_SCL_1V8", + "AP_I2C_TCHSCR_SDA_1V8", + "AP_I2C_PMIC_SAR_SCL_1V8", + "AP_I2C_PMIC_SAR_SDA_1V8", + "AP_I2C_EC_HID_KB_SCL_1V8", + "AP_I2C_EC_HID_KB_SDA_1V8", + "AP_I2C_UCAM_SCL_1V8", + "AP_I2C_UCAM_SDA_1V8", + "AP_I2C_WCAM_SCL_1V8", + "AP_I2C_WCAM_SDA_1V8", + "SPI_AP_CS_EC_L", + "SPI_AP_CLK_EC", + "SPI_AP_DO_EC_DI", + "SPI_AP_DI_EC_DO", + "TP", + "TP", + "SPI_AP_CS_TCHSCR_L", + "SPI_AP_CLK_TCHSCR", + "SPI_AP_DO_TCHSCR_DI", + "SPI_AP_DI_TCHSCR_DO", + "TP", + "TP", + "TP", + "TP", + "", + "", + "", + "TP", + "", + "SAR_INT_ODL", + "", + "", + "", + "PWRAP_SPI_CS_L", + "PWRAP_SPI_CK", + "PWRAP_SPI_MOSI", + "PWRAP_SPI_MISO", + "SRCLKENA0", + "SRCLKENA1", + "SCP_VREQ_VAO", + "AP_RTC_CLK32K", + "AP_PMIC_WDTRST_L", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1", + "SD_CD_ODL", + "HP_INT_ODL", + "SPKR_INT_ODL", + "I2S_HP_DATAIN", + "EN_SPKR", + "I2S_SPKR_MCLK", + "I2S_SPKR_BCLK", + "I2S_HP_MCLK", + "I2S_HP_BCLK", + "I2S_HP_LRCK", + "I2S_HP_DATAOUT", + "RST_SPKR_L", + "I2S_SPKR_LRCK", + "I2S_SPKR_DATAIN", + "", + "", + "", + "", + "SPI_AP_CLK_ROM", + "SPI_AP_CS_ROM_L", + "SPI_AP_DO_ROM_DI", + "SPI_AP_DI_ROM_DO", + "TP", + "TP", + "", + "", + "", + "", + "", + "", + "", + "", + "EN_PP2800A_UCAM_X", + "EN_PP1200_UCAM_X", + "EN_PP2800A_WCAM_X", + "EN_PP1100_WCAM_X", + "TCHSCR_INT_1V8_L", + "EN_PP3300_MIPI_TCHSCR_X", + "MT7921_PMU_EN_1V8", + "EN_PP3300_EDP_TCHSCR_X", + "AP_EC_WARM_RST_REQ", + "EC_AP_HID_INT_ODL", + "EC_AP_INT_ODL", + "AP_XHCI_INIT_DONE", + "EMMC_DAT7", + "EMMC_DAT6", + "EMMC_DAT5", + "EMMC_DAT4", + "EMMC_RST_L", + "EMMC_CMD", + "EMMC_CLK", + "EMMC_DAT3", + "EMMC_DAT2", + "EMMC_DAT1", + "EMMC_DAT0", + "EMMC_DSL", + "SD_CMD", + "SD_CLK", + "SD_DAT0", + "SD_DAT1", + "SD_DAT2", + "SD_DAT3", + "", + "", + "USB3_HUB_RST_L", + "EC_AP_RSVD0_ODL", + "", + "", + "SPMI_SCL", + "SPMI_SDA"; + + adsp_uart_pins: adsp-uart-pins { + pins-bus { + pinmux = , + ; + }; + }; + + aud_etdm_hp_on: aud-etdm-hp-on-pins { + pins-bus { + pinmux = , + , + , + ; + }; + }; + + aud_etdm_hp_off: aud-etdm-hp-off-pins { + pins-bus { + pinmux = , + , + , + ; + bias-pull-down; + input-enable; + }; + }; + + aud_etdm_spk_on: aud-etdm-spk-on-pins { + pins-bus { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + }; + + aud_etdm_spk_off: aud-etdm-spk-off-pins { + pins-bus { + pinmux = , + , + , + ; + bias-pull-down; + input-enable; + }; + }; + + aud_mtkaif_on: aud-mtkaif-on-pins { + pins-bus { + pinmux = , + , + , + , + , + ; + }; + }; + + aud_mtkaif_off: aud-mtkaif-off-pins { + pins-bus { + pinmux = , + , + , + , + , + ; + bias-pull-down; + input-enable; + }; + }; + + cros_ec_int: cros-ec-int-pins { + pins-ec-ap-int-odl { + pinmux = ; + input-enable; + }; + }; + + disp_pwm0_pins: disp-pwm0-pins { + pins-disp-pwm0 { + pinmux = ; + output-high; + }; + }; + + disp_pwm1_pins: disp-pwm1-pins { + pins-disp-pwm1 { + pinmux = ; + output-high; + }; + }; + + dp_tx_hpd: dp-tx-hpd-pins { + pins-dp-tx-hpd { + pinmux = ; + }; + }; + + gsc_int: gsc-int-pins { + pins-gsc-ap-int-odl { + pinmux = ; + input-enable; + }; + }; + + i2c0_pins: i2c0-pins { + pins-bus { + pinmux = , + ; + }; + }; + + i2c1_pins: i2c1-pins { + pins-bus { + pinmux = , + ; + }; + }; + + i2c2_pins: i2c2-pins { + pins-bus { + pinmux = , + ; + bias-disable; + drive-strength = <12>; + }; + }; + + i2c3_pins: i2c3-pins { + pins-bus { + pinmux = , + ; + }; + }; + + i2c4_pins: i2c4-pins { + pins-bus { + pinmux = , + ; + }; + }; + + i2c5_pins: i2c5-pins { + pins-bus { + pinmux = , + ; + }; + }; + + i2c6_pins: i2c6-pins { + pins-bus { + pinmux = , + ; + }; + }; + + mipi_disp_avdd_en: mipi-disp-avdd-en-pins { + pins-en-ppvar-mipi-disp { + pinmux = ; + output-low; + }; + }; + + mipi_disp_avee_en: mipi-disp-avee-en-pins { + pins-en-ppvar-mipi-disp-150ma { + pinmux = ; + output-low; + }; + }; + + mipi_dsi_pins: mipi-dsi-pins { + pins-bus { + pinmux = , + ; + output-low; + }; + }; + + mmc0_pins_default: mmc0-default-pins { + pins-bus { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + pins-bus { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <8>; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-ds { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <8>; + bias-pull-up = ; + }; + }; + + nor_pins: nor-default-pins { + pins-clk { + pinmux = , + , + ; + bias-pull-down; + }; + + pins-cs { + pinmux = ; + bias-pull-up; + }; + }; + + pcie_pins: pcie-default-pins { + pins-bus { + pinmux = , + , + ; + }; + }; + + spi0_pins: spi0-pins { + pins-bus { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi1_pins_default: spi1-default-pins { + pins-bus { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi1_pins_sleep: spi1-sleep-pins { + pins-bus { + pinmux = , + , + , + ; + bias-pull-down; + input-enable; + }; + }; + + spi2_pins: spi2-pins { + pins-bus { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + uart0_pins: uart0-pins { + pins-bus { + pinmux = , + ; + bias-pull-up; + }; + }; + + wlan_en: wlan-en-pins { + pins-en-pp3300-wlan { + pinmux = ; + output-low; + }; + }; +}; + +&pmic { + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sound { + pinctrl-names = "aud_etdm_hp_on", "aud_etdm_hp_off", + "aud_etdm_spk_on", "aud_etdm_spk_off", + "aud_mtkaif_on", "aud_mtkaif_off"; + pinctrl-0 = <&aud_etdm_hp_on>; + pinctrl-1 = <&aud_etdm_hp_off>; + pinctrl-2 = <&aud_etdm_spk_on>; + pinctrl-3 = <&aud_etdm_spk_off>; + pinctrl-4 = <&aud_mtkaif_on>; + pinctrl-5 = <&aud_mtkaif_off>; + mediatek,adsp = <&adsp>; + /* The audio-routing is defined in each board dts */ + + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupts-extended = <&pio 149 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cros_ec_int>; + spi-max-frequency = <3000000>; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cbas { + compatible = "google,cros-cbas"; + }; + }; +}; + +&spi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_default>; + pinctrl-1 = <&spi1_pins_sleep>; + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +/* USB detachable base */ +&xhci0 { + /* controlled by EC */ + vbus-supply = <&pp3300_z1>; + status = "okay"; +}; + +/* USB3 hub */ +&xhci1 { + vusb33-supply = <&pp3300_s3>; + vbus-supply = <&pp5000_usb_vbus>; + status = "okay"; +}; + +/* USB BT */ +&xhci2 { + /* no power supply since MT7921's power is controlled by PCIe */ + /* MT7921's USB BT has issues with USB2 LPM */ + usb2-lpm-disable; + status = "okay"; +}; + +#include + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x01, 0x04, KEY_MICMUTE) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; From c31f6c2f25586557bc586a9b3713bd7473e0cac3 Mon Sep 17 00:00:00 2001 From: Wojciech Macek Date: Fri, 29 Nov 2024 05:57:19 +0000 Subject: [PATCH 06/71] dt-bindings: arm: mediatek: Add MT8186 Starmie Chromebooks Add an entry for the MT8186 based Starmie Chromebooks, also known as the ASUS Chromebook Enterprise CM30 Detachable (CM3001). The device is a tablet style chromebook. Signed-off-by: Wojciech Macek Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20241129055720.3328681-2-wmacek@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 4b68f0baf010..f8692ad455e7 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -263,6 +263,19 @@ properties: - const: google,steelix-sku196608 - const: google,steelix - const: mediatek,mt8186 + - description: Google Starmie (ASUS Chromebook Enterprise CM30 (CM3001)) + items: + - const: google,starmie-sku0 + - const: google,starmie-sku2 + - const: google,starmie-sku3 + - const: google,starmie + - const: mediatek,mt8186 + - description: Google Starmie (ASUS Chromebook Enterprise CM30 (CM3001)) + items: + - const: google,starmie-sku1 + - const: google,starmie-sku4 + - const: google,starmie + - const: mediatek,mt8186 - description: Google Steelix (Lenovo 300e Yoga Chromebook Gen 4) items: - enum: From d926d78bc93b1bfe18bc1cf80e66e1a0e38297ce Mon Sep 17 00:00:00 2001 From: Wojciech Macek Date: Fri, 29 Nov 2024 05:57:20 +0000 Subject: [PATCH 07/71] arm64: dts: mediatek: mt8186: Add Starmie device Add support for Starmie Chromebooks. Signed-off-by: Wojciech Macek Link: https://lore.kernel.org/r/20241129055720.3328681-3-wmacek@chromium.org Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 2 + .../mediatek/mt8186-corsola-starmie-sku0.dts | 31 ++ .../mediatek/mt8186-corsola-starmie-sku1.dts | 31 ++ .../dts/mediatek/mt8186-corsola-starmie.dtsi | 472 ++++++++++++++++++ 4 files changed, 536 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku0.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku1.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index c6c34d99316b..1a493052f4e4 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -59,6 +59,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393216.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393217.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393218.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-rusty-sku196608.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku0.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131072.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131073.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327681.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku0.dts new file mode 100644 index 000000000000..23e194579bf2 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku0.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-starmie.dtsi" + +/ { + model = "Google Starmie sku0 board"; + compatible = "google,starmie-sku0", "google,starmie-sku2", + "google,starmie-sku3", "google,starmie", + "mediatek,mt8186"; +}; + +&panel { + compatible = "starry,ili9882t"; +}; + +&i2c1 { + touchscreen: touchscreen@41 { + compatible = "ilitek,ili9882t"; + reg = <0x41>; + interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + panel = <&panel>; + reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>; + vccio-supply = <&mt6366_vio18_reg>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku1.dts new file mode 100644 index 000000000000..214b972c9357 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku1.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-starmie.dtsi" + +/ { + model = "Google Starmie sku1 board"; + compatible = "google,starmie-sku1", "google,starmie-sku4", + "google,starmie", "mediatek,mt8186"; +}; + +&panel { + compatible = "starry,himax83102-j02", "himax,hx83102"; +}; + +&i2c1 { + touchscreen_himax: touchscreen@4f { + compatible = "hid-over-i2c"; + reg = <0x4f>; + interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + vdd-supply = <&mt6366_vio18_reg>; + panel = <&panel>; + post-power-on-delay-ms = <450>; + hid-descr-addr = <0x0001>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie.dtsi new file mode 100644 index 000000000000..5ea8bdc00e81 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie.dtsi @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola.dtsi" + +/ { + en_pp6000_mipi_disp_150ma: en-pp6000-mipi-disp-150ma { + compatible = "regulator-fixed"; + regulator-name = "en_pp6000_mipi_disp_150ma"; + gpio = <&pio 154 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp6000_mipi_disp_150ma_fixed_pins>; + }; + + /* + * Starmie does not have 3.3V display regulator. It is replaced + * with 6V module for enabling panel, re-using eDP GPIOs. + */ + /delete-node/ pp3300_disp_x; + en_pp6000_mipi_disp: en-regulator-pp6000-mipi-disp { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_panel_fixed_pins>; + gpios = <&pio 153 GPIO_ACTIVE_HIGH>; + regulator-name = "en_pp6000_mipi_disp"; + enable-active-high; + regulator-enable-ramp-delay = <3000>; + vin-supply = <&pp3300_z2>; + }; + + tboard_thermistor1: thermal-sensor1 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&auxadc 0>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-5000) 1492 + 0 1413 + 5000 1324 + 10000 1227 + 15000 1121 + 20000 1017 + 25000 900 + 30000 797 + 35000 698 + 40000 606 + 45000 522 + 50000 449 + 55000 383 + 60000 327 + 65000 278 + 70000 236 + 75000 201 + 80000 171 + 85000 145 + 90000 163 + 95000 124 + 100000 91 + 105000 78 + 110000 67 + 115000 58 + 120000 50 + 125000 44>; + }; + + tboard_thermistor2: thermal-sensor2 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&auxadc 1>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-5000) 1492 + 0 1413 + 5000 1324 + 10000 1227 + 15000 1121 + 20000 1017 + 25000 900 + 30000 797 + 35000 698 + 40000 606 + 45000 522 + 50000 449 + 55000 383 + 60000 327 + 65000 278 + 70000 236 + 75000 201 + 80000 171 + 85000 145 + 90000 163 + 95000 124 + 100000 91 + 105000 78 + 110000 67 + 115000 58 + 120000 50 + 125000 44>; + }; +}; + +/* + * Starmie does not have EC keyboard. Remove default keyboard controller + * and replace it with the driver for side switches. + */ +/delete-node/ &keyboard_controller; + +&cros_ec { + cbas: cbas { + compatible = "google,cros-cbas"; + }; + + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + panel: panel@0 { + /* compatible will be set in board dts */ + reg = <0>; + enable-gpios = <&pio 98 0>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_default_pins>; + avdd-supply = <&en_pp6000_mipi_disp>; + avee-supply = <&en_pp6000_mipi_disp_150ma>; + pp1800-supply = <&mt6366_vio18_reg>; + backlight = <&backlight_lcd0>; + rotation = <270>; + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_out { + remote-endpoint = <&panel_in>; +}; + +&i2c0 { + status = "disabled"; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c4 { + status = "disabled"; +}; + +&i2c5 { + clock-frequency = <400000>; +}; + +&mmc1_pins_default { + pins-clk { + drive-strength = <8>; + }; + + pins-cmd-dat { + drive-strength = <8>; + }; +}; + +&mmc1_pins_uhs { + pins-clk { + drive-strength = <8>; + }; + + pins-cmd-dat { + drive-strength = <8>; + }; +}; + +&pen_insert { + wakeup-event-action = ; +}; + +&pio { + /* 185 lines */ + gpio-line-names = "TP", + "TP", + "TP", + "I2S0_HP_DI", + "I2S3_DP_SPKR_DO", + "SAR_INT_ODL", + "BT_WAKE_AP_ODL", + "WIFI_INT_ODL", + "DPBRDG_INT_ODL", + "NC", + "EC_AP_HPD_OD", + "NC", + "TCHSCR_INT_1V8_ODL", + "EC_AP_INT_ODL", + "EC_IN_RW_ODL", + "GSC_AP_INT_ODL", + /* + * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics + * call it AP_WP_ODL. + */ + "AP_FLASH_WP_L", + "HP_INT_ODL", + "PEN_EJECT_OD", + "NC", + "NC", + "UCAM_SEN_EN", + "NC", + "NC", + "NC", + "I2S2_DP_SPK_MCK", + "I2S2_DP_SPKR_BCK", + "I2S2_DP_SPKR_LRCK", + "NC", + "NC", + "NC", + "NC", + "UART_GSC_TX_AP_RX", + "UART_AP_TX_GSC_RX", + "UART_DBGCON_TX_ADSP_RX", + "UART_ADSP_TX_DBGCON_RX", + "NC", + "TCHSCR_REPORT_DISABLE", + "NC", + "EN_PP1800_DPBRDG", + "SPI_AP_CLK_EC", + "SPI_AP_CS_EC_L", + "SPI_AP_DO_EC_DI", + "SPI_AP_DI_EC_DO", + "SPI_AP_CLK_GSC", + "SPI_AP_CS_GSC_L", + "SPI_AP_DO_GSC_DI", + "SPI_AP_DI_GSC_DO", + "UART_DBGCON_TX_SCP_RX", + "UART_SCP_TX_DBGCON_RX", + "EN_PP1200_CAM_X", + "WLAN_MODULE_RST_L", + "NC", + "NC", + "NC", + "NC", + "I2S1_HP_DO", + "I2S1_HP_BCK", + "I2S1_HP_LRCK", + "I2S1_HP_MCK", + "TCHSCR_RST_1V8_L", + "SPI_AP_CLK_ROM", + "SPI_AP_CS_ROM_L", + "SPI_AP_DO_ROM_DI", + "SPI_AP_DI_ROM_DO", + "NC", + "NC", + "EMMC_STRB", + "EMMC_CLK", + "EMMC_CMD", + "EMMC_RST_L", + "EMMC_DATA0", + "EMMC_DATA1", + "EMMC_DATA2", + "EMMC_DATA3", + "EMMC_DATA4", + "EMMC_DATA5", + "EMMC_DATA6", + "EMMC_DATA7", + "AP_KPCOL0", + "NC", + "NC", + "NC", + "TP", + "SDIO_CLK", + "SDIO_CMD", + "SDIO_DATA0", + "SDIO_DATA1", + "SDIO_DATA2", + "SDIO_DATA3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "MIPI_BL_PWM_1V8", + "DISP_RST_1V8_L", + "MIPI_DPI_CLK", + "MIPI_DPI_VSYNC", + "MIPI_DPI_HSYNC", + "MIPI_DPI_DE", + "MIPI_DPI_D0", + "MIPI_DPI_D1", + "MIPI_DPI_D2", + "MIPI_DPI_D3", + "MIPI_DPI_D4", + "MIPI_DPI_D5", + "MIPI_DPI_D6", + "MIPI_DPI_DA7", + "MIPI_DPI_D8", + "MIPI_DPI_D9", + "MIPI_DPI_D10", + "MIPI_DPI_D11", + "PCM_BT_CLK", + "PCM_BT_SYNC", + "PCM_BT_DI", + "PCM_BT_DO", + "JTAG_TMS_TP", + "JTAG_TCK_TP", + "JTAG_TDI_TP", + "JTAG_TDO_TP", + "JTAG_TRSTN_TP", + "NC", + "NC", + "UCAM_DET_ODL", + "NC", + "NC", + "AP_I2C_TCHSCR_SCL_1V8", + "AP_I2C_TCHSCR_SDA_1V8", + "NC", + "NC", + "AP_I2C_DPBRDG_SCL_1V8", + "AP_I2C_DPBRDG_SDA_1V8", + "NC", + "NC", + "AP_I2C_AUD_SCL_1V8", + "AP_I2C_AUD_SDA_1V8", + "AP_I2C_DISP_SCL_1V8", + "AP_I2C_DISP_SDA_1V8", + "NC", + "NC", + "NC", + "NC", + "SCP_I2C_SENSOR_SCL_1V8", + "SCP_I2C_SENSOR_SDA_1V8", + "AP_EC_WARM_RST_REQ", + "AP_XHCI_INIT_DONE", + "USB3_HUB_RST_L", + "EN_SPKR", + "BEEP_ON", + "AP_DISP_BKLTEN", + "EN_PP6000_MIPI_DISP", + "EN_PP6000_MIPI_DISP_150MA", + "BT_KILL_1V8_L", + "WIFI_KILL_1V8_L", + "PWRAP_SPI0_CSN", + "PWRAP_SPI0_CK", + "PWRAP_SPI0_MO", + "PWRAP_SPI0_MI", + "SRCLKENA0", + "SRCLKENA1", + "SCP_VREQ_VAO", + "AP_RTC_CLK32K", + "AP_PMIC_WDTRST_L", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_CLK_MISO", + "AUD_SYNC_MISO", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1", + "NC", + "NC", + "NC", + "DPBRDG_RST_L", + "LTE_W_DISABLE_L", + "LTE_SAR_DETECT_L", + "EN_PP3300_LTE_X", + "LTE_PWR_OFF_L", + "LTE_RESET_L", + "TP", + "TP"; + + dpi_default_pins: dpi-default-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = <10>; + output-low; + }; + }; + + dpi_func_pins: dpi-func-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = <10>; + }; + }; + + en_pp6000_mipi_disp_150ma_fixed_pins: en_pp6000-mipi-disp-150ma-fixed-pins { + pins-en { + pinmux = ; + output-low; + }; + }; + + panel_default_pins: panel-default-pins { + pins-en { + pinmux = ; + output-low; + }; + }; +}; + +&usb_c1 { + status = "disabled"; +}; + +&thermal_zones { + tboard1-thermal { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&tboard_thermistor1>; + }; + + tboard2-thermal { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&tboard_thermistor2>; + }; +}; + +&wifi_pwrseq { + reset-gpios = <&pio 51 1>; +}; + +/* + * Battery on Starmie is using a different address than default. + * Remove old node to reuse "battery" alias. + */ +/delete-node/ &battery; +&i2c_tunnel { + battery: sbs-battery@f { + compatible = "sbs,sbs-battery"; + reg = <0xf>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <1>; + }; +}; From e3ee31e4409f051c021a30122f3c470f093a7386 Mon Sep 17 00:00:00 2001 From: Val Packett Date: Wed, 4 Dec 2024 16:05:04 -0300 Subject: [PATCH 08/71] arm64: dts: mediatek: mt8516: fix GICv2 range On the MT8167 which is based on the MT8516 DTS, the following error was appearing on boot, breaking interrupt operation: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set Similar to what's been proposed for MT7622 which has the same issue, fix by using the range reported by force_probe. Link: https://lore.kernel.org/all/YmhNSLgp%2Fyg8Vr1F@makrotopia.org/ Fixes: 5236347bde42 ("arm64: dts: mediatek: add dtsi for MT8516") Signed-off-by: Val Packett Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241204190524.21862-2-val@packett.cool Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index d0b03dc4d3f4..444429341302 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -268,7 +268,7 @@ gic: interrupt-controller@10310000 { interrupt-parent = <&gic>; interrupt-controller; reg = <0 0x10310000 0 0x1000>, - <0 0x10320000 0 0x1000>, + <0 0x1032f000 0 0x2000>, <0 0x10340000 0 0x2000>, <0 0x10360000 0 0x2000>; interrupts = Date: Wed, 4 Dec 2024 16:05:05 -0300 Subject: [PATCH 09/71] arm64: dts: mediatek: mt8516: fix wdt irq type The GICv2 does not support EDGE_FALLING interrupts, so the watchdog would refuse to attach due to a failing check coming from the GIC driver. Fixes: 5236347bde42 ("arm64: dts: mediatek: add dtsi for MT8516") Signed-off-by: Val Packett Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241204190524.21862-3-val@packett.cool Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index 444429341302..098c32ebf678 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -206,7 +206,7 @@ watchdog@10007000 { compatible = "mediatek,mt8516-wdt", "mediatek,mt6589-wdt"; reg = <0 0x10007000 0 0x1000>; - interrupts = ; + interrupts = ; #reset-cells = <1>; }; From eb72341fd92b7af510d236e5a8554d855ed38d3c Mon Sep 17 00:00:00 2001 From: Val Packett Date: Wed, 4 Dec 2024 16:05:06 -0300 Subject: [PATCH 10/71] arm64: dts: mediatek: mt8516: add i2c clock-div property Move the clock-div property from the pumpkin board dtsi to the SoC's since it belongs to the SoC itself and is required on other devices. Fixes: 5236347bde42 ("arm64: dts: mediatek: add dtsi for MT8516") Signed-off-by: Val Packett Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241204190524.21862-4-val@packett.cool Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 3 +++ arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index 098c32ebf678..dd17d8a88c19 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -344,6 +344,7 @@ i2c0: i2c@11009000 { reg = <0 0x11009000 0 0x90>, <0 0x11000180 0 0x80>; interrupts = ; + clock-div = <2>; clocks = <&topckgen CLK_TOP_I2C0>, <&topckgen CLK_TOP_APDMA>; clock-names = "main", "dma"; @@ -358,6 +359,7 @@ i2c1: i2c@1100a000 { reg = <0 0x1100a000 0 0x90>, <0 0x11000200 0 0x80>; interrupts = ; + clock-div = <2>; clocks = <&topckgen CLK_TOP_I2C1>, <&topckgen CLK_TOP_APDMA>; clock-names = "main", "dma"; @@ -372,6 +374,7 @@ i2c2: i2c@1100b000 { reg = <0 0x1100b000 0 0x90>, <0 0x11000280 0 0x80>; interrupts = ; + clock-div = <2>; clocks = <&topckgen CLK_TOP_I2C2>, <&topckgen CLK_TOP_APDMA>; clock-names = "main", "dma"; diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index ec8dfb3d1c6d..a356db5fcc5f 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -47,7 +47,6 @@ key-volume-down { }; &i2c0 { - clock-div = <2>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; @@ -156,7 +155,6 @@ cam-pwdn-hog { }; &i2c2 { - clock-div = <2>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; status = "okay"; From 2561c7d5d497b988deccc36fe5eac7fd50b937f8 Mon Sep 17 00:00:00 2001 From: Val Packett Date: Wed, 4 Dec 2024 16:05:07 -0300 Subject: [PATCH 11/71] arm64: dts: mediatek: mt8516: reserve 192 KiB for TF-A The Android DTB for the related MT8167 reserves 0x30000. This is likely correct for MT8516 Android devices as well, and there's never any harm in reserving 64KiB more. Fixes: 5236347bde42 ("arm64: dts: mediatek: add dtsi for MT8516") Signed-off-by: Val Packett Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241204190524.21862-5-val@packett.cool Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index dd17d8a88c19..e30623ebac0e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -144,10 +144,10 @@ reserved-memory { #size-cells = <2>; ranges; - /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ bl31_secmon_reserved: secmon@43000000 { no-map; - reg = <0 0x43000000 0 0x20000>; + reg = <0 0x43000000 0 0x30000>; }; }; From 93a680af46436780fd64f4e856a4cfa8b393be6e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 25 Oct 2024 15:56:27 +0800 Subject: [PATCH 12/71] arm64: dts: mediatek: mt8183: Disable DPI display output by default This reverts commit 377548f05bd0905db52a1d50e5b328b9b4eb049d. Most SoC dtsi files have the display output interfaces disabled by default, and only enabled on boards that utilize them. The MT8183 has it backwards: the display outputs are left enabled by default, and only disabled at the board level. Reverse the situation for the DPI output so that it follows the normal scheme. For ease of backporting the DSI output is handled in a separate patch. Fixes: 009d855a26fd ("arm64: dts: mt8183: add dpi node to mt8183") Fixes: 377548f05bd0 ("arm64: dts: mediatek: mt8183-kukui: Disable DPI display interface") Cc: stable@vger.kernel.org Signed-off-by: Chen-Yu Tsai Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20241025075630.3917458-1-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 5 ----- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 + 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 2828f34949ae..e1495f1900a7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -269,11 +269,6 @@ dsi_out: endpoint { }; }; -&dpi0 { - /* TODO Re-enable after DP to Type-C port muxing can be described */ - status = "disabled"; -}; - &gic { mediatek,broken-save-restore-fw; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 1afeeb1155f5..8f31fc9050ec 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1845,6 +1845,7 @@ dpi0: dpi@14015000 { <&mmsys CLK_MM_DPI_MM>, <&apmixedsys CLK_APMIXED_TVDPLL>; clock-names = "pixel", "engine", "pll"; + status = "disabled"; port { dpi_out: endpoint { }; From 26f6e91fa29a58fdc76b47f94f8f6027944a490c Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 25 Oct 2024 15:56:28 +0800 Subject: [PATCH 13/71] arm64: dts: mediatek: mt8183: Disable DSI display output by default Most SoC dtsi files have the display output interfaces disabled by default, and only enabled on boards that utilize them. The MT8183 has it backwards: the display outputs are left enabled by default, and only disabled at the board level. Reverse the situation for the DSI output so that it follows the normal scheme. For ease of backporting the DPI output is handled in a separate patch. Fixes: 88ec840270e6 ("arm64: dts: mt8183: Add dsi node") Fixes: 19b6403f1e2a ("arm64: dts: mt8183: add mt8183 pumpkin board") Cc: stable@vger.kernel.org Signed-off-by: Chen-Yu Tsai Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20241025075630.3917458-2-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 4 ---- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 + 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index 61a6f66914b8..dbdee604edab 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -522,10 +522,6 @@ &scp { status = "okay"; }; -&dsi0 { - status = "disabled"; -}; - &dpi0 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&dpi_func_pins>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 8f31fc9050ec..c7008bb8a81d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1834,6 +1834,7 @@ dsi0: dsi@14014000 { resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; phys = <&mipi_tx0>; phy-names = "dphy"; + status = "disabled"; }; dpi0: dpi@14015000 { From a6d5983e40f5d5b219337569cdd269727f5a3e2e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 11 Dec 2024 13:24:20 +0800 Subject: [PATCH 14/71] arm64: dts: mediatek: mt8173-evb: Drop regulator-compatible property The "regulator-compatible" property has been deprecated since 2012 in commit 13511def87b9 ("regulator: deprecate regulator-compatible DT property"), which is so old it's not even mentioned in the converted regulator bindings YAML file. It is also not listed in the MT6397 regulator bindings. Having them present produces a whole bunch of validation errors: Unevaluated properties are not allowed ('regulator-compatible' was unexpected) Drop the "regulator-compatible" property from the board dts. The property values are the same as the node name, so everything should continue to work. Fixes: 16ea61fc5614 ("arm64: dts: mt8173-evb: Add PMIC support") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241211052427.4178367-3-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 23 --------------------- 1 file changed, 23 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index bb4671c18e3b..511c16cb1d59 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -311,7 +311,6 @@ mt6397regulator: mt6397regulator { compatible = "mediatek,mt6397-regulator"; mt6397_vpca15_reg: buck_vpca15 { - regulator-compatible = "buck_vpca15"; regulator-name = "vpca15"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1350000>; @@ -320,7 +319,6 @@ mt6397_vpca15_reg: buck_vpca15 { }; mt6397_vpca7_reg: buck_vpca7 { - regulator-compatible = "buck_vpca7"; regulator-name = "vpca7"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1350000>; @@ -329,7 +327,6 @@ mt6397_vpca7_reg: buck_vpca7 { }; mt6397_vsramca15_reg: buck_vsramca15 { - regulator-compatible = "buck_vsramca15"; regulator-name = "vsramca15"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1350000>; @@ -338,7 +335,6 @@ mt6397_vsramca15_reg: buck_vsramca15 { }; mt6397_vsramca7_reg: buck_vsramca7 { - regulator-compatible = "buck_vsramca7"; regulator-name = "vsramca7"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1350000>; @@ -347,7 +343,6 @@ mt6397_vsramca7_reg: buck_vsramca7 { }; mt6397_vcore_reg: buck_vcore { - regulator-compatible = "buck_vcore"; regulator-name = "vcore"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1350000>; @@ -356,7 +351,6 @@ mt6397_vcore_reg: buck_vcore { }; mt6397_vgpu_reg: buck_vgpu { - regulator-compatible = "buck_vgpu"; regulator-name = "vgpu"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1350000>; @@ -365,7 +359,6 @@ mt6397_vgpu_reg: buck_vgpu { }; mt6397_vdrm_reg: buck_vdrm { - regulator-compatible = "buck_vdrm"; regulator-name = "vdrm"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1400000>; @@ -374,7 +367,6 @@ mt6397_vdrm_reg: buck_vdrm { }; mt6397_vio18_reg: buck_vio18 { - regulator-compatible = "buck_vio18"; regulator-name = "vio18"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; @@ -383,19 +375,16 @@ mt6397_vio18_reg: buck_vio18 { }; mt6397_vtcxo_reg: ldo_vtcxo { - regulator-compatible = "ldo_vtcxo"; regulator-name = "vtcxo"; regulator-always-on; }; mt6397_va28_reg: ldo_va28 { - regulator-compatible = "ldo_va28"; regulator-name = "va28"; regulator-always-on; }; mt6397_vcama_reg: ldo_vcama { - regulator-compatible = "ldo_vcama"; regulator-name = "vcama"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <2800000>; @@ -403,18 +392,15 @@ mt6397_vcama_reg: ldo_vcama { }; mt6397_vio28_reg: ldo_vio28 { - regulator-compatible = "ldo_vio28"; regulator-name = "vio28"; regulator-always-on; }; mt6397_vusb_reg: ldo_vusb { - regulator-compatible = "ldo_vusb"; regulator-name = "vusb"; }; mt6397_vmc_reg: ldo_vmc { - regulator-compatible = "ldo_vmc"; regulator-name = "vmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; @@ -422,7 +408,6 @@ mt6397_vmc_reg: ldo_vmc { }; mt6397_vmch_reg: ldo_vmch { - regulator-compatible = "ldo_vmch"; regulator-name = "vmch"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; @@ -430,7 +415,6 @@ mt6397_vmch_reg: ldo_vmch { }; mt6397_vemc_3v3_reg: ldo_vemc3v3 { - regulator-compatible = "ldo_vemc3v3"; regulator-name = "vemc_3v3"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; @@ -438,7 +422,6 @@ mt6397_vemc_3v3_reg: ldo_vemc3v3 { }; mt6397_vgp1_reg: ldo_vgp1 { - regulator-compatible = "ldo_vgp1"; regulator-name = "vcamd"; regulator-min-microvolt = <1220000>; regulator-max-microvolt = <3300000>; @@ -446,7 +429,6 @@ mt6397_vgp1_reg: ldo_vgp1 { }; mt6397_vgp2_reg: ldo_vgp2 { - regulator-compatible = "ldo_vgp2"; regulator-name = "vcamio"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <3300000>; @@ -454,7 +436,6 @@ mt6397_vgp2_reg: ldo_vgp2 { }; mt6397_vgp3_reg: ldo_vgp3 { - regulator-compatible = "ldo_vgp3"; regulator-name = "vcamaf"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3300000>; @@ -462,7 +443,6 @@ mt6397_vgp3_reg: ldo_vgp3 { }; mt6397_vgp4_reg: ldo_vgp4 { - regulator-compatible = "ldo_vgp4"; regulator-name = "vgp4"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3300000>; @@ -470,7 +450,6 @@ mt6397_vgp4_reg: ldo_vgp4 { }; mt6397_vgp5_reg: ldo_vgp5 { - regulator-compatible = "ldo_vgp5"; regulator-name = "vgp5"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3000000>; @@ -478,7 +457,6 @@ mt6397_vgp5_reg: ldo_vgp5 { }; mt6397_vgp6_reg: ldo_vgp6 { - regulator-compatible = "ldo_vgp6"; regulator-name = "vgp6"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3300000>; @@ -486,7 +464,6 @@ mt6397_vgp6_reg: ldo_vgp6 { }; mt6397_vibr_reg: ldo_vibr { - regulator-compatible = "ldo_vibr"; regulator-name = "vibr"; regulator-min-microvolt = <1300000>; regulator-max-microvolt = <3300000>; From 4b907b3ea5fba240808136cc5599d14b52230b39 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 11 Dec 2024 13:24:21 +0800 Subject: [PATCH 15/71] arm64: dts: mediatek: mt8173-elm: Drop regulator-compatible property The "regulator-compatible" property has been deprecated since 2012 in commit 13511def87b9 ("regulator: deprecate regulator-compatible DT property"), which is so old it's not even mentioned in the converted regulator bindings YAML file. It is also not listed in the MT6397 regulator bindings. Having them present produces a whole bunch of validation errors: Unevaluated properties are not allowed ('regulator-compatible' was unexpected) Drop the "regulator-compatible" property from the board dts. The property values are the same as the node name, so everything should continue to work. Fixes: 689b937bedde ("arm64: dts: mediatek: add mt8173 elm and hana board") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241211052427.4178367-4-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 23 -------------------- 1 file changed, 23 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index eee64461421f..b91072f4723f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -946,7 +946,6 @@ regulator: mt6397regulator { compatible = "mediatek,mt6397-regulator"; mt6397_vpca15_reg: buck_vpca15 { - regulator-compatible = "buck_vpca15"; regulator-name = "vpca15"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1350000>; @@ -956,7 +955,6 @@ mt6397_vpca15_reg: buck_vpca15 { }; mt6397_vpca7_reg: buck_vpca7 { - regulator-compatible = "buck_vpca7"; regulator-name = "vpca7"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1350000>; @@ -966,7 +964,6 @@ mt6397_vpca7_reg: buck_vpca7 { }; mt6397_vsramca15_reg: buck_vsramca15 { - regulator-compatible = "buck_vsramca15"; regulator-name = "vsramca15"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1350000>; @@ -975,7 +972,6 @@ mt6397_vsramca15_reg: buck_vsramca15 { }; mt6397_vsramca7_reg: buck_vsramca7 { - regulator-compatible = "buck_vsramca7"; regulator-name = "vsramca7"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1350000>; @@ -984,7 +980,6 @@ mt6397_vsramca7_reg: buck_vsramca7 { }; mt6397_vcore_reg: buck_vcore { - regulator-compatible = "buck_vcore"; regulator-name = "vcore"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1350000>; @@ -993,7 +988,6 @@ mt6397_vcore_reg: buck_vcore { }; mt6397_vgpu_reg: buck_vgpu { - regulator-compatible = "buck_vgpu"; regulator-name = "vgpu"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1350000>; @@ -1002,7 +996,6 @@ mt6397_vgpu_reg: buck_vgpu { }; mt6397_vdrm_reg: buck_vdrm { - regulator-compatible = "buck_vdrm"; regulator-name = "vdrm"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1400000>; @@ -1011,7 +1004,6 @@ mt6397_vdrm_reg: buck_vdrm { }; mt6397_vio18_reg: buck_vio18 { - regulator-compatible = "buck_vio18"; regulator-name = "vio18"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; @@ -1020,18 +1012,15 @@ mt6397_vio18_reg: buck_vio18 { }; mt6397_vtcxo_reg: ldo_vtcxo { - regulator-compatible = "ldo_vtcxo"; regulator-name = "vtcxo"; regulator-always-on; }; mt6397_va28_reg: ldo_va28 { - regulator-compatible = "ldo_va28"; regulator-name = "va28"; }; mt6397_vcama_reg: ldo_vcama { - regulator-compatible = "ldo_vcama"; regulator-name = "vcama"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -1039,18 +1028,15 @@ mt6397_vcama_reg: ldo_vcama { }; mt6397_vio28_reg: ldo_vio28 { - regulator-compatible = "ldo_vio28"; regulator-name = "vio28"; regulator-always-on; }; mt6397_vusb_reg: ldo_vusb { - regulator-compatible = "ldo_vusb"; regulator-name = "vusb"; }; mt6397_vmc_reg: ldo_vmc { - regulator-compatible = "ldo_vmc"; regulator-name = "vmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; @@ -1058,7 +1044,6 @@ mt6397_vmc_reg: ldo_vmc { }; mt6397_vmch_reg: ldo_vmch { - regulator-compatible = "ldo_vmch"; regulator-name = "vmch"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; @@ -1066,7 +1051,6 @@ mt6397_vmch_reg: ldo_vmch { }; mt6397_vemc_3v3_reg: ldo_vemc3v3 { - regulator-compatible = "ldo_vemc3v3"; regulator-name = "vemc_3v3"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; @@ -1074,7 +1058,6 @@ mt6397_vemc_3v3_reg: ldo_vemc3v3 { }; mt6397_vgp1_reg: ldo_vgp1 { - regulator-compatible = "ldo_vgp1"; regulator-name = "vcamd"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -1082,7 +1065,6 @@ mt6397_vgp1_reg: ldo_vgp1 { }; mt6397_vgp2_reg: ldo_vgp2 { - regulator-compatible = "ldo_vgp2"; regulator-name = "vcamio"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -1090,7 +1072,6 @@ mt6397_vgp2_reg: ldo_vgp2 { }; mt6397_vgp3_reg: ldo_vgp3 { - regulator-compatible = "ldo_vgp3"; regulator-name = "vcamaf"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -1098,7 +1079,6 @@ mt6397_vgp3_reg: ldo_vgp3 { }; mt6397_vgp4_reg: ldo_vgp4 { - regulator-compatible = "ldo_vgp4"; regulator-name = "vgp4"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3300000>; @@ -1106,7 +1086,6 @@ mt6397_vgp4_reg: ldo_vgp4 { }; mt6397_vgp5_reg: ldo_vgp5 { - regulator-compatible = "ldo_vgp5"; regulator-name = "vgp5"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3000000>; @@ -1114,7 +1093,6 @@ mt6397_vgp5_reg: ldo_vgp5 { }; mt6397_vgp6_reg: ldo_vgp6 { - regulator-compatible = "ldo_vgp6"; regulator-name = "vgp6"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -1123,7 +1101,6 @@ mt6397_vgp6_reg: ldo_vgp6 { }; mt6397_vibr_reg: ldo_vibr { - regulator-compatible = "ldo_vibr"; regulator-name = "vibr"; regulator-min-microvolt = <1300000>; regulator-max-microvolt = <3300000>; From d1fb968551c8688652b8b817bb081fdc9c25cd48 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 11 Dec 2024 13:24:22 +0800 Subject: [PATCH 16/71] arm64: dts: mediatek: mt8192-asurada: Drop regulator-compatible property The "regulator-compatible" property has been deprecated since 2012 in commit 13511def87b9 ("regulator: deprecate regulator-compatible DT property"), which is so old it's not even mentioned in the converted regulator bindings YAML file. It should not have been used for new submissions such as the MT6315. Drop the "regulator-compatible" property from the board dts. The property values are the same as the node name, so everything should continue to work. Fixes: 3183cb62b033 ("arm64: dts: mediatek: asurada: Add SPMI regulators") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241211052427.4178367-5-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 8dda8b63765b..dd0d07fbe61a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -1418,7 +1418,6 @@ mt6315_6: pmic@6 { regulators { mt6315_6_vbuck1: vbuck1 { - regulator-compatible = "vbuck1"; regulator-name = "Vbcpu"; regulator-min-microvolt = <400000>; regulator-max-microvolt = <1193750>; @@ -1428,7 +1427,6 @@ mt6315_6_vbuck1: vbuck1 { }; mt6315_6_vbuck3: vbuck3 { - regulator-compatible = "vbuck3"; regulator-name = "Vlcpu"; regulator-min-microvolt = <400000>; regulator-max-microvolt = <1193750>; @@ -1445,7 +1443,6 @@ mt6315_7: pmic@7 { regulators { mt6315_7_vbuck1: vbuck1 { - regulator-compatible = "vbuck1"; regulator-name = "Vgpu"; regulator-min-microvolt = <400000>; regulator-max-microvolt = <800000>; From 4dbaa5d5def2c49e44efaa5e796c23d9b904be09 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 11 Dec 2024 13:24:23 +0800 Subject: [PATCH 17/71] arm64: dts: mediatek: mt8195-cherry: Drop regulator-compatible property The "regulator-compatible" property has been deprecated since 2012 in commit 13511def87b9 ("regulator: deprecate regulator-compatible DT property"), which is so old it's not even mentioned in the converted regulator bindings YAML file. It should not have been used for new submissions such as the MT6315. Drop the "regulator-compatible" property from the board dts. The property values are the same as the node name, so everything should continue to work. Fixes: 260c04d425eb ("arm64: dts: mediatek: cherry: Enable MT6315 regulators on SPMI bus") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241211052427.4178367-6-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 2c7b2223ee76..5056e07399e2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -1285,7 +1285,6 @@ mt6315@6 { regulators { mt6315_6_vbuck1: vbuck1 { - regulator-compatible = "vbuck1"; regulator-name = "Vbcpu"; regulator-min-microvolt = <400000>; regulator-max-microvolt = <1193750>; @@ -1303,7 +1302,6 @@ mt6315@7 { regulators { mt6315_7_vbuck1: vbuck1 { - regulator-compatible = "vbuck1"; regulator-name = "Vgpu"; regulator-min-microvolt = <400000>; regulator-max-microvolt = <1193750>; From 2a8af9b95f504260a6d8200a11f0ae5c90e9f787 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 11 Dec 2024 13:24:24 +0800 Subject: [PATCH 18/71] arm64: dts: mediatek: mt8195-demo: Drop regulator-compatible property The "regulator-compatible" property has been deprecated since 2012 in commit 13511def87b9 ("regulator: deprecate regulator-compatible DT property"), which is so old it's not even mentioned in the converted regulator bindings YAML file. It is also not listed in the MT6360 regulator and charger bindings. Drop the "regulator-compatible" property from the board dts. The MT6360 bindings actually require the lowercase name, so with the property present the regulators were likely not actually working. Fixes: 6147314aeedc ("arm64: dts: mediatek: Add device-tree for MT8195 Demo board") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241211052427.4178367-7-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index 31d424b8fc7c..bfb75296795c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -137,7 +137,6 @@ charger { richtek,vinovp-microvolt = <14500000>; otg_vbus_regulator: usb-otg-vbus-regulator { - regulator-compatible = "usb-otg-vbus"; regulator-name = "usb-otg-vbus"; regulator-min-microvolt = <4425000>; regulator-max-microvolt = <5825000>; @@ -149,7 +148,6 @@ regulator { LDO_VIN3-supply = <&mt6360_buck2>; mt6360_buck1: buck1 { - regulator-compatible = "BUCK1"; regulator-name = "mt6360,buck1"; regulator-min-microvolt = <300000>; regulator-max-microvolt = <1300000>; @@ -160,7 +158,6 @@ MT6360_OPMODE_LP }; mt6360_buck2: buck2 { - regulator-compatible = "BUCK2"; regulator-name = "mt6360,buck2"; regulator-min-microvolt = <300000>; regulator-max-microvolt = <1300000>; @@ -171,7 +168,6 @@ MT6360_OPMODE_LP }; mt6360_ldo1: ldo1 { - regulator-compatible = "LDO1"; regulator-name = "mt6360,ldo1"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3600000>; @@ -180,7 +176,6 @@ mt6360_ldo1: ldo1 { }; mt6360_ldo2: ldo2 { - regulator-compatible = "LDO2"; regulator-name = "mt6360,ldo2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3600000>; @@ -189,7 +184,6 @@ mt6360_ldo2: ldo2 { }; mt6360_ldo3: ldo3 { - regulator-compatible = "LDO3"; regulator-name = "mt6360,ldo3"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3600000>; @@ -198,7 +192,6 @@ mt6360_ldo3: ldo3 { }; mt6360_ldo5: ldo5 { - regulator-compatible = "LDO5"; regulator-name = "mt6360,ldo5"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3600000>; @@ -207,7 +200,6 @@ mt6360_ldo5: ldo5 { }; mt6360_ldo6: ldo6 { - regulator-compatible = "LDO6"; regulator-name = "mt6360,ldo6"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <2100000>; @@ -216,7 +208,6 @@ mt6360_ldo6: ldo6 { }; mt6360_ldo7: ldo7 { - regulator-compatible = "LDO7"; regulator-name = "mt6360,ldo7"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <2100000>; From ab60442f26b15ba69b210974722a851ed03188ff Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 11 Dec 2024 13:24:25 +0800 Subject: [PATCH 19/71] arm64: dts: medaitek: mt8395-nio-12l: Drop regulator-compatible property The "regulator-compatible" property has been deprecated since 2012 in commit 13511def87b9 ("regulator: deprecate regulator-compatible DT property"), which is so old it's not even mentioned in the converted regulator bindings YAML file. It should not have been used for new submissions such as the MT6315. Drop the "regulator-compatible" property from the board dts. The property values are the same as the node name, so everything should continue to work. Fixes: 96564b1e2ea4 ("arm64: dts: mediatek: Introduce the MT8395 Radxa NIO 12L board") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241211052427.4178367-8-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index 14ec970c4e49..41dc34837b02 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -812,7 +812,6 @@ mt6315_6: pmic@6 { regulators { mt6315_6_vbuck1: vbuck1 { - regulator-compatible = "vbuck1"; regulator-name = "Vbcpu"; regulator-min-microvolt = <300000>; regulator-max-microvolt = <1193750>; @@ -829,7 +828,6 @@ mt6315_7: pmic@7 { regulators { mt6315_7_vbuck1: vbuck1 { - regulator-compatible = "vbuck1"; regulator-name = "Vgpu"; regulator-min-microvolt = <300000>; regulator-max-microvolt = <1193750>; From b99bf07c2c8b3c85c1935ddca2a73bc686f8d847 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 11 Dec 2024 13:24:26 +0800 Subject: [PATCH 20/71] arm64: dts: mediatek: mt8395-genio-1200-evk: Drop regulator-compatible property The "regulator-compatible" property has been deprecated since 2012 in commit 13511def87b9 ("regulator: deprecate regulator-compatible DT property"), which is so old it's not even mentioned in the converted regulator bindings YAML file. It should not have been used for new submissions such as the MT6315. Drop the "regulator-compatible" property from the board dts. The property values are the same as the node name, so everything should continue to work. Fixes: f2b543a191b6 ("arm64: dts: mediatek: add device-tree for Genio 1200 EVK board") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241211052427.4178367-9-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts index 5f16fb820580..5950194c9ccb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts @@ -835,7 +835,6 @@ mt6315_6: pmic@6 { regulators { mt6315_6_vbuck1: vbuck1 { - regulator-compatible = "vbuck1"; regulator-name = "Vbcpu"; regulator-min-microvolt = <300000>; regulator-max-microvolt = <1193750>; @@ -852,7 +851,6 @@ mt6315_7: pmic@7 { regulators { mt6315_7_vbuck1: vbuck1 { - regulator-compatible = "vbuck1"; regulator-name = "Vgpu"; regulator-min-microvolt = <546000>; regulator-max-microvolt = <787000>; From beb06b727194f68b0a4b5183e50c88265ce185af Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 10 Dec 2024 17:26:12 +0800 Subject: [PATCH 21/71] arm64: dts: mediatek: mt8173-elm: Fix MT6397 PMIC sub-node names The MT6397 PMIC bindings specify exact names for its sub-nodes. The names used in the current dts don't match, causing a validation error. Fix up the names. Also drop the label for the regulators node, since any reference should be against the individual regulator sub-nodes. Fixes: 689b937bedde ("arm64: dts: mediatek: add mt8173 elm and hana board") Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20241210092614.3951748-1-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index b91072f4723f..b5d4b5baf478 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -931,7 +931,7 @@ pmic: pmic { interrupt-controller; #interrupt-cells = <2>; - clock: mt6397clock { + clock: clocks { compatible = "mediatek,mt6397-clk"; #clock-cells = <1>; }; @@ -942,7 +942,7 @@ pio6397: pinctrl { #gpio-cells = <2>; }; - regulator: mt6397regulator { + regulators { compatible = "mediatek,mt6397-regulator"; mt6397_vpca15_reg: buck_vpca15 { @@ -1108,7 +1108,7 @@ mt6397_vibr_reg: ldo_vibr { }; }; - rtc: mt6397rtc { + rtc: rtc { compatible = "mediatek,mt6397-rtc"; }; }; From 9545ba142865b9099d43c972b9ebcf463606499a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 10 Dec 2024 17:26:13 +0800 Subject: [PATCH 22/71] arm64: dts: mediatek: mt8173-evb: Fix MT6397 PMIC sub-node names The MT6397 PMIC bindings specify exact names for its sub-nodes. The names used in the current dts don't match, causing a validation error. Fix up the names. Also drop the label for the regulators node, since any reference should be against the individual regulator sub-nodes. Fixes: 16ea61fc5614 ("arm64: dts: mt8173-evb: Add PMIC support") Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20241210092614.3951748-2-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 511c16cb1d59..9fffed0ef4bf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -307,7 +307,7 @@ pmic: pmic { interrupt-controller; #interrupt-cells = <2>; - mt6397regulator: mt6397regulator { + regulators { compatible = "mediatek,mt6397-regulator"; mt6397_vpca15_reg: buck_vpca15 { From 9bc8353be720ca1f9cb6e03825929bc172e1157d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Tue, 10 Dec 2024 17:54:28 -0300 Subject: [PATCH 23/71] arm64: dts: mt6359: Add #sound-dai-cells property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT6359 provides digital audio interfaces. Add a #sound-dai-cells property for it to allow pointing to it from dai-link nodes. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20241210-genio700-audio-output-v2-1-c50886ae0be2@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6359.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi index 8e1b8c85c6ed..150ad84d5d2b 100644 --- a/arch/arm64/boot/dts/mediatek/mt6359.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi @@ -8,6 +8,7 @@ pmic: pmic { compatible = "mediatek,mt6359"; interrupt-controller; #interrupt-cells = <2>; + #sound-dai-cells = <1>; pmic_adc: adc { compatible = "mediatek,mt6359-auxadc"; From b8457716eeee45ed5cb6b8fdc5a5b459f7ebe819 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Tue, 10 Dec 2024 17:54:29 -0300 Subject: [PATCH 24/71] arm64: dts: mediatek: mt8390-genio-700-evk: Add sound output support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Describe all the components to get sound output working on the two audio jacks, Earphone and Speaker, present on the Genio 700 EVK board with the audio DSP enabled. Co-developed-by: Aary Patil Signed-off-by: Aary Patil Co-developed-by: Suhrid Subramaniam Signed-off-by: Suhrid Subramaniam Co-developed-by: parkeryang Signed-off-by: parkeryang Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241210-genio700-audio-output-v2-2-c50886ae0be2@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8390-genio-700-evk.dts | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts index 13f2e0e3fa8a..04e4a2f73799 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts @@ -93,6 +93,24 @@ vpu_mem: memory@57000000 { compatible = "shared-dma-pool"; reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ }; + + adsp_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0xf00000>; + no-map; + }; + + afe_dma_mem: memory@60f00000 { + compatible = "shared-dma-pool"; + reg = <0 0x60f00000 0 0x100000>; + no-map; + }; + + adsp_dma_mem: memory@61000000 { + compatible = "shared-dma-pool"; + reg = <0 0x61000000 0 0x100000>; + no-map; + }; }; common_fixed_5v: regulator-0 { @@ -210,6 +228,16 @@ usb_p2_vbus: regulator-9 { }; }; +&adsp { + memory-region = <&adsp_dma_mem>, <&adsp_mem>; + status = "okay"; +}; + +&afe { + memory-region = <&afe_dma_mem>; + status = "okay"; +}; + &gpu { mali-supply = <&mt6359_vproc2_buck_reg>; status = "okay"; @@ -932,6 +960,26 @@ &scp { status = "okay"; }; +&sound { + compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb"; + model = "mt8390-evk"; + pinctrl-names = "default"; + pinctrl-0 = <&audio_default_pins>; + audio-routing = + "Headphone", "Headphone L", + "Headphone", "Headphone R"; + mediatek,adsp = <&adsp>; + status = "okay"; + + dai-link-0 { + link-name = "DL_SRC_BE"; + + codec { + sound-dai = <&pmic 0>; + }; + }; +}; + &spi2 { pinctrl-0 = <&spi2_pins>; pinctrl-names = "default"; From d49df8e014ee48fe81078c9c24c6b7c2b9c21c27 Mon Sep 17 00:00:00 2001 From: Zhengqiao Xia Date: Thu, 12 Dec 2024 14:20:43 +0800 Subject: [PATCH 25/71] dt-bindings: arm: mediatek: Add MT8186 Chinchou Chromebook Add an entry for the MT8186 based Chinchou Chromebook, also known as the ASUS Chromebook CZ12 Flip (CZ1204F) and CZ12(CZ1204C). Signed-off-by: Zhengqiao Xia Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241212062046.22509-2-xiazhengqiao@huaqin.corp-partner.google.com Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/arm/mediatek.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index f8692ad455e7..da6af39caa9b 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -239,6 +239,34 @@ properties: - enum: - mediatek,mt8183-pumpkin - const: mediatek,mt8183 + - description: Google Chinchou (Asus Chromebook CZ1104CM2A/CZ1204CM2A) + items: + - const: google,chinchou-sku0 + - const: google,chinchou-sku2 + - const: google,chinchou-sku4 + - const: google,chinchou-sku5 + - const: google,chinchou + - const: mediatek,mt8186 + - description: Google Chinchou (Asus Chromebook CZ1104FM2A/CZ1204FM2A/CZ1104CM2A/CZ1204CM2A) + items: + - const: google,chinchou-sku1 + - const: google,chinchou-sku3 + - const: google,chinchou-sku6 + - const: google,chinchou-sku7 + - const: google,chinchou-sku17 + - const: google,chinchou-sku20 + - const: google,chinchou-sku22 + - const: google,chinchou-sku23 + - const: google,chinchou + - const: mediatek,mt8186 + - description: Google Chinchou360 (Asus Chromebook CZ1104FM2A/CZ1204FM2A Flip) + items: + - const: google,chinchou-sku16 + - const: google,chinchou-sku18 + - const: google,chinchou-sku19 + - const: google,chinchou-sku21 + - const: google,chinchou + - const: mediatek,mt8186 - description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868)) items: - const: google,steelix-sku393219 From 5fbe5332623c0b3fe95b940f9a76cb0e09691395 Mon Sep 17 00:00:00 2001 From: Zhengqiao Xia Date: Thu, 12 Dec 2024 14:20:44 +0800 Subject: [PATCH 26/71] arm64: dts: mediatek: Add MT8186 Chinchou Chromebooks MT8186 chinchou, known as ASUS Chromebook CZ12 Flip (CZ1204F) and CZ12(CZ1204C), is a MT8186 based laptop. It is based on the "corsola" design.It includes chinchou and chinchou360, including LTE, stylus, touchscreen combinations. Signed-off-by: Zhengqiao Xia Link: https://lore.kernel.org/r/20241212062046.22509-3-xiazhengqiao@huaqin.corp-partner.google.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 3 + .../mediatek/mt8186-corsola-chinchou-sku0.dts | 18 + .../mediatek/mt8186-corsola-chinchou-sku1.dts | 35 ++ .../mt8186-corsola-chinchou-sku16.dts | 29 ++ .../dts/mediatek/mt8186-corsola-chinchou.dtsi | 321 ++++++++++++++++++ 5 files changed, 406 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku0.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku1.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku16.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 1a493052f4e4..08dbea48eaea 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -55,6 +55,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku0.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku16.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393216.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393217.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393218.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku0.dts new file mode 100644 index 000000000000..5d012bc4ff0d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku0.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-chinchou.dtsi" + +/ { + model = "Google chinchou CZ1104CM2A/CZ1204CM2A"; + compatible = "google,chinchou-sku0", "google,chinchou-sku2", + "google,chinchou-sku4", "google,chinchou-sku5", + "google,chinchou", "mediatek,mt8186"; +}; + +&gpio_keys { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku1.dts new file mode 100644 index 000000000000..9d6e62af6944 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku1.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-chinchou.dtsi" + +/ { + model = "Google chinchou CZ1104FM2A/CZ1204FM2A/CZ1104CM2A/CZ1204CM2A"; + compatible = "google,chinchou-sku1", "google,chinchou-sku3", + "google,chinchou-sku6", "google,chinchou-sku7", + "google,chinchou-sku17", "google,chinchou-sku20", + "google,chinchou-sku22", "google,chinchou-sku23", + "google,chinchou", "mediatek,mt8186"; +}; + +&gpio_keys { + status = "disabled"; +}; + +&i2c1 { + i2c-scl-internal-delay-ns = <10000>; + + touchscreen: touchscreen@41 { + compatible = "ilitek,ili2901"; + reg = <0x41>; + interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>; + vccio-supply = <&pp1800_tchscr_report_disable>; + vcc33-supply = <&pp3300_z2>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku16.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku16.dts new file mode 100644 index 000000000000..eb377de1fcde --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku16.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-chinchou.dtsi" + +/ { + model = "Google chinchou CZ1104FM2A/CZ1204FM2A"; + compatible = "google,chinchou-sku16", "google,chinchou-sku18", + "google,chinchou-sku19", "google,chinchou-sku21", + "google,chinchou", "mediatek,mt8186"; +}; + +&i2c1 { + i2c-scl-internal-delay-ns = <10000>; + + touchscreen: touchscreen@41 { + compatible = "ilitek,ili2901"; + reg = <0x41>; + interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>; + vccio-supply = <&pp1800_tchscr_report_disable>; + vcc33-supply = <&pp3300_z2>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou.dtsi new file mode 100644 index 000000000000..800792157021 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou.dtsi @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola.dtsi" + +/ { + /delete-node/ speaker-codec; + + pp1000_edpbrdg: regulator-pp1000-edpbrdg { + compatible = "regulator-fixed"; + regulator-name = "pp1000_edpbrdg"; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp1000_edpbrdg>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 29 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_z2>; + }; + + pp1800_edpbrdg_dx: regulator-pp1800-edpbrdg-dx { + compatible = "regulator-fixed"; + regulator-name = "pp1800_edpbrdg_dx"; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp1800_edpbrdg>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 30 GPIO_ACTIVE_HIGH>; + vin-supply = <&mt6366_vio18_reg>; + }; + + pp3300_edp_dx: regulator-pp3300-edp-dx { + compatible = "regulator-fixed"; + regulator-name = "pp3300_edp_dx"; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_edpbrdg>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 31 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_z2>; + }; + + pp1800_tchscr_report_disable: regulator-pp1800-tchscr-report-disable { + compatible = "regulator-fixed"; + regulator-name = "pp1800_tchscr_report_disable"; + pinctrl-names = "default"; + regulator-boot-on; + pinctrl-0 = <&touch_pin_report>; + gpio = <&pio 37 GPIO_ACTIVE_LOW>; + }; +}; + +&dsi_out { + remote-endpoint = <&anx7625_in>; +}; + +&i2c0 { + clock-frequency = <400000>; + + anx_bridge: anx7625@58 { + compatible = "analogix,anx7625"; + reg = <0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&anx7625_pins>; + enable-gpios = <&pio 96 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>; + vdd10-supply = <&pp1000_edpbrdg>; + vdd18-supply = <&pp1800_edpbrdg_dx>; + vdd33-supply = <&pp3300_edp_dx>; + analogix,lane0-swing = /bits/ 8 <0x70 0x30>; + analogix,lane1-swing = /bits/ 8 <0x70 0x30>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + anx7625_in: endpoint { + remote-endpoint = <&dsi_out>; + data-lanes = <0 1 2 3>; + }; + }; + + port@1 { + reg = <1>; + + anx7625_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + aux-bus { + panel: panel { + compatible = "edp-panel"; + power-supply = <&pp3300_disp_x>; + backlight = <&backlight_lcd0>; + + port { + panel_in: endpoint { + remote-endpoint = <&anx7625_out>; + }; + }; + }; + }; + }; +}; + +&i2c2 { + /delete-node/ trackpad@15; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>; + post-power-on-delay-ms = <10>; + hid-descr-addr = <0x0001>; + vdd-supply = <&pp3300_s3>; + wakeup-source; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + /delete-node/ codec@1a; + + rt5650: rt5650@1a { + compatible = "realtek,rt5650"; + reg = <0x1a>; + avdd-supply = <&mt6366_vio18_reg>; + cpvdd-supply = <&mt6366_vio18_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&speaker_codec_pins_default>; + cbj-sleeve-gpios = <&pio 150 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&pio>; + interrupts = <17 IRQ_TYPE_EDGE_BOTH>; + #sound-dai-cells = <0>; + realtek,dmic1-data-pin = <2>; + realtek,jd-mode = <2>; + }; +}; + +&i2c_tunnel { + /delete-node/ sbs-battery@b; + + battery: sbs-battery@f { + compatible = "sbs,sbs-battery"; + reg = <0xf>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <1>; + }; +}; + +&keyboard_controller { + keypad,num-columns = <15>; + + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + MATRIX_KEY(0x00, 0x01, 0) /* T11 */ + MATRIX_KEY(0x01, 0x05, 0) /* T12 */ + >; + + linux,keymap = < + CROS_STD_MAIN_KEYMAP + MATRIX_KEY(0x00, 0x02, KEY_BACK) /* T1 */ + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) /* T2 */ + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) /* T3 */ + MATRIX_KEY(0x01, 0x02, KEY_SCALE) /* T4 */ + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) /* T5 */ + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) /* T6 */ + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) /* T7 */ + MATRIX_KEY(0x02, 0x09, KEY_MUTE) /* T8 */ + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) /* T9 */ + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) /* T10 */ + MATRIX_KEY(0x00, 0x01, KEY_MICMUTE) /* T11 */ + MATRIX_KEY(0x01, 0x05, KEY_CONTROLPANEL) /* T12 */ + MATRIX_KEY(0x03, 0x05, KEY_PREVIOUSSONG) /* T13 */ + MATRIX_KEY(0x00, 0x09, KEY_PLAYPAUSE) /* T14 */ + MATRIX_KEY(0x00, 0x0b, KEY_NEXTSONG) /* T15 */ + MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA) /* Search*/ + MATRIX_KEY(0x01, 0x0e, KEY_LEFTCTRL) /* Left Control*/ + MATRIX_KEY(0x06, 0x0d, KEY_LEFTALT) /* Left ALT*/ + MATRIX_KEY(0x03, 0x0e, KEY_RIGHTCTRL) /* Right Control*/ + MATRIX_KEY(0x06, 0x0a, KEY_BACKSLASH) /* BACKSLASH*/ + >; +}; + +&mmc1_pins_default { + pins-clk { + drive-strength = <8>; + }; + + pins-cmd-dat { + drive-strength = <8>; + }; +}; + +&mmc1_pins_uhs { + pins-clk { + drive-strength = <8>; + }; + + pins-cmd-dat { + drive-strength = <8>; + }; +}; + +&pen_insert { + wakeup-event-action = ; +}; + +&pio { + anx7625_pins: anx7625-pins { + pins-int { + pinmux = ; + input-enable; + bias-disable; + }; + + pins-reset { + pinmux = ; + output-low; + }; + + pins-power-en { + pinmux = ; + output-low; + }; + }; + + en_pp1000_edpbrdg: pp1000-edpbrdg-en-pins { + pins-vreg-en { + pinmux = ; + output-low; + }; + }; + + en_pp1800_edpbrdg: pp1800-edpbrdg-en-pins { + pins-vreg-en { + pinmux = ; + output-low; + }; + }; + + en_pp3300_edpbrdg: pp3300-edpbrdg-en-pins { + pins-vreg-en { + pinmux = ; + output-low; + }; + }; + + touch_pin_report: pin-report-pins { + pins-touch-en { + pinmux = ; + output-low; + }; + }; +}; + +&sound { + compatible = "mediatek,mt8186-mt6366-rt5650-sound"; + model = "mt8186_rt5650"; + mediatek,adsp = <&adsp>; + + audio-routing = + "Headphone", "HPOL", + "Headphone", "HPOR", + "IN1P", "Headset Mic", + "IN1N", "Headset Mic", + "Speakers", "SPOL", + "Speakers", "SPOR", + "HDMI1", "TX"; + + hs-playback-dai-link { + codec { + sound-dai = <&rt5650>; + }; + }; + + hs-capture-dai-link { + codec { + sound-dai = <&rt5650>; + }; + }; + + spk-share-dai-link { + }; + + spk-hdmi-playback-dai-link { + codec { + sound-dai = <&it6505dptx>; + }; + }; +}; + +&touchscreen_pins { + /delete-node/ pins-report-sw; +}; + +&wifi_enable_pin { + pins-wifi-enable { + pinmux = ; + }; +}; + +&wifi_pwrseq { + reset-gpios = <&pio 51 GPIO_ACTIVE_LOW>; +}; From 79ef2aae9fde746217c82a3c659e73fa2583774d Mon Sep 17 00:00:00 2001 From: Zhengqiao Xia Date: Thu, 12 Dec 2024 14:20:45 +0800 Subject: [PATCH 27/71] arm64: dts: mediatek: Add extcon node for DP bridge Add extcon node for DP bridge to make the display work properly. Signed-off-by: Zhengqiao Xia Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241212062046.22509-4-xiazhengqiao@huaqin.corp-partner.google.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi index cfcc7909dfe6..e324e3fd347e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi @@ -424,6 +424,7 @@ it6505dptx: dp-bridge@5c { ovdd-supply = <&mt6366_vsim2_reg>; pwr18-supply = <&pp1800_dpbrdg_dx>; reset-gpios = <&pio 177 GPIO_ACTIVE_LOW>; + extcon = <&usbc_extcon>; ports { #address-cells = <1>; @@ -1656,6 +1657,11 @@ usb_c1: connector@1 { try-power-role = "source"; }; }; + + usbc_extcon: extcon0 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <0>; + }; }; }; From 0f9a4f02a878dc330d2654eaecb3698aa4ff4fcb Mon Sep 17 00:00:00 2001 From: Zhengqiao Xia Date: Thu, 12 Dec 2024 14:20:46 +0800 Subject: [PATCH 28/71] arm64: dts: mediatek: Modify audio codec name for pmic change `codec` in pmic (in mt8186-corsola.dtsi) to `audio-codec` Signed-off-by: Zhengqiao Xia Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241212062046.22509-5-xiazhengqiao@huaqin.corp-partner.google.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi index e324e3fd347e..cebb134331fb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi @@ -1276,7 +1276,7 @@ pmic { interrupts-extended = <&pio 201 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; - mt6366codec: codec { + mt6366codec: audio-codec { compatible = "mediatek,mt6366-sound", "mediatek,mt6358-sound"; Avdd-supply = <&mt6366_vaud28_reg>; mediatek,dmic-mode = <1>; /* one-wire */ From 5ec5dc73c5ac0c6e06803dc3b5aea4493e856568 Mon Sep 17 00:00:00 2001 From: Hsin-Te Yuan Date: Fri, 13 Dec 2024 05:27:47 +0000 Subject: [PATCH 29/71] arm64: dts: mediatek: mt8183: kenzo: Support second source touchscreen Some kenzo devices use second source touchscreen. Fixes: 0a9cefe21aec ("arm64: dts: mt8183: Add kukui-jacuzzi-kenzo board") Signed-off-by: Hsin-Te Yuan Link: https://lore.kernel.org/r/20241213-touchscreen-v3-1-7c1f670913f9@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts index e8241587949b..561770fcf69e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts @@ -12,3 +12,18 @@ / { chassis-type = "laptop"; compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183"; }; + +&i2c0 { + touchscreen@40 { + compatible = "hid-over-i2c"; + reg = <0x40>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + + interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <70>; + hid-descr-addr = <0x0001>; + }; +}; From 9594935260d76bffe200bea6cfab6ba0752e70d9 Mon Sep 17 00:00:00 2001 From: Hsin-Te Yuan Date: Fri, 13 Dec 2024 05:27:48 +0000 Subject: [PATCH 30/71] arm64: dts: mediatek: mt8183: willow: Support second source touchscreen Some willow devices use second source touchscreen. Fixes: f006bcf1c972 ("arm64: dts: mt8183: Add kukui-jacuzzi-willow board") Signed-off-by: Hsin-Te Yuan Link: https://lore.kernel.org/r/20241213-touchscreen-v3-2-7c1f670913f9@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi index 76d33540166f..c942e461a177 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi @@ -6,6 +6,21 @@ /dts-v1/; #include "mt8183-kukui-jacuzzi.dtsi" +&i2c0 { + touchscreen@40 { + compatible = "hid-over-i2c"; + reg = <0x40>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + + interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <70>; + hid-descr-addr = <0x0001>; + }; +}; + &i2c2 { trackpad@2c { compatible = "hid-over-i2c"; From 50e7592cb696b3767d2186b0d51bb37a2fddbb67 Mon Sep 17 00:00:00 2001 From: Hsin-Te Yuan Date: Fri, 13 Dec 2024 09:29:22 +0000 Subject: [PATCH 31/71] arm64: dts: mediatek: mt8188: Add GPU speed bin NVMEM cells On the MT8188, the chip is binned for different GPU voltages at the highest OPPs. The binning value is stored in the efuse. Add the NVMEM cell, and tie it to the GPU. Signed-off-by: Hsin-Te Yuan Link: https://lore.kernel.org/r/20241213-speedbin-v1-1-a0053ead9477@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index faccc7f16259..981853cd0192 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2125,6 +2125,11 @@ lvts_efuse_data1: lvts1-calib@1ac { reg = <0x1ac 0x40>; }; + gpu_speedbin: gpu-speedbin@581 { + reg = <0x581 0x1>; + bits = <0 3>; + }; + socinfo-data1@7a0 { reg = <0x7a0 0x4>; }; @@ -2143,6 +2148,8 @@ gpu: gpu@13000000 { , ; interrupt-names = "job", "mmu", "gpu"; + nvmem-cells = <&gpu_speedbin>; + nvmem-cell-names = "speed-bin"; operating-points-v2 = <&gpu_opp_table>; power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>, <&spm MT8188_POWER_DOMAIN_MFG3>, From 312189ebb802a0242639a9c628cfdc6e532d8e11 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 6 Dec 2024 14:23:59 +0100 Subject: [PATCH 32/71] arm64: dts: mt7986: add overlay for SATA power socket on BPI-R3 Bananapi R3 has a Power socket entended for using external SATA drives. This Socket is off by default but can be switched with gpio 8. Add an overlay to activate it. Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20241206132401.70259-1-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../mt7986a-bananapi-bpi-r3-sata.dtso | 34 +++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 08dbea48eaea..8d638976a2af 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-mini.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sata.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso new file mode 100644 index 000000000000..f7dd52981977 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + reg_sata12v: regulator-sata12v { + compatible = "regulator-fixed"; + regulator-name = "sata12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&pio 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_sata5v: regulator-sata5v { + compatible = "regulator-fixed"; + regulator-name = "sata5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_sata12v>; + }; + +}; From 3d7fdd8e38aafd4858935df2392762c1ab8fb40f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Wed, 18 Dec 2024 19:01:08 -0300 Subject: [PATCH 33/71] arm64: dts: mediatek: mt8195: Remove suspend-breaking reset from pcie1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MAC reset for PCIe port 1 on MT8195 when asserted during suspend causes the system to hang during resume with the following error (with no_console_suspend enabled): mtk-pcie-gen3 112f8000.pcie: PCIe link down, current LTSSM state: detect.quiet (0x0) mtk-pcie-gen3 112f8000.pcie: PM: dpm_run_callback(): genpd_resume_noirq+0x0/0x24 returns -110 mtk-pcie-gen3 112f8000.pcie: PM: failed to resume noirq: error -110 This issue is specific to MT8195. On MT8192 with the PCIe reset, MT8192_INFRA_RST4_PCIE_TOP_SWRST, added to the DT node, the issue is not observed. Since without the reset, the PCIe controller and WiFi card connected to it, work just as well, remove the reset to allow the system to suspend and resume properly. Fixes: ecc0af6a3fe6 ("arm64: dts: mt8195: Add pcie and pcie phy nodes") Signed-off-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20241218-mt8195-pcie1-reset-suspend-fix-v1-1-1c021dda42a6@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index ade685ed2190..04e41b557d44 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1611,9 +1611,6 @@ pcie1: pcie@112f8000 { phy-names = "pcie-phy"; power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; - resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; - reset-names = "mac"; - #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc1 0>, From f8a032834abceed9db3f20a5eb56064b21c84613 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Sat, 9 Nov 2024 10:16:33 -0500 Subject: [PATCH 34/71] arm64: dts: mediatek: Set mediatek,mac-wol on DWMAC node for all boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Due to the mediatek,mac-wol property previously being handled backwards by the dwmac-mediatek driver, its use in the DTs seems to have been inconsistent. Now that the driver has been fixed, correct this description. All the currently upstream boards support MAC WOL, so add the mediatek,mac-wol property to the missing ones. Signed-off-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20241109-mediatek-mac-wol-noninverted-v2-2-0e264e213878@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 1 + arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 1 + arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts index c84c47c1352f..0449686bd06b 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -115,6 +115,7 @@ ð { pinctrl-names = "default", "sleep"; pinctrl-0 = <ð_default>; pinctrl-1 = <ð_sleep>; + mediatek,mac-wol; status = "okay"; mdio { diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index bfb75296795c..1f59b5786b81 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -109,6 +109,7 @@ ð { pinctrl-names = "default", "sleep"; pinctrl-0 = <ð_default_pins>; pinctrl-1 = <ð_sleep_pins>; + mediatek,mac-wol; status = "okay"; mdio { diff --git a/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts index e2e75b8ff918..4985b65925a9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts @@ -271,6 +271,7 @@ ð { pinctrl-names = "default", "sleep"; pinctrl-0 = <ð_default_pins>; pinctrl-1 = <ð_sleep_pins>; + mediatek,mac-wol; status = "okay"; mdio { From 0b5b1c881a909f17c05ef4b1ccb421e077f6e466 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 30 Oct 2024 15:02:20 +0800 Subject: [PATCH 35/71] arm64: dts: mediatek: mt8183-kukui-jacuzzi: Drop pp3300_panel voltage settings The pp3300_panel fixed regulator is just a load switch. It does not have any regulating capabilities. Thus having voltage constraints on it is wrong. Remove the voltage constraints. Fixes: cabc71b08eb5 ("arm64: dts: mt8183: Add kukui-jacuzzi-damu board") Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20241030070224.1006331-2-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 49e053b932e7..80888bd4ad82 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -39,8 +39,6 @@ pp1800_mipibrdg: pp1800-mipibrdg { pp3300_panel: pp3300-panel { compatible = "regulator-fixed"; regulator-name = "pp3300_panel"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; pinctrl-names = "default"; pinctrl-0 = <&pp3300_panel_pins>; From 7d887c0c9f89310c43387425ccee9be10bf6c665 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 09:54:29 +0100 Subject: [PATCH 36/71] arm64: dts: mediatek: mt7988: Add pinctrl support Add mt7988a pinctrl node. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217085435.9586-5-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 54 +++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index c9649b815276..46969577c87a 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include / { compatible = "mediatek,mt7988a"; @@ -105,6 +106,59 @@ clock-controller@1001e000 { #clock-cells = <1>; }; + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7988-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d00000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_tr", + "iocfg_br", "iocfg_rb", + "iocfg_lb", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 84>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", + "pcie_wake_n0_0"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", + "pcie_wake_n1_0"; + }; + }; + + pcie2_pins: pcie2-pins { + mux { + function = "pcie"; + groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", + "pcie_wake_n2_0"; + }; + }; + + pcie3_pins: pcie3-pins { + mux { + function = "pcie"; + groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", + "pcie_wake_n3_0"; + }; + }; + }; + pwm@10048000 { compatible = "mediatek,mt7988-pwm"; reg = <0 0x10048000 0 0x1000>; From 1497f14d8bbc0a4631da3045861e97318e238746 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 09:54:30 +0100 Subject: [PATCH 37/71] arm64: dts: mediatek: mt7988a-bpi-r4: Add pinctrl subnodes for bpi-r4 Add board specific pinctrl configurations on Bananapi R4. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217085435.9586-6-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 189 ++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index efc4ad0b08b8..aa2dabc041fd 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -9,3 +9,192 @@ / { model = "Banana Pi BPI-R4"; chassis-type = "embedded"; }; + +&pio { + mdio0_pins: mdio0-pins { + mux { + function = "eth"; + groups = "mdc_mdio0"; + }; + + conf { + pins = "SMI_0_MDC", "SMI_0_MDIO"; + drive-strength = <8>; + }; + }; + + i2c0_pins: i2c0-g0-pins { + mux { + function = "i2c"; + groups = "i2c0_1"; + }; + }; + + i2c1_pins: i2c1-g0-pins { + mux { + function = "i2c"; + groups = "i2c1_0"; + }; + }; + + i2c1_sfp_pins: i2c1-sfp-g0-pins { + mux { + function = "i2c"; + groups = "i2c1_sfp"; + }; + }; + + i2c2_0_pins: i2c2-g0-pins { + mux { + function = "i2c"; + groups = "i2c2_0"; + }; + }; + + i2c2_1_pins: i2c2-g1-pins { + mux { + function = "i2c"; + groups = "i2c2_1"; + }; + }; + + gbe0_led0_pins: gbe0-led0-pins { + mux { + function = "led"; + groups = "gbe0_led0"; + }; + }; + + gbe1_led0_pins: gbe1-led0-pins { + mux { + function = "led"; + groups = "gbe1_led0"; + }; + }; + + gbe2_led0_pins: gbe2-led0-pins { + mux { + function = "led"; + groups = "gbe2_led0"; + }; + }; + + gbe3_led0_pins: gbe3-led0-pins { + mux { + function = "led"; + groups = "gbe3_led0"; + }; + }; + + gbe0_led1_pins: gbe0-led1-pins { + mux { + function = "led"; + groups = "gbe0_led1"; + }; + }; + + gbe1_led1_pins: gbe1-led1-pins { + mux { + function = "led"; + groups = "gbe1_led1"; + }; + }; + + gbe2_led1_pins: gbe2-led1-pins { + mux { + function = "led"; + groups = "gbe2_led1"; + }; + }; + + gbe3_led1_pins: gbe3-led1-pins { + mux { + function = "led"; + groups = "gbe3_led1"; + }; + }; + + i2p5gbe_led0_pins: 2p5gbe-led0-pins { + mux { + function = "led"; + groups = "2p5gbe_led0"; + }; + }; + + i2p5gbe_led1_pins: 2p5gbe-led1-pins { + mux { + function = "led"; + groups = "2p5gbe_led1"; + }; + }; + + mmc0_pins_emmc_45: mmc0-emmc-45-pins { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; + + mmc0_pins_emmc_51: mmc0-emmc-51-pins { + mux { + function = "flash"; + groups = "emmc_51"; + }; + }; + + mmc0_pins_sdcard: mmc0-sdcard-pins { + mux { + function = "flash"; + groups = "sdcard"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; + + snfi_pins: snfi-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + spi0_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0"; + }; + }; + + spi0_flash_pins: spi0-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spi1_pins: spi1-pins { + mux { + function = "spi"; + groups = "spi1"; + }; + }; + + spi2_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2"; + }; + }; + + spi2_flash_pins: spi2-flash-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + }; +}; From 69b2d44b91504d837e3687fdbffc0b5ad66ebdb5 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:15 +0100 Subject: [PATCH 38/71] arm64: dts: mediatek: mt7988: Add reserved memory Add memory range handled by ATF to not be touched by linux kernel. ATF is SoC specific and not board-specific so add it to mt7988.dtsi. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-2-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 46969577c87a..d205717ac78b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -62,6 +62,18 @@ psci { method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ + secmon@43000000 { + reg = <0 0x43000000 0 0x50000>; + no-map; + }; + }; + soc { compatible = "simple-bus"; ranges; From 206994e3b636ae5ce39657f81e39f81ac874eb89 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:16 +0100 Subject: [PATCH 39/71] arm64: dts: mediatek: mt7988: Add mmc support Add devicetree node for MMC controller. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-3-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index d205717ac78b..2e224d0d0168 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -112,7 +112,7 @@ watchdog: watchdog@1001c000 { #reset-cells = <1>; }; - clock-controller@1001e000 { + apmixedsys: clock-controller@1001e000 { compatible = "mediatek,mt7988-apmixedsys"; reg = <0 0x1001e000 0 0x1000>; #clock-cells = <1>; @@ -290,6 +290,25 @@ usb@11200000 { clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; }; + mmc0: mmc@11230000 { + compatible = "mediatek,mt7988-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11D60000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_MSDC400>, + <&infracfg CLK_INFRA_MSDC2_HCK>, + <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, + <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; + assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, + <&topckgen CLK_TOP_EMMC_400M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, + <&apmixedsys CLK_APMIXED_MSDCPLL>; + clock-names = "source", "hclk", "axi_cg", "ahb_cg"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + clock-controller@11f40000 { compatible = "mediatek,mt7988-xfi-pll"; reg = <0 0x11f40000 0 0x1000>; From 6a47514804e0e9607568c32b55c57bb5edd10d13 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:17 +0100 Subject: [PATCH 40/71] arm64: dts: mediatek: mt7988: Add lvts node Add Low Voltage Thermal Sensor (LVTS) node for mt7988 SoC. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-4-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 2e224d0d0168..32bb04ce21b3 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include / { compatible = "mediatek,mt7988a"; @@ -97,6 +98,7 @@ infracfg: clock-controller@10001000 { compatible = "mediatek,mt7988-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; topckgen: clock-controller@1001b000 { @@ -262,6 +264,17 @@ i2c@11005000 { status = "disabled"; }; + lvts: lvts@1100a000 { + compatible = "mediatek,mt7988-lvts-ap"; + #thermal-sensor-cells = <1>; + reg = <0 0x1100a000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; + interrupts = ; + resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>; + nvmem-cells = <&lvts_calibration>; + nvmem-cell-names = "lvts-calib-data-1"; + }; + usb@11190000 { compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; reg = <0 0x11190000 0 0x2e00>, @@ -321,6 +334,10 @@ efuse@11f50000 { reg = <0 0x11f50000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + lvts_calibration: calib@918 { + reg = <0x918 0x28>; + }; }; clock-controller@15000000 { From c26964fb5b6d395ddee624f6ced5891afabbccb2 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:18 +0100 Subject: [PATCH 41/71] arm64: dts: mediatek: mt7988: Add thermal-zone Add basic thermal-zone node. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-5-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 32bb04ce21b3..0e75a8692879 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -355,6 +355,21 @@ clock-controller@15031000 { }; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&lvts 0>; + trips { + cpu_trip_crit: crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; From e14b49db0087aa5d72f736d7306220ff2e3777f5 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:19 +0100 Subject: [PATCH 42/71] arm64: dts: mediatek: mt7988: Add missing clock-div property for i2c I2C binding requires clock-div property. Signed-off-by: Frank Wunderlich Fixes: 660c230bf302 ("arm64: dts: mediatek: mt7988: add I2C controllers") Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-6-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 0e75a8692879..16b28fcf1e3c 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -230,6 +230,7 @@ i2c@11003000 { reg = <0 0x11003000 0 0x1000>, <0 0x10217080 0 0x80>; interrupts = ; + clock-div = <1>; clocks = <&infracfg CLK_INFRA_I2C_BCK>, <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; clock-names = "main", "dma"; @@ -243,6 +244,7 @@ i2c@11004000 { reg = <0 0x11004000 0 0x1000>, <0 0x10217100 0 0x80>; interrupts = ; + clock-div = <1>; clocks = <&infracfg CLK_INFRA_I2C_BCK>, <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; clock-names = "main", "dma"; @@ -256,6 +258,7 @@ i2c@11005000 { reg = <0 0x11005000 0 0x1000>, <0 0x10217180 0 0x80>; interrupts = ; + clock-div = <1>; clocks = <&infracfg CLK_INFRA_I2C_BCK>, <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; clock-names = "main", "dma"; From b87cf19876c85e515a0ab28c957c30133c34fdc6 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:20 +0100 Subject: [PATCH 43/71] arm64: dts: mediatek: mt7988: Add mcu-sys node for cpu In preparation for adding support for CPU DVFS and clock tables for it, add the MCUSYS clock controller node. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-7-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 16b28fcf1e3c..5e53ea47f159 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -192,6 +192,12 @@ pwm@10048000 { status = "disabled"; }; + mcusys: mcusys@100e0000 { + compatible = "mediatek,mt7988-mcusys", "syscon"; + reg = <0 0x100e0000 0 0x1000>; + #clock-cells = <1>; + }; + serial@11000000 { compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; reg = <0 0x11000000 0 0x100>; From 343855d29b5c76e6d98a6539e2c087542298bb8c Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:21 +0100 Subject: [PATCH 44/71] arm64: dts: mediatek: mt7988: Add CPU OPP table for clock scaling Add operating points defining frequency/voltages of cpu cores. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-8-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 38 +++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 5e53ea47f159..a7954bf5c81e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -21,6 +21,10 @@ cpu@0 { reg = <0x0>; device_type = "cpu"; enable-method = "psci"; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; }; cpu@1 { @@ -28,6 +32,10 @@ cpu@1 { reg = <0x1>; device_type = "cpu"; enable-method = "psci"; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; }; cpu@2 { @@ -35,6 +43,10 @@ cpu@2 { reg = <0x2>; device_type = "cpu"; enable-method = "psci"; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; }; cpu@3 { @@ -42,6 +54,32 @@ cpu@3 { reg = <0x3>; device_type = "cpu"; enable-method = "psci"; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + }; + + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <850000>; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <850000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <850000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <900000>; + }; }; }; From 32c21f43147201a38bae30b7194d8528238a16d9 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:22 +0100 Subject: [PATCH 45/71] arm64: dts: mediatek: mt7988: Disable usb controllers by default The controllers should be enabled at board level if used. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-9-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index a7954bf5c81e..f8b01f3fff32 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -334,6 +334,7 @@ usb@11190000 { <&infracfg CLK_INFRA_133M_USB_HCK>, <&infracfg CLK_INFRA_USB_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + status = "disabled"; }; usb@11200000 { @@ -348,6 +349,7 @@ usb@11200000 { <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + status = "disabled"; }; mmc0: mmc@11230000 { From f693e6ba55ae98eeb226d0bef0fd37fcae4435a3 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:23 +0100 Subject: [PATCH 46/71] arm64: dts: mediatek: mt7988: Add t-phy for ssusb1 USB controller needs phys for working properly. On mt7988 ssusb0 uses a xs-phy, ssusb uses t-phy. For now add the t-phy for ssusb1. We can reuse the mt7986 compatible here. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-10-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index f8b01f3fff32..209d170bce7f 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -349,6 +349,8 @@ usb@11200000 { <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + phys = <&tphyu2port0 PHY_TYPE_USB2>, + <&tphyu3port0 PHY_TYPE_USB3>; status = "disabled"; }; @@ -371,6 +373,29 @@ mmc0: mmc@11230000 { status = "disabled"; }; + t-phy@11c50000 { + compatible = "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + tphyu2port0: usb-phy@11c50000 { + reg = <0 0x11c50000 0 0x700>; + clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + tphyu3port0: usb-phy@11c50700 { + reg = <0 0x11c50700 0 0x900>; + clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + clock-controller@11f40000 { compatible = "mediatek,mt7988-xfi-pll"; reg = <0 0x11f40000 0 0x1000>; From fda61ffb3a40a87da97feb95d0315458120a8353 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:24 +0100 Subject: [PATCH 47/71] arm64: dts: mediatek: mt7988: Add pcie nodes Add pcie controllers for mt7988. Reuse mt7986 compatible. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-11-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 152 ++++++++++++++++++++++ 1 file changed, 152 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 209d170bce7f..74c75d5149d7 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -373,6 +373,158 @@ mmc0: mmc@11230000 { status = "disabled"; }; + pcie@11280000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11280000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <3>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x00200000>, + <0x82000000 0x00 0x20200000 0x00 + 0x20200000 0x00 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_pins>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc2 0>, + <0 0 0 2 &pcie_intc2 1>, + <0 0 0 3 &pcie_intc2 2>, + <0 0 0 4 &pcie_intc2 3>; + pcie_intc2: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie@11290000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11290000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <2>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x28000000 0x00 + 0x28000000 0x00 0x00200000>, + <0x82000000 0x00 0x28200000 0x00 + 0x28200000 0x00 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_pins>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc3 0>, + <0 0 0 2 &pcie_intc3 1>, + <0 0 0 3 &pcie_intc3 2>, + <0 0 0 4 &pcie_intc3 3>; + pcie_intc3: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie@11300000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11300000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <0>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x30000000 0x00 + 0x30000000 0x00 0x00200000>, + <0x82000000 0x00 0x30200000 0x00 + 0x30200000 0x00 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie@11310000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11310000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <1>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x38000000 0x00 + 0x38000000 0x00 0x00200000>, + <0x82000000 0x00 0x38200000 0x00 + 0x38200000 0x00 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + t-phy@11c50000 { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; From 6a4601d80778e6ee6fde5412ee83e3e6c8f98453 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:25 +0100 Subject: [PATCH 48/71] arm64: dts: mediatek: mt7988a-bpi-r4: Enable watchdog Enable the watchdog on Bananapi R4 board. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-12-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index aa2dabc041fd..d914eae2b524 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -198,3 +198,7 @@ mux { }; }; }; + +&watchdog { + status = "okay"; +}; From 6e647beeb22124c5407b06037caa2cc7556dc0c3 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:26 +0100 Subject: [PATCH 49/71] arm64: dts: mediatek: mt7988a-bpi-r4: Add fixed regulators for 1v8 and 3v3 Add regulator nodes used for mmc to Bananapi R4 board. This board has 1 MMC controller used for SDMMC and eMMC where only one can be used at one time, selected by hardware switches. SD uses 3v3 for both supplies and emmc uses both regulators. So defining both regulators in board dts and referencing them in the dt overlay. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-13-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index d914eae2b524..df53512c6890 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -8,6 +8,24 @@ / { compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; model = "Banana Pi BPI-R4"; chassis-type = "embedded"; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &pio { From 714a80ced07ac495513153840169a0d3b107d294 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:27 +0100 Subject: [PATCH 50/71] arm64: dts: mediatek: mt7988a-bpi-r4: Add dt overlays for sd + emmc Bananapi R4 can use the mmc controller either with sd card or the onboard emmc. The used device is selected through hardware-switches and probed in bootloader. Add devicetree overlays for both mmc configurations. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-14-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 3 ++ .../mt7988a-bananapi-bpi-r4-emmc.dtso | 33 +++++++++++++++++++ .../mediatek/mt7988a-bananapi-bpi-r4-sd.dtso | 31 +++++++++++++++++ 3 files changed, 67 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso create mode 100644 arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 8d638976a2af..2d2805119943 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -22,6 +22,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb @@ -104,3 +106,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb # Device tree overlays support DTC_FLAGS_mt7986a-bananapi-bpi-r3 := -@ DTC_FLAGS_mt7986a-bananapi-bpi-r3-mini := -@ +DTC_FLAGS_mt7988a-bananapi-bpi-r4 := -@ diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso new file mode 100644 index 000000000000..3e320b2f83d5 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-emmc.dtso @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; +}; + +&{/soc/mmc@11230000} { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_emmc_51>; + pinctrl-1 = <&mmc0_pins_emmc_51>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x12814>; + vqmmc-supply = <®_1p8v>; + vmmc-supply = <®_3p3v>; + non-removable; + no-sd; + no-sdio; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso new file mode 100644 index 000000000000..663c6345dd31 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-sd.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Frank Wunderlich + */ + +/dts-v1/; +/plugin/; + +#include + +/ { + compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; +}; + +&{/soc/mmc@11230000} { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_sdcard>; + pinctrl-1 = <&mmc0_pins_sdcard>; + cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + no-mmc; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + From 3687df2792bee54a13b797d2897b6650028564f3 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:28 +0100 Subject: [PATCH 51/71] arm64: dts: mediatek: mt7988a-bpi-r4: Add thermal configuration Add additional thermal trips to Bananapi R4 board. SoC only contains the critical trip. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-15-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index df53512c6890..8a320d9da443 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -28,6 +28,34 @@ reg_3p3v: regulator-3p3v { }; }; +&cpu_thermal { + trips { + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_med: active-med { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <40000>; + hysteresis = <2000>; + type = "active"; + }; + }; +}; + &pio { mdio0_pins: mdio0-pins { mux { From 54df2f1e0ad1ae1bd11d254143a3d66c1c83a0be Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:29 +0100 Subject: [PATCH 52/71] arm64: dts: mediatek: mt7988a-bpi-r4: Enable serial0 debug uart Enable the debug uart on Bananapi R4 board. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-16-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index 8a320d9da443..9037f35857a9 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -245,6 +245,10 @@ mux { }; }; +&serial0 { + status = "okay"; +}; + &watchdog { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 74c75d5149d7..59a1ffc2edfc 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -236,7 +236,7 @@ mcusys: mcusys@100e0000 { #clock-cells = <1>; }; - serial@11000000 { + serial0: serial@11000000 { compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; reg = <0 0x11000000 0 0x100>; interrupts = ; From 2f2f9a4a2bc647e397e74f276f02eb0b82de39e8 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:30 +0100 Subject: [PATCH 53/71] arm64: dts: mediatek: mt7988a-bpi-r4: Add default UART stdout Add chosen node on Bananapi R4 board with stdout and default bootargs. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-17-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index 9037f35857a9..46117df7d44c 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -9,6 +9,10 @@ / { model = "Banana Pi BPI-R4"; chassis-type = "embedded"; + chosen { + stdout-path = "serial0:115200n8"; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; From faf97571ae83a8db3eb74109275d217514d2b474 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:31 +0100 Subject: [PATCH 54/71] arm64: dts: mediatek: mt7988a-bpi-r4: Enable I2C controllers Enable the I2C0, I2C2 controllers found on the BananaPi R4 board. Both controllers are not accessible from user and having fixed spare devices. I2C0 have a pmic connected, I2C2 is used with I2C-multiplexer for e.g. SFP cages. The missing I2C1 is connected to GPIO header which can have either GPIO mode or I2C mode. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-18-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 12 ++++++++++++ arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 6 +++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index 46117df7d44c..3d165f7b29dc 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -60,6 +60,18 @@ cpu_trip_active_low: active-low { }; }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_1_pins>; + status = "okay"; +}; + &pio { mdio0_pins: mdio0-pins { mux { diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 59a1ffc2edfc..c0a49f68834a 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -269,7 +269,7 @@ serial@11000200 { status = "disabled"; }; - i2c@11003000 { + i2c0: i2c@11003000 { compatible = "mediatek,mt7981-i2c"; reg = <0 0x11003000 0 0x1000>, <0 0x10217080 0 0x80>; @@ -283,7 +283,7 @@ i2c@11003000 { status = "disabled"; }; - i2c@11004000 { + i2c1: i2c@11004000 { compatible = "mediatek,mt7981-i2c"; reg = <0 0x11004000 0 0x1000>, <0 0x10217100 0 0x80>; @@ -297,7 +297,7 @@ i2c@11004000 { status = "disabled"; }; - i2c@11005000 { + i2c2: i2c@11005000 { compatible = "mediatek,mt7981-i2c"; reg = <0 0x11005000 0 0x1000>, <0 0x10217180 0 0x80>; From 572c02e687ba803bd17498218eaa21aeaebe3b97 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:32 +0100 Subject: [PATCH 55/71] arm64: dts: mediatek: mt7988a-bpi-r4: Add PCA9545 I2C Mux Bananapi R4 uses an i2c multiplexer for SFP slots, rtc and eeprom. Add its node to the right i2c controller. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-19-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index 3d165f7b29dc..0dc1fd9265c6 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -2,6 +2,8 @@ /dts-v1/; +#include + #include "mt7988a.dtsi" / { @@ -70,6 +72,45 @@ &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_1_pins>; status = "okay"; + + pca9545: i2c-mux@70 { + compatible = "nxp,pca9545"; + reg = <0x70>; + reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + }; + + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + size = <256>; + }; + + }; + + i2c_sfp1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_sfp2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + }; }; &pio { From b1e011c7b5800d256293d649fbf2335da2474704 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:33 +0100 Subject: [PATCH 56/71] arm64: dts: mediatek: mt7988a-bpi-r4: Enable t-phy for ssusb1 Bananapi R4 uses t-phy for usb. Enable its node at board level. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-20-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index 0dc1fd9265c6..129031b0d784 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -306,6 +306,10 @@ &serial0 { status = "okay"; }; +&tphy { + status = "okay"; +}; + &watchdog { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index c0a49f68834a..0766ca0dd3f6 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -525,7 +525,7 @@ pcie_intc1: interrupt-controller { }; }; - t-phy@11c50000 { + tphy: t-phy@11c50000 { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; #address-cells = <2>; From 85445d88d1f96d9d53b4571feeb0e97a466a0d59 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:34 +0100 Subject: [PATCH 57/71] arm64: dts: mediatek: mt7988a-bpi-r4: Enable ssusb1 on bpi-r4 Enable usb on Bananapi R4 board. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-21-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index 129031b0d784..08d664d6449b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -306,6 +306,10 @@ &serial0 { status = "okay"; }; +&ssusb1 { + status = "okay"; +}; + &tphy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 0766ca0dd3f6..f3e942db0b99 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -337,7 +337,7 @@ usb@11190000 { status = "disabled"; }; - usb@11200000 { + ssusb1: usb@11200000 { compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; reg = <0 0x11200000 0 0x2e00>, <0 0x11203e00 0 0x0100>; From 6c7ab311939c1187b591ef938c10fa33648743c9 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:35 +0100 Subject: [PATCH 58/71] arm64: dts: mediatek: mt7988a-bpi-r4: Enable pwm Enable pwm on Bananapi R4 board. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-22-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 4 ++++ arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index 08d664d6449b..4b1eaf818b66 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -302,6 +302,10 @@ mux { }; }; +&pwm { + status = "okay"; +}; + &serial0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index f3e942db0b99..6f6a1a1c1d78 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -211,7 +211,7 @@ mux { }; }; - pwm@10048000 { + pwm: pwm@10048000 { compatible = "mediatek,mt7988-pwm"; reg = <0 0x10048000 0 0x1000>; clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, From 8b74b1acba92fc64962b48a777317cf4ed2af9c5 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Tue, 17 Dec 2024 10:12:36 +0100 Subject: [PATCH 59/71] arm64: dts: mediatek: mt7988a-bpi-r4: Enable pcie Enable the pci controllers on BPI-R4. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241217091238.16032-23-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 20 +++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 8 ++++---- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index 4b1eaf818b66..d6f1fca3323c 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -113,6 +113,26 @@ i2c_sfp2: i2c@2 { }; }; +/* mPCIe SIM2 */ +&pcie0 { + status = "okay"; +}; + +/* mPCIe SIM3 */ +&pcie1 { + status = "okay"; +}; + +/* M.2 key-B SIM1 */ +&pcie2 { + status = "okay"; +}; + +/* M.2 key-M SSD */ +&pcie3 { + status = "okay"; +}; + &pio { mdio0_pins: mdio0-pins { mux { diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 6f6a1a1c1d78..7a5e16a97476 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -373,7 +373,7 @@ mmc0: mmc@11230000 { status = "disabled"; }; - pcie@11280000 { + pcie2: pcie@11280000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; device_type = "pci"; @@ -411,7 +411,7 @@ pcie_intc2: interrupt-controller { }; }; - pcie@11290000 { + pcie3: pcie@11290000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; device_type = "pci"; @@ -449,7 +449,7 @@ pcie_intc3: interrupt-controller { }; }; - pcie@11300000 { + pcie0: pcie@11300000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; device_type = "pci"; @@ -487,7 +487,7 @@ pcie_intc0: interrupt-controller { }; }; - pcie@11310000 { + pcie1: pcie@11310000 { compatible = "mediatek,mt7986-pcie", "mediatek,mt8192-pcie"; device_type = "pci"; From 285cbdd9f52526842986ecb77b8f35788299a5f8 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 20 Dec 2024 17:38:35 +0100 Subject: [PATCH 60/71] arm64: dts: mediatek: mt7988a-bpi-r4: Add MediaTek MT6682A/RT5190A PMIC Bananapi R4 Board contains a MT6682A pmic which is compatible to rt5190a. Add its node to the i2 controller. The BananaPi R4 board has a MediaTek MT6682A PMIC, a rebrand of the Richtek RT5190A chip, connected to the I2C0 bus. Add the relevant node and, while at it, also configure the regulators from this PMIC that are used on this board. Only Buck2/Buck3 voltage can be controlled by software. BUCK4 input is 5V from BUCK1 output, and the resistor (mapped to RP30/RP31 on BPI-R4) configures BUCK4 output to 1.8V. LDO input is 3.3V from 3.3VD, and the resistor (mapped to RP38/RP40 on BPI-R4) configures LDO output to 1.8V. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241220163838.114786-2-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index d6f1fca3323c..27edc6b84f80 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -3,6 +3,7 @@ /dts-v1/; #include +#include #include "mt7988a.dtsi" @@ -66,6 +67,55 @@ &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; status = "okay"; + + rt5190a_64: rt5190a@64 { + compatible = "richtek,rt5190a"; + reg = <0x64>; + vin2-supply = <&rt5190_buck1>; + vin3-supply = <&rt5190_buck1>; + vin4-supply = <&rt5190_buck1>; + + regulators { + rt5190_buck1: buck1 { + regulator-name = "rt5190a-buck1"; + regulator-min-microvolt = <5090000>; + regulator-max-microvolt = <5090000>; + regulator-allowed-modes = + , ; + regulator-boot-on; + regulator-always-on; + }; + buck2 { + regulator-name = "vcore"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + rt5190_buck3: buck3 { + regulator-name = "vproc"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + }; + buck4 { + regulator-name = "rt5190a-buck4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = + , ; + regulator-boot-on; + regulator-always-on; + }; + ldo { + regulator-name = "rt5190a-ldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; &i2c2 { From 607cc6e9b5f10f5f41b1cca6efc5405272136013 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 20 Dec 2024 17:38:36 +0100 Subject: [PATCH 61/71] arm64: dts: mediatek: mt7988a-bpi-r4: Add proc-supply for cpus Add proc-supply property to cpus on Bananapi R4 board. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241220163838.114786-3-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 8 ++++---- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index 27edc6b84f80..6623112c24c7 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -35,6 +35,22 @@ reg_3p3v: regulator-3p3v { }; }; +&cpu0 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu1 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu2 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu3 { + proc-supply = <&rt5190_buck3>; +}; + &cpu_thermal { trips { cpu_trip_hot: hot { diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 7a5e16a97476..88b56a24efca 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -16,7 +16,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a73"; reg = <0x0>; device_type = "cpu"; @@ -27,7 +27,7 @@ cpu@0 { operating-points-v2 = <&cluster0_opp>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a73"; reg = <0x1>; device_type = "cpu"; @@ -38,7 +38,7 @@ cpu@1 { operating-points-v2 = <&cluster0_opp>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a73"; reg = <0x2>; device_type = "cpu"; @@ -49,7 +49,7 @@ cpu@2 { operating-points-v2 = <&cluster0_opp>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a73"; reg = <0x3>; device_type = "cpu"; From 0cea8dcb58e2ad83cb8a5be57640b4ef30c133f8 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 24 Dec 2024 16:48:38 +0800 Subject: [PATCH 62/71] arm64: dts: mediatek: mt8192: Drop Chromebook variants that never shipped The Hayato rev5 sku2 and Spherion rev4 variants were designed in anticipation of shortages of the headphone codec. This never happened. As far as our records show: the variants were never produced or shipped, and no such devices were deployed to any lab. Drop them. Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20241224084839.2904335-2-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 2 - .../mt8192-asurada-hayato-r5-sku2.dts | 65 ---------------- .../mediatek/mt8192-asurada-spherion-r4.dts | 78 ------------------- 3 files changed, 145 deletions(-) delete mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts delete mode 100644 arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 2d2805119943..b763b73788a4 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -86,9 +86,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r5-sku2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb -dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r4.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-dojo-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r1.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts deleted file mode 100644 index cd86ad9ba28a..000000000000 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2022 Google LLC - */ -/dts-v1/; -#include "mt8192-asurada.dtsi" - -/ { - model = "Google Hayato rev5"; - chassis-type = "convertible"; - compatible = "google,hayato-rev5-sku2", "google,hayato-sku2", - "google,hayato", "mediatek,mt8192"; -}; - -&keyboard_controller { - function-row-physmap = < - MATRIX_KEY(0x00, 0x02, 0) /* T1 */ - MATRIX_KEY(0x03, 0x02, 0) /* T2 */ - MATRIX_KEY(0x02, 0x02, 0) /* T3 */ - MATRIX_KEY(0x01, 0x02, 0) /* T4 */ - MATRIX_KEY(0x03, 0x04, 0) /* T5 */ - MATRIX_KEY(0x02, 0x04, 0) /* T6 */ - MATRIX_KEY(0x01, 0x04, 0) /* T7 */ - MATRIX_KEY(0x02, 0x09, 0) /* T8 */ - MATRIX_KEY(0x01, 0x09, 0) /* T9 */ - MATRIX_KEY(0x00, 0x04, 0) /* T10 */ - >; - linux,keymap = < - MATRIX_KEY(0x00, 0x02, KEY_BACK) - MATRIX_KEY(0x03, 0x02, KEY_FORWARD) - MATRIX_KEY(0x02, 0x02, KEY_REFRESH) - MATRIX_KEY(0x01, 0x02, KEY_FULL_SCREEN) - MATRIX_KEY(0x03, 0x04, KEY_SCALE) - MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) - MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) - MATRIX_KEY(0x02, 0x09, KEY_MUTE) - MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) - MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) - - CROS_STD_MAIN_KEYMAP - >; -}; - -&rt5682 { - compatible = "realtek,rt5682s"; -}; - -&sound { - compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682s"; - - speaker-codecs { - sound-dai = <&rt1015p>; - }; - - headset-codec { - sound-dai = <&rt5682 0>; - }; -}; - -&touchscreen { - compatible = "hid-over-i2c"; - post-power-on-delay-ms = <10>; - hid-descr-addr = <0x0001>; - vdd-supply = <&pp3300_u>; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts deleted file mode 100644 index 5e9e598bab90..000000000000 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright 2022 Google LLC - */ -/dts-v1/; -#include "mt8192-asurada.dtsi" -#include - -/ { - model = "Google Spherion (rev4)"; - chassis-type = "laptop"; - compatible = "google,spherion-rev4", "google,spherion", - "mediatek,mt8192"; - - pwmleds { - compatible = "pwm-leds"; - - led { - function = LED_FUNCTION_KBD_BACKLIGHT; - color = ; - pwms = <&cros_ec_pwm 0>; - max-brightness = <1023>; - }; - }; -}; - -&cros_ec_pwm { - status = "okay"; -}; - -&keyboard_controller { - function-row-physmap = < - MATRIX_KEY(0x00, 0x02, 0) /* T1 */ - MATRIX_KEY(0x03, 0x02, 0) /* T2 */ - MATRIX_KEY(0x02, 0x02, 0) /* T3 */ - MATRIX_KEY(0x01, 0x02, 0) /* T4 */ - MATRIX_KEY(0x03, 0x04, 0) /* T5 */ - MATRIX_KEY(0x02, 0x04, 0) /* T6 */ - MATRIX_KEY(0x01, 0x04, 0) /* T7 */ - MATRIX_KEY(0x02, 0x09, 0) /* T8 */ - MATRIX_KEY(0x01, 0x09, 0) /* T9 */ - MATRIX_KEY(0x00, 0x04, 0) /* T10 */ - >; - linux,keymap = < - MATRIX_KEY(0x00, 0x02, KEY_BACK) - MATRIX_KEY(0x03, 0x02, KEY_REFRESH) - MATRIX_KEY(0x02, 0x02, KEY_FULL_SCREEN) - MATRIX_KEY(0x01, 0x02, KEY_SCALE) - MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) - MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) - MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) - MATRIX_KEY(0x02, 0x09, KEY_MUTE) - MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) - MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) - - CROS_STD_MAIN_KEYMAP - >; -}; - -&rt5682 { - compatible = "realtek,rt5682s"; -}; - -&sound { - compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682s"; - - speaker-codecs { - sound-dai = <&rt1015p>; - }; - - headset-codec { - sound-dai = <&rt5682 0>; - }; -}; - -&touchscreen { - compatible = "elan,ekth3500"; -}; From 5c9f4bc4b6730d21b436085b302869f572695f0b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 24 Dec 2024 16:48:37 +0800 Subject: [PATCH 63/71] dt-bindings: arm: mediatek: Drop MT8192 Chromebook variants that never shipped The Hayato rev5 sku2 and Spherion rev4 variants were designed in anticipation of shortages of the headphone codec. This never happened. As far as our records show: the variants were never produced or shipped, and no such devices were deployed to any lab. Drop them. Signed-off-by: Chen-Yu Tsai Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20241224084839.2904335-1-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index da6af39caa9b..3ce34d68c213 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -370,12 +370,6 @@ properties: - const: google,hayato-rev1 - const: google,hayato - const: mediatek,mt8192 - - description: Google Hayato rev5 - items: - - const: google,hayato-rev5-sku2 - - const: google,hayato-sku2 - - const: google,hayato - - const: mediatek,mt8192 - description: Google Spherion (Acer Chromebook 514) items: - const: google,spherion-rev3 @@ -384,11 +378,6 @@ properties: - const: google,spherion-rev0 - const: google,spherion - const: mediatek,mt8192 - - description: Google Spherion rev4 (Acer Chromebook 514) - items: - - const: google,spherion-rev4 - - const: google,spherion - - const: mediatek,mt8192 - items: - enum: - mediatek,mt8192-evb From 4726336c6b44693314b02e07925eabc2dea5e361 Mon Sep 17 00:00:00 2001 From: "Jason-JH.Lin" Date: Fri, 20 Dec 2024 02:15:28 +0800 Subject: [PATCH 64/71] dt-bindings: display: mediatek: ovl: Add compatible strings for MT8188 MDP3 Add compatible strings for the MDP3 OVL hardware components in MediaTek's MT8188 SoC and it is compatible with the existing MT8195 MDP OVL components. Signed-off-by: Jason-JH.Lin Suggested-by: AngeloGioacchino Del Regno Acked-by: Chun-Kuang Hu Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20241219181531.4282-2-jason-jh.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index 9ea796a033b2..33542211507f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -46,6 +46,9 @@ properties: - mediatek,mt8186-disp-ovl - mediatek,mt8365-disp-ovl - const: mediatek,mt8192-disp-ovl + - items: + - const: mediatek,mt8188-mdp3-ovl + - const: mediatek,mt8195-mdp3-ovl reg: maxItems: 1 From 5086c55a95bef952950732cf0fa20d16c3a5cf64 Mon Sep 17 00:00:00 2001 From: Hsiao Chien Sung Date: Fri, 20 Dec 2024 02:15:29 +0800 Subject: [PATCH 65/71] dt-bindings: display: mediatek: ovl: Modify rules for MT8195/MT8188 Modify rules for both MT8195 and MT8188. Hardware capabilities include color formats and AFBC are changed since MT8195, stop using the settings of MT8183. Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Signed-off-by: Hsiao Chien Sung Signed-off-by: Jason-JH.Lin Acked-by: Chun-Kuang Hu Link: https://lore.kernel.org/r/20241219181531.4282-3-jason-jh.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno --- .../bindings/display/mediatek/mediatek,ovl.yaml | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index 33542211507f..4f110635afb6 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt8173-disp-ovl - mediatek,mt8183-disp-ovl - mediatek,mt8192-disp-ovl + - mediatek,mt8195-disp-ovl - mediatek,mt8195-mdp3-ovl - items: - enum: @@ -36,16 +37,14 @@ properties: - enum: - mediatek,mt6795-disp-ovl - const: mediatek,mt8173-disp-ovl - - items: - - enum: - - mediatek,mt8188-disp-ovl - - mediatek,mt8195-disp-ovl - - const: mediatek,mt8183-disp-ovl - items: - enum: - mediatek,mt8186-disp-ovl - mediatek,mt8365-disp-ovl - const: mediatek,mt8192-disp-ovl + - items: + - const: mediatek,mt8188-disp-ovl + - const: mediatek,mt8195-disp-ovl - items: - const: mediatek,mt8188-mdp3-ovl - const: mediatek,mt8195-mdp3-ovl From 2a1a08590d371fc6327efc8b60d8bc1831f23fb4 Mon Sep 17 00:00:00 2001 From: "Jason-JH.Lin" Date: Fri, 20 Dec 2024 02:15:30 +0800 Subject: [PATCH 66/71] dts: arm64: mediatek: mt8188: Update OVL compatible from MT8183 to MT8195 The OVL hardware capabilities have changed starting from MT8195, making the MT8183 compatible no longer applicable. Therefore, it is necessary to update the OVL compatible from MT8183 to MT8195. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Jason-JH.Lin Fixes: 7075b21d1a8e ("arm64: dts: mediatek: mt8188: Add display nodes for vdosys0") Link: https://lore.kernel.org/r/20241219181531.4282-4-jason-jh.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 981853cd0192..338120930b81 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2495,7 +2495,7 @@ jpeg_decoder: jpeg-decoder@1a040000 { }; ovl0: ovl@1c000000 { - compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8183-disp-ovl"; + compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8195-disp-ovl"; reg = <0 0x1c000000 0 0x1000>; clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; interrupts = ; From ce3dbc46d7e30a84b8e99c730e3172dd5efbf094 Mon Sep 17 00:00:00 2001 From: "Jason-JH.Lin" Date: Fri, 20 Dec 2024 02:15:31 +0800 Subject: [PATCH 67/71] dts: arm64: mediatek: mt8195: Remove MT8183 compatible for OVL The OVL hardware capabilities have changed starting from MT8195, making the MT8183 compatible no longer applicable. Therefore, it is necessary to remove the MT8183 compatible for OVL. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Jason-JH.Lin Fixes: b852ee68fd72 ("arm64: dts: mt8195: Add display node for vdosys0") Link: https://lore.kernel.org/r/20241219181531.4282-5-jason-jh.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 04e41b557d44..f013dbad9dc4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -3135,7 +3135,7 @@ larb20: larb@1b010000 { }; ovl0: ovl@1c000000 { - compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl"; + compatible = "mediatek,mt8195-disp-ovl"; reg = <0 0x1c000000 0 0x1000>; interrupts = ; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; From 798e949b63e2ff05cca813e2de3eeb3f4bba470c Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Mon, 6 Jan 2025 09:57:31 +0100 Subject: [PATCH 68/71] arm64: dts: mediatek: mt8365-evk: Set ethernet alias Configure an the ethernet alias to match the ethernet controller (even if it's off by default). This allows e.g. u-boot to configure the mac address on boot properly Signed-off-by: Sjoerd Simons Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250106085737.227622-1-sjoerd@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 7d90112a7e27..44c61094c4d5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -21,6 +21,7 @@ / { aliases { serial0 = &uart0; + ethernet = ðernet; }; chosen { From 3b19239ad4201123a2bc05af5859f5d75a30a49e Mon Sep 17 00:00:00 2001 From: Val Packett Date: Wed, 25 Dec 2024 16:26:19 -0300 Subject: [PATCH 69/71] dt-bindings: mediatek,mt6779-keypad: add more compatibles Add compatibles for SoCs using this device (mt8183, mt8365, mt8516). Signed-off-by: Val Packett Acked-by: Krzysztof Kozlowski Reviewed-by: Mattijs Korpershoek Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241225192631.25017-2-val@packett.cool Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/input/mediatek,mt6779-keypad.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml b/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml index 47aac8794b68..517a4ac1bea3 100644 --- a/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml @@ -26,6 +26,9 @@ properties: - items: - enum: - mediatek,mt6873-keypad + - mediatek,mt8183-keypad + - mediatek,mt8365-keypad + - mediatek,mt8516-keypad - const: mediatek,mt6779-keypad reg: From 6139d9e9e397dc9711cf10f8f548a8f9da3b5323 Mon Sep 17 00:00:00 2001 From: Val Packett Date: Wed, 25 Dec 2024 16:26:20 -0300 Subject: [PATCH 70/71] arm64: dts: mediatek: add per-SoC compatibles for keypad nodes The mt6779-keypad binding specifies using a compatible for the actual SoC before the generic MT6779 one. Fixes: a8013418d35c ("arm64: dts: mediatek: mt8183: add keyboard node") Fixes: 6ff945376556 ("arm64: dts: mediatek: Initial mt8365-evk support") Signed-off-by: Val Packett Reviewed-by: Mattijs Korpershoek Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241225192631.25017-3-val@packett.cool Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 ++- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index c7008bb8a81d..0aa34e5bbaaa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1024,7 +1024,8 @@ pwrap: pwrap@1000d000 { }; keyboard: keyboard@10010000 { - compatible = "mediatek,mt6779-keypad"; + compatible = "mediatek,mt8183-keypad", + "mediatek,mt6779-keypad"; reg = <0 0x10010000 0 0x1000>; interrupts = ; clocks = <&clk26m>; diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 9c91fe8ea0f9..2bf8c9d02b6e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -449,7 +449,8 @@ pwrap: pwrap@1000d000 { }; keypad: keypad@10010000 { - compatible = "mediatek,mt6779-keypad"; + compatible = "mediatek,mt8365-keypad", + "mediatek,mt6779-keypad"; reg = <0 0x10010000 0 0x1000>; wakeup-source; interrupts = ; From 0fb0d360218129f00b76f13e30b86321b64e36f6 Mon Sep 17 00:00:00 2001 From: Val Packett Date: Wed, 25 Dec 2024 16:26:21 -0300 Subject: [PATCH 71/71] arm64: dts: mediatek: mt8516: add keypad node Add a keypad matrix node for the MT8516/MT8167 SoC. Signed-off-by: Val Packett Reviewed-by: Mattijs Korpershoek Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20241225192631.25017-4-val@packett.cool Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index e30623ebac0e..b5e753759465 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -220,6 +220,17 @@ timer: timer@10008000 { clock-names = "clk13m", "bus"; }; + keypad: keypad@10002000 { + compatible = "mediatek,mt8516-keypad", + "mediatek,mt6779-keypad"; + reg = <0 0x10002000 0 0x1000>; + wakeup-source; + interrupts = ; + clocks = <&clk26m>; + clock-names = "kpd"; + status = "disabled"; + }; + syscfg_pctl: syscfg-pctl@10005000 { compatible = "syscon"; reg = <0 0x10005000 0 0x1000>;