diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 00c05243b9a4..fb1fe1ea759f 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a08g045-pinctrl # RZ/G3S + - renesas,r9a08g046-pinctrl # RZ/G3L - renesas,r9a09g047-pinctrl # RZ/G3E - renesas,r9a09g056-pinctrl # RZ/V2N - renesas,r9a09g057-pinctrl # RZ/V2H(P) @@ -78,6 +79,26 @@ properties: - description: PFC main reset - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins + reset-names: + oneOf: + - items: + - const: rstn + - const: port + - const: spare + - items: + - const: main + - const: error + + renesas,clonech: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to system controller + - description: offset of clone channel control register + description: + Phandle and offset to the system controller containing the clone channel + control values. + additionalProperties: anyOf: - type: object @@ -140,6 +161,15 @@ additionalProperties: allOf: - $ref: pinctrl.yaml# + - if: + properties: + compatible: + contains: + const: renesas,r9a08g046-pinctrl + then: + required: + - renesas,clonech + - if: properties: compatible: @@ -152,10 +182,14 @@ allOf: properties: resets: maxItems: 2 + reset-names: + maxItems: 2 else: properties: resets: minItems: 3 + reset-names: + minItems: 3 required: - compatible @@ -187,6 +221,7 @@ examples: resets = <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, <&cpg R9A07G044_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; power-domains = <&cpg>; scif0_pins: serial0 { diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 561e6018fd89..a106e087c224 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -11,12 +11,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include @@ -26,6 +28,7 @@ #include #include +#include #include #include #include @@ -63,10 +66,18 @@ #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */ #define PIN_CFG_ELC BIT(17) #define PIN_CFG_IOLH_RZV2H BIT(18) +#define PIN_CFG_PVDD1833_OTH_AWO_POC BIT(19) /* known on RZ/G3L only */ +#define PIN_CFG_PVDD1833_OTH_ISO_POC BIT(20) /* known on RZ/G3L only */ +#define PIN_CFG_WDTOVF_N_POC BIT(21) /* known on RZ/G3L only */ #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ +#define PIN_CFG_OTHER_POC_MASK \ + (PIN_CFG_PVDD1833_OTH_AWO_POC | \ + PIN_CFG_PVDD1833_OTH_ISO_POC | \ + PIN_CFG_WDTOVF_N_POC) + #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ PIN_CFG_PUPD | \ @@ -85,6 +96,18 @@ #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF) +#define RZG3L_MPXED_ETH_PIN_FUNCS(ether) \ + (PIN_CFG_IO_VMC_##ether | \ + PIN_CFG_IOLH_C | \ + PIN_CFG_PUPD | \ + PIN_CFG_NF) + +#define RZG3L_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \ + PIN_CFG_SOFT_PS) + +#define RZG3L_MPXED_PIN_FUNCS_POC(grp, poc) (RZG2L_MPXED_COMMON_PIN_FUNCS(grp) | \ + PIN_CFG_PVDD1833_OTH_##poc##_POC) + #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54) #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46) #define PIN_CFG_MASK GENMASK_ULL(31, 0) @@ -131,6 +154,18 @@ FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \ FIELD_PREP_CONST(PIN_CFG_MASK, (cfg))) +#define RZG3L_CLONE_CHANNEL_PIN_MASK GENMASK(31, 24) +#define RZG3L_CLONE_CHANNEL_PORT_MASK GENMASK(23, 19) +#define RZG3L_CLONE_CHANNEL_BIT_MASK GENMASK(12, 9) +#define RZG3L_CLONE_CHANNEL_VAL_MASK BIT(8) +#define RZG3L_CLONE_CHANNEL_PFC_MASK GENMASK(7, 0) +#define RZG3L_CLONE_CHANNEL_DATA(port, pins, bit, val, pfc) \ + (FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PIN_MASK, (pins)) | \ + FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PORT_MASK, (port)) | \ + FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_BIT_MASK, (bit)) | \ + FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_VAL_MASK, (val)) | \ + FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PFC_MASK, (pfc))) + #define P(off) (0x0000 + (off)) #define PM(off) (0x0100 + (off) * 2) #define PMC(off) (0x0200 + (off)) @@ -145,7 +180,8 @@ #define SMT(off) (0x3400 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) -#define QSPI (0x3008) +#define QSPI (0x3008) /* known on RZ/{G2L,G2LC,G2UL,Five} only */ +#define OTHER_POC (0x3028) /* known on RZ/G3L only */ #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ @@ -220,12 +256,16 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = { * @sd_ch: SD_CH register offset * @eth_poc: ETH_POC register offset * @oen: OEN register offset + * @qspi: QSPI register offset + * @other_poc: OTHER_POC register offset */ struct rzg2l_register_offsets { u16 pwpr; u16 sd_ch; u16 eth_poc; u16 oen; + u16 qspi; + u16 other_poc; }; /** @@ -287,6 +327,8 @@ struct rzg2l_pinctrl_data { const struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; unsigned int n_dedicated_pins; + const u32 *clone_channel_data; + unsigned int n_clone_channel_data; const struct rzg2l_hwcfg *hwcfg; const u64 *variable_pin_cfg; unsigned int n_variable_pin_cfg; @@ -322,8 +364,12 @@ struct rzg2l_pinctrl_pin_settings { * @pupd: PUPD registers cache * @ien: IEN registers cache * @smt: SMT registers cache + * @sr: SR registers cache + * @nod: NOD registers cache + * @clone: Clone register cache * @sd_ch: SD_CH registers cache * @eth_poc: ET_POC registers cache + * @other_poc: OTHER_POC register cache * @oen: Output Enable register cache * @qspi: QSPI registers cache */ @@ -335,10 +381,14 @@ struct rzg2l_pinctrl_reg_cache { u32 *iolh[2]; u32 *ien[2]; u32 *pupd[2]; - u32 *smt; + u32 *smt[2]; + u32 *sr[2]; + u32 *nod[2]; + u32 clone; u8 sd_ch[2]; u8 eth_poc[2]; u8 oen; + u8 other_poc; u8 qspi; }; @@ -353,6 +403,8 @@ struct rzg2l_pinctrl { struct clk *clk; + struct regmap *syscon; + struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); @@ -366,6 +418,7 @@ struct rzg2l_pinctrl { struct rzg2l_pinctrl_reg_cache *cache; struct rzg2l_pinctrl_reg_cache *dedicated_cache; atomic_t wakeup_path; + u32 clone_offset; }; static const u16 available_ps[] = { 1800, 2500, 3300 }; @@ -388,6 +441,60 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, return 0; } +static const u64 r9a08g046_variable_pin_cfg[] = { + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) | PIN_CFG_OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG3L_MPXED_PIN_FUNCS(B)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 6, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 7, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG3L_MPXED_PIN_FUNCS(B)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 0, RZG3L_MPXED_PIN_FUNCS(A) | PIN_CFG_IEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 1, RZG3L_MPXED_PIN_FUNCS(A)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 2, RZG3L_MPXED_PIN_FUNCS(A)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 3, RZG3L_MPXED_PIN_FUNCS(A)), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 4, RZG3L_MPXED_PIN_FUNCS(A)), +}; + static const u64 r9a09g047_variable_pin_cfg[] = { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS), @@ -537,6 +644,45 @@ static int rzg2l_validate_pin(struct rzg2l_pinctrl *pctrl, return 0; } +static int rzg2l_pinctrl_set_clone_mode(struct rzg2l_pinctrl *pctrl, + u8 port, u8 pin, u8 func) +{ + unsigned int i; + + if (!pctrl->data->clone_channel_data) + return 0; + + switch (func) { + case 2: + case 4 ... 7: + break; + default: + return 0; + } + + for (i = 0; i < pctrl->data->n_clone_channel_data; i++) { + u32 pin_data = pctrl->data->clone_channel_data[i]; + unsigned int pin_func_mask = FIELD_GET(RZG3L_CLONE_CHANNEL_PFC_MASK, pin_data); + unsigned int pin_mask = FIELD_GET(RZG3L_CLONE_CHANNEL_PIN_MASK, pin_data); + u32 bit, val; + + if (!(pin_func_mask & BIT(func)) || + FIELD_GET(RZG3L_CLONE_CHANNEL_PORT_MASK, pin_data) != port) + continue; + + if (!(pin_mask & BIT(pin))) + continue; + + bit = FIELD_GET(RZG3L_CLONE_CHANNEL_BIT_MASK, pin_data); + val = FIELD_GET(RZG3L_CLONE_CHANNEL_VAL_MASK, pin_data); + + return regmap_update_bits(pctrl->syscon, pctrl->clone_offset, + BIT(bit), val << bit); + } + + return 0; +} + static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -601,16 +747,22 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, for (i = 0; i < group->grp.npins; i++) { u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); + u32 port = RZG2L_PIN_ID_TO_PORT(pins[i]); u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); + unsigned int func; - ret = rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(pins[i]), pin); + ret = rzg2l_validate_pin(pctrl, *pin_data, port, pin); if (ret) return ret; - dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", - RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base); + func = psel_val[i] - hwcfg->func_base; + dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", port, pin, off, func); - rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); + ret = rzg2l_pinctrl_set_clone_mode(pctrl, port, pin, func); + if (ret) + return ret; + + rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, func); } return 0; @@ -894,7 +1046,8 @@ static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, raw_spin_unlock_irqrestore(&pctrl->lock, flags); } -static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps) +static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, + u32 caps, u8 *mask) { if (caps & PIN_CFG_IO_VMC_SD0) return SD_CH(regs->sd_ch, 0); @@ -906,6 +1059,16 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 return ETH_POC(regs->eth_poc, 1); if (caps & PIN_CFG_IO_VMC_QSPI) return QSPI; + if (caps & PIN_CFG_OTHER_POC_MASK) { + if (caps & PIN_CFG_PVDD1833_OTH_AWO_POC) + *mask = BIT(0); + else if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC) + *mask = BIT(1); + else + *mask = BIT(2); + + return OTHER_POC; + } return -EINVAL; } @@ -914,17 +1077,20 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps { const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs = &hwcfg->regs; + u8 val, mask; int pwr_reg; - u8 val; if (caps & PIN_CFG_SOFT_PS) return pctrl->settings[pin].power_source; - pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); + pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask); if (pwr_reg < 0) return pwr_reg; val = readb(pctrl->base + pwr_reg); + if (pwr_reg == OTHER_POC) + val = field_get(mask, val); + switch (val) { case PVDD_1800: return 1800; @@ -942,8 +1108,8 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps { const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs = &hwcfg->regs; + u8 poc_val, val, mask; int pwr_reg; - u8 val; if (caps & PIN_CFG_SOFT_PS) { pctrl->settings[pin].power_source = ps; @@ -952,25 +1118,37 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps switch (ps) { case 1800: - val = PVDD_1800; + poc_val = PVDD_1800; break; case 2500: if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1))) return -EINVAL; - val = PVDD_2500; + poc_val = PVDD_2500; break; case 3300: - val = PVDD_3300; + poc_val = PVDD_3300; break; default: return -EINVAL; } - pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); + pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask); if (pwr_reg < 0) return pwr_reg; - writeb(val, pctrl->base + pwr_reg); + if (pwr_reg == OTHER_POC) { + scoped_guard(raw_spinlock, &pctrl->lock) { + val = readb(pctrl->base + pwr_reg); + if (poc_val) + val |= mask; + else + val &= ~mask; + writeb(val, pctrl->base + pwr_reg); + } + } else { + writeb(poc_val, pctrl->base + pwr_reg); + } + pctrl->settings[pin].power_source = ps; return 0; @@ -1083,7 +1261,7 @@ static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin) u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data); u8 pin = RZG2L_PIN_ID_TO_PIN(_pin); - if (pin > pctrl->data->hwcfg->oen_max_pin) + if (pin != pctrl->data->hwcfg->oen_max_pin) return -EINVAL; /* @@ -1643,8 +1821,9 @@ static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *config) { + unsigned long prev_config = 0; const unsigned int *pins; - unsigned int i, npins, prev_config = 0; + unsigned int i, npins; int ret; ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); @@ -2089,6 +2268,70 @@ static const u64 r9a09g047_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */ }; +static const char * const rzg3l_gpio_names[] = { + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27", + "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37", + "", "", "", "", "", "", "", "", + "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57", + "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67", + "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77", + "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87", + "", "", "", "", "", "", "", "", + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", + "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", + "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7", + "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7", + "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7", + "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7", + "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7", + "", "", "", "", "", "", "", "", + "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7", + "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7", + "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7", + "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7", +}; + +static const u64 r9a08g046_gpio_configs[] = { + 0x0, + 0x0, + RZG2L_GPIO_PORT_PACK(2, 0x22, PIN_CFG_NF | PIN_CFG_IEN), /* P2 */ + RZG2L_GPIO_PORT_PACK(7, 0x23, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P3 */ + 0x0, + RZG2L_GPIO_PORT_PACK(7, 0x25, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P5 */ + RZG2L_GPIO_PORT_PACK(7, 0x26, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P6 */ + RZG2L_GPIO_PORT_PACK(8, 0x27, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P7 */ + RZG2L_GPIO_PORT_PACK(6, 0x28, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P8 */ + 0x0, + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */ + RZG2L_GPIO_PORT_PACK(3, 0x2c, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)), /* PC */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */ + RZG2L_GPIO_PORT_PACK(3, 0x2f, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)), /* PF */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */ + RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */ + 0x0, + RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */ + RZG2L_GPIO_PORT_PACK(4, 0x34, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)), /* PK */ + RZG2L_GPIO_PORT_PACK(5, 0x35, RZG3L_MPXED_PIN_FUNCS(C)), /* PL */ + RZG2L_GPIO_PORT_PACK(8, 0x36, RZG3L_MPXED_PIN_FUNCS(C)), /* PM */ + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + RZG2L_GPIO_PORT_PACK(2, 0x3c, RZG3L_MPXED_PIN_FUNCS(A)), /* PS */ +}; + static const char * const rzv2h_gpio_names[] = { "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07", "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17", @@ -2427,6 +2670,128 @@ static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = { (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, }; +static const struct rzg2l_dedicated_configs rzg3l_dedicated_pins[] = { + { "WDTOVF_N", RZG2L_SINGLE_PIN_PACK(0x5, 0, + (PIN_CFG_IOLH_A | PIN_CFG_WDTOVF_N_POC)) }, + { "SCIF0_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, + (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, + { "SCIF0_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, + (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) }, + { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, PIN_CFG_IOLH_B) }, + { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x9, 2, PIN_CFG_IOLH_B) }, + { "SD0_DS", RZG2L_SINGLE_PIN_PACK(0x9, 5, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT0", RZG2L_SINGLE_PIN_PACK(0x0a, 0, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT1", RZG2L_SINGLE_PIN_PACK(0x0a, 1, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT2", RZG2L_SINGLE_PIN_PACK(0x0a, 2, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT3", RZG2L_SINGLE_PIN_PACK(0x0a, 3, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT4", RZG2L_SINGLE_PIN_PACK(0x0a, 4, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT5", RZG2L_SINGLE_PIN_PACK(0x0a, 5, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT6", RZG2L_SINGLE_PIN_PACK(0x0a, 6, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, + { "SD0_DAT7", RZG2L_SINGLE_PIN_PACK(0x0a, 7, + (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) }, +}; + +static const u32 r9a08g046_clone_channel_data[] = { + /* I2C ch2 Bit:0 Value:0 PFC:4 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(7, 6), 0, 0, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(3, 2), 0, 0, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(1, 0), 0, 0, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(5, 4) | GENMASK(1, 0), 0, 0, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(5, 4) | GENMASK(1, 0), 0, 0, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, GENMASK(1, 0), 0, 0, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 6) | GENMASK(3, 2), 0, 0, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 6) | GENMASK(3, 2), 0, 0, BIT(4)), + /* I2C ch2 Bit:0 Value:1 PFC:4 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(5, 4) | GENMASK(1, 0), 0, 1, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | GENMASK(2, 1), 0, 1, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 4) | GENMASK(1, 0), 0, 1, BIT(4)), + /* I2C ch3 Bit:1 Value:0 PFC:4 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 1, 0, BIT(4)), + /* I2C ch3 Bit:1 Value:1 PFC:4 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P2, GENMASK(1, 0), 1, 1, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, BIT(6) | GENMASK(3, 2), 1, 1, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 3) | BIT(0), 1, 1, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 6), 1, 1, BIT(4)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(3, 2), 1, 1, BIT(4)), + /* SCIF ch3 Bit:4 Value:0 PFC:{6,7} */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(6, 4), 4, 0, BIT(6)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(5, 3), 4, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(4, 2), 4, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(5, 3), 4, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(2, 0), 4, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 1), 4, 0, BIT(7)), + /* SCIF ch3 Bit:4 Value:1 PFC:7 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(2, 0), 4, 1, BIT(7)), + /* SCIF ch4 Bit:5 Value:0 PFC:7 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(2, 0), 5, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(7, 5), 5, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(7, 6), 5, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, BIT(0), 5, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(5, 3), 5, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(6, 4), 5, 0, BIT(7)), + /* SCIF ch4 Bit:5 Value:1 PFC:7 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(5, 3), 5, 1, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 2), 5, 1, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 5), 5, 1, BIT(7)), + /* SCIF ch5 Bit:6 Value:0 PFC:7 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, BIT(7), 6, 0, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 6, 0, BIT(7)), + /* SCIF ch5 Bit:6 Value:1 PFC:7 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, BIT(6), 6, 1, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | GENMASK(1, 0), 6, 1, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(4, 2) | BIT(0), 6, 1, BIT(7)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(2, 0), 6, 1, BIT(7)), + /* RSPI ch1 Bit:8 Value:0 PFC:2 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(5, 0), 8, 0, BIT(2)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 5), 8, 0, BIT(2)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 0), 8, 0, BIT(2)), + /* RSPI ch1 Bit:8 Value:1 PFC:2 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(6, 0), 8, 1, BIT(2)), + /* RSPI ch2 Bit:9 Value:0 PFC:2 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 4), 9, 0, BIT(2)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(2, 0), 9, 0, BIT(2)), + /* RSPI ch2 Bit:9 Value:1 PFC:2 */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 0), 9, 1, BIT(2)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, BIT(7), 9, 1, BIT(2)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 0), 9, 1, BIT(2)), + /* RSCI ch1 Bit:12 Value:0 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(3, 0), 12, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(3, 0), 12, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(7, 6), 12, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, GENMASK(1, 0), 12, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 4), 12, 0, GENMASK(6, 5)), + /* RSCI ch1 Bit:12 Value:1 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(3, 0), 12, 1, GENMASK(6, 5)), + /* RSCI ch2 Bit:13 Value:0 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(3, 0), 13, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(3, 0), 13, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(7, 4), 13, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(3, 0), 13, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 0), 13, 0, GENMASK(6, 5)), + /* RSCI ch2 Bit:13 Value:1 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(6, 4), 13, 1, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | BIT(0), 13, 1, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 6) | GENMASK(1, 0), 13, 1, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(1, 0), 13, 1, GENMASK(6, 5)), + /* RSCI ch3 Bit:14 Value:0 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 6), 14, 0, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 14, 0, GENMASK(6, 5)), + /* RSCI ch3 Bit:14 Value:1 PFC:{5,6} shared pins based on RSCI mode */ + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 1), 14, 1, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(5, 2), 14, 1, GENMASK(6, 5)), + RZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 2), 14, 1, GENMASK(6, 5)), +}; + static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) { const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; @@ -2737,10 +3102,6 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) if (!cache->pfc) return -ENOMEM; - cache->smt = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt), GFP_KERNEL); - if (!cache->smt) - return -ENOMEM; - for (u8 i = 0; i < 2; i++) { u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; @@ -2759,6 +3120,21 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) if (!cache->pupd[i]) return -ENOMEM; + cache->smt[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt[i]), + GFP_KERNEL); + if (!cache->smt[i]) + return -ENOMEM; + + cache->sr[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->sr[i]), + GFP_KERNEL); + if (!cache->sr[i]) + return -ENOMEM; + + cache->nod[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->nod[i]), + GFP_KERNEL); + if (!cache->nod[i]) + return -ENOMEM; + /* Allocate dedicated cache. */ dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, sizeof(*dedicated_cache->iolh[i]), @@ -2771,6 +3147,24 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) GFP_KERNEL); if (!dedicated_cache->ien[i]) return -ENOMEM; + + dedicated_cache->sr[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, + sizeof(*dedicated_cache->sr[i]), + GFP_KERNEL); + if (!dedicated_cache->sr[i]) + return -ENOMEM; + + dedicated_cache->nod[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, + sizeof(*dedicated_cache->nod[i]), + GFP_KERNEL); + if (!dedicated_cache->nod[i]) + return -ENOMEM; + + dedicated_cache->pupd[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, + sizeof(*dedicated_cache->pupd[i]), + GFP_KERNEL); + if (!dedicated_cache->pupd[i]) + return -ENOMEM; } pctrl->cache = cache; @@ -2955,6 +3349,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzg2l_gpio_names)); + BUILD_BUG_ON(ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg3l_gpio_names)); + BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT > ARRAY_SIZE(rzg3e_gpio_names)); @@ -2981,6 +3378,16 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) "failed to enable GPIO clk\n"); } + if (pctrl->data->clone_channel_data) { + struct device_node *np = pctrl->dev->of_node; + + pctrl->syscon = syscon_regmap_lookup_by_phandle_args(np, "renesas,clonech", + 1, &pctrl->clone_offset); + if (IS_ERR(pctrl->syscon)) + return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->syscon), + "Failed to parse renesas,clonech\n"); + } + raw_spin_lock_init(&pctrl->lock); spin_lock_init(&pctrl->bitmap_lock); mutex_init(&pctrl->mutex); @@ -3002,7 +3409,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; for (u32 port = 0; port < nports; port++) { - bool has_iolh, has_ien, has_pupd, has_smt; + bool has_iolh, has_ien, has_pupd, has_smt, has_sr, has_nod; u32 off, caps; u8 pincnt; u64 cfg; @@ -3023,6 +3430,8 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen has_ien = !!(caps & PIN_CFG_IEN); has_pupd = !!(caps & PIN_CFG_PUPD); has_smt = !!(caps & PIN_CFG_SMT); + has_sr = !!(caps & PIN_CFG_SR); + has_nod = !!(caps & PIN_CFG_NOD); if (suspend) RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); @@ -3049,7 +3458,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), cache->pupd[0][port]); if (pincnt >= 4) { - RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off) + 4, cache->pupd[1][port]); } } @@ -3066,8 +3475,32 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen } } - if (has_smt) - RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), cache->smt[port]); + if (has_smt) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), + cache->smt[0][port]); + if (pincnt >= 4) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off) + 4, + cache->smt[1][port]); + } + } + + if (has_sr) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off), + cache->sr[0][port]); + if (pincnt >= 4) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off) + 4, + cache->sr[1][port]); + } + } + + if (has_nod) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off), + cache->nod[0][port]); + if (pincnt >= 4) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off) + 4, + cache->nod[1][port]); + } + } } } @@ -3082,7 +3515,7 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b * port offset are close together. */ for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { - bool has_iolh, has_ien; + bool has_iolh, has_ien, has_sr, has_nod, has_pupd; u32 off, next_off = 0; u64 cfg, next_cfg; u8 pincnt; @@ -3101,8 +3534,12 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b } /* And apply them in a single shot. */ - has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); + has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | + PIN_CFG_IOLH_C | PIN_CFG_IOLH_RZV2H)); has_ien = !!(caps & PIN_CFG_IEN); + has_sr = !!(caps & PIN_CFG_SR); + has_nod = !!(caps & PIN_CFG_NOD); + has_pupd = !!(caps & PIN_CFG_PUPD); pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg)); if (has_iolh) { @@ -3113,6 +3550,18 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), cache->ien[0][i]); } + if (has_sr) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off), + cache->sr[0][i]); + } + if (has_nod) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + NOD(off), + cache->nod[0][i]); + } + if (has_pupd) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off), + cache->pupd[0][i]); + } if (pincnt >= 4) { if (has_iolh) { @@ -3125,6 +3574,21 @@ static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, b pctrl->base + IEN(off) + 4, cache->ien[1][i]); } + if (has_sr) { + RZG2L_PCTRL_REG_ACCESS32(suspend, + pctrl->base + SR(off) + 4, + cache->sr[1][i]); + } + if (has_nod) { + RZG2L_PCTRL_REG_ACCESS32(suspend, + pctrl->base + NOD(off) + 4, + cache->nod[1][i]); + } + if (has_pupd) { + RZG2L_PCTRL_REG_ACCESS32(suspend, + pctrl->base + PUPD(off) + 4, + cache->pupd[1][i]); + } } caps = 0; } @@ -3207,8 +3671,19 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev) cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); } - cache->qspi = readb(pctrl->base + QSPI); + if (regs->qspi) + cache->qspi = readb(pctrl->base + regs->qspi); cache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen); + if (regs->other_poc) + cache->other_poc = readb(pctrl->base + regs->other_poc); + + if (pctrl->syscon) { + int ret; + + ret = regmap_read(pctrl->syscon, pctrl->clone_offset, &cache->clone); + if (ret) + return ret; + } if (!atomic_read(&pctrl->wakeup_path)) clk_disable_unprepare(pctrl->clk); @@ -3227,13 +3702,22 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) unsigned long flags; int ret; + if (pctrl->syscon) { + ret = regmap_write(pctrl->syscon, pctrl->clone_offset, cache->clone); + if (ret) + return ret; + } + if (!atomic_read(&pctrl->wakeup_path)) { ret = clk_prepare_enable(pctrl->clk); if (ret) return ret; } - writeb(cache->qspi, pctrl->base + QSPI); + if (regs->qspi) + writeb(cache->qspi, pctrl->base + regs->qspi); + if (regs->other_poc) + writeb(cache->other_poc, pctrl->base + regs->other_poc); raw_spin_lock_irqsave(&pctrl->lock, flags); rzg2l_oen_write_with_pwpr(pctrl, cache->oen); @@ -3291,6 +3775,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { .sd_ch = 0x3000, .eth_poc = 0x300c, .oen = 0x3018, + .qspi = QSPI, }, .iolh_groupa_ua = { /* 3v3 power source */ @@ -3301,6 +3786,40 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { .oen_max_pin = 0, }; +static const struct rzg2l_hwcfg rzg3l_hwcfg = { + .regs = { + .pwpr = 0x3000, + .sd_ch = 0x3004, + .eth_poc = 0x3010, + .oen = 0x3018, + .other_poc = OTHER_POC, + }, + .iolh_groupa_ua = { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000, + }, + .iolh_groupb_ua = { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000, + }, + .iolh_groupc_ua = { + /* 1v8 power source */ + [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800, + /* 2v5 source */ + [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100, + /* 3v3 power source */ + [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050, + }, + .tint_start_index = 17, + .drive_strength_ua = true, + .func_base = 0, + .oen_max_pin = 1, /* Pin 1 of P{B,E}1_ISO is the maximum OEN pin. */ +}; + static const struct rzg2l_hwcfg rzg3s_hwcfg = { .regs = { .pwpr = 0x3000, @@ -3394,6 +3913,25 @@ static struct rzg2l_pinctrl_data r9a08g045_data = { .bias_param_to_hw = &rzg2l_bias_param_to_hw, }; +static struct rzg2l_pinctrl_data r9a08g046_data = { + .port_pins = rzg3l_gpio_names, + .port_pin_configs = r9a08g046_gpio_configs, + .n_ports = ARRAY_SIZE(r9a08g046_gpio_configs), + .variable_pin_cfg = r9a08g046_variable_pin_cfg, + .n_variable_pin_cfg = ARRAY_SIZE(r9a08g046_variable_pin_cfg), + .dedicated_pins = rzg3l_dedicated_pins, + .n_port_pins = ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins = ARRAY_SIZE(rzg3l_dedicated_pins), + .clone_channel_data = r9a08g046_clone_channel_data, + .n_clone_channel_data = ARRAY_SIZE(r9a08g046_clone_channel_data), + .hwcfg = &rzg3l_hwcfg, + .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock, + .pmc_writeb = &rzg2l_pmc_writeb, + .pin_to_oen_bit = &rzg2l_pin_to_oen_bit, + .hw_to_bias_param = &rzg2l_hw_to_bias_param, + .bias_param_to_hw = &rzg2l_bias_param_to_hw, +}; + static struct rzg2l_pinctrl_data r9a09g047_data = { .port_pins = rzg3e_gpio_names, .port_pin_configs = r9a09g047_gpio_configs, @@ -3474,6 +4012,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = { .compatible = "renesas,r9a08g045-pinctrl", .data = &r9a08g045_data, }, + { + .compatible = "renesas,r9a08g046-pinctrl", + .data = &r9a08g046_data, + }, { .compatible = "renesas,r9a09g047-pinctrl", .data = &r9a09g047_data, diff --git a/drivers/pinctrl/renesas/pinctrl-rzv2m.c b/drivers/pinctrl/renesas/pinctrl-rzv2m.c index 495e7f5d4128..827b3e91a6cc 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzv2m.c +++ b/drivers/pinctrl/renesas/pinctrl-rzv2m.c @@ -695,8 +695,9 @@ static int rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *config) { + unsigned long prev_config = 0; const unsigned int *pins; - unsigned int i, npins, prev_config = 0; + unsigned int i, npins; int ret; ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index 3a742f74ecd1..8585ed4bcfe0 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -719,6 +719,30 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, return 0; } +static int sh_pfc_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, unsigned long *config) +{ + struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pins = pmx->pfc->info->groups[group].pins; + unsigned int num_pins = pmx->pfc->info->groups[group].nr_pins; + unsigned long prev_config = 0; + int ret; + + for (unsigned int i = 0; i < num_pins; ++i) { + ret = sh_pfc_pinconf_get(pctldev, pins[i], config); + if (ret) + return ret; + + /* configs should match for all pins in the group */ + if (i && prev_config != *config) + return -ENOTSUPP; + + prev_config = *config; + } + + return 0; +} + static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, unsigned long *configs, unsigned num_configs) @@ -745,6 +769,7 @@ static const struct pinconf_ops sh_pfc_pinconf_ops = { .is_generic = true, .pin_config_get = sh_pfc_pinconf_get, .pin_config_set = sh_pfc_pinconf_set, + .pin_config_group_get = sh_pfc_pinconf_group_get, .pin_config_group_set = sh_pfc_pinconf_group_set, .pin_config_config_dbg_show = pinconf_generic_dump_config, }; diff --git a/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h new file mode 100644 index 000000000000..5ec5bfc27c7d --- /dev/null +++ b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G3L family pinctrl bindings. + * + * Copyright (C) 2026 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ +#define __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ + +#include + +/* RZG3L_Px = Offset address of PFC_P_mn - 0x22 */ +#define RZG3L_P2 2 +#define RZG3L_P3 3 +#define RZG3L_P5 5 +#define RZG3L_P6 6 +#define RZG3L_P7 7 +#define RZG3L_P8 8 +#define RZG3L_PA 10 +#define RZG3L_PB 11 +#define RZG3L_PC 12 +#define RZG3L_PD 13 +#define RZG3L_PE 14 +#define RZG3L_PF 15 +#define RZG3L_PG 16 +#define RZG3L_PH 17 +#define RZG3L_PJ 19 +#define RZG3L_PK 20 +#define RZG3L_PL 21 +#define RZG3L_PM 22 +#define RZG3L_PS 28 + +#define RZG3L_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3L_P##b, p, f) +#define RZG3L_GPIO(port, pin) RZG2L_GPIO(RZG3L_P##port, pin) + +#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ */