From cca3731e026a6b540bf651c6f59d37bd4e4198a0 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 16 May 2019 17:07:50 -0500 Subject: [PATCH 1/4] ARM: dts: socfpga: use the "altr,socfpga-stmmac-a10-s10" binding Because of register and bits difference for setting PHY modes, PTP reference clock, and FPGA signalling, the Arria10 SoC needs to use the "altr,socfpga-stmmac-a10-s10" binding to set the correct modes. On Arria10, each EMAC has its own register for PHY modes, and they all have the same offset, thus we can use the 2nd parameter to specify the offsets for the FPGA signal bits. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index ae24599d5829..61a767c905b3 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -418,7 +418,7 @@ socfpga_axi_setup: stmmac-axi-config { }; gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; altr,sysmgr-syscon = <&sysmgr 0x44 0>; reg = <0xff800000 0x2000>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; @@ -438,8 +438,8 @@ gmac0: ethernet@ff800000 { }; gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x48 0>; + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x48 8>; reg = <0xff802000 0x2000>; interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; @@ -458,8 +458,8 @@ gmac1: ethernet@ff802000 { }; gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; - altr,sysmgr-syscon = <&sysmgr 0x4C 0>; + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; + altr,sysmgr-syscon = <&sysmgr 0x4C 16>; reg = <0xff804000 0x2000>; interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; From 9aa0cae1d458278a75008885654a0e240020598c Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 16 May 2019 17:30:00 -0500 Subject: [PATCH 2/4] arm64: dts: stratix10: use the "altr,socfpga-stmmac-a10-s10" binding Because of register and bits difference for setting PHY modes, PTP reference clock, and FPGA signalling, the Stratix10 SoC needs to use the "altr,socfpga-stmmac-a10-s10" binding to set the correct modes. On Stratix10, each EMAC has its own register for PHY modes, and they all have the same offset, thus we can use the 2nd parameter to specify the offsets for the FPGA signal bits. Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index fe107ce115ef..a781e699a538 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -149,7 +149,7 @@ qspi_clk: qspi-clk { }; gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; reg = <0xff800000 0x2000>; interrupts = <0 90 4>; interrupt-names = "macirq"; @@ -167,7 +167,7 @@ gmac0: ethernet@ff800000 { }; gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; reg = <0xff802000 0x2000>; interrupts = <0 91 4>; interrupt-names = "macirq"; @@ -180,12 +180,12 @@ gmac1: ethernet@ff802000 { rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; iommus = <&smmu 2>; - altr,sysmgr-syscon = <&sysmgr 0x48 0>; + altr,sysmgr-syscon = <&sysmgr 0x48 8>; status = "disabled"; }; gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; reg = <0xff804000 0x2000>; interrupts = <0 92 4>; interrupt-names = "macirq"; @@ -198,7 +198,7 @@ gmac2: ethernet@ff804000 { rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; iommus = <&smmu 3>; - altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + altr,sysmgr-syscon = <&sysmgr 0x4c 16>; status = "disabled"; }; From d9b9f805ee2b63a9d0297c11e168cb303f15f717 Mon Sep 17 00:00:00 2001 From: Alan Tull Date: Wed, 24 Apr 2019 10:39:15 -0500 Subject: [PATCH 3/4] ARM: dts: socfpga: add ltc2497 on arria10 devkit Add the two ltc2497 devices that are on the SoCFPGA Arria10 Socdk board at addresses 0x14 and 0x16. Signed-off-by: Alan Tull Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 360dae5a5b12..0efbeccc5cd2 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -48,6 +48,13 @@ a10sr_led3 { }; }; + ref_033v: 033-v-ref { + compatible = "regulator-fixed"; + regulator-name = "0.33V"; + regulator-min-microvolt = <330000>; + regulator-max-microvolt = <330000>; + }; + soc { clkmgr@ffd04000 { clocks { @@ -128,6 +135,18 @@ &i2c1 { i2c-sda-falling-time-ns = <6000>; i2c-scl-falling-time-ns = <6000>; + adc@14 { + compatible = "lltc,ltc2497"; + reg = <0x14>; + vref-supply = <&ref_033v>; + }; + + adc@16 { + compatible = "lltc,ltc2497"; + reg = <0x16>; + vref-supply = <&ref_033v>; + }; + eeprom@51 { compatible = "atmel,24c32"; reg = <0x51>; From c946feaabbdd05b949756cd209ac3937f98aa148 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 29 Apr 2019 12:33:02 -0500 Subject: [PATCH 4/4] ARM: dts: arria10: Add EMAC OCP reset property Add the EMAC's OCP reset property on Arria10. The OCP reset bits are also needed to correctly bring the EMACs out of reset correctly. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 61a767c905b3..a0a6d8507265 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -431,8 +431,8 @@ gmac0: ethernet@ff800000 { rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; clock-names = "stmmaceth"; - resets = <&rst EMAC0_RESET>; - reset-names = "stmmaceth"; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -451,8 +451,8 @@ gmac1: ethernet@ff802000 { rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; clock-names = "stmmaceth"; - resets = <&rst EMAC1_RESET>; - reset-names = "stmmaceth"; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -470,8 +470,9 @@ gmac2: ethernet@ff804000 { tx-fifo-depth = <4096>; rx-fifo-depth = <16384>; clocks = <&l4_mp_clk>; - resets = <&rst EMAC2_RESET>; clock-names = "stmmaceth"; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; };