From d8dfc3bd461def65fbd180acab7c49a8d8394d7b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 27 Jun 2019 08:48:19 -0500 Subject: [PATCH 01/10] drm/amdgpu: fix warning on 32 bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Properly cast pointer to int. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index c441e6ce95ec..988c0adaca91 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -1010,8 +1010,8 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) if (indirect) psp_update_vcn_sram(adev, 0, adev->vcn.dpg_sram_gpu_addr, - (uint32_t)((uint64_t)adev->vcn.dpg_sram_curr_addr - - (uint64_t)adev->vcn.dpg_sram_cpu_addr)); + (uint32_t)((uintptr_t)adev->vcn.dpg_sram_curr_addr - + (uintptr_t)adev->vcn.dpg_sram_cpu_addr)); /* force RBC into idle state */ rb_bufsz = order_base_2(ring->ring_size); From 687ac4a702ea92873fb8c45acec0c30eae9acfa9 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 27 Jun 2019 09:13:41 -0500 Subject: [PATCH 02/10] drm/amdgpu: drop copy/paste leftover to fix big endian MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The buf swap field doesn't exist on RB1. Reviewed-by: Hawking Zhang Reviewed-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 0061a0e8ab78..2932ade7dbd0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -2624,9 +2624,6 @@ static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) rb_bufsz = order_base_2(ring->ring_size / 8); tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); -#ifdef __BIG_ENDIAN - tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, BUF_SWAP, 1); -#endif WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); /* Initialize the ring buffer's write pointers */ ring->wptr = 0; From f6319596535f157ce95504b193e0bfc3da7119e6 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 26 Jun 2019 02:32:43 -0400 Subject: [PATCH 03/10] drm/ttm: return -EBUSY if waiting for busy BO fails MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Returning -EAGAIN prevents ttm_bo_mem_space from trying alternate placements and can lead to live-locks in amdgpu_cs, retrying indefinitely and never succeeding. Fixes: d367bd2a5e2b12 ("drm/ttm: fix busy memory to fail other user v10") Signed-off-by: Felix Kuehling Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_bo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 6953dd264172..a7fd5a4955c9 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -827,7 +827,7 @@ static int ttm_mem_evict_wait_busy(struct ttm_buffer_object *busy_bo, if (!r) reservation_object_unlock(busy_bo->resv); - return r == -EDEADLK ? -EAGAIN : r; + return r == -EDEADLK ? -EBUSY : r; } static int ttm_mem_evict_first(struct ttm_bo_device *bdev, From b213646519f4988ac1f40468e3fba81f7de7ccd7 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Mon, 17 Jun 2019 17:27:49 +0800 Subject: [PATCH 04/10] drm/amd/powerplay: check prerequisite for VCN power gating VCN DPM is a necessary prerequisite for VCN power gating. Signed-off-by: Evan Quan Reviewed-by: Kevin Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 527f7fa442ef..137c2a34a606 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -574,15 +574,19 @@ static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable) struct smu_power_gate *power_gate = &smu_power->power_gate; if (enable && power_gate->uvd_gated) { - ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1); - if (ret) - return ret; + if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) { + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1); + if (ret) + return ret; + } power_gate->uvd_gated = false; } else { if (!enable && !power_gate->uvd_gated) { - ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn); - if (ret) - return ret; + if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) { + ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn); + if (ret) + return ret; + } power_gate->uvd_gated = true; } } From 505ac3039a184b53ddb16f25cd10cab67af633f5 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 25 Jun 2019 11:06:08 +0800 Subject: [PATCH 05/10] drm/amd/powerplay: support runtime ppfeatures setting on Navi10 Implement Navi10 backend for runtime ppfeatures status retrieving and setting support. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 165 +++++++++++++++++++++ 1 file changed, 165 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 137c2a34a606..27e5c8088f1b 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -1304,6 +1304,169 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_ return 0; } +static int navi10_get_ppfeature_status(struct smu_context *smu, + char *buf) +{ + static const char *ppfeature_name[] = { + "DPM_PREFETCHER", + "DPM_GFXCLK", + "DPM_GFX_PACE", + "DPM_UCLK", + "DPM_SOCCLK", + "DPM_MP0CLK", + "DPM_LINK", + "DPM_DCEFCLK", + "MEM_VDDCI_SCALING", + "MEM_MVDD_SCALING", + "DS_GFXCLK", + "DS_SOCCLK", + "DS_LCLK", + "DS_DCEFCLK", + "DS_UCLK", + "GFX_ULV", + "FW_DSTATE", + "GFXOFF", + "BACO", + "VCN_PG", + "JPEG_PG", + "USB_PG", + "RSMU_SMN_CG", + "PPT", + "TDC", + "GFX_EDC", + "APCC_PLUS", + "GTHR", + "ACDC", + "VR0HOT", + "VR1HOT", + "FW_CTF", + "FAN_CONTROL", + "THERMAL", + "GFX_DCS", + "RM", + "LED_DISPLAY", + "GFX_SS", + "OUT_OF_BAND_MONITOR", + "TEMP_DEPENDENT_VMIN", + "MMHUB_PG", + "ATHUB_PG"}; + static const char *output_title[] = { + "FEATURES", + "BITMASK", + "ENABLEMENT"}; + uint64_t features_enabled; + uint32_t feature_mask[2]; + int i; + int ret = 0; + int size = 0; + + ret = smu_feature_get_enabled_mask(smu, feature_mask, 2); + PP_ASSERT_WITH_CODE(!ret, + "[GetPPfeatureStatus] Failed to get enabled smc features!", + return ret); + features_enabled = (uint64_t)feature_mask[0] | + (uint64_t)feature_mask[1] << 32; + + size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled); + size += sprintf(buf + size, "%-19s %-22s %s\n", + output_title[0], + output_title[1], + output_title[2]); + for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) { + size += sprintf(buf + size, "%-19s 0x%016llx %6s\n", + ppfeature_name[i], + 1ULL << i, + (features_enabled & (1ULL << i)) ? "Y" : "N"); + } + + return size; +} + +static int navi10_enable_smc_features(struct smu_context *smu, + bool enabled, + uint64_t feature_masks) +{ + struct smu_feature *feature = &smu->smu_feature; + uint32_t feature_low, feature_high; + uint32_t feature_mask[2]; + int ret = 0; + + feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF); + feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32); + + if (enabled) { + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow, + feature_low); + if (ret) + return ret; + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh, + feature_high); + if (ret) + return ret; + } else { + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow, + feature_low); + if (ret) + return ret; + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh, + feature_high); + if (ret) + return ret; + } + + ret = smu_feature_get_enabled_mask(smu, feature_mask, 2); + if (ret) + return ret; + + mutex_lock(&feature->mutex); + bitmap_copy(feature->enabled, (unsigned long *)&feature_mask, + feature->feature_num); + mutex_unlock(&feature->mutex); + + return 0; +} + +static int navi10_set_ppfeature_status(struct smu_context *smu, + uint64_t new_ppfeature_masks) +{ + uint64_t features_enabled; + uint32_t feature_mask[2]; + uint64_t features_to_enable; + uint64_t features_to_disable; + int ret = 0; + + ret = smu_feature_get_enabled_mask(smu, feature_mask, 2); + PP_ASSERT_WITH_CODE(!ret, + "[SetPPfeatureStatus] Failed to get enabled smc features!", + return ret); + features_enabled = (uint64_t)feature_mask[0] | + (uint64_t)feature_mask[1] << 32; + + features_to_disable = + features_enabled & ~new_ppfeature_masks; + features_to_enable = + ~features_enabled & new_ppfeature_masks; + + pr_debug("features_to_disable 0x%llx\n", features_to_disable); + pr_debug("features_to_enable 0x%llx\n", features_to_enable); + + if (features_to_disable) { + ret = navi10_enable_smc_features(smu, false, features_to_disable); + PP_ASSERT_WITH_CODE(!ret, + "[SetPPfeatureStatus] Failed to disable smc features!", + return ret); + } + + if (features_to_enable) { + ret = navi10_enable_smc_features(smu, true, features_to_enable); + PP_ASSERT_WITH_CODE(!ret, + "[SetPPfeatureStatus] Failed to enable smc features!", + return ret); + } + + return 0; +} + static const struct pptable_funcs navi10_ppt_funcs = { .tables_init = navi10_tables_init, .alloc_dpm_context = navi10_allocate_dpm_context, @@ -1337,6 +1500,8 @@ static const struct pptable_funcs navi10_ppt_funcs = { .set_watermarks_table = navi10_set_watermarks_table, .read_sensor = navi10_read_sensor, .get_uclk_dpm_states = navi10_get_uclk_dpm_states, + .get_ppfeature_status = navi10_get_ppfeature_status, + .set_ppfeature_status = navi10_set_ppfeature_status, }; void navi10_set_ppt_funcs(struct smu_context *smu) From 309bce0ca8bd5804db27bc2d56fb1e272c1a5359 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 25 Jun 2019 23:03:00 +0800 Subject: [PATCH 06/10] drm/amd/powerplay: add missing smu_get_clk_info_from_vbios() call This seems a merge error. Signed-off-by: Evan Quan Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index a0fb36360bea..31152d495f69 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -820,6 +820,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu, if (ret) return ret; + ret = smu_get_clk_info_from_vbios(smu); + if (ret) + return ret; + /* * check if the format_revision in vbios is up to pptable header * version, and the structure size is not 0. From f51af4357c4a15fc1aa1d9250935100b63a91d1e Mon Sep 17 00:00:00 2001 From: Oak Zeng Date: Wed, 26 Jun 2019 10:16:56 -0500 Subject: [PATCH 07/10] drm/amdgpu: Set queue_preemption_timeout_ms default value Set default value of this kernel parameter to 9000 Signed-off-by: Oak Zeng Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 92d415a4ee47..3913a75924c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -702,7 +702,7 @@ MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supp * DOC: queue_preemption_timeout_ms (int) * queue preemption timeout in ms (1 = Minimum, 9000 = default) */ -int queue_preemption_timeout_ms; +int queue_preemption_timeout_ms = 9000; module_param(queue_preemption_timeout_ms, int, 0644); MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); #endif From a864e29d94abac7f9756e07180c167f50fb00042 Mon Sep 17 00:00:00 2001 From: shaoyunl Date: Wed, 26 Jun 2019 13:42:24 -0400 Subject: [PATCH 08/10] drm/amdkfd: remove unnecessary warning message on gpu reset In XGMI configuration, more than one asic can be reset at same time, kfd is able to handle this and no need to trigger the warning Signed-off-by: shaoyunl Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 26ea46de3722..2e2f7241f381 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -738,7 +738,6 @@ int kgd2kfd_post_reset(struct kfd_dev *kfd) if (ret) return ret; count = atomic_dec_return(&kfd_locked); - WARN_ONCE(count != 0, "KFD reset ref. error"); atomic_set(&kfd->sram_ecc_flag, 0); From 4130ff8027dd679a6f2e45c26fb95860e6d235a3 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Fri, 21 Jun 2019 09:46:14 +0800 Subject: [PATCH 09/10] drm/amd/powerplay: no memory activity support on Vega10 Make mem_busy_percent sysfs interface invisible on Vega10. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 704c7034da09..193d53720d9b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -2886,7 +2886,8 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) return ret; } /* APU does not have its own dedicated memory */ - if (!(adev->flags & AMD_IS_APU)) { + if (!(adev->flags & AMD_IS_APU) && + (adev->asic_type != CHIP_VEGA10)) { ret = device_create_file(adev->dev, &dev_attr_mem_busy_percent); if (ret) { @@ -2966,7 +2967,8 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) device_remove_file(adev->dev, &dev_attr_pp_od_clk_voltage); device_remove_file(adev->dev, &dev_attr_gpu_busy_percent); - if (!(adev->flags & AMD_IS_APU)) + if (!(adev->flags & AMD_IS_APU) && + (adev->asic_type != CHIP_VEGA10)) device_remove_file(adev->dev, &dev_attr_mem_busy_percent); if (!(adev->flags & AMD_IS_APU)) device_remove_file(adev->dev, &dev_attr_pcie_bw); From 440e80ce02cde7b810e4eb555768c2d77e7a27c8 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Wed, 26 Jun 2019 14:24:27 +0100 Subject: [PATCH 10/10] drm/amd/display: fix a couple of spelling mistakes There are a couple of spelling mistakes in dm_error messages and a comment. Fix these. Signed-off-by: Colin Ian King Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 2 +- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c index be49fc7f4abe..ffd0014ec3b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c @@ -126,7 +126,7 @@ static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it. * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices. - * The value below is the absolute maximum value. The actual througput may be lower, but it'll always + * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always * be sufficient to process the input pixel rate fed into a single DSC engine. */ dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 77e7a0f8a527..ef5f84a144c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -47,7 +47,7 @@ static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_bl *buff_block_size = 64 * 1024; break; default: { - dm_error("%s: DPCD DSC buffer size not recoginzed.\n", __func__); + dm_error("%s: DPCD DSC buffer size not recognized.\n", __func__); return false; } } @@ -63,7 +63,7 @@ static bool dsc_line_buff_depth_from_dpcd(int dpcd_line_buff_bit_depth, int *lin else if (dpcd_line_buff_bit_depth == 8) *line_buff_bit_depth = 8; else { - dm_error("%s: DPCD DSC buffer depth not recoginzed.\n", __func__); + dm_error("%s: DPCD DSC buffer depth not recognized.\n", __func__); return false; } @@ -123,7 +123,7 @@ static bool dsc_throughput_from_dpcd(int dpcd_throughput, int *throughput) *throughput = 1000; break; default: { - dm_error("%s: DPCD DSC througput mode not recoginzed.\n", __func__); + dm_error("%s: DPCD DSC throughput mode not recognized.\n", __func__); return false; } } @@ -152,7 +152,7 @@ static bool dsc_bpp_increment_div_from_dpcd(int bpp_increment_dpcd, uint32_t *bp *bpp_increment_div = 1; break; default: { - dm_error("%s: DPCD DSC bits-per-pixel increment not recoginzed.\n", __func__); + dm_error("%s: DPCD DSC bits-per-pixel increment not recognized.\n", __func__); return false; } }