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scsi: hisi_sas: Use macro instead of magic number

Browse Source 
The hisi_sas driver has a large number of magic numbers which makes for
unfriendly code reading. Use macro definitions instead.

Signed-off-by: Yihang Li <liyihang9@huawei.com>
Link: https://lore.kernel.org/r/20250414080845.1220997-2-liyihang9@huawei.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Yihang Li
2025-04-14 16:08:42 +08:00
committed by Martin K. Petersen
parent 0af2f6be1b
commit 4ca7fe99fc
3 changed files with 213 additions and 115 deletions
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43
drivers/scsi/hisi_sas/hisi_sas.h
View File

@@ -46,6 +46,13 @@
#define HISI_SAS_IOST_ITCT_CACHE_DW_SZ 10 #define HISI_SAS_IOST_ITCT_CACHE_DW_SZ 10
#define HISI_SAS_FIFO_DATA_DW_SIZE 32 #define HISI_SAS_FIFO_DATA_DW_SIZE 32
#define HISI_SAS_REG_MEM_SIZE 4
#define HISI_SAS_MAX_CDB_LEN 16
#define HISI_SAS_BLK_QUEUE_DEPTH 64
#define BYTE_TO_DW 4
#define BYTE_TO_DDW 8
#define HISI_SAS_STATUS_BUF_SZ (sizeof(struct hisi_sas_status_buffer)) #define HISI_SAS_STATUS_BUF_SZ (sizeof(struct hisi_sas_status_buffer))
#define HISI_SAS_COMMAND_TABLE_SZ (sizeof(union hisi_sas_command_table)) #define HISI_SAS_COMMAND_TABLE_SZ (sizeof(union hisi_sas_command_table))
@@ -92,6 +99,8 @@
#define HISI_SAS_WAIT_PHYUP_TIMEOUT (30 * HZ) #define HISI_SAS_WAIT_PHYUP_TIMEOUT (30 * HZ)
#define HISI_SAS_CLEAR_ITCT_TIMEOUT (20 * HZ) #define HISI_SAS_CLEAR_ITCT_TIMEOUT (20 * HZ)
#define HISI_SAS_DELAY_FOR_PHY_DISABLE 100
#define NAME_BUF_SIZE 256
struct hisi_hba; struct hisi_hba;
@@ -167,6 +176,8 @@ struct hisi_sas_debugfs_fifo {
u32 rd_data[HISI_SAS_FIFO_DATA_DW_SIZE]; u32 rd_data[HISI_SAS_FIFO_DATA_DW_SIZE];
}; };
#define FRAME_RCVD_BUF 32
#define SAS_PHY_RESV_SIZE 2
struct hisi_sas_phy { struct hisi_sas_phy {
struct work_struct works[HISI_PHYES_NUM]; struct work_struct works[HISI_PHYES_NUM];
struct hisi_hba *hisi_hba; struct hisi_hba *hisi_hba;
@@ -178,10 +189,10 @@ struct hisi_sas_phy {
spinlock_t lock; spinlock_t lock;
u64 port_id; /* from hw */ u64 port_id; /* from hw */
u64 frame_rcvd_size; u64 frame_rcvd_size;
u8 frame_rcvd[32]; u8 frame_rcvd[FRAME_RCVD_BUF];
u8 phy_attached; u8 phy_attached;
u8 in_reset; u8 in_reset;
u8 reserved[2]; u8 reserved[SAS_PHY_RESV_SIZE];
u32 phy_type; u32 phy_type;
u32 code_violation_err_count; u32 code_violation_err_count;
enum sas_linkrate minimum_linkrate; enum sas_linkrate minimum_linkrate;
@@ -349,6 +360,7 @@ struct hisi_sas_hw {
}; };
#define HISI_SAS_MAX_DEBUGFS_DUMP (50) #define HISI_SAS_MAX_DEBUGFS_DUMP (50)
#define HISI_SAS_DEFAULT_DEBUGFS_DUMP 1
struct hisi_sas_debugfs_cq { struct hisi_sas_debugfs_cq {
struct hisi_sas_cq *cq; struct hisi_sas_cq *cq;
@@ -528,12 +540,13 @@ struct hisi_sas_cmd_hdr {
__le64 dif_prd_table_addr; __le64 dif_prd_table_addr;
}; };
#define ITCT_RESV_DDW 12
struct hisi_sas_itct { struct hisi_sas_itct {
__le64 qw0; __le64 qw0;
__le64 sas_addr; __le64 sas_addr;
__le64 qw2; __le64 qw2;
__le64 qw3; __le64 qw3;
__le64 qw4_15[12]; __le64 qw4_15[ITCT_RESV_DDW];
}; };
struct hisi_sas_iost { struct hisi_sas_iost {
@@ -543,22 +556,26 @@ struct hisi_sas_iost {
__le64 qw3; __le64 qw3;
}; };
#define ERROR_RECORD_BUF_DW 4
struct hisi_sas_err_record { struct hisi_sas_err_record {
u32 data[4]; u32 data[ERROR_RECORD_BUF_DW];
}; };
#define FIS_RESV_DW 3
struct hisi_sas_initial_fis { struct hisi_sas_initial_fis {
struct hisi_sas_err_record err_record; struct hisi_sas_err_record err_record;
struct dev_to_host_fis fis; struct dev_to_host_fis fis;
u32 rsvd[3]; u32 rsvd[FIS_RESV_DW];
}; };
#define BREAKPOINT_DATA_SIZE 128
struct hisi_sas_breakpoint { struct hisi_sas_breakpoint {
u8 data[128]; u8 data[BREAKPOINT_DATA_SIZE];
}; };
#define BREAKPOINT_TAG_NUM 32
struct hisi_sas_sata_breakpoint { struct hisi_sas_sata_breakpoint {
struct hisi_sas_breakpoint tag[32]; struct hisi_sas_breakpoint tag[BREAKPOINT_TAG_NUM];
}; };
struct hisi_sas_sge { struct hisi_sas_sge {
@@ -569,13 +586,15 @@ struct hisi_sas_sge {
__le32 data_off; __le32 data_off;
}; };
#define SMP_CMD_TABLE_SIZE 44
struct hisi_sas_command_table_smp { struct hisi_sas_command_table_smp {
u8 bytes[44]; u8 bytes[SMP_CMD_TABLE_SIZE];
}; };
#define DUMMY_BUF_SIZE 12
struct hisi_sas_command_table_stp { struct hisi_sas_command_table_stp {
struct host_to_dev_fis command_fis; struct host_to_dev_fis command_fis;
u8 dummy[12]; u8 dummy[DUMMY_BUF_SIZE];
u8 atapi_cdb[ATAPI_CDB_LEN]; u8 atapi_cdb[ATAPI_CDB_LEN];
}; };
@@ -589,12 +608,13 @@ struct hisi_sas_sge_dif_page {
struct hisi_sas_sge sge[HISI_SAS_SGE_DIF_PAGE_CNT]; struct hisi_sas_sge sge[HISI_SAS_SGE_DIF_PAGE_CNT];
} __aligned(16); } __aligned(16);
#define PROT_BUF_SIZE 7
struct hisi_sas_command_table_ssp { struct hisi_sas_command_table_ssp {
struct ssp_frame_hdr hdr; struct ssp_frame_hdr hdr;
union { union {
struct { struct {
struct ssp_command_iu task; struct ssp_command_iu task;
u32 prot[7]; u32 prot[PROT_BUF_SIZE];
}; };
struct ssp_tmf_iu ssp_task; struct ssp_tmf_iu ssp_task;
struct xfer_rdy_iu xfer_rdy; struct xfer_rdy_iu xfer_rdy;
@@ -608,9 +628,10 @@ union hisi_sas_command_table {
struct hisi_sas_command_table_stp stp; struct hisi_sas_command_table_stp stp;
} __aligned(16); } __aligned(16);
#define IU_BUF_SIZE 1024
struct hisi_sas_status_buffer { struct hisi_sas_status_buffer {
struct hisi_sas_err_record err; struct hisi_sas_err_record err;
u8 iu[1024]; u8 iu[IU_BUF_SIZE];
} __aligned(16); } __aligned(16);
struct hisi_sas_slot_buf_table { struct hisi_sas_slot_buf_table {

41
drivers/scsi/hisi_sas/hisi_sas_main.c
View File

@@ -7,6 +7,16 @@
#include "hisi_sas.h" #include "hisi_sas.h"
#define DRV_NAME "hisi_sas" #define DRV_NAME "hisi_sas"
#define LINK_RATE_BIT_MASK 2
#define FIS_BUF_SIZE 20
#define WAIT_CMD_COMPLETE_DELAY 100
#define WAIT_CMD_COMPLETE_TMROUT 5000
#define DELAY_FOR_LINK_READY 2000
#define BLK_CNT_OPTIMIZE_MARK 64
#define HZ_TO_MHZ 1000000
#define DELAY_FOR_SOFTRESET_MAX 1000
#define DELAY_FOR_SOFTRESET_MIN 900
#define DEV_IS_GONE(dev) \ #define DEV_IS_GONE(dev) \
((!dev) || (dev->dev_type == SAS_PHY_UNUSED)) ((!dev) || (dev->dev_type == SAS_PHY_UNUSED))
@@ -151,7 +161,7 @@ u8 hisi_sas_get_prog_phy_linkrate_mask(enum sas_linkrate max)
max -= SAS_LINK_RATE_1_5_GBPS; max -= SAS_LINK_RATE_1_5_GBPS;
for (i = 0; i <= max; i++) for (i = 0; i <= max; i++)
rate |= 1 << (i * 2); rate |= 1 << (i * LINK_RATE_BIT_MASK);
return rate; return rate;
} }
EXPORT_SYMBOL_GPL(hisi_sas_get_prog_phy_linkrate_mask); EXPORT_SYMBOL_GPL(hisi_sas_get_prog_phy_linkrate_mask);
@@ -900,7 +910,7 @@ int hisi_sas_sdev_configure(struct scsi_device *sdev, struct queue_limits *lim)
if (ret) if (ret)
return ret; return ret;
if (!dev_is_sata(dev)) if (!dev_is_sata(dev))
sas_change_queue_depth(sdev, 64); sas_change_queue_depth(sdev, HISI_SAS_BLK_QUEUE_DEPTH);
return 0; return 0;
} }
@@ -1242,7 +1252,7 @@ static int hisi_sas_phy_set_linkrate(struct hisi_hba *hisi_hba, int phy_no,
sas_phy->phy->minimum_linkrate = min; sas_phy->phy->minimum_linkrate = min;
hisi_sas_phy_enable(hisi_hba, phy_no, 0); hisi_sas_phy_enable(hisi_hba, phy_no, 0);
msleep(100); msleep(HISI_SAS_DELAY_FOR_PHY_DISABLE);
hisi_hba->hw->phy_set_linkrate(hisi_hba, phy_no, &_r); hisi_hba->hw->phy_set_linkrate(hisi_hba, phy_no, &_r);
hisi_sas_phy_enable(hisi_hba, phy_no, 1); hisi_sas_phy_enable(hisi_hba, phy_no, 1);
@@ -1272,7 +1282,7 @@ static int hisi_sas_control_phy(struct asd_sas_phy *sas_phy, enum phy_func func,
case PHY_FUNC_LINK_RESET: case PHY_FUNC_LINK_RESET:
hisi_sas_phy_enable(hisi_hba, phy_no, 0); hisi_sas_phy_enable(hisi_hba, phy_no, 0);
msleep(100); msleep(HISI_SAS_DELAY_FOR_PHY_DISABLE);
hisi_sas_phy_enable(hisi_hba, phy_no, 1); hisi_sas_phy_enable(hisi_hba, phy_no, 1);
break; break;
@@ -1327,7 +1337,7 @@ static void hisi_sas_fill_ata_reset_cmd(struct ata_device *dev,
static int hisi_sas_softreset_ata_disk(struct domain_device *device) static int hisi_sas_softreset_ata_disk(struct domain_device *device)
{ {
u8 fis[20] = {0}; u8 fis[FIS_BUF_SIZE] = {0};
struct ata_port *ap = device->sata_dev.ap; struct ata_port *ap = device->sata_dev.ap;
struct ata_link *link; struct ata_link *link;
int rc = TMF_RESP_FUNC_FAILED; int rc = TMF_RESP_FUNC_FAILED;
@@ -1344,7 +1354,7 @@ static int hisi_sas_softreset_ata_disk(struct domain_device *device)
} }
if (rc == TMF_RESP_FUNC_COMPLETE) { if (rc == TMF_RESP_FUNC_COMPLETE) {
usleep_range(900, 1000); usleep_range(DELAY_FOR_SOFTRESET_MIN, DELAY_FOR_SOFTRESET_MAX);
ata_for_each_link(link, ap, EDGE) { ata_for_each_link(link, ap, EDGE) {
int pmp = sata_srst_pmp(link); int pmp = sata_srst_pmp(link);
@@ -1474,7 +1484,7 @@ static void hisi_sas_send_ata_reset_each_phy(struct hisi_hba *hisi_hba,
struct device *dev = hisi_hba->dev; struct device *dev = hisi_hba->dev;
int rc = TMF_RESP_FUNC_FAILED; int rc = TMF_RESP_FUNC_FAILED;
struct ata_link *link; struct ata_link *link;
u8 fis[20] = {0}; u8 fis[FIS_BUF_SIZE] = {0};
int i; int i;
for (i = 0; i < hisi_hba->n_phy; i++) { for (i = 0; i < hisi_hba->n_phy; i++) {
@@ -1541,7 +1551,9 @@ void hisi_sas_controller_reset_prepare(struct hisi_hba *hisi_hba)
hisi_hba->phy_state = hisi_hba->hw->get_phys_state(hisi_hba); hisi_hba->phy_state = hisi_hba->hw->get_phys_state(hisi_hba);
scsi_block_requests(shost); scsi_block_requests(shost);
hisi_hba->hw->wait_cmds_complete_timeout(hisi_hba, 100, 5000); hisi_hba->hw->wait_cmds_complete_timeout(hisi_hba,
WAIT_CMD_COMPLETE_DELAY,
WAIT_CMD_COMPLETE_TMROUT);
/* /*
* hisi_hba->timer is only used for v1/v2 hw, and check hw->sht * hisi_hba->timer is only used for v1/v2 hw, and check hw->sht
@@ -1842,7 +1854,7 @@ static int hisi_sas_debug_I_T_nexus_reset(struct domain_device *device)
rc = ata_wait_after_reset(link, jiffies + HISI_SAS_WAIT_PHYUP_TIMEOUT, rc = ata_wait_after_reset(link, jiffies + HISI_SAS_WAIT_PHYUP_TIMEOUT,
smp_ata_check_ready_type); smp_ata_check_ready_type);
} else { } else {
msleep(2000); msleep(DELAY_FOR_LINK_READY);
} }
return rc; return rc;
@@ -2276,12 +2288,14 @@ int hisi_sas_alloc(struct hisi_hba *hisi_hba)
goto err_out; goto err_out;
/* roundup to avoid overly large block size */ /* roundup to avoid overly large block size */
max_command_entries_ru = roundup(max_command_entries, 64); max_command_entries_ru = roundup(max_command_entries,
BLK_CNT_OPTIMIZE_MARK);
if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK) if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK)
sz_slot_buf_ru = sizeof(struct hisi_sas_slot_dif_buf_table); sz_slot_buf_ru = sizeof(struct hisi_sas_slot_dif_buf_table);
else else
sz_slot_buf_ru = sizeof(struct hisi_sas_slot_buf_table); sz_slot_buf_ru = sizeof(struct hisi_sas_slot_buf_table);
sz_slot_buf_ru = roundup(sz_slot_buf_ru, 64);
sz_slot_buf_ru = roundup(sz_slot_buf_ru, BLK_CNT_OPTIMIZE_MARK);
s = max(lcm(max_command_entries_ru, sz_slot_buf_ru), PAGE_SIZE); s = max(lcm(max_command_entries_ru, sz_slot_buf_ru), PAGE_SIZE);
blk_cnt = (max_command_entries_ru * sz_slot_buf_ru) / s; blk_cnt = (max_command_entries_ru * sz_slot_buf_ru) / s;
slots_per_blk = s / sz_slot_buf_ru; slots_per_blk = s / sz_slot_buf_ru;
@@ -2446,7 +2460,8 @@ int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba)
if (IS_ERR(refclk)) if (IS_ERR(refclk))
dev_dbg(dev, "no ref clk property\n"); dev_dbg(dev, "no ref clk property\n");
else else
hisi_hba->refclk_frequency_mhz = clk_get_rate(refclk) / 1000000; hisi_hba->refclk_frequency_mhz = clk_get_rate(refclk) /
HZ_TO_MHZ;
if (device_property_read_u32(dev, "phy-count", &hisi_hba->n_phy)) { if (device_property_read_u32(dev, "phy-count", &hisi_hba->n_phy)) {
dev_err(dev, "could not get property phy-count\n"); dev_err(dev, "could not get property phy-count\n");
@@ -2568,7 +2583,7 @@ int hisi_sas_probe(struct platform_device *pdev,
shost->max_id = HISI_SAS_MAX_DEVICES; shost->max_id = HISI_SAS_MAX_DEVICES;
shost->max_lun = ~0; shost->max_lun = ~0;
shost->max_channel = 1; shost->max_channel = 1;
shost->max_cmd_len = 16; shost->max_cmd_len = HISI_SAS_MAX_CDB_LEN;
if (hisi_hba->hw->slot_index_alloc) { if (hisi_hba->hw->slot_index_alloc) {
shost->can_queue = HISI_SAS_MAX_COMMANDS; shost->can_queue = HISI_SAS_MAX_COMMANDS;
shost->cmd_per_lun = HISI_SAS_MAX_COMMANDS; shost->cmd_per_lun = HISI_SAS_MAX_COMMANDS;

244
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
View File

@@ -462,6 +462,12 @@
#define ITCT_HDR_RTOLT_OFF 48 #define ITCT_HDR_RTOLT_OFF 48
#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
/*debugfs*/
#define TWO_PARA_PER_LINE 2
#define FOUR_PARA_PER_LINE 4
#define DUMP_BUF_SIZE 8
#define BIST_BUF_SIZE 16
struct hisi_sas_protect_iu_v3_hw { struct hisi_sas_protect_iu_v3_hw {
u32 dw0; u32 dw0;
u32 lbrtcv; u32 lbrtcv;
@@ -532,6 +538,43 @@ struct hisi_sas_err_record_v3 {
#define BASE_VECTORS_V3_HW 16 #define BASE_VECTORS_V3_HW 16
#define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1) #define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1)
#define IRQ_PHY_UP_DOWN_INDEX 1
#define IRQ_CHL_INDEX 2
#define IRQ_AXI_INDEX 11
#define DELAY_FOR_RESET_HW 100
#define HDR_SG_MOD 0x2
#define LUN_SIZE 8
#define ATTR_PRIO_REGION 9
#define CDB_REGION 12
#define PRIO_OFF 3
#define TMF_REGION 10
#define TAG_MSB 12
#define TAG_LSB 13
#define SMP_FRAME_TYPE 2
#define SMP_CRC_SIZE 4
#define HDR_TAG_OFF 3
#define HOST_NO_OFF 6
#define PHY_NO_OFF 7
#define IDENTIFY_REG_READ 6
#define LINK_RESET_TIMEOUT_OFF 4
#define DECIMALISM_FLAG 10
#define WAIT_RETRY 100
#define WAIT_TMROUT 5000
#define ID_DWORD0_INDEX 0
#define ID_DWORD1_INDEX 1
#define ID_DWORD2_INDEX 2
#define ID_DWORD3_INDEX 3
#define ID_DWORD4_INDEX 4
#define ID_DWORD5_INDEX 5
#define TICKS_BIT_INDEX 24
#define COUNT_BIT_INDEX 8
#define PORT_REG_LENGTH 0x100
#define GLOBAL_REG_LENGTH 0x800
#define AXI_REG_LENGTH 0x61
#define RAS_REG_LENGTH 0x10
#define CHNL_INT_STS_MSK 0xeeeeeeee #define CHNL_INT_STS_MSK 0xeeeeeeee
#define CHNL_INT_STS_PHY_MSK 0xe #define CHNL_INT_STS_PHY_MSK 0xe
@@ -807,17 +850,17 @@ static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
identify_buffer = (u32 *)(&identify_frame); identify_buffer = (u32 *)(&identify_frame);
hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
__swab32(identify_buffer[0])); __swab32(identify_buffer[ID_DWORD0_INDEX]));
hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
__swab32(identify_buffer[1])); __swab32(identify_buffer[ID_DWORD1_INDEX]));
hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
__swab32(identify_buffer[2])); __swab32(identify_buffer[ID_DWORD2_INDEX]));
hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
__swab32(identify_buffer[3])); __swab32(identify_buffer[ID_DWORD3_INDEX]));
hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
__swab32(identify_buffer[4])); __swab32(identify_buffer[ID_DWORD4_INDEX]));
hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
__swab32(identify_buffer[5])); __swab32(identify_buffer[ID_DWORD5_INDEX]));
} }
static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
@@ -937,7 +980,7 @@ static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
/* Disable all of the PHYs */ /* Disable all of the PHYs */
hisi_sas_stop_phys(hisi_hba); hisi_sas_stop_phys(hisi_hba);
udelay(50); udelay(HISI_SAS_DELAY_FOR_PHY_DISABLE);
/* Ensure axi bus idle */ /* Ensure axi bus idle */
ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
@@ -977,7 +1020,7 @@ static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
return rc; return rc;
} }
msleep(100); msleep(DELAY_FOR_RESET_HW);
init_reg_v3_hw(hisi_hba); init_reg_v3_hw(hisi_hba);
if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) { if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) {
@@ -1026,7 +1069,7 @@ static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
cfg &= ~PHY_CFG_ENA_MSK; cfg &= ~PHY_CFG_ENA_MSK;
hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
mdelay(50); mdelay(HISI_SAS_DELAY_FOR_PHY_DISABLE);
state = hisi_sas_read32(hisi_hba, PHY_STATE); state = hisi_sas_read32(hisi_hba, PHY_STATE);
if (state & BIT(phy_no)) { if (state & BIT(phy_no)) {
@@ -1062,7 +1105,7 @@ static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
txid_auto | TX_HARDRST_MSK); txid_auto | TX_HARDRST_MSK);
} }
msleep(100); msleep(HISI_SAS_DELAY_FOR_PHY_DISABLE);
hisi_sas_phy_enable(hisi_hba, phy_no, 1); hisi_sas_phy_enable(hisi_hba, phy_no, 1);
} }
@@ -1107,7 +1150,8 @@ static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
for (i = 0; i < hisi_hba->n_phy; i++) for (i = 0; i < hisi_hba->n_phy; i++)
if (phy_state & BIT(i)) if (phy_state & BIT(i))
if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) if (((phy_port_num_ma >> (i * HISI_SAS_REG_MEM_SIZE)) & 0xf) ==
port_id)
bitmap |= BIT(i); bitmap |= BIT(i);
return bitmap; return bitmap;
@@ -1305,9 +1349,9 @@ static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
+ 3) / 4) << CMD_HDR_CFL_OFF) | + 3) / BYTE_TO_DW) << CMD_HDR_CFL_OFF) |
((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | ((HISI_SAS_MAX_SSP_RESP_SZ / BYTE_TO_DW) << CMD_HDR_MRFL_OFF) |
(2 << CMD_HDR_SG_MOD_OFF); (HDR_SG_MOD << CMD_HDR_SG_MOD_OFF);
hdr->dw2 = cpu_to_le32(dw2); hdr->dw2 = cpu_to_le32(dw2);
hdr->transfer_tags = cpu_to_le32(slot->idx); hdr->transfer_tags = cpu_to_le32(slot->idx);
@@ -1327,18 +1371,19 @@ static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
sizeof(struct ssp_frame_hdr); sizeof(struct ssp_frame_hdr);
memcpy(buf_cmd, &task->ssp_task.LUN, 8); memcpy(buf_cmd, &task->ssp_task.LUN, LUN_SIZE);
if (!tmf) { if (!tmf) {
buf_cmd[9] = ssp_task->task_attr; buf_cmd[ATTR_PRIO_REGION] = ssp_task->task_attr;
memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); memcpy(buf_cmd + CDB_REGION, scsi_cmnd->cmnd,
scsi_cmnd->cmd_len);
} else { } else {
buf_cmd[10] = tmf->tmf; buf_cmd[TMF_REGION] = tmf->tmf;
switch (tmf->tmf) { switch (tmf->tmf) {
case TMF_ABORT_TASK: case TMF_ABORT_TASK:
case TMF_QUERY_TASK: case TMF_QUERY_TASK:
buf_cmd[12] = buf_cmd[TAG_MSB] =
(tmf->tag_of_task_to_be_managed >> 8) & 0xff; (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
buf_cmd[13] = buf_cmd[TAG_LSB] =
tmf->tag_of_task_to_be_managed & 0xff; tmf->tag_of_task_to_be_managed & 0xff;
break; break;
default: default:
@@ -1371,7 +1416,8 @@ static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
unsigned int interval = scsi_prot_interval(scsi_cmnd); unsigned int interval = scsi_prot_interval(scsi_cmnd);
unsigned int ilog2_interval = ilog2(interval); unsigned int ilog2_interval = ilog2(interval);
len = (task->total_xfer_len >> ilog2_interval) * 8; len = (task->total_xfer_len >> ilog2_interval) *
BYTE_TO_DDW;
} }
} }
@@ -1391,6 +1437,7 @@ static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
struct hisi_sas_device *sas_dev = device->lldd_dev; struct hisi_sas_device *sas_dev = device->lldd_dev;
dma_addr_t req_dma_addr; dma_addr_t req_dma_addr;
unsigned int req_len; unsigned int req_len;
u32 cfl;
/* req */ /* req */
sg_req = &task->smp_task.smp_req; sg_req = &task->smp_task.smp_req;
@@ -1401,7 +1448,7 @@ static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
/* dw0 */ /* dw0 */
hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
(1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
(2 << CMD_HDR_CMD_OFF)); /* smp */ (SMP_FRAME_TYPE << CMD_HDR_CMD_OFF)); /* smp */
/* map itct entry */ /* map itct entry */
hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
@@ -1409,8 +1456,9 @@ static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
(DIR_NO_DATA << CMD_HDR_DIR_OFF)); (DIR_NO_DATA << CMD_HDR_DIR_OFF));
/* dw2 */ /* dw2 */
hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | cfl = (req_len - SMP_CRC_SIZE) / BYTE_TO_DW;
(HISI_SAS_MAX_SMP_RESP_SZ / 4 << hdr->dw2 = cpu_to_le32((cfl << CMD_HDR_CFL_OFF) |
(HISI_SAS_MAX_SMP_RESP_SZ / BYTE_TO_DW <<
CMD_HDR_MRFL_OFF)); CMD_HDR_MRFL_OFF));
hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
@@ -1469,12 +1517,13 @@ static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
struct ata_queued_cmd *qc = task->uldd_task; struct ata_queued_cmd *qc = task->uldd_task;
hdr_tag = qc->tag; hdr_tag = qc->tag;
task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); task->ata_task.fis.sector_count |=
(u8)(hdr_tag << HDR_TAG_OFF);
dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
} }
dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / BYTE_TO_DW) << CMD_HDR_CFL_OFF |
2 << CMD_HDR_SG_MOD_OFF; HDR_SG_MOD << CMD_HDR_SG_MOD_OFF;
hdr->dw2 = cpu_to_le32(dw2); hdr->dw2 = cpu_to_le32(dw2);
/* dw3 */ /* dw3 */
@@ -1534,9 +1583,9 @@ static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
port_id = (port_id >> (4 * phy_no)) & 0xf; port_id = (port_id >> (HISI_SAS_REG_MEM_SIZE * phy_no)) & 0xf;
link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
link_rate = (link_rate >> (phy_no * 4)) & 0xf; link_rate = (link_rate >> (phy_no * HISI_SAS_REG_MEM_SIZE)) & 0xf;
if (port_id == 0xf) { if (port_id == 0xf) {
dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
@@ -1569,8 +1618,8 @@ static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
sas_phy->oob_mode = SATA_OOB_MODE; sas_phy->oob_mode = SATA_OOB_MODE;
attached_sas_addr[0] = 0x50; attached_sas_addr[0] = 0x50;
attached_sas_addr[6] = shost->host_no; attached_sas_addr[HOST_NO_OFF] = shost->host_no;
attached_sas_addr[7] = phy_no; attached_sas_addr[PHY_NO_OFF] = phy_no;
memcpy(sas_phy->attached_sas_addr, memcpy(sas_phy->attached_sas_addr,
attached_sas_addr, attached_sas_addr,
SAS_ADDR_SIZE); SAS_ADDR_SIZE);
@@ -1586,7 +1635,7 @@ static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
(struct sas_identify_frame *)frame_rcvd; (struct sas_identify_frame *)frame_rcvd;
dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
for (i = 0; i < 6; i++) { for (i = 0; i < IDENTIFY_REG_READ; i++) {
u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
RX_IDAF_DWORD0 + (i * 4)); RX_IDAF_DWORD0 + (i * 4));
frame_rcvd[i] = __swab32(idaf); frame_rcvd[i] = __swab32(idaf);
@@ -1856,7 +1905,7 @@ static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
dev_warn(dev, "phy%d stp link timeout (0x%x)\n", dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
phy_no, reg_value); phy_no, reg_value);
if (reg_value & BIT(4)) if (reg_value & BIT(LINK_RESET_TIMEOUT_OFF))
hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
} }
@@ -2573,7 +2622,7 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
struct pci_dev *pdev = hisi_hba->pci_dev; struct pci_dev *pdev = hisi_hba->pci_dev;
int rc, i; int rc, i;
rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), rc = devm_request_irq(dev, pci_irq_vector(pdev, IRQ_PHY_UP_DOWN_INDEX),
int_phy_up_down_bcast_v3_hw, 0, int_phy_up_down_bcast_v3_hw, 0,
DRV_NAME " phy", hisi_hba); DRV_NAME " phy", hisi_hba);
if (rc) { if (rc) {
@@ -2581,7 +2630,7 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
return -ENOENT; return -ENOENT;
} }
rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), rc = devm_request_irq(dev, pci_irq_vector(pdev, IRQ_CHL_INDEX),
int_chnl_int_v3_hw, 0, int_chnl_int_v3_hw, 0,
DRV_NAME " channel", hisi_hba); DRV_NAME " channel", hisi_hba);
if (rc) { if (rc) {
@@ -2589,7 +2638,7 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
return -ENOENT; return -ENOENT;
} }
rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), rc = devm_request_irq(dev, pci_irq_vector(pdev, IRQ_AXI_INDEX),
fatal_axi_int_v3_hw, 0, fatal_axi_int_v3_hw, 0,
DRV_NAME " fatal", hisi_hba); DRV_NAME " fatal", hisi_hba);
if (rc) { if (rc) {
@@ -2602,7 +2651,8 @@ static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
for (i = 0; i < hisi_hba->cq_nvecs; i++) { for (i = 0; i < hisi_hba->cq_nvecs; i++) {
struct hisi_sas_cq *cq = &hisi_hba->cq[i]; struct hisi_sas_cq *cq = &hisi_hba->cq[i];
int nr = hisi_sas_intr_conv ? 16 : 16 + i; int nr = hisi_sas_intr_conv ? BASE_VECTORS_V3_HW :
BASE_VECTORS_V3_HW + i;
unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED : unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED :
IRQF_ONESHOT; IRQF_ONESHOT;
@@ -2660,14 +2710,14 @@ static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
struct pci_dev *pdev = hisi_hba->pci_dev; struct pci_dev *pdev = hisi_hba->pci_dev;
int i; int i;
synchronize_irq(pci_irq_vector(pdev, 1)); synchronize_irq(pci_irq_vector(pdev, IRQ_PHY_UP_DOWN_INDEX));
synchronize_irq(pci_irq_vector(pdev, 2)); synchronize_irq(pci_irq_vector(pdev, IRQ_CHL_INDEX));
synchronize_irq(pci_irq_vector(pdev, 11)); synchronize_irq(pci_irq_vector(pdev, IRQ_AXI_INDEX));
for (i = 0; i < hisi_hba->queue_count; i++) for (i = 0; i < hisi_hba->queue_count; i++)
hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
for (i = 0; i < hisi_hba->cq_nvecs; i++) for (i = 0; i < hisi_hba->cq_nvecs; i++)
synchronize_irq(pci_irq_vector(pdev, i + 16)); synchronize_irq(pci_irq_vector(pdev, i + BASE_VECTORS_V3_HW));
hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
@@ -2699,7 +2749,7 @@ static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
hisi_sas_stop_phys(hisi_hba); hisi_sas_stop_phys(hisi_hba);
mdelay(10); mdelay(HISI_SAS_DELAY_FOR_PHY_DISABLE);
reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
AM_CTRL_GLOBAL); AM_CTRL_GLOBAL);
@@ -2836,13 +2886,13 @@ static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev,
u32 intr_coal_ticks; u32 intr_coal_ticks;
int ret; int ret;
ret = kstrtou32(buf, 10, &intr_coal_ticks); ret = kstrtou32(buf, DECIMALISM_FLAG, &intr_coal_ticks);
if (ret) { if (ret) {
dev_err(dev, "Input data of interrupt coalesce unmatch\n"); dev_err(dev, "Input data of interrupt coalesce unmatch\n");
return -EINVAL; return -EINVAL;
} }
if (intr_coal_ticks >= BIT(24)) { if (intr_coal_ticks >= BIT(TICKS_BIT_INDEX)) {
dev_err(dev, "intr_coal_ticks must be less than 2^24!\n"); dev_err(dev, "intr_coal_ticks must be less than 2^24!\n");
return -EINVAL; return -EINVAL;
} }
@@ -2875,13 +2925,13 @@ static ssize_t intr_coal_count_v3_hw_store(struct device *dev,
u32 intr_coal_count; u32 intr_coal_count;
int ret; int ret;
ret = kstrtou32(buf, 10, &intr_coal_count); ret = kstrtou32(buf, DECIMALISM_FLAG, &intr_coal_count);
if (ret) { if (ret) {
dev_err(dev, "Input data of interrupt coalesce unmatch\n"); dev_err(dev, "Input data of interrupt coalesce unmatch\n");
return -EINVAL; return -EINVAL;
} }
if (intr_coal_count >= BIT(8)) { if (intr_coal_count >= BIT(COUNT_BIT_INDEX)) {
dev_err(dev, "intr_coal_count must be less than 2^8!\n"); dev_err(dev, "intr_coal_count must be less than 2^8!\n");
return -EINVAL; return -EINVAL;
} }
@@ -3013,7 +3063,7 @@ static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = {
static const struct hisi_sas_debugfs_reg debugfs_port_reg = { static const struct hisi_sas_debugfs_reg debugfs_port_reg = {
.lu = debugfs_port_reg_lu, .lu = debugfs_port_reg_lu,
.count = 0x100, .count = PORT_REG_LENGTH,
.base_off = PORT_BASE, .base_off = PORT_BASE,
}; };
@@ -3087,7 +3137,7 @@ static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = {
static const struct hisi_sas_debugfs_reg debugfs_global_reg = { static const struct hisi_sas_debugfs_reg debugfs_global_reg = {
.lu = debugfs_global_reg_lu, .lu = debugfs_global_reg_lu,
.count = 0x800, .count = GLOBAL_REG_LENGTH,
}; };
static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = { static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = {
@@ -3100,7 +3150,7 @@ static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = {
static const struct hisi_sas_debugfs_reg debugfs_axi_reg = { static const struct hisi_sas_debugfs_reg debugfs_axi_reg = {
.lu = debugfs_axi_reg_lu, .lu = debugfs_axi_reg_lu,
.count = 0x61, .count = AXI_REG_LENGTH,
.base_off = AXI_MASTER_CFG_BASE, .base_off = AXI_MASTER_CFG_BASE,
}; };
@@ -3117,7 +3167,7 @@ static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = {
static const struct hisi_sas_debugfs_reg debugfs_ras_reg = { static const struct hisi_sas_debugfs_reg debugfs_ras_reg = {
.lu = debugfs_ras_reg_lu, .lu = debugfs_ras_reg_lu,
.count = 0x10, .count = RAS_REG_LENGTH,
.base_off = RAS_BASE, .base_off = RAS_BASE,
}; };
@@ -3126,7 +3176,7 @@ static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba)
struct Scsi_Host *shost = hisi_hba->shost; struct Scsi_Host *shost = hisi_hba->shost;
scsi_block_requests(shost); scsi_block_requests(shost);
wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000); wait_cmds_complete_timeout_v3_hw(hisi_hba, WAIT_RETRY, WAIT_TMROUT);
set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
hisi_sas_sync_cqs(hisi_hba); hisi_sas_sync_cqs(hisi_hba);
@@ -3167,7 +3217,7 @@ static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba,
return; return;
} }
memset(buf, 0, cache_dw_size * 4); memset(buf, 0, cache_dw_size * BYTE_TO_DW);
buf[0] = val; buf[0] = val;
for (i = 1; i < cache_dw_size; i++) for (i = 1; i < cache_dw_size; i++)
@@ -3214,7 +3264,7 @@ static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE); reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
/* init OOB link rate as 1.5 Gbits */ /* init OOB link rate as 1.5 Gbits */
reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK; reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
reg_val |= (0x8 << CFG_PROG_OOB_PHY_LINK_RATE_OFF); reg_val |= (SAS_LINK_RATE_1_5_GBPS << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, reg_val); hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, reg_val);
/* enable PHY */ /* enable PHY */
@@ -3223,6 +3273,9 @@ static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
#define SAS_PHY_BIST_CODE_INIT 0x1 #define SAS_PHY_BIST_CODE_INIT 0x1
#define SAS_PHY_BIST_CODE1_INIT 0X80 #define SAS_PHY_BIST_CODE1_INIT 0X80
#define SAS_PHY_BIST_INIT_DELAY 100
#define SAS_PHY_BIST_LOOP_TEST_0 1
#define SAS_PHY_BIST_LOOP_TEST_1 2
static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable) static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
{ {
u32 reg_val, mode_tmp; u32 reg_val, mode_tmp;
@@ -3241,7 +3294,8 @@ static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
ffe[FFE_SATA_1_5_GBPS], ffe[FFE_SATA_3_0_GBPS], ffe[FFE_SATA_1_5_GBPS], ffe[FFE_SATA_3_0_GBPS],
ffe[FFE_SATA_6_0_GBPS], fix_code[FIXED_CODE], ffe[FFE_SATA_6_0_GBPS], fix_code[FIXED_CODE],
fix_code[FIXED_CODE_1]); fix_code[FIXED_CODE_1]);
mode_tmp = path_mode ? 2 : 1; mode_tmp = path_mode ? SAS_PHY_BIST_LOOP_TEST_1 :
SAS_PHY_BIST_LOOP_TEST_0;
if (enable) { if (enable) {
/* some preparations before bist test */ /* some preparations before bist test */
hisi_sas_bist_test_prep_v3_hw(hisi_hba); hisi_sas_bist_test_prep_v3_hw(hisi_hba);
@@ -3284,13 +3338,13 @@ static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
SAS_PHY_BIST_CODE1_INIT); SAS_PHY_BIST_CODE1_INIT);
} }
mdelay(100); mdelay(SAS_PHY_BIST_INIT_DELAY);
reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK); reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
reg_val); reg_val);
/* clear error bit */ /* clear error bit */
mdelay(100); mdelay(SAS_PHY_BIST_INIT_DELAY);
hisi_sas_phy_read32(hisi_hba, phy_no, SAS_BIST_ERR_CNT); hisi_sas_phy_read32(hisi_hba, phy_no, SAS_BIST_ERR_CNT);
} else { } else {
/* disable bist test and recover it */ /* disable bist test and recover it */
@@ -3486,7 +3540,7 @@ static void debugfs_snapshot_port_reg_v3_hw(struct hisi_hba *hisi_hba)
for (phy_cnt = 0; phy_cnt < hisi_hba->n_phy; phy_cnt++) { for (phy_cnt = 0; phy_cnt < hisi_hba->n_phy; phy_cnt++) {
databuf = hisi_hba->debugfs_port_reg[dump_index][phy_cnt].data; databuf = hisi_hba->debugfs_port_reg[dump_index][phy_cnt].data;
for (i = 0; i < port->count; i++, databuf++) { for (i = 0; i < port->count; i++, databuf++) {
offset = port->base_off + 4 * i; offset = port->base_off + HISI_SAS_REG_MEM_SIZE * i;
*databuf = hisi_sas_phy_read32(hisi_hba, phy_cnt, *databuf = hisi_sas_phy_read32(hisi_hba, phy_cnt,
offset); offset);
} }
@@ -3500,7 +3554,8 @@ static void debugfs_snapshot_global_reg_v3_hw(struct hisi_hba *hisi_hba)
int i; int i;
for (i = 0; i < debugfs_global_reg.count; i++, databuf++) for (i = 0; i < debugfs_global_reg.count; i++, databuf++)
*databuf = hisi_sas_read32(hisi_hba, 4 * i); *databuf = hisi_sas_read32(hisi_hba,
HISI_SAS_REG_MEM_SIZE * i);
} }
static void debugfs_snapshot_axi_reg_v3_hw(struct hisi_hba *hisi_hba) static void debugfs_snapshot_axi_reg_v3_hw(struct hisi_hba *hisi_hba)
@@ -3511,7 +3566,9 @@ static void debugfs_snapshot_axi_reg_v3_hw(struct hisi_hba *hisi_hba)
int i; int i;
for (i = 0; i < axi->count; i++, databuf++) for (i = 0; i < axi->count; i++, databuf++)
*databuf = hisi_sas_read32(hisi_hba, 4 * i + axi->base_off); *databuf = hisi_sas_read32(hisi_hba,
HISI_SAS_REG_MEM_SIZE * i +
axi->base_off);
} }
static void debugfs_snapshot_ras_reg_v3_hw(struct hisi_hba *hisi_hba) static void debugfs_snapshot_ras_reg_v3_hw(struct hisi_hba *hisi_hba)
@@ -3522,7 +3579,9 @@ static void debugfs_snapshot_ras_reg_v3_hw(struct hisi_hba *hisi_hba)
int i; int i;
for (i = 0; i < ras->count; i++, databuf++) for (i = 0; i < ras->count; i++, databuf++)
*databuf = hisi_sas_read32(hisi_hba, 4 * i + ras->base_off); *databuf = hisi_sas_read32(hisi_hba,
HISI_SAS_REG_MEM_SIZE * i +
ras->base_off);
} }
static void debugfs_snapshot_itct_reg_v3_hw(struct hisi_hba *hisi_hba) static void debugfs_snapshot_itct_reg_v3_hw(struct hisi_hba *hisi_hba)
@@ -3585,7 +3644,7 @@ static void debugfs_print_reg_v3_hw(u32 *regs_val, struct seq_file *s,
int i; int i;
for (i = 0; i < reg->count; i++) { for (i = 0; i < reg->count; i++) {
int off = i * 4; int off = i * HISI_SAS_REG_MEM_SIZE;
const char *name; const char *name;
name = debugfs_to_reg_name_v3_hw(off, reg->base_off, name = debugfs_to_reg_name_v3_hw(off, reg->base_off,
@@ -3663,9 +3722,9 @@ static void debugfs_show_row_64_v3_hw(struct seq_file *s, int index,
/* completion header size not fixed per HW version */ /* completion header size not fixed per HW version */
seq_printf(s, "index %04d:\n\t", index); seq_printf(s, "index %04d:\n\t", index);
for (i = 1; i <= sz / 8; i++, ptr++) { for (i = 1; i <= sz / BYTE_TO_DDW; i++, ptr++) {
seq_printf(s, " 0x%016llx", le64_to_cpu(*ptr)); seq_printf(s, " 0x%016llx", le64_to_cpu(*ptr));
if (!(i % 2)) if (!(i % TWO_PARA_PER_LINE))
seq_puts(s, "\n\t"); seq_puts(s, "\n\t");
} }
@@ -3679,9 +3738,9 @@ static void debugfs_show_row_32_v3_hw(struct seq_file *s, int index,
/* completion header size not fixed per HW version */ /* completion header size not fixed per HW version */
seq_printf(s, "index %04d:\n\t", index); seq_printf(s, "index %04d:\n\t", index);
for (i = 1; i <= sz / 4; i++, ptr++) { for (i = 1; i <= sz / BYTE_TO_DW; i++, ptr++) {
seq_printf(s, " 0x%08x", le32_to_cpu(*ptr)); seq_printf(s, " 0x%08x", le32_to_cpu(*ptr));
if (!(i % 4)) if (!(i % FOUR_PARA_PER_LINE))
seq_puts(s, "\n\t"); seq_puts(s, "\n\t");
} }
seq_puts(s, "\n"); seq_puts(s, "\n");
@@ -3766,7 +3825,7 @@ static int debugfs_iost_cache_v3_hw_show(struct seq_file *s, void *p)
struct hisi_sas_debugfs_iost_cache *debugfs_iost_cache = s->private; struct hisi_sas_debugfs_iost_cache *debugfs_iost_cache = s->private;
struct hisi_sas_iost_itct_cache *iost_cache = struct hisi_sas_iost_itct_cache *iost_cache =
debugfs_iost_cache->cache; debugfs_iost_cache->cache;
u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4; u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * BYTE_TO_DW;
int i, tab_idx; int i, tab_idx;
__le64 *iost; __le64 *iost;
@@ -3814,7 +3873,7 @@ static int debugfs_itct_cache_v3_hw_show(struct seq_file *s, void *p)
struct hisi_sas_debugfs_itct_cache *debugfs_itct_cache = s->private; struct hisi_sas_debugfs_itct_cache *debugfs_itct_cache = s->private;
struct hisi_sas_iost_itct_cache *itct_cache = struct hisi_sas_iost_itct_cache *itct_cache =
debugfs_itct_cache->cache; debugfs_itct_cache->cache;
u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4; u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * BYTE_TO_DW;
int i, tab_idx; int i, tab_idx;
__le64 *itct; __le64 *itct;
@@ -3843,12 +3902,12 @@ static void debugfs_create_files_v3_hw(struct hisi_hba *hisi_hba, int index)
u64 *debugfs_timestamp; u64 *debugfs_timestamp;
struct dentry *dump_dentry; struct dentry *dump_dentry;
struct dentry *dentry; struct dentry *dentry;
char name[256]; char name[NAME_BUF_SIZE];
int p; int p;
int c; int c;
int d; int d;
snprintf(name, 256, "%d", index); snprintf(name, NAME_BUF_SIZE, "%d", index);
dump_dentry = debugfs_create_dir(name, hisi_hba->debugfs_dump_dentry); dump_dentry = debugfs_create_dir(name, hisi_hba->debugfs_dump_dentry);
@@ -3864,7 +3923,7 @@ static void debugfs_create_files_v3_hw(struct hisi_hba *hisi_hba, int index)
/* Create port dir and files */ /* Create port dir and files */
dentry = debugfs_create_dir("port", dump_dentry); dentry = debugfs_create_dir("port", dump_dentry);
for (p = 0; p < hisi_hba->n_phy; p++) { for (p = 0; p < hisi_hba->n_phy; p++) {
snprintf(name, 256, "%d", p); snprintf(name, NAME_BUF_SIZE, "%d", p);
debugfs_create_file(name, 0400, dentry, debugfs_create_file(name, 0400, dentry,
&hisi_hba->debugfs_port_reg[index][p], &hisi_hba->debugfs_port_reg[index][p],
@@ -3874,7 +3933,7 @@ static void debugfs_create_files_v3_hw(struct hisi_hba *hisi_hba, int index)
/* Create CQ dir and files */ /* Create CQ dir and files */
dentry = debugfs_create_dir("cq", dump_dentry); dentry = debugfs_create_dir("cq", dump_dentry);
for (c = 0; c < hisi_hba->queue_count; c++) { for (c = 0; c < hisi_hba->queue_count; c++) {
snprintf(name, 256, "%d", c); snprintf(name, NAME_BUF_SIZE, "%d", c);
debugfs_create_file(name, 0400, dentry, debugfs_create_file(name, 0400, dentry,
&hisi_hba->debugfs_cq[index][c], &hisi_hba->debugfs_cq[index][c],
@@ -3884,7 +3943,7 @@ static void debugfs_create_files_v3_hw(struct hisi_hba *hisi_hba, int index)
/* Create DQ dir and files */ /* Create DQ dir and files */
dentry = debugfs_create_dir("dq", dump_dentry); dentry = debugfs_create_dir("dq", dump_dentry);
for (d = 0; d < hisi_hba->queue_count; d++) { for (d = 0; d < hisi_hba->queue_count; d++) {
snprintf(name, 256, "%d", d); snprintf(name, NAME_BUF_SIZE, "%d", d);
debugfs_create_file(name, 0400, dentry, debugfs_create_file(name, 0400, dentry,
&hisi_hba->debugfs_dq[index][d], &hisi_hba->debugfs_dq[index][d],
@@ -3921,9 +3980,9 @@ static ssize_t debugfs_trigger_dump_v3_hw_write(struct file *file,
size_t count, loff_t *ppos) size_t count, loff_t *ppos)
{ {
struct hisi_hba *hisi_hba = file->f_inode->i_private; struct hisi_hba *hisi_hba = file->f_inode->i_private;
char buf[8]; char buf[DUMP_BUF_SIZE];
if (count > 8) if (count > DUMP_BUF_SIZE)
return -EFAULT; return -EFAULT;
if (copy_from_user(buf, user_buf, count)) if (copy_from_user(buf, user_buf, count))
@@ -3987,7 +4046,7 @@ static ssize_t debugfs_bist_linkrate_v3_hw_write(struct file *filp,
{ {
struct seq_file *m = filp->private_data; struct seq_file *m = filp->private_data;
struct hisi_hba *hisi_hba = m->private; struct hisi_hba *hisi_hba = m->private;
char kbuf[16] = {}, *pkbuf; char kbuf[BIST_BUF_SIZE] = {}, *pkbuf;
bool found = false; bool found = false;
int i; int i;
@@ -4004,7 +4063,7 @@ static ssize_t debugfs_bist_linkrate_v3_hw_write(struct file *filp,
for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) { for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
if (!strncmp(debugfs_loop_linkrate_v3_hw[i].name, if (!strncmp(debugfs_loop_linkrate_v3_hw[i].name,
pkbuf, 16)) { pkbuf, BIST_BUF_SIZE)) {
hisi_hba->debugfs_bist_linkrate = hisi_hba->debugfs_bist_linkrate =
debugfs_loop_linkrate_v3_hw[i].value; debugfs_loop_linkrate_v3_hw[i].value;
found = true; found = true;
@@ -4062,7 +4121,7 @@ static ssize_t debugfs_bist_code_mode_v3_hw_write(struct file *filp,
{ {
struct seq_file *m = filp->private_data; struct seq_file *m = filp->private_data;
struct hisi_hba *hisi_hba = m->private; struct hisi_hba *hisi_hba = m->private;
char kbuf[16] = {}, *pkbuf; char kbuf[BIST_BUF_SIZE] = {}, *pkbuf;
bool found = false; bool found = false;
int i; int i;
@@ -4079,7 +4138,7 @@ static ssize_t debugfs_bist_code_mode_v3_hw_write(struct file *filp,
for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) { for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
if (!strncmp(debugfs_loop_code_mode_v3_hw[i].name, if (!strncmp(debugfs_loop_code_mode_v3_hw[i].name,
pkbuf, 16)) { pkbuf, BIST_BUF_SIZE)) {
hisi_hba->debugfs_bist_code_mode = hisi_hba->debugfs_bist_code_mode =
debugfs_loop_code_mode_v3_hw[i].value; debugfs_loop_code_mode_v3_hw[i].value;
found = true; found = true;
@@ -4194,7 +4253,7 @@ static ssize_t debugfs_bist_mode_v3_hw_write(struct file *filp,
{ {
struct seq_file *m = filp->private_data; struct seq_file *m = filp->private_data;
struct hisi_hba *hisi_hba = m->private; struct hisi_hba *hisi_hba = m->private;
char kbuf[16] = {}, *pkbuf; char kbuf[BIST_BUF_SIZE] = {}, *pkbuf;
bool found = false; bool found = false;
int i; int i;
@@ -4210,7 +4269,8 @@ static ssize_t debugfs_bist_mode_v3_hw_write(struct file *filp,
pkbuf = strstrip(kbuf); pkbuf = strstrip(kbuf);
for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) { for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
if (!strncmp(debugfs_loop_modes_v3_hw[i].name, pkbuf, 16)) { if (!strncmp(debugfs_loop_modes_v3_hw[i].name, pkbuf,
BIST_BUF_SIZE)) {
hisi_hba->debugfs_bist_mode = hisi_hba->debugfs_bist_mode =
debugfs_loop_modes_v3_hw[i].value; debugfs_loop_modes_v3_hw[i].value;
found = true; found = true;
@@ -4489,8 +4549,9 @@ static int debugfs_fifo_data_v3_hw_show(struct seq_file *s, void *p)
debugfs_read_fifo_data_v3_hw(phy); debugfs_read_fifo_data_v3_hw(phy);
debugfs_show_row_32_v3_hw(s, 0, HISI_SAS_FIFO_DATA_DW_SIZE * 4, debugfs_show_row_32_v3_hw(s, 0,
(__le32 *)phy->fifo.rd_data); HISI_SAS_FIFO_DATA_DW_SIZE * HISI_SAS_REG_MEM_SIZE,
phy->fifo.rd_data);
return 0; return 0;
} }
@@ -4622,14 +4683,14 @@ static int debugfs_alloc_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
struct hisi_sas_debugfs_regs *regs = struct hisi_sas_debugfs_regs *regs =
&hisi_hba->debugfs_regs[dump_index][r]; &hisi_hba->debugfs_regs[dump_index][r];
sz = debugfs_reg_array_v3_hw[r]->count * 4; sz = debugfs_reg_array_v3_hw[r]->count * HISI_SAS_REG_MEM_SIZE;
regs->data = devm_kmalloc(dev, sz, GFP_KERNEL); regs->data = devm_kmalloc(dev, sz, GFP_KERNEL);
if (!regs->data) if (!regs->data)
goto fail; goto fail;
regs->hisi_hba = hisi_hba; regs->hisi_hba = hisi_hba;
} }
sz = debugfs_port_reg.count * 4; sz = debugfs_port_reg.count * HISI_SAS_REG_MEM_SIZE;
for (p = 0; p < hisi_hba->n_phy; p++) { for (p = 0; p < hisi_hba->n_phy; p++) {
struct hisi_sas_debugfs_port *port = struct hisi_sas_debugfs_port *port =
&hisi_hba->debugfs_port_reg[dump_index][p]; &hisi_hba->debugfs_port_reg[dump_index][p];
@@ -4739,11 +4800,11 @@ static void debugfs_phy_down_cnt_init_v3_hw(struct hisi_hba *hisi_hba)
{ {
struct dentry *dir = debugfs_create_dir("phy_down_cnt", struct dentry *dir = debugfs_create_dir("phy_down_cnt",
hisi_hba->debugfs_dir); hisi_hba->debugfs_dir);
char name[16]; char name[NAME_BUF_SIZE];
int phy_no; int phy_no;
for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) { for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
snprintf(name, 16, "%d", phy_no); snprintf(name, NAME_BUF_SIZE, "%d", phy_no);
debugfs_create_file(name, 0600, dir, debugfs_create_file(name, 0600, dir,
&hisi_hba->phy[phy_no], &hisi_hba->phy[phy_no],
&debugfs_phy_down_cnt_v3_hw_fops); &debugfs_phy_down_cnt_v3_hw_fops);
@@ -4928,7 +4989,7 @@ hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
shost->max_id = HISI_SAS_MAX_DEVICES; shost->max_id = HISI_SAS_MAX_DEVICES;
shost->max_lun = ~0; shost->max_lun = ~0;
shost->max_channel = 1; shost->max_channel = 1;
shost->max_cmd_len = 16; shost->max_cmd_len = HISI_SAS_MAX_CDB_LEN;
shost->can_queue = HISI_SAS_UNRESERVED_IPTT; shost->can_queue = HISI_SAS_UNRESERVED_IPTT;
shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT; shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT;
if (hisi_hba->iopoll_q_cnt) if (hisi_hba->iopoll_q_cnt)
@@ -5006,12 +5067,13 @@ hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
{ {
int i; int i;
devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 1), hisi_hba); devm_free_irq(&pdev->dev, pci_irq_vector(pdev, IRQ_PHY_UP_DOWN_INDEX), hisi_hba);
devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 2), hisi_hba); devm_free_irq(&pdev->dev, pci_irq_vector(pdev, IRQ_CHL_INDEX), hisi_hba);
devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 11), hisi_hba); devm_free_irq(&pdev->dev, pci_irq_vector(pdev, IRQ_AXI_INDEX), hisi_hba);
for (i = 0; i < hisi_hba->cq_nvecs; i++) { for (i = 0; i < hisi_hba->cq_nvecs; i++) {
struct hisi_sas_cq *cq = &hisi_hba->cq[i]; struct hisi_sas_cq *cq = &hisi_hba->cq[i];
int nr = hisi_sas_intr_conv ? 16 : 16 + i; int nr = hisi_sas_intr_conv ? BASE_VECTORS_V3_HW :
BASE_VECTORS_V3_HW + i;
devm_free_irq(&pdev->dev, pci_irq_vector(pdev, nr), cq); devm_free_irq(&pdev->dev, pci_irq_vector(pdev, nr), cq);
} }