From 096a22ae0815e5252e098c6808db501a071803bd Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 14 Nov 2024 01:12:05 +0000 Subject: [PATCH 01/33] arm64: dts: renesas: ulcb: Add sample Audio Codec settings ulcb{-kf} needs amixer settings to use Audio. Add Sample settings for it, for not to forget. Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/87wmh6pqje.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 18 +++++++++++++++++- arch/arm64/boot/dts/renesas/ulcb.dtsi | 5 +++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 5c211ed83049..2a157d1efb3d 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -4,8 +4,24 @@ * * Copyright (C) 2017 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. + * + * Sample Audio settings: + * + * > amixer set "DVC Out" 1% + * > amixer set "DVC In" 20% + * + * // if you use xxxx-mix+split.dtsi + * > amixer -D hw:1 set "pcm3168a DAC1" 50% + * > amixer -D hw:1 set "pcm3168a DAC2" 50% + * > amixer -D hw:1 set "pcm3168a DAC3" 50% + * > amixer -D hw:1 set "pcm3168a DAC4" 50% + * + * // else + * > amixer -D hw:1 set "DAC1" 50% + * > amixer -D hw:1 set "DAC2" 50% + * > amixer -D hw:1 set "DAC3" 50% + * > amixer -D hw:1 set "DAC4" 50% */ - / { aliases { serial1 = &hscif0; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index cb11abba7bef..0c58d816c375 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -4,6 +4,11 @@ * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2016 Cogent Embedded, Inc. + * + * Sample Audio settings: + * + * > amixer set "DVC Out" 1% + * > amixer set "DVC In" 20% */ #include From aaf7188d7f77bb8a6e043c70dc6cc6616c427762 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 15 Nov 2024 15:43:57 +0200 Subject: [PATCH 02/33] arm64: dts: renesas: r9a08g045: Add the remaining SCIF interfaces The Renesas RZ/G3S SoC has 6 SCIF interfaces. SCIF0 is used as debug console. Add the remaining ones. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241115134401.3893008-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index be8a0a768c65..5b15ff2482ab 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -73,6 +73,96 @@ scif0: serial@1004b800 { status = "disabled"; }; + scif1: serial@1004bc00 { + compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; + reg = <0 0x1004bc00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif2: serial@1004c000 { + compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; + reg = <0 0x1004c000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_SCIF2_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif3: serial@1004c400 { + compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; + reg = <0 0x1004c400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G045_SCIF3_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_SCIF3_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif4: serial@1004c800 { + compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; + reg = <0 0x1004c800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G045_SCIF4_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_SCIF4_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif5: serial@1004e000 { + compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; + reg = <0 0x1004e000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A08G045_SCIF5_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_SCIF5_RST_SYSTEM_N>; + status = "disabled"; + }; + rtc: rtc@1004ec00 { compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; reg = <0 0x1004ec00 0 0x400>; From 08811b984f5af8eeda4fb157894fe9bf230ec1e1 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 15 Nov 2024 15:43:58 +0200 Subject: [PATCH 03/33] arm64: dts: renesas: rzg3s-smarc: Fix the debug serial alias The debug serial of the RZ/G3S is SCIF0 which is routed on the Renesas RZ SMARC Carrier II board on the SER3_UART. Use serial3 alias for it for better hardware description. Along with it, the chosen properties were moved to the device tree corresponding to the RZ SMARC Carrier II board. Fixes: adb4f0c5699c ("arm64: dts: renesas: Add initial support for RZ/G3S SMARC SoM") Fixes: d1ae4200bb26 ("arm64: dts: renesas: Add initial device tree for RZ SMARC Carrier-II Board") Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241115134401.3893008-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 5 ----- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 7 ++++++- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 2ed01d391554..55c72c8a0735 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -43,11 +43,6 @@ aliases { #endif }; - chosen { - bootargs = "ignore_loglevel"; - stdout-path = "serial0:115200n8"; - }; - memory@48000000 { device_type = "memory"; /* First 128MB is reserved for secure area. */ diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 4509151344c4..33b9873b225a 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -12,10 +12,15 @@ / { aliases { i2c0 = &i2c0; - serial0 = &scif0; + serial3 = &scif0; mmc1 = &sdhi1; }; + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial3:115200n8"; + }; + keys { compatible = "gpio-keys"; From a62727cf33e49634d03362800b2edc43538f1913 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 20 Nov 2024 09:49:59 +0100 Subject: [PATCH 04/33] arm64: dts: renesas: rzg3s-smarc: Enable I2C1 and connected power monitor Enable I2C1 for the carrier board and the connected power monitor ISL28022. Limit the bus speed to the maximum the power monitor supports. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Reviewed-by: Claudiu Beznea Tested-by: Claudiu Beznea Link: https://lore.kernel.org/20241120085345.24638-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 33b9873b225a..aaf7f9c7bdf9 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -75,6 +75,19 @@ &i2c0 { clock-frequency = <1000000>; }; +&i2c1 { + status = "okay"; + + clock-frequency = <400000>; + + power-monitor@44 { + compatible = "renesas,isl28022"; + reg = <0x44>; + shunt-resistor-micro-ohms = <8000>; + renesas,average-samples = <32>; + }; +}; + &pinctrl { key-1-gpio-hog { gpio-hog; From f71429df70fb0ed5ca90f595f4d0e9cfa23fcf31 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 Dec 2024 17:30:07 +0100 Subject: [PATCH 05/33] dt-bindings: soc: renesas: Move R8A779G0 White Hawk up Move the R8A779G0-only White Hawk board stack section up, just below the R8A779G0-only White Hawk CPU section, to improve sort order. Signed-off-by: Geert Uytterhoeven Acked-by: Krzysztof Kozlowski Reviewed-by: Kuninori Morimoto Link: https://lore.kernel.org/d553ef4b1f969f72e384f274d42ac7a62fe45fd4.1733156661.git.geert+renesas@glider.be --- .../devicetree/bindings/soc/renesas/renesas.yaml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index b7acb65bdecd..dab666797032 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -360,6 +360,12 @@ properties: - renesas,white-hawk-cpu # White Hawk CPU board (RTP8A779G0ASKB0FC0SA000) - const: renesas,r8a779g0 + - items: + - enum: + - renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000) + - const: renesas,white-hawk-cpu + - const: renesas,r8a779g0 + - description: R-Car V4H (R8A779G2) items: - enum: @@ -367,12 +373,6 @@ properties: - const: renesas,r8a779g2 - const: renesas,r8a779g0 - - items: - - enum: - - renesas,white-hawk-breakout # White Hawk BreakOut board (RTP8A779G0ASKB0SB0SA000) - - const: renesas,white-hawk-cpu - - const: renesas,r8a779g0 - - description: R-Car V4M (R8A779H0) items: - enum: From 5c3e55ad76cf5eda2cd6cbda56161184888ea463 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 Dec 2024 17:30:08 +0100 Subject: [PATCH 06/33] dt-bindings: soc: renesas: Document R8A779G3 White Hawk Single Document the compatible value for the Renesas R-Car V4H ES3.0 (R8A779G3) SoC, as used on the Renesas White Hawk Single board. Signed-off-by: Geert Uytterhoeven Acked-by: Krzysztof Kozlowski Reviewed-by: Kuninori Morimoto Link: https://lore.kernel.org/1d2d2a6cbf31c817f574f6eed310a960e6175afe.1733156661.git.geert+renesas@glider.be --- .../devicetree/bindings/soc/renesas/renesas.yaml | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index dab666797032..eabb5bc81d84 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -366,11 +366,13 @@ properties: - const: renesas,white-hawk-cpu - const: renesas,r8a779g0 - - description: R-Car V4H (R8A779G2) + - description: R-Car V4H (R8A779G[23]) items: - enum: - - renesas,white-hawk-single # White Hawk Single board (RTP8A779G2ASKB0F10SA001) - - const: renesas,r8a779g2 + - renesas,white-hawk-single # White Hawk Single board (RTP8A779G[23]ASKB0F10SA001) + - enum: + - renesas,r8a779g2 # ES2.x + - renesas,r8a779g3 # ES3.x - const: renesas,r8a779g0 - description: R-Car V4M (R8A779H0) From d43c077cb88d800d0c2a372d70d5af75c6a16356 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 Dec 2024 17:30:09 +0100 Subject: [PATCH 07/33] arm64: dts: renesas: Factor out White Hawk Single board support Move the common parts for the Renesas White Hawk Single board to white-hawk-single.dtsi, to enable future reuse. Signed-off-by: Geert Uytterhoeven Reviewed-by: Kuninori Morimoto Link: https://lore.kernel.org/1661743b18a9ff9fac716f98a663b39fc8488d7e.1733156661.git.geert+renesas@glider.be --- .../renesas/r8a779g2-white-hawk-single.dts | 62 +--------------- .../boot/dts/renesas/white-hawk-single.dtsi | 73 +++++++++++++++++++ 2 files changed, 74 insertions(+), 61 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/white-hawk-single.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts index 0062362b0ba0..48befde38937 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts @@ -7,70 +7,10 @@ /dts-v1/; #include "r8a779g2.dtsi" -#include "white-hawk-cpu-common.dtsi" -#include "white-hawk-common.dtsi" +#include "white-hawk-single.dtsi" / { model = "Renesas White Hawk Single board based on r8a779g2"; compatible = "renesas,white-hawk-single", "renesas,r8a779g2", "renesas,r8a779g0"; }; - -&hscif0 { - uart-has-rtscts; -}; - -&hscif0_pins { - groups = "hscif0_data", "hscif0_ctrl"; - function = "hscif0"; -}; - -&pfc { - tsn0_pins: tsn0 { - mux { - groups = "tsn0_link", "tsn0_mdio", "tsn0_rgmii", - "tsn0_txcrefclk"; - function = "tsn0"; - }; - - link { - groups = "tsn0_link"; - bias-disable; - }; - - mdio { - groups = "tsn0_mdio"; - drive-strength = <24>; - bias-disable; - }; - - rgmii { - groups = "tsn0_rgmii"; - drive-strength = <24>; - bias-disable; - }; - }; -}; - -&tsn0 { - pinctrl-0 = <&tsn0_pins>; - pinctrl-names = "default"; - phy-mode = "rgmii"; - phy-handle = <&phy3>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; - reset-post-delay-us = <4000>; - - phy3: ethernet-phy@0 { - compatible = "ethernet-phy-id002b.0980", - "ethernet-phy-ieee802.3-c22"; - reg = <0>; - interrupts-extended = <&gpio4 3 IRQ_TYPE_LEVEL_LOW>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/white-hawk-single.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-single.dtsi new file mode 100644 index 000000000000..20e8232f2f32 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/white-hawk-single.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the White Hawk Single board + * + * Copyright (C) 2023-2024 Glider bv + */ + +#include "white-hawk-cpu-common.dtsi" +#include "white-hawk-common.dtsi" + +/ { + model = "Renesas White Hawk Single board"; + compatible = "renesas,white-hawk-single"; +}; + +&hscif0 { + uart-has-rtscts; +}; + +&hscif0_pins { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; +}; + +&pfc { + tsn0_pins: tsn0 { + mux { + groups = "tsn0_link", "tsn0_mdio", "tsn0_rgmii", + "tsn0_txcrefclk"; + function = "tsn0"; + }; + + link { + groups = "tsn0_link"; + bias-disable; + }; + + mdio { + groups = "tsn0_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "tsn0_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; +}; + +&tsn0 { + pinctrl-0 = <&tsn0_pins>; + pinctrl-names = "default"; + phy-mode = "rgmii"; + phy-handle = <&phy3>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + phy3: ethernet-phy@0 { + compatible = "ethernet-phy-id002b.0980", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupts-extended = <&gpio4 3 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; From f7cd4b412020e71ab4c248c908558c67248a8392 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 Dec 2024 17:30:10 +0100 Subject: [PATCH 08/33] arm64: dts: renesas: Add R8A779G3 SoC support Add support for the Renesas R-Car V4H ES3.0 (R8A779G3) SoC, which is an updated version of the R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Kuninori Morimoto Link: https://lore.kernel.org/978c41f932aa2dccd46ad91fc1ddfabacd1c254c.1733156661.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g3.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g3.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a779g3.dtsi b/arch/arm64/boot/dts/renesas/r8a779g3.dtsi new file mode 100644 index 000000000000..0295858a0260 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H (R8A779G3) SoC + * + * Copyright (C) 2024 Glider bv + */ + +#include "r8a779g0.dtsi" + +/ { + compatible = "renesas,r8a779g3", "renesas,r8a779g0"; +}; From bf6b3ccda3e6797c6b7b774726fe29a1c4602e95 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 Dec 2024 17:30:11 +0100 Subject: [PATCH 09/33] arm64: dts: renesas: r8a779g3: Add White Hawk Single support The White Hawk Single board with R-Car V4H ES3.0 (R8A779G3) uses an updated version of the R-Car V4H (R8A779G0) SoC. For now, there are no visible differences compared to the variant equipped with an R-Car V4H ES2.0 (R8A779G2) SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Kuninori Morimoto Link: https://lore.kernel.org/66d0fe78c393e6df2775287c730464e91732ec56.1733156661.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/Makefile | 2 ++ .../dts/renesas/r8a779g3-white-hawk-single.dts | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g3-white-hawk-single.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 97228a3cb99c..df9ea5b2e208 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -92,6 +92,8 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single.dtb + dtb-$(CONFIG_ARCH_R8A779H0) += r8a779h0-gray-hawk-single.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-white-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779g3-white-hawk-single.dts new file mode 100644 index 000000000000..cd466d858854 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-white-hawk-single.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H ES3.0 White Hawk Single board + * + * Copyright (C) 2024 Glider bv + */ + +/dts-v1/; +#include "r8a779g3.dtsi" +#include "white-hawk-single.dtsi" + +/ { + model = "Renesas White Hawk Single board based on r8a779g3"; + compatible = "renesas,white-hawk-single", "renesas,r8a779g3", + "renesas,r8a779g0"; +}; From b72dc7b9e388e1a5997c1ab3239947ff23fe3f72 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 5 Dec 2024 13:53:48 +0100 Subject: [PATCH 10/33] arm64: dts: renesas: white-hawk-ard-audio: Drop SoC part The White Hawk with ARD-AUDIO-DA7212 external audio board stack is not specific to R8A779G0. Hence rename its DTS file name to drop the "r8a779g0-" prefix. Signed-off-by: Geert Uytterhoeven Reviewed-by: Kuninori Morimoto Link: https://lore.kernel.org/0a72c67991828784066f76b61605d2f7913a353c.1733402907.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/Makefile | 4 ++-- ...ard-audio-da7212.dtso => white-hawk-ard-audio-da7212.dtso} | 0 2 files changed, 2 insertions(+), 2 deletions(-) rename arch/arm64/boot/dts/renesas/{r8a779g0-white-hawk-ard-audio-da7212.dtso => white-hawk-ard-audio-da7212.dtso} (100%) diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index df9ea5b2e208..dea812ba55f3 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -86,8 +86,8 @@ dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f4-s4sk.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-cpu.dtb -dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtbo -r8a779g0-white-hawk-ard-audio-da7212-dtbs := r8a779g0-white-hawk.dtb r8a779g0-white-hawk-ard-audio-da7212.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += white-hawk-ard-audio-da7212.dtbo +r8a779g0-white-hawk-ard-audio-da7212-dtbs := r8a779g0-white-hawk.dtb white-hawk-ard-audio-da7212.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso b/arch/arm64/boot/dts/renesas/white-hawk-ard-audio-da7212.dtso similarity index 100% rename from arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso rename to arch/arm64/boot/dts/renesas/white-hawk-ard-audio-da7212.dtso From b0cf8110843ad2ee4c9665e1f590069108fe1881 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 5 Dec 2024 13:53:49 +0100 Subject: [PATCH 11/33] arm64: dts: renesas: white-hawk-single: Add R-Car Sound support White Hawk Single boards can use the same ARD-AUDIO-DA7212 external audio board as the White Hawk board stack. Add support for building DTBs for them, and document the small differences in connector labels. Signed-off-by: Geert Uytterhoeven Reviewed-by: Kuninori Morimoto Link: https://lore.kernel.org/7c840b6e08e0af8a6b9bd5516969eb585f16e10a.1733402907.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/Makefile | 4 ++++ .../arm64/boot/dts/renesas/white-hawk-ard-audio-da7212.dtso | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index dea812ba55f3..68031d0f28fb 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -91,8 +91,12 @@ r8a779g0-white-hawk-ard-audio-da7212-dtbs := r8a779g0-white-hawk.dtb white-hawk- dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single.dtb +r8a779g2-white-hawk-single-ard-audio-da7212-dtbs := r8a779g2-white-hawk-single.dtb white-hawk-ard-audio-da7212.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single-ard-audio-da7212.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single.dtb +r8a779g3-white-hawk-single-ard-audio-da7212-dtbs := r8a779g3-white-hawk-single.dtb white-hawk-ard-audio-da7212.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-white-hawk-single-ard-audio-da7212.dtb dtb-$(CONFIG_ARCH_R8A779H0) += r8a779h0-gray-hawk-single.dtb diff --git a/arch/arm64/boot/dts/renesas/white-hawk-ard-audio-da7212.dtso b/arch/arm64/boot/dts/renesas/white-hawk-ard-audio-da7212.dtso index e6cf304c77ee..c27b9b3d4e5f 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-ard-audio-da7212.dtso +++ b/arch/arm64/boot/dts/renesas/white-hawk-ard-audio-da7212.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Device Tree Source for the White Hawk board with ARD-AUDIO-DA7212 Board + * Device Tree Source for White Hawk (Single) board with ARD-AUDIO-DA7212 board * * You can find and buy "ARD-AUDIO-DA7212" at Digi-Key * @@ -27,12 +27,12 @@ * +----------------------------+ * |Breakout board | * | | +---------------+ - * |CN34 (I2C CN) | |J1 | + * |CN(30)34 (I2C CN) | |J1 | * | I2C0_SCL pin3 |<----->| pin20 SCL | * | I2C0_SDA pin5 |<----->| pin18 SDA | * | | +---------------+ * | | +-----------------------+ - * |CN4 (Power) | |J7 | + * |CN(300)4 (Power) | |J7 | * | 3v3 (v) pin9 |<----->| pin4 / pin8 3.3v | * | GND (v) pin3 / pin4 |<----->| pin12 / pin14 GND | * +----------------------------+ +-----------------------+ From b47325cc1f7820e01755acca9ee09d1de240e7d4 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 20 Nov 2024 11:30:46 +0100 Subject: [PATCH 12/33] ARM: dts: renesas: r7s72100: Add DMA support to RSPI Add DMA properties to the device nodes for Renesas Serial Peripheral Interfaces. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/dfafc16b840630f20e75292d419479294558e173.1732098491.git.geert+renesas@glider.be --- arch/arm/boot/dts/renesas/r7s72100.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r7s72100.dtsi b/arch/arm/boot/dts/renesas/r7s72100.dtsi index b831bbc431ef..1a866dbaf5e9 100644 --- a/arch/arm/boot/dts/renesas/r7s72100.dtsi +++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi @@ -238,6 +238,8 @@ spi0: spi@e800c800 { ; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI0>; + dmas = <&dmac 0x2d21>, <&dmac 0x2d22>; + dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; @@ -253,6 +255,8 @@ spi1: spi@e800d000 { ; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI1>; + dmas = <&dmac 0x2d25>, <&dmac 0x2d26>; + dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; @@ -268,6 +272,8 @@ spi2: spi@e800d800 { ; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI2>; + dmas = <&dmac 0x2d29>, <&dmac 0x2d2a>; + dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; @@ -283,6 +289,8 @@ spi3: spi@e800e000 { ; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI3>; + dmas = <&dmac 0x2d2d>, <&dmac 0x2d2e>; + dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; @@ -298,6 +306,8 @@ spi4: spi@e800e800 { ; interrupt-names = "error", "rx", "tx"; clocks = <&mstp10_clks R7S72100_CLK_SPI4>; + dmas = <&dmac 0x2d31>, <&dmac 0x2d32>; + dma-names = "tx", "rx"; power-domains = <&cpg_clocks>; num-cs = <1>; #address-cells = <1>; From 4fd66d72b9d0b2b343332aec309ae8861f881181 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Fri, 6 Dec 2024 11:32:41 +0200 Subject: [PATCH 13/33] arm64: dts: renesas: gray-hawk-single: Fix indentation Fix the indent on the two regulators. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Tested-by: Geert Uytterhoeven Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241206-rcar-gh-dsi-v3-8-d74c2166fa15@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r8a779h0-gray-hawk-single.dts | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index 58eabcc7e0e0..a455450d6987 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -133,21 +133,21 @@ pcie_clk: clk-9fgv0841-pci { }; reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; }; reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; }; sound_mux: sound-mux { From c2484af44be1ee55cc9116fcde2b4dffe9bfcf5d Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Fri, 6 Dec 2024 11:32:42 +0200 Subject: [PATCH 14/33] arm64: dts: renesas: r8a779h0: Add display support Add the device nodes for supporting DU and DSI. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Tested-by: Geert Uytterhoeven Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241206-rcar-gh-dsi-v3-9-d74c2166fa15@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 73 +++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index facfff4b9cdc..d0c01c0fdda2 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -1900,6 +1900,50 @@ csi41isp1: endpoint { }; }; + fcpvd0: fcp@fea10000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea10000 0 0x200>; + clocks = <&cpg CPG_MOD 508>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 508>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 830>; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 830>; + renesas,fcp = <&fcpvd0>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a779h0"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = ; + clocks = <&cpg CPG_MOD 411>; + clock-names = "du.0"; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 411>; + reset-names = "du.0"; + renesas,vsps = <&vspd0 0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi0: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + }; + isp0: isp@fed00000 { compatible = "renesas,r8a779h0-isp", "renesas,rcar-gen4-isp"; @@ -2068,6 +2112,35 @@ isp1vin15: endpoint { }; }; + dsi0: dsi-encoder@fed80000 { + compatible = "renesas,r8a779h0-dsi-csi2-tx"; + reg = <0 0xfed80000 0 0x10000>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779H0_CLK_DSIEXT>, + <&cpg CPG_CORE R8A779H0_CLK_DSIREF>; + clock-names = "fck", "dsi", "pll"; + power-domains = <&sysc R8A779H0_PD_C4>; + resets = <&cpg 415>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From b1000645dc29701fafd12d0c6f22ab080de6ab43 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Fri, 6 Dec 2024 11:32:43 +0200 Subject: [PATCH 15/33] arm64: dts: renesas: gray-hawk-single: Add DisplayPort support Add support for the mini DP output on the Gray Hawk board. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart Tested-by: Geert Uytterhoeven Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241206-rcar-gh-dsi-v3-10-d74c2166fa15@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r8a779h0-gray-hawk-single.dts | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index a455450d6987..521d4ea94aa8 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -59,6 +59,12 @@ chosen { stdout-path = "serial0:921600n8"; }; + sn65dsi86_refclk: clk-x6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; + keys { compatible = "gpio-keys"; @@ -132,6 +138,27 @@ pcie_clk: clk-9fgv0841-pci { #clock-cells = <0>; }; + mini-dp-con { + compatible = "dp-connector"; + label = "CN5"; + type = "mini"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint = <&sn65dsi86_out0>; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -205,6 +232,25 @@ channel1 { }; }; +&dsi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi86_in0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -284,6 +330,55 @@ eeprom@53 { }; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + bridge@2c { + pinctrl-0 = <&irq0_pins>; + pinctrl-names = "default"; + + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + interrupts-extended = <&intc_ex 0 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + vcca-supply = <®_1p2v>; + vcc-supply = <®_1p2v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sn65dsi86_in0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + sn65dsi86_out0: endpoint { + remote-endpoint = <&mini_dp_con_in>; + }; + }; + }; + }; +}; + &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; @@ -388,11 +483,21 @@ i2c0_pins: i2c0 { function = "i2c0"; }; + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + i2c3_pins: i2c3 { groups = "i2c3"; function = "i2c3"; }; + irq0_pins: irq0_pins { + groups = "intc_ex_irq0_a"; + function = "intc_ex"; + }; + keys_pins: keys { pins = "GP_5_0", "GP_5_1", "GP_5_2"; bias-pull-up; From e7402a7983de1c7148ee0fdc024fe5242f2c3357 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Mon, 9 Dec 2024 13:55:04 +0100 Subject: [PATCH 16/33] arm64: dts: renesas: gray-hawk-single: Add video capture support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Gray-Hawk single board contains two MAX96724 connected to the using I2C and CSI-2, record the connections. Also enable all nodes (VIN, CSI-2 and ISP) that are part of the downstream video capture pipeline. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241209125504.2010984-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r8a779h0-gray-hawk-single.dts | 169 ++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index 521d4ea94aa8..18fd52f55de5 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -30,6 +30,7 @@ #include #include #include +#include #include "r8a779h0.dtsi" @@ -251,6 +252,46 @@ &du { status = "okay"; }; +&csi40 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi40_in: endpoint { + bus-type = ; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max96724_out0>; + }; + }; + }; +}; + +&csi41 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi41_in: endpoint { + bus-type = ; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max96724_out1>; + }; + }; + }; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -301,6 +342,20 @@ io_expander_a: gpio@20 { #interrupt-cells = <2>; }; + io_expander_b: gpio@21 { + compatible = "onnn,pca9654"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + io_expander_c: gpio@22 { + compatible = "onnn,pca9654"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + eeprom@50 { compatible = "rohm,br24g01", "atmel,24c01"; label = "cpu-board"; @@ -377,6 +432,48 @@ sn65dsi86_out0: endpoint { }; }; }; + + gmsl0: gmsl-deserializer@4e { + compatible = "maxim,max96724"; + reg = <0x4e>; + enable-gpios = <&io_expander_b 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + max96724_out0: endpoint { + bus-type = ; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + }; + + gmsl1: gmsl-deserializer@4f { + compatible = "maxim,max96724"; + reg = <0x4f>; + enable-gpios = <&io_expander_c 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + max96724_out1: endpoint { + bus-type = ; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi41_in>; + }; + }; + }; + }; }; &i2c3 { @@ -402,6 +499,14 @@ ak4619_endpoint: endpoint { }; }; +&isp0 { + status = "okay"; +}; + +&isp1 { + status = "okay"; +}; + &mmc0 { pinctrl-0 = <&mmc_pins>; pinctrl-1 = <&mmc_pins>; @@ -599,3 +704,67 @@ &scif_clk { &scif_clk2 { clock-frequency = <24000000>; }; + +&vin00 { + status = "okay"; +}; + +&vin01 { + status = "okay"; +}; + +&vin02 { + status = "okay"; +}; + +&vin03 { + status = "okay"; +}; + +&vin04 { + status = "okay"; +}; + +&vin05 { + status = "okay"; +}; + +&vin06 { + status = "okay"; +}; + +&vin07 { + status = "okay"; +}; + +&vin08 { + status = "okay"; +}; + +&vin09 { + status = "okay"; +}; + +&vin10 { + status = "okay"; +}; + +&vin11 { + status = "okay"; +}; + +&vin12 { + status = "okay"; +}; + +&vin13 { + status = "okay"; +}; + +&vin14 { + status = "okay"; +}; + +&vin15 { + status = "okay"; +}; From ceaa1428e197d9d273ceaf60b8a7bbb3a60565b3 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 3 Dec 2024 10:49:29 +0000 Subject: [PATCH 17/33] dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants Document Renesas RZ/G3E (R9A09G047) SoC variants. Acked-by: Conor Dooley Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241203105005.103927-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/soc/renesas/renesas.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index b7acb65bdecd..52df3acfb1c5 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -525,6 +525,19 @@ properties: - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0 - const: renesas,r9a09g011 + - description: RZ/G3E (R9A09G047) + items: + - enum: + - renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA) + - renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA) + - renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA) + - renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA) + - renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA) + - renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA) + - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA) + - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA) + - const: renesas,r9a09g047 + - description: RZ/V2H(P) (R9A09G057) items: - enum: From 2bf1a3ca1df7ed93e5ac82ff672753a4edbb6e80 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 3 Dec 2024 10:49:30 +0000 Subject: [PATCH 18/33] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK Document the Renesas RZ/G3E SMARC Carrier-II EVK board which is based on the Renesas RZ/G3E SMARC SoM. The RZ/G3E SMARC Carrier-II EVK consists of an RZ/G3E SoM module and a SMARC Carrier-II carrier board. The SoM module sits on top of the carrier board. Signed-off-by: Biju Das Acked-by: Rob Herring (Arm) Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241203105005.103927-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 52df3acfb1c5..a8da7573cdaf 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -527,6 +527,10 @@ properties: - description: RZ/G3E (R9A09G047) items: + - enum: + - renesas,smarc2-evk # RZ SMARC Carrier-II EVK + - enum: + - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM) - enum: - renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA) - renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA) From 25458fdd39a18a5ce00c36f38992da54bb7453f3 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 3 Dec 2024 10:49:31 +0000 Subject: [PATCH 19/33] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG Document the device tree bindings for the Renesas RZ/G3E SoC Clock Pulse Generator (CPG). Also define constants for the core clocks of the RZ/G3E SoC. Acked-by: Conor Dooley Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241203105005.103927-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../bindings/clock/renesas,rzv2h-cpg.yaml | 15 +++++++------ .../dt-bindings/clock/renesas,r9a09g047-cpg.h | 21 +++++++++++++++++++ 2 files changed, 30 insertions(+), 6 deletions(-) create mode 100644 include/dt-bindings/clock/renesas,r9a09g047-cpg.h diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index 926c503bed1f..c3fe76abd549 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -4,19 +4,22 @@ $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG) +title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG) maintainers: - Lad Prabhakar description: - On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation - and control of clock signals for the IP modules, generation and control of resets, - and control over booting, low power consumption and power supply domains. + On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles + generation and control of clock signals for the IP modules, generation and + control of resets, and control over booting, low power consumption and power + supply domains. properties: compatible: - const: renesas,r9a09g057-cpg + enum: + - renesas,r9a09g047-cpg # RZ/G3E + - renesas,r9a09g057-cpg # RZ/V2H reg: maxItems: 1 @@ -37,7 +40,7 @@ properties: description: | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" and a core clock reference, as defined in - , + , - For module clocks, the two clock specifier cells must be "CPG_MOD" and a module number. The module number is calculated as the CLKON register offset index multiplied by 16, plus the actual bit in the register diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h new file mode 100644 index 000000000000..1d031bf6bf03 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ + +#include + +/* Core Clock list */ +#define R9A09G047_SYS_0_PCLK 0 +#define R9A09G047_CA55_0_CORECLK0 1 +#define R9A09G047_CA55_0_CORECLK1 2 +#define R9A09G047_CA55_0_CORECLK2 3 +#define R9A09G047_CA55_0_CORECLK3 4 +#define R9A09G047_CA55_0_PERIPHCLK 5 +#define R9A09G047_CM33_CLK0 6 +#define R9A09G047_CST_0_SWCLKTCK 7 +#define R9A09G047_IOTOP_0_SHCLK 8 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ From 95605458312787fadff4001b1df53154451c05a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Wed, 23 Oct 2024 17:46:42 +0200 Subject: [PATCH 20/33] arm64: dts: renesas: r8a779a0: Remove address- and size-cells from AVB[1-5] MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When describing the PHYs on the Falcon Ethernet breakout board mdio nodes will be needed to describe the connections, and each mdio node will need to contain these two properties instead. This will make the address-cells and size-cells described in the base SoC include file redundant and they will produce warnings, remove them. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241023154643.4025941-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 7156b1a542e8..fe6d97859e4a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -765,8 +765,6 @@ avb1: ethernet@e6810000 { rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds1 1>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -814,8 +812,6 @@ avb2: ethernet@e6820000 { rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds1 2>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -863,8 +859,6 @@ avb3: ethernet@e6830000 { rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds1 3>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -912,8 +906,6 @@ avb4: ethernet@e6840000 { rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds1 4>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -961,8 +953,6 @@ avb5: ethernet@e6850000 { rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds1 11>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; From a57e6e1fe02e2499663c409f039eab7a746af11d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Wed, 23 Oct 2024 17:46:43 +0200 Subject: [PATCH 21/33] arm64: dts: renesas: falcon-ethernet: Describe PHYs connected on the breakout board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Describe and connect the five Marvell 88Q2110 PHYs present on the Falcon Ethernet breakout board. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241023154643.4025941-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r8a779a0-falcon-ethernet.dtsi | 242 ++++++++++++++++++ 1 file changed, 242 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-ethernet.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-ethernet.dtsi index e11bf9ace776..2a8537e13873 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-ethernet.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-ethernet.dtsi @@ -5,6 +5,121 @@ * Copyright (C) 2021 Glider bv */ +/ { + aliases { + ethernet1 = &avb1; + ethernet2 = &avb2; + ethernet3 = &avb3; + ethernet4 = &avb4; + ethernet5 = &avb5; + }; +}; + +&avb1 { + pinctrl-0 = <&avb1_pins>; + pinctrl-names = "default"; + phy-handle = <&avb1_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio5 15 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb1_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <7>; + interrupts-extended = <&gpio5 16 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&avb2 { + pinctrl-0 = <&avb2_pins>; + pinctrl-names = "default"; + phy-handle = <&avb2_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb2_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <7>; + interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&avb3 { + pinctrl-0 = <&avb3_pins>; + pinctrl-names = "default"; + phy-handle = <&avb3_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb3_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <7>; + interrupts-extended = <&gpio7 16 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&avb4 { + pinctrl-0 = <&avb4_pins>; + pinctrl-names = "default"; + phy-handle = <&avb4_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio8 15 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb4_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <7>; + interrupts-extended = <&gpio8 16 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&avb5 { + pinctrl-0 = <&avb5_pins>; + pinctrl-names = "default"; + phy-handle = <&avb5_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio9 15 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb5_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <7>; + interrupts-extended = <&gpio9 16 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + &i2c0 { eeprom@53 { compatible = "rohm,br24g01", "atmel,24c01"; @@ -13,3 +128,130 @@ eeprom@53 { pagesize = <8>; }; }; + +&pfc { + avb1_pins: avb1 { + mux { + groups = "avb1_link", "avb1_mdio", "avb1_rgmii", + "avb1_txcrefclk"; + function = "avb1"; + }; + + link { + groups = "avb1_link"; + bias-disable; + }; + + mdio { + groups = "avb1_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb1_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; + + avb2_pins: avb2 { + mux { + groups = "avb2_link", "avb2_mdio", "avb2_rgmii", + "avb2_txcrefclk"; + function = "avb2"; + }; + + link { + groups = "avb2_link"; + bias-disable; + }; + + mdio { + groups = "avb2_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb2_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; + + avb3_pins: avb3 { + mux { + groups = "avb3_link", "avb3_mdio", "avb3_rgmii", + "avb3_txcrefclk"; + function = "avb3"; + }; + + link { + groups = "avb3_link"; + bias-disable; + }; + + mdio { + groups = "avb3_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb3_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; + + avb4_pins: avb4 { + mux { + groups = "avb4_link", "avb4_mdio", "avb4_rgmii", + "avb4_txcrefclk"; + function = "avb4"; + }; + + link { + groups = "avb4_link"; + bias-disable; + }; + + mdio { + groups = "avb4_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb4_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; + + avb5_pins: avb5 { + mux { + groups = "avb5_link", "avb5_mdio", "avb5_rgmii", + "avb5_txcrefclk"; + function = "avb5"; + }; + + link { + groups = "avb5_link"; + bias-disable; + }; + + mdio { + groups = "avb5_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb5_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; +}; From 9977754eeebed749a071492d98e46700307c0bd1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 3 Dec 2024 10:49:36 +0000 Subject: [PATCH 22/33] arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC Add the initial DTSI for the RZ/G3E SoC. The files in this commit have the following meaning: - r9a09g047.dtsi: RZ/G3E family SoC common parts - r9a09g047e57.dtsi: RZ/G3E R0A09G047E{4,5}{7,8} SoC specific parts - r9a09g047e37.dtsi: RZ/G3E R0A09G047E{2,3}{7,8} SoC specific parts Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241203105005.103927-10-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 144 ++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi | 18 +++ arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi | 13 ++ 3 files changed, 175 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi new file mode 100644 index 000000000000..4176b9aa6892 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3E SoC + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a09g047"; + #address-cells = <2>; + #size-cells = <2>; + + audio_extal_clk: audio-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a55"; + reg = <0x200>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a55"; + reg = <0x300>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x100000>; + cache-level = <3>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + qextal_clk: qextal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + rtxin_clk: rtxin-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@10420000 { + compatible = "renesas,r9a09g047-cpg"; + reg = <0 0x10420000 0 0x10000>; + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; + clock-names = "audio_extal", "rtxin", "qextal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + scif0: serial@11c01400 { + compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; + reg = <0 0x11c01400 0 0x400>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "bri", "dri", + "tei", "tei-dri", "rxi-edge", "txi-edge"; + clocks = <&cpg CPG_MOD 0x8f>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg 0x95>; + status = "disabled"; + }; + + gic: interrupt-controller@14900000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x14900000 0 0x20000>, + <0x0 0x14940000 0 0x80000>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi new file mode 100644 index 000000000000..e50d9159e832 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3E R9A09G047E37 SoC specific parts + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a09g047.dtsi" + +/ { + compatible = "renesas,r9a09g047e37", "renesas,r9a09g047"; + + cpus { + /delete-node/ cpu@200; + /delete-node/ cpu@300; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi new file mode 100644 index 000000000000..98a5faebd47a --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3E R9A09G047E57 SoC specific parts + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a09g047.dtsi" + +/ { + compatible = "renesas,r9a09g047e57", "renesas,r9a09g047"; +}; From 8e96597f3c25007d292eabba9cfc9612e7d90f0f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 3 Dec 2024 10:49:37 +0000 Subject: [PATCH 23/33] arm64: dts: renesas: r9a09g047: Add OPP table Add OPP table for RZ/G3E SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241203105005.103927-11-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 4176b9aa6892..39a7cfb3095b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { clock-frequency = <0>; }; + /* + * The default cluster table is based on the assumption that the PLLCA55 clock + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be + * clocked to 1.8GHz as well). The table below should be overridden in the board + * DTS based on the PLLCA55 clock frequency. + */ + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + }; + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + }; + opp-425000000 { + opp-hz = /bits/ 64 <425000000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + }; + opp-212500000 { + opp-hz = /bits/ 64 <212500000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -30,6 +63,8 @@ cpu0: cpu@0 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -38,6 +73,8 @@ cpu1: cpu@100 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@200 { @@ -46,6 +83,8 @@ cpu2: cpu@200 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@300 { @@ -54,6 +93,8 @@ cpu3: cpu@300 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { From e0379695728b0d79c20bc1a904bb4168d4f117c0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 3 Dec 2024 10:49:38 +0000 Subject: [PATCH 24/33] arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM Add initial support for the RZ/G3E SMARC SoM with 4GB memory, audio_extal, qextal and rtxin clks. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241203105005.103927-12-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi new file mode 100644 index 000000000000..6b583ae2ac52 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R9A09G047E57 SMARC SoM board. + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/ { + compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047"; + + memory@48000000 { + device_type = "memory"; + /* First 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0xf8000000>; + }; +}; + +&audio_extal_clk { + clock-frequency = <48000000>; +}; + +&qextal_clk { + clock-frequency = <24000000>; +}; + +&rtxin_clk { + clock-frequency = <32768>; +}; From c4d87fe3cd4eab905f235ecfdd09313be9bc0e99 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 3 Dec 2024 10:49:39 +0000 Subject: [PATCH 25/33] arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board Add the initial device tree for the Renesas RZ/G3E SMARC EVK board. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241203105005.103927-13-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 ++ .../boot/dts/renesas/r9a09g047e57-smarc.dts | 18 ++++++++++++++ .../boot/dts/renesas/renesas-smarc2.dtsi | 24 +++++++++++++++++++ 3 files changed, 44 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 68031d0f28fb..928635f2e76b 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -146,6 +146,8 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb +dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb + dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts new file mode 100644 index 000000000000..d4d61bd03969 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3E SMARC EVK board + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a09g047e57.dtsi" +#include "rzg3e-smarc-som.dtsi" +#include "renesas-smarc2.dtsi" + +/ { + model = "Renesas SMARC EVK version 2 based on r9a09g047e57"; + compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm", + "renesas,r9a09g047e57", "renesas,r9a09g047"; +}; diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi new file mode 100644 index 000000000000..e378d55e6e9b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ SMARC Carrier-II Board. + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/ { + model = "Renesas RZ SMARC Carrier-II Board"; + compatible = "renesas,smarc2-evk"; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial3:115200n8"; + }; + + aliases { + serial3 = &scif0; + }; +}; + +&scif0 { + status = "okay"; +}; From 78f2c089d0797fbf677a415aeeba8061b442027b Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 6 Dec 2024 13:13:36 +0200 Subject: [PATCH 26/33] arm64: dts: renesas: r9a08g045: Add ADC node Add the device tree node for the ADC IP available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241206111337.726244-15-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 5b15ff2482ab..66b6a23d8eb7 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -177,6 +177,59 @@ rtc: rtc@1004ec00 { status = "disabled"; }; + adc: adc@10058000 { + compatible = "renesas,r9a08g045-adc"; + reg = <0 0x10058000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>, + <&cpg CPG_MOD R9A08G045_ADC_PCLK>; + clock-names = "adclk", "pclk"; + resets = <&cpg R9A08G045_ADC_PRESETN>, + <&cpg R9A08G045_ADC_ADRST_N>; + reset-names = "presetn", "adrst-n"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + status = "disabled"; + + channel@0 { + reg = <0>; + }; + + channel@1 { + reg = <1>; + }; + + channel@2 { + reg = <2>; + }; + + channel@3 { + reg = <3>; + }; + + channel@4 { + reg = <4>; + }; + + channel@5 { + reg = <5>; + }; + + channel@6 { + reg = <6>; + }; + + channel@7 { + reg = <7>; + }; + + channel@8 { + reg = <8>; + }; + }; + vbattb: clock-controller@1005c000 { compatible = "renesas,r9a08g045-vbattb"; reg = <0 0x1005c000 0 0x1000>; From 8cbf69bc74e1f365b0ef8caf5dd2ac994ce965e0 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 6 Dec 2024 13:13:37 +0200 Subject: [PATCH 27/33] arm64: dts: renesas: rzg3s-smarc-som: Enable ADC Enable ADC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241206111337.726244-16-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 55c72c8a0735..4ee91ea05261 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -89,6 +89,10 @@ vcc_sdhi2: regulator2 { }; }; +&adc { + status = "okay"; +}; + #if SW_CONFIG3 == SW_ON ð0 { pinctrl-0 = <ð0_pins>; From 880f6c84701cb7735d19f20db89e757086a8fcfa Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 10 Dec 2024 19:09:49 +0200 Subject: [PATCH 28/33] arm64: dts: renesas: r9a08g045: Add SSI nodes Add DT nodes for the SSI IPs available on the Renesas RZ/G3S SoC. Along with it external audio clocks were added. Board device tree could use it and update the frequencies. Reviewed-by: Biju Das Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241210170953.2936724-21-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 94 ++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 66b6a23d8eb7..a9b98db9ef95 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -14,6 +14,20 @@ / { #address-cells = <2>; #size-cells = <2>; + audio_clk1: audio1-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it. */ + clock-frequency = <0>; + }; + + audio_clk2: audio2-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -330,6 +344,86 @@ i2c3: i2c@10090c00 { status = "disabled"; }; + ssi0: ssi@100a8000 { + compatible = "renesas,r9a08g045-ssi", + "renesas,rz-ssi"; + reg = <0 0x100a8000 0 0x400>; + interrupts = , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A08G045_SSI0_PCLK2>, + <&cpg CPG_MOD R9A08G045_SSI0_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A08G045_SSI0_RST_M2_REG>; + dmas = <&dmac 0x2665>, <&dmac 0x2666>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi1: ssi@100a8400 { + compatible = "renesas,r9a08g045-ssi", + "renesas,rz-ssi"; + reg = <0 0x100a8400 0 0x400>; + interrupts = , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A08G045_SSI1_PCLK2>, + <&cpg CPG_MOD R9A08G045_SSI1_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A08G045_SSI1_RST_M2_REG>; + dmas = <&dmac 0x2669>, <&dmac 0x266a>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi2: ssi@100a8800 { + compatible = "renesas,r9a08g045-ssi", + "renesas,rz-ssi"; + reg = <0 0x100a8800 0 0x400>; + interrupts = , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A08G045_SSI2_PCLK2>, + <&cpg CPG_MOD R9A08G045_SSI2_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A08G045_SSI2_RST_M2_REG>; + dmas = <&dmac 0x266d>, <&dmac 0x266e>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi3: ssi@100a8c00 { + compatible = "renesas,r9a08g045-ssi", + "renesas,rz-ssi"; + reg = <0 0x100a8c00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; + clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>, + <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A08G045_SSI3_RST_M2_REG>; + dmas = <&dmac 0x2671>, <&dmac 0x2672>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a08g045-cpg"; reg = <0 0x11010000 0 0x10000>; From a94253232b0454ae3f45e2a941bbc0a1d5bdb955 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 10 Dec 2024 19:09:50 +0200 Subject: [PATCH 29/33] arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node Add versa3 clock generator node. It provides the clocks for the Ethernet PHY, PCIe, audio devices. Reviewed-by: Geert Uytterhoeven Reviewed-by: Biju Das Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241210170953.2936724-22-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 4ee91ea05261..5117de3c8c4b 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -87,6 +87,12 @@ vcc_sdhi2: regulator2 { gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>; enable-active-high; }; + + x3_clk: x3-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; &adc { @@ -151,6 +157,30 @@ &extal_clk { &i2c1 { status = "okay"; + + versa3: clock-generator@68 { + compatible = "renesas,5l35023"; + reg = <0x68>; + clocks = <&x3_clk>; + #clock-cells = <1>; + assigned-clocks = <&versa3 0>, + <&versa3 1>, + <&versa3 2>, + <&versa3 3>, + <&versa3 4>, + <&versa3 5>; + assigned-clock-rates = <24000000>, + <12288000>, + <11289600>, + <25000000>, + <100000000>, + <100000000>; + renesas,settings = [ + 80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27 + 00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86 + a0 80 30 30 9c + ]; + }; }; #if SW_CONFIG2 == SW_ON From c3de00ac31f76b8e3af9f7a85c2da29c1b72babf Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 10 Dec 2024 19:09:51 +0200 Subject: [PATCH 30/33] arm64: dts: renesas: Add da7212 audio codec node Add the da7212 audio codec node. Along with it regulators nodes were reworked to be able to re-use them on da7212. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241210170953.2936724-23-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 17 ++++++++++----- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 21 +++++++++++++++++++ 2 files changed, 33 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 5117de3c8c4b..ef12c1c462a7 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -58,7 +58,6 @@ vcc_sdhi0: regulator0 { enable-active-high; }; -#if SW_CONFIG2 == SW_ON vccq_sdhi0: regulator1 { compatible = "regulator-gpio"; regulator-name = "SDHI0 VccQ"; @@ -68,8 +67,8 @@ vccq_sdhi0: regulator1 { gpios-states = <1>; states = <3300000 1>, <1800000 0>; }; -#else - reg_1p8v: regulator1 { + + reg_1p8v: regulator2 { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; regulator-min-microvolt = <1800000>; @@ -77,9 +76,17 @@ reg_1p8v: regulator1 { regulator-boot-on; regulator-always-on; }; -#endif - vcc_sdhi2: regulator2 { + reg_3p3v: regulator3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi2: regulator4 { compatible = "regulator-fixed"; regulator-name = "SDHI2 Vcc"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index aaf7f9c7bdf9..1a6689e3c8b2 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -73,6 +73,27 @@ &i2c0 { status = "okay"; clock-frequency = <1000000>; + + da7212: codec@1a { + compatible = "dlg,da7212"; + reg = <0x1a>; + + clocks = <&versa3 1>; + clock-names = "mclk"; + + #sound-dai-cells = <0>; + + dlg,micbias1-lvl = <2500>; + dlg,micbias2-lvl = <2500>; + dlg,dmic-data-sel = "lrise_rfall"; + dlg,dmic-samplephase = "between_clkedge"; + dlg,dmic-clkrate = <3000000>; + + VDDA-supply = <®_1p8v>; + VDDSP-supply = <®_3p3v>; + VDDMIC-supply = <®_3p3v>; + VDDIO-supply = <®_1p8v>; + }; }; &i2c1 { From 558a25c2ee3815c3d59d4dd9440a1cb3a78d20ab Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 10 Dec 2024 19:09:52 +0200 Subject: [PATCH 31/33] arm64: dts: renesas: rzg3s-smarc: Enable SSI3 Enable SSI3. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241210170953.2936724-24-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 25 ++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 1a6689e3c8b2..f87f0c18a083 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -69,6 +69,10 @@ vccq_sdhi1: regulator-vccq-sdhi1 { }; }; +&audio_clk2 { + clock-frequency = <12288000>; +}; + &i2c0 { status = "okay"; @@ -110,6 +114,11 @@ power-monitor@44 { }; &pinctrl { + audio_clock_pins: audio-clock { + pins = "AUDIO_CLK1", "AUDIO_CLK2"; + input-enable; + }; + key-1-gpio-hog { gpio-hog; gpios = ; @@ -167,6 +176,13 @@ cd { pinmux = ; /* SD1_CD */ }; }; + + ssi3_pins: ssi3 { + pinmux = , /* BCK */ + , /* RCK */ + , /* TXD */ + ; /* RXD */ + }; }; &scif0 { @@ -187,3 +203,12 @@ &sdhi1 { max-frequency = <125000000>; status = "okay"; }; + +&ssi3 { + clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>, + <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>, + <&versa3 2>, <&audio_clk2>; + pinctrl-names = "default"; + pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>; + status = "okay"; +}; From 24bfc042ba3dc3692e206ff060eb22733b6d3ac0 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 10 Dec 2024 19:09:53 +0200 Subject: [PATCH 32/33] arm64: dts: renesas: rzg3s-smarc: Add sound card Add sound card with SSI3 as CPU DAI and DA7212 as codec DAI. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/20241210170953.2936724-25-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index f87f0c18a083..81b4ffd1417d 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -49,6 +49,23 @@ key-3 { }; }; + snd_rzg3s: sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&cpu_dai>; + simple-audio-card,frame-master = <&cpu_dai>; + simple-audio-card,mclk-fs = <256>; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&ssi3>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&da7212>; + clocks = <&versa3 1>; + }; + }; + vcc_sdhi1: regulator-vcc-sdhi1 { compatible = "regulator-fixed"; regulator-name = "SDHI1 Vcc"; From acb247afab5bc2b4462f4dfc17a9d930e1153e52 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 16 Dec 2024 12:00:25 +0000 Subject: [PATCH 33/33] arm64: dts: renesas: r9a09g047: Add I2C nodes Add I2C{0..8} nodes to RZ/G3E (R9A09G047) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241216120029.143944-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 189 +++++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 39a7cfb3095b..7a422e9ad29e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -162,6 +162,195 @@ scif0: serial@11c01400 { status = "disabled"; }; + i2c0: i2c@14400400 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14400400 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x94>; + resets = <&cpg 0x98>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@14400800 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14400800 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x95>; + resets = <&cpg 0x99>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@14400c00 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14400c00 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x96>; + resets = <&cpg 0x9a>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@14401000 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14401000 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x97>; + resets = <&cpg 0x9b>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@14401400 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14401400 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x98>; + resets = <&cpg 0x9c>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@14401800 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14401800 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x99>; + resets = <&cpg 0x9d>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@14401c00 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14401c00 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x9a>; + resets = <&cpg 0x9e>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@14402000 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x14402000 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x9b>; + resets = <&cpg 0x9f>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@11c01000 { + compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; + reg = <0 0x11c01000 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x93>; + resets = <&cpg 0xa0>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@14900000 { compatible = "arm,gic-v3"; reg = <0x0 0x14900000 0 0x20000>,