From 7222ae1d3e4e79a3df37a0668f3718a7898b35df Mon Sep 17 00:00:00 2001 From: Youssef Samir Date: Thu, 24 Oct 2024 23:47:15 +0200 Subject: [PATCH 1/3] bus: mhi: host: Free mhi_buf vector inside mhi_alloc_bhie_table() mhi_alloc_bhie_table() starts by allocating a vector of struct mhi_buf then it allocates a DMA buffer for each element. If allocation fails, it will free the allocated DMA buffers, but it neglects freeing the mhi_buf vector. Avoid memory leaks by freeing the mhi_buf vector on error. Fixes: 3000f85b8f47 ("bus: mhi: core: Add support for basic PM operations") Signed-off-by: Youssef Samir Reviewed-by: Jeffrey Hugo Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20241024214715.1208940-1-quic_yabdulra@quicinc.com Signed-off-by: Manivannan Sadhasivam --- drivers/bus/mhi/host/boot.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/bus/mhi/host/boot.c b/drivers/bus/mhi/host/boot.c index e8c92972f9df..9dcc7184817d 100644 --- a/drivers/bus/mhi/host/boot.c +++ b/drivers/bus/mhi/host/boot.c @@ -357,6 +357,7 @@ int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl, for (--i, --mhi_buf; i >= 0; i--, mhi_buf--) dma_free_coherent(mhi_cntrl->cntrl_dev, mhi_buf->len, mhi_buf->buf, mhi_buf->dma_addr); + kfree(img_info->mhi_buf); error_alloc_mhi_buf: kfree(img_info); From 9241459b3cc2e66252d32bef88e858dcf9c7c487 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Thu, 12 Dec 2024 17:27:27 +0530 Subject: [PATCH 2/3] bus: mhi: host: pci_generic: Add support for QDU100 device Add MHI controller configuration for QDU100 device. The Qualcomm X100 5G RAN Accelerator card is designed to enhance Open vRAN servers by offloading CPUs from intensive 5G baseband functions. Link: https://docs.qualcomm.com/bundle/publicresource/87-79371-1_REV_A_Qualcomm_X100_5G_RAN_Accelerator_Card_Product_Brief.pdf Signed-off-by: Vivek Pernamitta Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20241212-qdu100_us-v5-1-3349fb23512a@quicinc.com Signed-off-by: Manivannan Sadhasivam --- drivers/bus/mhi/host/pci_generic.c | 55 ++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c index 07645ce2119a..aa5118dbe2e5 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -245,6 +245,58 @@ struct mhi_pci_dev_info { .channel = ch_num, \ } +static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = { + MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2), + MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2), + MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1), + MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1), + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3), + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3), + MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3), + MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4), + MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4), + MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4), + MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4), + MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4), + MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4), + MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5), + MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5), +}; + +static struct mhi_event_config mhi_qcom_qdu100_events[] = { + /* first ring is control+data ring */ + MHI_EVENT_CONFIG_CTRL(0, 64), + /* SAHARA dedicated event ring */ + MHI_EVENT_CONFIG_SW_DATA(1, 256), + /* Software channels dedicated event ring */ + MHI_EVENT_CONFIG_SW_DATA(2, 64), + MHI_EVENT_CONFIG_SW_DATA(3, 256), + MHI_EVENT_CONFIG_SW_DATA(4, 256), + /* Software IP channels dedicated event ring */ + MHI_EVENT_CONFIG_SW_DATA(5, 512), + MHI_EVENT_CONFIG_SW_DATA(6, 512), + MHI_EVENT_CONFIG_SW_DATA(7, 512), +}; + +static const struct mhi_controller_config mhi_qcom_qdu100_config = { + .max_channels = 128, + .timeout_ms = 120000, + .num_channels = ARRAY_SIZE(mhi_qcom_qdu100_channels), + .ch_cfg = mhi_qcom_qdu100_channels, + .num_events = ARRAY_SIZE(mhi_qcom_qdu100_events), + .event_cfg = mhi_qcom_qdu100_events, +}; + +static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = { + .name = "qcom-qdu100", + .fw = "qcom/qdu100/xbl_s.melf", + .edl_trigger = true, + .config = &mhi_qcom_qdu100_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32, + .sideband_wake = false, +}; + static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), @@ -742,6 +794,9 @@ static const struct pci_device_id mhi_pci_id_table[] = { .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info }, { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info }, + /* QDU100, x100-DU */ + { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601), + .driver_data = (kernel_ulong_t) &mhi_qcom_qdu100_info }, { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ From 29904a40127ca5df120bcbcab444ea725926b075 Mon Sep 17 00:00:00 2001 From: Vivek Pernamitta Date: Wed, 8 Jan 2025 21:52:07 +0530 Subject: [PATCH 3/3] bus: mhi: host: pci_generic: Enable MSI-X if the endpoint supports Enable MSI-X if the endpoint supports. Signed-off-by: Vivek Pernamitta Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20250108-msix-v2-1-dc4466922350@quicinc.com [mani: added pci_generic prefix to subject] Signed-off-by: Manivannan Sadhasivam --- drivers/bus/mhi/host/pci_generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c index aa5118dbe2e5..3e28f4af58b3 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -1004,7 +1004,7 @@ static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl, */ mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events; - nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSI); + nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSIX | PCI_IRQ_MSI); if (nr_vectors < 0) { dev_err(&pdev->dev, "Error allocating MSI vectors %d\n", nr_vectors);