From ad38ea266b8dc6e15e0d2a14a9d8543345fdba44 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 31 Jul 2025 10:37:45 +0200 Subject: [PATCH 01/14] ARM: shmobile: rcar-gen2: Use SZ_256K definition Use SZ_256K instead of calculating the same value. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/c54097a263eb3e451e5e223609a3630d4409dcdd.1753951039.git.geert+renesas@glider.be --- arch/arm/mach-shmobile/pm-rcar-gen2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c index 907a4f8c5aed..46654d196f8d 100644 --- a/arch/arm/mach-shmobile/pm-rcar-gen2.c +++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c @@ -81,7 +81,7 @@ void __init rcar_gen2_pm_init(void) map: /* RAM for jump stub, because BAR requires 256KB aligned address */ - if (res.start & (256 * 1024 - 1) || + if (res.start & (SZ_256K - 1) || resource_size(&res) < shmobile_boot_size) { pr_err("Invalid smp-sram region\n"); return; From 6a3f890196b31b166a3e3e32735ff5c8116661cc Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 27 Aug 2025 16:54:25 +0200 Subject: [PATCH 02/14] ARM: at91: pm: fix .uhp_udp_mask specification for current SoCs All SoCs using this structure field .uhp_udp_mask in configuration index 4 don't have the bit 7 specified: sam9x60 nor sam9x75. Remove this bit from the mask definition to match register layout. This mask is used in function at91_pm_verify_clocks(). Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20250827145427.46819-2-nicolas.ferre@microchip.com Reviewed-by: Alexandre Belloni Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 3aa20038ad93..35058b99069c 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -1364,7 +1364,7 @@ static const struct pmc_info pmc_infos[] __initconst = { .version = AT91_PMC_V1, }, { - .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP, + .uhp_udp_mask = AT91SAM926x_PMC_UHP, .mckr = 0x28, .version = AT91_PMC_V2, }, From 296302d3d81360e09fa956e9be9edc8223b69a12 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 27 Aug 2025 16:54:26 +0200 Subject: [PATCH 03/14] ARM: at91: pm: fix MCKx restore routine The at91_mckx_ps_restore() assembly function is responsible for setting back MCKx system bus clocks after exiting low power modes. Fix a typo and use tmp3 variable instead of tmp2 to correctly set MCKx to previously saved state. Tmp2 was used without the needed changes in CSS and DIV. Moreover the required bit 7, telling that MCR register's content is to be changed (CMD/write), was not set. Fix function comment to match tmp variables actually used. Signed-off-by: Nicolas Ferre Fixes: 28eb1d40fe57 ("ARM: at91: pm: add support for MCK1..4 save/restore for ulp modes") Link: https://lore.kernel.org/r/20250827145427.46819-3-nicolas.ferre@microchip.com Reviewed-by: Alexandre Belloni [claudiu.beznea: s/sate/state in commit description] Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/pm_suspend.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index e23b86834096..7e6c94f8edee 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -904,7 +904,7 @@ e_done: /** * at91_mckx_ps_restore: restore MCKx settings * - * Side effects: overwrites tmp1, tmp2 + * Side effects: overwrites tmp1, tmp2 and tmp3 */ .macro at91_mckx_ps_restore #ifdef CONFIG_SOC_SAMA7 @@ -980,7 +980,7 @@ r_ps: bic tmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK orr tmp3, tmp3, tmp1 orr tmp3, tmp3, #AT91_PMC_MCR_V2_CMD - str tmp2, [pmc, #AT91_PMC_MCR_V2] + str tmp3, [pmc, #AT91_PMC_MCR_V2] wait_mckrdy tmp1 From 3cae7d18392feacf04354feac994c1b48eed91af Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Wed, 27 Aug 2025 16:54:27 +0200 Subject: [PATCH 04/14] ARM: at91: pm: save and restore ACR during PLL disable/enable Add a new word in assembly to store ACR value during the calls to at91_plla_disable/at91_plla_enable macros and use it. Signed-off-by: Nicolas Ferre [cristian.birsan@microchip.com: remove ACR_DEFAULT_PLLA loading] Signed-off-by: Cristian Birsan Link: https://lore.kernel.org/r/20250827145427.46819-4-nicolas.ferre@microchip.com Reviewed-by: Alexandre Belloni Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/pm_suspend.S | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index 7e6c94f8edee..aad53ec9e957 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -689,6 +689,10 @@ sr_dis_exit: bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID str tmp2, [pmc, #AT91_PMC_PLL_UPDT] + /* save acr */ + ldr tmp2, [pmc, #AT91_PMC_PLL_ACR] + str tmp2, .saved_acr + /* save div. */ mov tmp1, #0 ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0] @@ -758,7 +762,7 @@ sr_dis_exit: str tmp1, [pmc, #AT91_PMC_PLL_UPDT] /* step 2. */ - ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA + ldr tmp1, .saved_acr str tmp1, [pmc, #AT91_PMC_PLL_ACR] /* step 3. */ @@ -1207,6 +1211,8 @@ ENDPROC(at91_pm_suspend_in_sram) #endif .saved_mckr: .word 0 +.saved_acr: + .word 0 .saved_pllar: .word 0 .saved_sam9_lpr: From 8a6506e1ba0d2b831729808d958aae77604f12f9 Mon Sep 17 00:00:00 2001 From: Alexander Sverdlin Date: Thu, 17 Jul 2025 17:27:03 +0200 Subject: [PATCH 05/14] ARM: AM33xx: Implement TI advisory 1.0.36 (EMU0/EMU1 pins state on reset) There is an issue possible where TI AM33xx SoCs do not boot properly after a reset if EMU0/EMU1 pins were used as GPIO and have been driving low level actively prior to reset [1]. "Advisory 1.0.36 EMU0 and EMU1: Terminals Must be Pulled High Before ICEPick Samples The state of the EMU[1:0] terminals are latched during reset to determine ICEPick boot mode. For normal device operation, these terminals must be pulled up to a valid high logic level ( > VIH min) before ICEPick samples the state of these terminals, which occurs [five CLK_M_OSC clock cycles - 10 ns] after the falling edge of WARMRSTn. Many applications may not require the secondary GPIO function of the EMU[1:0] terminals. In this case, they would only be connected to pull-up resistors, which ensures they are always high when ICEPick samples. However, some applications may need to use these terminals as GPIO where they could be driven low before reset is asserted. This usage of the EMU[1:0] terminals may require special attention to ensure the terminals are allowed to return to a valid high-logic level before ICEPick samples the state of these terminals. When any device reset is asserted, the pin mux mode of EMU[1:0] terminals configured to operate as GPIO (mode 7) will change back to EMU input (mode 0) on the falling edge of WARMRSTn. This only provides a short period of time for the terminals to return high if driven low before reset is asserted... If the EMU[1:0] terminals are configured to operate as GPIO, the product should be designed such these terminals can be pulled to a valid high-logic level within 190 ns after the falling edge of WARMRSTn." We've noticed this problem with custom am335x hardware in combination with recently implemented cold reset method (commit 6521f6a195c70 ("ARM: AM33xx: PRM: Implement REBOOT_COLD")). It looks like the problem can affect other HW, for instance AM335x Chiliboard, because the latter has LEDs on GPIO3_7/GPIO3_8 as well. One option would be to check if the pins are in GPIO mode and either switch to output active high, or switch to input and poll until the external pull-ups have brought the pins to the desired high state. But fighting with GPIO driver for these pins is probably not the most straight forward approch in a reboot handler. Fortunately we can easily control pinmuxing here and rely on the external pull-ups. TI recommends 4k7 external pull up resistors [2] and even with quite conservative estimation for pin capacity (1 uF should never happen) the required delay shall not exceed 5ms. [1] Link: https://www.ti.com/lit/pdf/sprz360 [2] Link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/866346/am3352-emu-1-0-questions Cc: stable@vger.kernel.org Signed-off-by: Alexander Sverdlin Link: https://lore.kernel.org/r/20250717152708.487891-1-alexander.sverdlin@siemens.com Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/am33xx-restart.c | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c index fcf3d557aa78..3cdf223addcc 100644 --- a/arch/arm/mach-omap2/am33xx-restart.c +++ b/arch/arm/mach-omap2/am33xx-restart.c @@ -2,12 +2,46 @@ /* * am33xx-restart.c - Code common to all AM33xx machines. */ +#include +#include #include #include #include "common.h" +#include "control.h" #include "prm.h" +/* + * Advisory 1.0.36 EMU0 and EMU1: Terminals Must be Pulled High Before + * ICEPick Samples + * + * If EMU0/EMU1 pins have been used as GPIO outputs and actively driving low + * level, the device might not reboot in normal mode. We are in a bad position + * to override GPIO state here, so just switch the pins into EMU input mode + * (that's what reset will do anyway) and wait a bit, because the state will be + * latched 190 ns after reset. + */ +static void am33xx_advisory_1_0_36(void) +{ + u32 emu0 = omap_ctrl_readl(AM335X_PIN_EMU0); + u32 emu1 = omap_ctrl_readl(AM335X_PIN_EMU1); + + /* If both pins are in EMU mode, nothing to do */ + if (!(emu0 & 7) && !(emu1 & 7)) + return; + + /* Switch GPIO3_7/GPIO3_8 into EMU0/EMU1 modes respectively */ + omap_ctrl_writel(emu0 & ~7, AM335X_PIN_EMU0); + omap_ctrl_writel(emu1 & ~7, AM335X_PIN_EMU1); + + /* + * Give pull-ups time to load the pin/PCB trace capacity. + * 5 ms shall be enough to load 1 uF (would be huge capacity for these + * pins) with TI-recommended 4k7 external pull-ups. + */ + mdelay(5); +} + /** * am33xx_restart - trigger a software restart of the SoC * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c @@ -18,6 +52,8 @@ */ void am33xx_restart(enum reboot_mode mode, const char *cmd) { + am33xx_advisory_1_0_36(); + /* TODO: Handle cmd if necessary */ prm_reboot_mode = mode; From 045e81d8d7e65baefbd4dea0503ca3330f93f3e6 Mon Sep 17 00:00:00 2001 From: Yang Xiuwei Date: Sun, 17 Aug 2025 16:34:49 +0800 Subject: [PATCH 06/14] ARM: OMAP2+: use IS_ERR_OR_NULL() helper Simplify error handling in OMAP powerdomain, voltage, and VP code by replacing open-coded '!ptr || IS_ERR(ptr)' checks with the combined IS_ERR_OR_NULL() helper. This improves readability and consistency across omap_set_pwrdm_state(), voltdm_get_voltage(), voltdm_scale(), voltdm_reset(), and related functions. No functional change intended. Signed-off-by: Yang Xiuwei Reviewed-by: Andreas Kemnade Link: https://lore.kernel.org/r/20250817083449.2249268-1-yangxiuwei2025@163.com Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/powerdomain.c | 2 +- arch/arm/mach-omap2/voltage.c | 12 ++++++------ arch/arm/mach-omap2/vp.c | 4 ++-- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index a4785302b7ae..0225b9889404 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -1111,7 +1111,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst) int curr_pwrst; int ret = 0; - if (!pwrdm || IS_ERR(pwrdm)) + if (IS_ERR_OR_NULL(pwrdm)) return -EINVAL; while (!(pwrdm->pwrsts & (1 << pwrst))) { diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c index 49e8bc69abdd..000c2bca5ef0 100644 --- a/arch/arm/mach-omap2/voltage.c +++ b/arch/arm/mach-omap2/voltage.c @@ -51,7 +51,7 @@ static LIST_HEAD(voltdm_list); */ unsigned long voltdm_get_voltage(struct voltagedomain *voltdm) { - if (!voltdm || IS_ERR(voltdm)) { + if (IS_ERR_OR_NULL(voltdm)) { pr_warn("%s: VDD specified does not exist!\n", __func__); return 0; } @@ -73,7 +73,7 @@ static int voltdm_scale(struct voltagedomain *voltdm, int ret, i; unsigned long volt = 0; - if (!voltdm || IS_ERR(voltdm)) { + if (IS_ERR_OR_NULL(voltdm)) { pr_warn("%s: VDD specified does not exist!\n", __func__); return -EINVAL; } @@ -124,7 +124,7 @@ void voltdm_reset(struct voltagedomain *voltdm) { unsigned long target_volt; - if (!voltdm || IS_ERR(voltdm)) { + if (IS_ERR_OR_NULL(voltdm)) { pr_warn("%s: VDD specified does not exist!\n", __func__); return; } @@ -154,7 +154,7 @@ void voltdm_reset(struct voltagedomain *voltdm) void omap_voltage_get_volttable(struct voltagedomain *voltdm, struct omap_volt_data **volt_data) { - if (!voltdm || IS_ERR(voltdm)) { + if (IS_ERR_OR_NULL(voltdm)) { pr_warn("%s: VDD specified does not exist!\n", __func__); return; } @@ -182,7 +182,7 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, { int i; - if (!voltdm || IS_ERR(voltdm)) { + if (IS_ERR_OR_NULL(voltdm)) { pr_warn("%s: VDD specified does not exist!\n", __func__); return ERR_PTR(-EINVAL); } @@ -216,7 +216,7 @@ struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm, int omap_voltage_register_pmic(struct voltagedomain *voltdm, struct omap_voltdm_pmic *pmic) { - if (!voltdm || IS_ERR(voltdm)) { + if (IS_ERR_OR_NULL(voltdm)) { pr_warn("%s: VDD specified does not exist!\n", __func__); return -EINVAL; } diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c index a709655b978c..03c481c4742c 100644 --- a/arch/arm/mach-omap2/vp.c +++ b/arch/arm/mach-omap2/vp.c @@ -199,7 +199,7 @@ void omap_vp_enable(struct voltagedomain *voltdm) struct omap_vp_instance *vp; u32 vpconfig, volt; - if (!voltdm || IS_ERR(voltdm)) { + if (IS_ERR_OR_NULL(voltdm)) { pr_warn("%s: VDD specified does not exist!\n", __func__); return; } @@ -244,7 +244,7 @@ void omap_vp_disable(struct voltagedomain *voltdm) u32 vpconfig; int timeout; - if (!voltdm || IS_ERR(voltdm)) { + if (IS_ERR_OR_NULL(voltdm)) { pr_warn("%s: VDD specified does not exist!\n", __func__); return; } From 74139a64e8cedb6d971c78d5d17384efeced1725 Mon Sep 17 00:00:00 2001 From: Miaoqian Lin Date: Tue, 2 Sep 2025 15:59:43 +0800 Subject: [PATCH 07/14] ARM: OMAP2+: pm33xx-core: ix device node reference leaks in amx3_idle_init Add missing of_node_put() calls to release device node references obtained via of_parse_phandle(). Fixes: 06ee7a950b6a ("ARM: OMAP2+: pm33xx-core: Add cpuidle_ops for am335x/am437x") Cc: stable@vger.kernel.org Signed-off-by: Miaoqian Lin Link: https://lore.kernel.org/r/20250902075943.2408832-1-linmq006@gmail.com Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/pm33xx-core.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c index c907478be196..4abb86dc98fd 100644 --- a/arch/arm/mach-omap2/pm33xx-core.c +++ b/arch/arm/mach-omap2/pm33xx-core.c @@ -388,12 +388,15 @@ static int __init amx3_idle_init(struct device_node *cpu_node, int cpu) if (!state_node) break; - if (!of_device_is_available(state_node)) + if (!of_device_is_available(state_node)) { + of_node_put(state_node); continue; + } if (i == CPUIDLE_STATE_MAX) { pr_warn("%s: cpuidle states reached max possible\n", __func__); + of_node_put(state_node); break; } @@ -403,6 +406,7 @@ static int __init amx3_idle_init(struct device_node *cpu_node, int cpu) states[state_count].wfi_flags |= WFI_FLAG_WAKE_M3 | WFI_FLAG_FLUSH_CACHE; + of_node_put(state_node); state_count++; } From 21e2e1abd4321a220a11c2963ff60214fd73c3e8 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 18 Jul 2025 01:52:01 +0000 Subject: [PATCH 08/14] arm: omap2: use string choices helper We can use string choices helper, let's use it. Signed-off-by: Kuninori Morimoto Reviewed-by: Andy Shevchenko Reviewed-by: Andreas Kemnade Link: https://lore.kernel.org/r/87ikjq5kqm.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/board-n8x0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index ff2a4a4d8220..969265d5d5c6 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -167,7 +167,7 @@ static int n8x0_mmc_set_power_menelaus(struct device *dev, int slot, #ifdef CONFIG_MMC_DEBUG dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1, - power_on ? "on" : "off", vdd); + str_on_off(power_on), vdd); #endif if (slot == 0) { if (!power_on) From 9685b2975972640a98f682462ea0741757c13294 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Wed, 13 Aug 2025 12:03:08 -0500 Subject: [PATCH 09/14] ARM: mach-hpe: Rework support and directory structure Having a platform need a mach-* directory should be seen as a negative, it means the platform needs special non-standard handling. ARM64 support does not allow mach-* directories at all. While we may not get to that given all the non-standard architectures we support, we should still try to get as close as we can and reduce the number of mach directories. The mach-hpe/ directory and files, provides just one "feature": having the kernel print the machine name if the DTB does not also contain a "model" string (which they always do). To reduce the number of mach-* directories let's do without that feature and remove this directory. Note, we drop the l2c_aux_mask = ~0 line, but this is safe as the fallback GENERIC_DT machine has that as the default. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20250813170308.290349-1-afd@ti.com Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 - arch/arm/Kconfig | 2 -- arch/arm/Kconfig.platforms | 25 +++++++++++++++++++++++++ arch/arm/Makefile | 1 - arch/arm/mach-hpe/Kconfig | 23 ----------------------- arch/arm/mach-hpe/Makefile | 1 - arch/arm/mach-hpe/gxp.c | 15 --------------- 7 files changed, 25 insertions(+), 43 deletions(-) delete mode 100644 arch/arm/mach-hpe/Kconfig delete mode 100644 arch/arm/mach-hpe/Makefile delete mode 100644 arch/arm/mach-hpe/gxp.c diff --git a/MAINTAINERS b/MAINTAINERS index 6dcfbd11efef..81ab6ac5df1d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2728,7 +2728,6 @@ F: Documentation/devicetree/bindings/spi/hpe,gxp-spifi.yaml F: Documentation/devicetree/bindings/timer/hpe,gxp-timer.yaml F: Documentation/hwmon/gxp-fan-ctrl.rst F: arch/arm/boot/dts/hpe/ -F: arch/arm/mach-hpe/ F: drivers/clocksource/timer-gxp.c F: drivers/hwmon/gxp-fan-ctrl.c F: drivers/i2c/busses/i2c-gxp.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b1f3df39ed40..f8faa15c6a15 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -393,8 +393,6 @@ source "arch/arm/mach-highbank/Kconfig" source "arch/arm/mach-hisi/Kconfig" -source "arch/arm/mach-hpe/Kconfig" - source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-ixp4xx/Kconfig" diff --git a/arch/arm/Kconfig.platforms b/arch/arm/Kconfig.platforms index 845ab08e20a4..5c19c1f2cff6 100644 --- a/arch/arm/Kconfig.platforms +++ b/arch/arm/Kconfig.platforms @@ -87,6 +87,31 @@ config MACH_ASM9260 help Support for Alphascale ASM9260 based platform. +menuconfig ARCH_HPE + bool "HPE SoC support" + depends on ARCH_MULTI_V7 + help + This enables support for HPE ARM based BMC chips. + +if ARCH_HPE + +config ARCH_HPE_GXP + bool "HPE GXP SoC" + depends on ARCH_MULTI_V7 + select ARM_VIC + select GENERIC_IRQ_CHIP + select CLKSRC_MMIO + help + HPE GXP is the name of the HPE Soc. This SoC is used to implement many + BMC features at HPE. It supports ARMv7 architecture based on the Cortex + A9 core. It is capable of using an AXI bus to which a memory controller + is attached. It has multiple SPI interfaces to connect boot flash and + BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It + has multiple i2c engines to drive connectivity with a host + infrastructure. + +endif + menuconfig ARCH_MOXART bool "MOXA ART SoC" depends on ARCH_MULTI_V4 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index e31e95ffd33f..b7de4b6b284c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -189,7 +189,6 @@ machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge machine-$(CONFIG_ARCH_GEMINI) += gemini machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_HISI) += hisi -machine-$(CONFIG_ARCH_HPE) += hpe machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx machine-$(CONFIG_ARCH_KEYSTONE) += keystone machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx diff --git a/arch/arm/mach-hpe/Kconfig b/arch/arm/mach-hpe/Kconfig deleted file mode 100644 index 3372bbf38d38..000000000000 --- a/arch/arm/mach-hpe/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -menuconfig ARCH_HPE - bool "HPE SoC support" - depends on ARCH_MULTI_V7 - help - This enables support for HPE ARM based BMC chips. -if ARCH_HPE - -config ARCH_HPE_GXP - bool "HPE GXP SoC" - depends on ARCH_MULTI_V7 - select ARM_VIC - select GENERIC_IRQ_CHIP - select CLKSRC_MMIO - help - HPE GXP is the name of the HPE Soc. This SoC is used to implement many - BMC features at HPE. It supports ARMv7 architecture based on the Cortex - A9 core. It is capable of using an AXI bus to which a memory controller - is attached. It has multiple SPI interfaces to connect boot flash and - BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It - has multiple i2c engines to drive connectivity with a host - infrastructure. - -endif diff --git a/arch/arm/mach-hpe/Makefile b/arch/arm/mach-hpe/Makefile deleted file mode 100644 index 8b0a91234df4..000000000000 --- a/arch/arm/mach-hpe/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-$(CONFIG_ARCH_HPE_GXP) += gxp.o diff --git a/arch/arm/mach-hpe/gxp.c b/arch/arm/mach-hpe/gxp.c deleted file mode 100644 index 581c8da517b8..000000000000 --- a/arch/arm/mach-hpe/gxp.c +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */ - -#include - -static const char * const gxp_board_dt_compat[] = { - "hpe,gxp", - NULL, -}; - -DT_MACHINE_START(GXP_DT, "HPE GXP") - .dt_compat = gxp_board_dt_compat, - .l2c_aux_val = 0, - .l2c_aux_mask = ~0, -MACHINE_END From e2c0510935c5485a2dacfd13af3958536b9d138b Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Thu, 10 Jul 2025 19:42:16 -0400 Subject: [PATCH 10/14] ARM: OMAP1: clock: convert from round_rate() to determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney Acked-by: Janusz Krzysztofik Link: https://lore.kernel.org/r/20250710-arm32-clk-round-rate-v1-1-a9146b77aca9@redhat.com Signed-off-by: Kevin Hilman --- arch/arm/mach-omap1/clock.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 83381e23fab9..afc6404f62d3 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -705,14 +705,21 @@ static unsigned long omap1_clk_recalc_rate(struct clk_hw *hw, unsigned long p_ra return clk->rate; } -static long omap1_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *p_rate) +static int omap1_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct omap1_clk *clk = to_omap1_clk(hw); - if (clk->round_rate != NULL) - return clk->round_rate(clk, rate, p_rate); + if (clk->round_rate != NULL) { + req->rate = clk->round_rate(clk, req->rate, + &req->best_parent_rate); - return omap1_clk_recalc_rate(hw, *p_rate); + return 0; + } + + req->rate = omap1_clk_recalc_rate(hw, req->best_parent_rate); + + return 0; } static int omap1_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate) @@ -771,7 +778,7 @@ const struct clk_ops omap1_clk_gate_ops = { const struct clk_ops omap1_clk_rate_ops = { .recalc_rate = omap1_clk_recalc_rate, - .round_rate = omap1_clk_round_rate, + .determine_rate = omap1_clk_determine_rate, .set_rate = omap1_clk_set_rate, .init = omap1_clk_init_op, }; @@ -784,7 +791,7 @@ const struct clk_ops omap1_clk_full_ops = { .disable_unused = omap1_clk_disable_unused, #endif .recalc_rate = omap1_clk_recalc_rate, - .round_rate = omap1_clk_round_rate, + .determine_rate = omap1_clk_determine_rate, .set_rate = omap1_clk_set_rate, .init = omap1_clk_init_op, }; From bb676996ed583464504123721195e98a708fbba9 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Thu, 10 Jul 2025 19:42:17 -0400 Subject: [PATCH 11/14] ARM: OMAP2+: clock: convert from round_rate() to determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. The change to virt_prcm_set_ops had to be made manually. Signed-off-by: Brian Masney Link: https://lore.kernel.org/r/20250710-arm32-clk-round-rate-v1-2-a9146b77aca9@redhat.com Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 011076a5952f..96c5cdc718c8 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -70,8 +70,8 @@ static unsigned long omap2_table_mpu_recalc(struct clk_hw *clk, * Some might argue L3-DDR, others ARM, others IVA. This code is simple and * just uses the ARM rates. */ -static long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int omap2_determine_rate_to_table(struct clk_hw *hw, + struct clk_rate_request *req) { const struct prcm_config *ptr; long highest_rate; @@ -87,10 +87,12 @@ static long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, highest_rate = ptr->mpu_speed; /* Can check only after xtal frequency check */ - if (ptr->mpu_speed <= rate) + if (ptr->mpu_speed <= req->rate) break; } - return highest_rate; + req->rate = highest_rate; + + return 0; } /* Sets basic clocks based on the specified rate */ @@ -215,7 +217,7 @@ static void omap2xxx_clkt_vps_late_init(void) static const struct clk_ops virt_prcm_set_ops = { .recalc_rate = &omap2_table_mpu_recalc, .set_rate = &omap2_select_table_rate, - .round_rate = &omap2_round_to_table_rate, + .determine_rate = &omap2_determine_rate_to_table, }; /** From 747436750bc0ef73be32391bd5d0d7dcd185da7f Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Wed, 10 Sep 2025 09:20:38 -0700 Subject: [PATCH 12/14] ARM: at91: pm: Remove 2.5V regulator Remove 2.5V regulator since enabling and disabling this regulator is no longer supported. Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/a6785a40648b315a07152bca261a42bbf0f356af.1757519351.git.Ryan.Wanner@microchip.com Signed-off-by: Nicolas Ferre --- arch/arm/mach-at91/pm_suspend.S | 29 ----------------------------- include/soc/at91/sama7-sfrbu.h | 7 ------- 2 files changed, 36 deletions(-) diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index aad53ec9e957..2e639f9ed648 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -87,29 +87,6 @@ tmp3 .req r6 .endm -/** - * Set state for 2.5V low power regulator - * @ena: 0 - disable regulator - * 1 - enable regulator - * - * Side effects: overwrites r7, r8, r9, r10 - */ - .macro at91_2_5V_reg_set_low_power ena -#ifdef CONFIG_SOC_SAMA7 - ldr r7, .sfrbu - mov r8, #\ena - ldr r9, [r7, #AT91_SFRBU_25LDOCR] - orr r9, r9, #AT91_SFRBU_25LDOCR_LP - cmp r8, #1 - beq lp_done_\ena - bic r9, r9, #AT91_SFRBU_25LDOCR_LP -lp_done_\ena: - ldr r10, =AT91_SFRBU_25LDOCR_LDOANAKEY - orr r9, r9, r10 - str r9, [r7, #AT91_SFRBU_25LDOCR] -#endif - .endm - .macro at91_backup_set_lpm reg #ifdef CONFIG_SOC_SAMA7 orr \reg, \reg, #0x200000 @@ -1023,9 +1000,6 @@ save_mck: at91_plla_disable - /* Enable low power mode for 2.5V regulator. */ - at91_2_5V_reg_set_low_power 1 - ldr tmp3, .pm_mode cmp tmp3, #AT91_PM_ULP1 beq ulp1_mode @@ -1038,9 +1012,6 @@ ulp1_mode: b ulp_exit ulp_exit: - /* Disable low power mode for 2.5V regulator. */ - at91_2_5V_reg_set_low_power 0 - ldr pmc, .pmc_base at91_plla_enable diff --git a/include/soc/at91/sama7-sfrbu.h b/include/soc/at91/sama7-sfrbu.h index 76b740810d34..8cee48d1ae2c 100644 --- a/include/soc/at91/sama7-sfrbu.h +++ b/include/soc/at91/sama7-sfrbu.h @@ -18,13 +18,6 @@ #define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */ #define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */ -#define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */ -#define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */ -#define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */ -#define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */ -#define AT91_SFRBU_PD_VALUE_MSK (0x3) -#define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */ - #define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */ #define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */ From a1b20e062245571c128ec521c4df56ad1bff9bd0 Mon Sep 17 00:00:00 2001 From: Mikko Rapeli Date: Mon, 15 Sep 2025 11:33:17 +0300 Subject: [PATCH 13/14] ARM: rockchip: remove REGULATOR conditional to PM PM is explicitly enabled in lines just below so REGULATOR can be too. Suggested-by: Geert Uytterhoeven Signed-off-by: Mikko Rapeli Link: https://lore.kernel.org/r/20250915083317.2885761-5-mikko.rapeli@linaro.org Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index b7855cc665e9..c90193dd3928 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -13,7 +13,7 @@ config ARCH_ROCKCHIP select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select DW_APB_TIMER_OF - select REGULATOR if PM + select REGULATOR select ROCKCHIP_TIMER select ARM_GLOBAL_TIMER select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK From 65d2419f931c08ead6722fbb9d4bd8cecb25a7e3 Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Wed, 1 Oct 2025 08:11:00 +0200 Subject: [PATCH 14/14] ARM: versatile: clock: convert from round_rate() to determine_rate() The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney Acked-by: Sudeep Holla Reviewed-by: Linus Walleij Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20251001061100.372737-1-linus.walleij@linaro.org Signed-off-by: Arnd Bergmann --- arch/arm/mach-versatile/spc.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-versatile/spc.c b/arch/arm/mach-versatile/spc.c index 790092734cf6..812db32448fc 100644 --- a/arch/arm/mach-versatile/spc.c +++ b/arch/arm/mach-versatile/spc.c @@ -497,12 +497,13 @@ static unsigned long spc_recalc_rate(struct clk_hw *hw, return freq * 1000; } -static long spc_round_rate(struct clk_hw *hw, unsigned long drate, - unsigned long *parent_rate) +static int spc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { struct clk_spc *spc = to_clk_spc(hw); - return ve_spc_round_performance(spc->cluster, drate); + req->rate = ve_spc_round_performance(spc->cluster, req->rate); + + return 0; } static int spc_set_rate(struct clk_hw *hw, unsigned long rate, @@ -515,7 +516,7 @@ static int spc_set_rate(struct clk_hw *hw, unsigned long rate, static struct clk_ops clk_spc_ops = { .recalc_rate = spc_recalc_rate, - .round_rate = spc_round_rate, + .determine_rate = spc_determine_rate, .set_rate = spc_set_rate, };