From 3e9f1b1f771c686fcd0a46ee6a9155e398ed7afe Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 3 Apr 2026 17:13:39 +0300 Subject: [PATCH] soc: renesas: r9a09g047-sys: Move common code to a helper Move common code from rzg3e_regmap_{readable,writeable}_reg() to a helper and use it to avoid code duplication. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260403141341.2851926-4-claudiu.beznea.uj@bp.reneasas.com Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/r9a09g047-sys.c | 42 +++++++++++------------------ 1 file changed, 16 insertions(+), 26 deletions(-) diff --git a/drivers/soc/renesas/r9a09g047-sys.c b/drivers/soc/renesas/r9a09g047-sys.c index ea3ca10fcc33..b617fb0bde7b 100644 --- a/drivers/soc/renesas/r9a09g047-sys.c +++ b/drivers/soc/renesas/r9a09g047-sys.c @@ -83,11 +83,9 @@ static const struct rz_sysc_soc_id_init_data rzg3e_sys_soc_id_init_data __initco .print_id = rzg3e_sys_print_id, }; -static bool rzg3e_regmap_readable_reg(struct device *dev, unsigned int reg) +static bool rzg3e_regmap_readable_writeable_reg(unsigned int reg) { switch (reg) { - case SYS_LSI_OTPTSU1TRMVAL0: - case SYS_LSI_OTPTSU1TRMVAL1: case SYS_SPI_STAADDCS0: case SYS_SPI_ENDADDCS0: case SYS_SPI_STAADDCS1: @@ -112,31 +110,23 @@ static bool rzg3e_regmap_readable_reg(struct device *dev, unsigned int reg) } } +static bool rzg3e_regmap_readable_reg(struct device *dev, unsigned int reg) +{ + if (rzg3e_regmap_readable_writeable_reg(reg)) + return true; + + switch (reg) { + case SYS_LSI_OTPTSU1TRMVAL0: + case SYS_LSI_OTPTSU1TRMVAL1: + return true; + default: + return false; + } +} + static bool rzg3e_regmap_writeable_reg(struct device *dev, unsigned int reg) { - switch (reg) { - case SYS_SPI_STAADDCS0: - case SYS_SPI_ENDADDCS0: - case SYS_SPI_STAADDCS1: - case SYS_SPI_ENDADDCS1: - case SYS_VSP_CLK: - case SYS_GBETH0_CFG: - case SYS_GBETH1_CFG: - case SYS_PCIE_INTX_CH0: - case SYS_PCIE_MSI1_CH0: - case SYS_PCIE_MSI2_CH0: - case SYS_PCIE_MSI3_CH0: - case SYS_PCIE_MSI4_CH0: - case SYS_PCIE_MSI5_CH0: - case SYS_PCIE_PME_CH0: - case SYS_PCIE_ACK_CH0: - case SYS_PCIE_MISC_CH0: - case SYS_PCIE_MODE_CH0: - case SYS_ADC_CFG: - return true; - default: - return false; - } + return rzg3e_regmap_readable_writeable_reg(reg); } const struct rz_sysc_init_data rzg3e_sys_init_data __initconst = {