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[ARM] 4457/2: davinci: GPIO support
Support GPIO driver for TI DaVinci SoC Signed-off-by: Vladimir Barinov <vbarino@ru.mvista.com> Acked-by: David Brownell <david-b@pacbell.net> Acked-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Vladimir Barinov
committed by
Russell King
Russell King
parent
3e062b07ad
commit
3d9edf09d4
156
include/asm-arm/arch-davinci/gpio.h
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156
include/asm-arm/arch-davinci/gpio.h
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/*
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* TI DaVinci GPIO Support
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*
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* Copyright (c) 2006 David Brownell
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* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __DAVINCI_GPIO_H
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#define __DAVINCI_GPIO_H
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/*
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* basic gpio routines
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*
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* board-specific init should be done by arch/.../.../board-XXX.c (maybe
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* initializing banks together) rather than boot loaders; kexec() won't
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* go through boot loaders.
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*
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* the gpio clock will be turned on when gpios are used, and you may also
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* need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are
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* used as gpios, not with other peripherals.
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*
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* GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, and maybe
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* for later updates, code should write GPIO(N) or:
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* - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53)
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* - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70)
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*
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* For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc
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* for now, that's != GPIO(N)
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*/
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#define GPIO(X) (X) /* 0 <= X <= 70 */
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#define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */
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#define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */
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struct gpio_controller {
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u32 dir;
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u32 out_data;
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u32 set_data;
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u32 clr_data;
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u32 in_data;
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u32 set_rising;
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u32 clr_rising;
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u32 set_falling;
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u32 clr_falling;
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u32 intstat;
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};
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/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
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* with constant parameters; or in outlined code they execute at runtime.
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*
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* You'd access the controller directly when reading or writing more than
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* one gpio value at a time, and to support wired logic where the value
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* being driven by the cpu need not match the value read back.
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*
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* These are NOT part of the cross-platform GPIO interface
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*/
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static inline struct gpio_controller *__iomem
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__gpio_to_controller(unsigned gpio)
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{
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void *__iomem ptr;
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if (gpio < 32)
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ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
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else if (gpio < 64)
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ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
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else if (gpio < DAVINCI_N_GPIO)
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ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
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else
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ptr = NULL;
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return ptr;
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}
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static inline u32 __gpio_mask(unsigned gpio)
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{
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return 1 << (gpio % 32);
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}
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/* The get/set/clear functions will inline when called with constant
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* parameters, for low-overhead bitbanging. Illegal constant parameters
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* cause link-time errors.
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*
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* Otherwise, calls with variable parameters use outlined functions.
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*/
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extern int __error_inval_gpio(void);
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extern void __gpio_set(unsigned gpio, int value);
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extern int __gpio_get(unsigned gpio);
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static inline void gpio_set_value(unsigned gpio, int value)
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{
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if (__builtin_constant_p(value)) {
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struct gpio_controller *__iomem g;
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u32 mask;
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if (gpio >= DAVINCI_N_GPIO)
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__error_inval_gpio();
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g = __gpio_to_controller(gpio);
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mask = __gpio_mask(gpio);
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if (value)
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__raw_writel(mask, &g->set_data);
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else
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__raw_writel(mask, &g->clr_data);
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return;
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}
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__gpio_set(gpio, value);
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}
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/* Returns zero or nonzero; works for gpios configured as inputs OR
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* as outputs.
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*
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* NOTE: changes in reported values are synchronized to the GPIO clock.
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* This is most easily seen after calling gpio_set_value() and then immediatly
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* gpio_get_value(), where the gpio_get_value() would return the old value
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* until the GPIO clock ticks and the new value gets latched.
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*/
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static inline int gpio_get_value(unsigned gpio)
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{
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struct gpio_controller *__iomem g;
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if (!__builtin_constant_p(gpio))
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return __gpio_get(gpio);
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if (gpio >= DAVINCI_N_GPIO)
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return __error_inval_gpio();
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g = __gpio_to_controller(gpio);
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return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data));
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}
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/* powerup default direction is IN */
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extern int gpio_direction_input(unsigned gpio);
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extern int gpio_direction_output(unsigned gpio, int value);
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#include <asm-generic/gpio.h> /* cansleep wrappers */
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extern int gpio_request(unsigned gpio, const char *tag);
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extern void gpio_free(unsigned gpio);
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static inline int gpio_to_irq(unsigned gpio)
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{
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return DAVINCI_N_AINTC_IRQ + gpio;
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}
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static inline int irq_to_gpio(unsigned irq)
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{
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return irq - DAVINCI_N_AINTC_IRQ;
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}
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#endif /* __DAVINCI_GPIO_H */
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@@ -11,4 +11,42 @@
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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/*
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* Base register addresses
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*/
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#define DAVINCI_DMA_3PCC_BASE (0x01C00000)
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#define DAVINCI_DMA_3PTC0_BASE (0x01C10000)
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#define DAVINCI_DMA_3PTC1_BASE (0x01C10400)
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#define DAVINCI_I2C_BASE (0x01C21000)
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#define DAVINCI_PWM0_BASE (0x01C22000)
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#define DAVINCI_PWM1_BASE (0x01C22400)
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#define DAVINCI_PWM2_BASE (0x01C22800)
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#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000)
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#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800)
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#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00)
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#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000)
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#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000)
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#define DAVINCI_IEEE1394_BASE (0x01C60000)
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#define DAVINCI_USB_OTG_BASE (0x01C64000)
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#define DAVINCI_CFC_ATA_BASE (0x01C66000)
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#define DAVINCI_SPI_BASE (0x01C66800)
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#define DAVINCI_GPIO_BASE (0x01C67000)
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#define DAVINCI_UHPI_BASE (0x01C67800)
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#define DAVINCI_VPSS_REGS_BASE (0x01C70000)
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#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000)
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#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000)
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#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000)
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#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000)
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#define DAVINCI_IMCOP_BASE (0x01CC0000)
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000)
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#define DAVINCI_VLYNQ_BASE (0x01E01000)
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#define DAVINCI_MCBSP_BASE (0x01E02000)
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#define DAVINCI_MMC_SD_BASE (0x01E10000)
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#define DAVINCI_MS_BASE (0x01E20000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
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#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000)
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#endif /* __ASM_ARCH_HARDWARE_H */
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