From 73bf90d4d4e388a59f656e14fbc240de8fe8f728 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 23 Feb 2017 18:30:43 +0100 Subject: [PATCH 01/16] arm64: tegra: Add PMC controller on Tegra186 The NVIDIA Tegra186 SoC has a Power Management Controller that performs various tasks related to system power, boot as well as suspend/resume. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 62fa85ae0271..d6955bb46ae0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -307,6 +307,15 @@ gpio_aon: gpio@c2f0000 { #interrupt-cells = <2>; }; + pmc@c360000 { + compatible = "nvidia,tegra186-pmc"; + reg = <0 0x0c360000 0 0x10000>, + <0 0x0c370000 0 0x10000>, + <0 0x0c380000 0 0x10000>, + <0 0x0c390000 0 0x10000>; + reg-names = "pmc", "wake", "aotag", "scratch"; + }; + sysram@30000000 { compatible = "nvidia,tegra186-sysram", "mmio-sram"; reg = <0x0 0x30000000 0x0 0x50000>; From 0caafbde07ec36bc34b4746017a6c0ce4d22ab0b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 23 Feb 2017 18:30:44 +0100 Subject: [PATCH 02/16] arm64: tegra: Add ethernet support for Tegra186 The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC ethernet QOS IP block, which supports 10, 100 and 1000 Mbps data transfer rates. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 31 ++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index d6955bb46ae0..3ea5e6369bc3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -27,6 +27,37 @@ gpio: gpio@2200000 { gpio-controller; }; + ethernet@2490000 { + compatible = "nvidia,tegra186-eqos", + "snps,dwc-qos-ethernet-4.10"; + reg = <0x0 0x02490000 0x0 0x10000>; + interrupts = , /* common */ + , /* power */ + , /* rx0 */ + , /* tx0 */ + , /* rx1 */ + , /* tx1 */ + , /* rx2 */ + , /* tx2 */ + , /* rx3 */ + ; /* tx3 */ + clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, + <&bpmp TEGRA186_CLK_EQOS_AXI>, + <&bpmp TEGRA186_CLK_EQOS_RX>, + <&bpmp TEGRA186_CLK_EQOS_TX>, + <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; + clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; + resets = <&bpmp TEGRA186_RESET_EQOS>; + reset-names = "eqos"; + status = "disabled"; + + snps,write-requests = <1>; + snps,read-requests = <3>; + snps,burst-map = <0x7>; + snps,txpbl = <32>; + snps,rxpbl = <8>; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; reg = <0x0 0x03100000 0x0 0x40>; From 93dbb44c5c2678aaed08c096968ffd4fb171e154 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 23 Feb 2017 18:30:45 +0100 Subject: [PATCH 03/16] arm64: tegra: Invert the PMC interrupt on P3310 The PMC interrupt is inverted on P3310, so mark it as such in the device tree to avoid a flood of interrupts when the PMIC is enabled. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 1abe2eceb3d1..3653d0dd5f4f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -26,6 +26,10 @@ hsp@3c00000 { status = "okay"; }; + pmc@c360000 { + nvidia,invert-interrupt; + }; + cpus { cpu@0 { enable-method = "psci"; From a4c7aab2eaaeb479ae18a8299c69e8d28b50591b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 23 Feb 2017 18:30:46 +0100 Subject: [PATCH 04/16] arm64: tegra: Enable I2C controllers on P3310 The P3310 processor modules use seven I2C controllers for various peripherals. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 40 ++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 3653d0dd5f4f..762f4756346c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -6,6 +6,14 @@ / { aliases { serial0 = &uarta; + i2c0 = "/bpmp/i2c"; + i2c1 = "/i2c@3160000"; + i2c2 = "/i2c@c240000"; + i2c3 = "/i2c@3180000"; + i2c4 = "/i2c@3190000"; + i2c5 = "/i2c@31c0000"; + i2c6 = "/i2c@c250000"; + i2c7 = "/i2c@31e0000"; }; chosen { @@ -22,10 +30,38 @@ serial@3100000 { status = "okay"; }; + i2c@3160000 { + status = "okay"; + }; + + i2c@3180000 { + status = "okay"; + }; + + i2c@3190000 { + status = "okay"; + }; + + i2c@31c0000 { + status = "okay"; + }; + + i2c@31e0000 { + status = "okay"; + }; + hsp@3c00000 { status = "okay"; }; + i2c@c240000 { + status = "okay"; + }; + + i2c@c250000 { + status = "okay"; + }; + pmc@c360000 { nvidia,invert-interrupt; }; @@ -57,7 +93,9 @@ cpu@5 { }; bpmp { - status = "okay"; + i2c { + status = "okay"; + }; }; psci { From 24975b8c218ad7206f98062c97c9380c2163f6e2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 23 Feb 2017 18:30:47 +0100 Subject: [PATCH 05/16] arm64: tegra: Enable ethernet on P3310 The P3310 processor module provides networking via the ethernet controller found on NVIDIA Tegra186 SoCs. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 762f4756346c..ffbb4be5122e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -26,6 +26,26 @@ memory { reg = <0x0 0x80000000 0x2 0x00000000>; }; + ethernet@2490000 { + status = "okay"; + + phy-reset-gpios = <&gpio TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>; + phy-handle = <&phy>; + phy-mode = "rgmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + interrupt-parent = <&gpio>; + interrupts = ; + }; + }; + }; + serial@3100000 { status = "okay"; }; From 02df3f03a8db3e64348b8fce3d8ce2449ada3fa6 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 23 Feb 2017 18:30:48 +0100 Subject: [PATCH 06/16] arm64: tegra: Add initial power tree for P3310 Enable the Maxim MAX77620 PMIC found on P3310 and add some fixed regulators to model the power tree. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 220 ++++++++++++++++++ 1 file changed, 220 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index ffbb4be5122e..9eba6daac1a4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -1,5 +1,7 @@ #include "tegra186.dtsi" +#include + / { model = "NVIDIA Tegra186 P3310 Processor Module"; compatible = "nvidia,p3310", "nvidia,tegra186"; @@ -115,6 +117,189 @@ cpu@5 { bpmp { i2c { status = "okay"; + + pmic: pmic@3c { + compatible = "maxim,max77620"; + reg = <0x3c>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&max77620_default>; + + max77620_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + gpio1 { + pins = "gpio1"; + function = "fps-out"; + maxim,active-fps-source = ; + }; + + gpio2 { + pins = "gpio2"; + function = "fps-out"; + maxim,active-fps-source = ; + }; + + gpio3 { + pins = "gpio3"; + function = "fps-out"; + maxim,active-fps-source = ; + }; + + gpio4 { + pins = "gpio4"; + function = "32k-out1"; + drive-push-pull = <1>; + }; + + gpio5 { + pins = "gpio5"; + function = "gpio"; + drive-push-pull = <0>; + }; + + gpio6 { + pins = "gpio6"; + function = "gpio"; + drive-push-pull = <1>; + }; + + gpio7 { + pins = "gpio7"; + function = "gpio"; + drive-push-pull = <0>; + }; + }; + + fps { + fps0 { + maxim,fps-event-source = ; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps1 { + maxim,fps-event-source = ; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps2 { + maxim,fps-event-source = ; + maxim,shutdown-fps-time-period-us = <640>; + }; + }; + + regulators { + in-sd0-supply = <&vdd_5v0_sys>; + in-sd1-supply = <&vdd_5v0_sys>; + in-sd2-supply = <&vdd_5v0_sys>; + in-sd3-supply = <&vdd_5v0_sys>; + + in-ldo0-1-supply = <&vdd_5v0_sys>; + in-ldo2-supply = <&vdd_5v0_sys>; + in-ldo3-5-supply = <&vdd_5v0_sys>; + in-ldo4-6-supply = <&vdd_1v8>; + in-ldo7-8-supply = <&avdd_dsi_csi>; + + sd0 { + regulator-name = "VDD_DDR_1V1_PMIC"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_dsi_csi: sd1 { + regulator-name = "AVDD_DSI_CSI_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + /* XXX */ + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8: sd2 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* XXX */ + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3_sys: sd3 { + regulator-name = "VDD_3V3_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* XXX */ + regulator-always-on; + regulator-boot-on; + }; + + ldo0 { + regulator-name = "VDD_1V8_AP_PLL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* XXX */ + regulator-always-on; + regulator-boot-on; + }; + + ldo2 { + regulator-name = "VDDIO_3V3_AOHV"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* XXX */ + regulator-always-on; + regulator-boot-on; + }; + + vddio_sdmmc1: ldo3 { + regulator-name = "VDDIO_SDMMC1_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo4 { + regulator-name = "VDD_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vddio_sdmmc3: ldo5 { + regulator-name = "VDDIO_SDMMC3_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + avdd_1v05: ldo7 { + regulator-name = "VDD_HDMI_1V05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + /* XXX */ + regulator-always-on; + regulator-boot-on; + }; + + vdd_pex: ldo8 { + regulator-name = "VDD_PEX_1V05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + /* XXX */ + regulator-always-on; + regulator-boot-on; + }; + }; + }; }; }; @@ -123,4 +308,39 @@ psci { status = "okay"; method = "smc"; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_sys: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + + regulator-name = "VDD_5V0_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_ap: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + + regulator-name = "VDD_1V8_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + /* XXX */ + regulator-always-on; + regulator-boot-on; + + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vdd_1v8>; + }; + }; }; From 80fdf7b426f1c37571b68a4494fb72a7a73a31fd Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 23 Feb 2017 18:30:49 +0100 Subject: [PATCH 07/16] arm64: tegra: Enable SDHCI controllers on P3110 The P3110 processor module wires one of the SDHCI controllers to an on- board eMMC and exposes another set of SD/MMC signals on the connector to support an external SD/MMC card. A third controller is connected to the SDIO pins of an M.2 KEY E connector. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 9eba6daac1a4..5a49093d5ce7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -7,6 +7,8 @@ / { compatible = "nvidia,p3310", "nvidia,tegra186"; aliases { + sdhci0 = "/sdhci@3460000"; + sdhci1 = "/sdhci@3400000"; serial0 = &uarta; i2c0 = "/bpmp/i2c"; i2c1 = "/i2c@3160000"; @@ -72,6 +74,29 @@ i2c@31e0000 { status = "okay"; }; + /* SDMMC1 (SD/MMC) */ + sdhci@3400000 { + cd-gpios = <&gpio TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_LOW>; + + vqmmc-supply = <&vddio_sdmmc1>; + }; + + /* SDMMC3 (SDIO) */ + sdhci@3440000 { + status = "okay"; + }; + + /* SDMMC4 (eMMC) */ + sdhci@3460000 { + status = "okay"; + bus-width = <8>; + non-removable; + + vqmmc-supply = <&vdd_1v8_ap>; + vmmc-supply = <&vdd_3v3_sys>; + }; + hsp@3c00000 { status = "okay"; }; From b0ddea853919e6165d58b68dc086ad575112965b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 8 Mar 2017 14:31:45 +0100 Subject: [PATCH 08/16] arm64: tegra: Enable SD/MMC slot on P2771 The P3310 processor module makes provisions for exposing the SDMMC1 controller via a standard SD/MMC slot, which the P2771 supports. Hook up the power supply provided on the P2771 carrier board and enable the device tree node. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra186-p2771-0000.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 0d3c0996d832..b80c1c3483db 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -5,4 +5,27 @@ / { model = "NVIDIA Tegra186 P2771-0000 Development Board"; compatible = "nvidia,p2771-0000", "nvidia,tegra186"; + + /* SDMMC1 (SD/MMC) */ + sdhci@3400000 { + status = "okay"; + + vmmc-supply = <&vdd_sd>; + }; + + regulators { + vdd_sd: regulator@100 { + compatible = "regulator-fixed"; + reg = <100>; + + regulator-name = "SD_CARD_SW_PWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vdd_3v3_sys>; + }; + }; }; From b64994d18fcdb7ad5a1eedf291a0e95a44344e17 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 23 Feb 2017 18:30:50 +0100 Subject: [PATCH 09/16] arm64: tegra: Enable current monitors on P3310 The P3310 processor module contains two current monitors that can be used to determine the current flow across various parts of the board design. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 5a49093d5ce7..cf84d7046ad5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -56,6 +56,16 @@ serial@3100000 { i2c@3160000 { status = "okay"; + + power-monitor@40 { + compatible = "ti,ina3221"; + reg = <0x40>; + }; + + power-monitor@41 { + compatible = "ti,ina3221"; + reg = <0x41>; + }; }; i2c@3180000 { From 59686a92782c38e0f8bd603fcfef3c6b5f307c97 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 23 Feb 2017 18:30:51 +0100 Subject: [PATCH 10/16] arm64: tegra: Add GPIO keys on P2771 The P2771 has three keys (power, volume up and volume down) that are connected to pins on the AON GPIO controller. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra186-p2771-0000.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index b80c1c3483db..9a1d02228652 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -1,5 +1,7 @@ /dts-v1/; +#include + #include "tegra186-p3310.dtsi" / { @@ -13,6 +15,38 @@ sdhci@3400000 { vmmc-supply = <&vdd_sd>; }; + gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 0) + GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + + volume-up { + label = "Volume Up"; + gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 1) + GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio_aon TEGRA_AON_GPIO(FF, 2) + GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <10>; + }; + }; + regulators { vdd_sd: regulator@100 { compatible = "regulator-fixed"; From b693b3d709c855a4f4a4dc5d2ac75ca794e0fa5e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 23 Feb 2017 18:30:52 +0100 Subject: [PATCH 11/16] arm64: tegra: Add power monitors on P2771 The P2771 development board comes with two power monitors that can be used to determine power consumption in different parts of the board. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 9a1d02228652..78442ea81260 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -8,6 +8,18 @@ / { model = "NVIDIA Tegra186 P2771-0000 Development Board"; compatible = "nvidia,p2771-0000", "nvidia,tegra186"; + i2c@3160000 { + power-monitor@42 { + compatible = "ti,ina3221"; + reg = <0x42>; + }; + + power-monitor@43 { + compatible = "ti,ina3221"; + reg = <0x43>; + }; + }; + /* SDMMC1 (SD/MMC) */ sdhci@3400000 { status = "okay"; From b27d5250062ef7438f86d8ab6d0549dc912f4267 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 23 Feb 2017 18:30:53 +0100 Subject: [PATCH 12/16] arm64: tegra: Add GPIO expanders on P2771 The P2771 development board expands the number of GPIOs via two I2C chips. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra186-p2771-0000.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 78442ea81260..8daadadec63a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -18,6 +18,28 @@ power-monitor@43 { compatible = "ti,ina3221"; reg = <0x43>; }; + + exp1: gpio@74 { + compatible = "ti,tca9539"; + reg = <0x74>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #gpio-cells = <2>; + gpio-controller; + }; + + exp2: gpio@77 { + compatible = "ti,tca9539"; + reg = <0x77>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #gpio-cells = <2>; + gpio-controller; + }; }; /* SDMMC1 (SD/MMC) */ From 24963d1becbb26e4649b752e0011dd90c378f100 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 14 Dec 2016 13:16:16 +0200 Subject: [PATCH 13/16] arm64: tegra: Enable VIC on Tegra210 Enable the VIC (Video Image Compositor) host1x unit on Tegra210 systems. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 2f832df29da8..217e5a14745c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -185,7 +185,14 @@ dsi@54300000 { vic@54340000 { compatible = "nvidia,tegra210-vic"; reg = <0x0 0x54340000 0x0 0x00040000>; - status = "disabled"; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_VIC03>; + clock-names = "vic"; + resets = <&tegra_car 178>; + reset-names = "vic"; + + iommus = <&mc TEGRA_SWGROUP_VIC>; + power-domains = <&pd_vic>; }; nvjpg@54380000 { @@ -755,6 +762,14 @@ pd_xusbhost: xusbc { resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; #power-domain-cells = <0>; }; + + pd_vic: vic { + clocks = <&tegra_car TEGRA210_CLK_VIC03>; + clock-names = "vic"; + resets = <&tegra_car 178>; + reset-names = "vic"; + #power-domain-cells = <0>; + }; }; }; From 116503a62a5ab6d79397500ab37239ce088f03e3 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 14 Dec 2016 13:16:17 +0200 Subject: [PATCH 14/16] arm64: tegra: Enable IOMMU for host1x on Tegra210 The host1x driver now supports operation behind an IOMMU, so add its IOMMU domain to the device tree. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 217e5a14745c..8f26c4d4409a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -89,6 +89,8 @@ host1x@50000000 { ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; + iommus = <&mc TEGRA_SWGROUP_HC>; + dpaux1: dpaux@54040000 { compatible = "nvidia,tegra210-dpaux"; reg = <0x0 0x54040000 0x0 0x00040000>; From dfd7a3845a577e2350305609838bf31c08e4dec1 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Thu, 30 Mar 2017 18:28:28 +0900 Subject: [PATCH 15/16] arm64: tegra: Add GPU node for Tegra186 Add the DT node for the GP10B GPU on Tegra186. Signed-off-by: Alexandre Courbot Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 3ea5e6369bc3..5e62e68ac053 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -2,6 +2,7 @@ #include #include #include +#include #include / { @@ -347,6 +348,24 @@ pmc@c360000 { reg-names = "pmc", "wake", "aotag", "scratch"; }; + gpu@17000000 { + compatible = "nvidia,gp10b"; + reg = <0x0 0x17000000 0x0 0x1000000>, + <0x0 0x18000000 0x0 0x1000000>; + interrupts = ; + interrupt-names = "stall", "nonstall"; + + clocks = <&bpmp TEGRA186_CLK_GPCCLK>, + <&bpmp TEGRA186_CLK_GPU>; + clock-names = "gpu", "pwr"; + resets = <&bpmp TEGRA186_RESET_GPU>; + reset-names = "gpu"; + status = "disabled"; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; + }; + sysram@30000000 { compatible = "nvidia,tegra186-sysram", "mmio-sram"; reg = <0x0 0x30000000 0x0 0x50000>; From 18236a14883b718ce973e4c090db6ecb49b38287 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 28 Mar 2017 13:42:57 +0100 Subject: [PATCH 16/16] arm64: tegra: Update the Tegra132 flowctrl compatible string Update the Tegra132 flowctrl compatible string to include "nvidia,tegra132-flowctrl" so it is aligned with the flowctrl binding documentation. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 3f3a46a4bd01..2b17936ac5be 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -224,7 +224,7 @@ tegra_car: clock@60006000 { }; flow-controller@60007000 { - compatible = "nvidia,tegra124-flowctrl"; + compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; reg = <0x0 0x60007000 0x0 0x1000>; };