From e931a6f79620c2cc0e9dde215e35f016a3be33f4 Mon Sep 17 00:00:00 2001 From: David Jander Date: Mon, 21 Feb 2022 10:53:05 +0100 Subject: [PATCH 01/77] ARM: dts: imx6qdl-vicut1/vicutgo: Set default backlight brightness to maximum Recover default behavior of the device and set maximal brightness Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 2 +- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 227c952543d4..e6134efbfabd 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -28,7 +28,7 @@ backlight: backlight { pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 16 64 255>; num-interpolated-steps = <16>; - default-brightness-level = <1>; + default-brightness-level = <48>; power-supply = <®_3v3>; enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index 1ac7e13249d2..c1d06bc28c67 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -23,7 +23,7 @@ backlight: backlight { pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 16 64 255>; num-interpolated-steps = <16>; - default-brightness-level = <1>; + default-brightness-level = <48>; power-supply = <®_3v3>; enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; From 156a722b39315e95dd018dbc614e2becf4782237 Mon Sep 17 00:00:00 2001 From: David Jander Date: Mon, 21 Feb 2022 10:53:06 +0100 Subject: [PATCH 02/77] ARM: dts: imx6qdl-vicut1/vicutgo: Rename backlight to backlight_lcd We have two backlight sources on this boards. Use more specific name for the LCD backlight to see the difference. Signed-off-by: David Jander Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 4 ++-- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index e6134efbfabd..833340c30537 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -21,7 +21,7 @@ chosen { stdout-path = &uart4; }; - backlight: backlight { + backlight_lcd: backlight { compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight>; @@ -100,7 +100,7 @@ led-2 { panel { compatible = "kyo,tcg121xglp"; - backlight = <&backlight>; + backlight = <&backlight_lcd>; power-supply = <®_3v3>; port { diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index c1d06bc28c67..a1fbbc9c26b6 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -16,7 +16,7 @@ chosen { stdout-path = &uart4; }; - backlight: backlight { + backlight_lcd: backlight { compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight>; @@ -102,7 +102,7 @@ led-2 { panel { compatible = "kyo,tcg121xglp"; - backlight = <&backlight>; + backlight = <&backlight_lcd>; power-supply = <®_3v3>; port { From 98efa526a0c436efea4cdc834ab632f66f13ac0b Mon Sep 17 00:00:00 2001 From: David Jander Date: Mon, 21 Feb 2022 10:53:07 +0100 Subject: [PATCH 03/77] ARM: dts: imx6qdl-vicut1/vicutgo: Add backlight_led node backlight_led is the dimmable backlight for the rubber border on the case. It is also used to highlight the power- and some other buttons. MX6QDL_PAD_SD4_DAT1__PWM3_OUT is also assigned as output for pwm3. Since we need pwm3 for the backlight, we're forced to disable user space hardware revision detection. The bootloader will have to supply this information (i.e. through device tree). Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 24 +++++++++---------- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 33 +++++++++++++++++---------- 2 files changed, 32 insertions(+), 25 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 833340c30537..d542ddad4e32 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -33,6 +33,15 @@ backlight_lcd: backlight { enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; + backlight_led: backlight_led { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000 0>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <48>; + power-supply = <®_3v3>; + }; + connector { compatible = "composite-video-connector"; label = "Composite0"; @@ -392,8 +401,8 @@ &gpio1 { &gpio2 { gpio-line-names = "", "", "", "", "", "", "", "", - "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", - "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", + "", "LED_PWM", "", "", "", + "", "", "", "", "", "", "", "", "", "ISB_IN1", "ON_SWITCH", "POWER_LED", "", "", "", "", "", "", ""; }; @@ -778,17 +787,6 @@ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 /* ITU656_nPDN */ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 - /* HW revision detect */ - /* REV_ID0 */ - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 - /* REV_ID1 is shared with PWM3 */ - /* REV_ID2 */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - /* REV_ID3 */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - /* REV_ID4 */ - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - /* New in HW revision 1 */ /* ON1_FB */ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index a1fbbc9c26b6..2f6b263eea66 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -28,6 +28,15 @@ backlight_lcd: backlight { enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; }; + backlight_led: backlight_led { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000 0>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <48>; + power-supply = <®_3v3>; + }; + connector { compatible = "composite-video-connector"; label = "Composite0"; @@ -448,6 +457,12 @@ &pwm1 { status = "okay"; }; +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + &ssi1 { #sound-dai-cells = <0>; fsl,mode = "ac97-slave"; @@ -669,18 +684,6 @@ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 /* ITU656_nPDN */ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 - /* HW revision detect */ - /* REV_ID0 */ - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 - /* REV_ID1 */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - /* REV_ID2 */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - /* REV_ID3 */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - /* REV_ID4 */ - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - /* New in HW revision 1 */ /* ON1_FB */ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 @@ -738,6 +741,12 @@ MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 >; }; + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 + >; + }; + /* YaCO AUX Uart */ pinctrl_uart1: uart1grp { fsl,pins = < From cb15ebbc10b5d35af76f34f18b1592abc39c3f5b Mon Sep 17 00:00:00 2001 From: David Jander Date: Mon, 21 Feb 2022 10:53:08 +0100 Subject: [PATCH 04/77] ARM: dts: imx6qdl-vicut1: update gpio-line-names for some GPIOs countedX lines have different board names (YACO_x). And REV_ and BOARD_ pins have multiple functions. So, use names exposed to the OS. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index 2f6b263eea66..ec39008c0950 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -277,9 +277,9 @@ &gpio1 { &gpio2 { gpio-line-names = - "count0", "count1", "count2", "", "", "", "", "", - "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4", - "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", + "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", + "", "LED_PWM", "", "", "", + "", "", "", "", "", "", "", "", "", "", "ON_SWITCH", "POWER_LED", "", "ECSPI2_SS0", "", "", "", "", ""; }; @@ -298,8 +298,10 @@ &gpio4 { "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX", - "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "", "", "", "", "", "", - "", "", "", "", "BL_EN", "BL_PWM", "", ""; + "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "", "", "", "ON1_CTRL", + "ON2_CTRL", "HITCH_IN_OUT", + "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", + "ISB_LED"; }; &gpio5 { From 05ed0bc09a5377825b37240c0212a894aa4dad49 Mon Sep 17 00:00:00 2001 From: Robin van der Gracht Date: Mon, 21 Feb 2022 10:53:10 +0100 Subject: [PATCH 05/77] ARM: dts: imx6dl-victgo: Add interrupt-counter nodes Interrupt counter is mainlined, now we can add missing counter nodes. Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 41 ++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index d542ddad4e32..3d6dc1b2c5e9 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -54,6 +54,27 @@ comp0_out: endpoint { }; }; + counter-0 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter0>; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + }; + + counter-1 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter1>; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + counter-2 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter2>; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -400,7 +421,7 @@ &gpio1 { &gpio2 { gpio-line-names = - "", "", "", "", "", "", "", "", + "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", "", "LED_PWM", "", "", "", "", "", "", "", "", "", "", "", "", "ISB_IN1", "ON_SWITCH", @@ -708,6 +729,24 @@ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 >; }; + pinctrl_counter0: counter0grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 + >; + }; + + pinctrl_counter1: counter1grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 + >; + }; + + pinctrl_counter2: counter2grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 From e310ba3c0fd5d9d017831501e81dad7e5a9aa2d7 Mon Sep 17 00:00:00 2001 From: Robin van der Gracht Date: Mon, 21 Feb 2022 10:53:11 +0100 Subject: [PATCH 06/77] ARM: dts: imx6dl-victgo: The TGO uses a lg,lb070wv8 compatible 7" display This series of devices is using lg,lb070wv8 instead of kyo,tcg121xglp. Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 3d6dc1b2c5e9..7a29283da245 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -129,7 +129,7 @@ led-2 { }; panel { - compatible = "kyo,tcg121xglp"; + compatible = "lg,lb070wv8"; backlight = <&backlight_lcd>; power-supply = <®_3v3>; From 7bb9b9e34b8742afc0cd8547103ef0106012947b Mon Sep 17 00:00:00 2001 From: David Jander Date: Mon, 21 Feb 2022 10:53:12 +0100 Subject: [PATCH 07/77] ARM: dts: imx6qdl-victgo: add CAN termination support The gpio1 0 pin is controlling CAN termination, not USB H1 VBUS. So, remove wrong regulator and assign this gpio to new DT CAN termination property. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 7a29283da245..7dd7fb165432 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -160,15 +160,6 @@ reg_3v3: regulator-3v3 { regulator-max-microvolt = <3300000>; }; - reg_h1_vbus: regulator-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "h1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - reg_otg_vbus: regulator-otg-vbus { compatible = "regulator-fixed"; regulator-name = "otg-vbus"; @@ -312,6 +303,8 @@ IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1>; + termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + termination-ohms = <150>; status = "okay"; }; @@ -648,7 +641,6 @@ &uart5 { }; &usbh1 { - vbus-supply = <®_h1_vbus>; pinctrl-names = "default"; phy_type = "utmi"; dr_mode = "host"; From 7b8861d8e6279a27873b85e3786fba8706fde7c9 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 22 Feb 2022 08:09:42 +0100 Subject: [PATCH 08/77] ARM: dts: imx6ul: add TQ-Systems MBa6ULx device trees Add device trees for the MBa6ULx mainboard with TQMa6ULx SoMs. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi | 211 +++++++ arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts | 55 ++ arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi | 37 ++ arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts | 15 + arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi | 71 +++ arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi | 43 ++ arch/arm/boot/dts/mba6ulx.dtsi | 571 ++++++++++++++++++ 8 files changed, 1005 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi create mode 100644 arch/arm/boot/dts/mba6ulx.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c16f8a2b738..c76742cfe5b1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -690,6 +690,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-kontron-n6310-s.dtb \ imx6ul-kontron-n6310-s-43.dtb \ imx6ul-liteboard.dtb \ + imx6ul-tqma6ul1-mba6ulx.dtb \ + imx6ul-tqma6ul2-mba6ulx.dtb \ imx6ul-opos6uldev.dtb \ imx6ul-pico-dwarf.dtb \ imx6ul-pico-hobbit.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi new file mode 100644 index 000000000000..eca94ed6451b --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/* + * Common for + * - TQMa6ULx + * - TQMa6ULxL + * - TQMa6ULLx + * - TQMa6ULLxL + */ + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_recovery>; + scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pfuze3000: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + reg_sw1a: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-ramp-delay = <6250>; + /* not used */ + }; + + reg_sw1b_core: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + reg_sw2: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + reg_sw3_ddr: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_swbst: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + /* not used */ + }; + + reg_snvs_3v0: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + reg_vccsd: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + }; + + reg_v33_3v3: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vldo1_3v3: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + /* not used */ + }; + + reg_vldo2: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + /* not used */ + }; + + reg_vldo3: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + /* not used */ + }; + + reg_vldo4: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; + + jc42_1a: eeprom-temperature-sensor@1a { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1a>; + }; + + m24c64_50: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + m24c02_52: eeprom@52 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + read-only; + }; + + rtc0: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + + /* + * PMIC & temperature sensor IRQ + * Both do currently not use IRQ + * potentially dangerous if used on baseboard + */ + pmic-int-hog { + gpio-hog; + gpios = <24 0>; + input; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <33000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + reg = <0>; + }; +}; + +/* eMMC */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz" , "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + + bus-width = <8>; + disable-wp; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c4_recovery: i2c4recoverygrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x4001b8b0 + >; + }; + + pinctrl_pmic: pmic { + fsl,pins = < + /* PMIC irq */ + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x1b099 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts new file mode 100644 index 000000000000..f2a5f17f312e --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul1-mba6ulx.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul1.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul1-mba6ulx", "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; +}; + +/* + * Note: can2 and fec2 are enabled on mba6ulx level (for i.MX6ULG2 usage) + * and need to be disabled here again + */ +&can2 { + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_mdc>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <0>; + }; + }; +}; + +&fec2 { + /delete-property/ phy-handle; + /delete-node/ mdio; +}; + +&iomuxc { + pinctrl_enet1_mdc: enet1mdcgrp { + fsl,pins = < + /* mdio */ + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi new file mode 100644 index 000000000000..24192d012ef7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul1.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul-tqma6ul2.dtsi" + +/ { + model = "TQ-Systems TQMa6UL1 SoM"; + compatible = "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; +}; + +/* + * There are no module specific differences compared to TQMa6UL2, + * only external interfaces differ + */ + +/* + * Devices not available on i.MX6ULG1 and should not be enabled on + * mainboard level (again) + */ +&can2 { + status = "disabled"; +}; + +&csi { + status = "disabled"; +}; + +&fec2 { + status = "disabled"; +}; + +&lcdif { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts new file mode 100644 index 000000000000..0757df2b8f48 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul2.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6ULx SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul2-mba6ulx", "tq,imx6ul-tqma6ul2", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi new file mode 100644 index 000000000000..e2e95dd92263 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulx-common.dtsi" + +/ { + model = "TQ-Systems TQMa6UL2 SoM"; + compatible = "tq,imx6ul-tqma6ul2", "fsl,imx6ul"; +}; + +&usdhc2 { + fsl,tuning-step = <6>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170e1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170e1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170e1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170e1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170e1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170e1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170e1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170e1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170e1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi new file mode 100644 index 000000000000..5afb9046c202 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ulx-common.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/* + * Common for + * - TQMa6ULx + * - TQMa6ULLx + */ + +&m24c64_50 { + vcc-supply = <®_sw2>; +}; + +&m24c02_52 { + vcc-supply = <®_sw2>; +}; + +®_sw2 { + regulator-boot-on; + regulator-always-on; +}; + +/* eMMC */ +&usdhc2 { + vmmc-supply = <®_sw2>; + vqmmc-supply = <®_vldo4>; +}; + +&iomuxc { + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70b9 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70b9 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70b9 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70b9 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70b9 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; +}; diff --git a/arch/arm/boot/dts/mba6ulx.dtsi b/arch/arm/boot/dts/mba6ulx.dtsi new file mode 100644 index 000000000000..fc38e185a51e --- /dev/null +++ b/arch/arm/boot/dts/mba6ulx.dtsi @@ -0,0 +1,571 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/ { + model = "TQ-Systems MBA6ULx Baseboard"; + + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc1; + rtc0 = &rtc0; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <®_mba6ul_3v3>; + enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + beeper: beeper { + compatible = "gpio-beeper"; + gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>; + }; + + gpio_buttons: gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_buttons>; + + button1 { + label = "s14"; + linux,code = ; + gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>; + }; + + button2 { + label = "s6"; + linux,code = ; + gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>; + }; + + button3 { + label = "s7"; + linux,code = ; + gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>; + }; + + power-button { + label = "POWER"; + linux,code = ; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + status = "okay"; + + led1 { + label = "led1"; + gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2 { + label = "led2"; + gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_lcd_pwr: regulator-lcd-pwr { + compatible = "regulator-fixed"; + regulator-name = "lcd-pwr"; + gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_mba6ul_3v3: regulator-mba6ul-3v3 { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6ul-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_mba6ul_5v0: regulator-mba6ul-5v0 { + compatible = "regulator-fixed"; + regulator-name = "supply-mba6ul-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_mpcie: regulator-mpcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "mpcie-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + startup-delay-us = <500000>; + vin-supply = <®_mba6ul_3v3>; + }; + + reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 { + compatible = "regulator-fixed"; + gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "otg2-vbus-supply-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_mpcie>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x6000000>; + linux,cma-default; + }; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "imx-audio-tlv320aic32x4"; + ssi-controller = <&sai1>; + audio-codec = <&tlv320aic32x4>; + audio-asrc = <&asrc>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_mba6ul_3v3>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_mba6ul_3v3>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <768000000>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-cs = <1>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + phy-supply = <®_mba6ul_3v3>; + phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-reset-post-delay = <1>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-supply = <®_mba6ul_3v3>; + phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-reset-post-delay = <1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + reg = <0>; + max-speed = <100>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; + reg = <1>; + max-speed = <100>; + }; + }; +}; + +&i2c4 { + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&clks IMX6UL_CLK_SAI1>; + clock-names = "mclk"; + ldoin-supply = <®_mba6ul_3v3>; + iov-supply = <®_mba6ul_3v3>; + }; + + jc42: temperature-sensor@19 { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x19>; + }; + + expander_out0: gpio-expander@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + expander_in0: gpio-expander@21 { + compatible = "nxp,pca9554"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander_in0>; + interrupt-parent = <&gpio4>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + enet1_int-hog { + gpio-hog; + gpios = <6 0>; + input; + }; + + enet2_int-hog { + gpio-hog; + gpios = <7 0>; + input; + }; + }; + + expander_out1: gpio-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + analog_touch: touchscreen@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio4>; + interrupt-controller; + status = "disabled"; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ + st,ave-ctrl = <3>; /* 8 sample average control */ + st,fraction-z = <7>; /* 7 length fractional part in z */ + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + st,mod-12b = <1>; /* 12-bit ADC */ + st,ref-sel = <0>; /* internal ADC reference */ + st,sample-time = <4>; /* ADC converstion time: 80 clocks */ + st,settling = <3>; /* 1 ms panel driver settling time */ + st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */ + }; + }; + + /* NXP SE97BTP with temperature sensor + eeprom */ + se97b: eeprom@51 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>, + <&clks IMX6UL_CLK_SAI1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24000000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart6dte>; */ + uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + status = "okay"; +}; + +/* otg-port */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + power-active-high; + over-current-active-low; + /* we implement only dual role but not a fully featured OTG */ + hnp-disable; + srp-disable; + adp-disable; + dr_mode = "otg"; + status = "okay"; +}; + +/* 7-port usb hub */ +/* id, pwr, oc pins not connected */ +&usbotg2 { + disable-over-current; + vbus-supply = <®_otg2vbus_5v0>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + vmmc-supply = <®_mba6ul_3v3>; + vqmmc-supply = <®_vccsd>; + no-1-8-v; + no-mmc; + no-sdio; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_buttons: buttonsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x100b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b020 + MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b020 + MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b020 + MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x1b020 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 + >; + }; + + pinctrl_enet2_mdc: enet2mdcgrp { + fsl,pins = < + /* mdio */ + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + >; + }; + + pinctrl_expander_in0: expanderin0grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b0b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + /* 100 k PD, DSE 120 OHM, SPPEED LO */ + MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b1 + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b1 + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 + MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 + MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1 + MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart6dte: uart6dte { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1 + MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1 + MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x1b0b1 + MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059 + MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0 + MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x0001b099 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9 + /* WP */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 + /* CD */ + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099 + >; + }; +}; From a333f3e46d76ecbe1cb8337fade76ee0d8514a8a Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 22 Feb 2022 08:09:43 +0100 Subject: [PATCH 09/77] ARM: dts: imx6ul: add TQ-Systems MBa6ULxL device trees Add device trees for the MBa6ULx mainboard with TQMa6ULxL SoMs. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts | 15 ++++ arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi | 71 +++++++++++++++++++ .../arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi | 48 +++++++++++++ 4 files changed, 135 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi create mode 100644 arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c76742cfe5b1..e991232ae943 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -692,6 +692,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-liteboard.dtb \ imx6ul-tqma6ul1-mba6ulx.dtb \ imx6ul-tqma6ul2-mba6ulx.dtb \ + imx6ul-tqma6ul2l-mba6ulx.dtb \ imx6ul-opos6uldev.dtb \ imx6ul-pico-dwarf.dtb \ imx6ul-pico-hobbit.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts new file mode 100644 index 000000000000..9d9b6b744a1c --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ul-tqma6ul2l.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ Systems TQMa6UL2L SoM on MBa6ULx board"; + compatible = "tq,imx6ul-tqma6ul2l-mba6ulx", "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi new file mode 100644 index 000000000000..caf2c5d03f7e --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ul2l.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ul.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulxl-common.dtsi" + +/ { + model = "TQ-Systems TQMa6UL2L SoM"; + compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; +}; + +&usdhc2 { + fsl,tuning-step= <6>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi new file mode 100644 index 000000000000..ba84a4f70ebd --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tqma6ulxl-common.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/* + * Common for + * - TQMa6ULxL + * - TQMa6ULLxL + */ + +/ { + reg_vin: reg-vin { + compatible = "regulator-fixed"; + regulator-name = "VIN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&m24c64_50 { + vcc-supply = <®_vin>; +}; + +&m24c02_52 { + vcc-supply = <®_vin>; +}; + +/* eMMC */ +&usdhc2 { + vmmc-supply = <®_vin>; + vqmmc-supply = <®_vldo4>; +}; + +&iomuxc { + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a9 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a9 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a9 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a9 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a9 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; +}; From 05c44ed0b776170fdf031080463cb5abd62cbed8 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 22 Feb 2022 08:09:44 +0100 Subject: [PATCH 10/77] ARM: dts: imx6ull: add TQ-Systems MBa6ULLx device trees Add device trees for the MBa6ULx mainboard with TQMa6ULLx SoMs. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ull-tqma6ull2-mba6ulx.dts | 15 ++++ arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi | 76 +++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e991232ae943..df272d658031 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -713,6 +713,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ + imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts new file mode 100644 index 000000000000..e593b7036fc7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ull-tqma6ull2.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ-Systems TQMa6ULL2 SoM on MBa6ULx board"; + compatible = "tq,imx6ull-tqma6ull2-mba6ulx", "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi new file mode 100644 index 000000000000..326e6da91ed4 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ull.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulx-common.dtsi" + +/ { + model = "TQ-Systems TQMa6ULL2 SoM"; + compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull"; +}; + +&usdhc2 { + fsl,tuning-step= <6>; + /* Errata ERR010450 Workaround */ + max-frequency = <99000000>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; From cbff1ae6bf3b9ecf0f4bf6afc509ce4b9aa70191 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 22 Feb 2022 08:09:45 +0100 Subject: [PATCH 11/77] ARM: dts: imx6ull: add TQ-Systems MBa6ULLxL device trees Add device trees for the MBa6ULx mainboard with TQMa6ULLxL SoMs. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts | 15 ++++ arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi | 76 +++++++++++++++++++ 3 files changed, 92 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts create mode 100644 arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index df272d658031..aec4196d56fc 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -714,6 +714,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ imx6ull-tqma6ull2-mba6ulx.dtb \ + imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts b/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts new file mode 100644 index 000000000000..33437aae9822 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l-mba6ulx.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +/dts-v1/; + +#include "imx6ull-tqma6ull2l.dtsi" +#include "mba6ulx.dtsi" + +/ { + model = "TQ Systems TQMa6ULL2L SoM on MBa6ULx board"; + compatible = "tq,imx6ull-tqma6ull2l-mba6ulx", "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi new file mode 100644 index 000000000000..8e4d5cd18614 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tqma6ull2l.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2018-2022 TQ-Systems GmbH + * Author: Markus Niebel + */ + +#include "imx6ull.dtsi" +#include "imx6ul-tqma6ul-common.dtsi" +#include "imx6ul-tqma6ulxl-common.dtsi" + +/ { + model = "TQ Systems TQMa6ULL2L SoM"; + compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull"; +}; + +&usdhc2 { + fsl,tuning-step= <6>; + /* Errata ERR010450 Workaround */ + max-frequency = <99000000>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017031 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017039 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017039 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017039 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017039 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017039 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017039 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017039 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017039 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017039 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 + /* rst */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 + >; + }; +}; From 0b08af343ab0b2dc53f34e7b2c7b98562b60cc93 Mon Sep 17 00:00:00 2001 From: Alexander Bauer Date: Tue, 22 Feb 2022 10:16:05 +0100 Subject: [PATCH 12/77] ARM: dts: imx6ull: Add support for PHYTEC phyGATE-Tauri-S with i.MX 6ULL Add support for the PHYTEC phyGATE-Tauri-S with i.MX 6ULL with eMMC or NAND. Supported features: * eMMC/NAND * i2c RTC * i2c TEMP * PMIC * PWM * debug UART * CAN * SD card * 2x 1Gbit Ethernet * RS232/RS485 * USB 2.0 Host * TPM * SPI-NOR Signed-off-by: Alexander Bauer Signed-off-by: Jens Lang Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + .../boot/dts/imx6ull-phytec-tauri-emmc.dts | 20 + .../boot/dts/imx6ull-phytec-tauri-nand.dts | 20 + arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi | 588 ++++++++++++++++++ 4 files changed, 630 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index aec4196d56fc..252353fb4e3b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -713,6 +713,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ + imx6ull-phytec-tauri-emmc.dtb \ + imx6ull-phytec-tauri-nand.dtb \ imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts new file mode 100644 index 000000000000..14adb87da911 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer + */ + +/dts-v1/; +#include "imx6ull-phytec-tauri.dtsi" + +/ { + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-phygate-tauri-emmc", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +/* EMMC-Version */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts new file mode 100644 index 000000000000..ae396ac63443 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer + */ + +/dts-v1/; +#include "imx6ull-phytec-tauri.dtsi" + +/ { + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-phygate-tauri-nand", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +/* NAND-Version */ +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi new file mode 100644 index 000000000000..5464a52a1f94 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-phytec-phycore-som.dtsi" + +/ { + + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-key"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key { + label = "KEY-A"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + reg_adc1_vref_3v3: regulator-vref-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_s25fl064_hold: regulator-s25fl064-hold { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_s25fl064_hold>; + compatible = "regulator-fixed"; + regulator-name = "s25fl064_hold"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_hub_vbus: regulator-hub-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhubpwr>; + compatible = "regulator-fixed"; + regulator-name = "usb_hub_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1pwr>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>, + <&pinctrl_user_leds_snvs>; + + user-led1 { + label = "yellow"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + + user-led2 { + label = "red"; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, + <&pinctrl_ecspi1_cs>; + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>, + <&gpio3 10 GPIO_ACTIVE_LOW>, + <&gpio3 11 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm_tis: tpm@1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm>; + compatible = "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + }; + + s25fl064: flash@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = " jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <40000000>; + m25p,fast-read; + status = "disabled"; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + dmas = <&sdma 7 8 0>, + <&sdma 8 8 0>; + dma-names = "rx", "tx"; + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + tmp102: tmp@49 { + compatible = "ti,tmp102"; + reg = <0x49>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tempsense>; + interrupt-parent = <&gpio5>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + i2c_rtc: rtc@68 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + compatible = "microcrystal,rv4162"; + reg = <0x68>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&mdio { + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + status = "okay"; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + status = "okay"; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* UART4 * RS485 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* UART5 * RS232 */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_hub_vbus>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; + +&iomuxc_snvs { + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; + + pinctrl_tempsense: tempsensegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_tpm: tpmgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 + >; + }; + + pinctrl_usbhubpwr: usbhubpwrgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059 + >; + }; + + pinctrl_user_leds_snvs: user_ledsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; +}; + +&iomuxc { + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */ + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1 + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1 + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1 + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1 + >; + }; + + pinctrl_ecspi1_cs: ecspi1csgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0 + >; + }; + + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0 + MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0 + >; + }; + + princtrl_flexcan2_en: flexcan2engrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0 + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0 + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0 + MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0 + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm6: pwm6grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0 + >; + }; + + pinctrl_s25fl064_hold: s25fl064holdgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80 + >; + }; + + pinctrl_usbotg1pwr: usbotg1pwrgrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_user_leds: userledsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79 + >; + }; +}; From 8bcbcbba9109d6e26029c089826b708164a2cb12 Mon Sep 17 00:00:00 2001 From: Andrej Picej Date: Tue, 22 Feb 2022 10:16:06 +0100 Subject: [PATCH 13/77] ARM: dts: imx6ul: peb-av-02: move to 3 cell pwm Instead of changing default pwm-cells property, use the default "#pwm-cells = <3>" and add the third option. Signed-off-by: Andrej Picej Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi index 7cda6944501d..6ce534a896ef 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi @@ -11,7 +11,7 @@ backlight_lcd: backlight-lcd { brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <5>; power-supply = <®_backlight_en>; - pwms = <&pwm3 0 5000000>; + pwms = <&pwm3 0 5000000 0>; status = "disabled"; }; @@ -91,7 +91,6 @@ lcdif_parallel_out: endpoint { }; &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "disabled"; From 90f38145e6dd25ff0d9ebe48d28b8ae3a814d52d Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 3 Mar 2022 16:06:53 +0100 Subject: [PATCH 14/77] ARM: dts: imx7s: fix iomuxc_lpsr node name Schema requires the node being named 'pinctrl'. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 5af6d58666f4..008e3da460f1 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -446,7 +446,7 @@ wdog4: watchdog@302b0000 { status = "disabled"; }; - iomuxc_lpsr: iomuxc-lpsr@302c0000 { + iomuxc_lpsr: pinctrl@302c0000 { compatible = "fsl,imx7d-iomuxc-lpsr"; reg = <0x302c0000 0x10000>; fsl,input-sel = <&iomuxc>; From 94382f08702efdd6b6bb3e875726942954a723d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 25 Mar 2022 18:19:55 +0100 Subject: [PATCH 15/77] ARM: dts: imx6qdl-tx6: Drop some duplicated properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit clocks and clock-names are already present in imx6qdl.dtsi since commit f3e7dae323ab ("ARM: dts: imx6qdl: add enet_out clk support"). The change to imx6qdl.dtsi was explicitly done to avoid this construct in this file, so benefit from the change and drop these properties. Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-tx6.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index bcc5bbcce769..f41f86a76ea9 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -264,11 +264,6 @@ &gpio3 19 GPIO_ACTIVE_HIGH &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet &pinctrl_enet_mdio &pinctrl_etnphy_rst>; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET_REF>, - <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp", "enet_out"; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; phy-reset-post-delay = <10>; From 3d397a1277853498e8b7b305f2610881357c033f Mon Sep 17 00:00:00 2001 From: Thorsten Scherer Date: Wed, 6 Apr 2022 06:39:45 +0200 Subject: [PATCH 16/77] ARM: dts: ci4x10: Adapt to changes in imx6qdl.dtsi regarding fec clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit f3e7dae323ab ("ARM: dts: imx6qdl: add enet_out clk support") added another item to the list of clocks for the fec device. As imx6dl-eckelmann-ci4x10.dts only overwrites clocks, but not clock-names this resulted in an inconsistency with clocks having one item more than clock-names. Also overwrite clock-names with the same value as in imx6qdl.dtsi. This is a no-op today, but prevents similar inconsistencies if the soc file will be changed in a similar way in the future. Signed-off-by: Thorsten Scherer Reviewed-by: Uwe Kleine-König Fixes: f3e7dae323ab ("ARM: dts: imx6qdl: add enet_out clk support") Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts index b4a9523e325b..864dc5018451 100644 --- a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts +++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts @@ -297,7 +297,11 @@ &fec { phy-mode = "rmii"; phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; phy-handle = <&phy>; - clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&rmii_clk>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_out"; status = "okay"; mdio { From ba9fe460dc2cfe90dc115b22af14dd3f13cffa0f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:31:54 +0200 Subject: [PATCH 17/77] ARM: dts: imx: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-evk.dts | 2 +- arch/arm/boot/dts/imx28-m28evk.dts | 2 +- arch/arm/boot/dts/imx28-sps1.dts | 2 +- arch/arm/boot/dts/imx6dl-rex-basic.dts | 2 +- arch/arm/boot/dts/imx6q-ba16.dtsi | 2 +- arch/arm/boot/dts/imx6q-bx50v3.dtsi | 2 +- arch/arm/boot/dts/imx6q-cm-fx6.dts | 2 +- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 2 +- arch/arm/boot/dts/imx6q-dms-ba16.dts | 2 +- arch/arm/boot/dts/imx6q-gw5400-a.dts | 2 +- arch/arm/boot/dts/imx6q-marsboard.dts | 2 +- arch/arm/boot/dts/imx6q-rex-pro.dts | 2 +- arch/arm/boot/dts/imx6qdl-aristainetos.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 2 +- arch/arm/boot/dts/imx6sl-evk.dts | 2 +- arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 2 +- arch/arm/boot/dts/imx6sx-sdb-reva.dts | 4 ++-- arch/arm/boot/dts/imx6sx-sdb.dts | 4 ++-- arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 2 +- arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi | 2 +- arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi | 2 +- arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi | 2 +- arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi | 2 +- 32 files changed, 34 insertions(+), 34 deletions(-) diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 7e2b0f198dfa..1053b7c584d8 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -129,7 +129,7 @@ ssp2: spi@80014000 { pinctrl-0 = <&spi2_pins_a>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf016b", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index f3bddc5ada4b..13acdc7916b9 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -33,7 +33,7 @@ ssp2: spi@80014000 { pinctrl-0 = <&spi2_pins_a>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts index 43be7a6a769b..90928db0df70 100644 --- a/arch/arm/boot/dts/imx28-sps1.dts +++ b/arch/arm/boot/dts/imx28-sps1.dts @@ -51,7 +51,7 @@ ssp2: spi@80014000 { pinctrl-0 = <&spi2_pins_a>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "everspin,mr25h256", "mr25h256"; diff --git a/arch/arm/boot/dts/imx6dl-rex-basic.dts b/arch/arm/boot/dts/imx6dl-rex-basic.dts index 0f1616bfa9a8..b72f8ea1e6f6 100644 --- a/arch/arm/boot/dts/imx6dl-rex-basic.dts +++ b/arch/arm/boot/dts/imx6dl-rex-basic.dts @@ -19,7 +19,7 @@ memory@10000000 { }; &ecspi3 { - flash: m25p80@0 { + flash: flash@0 { compatible = "sst,sst25vf016b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi index 6330d75f8f39..f266f1b7e0cf 100644 --- a/arch/arm/boot/dts/imx6q-ba16.dtsi +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi @@ -142,7 +142,7 @@ &ecspi1 { pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: n25q032@0 { + flash: flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi index 10922375c51e..ead83091e193 100644 --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi @@ -160,7 +160,7 @@ &ecspi5 { pinctrl-0 = <&pinctrl_ecspi5>; status = "okay"; - m25_eeprom: m25p80@0 { + m25_eeprom: flash@0 { compatible = "atmel,at25"; spi-max-frequency = <10000000>; size = <0x8000>; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index bfb530f29d9d..1ad41c944b4b 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -260,7 +260,7 @@ &ecspi1 { pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index c713ac03b3b9..9591848cbd37 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -102,7 +102,7 @@ &ecspi5 { cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "m25p80", "jedec,spi-nor"; spi-max-frequency = <40000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6q-dms-ba16.dts b/arch/arm/boot/dts/imx6q-dms-ba16.dts index 48fb47e715f6..137db38f0d27 100644 --- a/arch/arm/boot/dts/imx6q-dms-ba16.dts +++ b/arch/arm/boot/dts/imx6q-dms-ba16.dts @@ -47,7 +47,7 @@ &ecspi5 { pinctrl-0 = <&pinctrl_ecspi5>; status = "okay"; - m25_eeprom: m25p80@0 { + m25_eeprom: flash@0 { compatible = "atmel,at25256B", "atmel,at25"; spi-max-frequency = <20000000>; size = <0x8000>; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 4cde45d5c90c..e894faba571f 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -137,7 +137,7 @@ &ecspi1 { pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "sst,w25q256", "jedec,spi-nor"; spi-max-frequency = <30000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts index 05ee28388229..cc1801002394 100644 --- a/arch/arm/boot/dts/imx6q-marsboard.dts +++ b/arch/arm/boot/dts/imx6q-marsboard.dts @@ -100,7 +100,7 @@ &ecspi1 { cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; status = "okay"; - m25p80@0 { + flash@0 { compatible = "microchip,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6q-rex-pro.dts b/arch/arm/boot/dts/imx6q-rex-pro.dts index 1767e1a3cd53..271f4b2d9b9f 100644 --- a/arch/arm/boot/dts/imx6q-rex-pro.dts +++ b/arch/arm/boot/dts/imx6q-rex-pro.dts @@ -19,7 +19,7 @@ memory@10000000 { }; &ecspi3 { - flash: m25p80@0 { + flash: flash@0 { compatible = "sst,sst25vf032b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi index e21f6ac864e5..baa197c90060 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi @@ -96,7 +96,7 @@ &ecspi4 { pinctrl-0 = <&pinctrl_ecspi4>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q128a11", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi index 563bf9d44fe0..2ba577e602e7 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi @@ -131,7 +131,7 @@ &ecspi4 { pinctrl-0 = <&pinctrl_ecspi4>; status = "okay"; - flash: m25p80@1 { + flash: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q128a11", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi index 648f5fcb72e6..2c1d6f28e695 100644 --- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi @@ -35,7 +35,7 @@ &ecspi3 { pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf040b", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi index b167b33bd108..095c9143d99a 100644 --- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi @@ -258,7 +258,7 @@ &ecspi4 { status = "okay"; /* default boot source: workaround #1 for errata ERR006282 */ - smarc_flash: spi-flash@0 { + smarc_flash: flash@0 { compatible = "winbond,w25q16dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index ac34709e9741..0ad4cb4f1e82 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -179,7 +179,7 @@ &ecspi1 { pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "microchip,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index c96f4d7e1e0d..beaa2dcd436c 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -321,7 +321,7 @@ &ecspi1 { pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "microchip,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi index 92d09a3ebe0e..ee7e2371f94b 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -252,7 +252,7 @@ &ecspi1 { pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "microchip,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 49da30d7510c..904d5d051d63 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -237,7 +237,7 @@ &ecspi1 { pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "sst,sst25vf016b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 5e58740d40c5..1368a4762037 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -272,7 +272,7 @@ &ecspi1 { pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; status = "disabled"; /* pin conflict with WEIM NOR */ - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p32", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index eb9a0b104f1c..901b9a761b66 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -313,7 +313,7 @@ &ecspi1 { pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "sst,sst25vf016b", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 0c0105468a2f..37482a9023fc 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -197,7 +197,7 @@ &ecspi1 { pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p32", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 25f6f2fb1555..f16c830f1e91 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -137,7 +137,7 @@ &ecspi1 { pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p32", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index 66af78e83b70..a2c79bcf9a11 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -107,7 +107,7 @@ &ecspi1 { pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; - flash: m25p80@0 { + flash: flash@0 { compatible = "microchip,sst25vf016b"; spi-max-frequency = <20000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index dce5dcf96c25..7dda42553f4b 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -123,7 +123,7 @@ &qspi2 { pinctrl-0 = <&pinctrl_qspi2>; status = "okay"; - flash0: s25fl128s@0 { + flash0: flash@0 { reg = <0>; #address-cells = <1>; #size-cells = <1>; @@ -133,7 +133,7 @@ flash0: s25fl128s@0 { spi-tx-bus-width = <4>; }; - flash1: s25fl128s@2 { + flash1: flash@2 { reg = <2>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 99f4cf777a38..969cfe920d25 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -108,7 +108,7 @@ &qspi2 { pinctrl-0 = <&pinctrl_qspi2>; status = "okay"; - flash0: n25q256a@0 { + flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; @@ -118,7 +118,7 @@ flash0: n25q256a@0 { reg = <0>; }; - flash1: n25q256a@2 { + flash1: flash@2 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi index a3fde3316c73..1a18c41ce385 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi @@ -286,7 +286,7 @@ &qspi { pinctrl-0 = <&pinctrl_qspi>; status = "okay"; - flash0: n25q256a@0 { + flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi index 47d3ce5d255f..acd936540d89 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi @@ -19,7 +19,7 @@ memory@80000000 { }; &qspi { - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spi-nand"; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi index a095a7654ac6..29ed38dce580 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6311-som.dtsi @@ -18,7 +18,7 @@ memory@80000000 { }; &qspi { - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spi-nand"; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi index 2a449a3c1ae2..09a83dbdf651 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi @@ -19,7 +19,7 @@ &ecspi2 { pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi b/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi index b7e984284e1a..d000606c0704 100644 --- a/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi +++ b/arch/arm/boot/dts/imx6ull-kontron-n6411-som.dtsi @@ -18,7 +18,7 @@ memory@80000000 { }; &qspi { - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spi-nand"; From 91dbd54ec55d3521f32beefddb64e81dc49e4abb Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:23 +0200 Subject: [PATCH 18/77] ARM: dts: imx6dl-colibri: Drop dedicated v1.1 device tree Drop Colibri V1.1 device tree, this is just a duplicate of Colibri V1.0 with the possibility to use SD cards in UHS mode if the carrier board does not have 3.3V pull up resistor. The dedicated device tree kept the feature switched of by setting the no-1-8-v property and thus does not offer anything different than what the regular device tree does. Thus drop the dedicated device tree and merge the preparation to allow enabling the feature should a carrier without pull ups be used into the regular device tree. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 - .../boot/dts/imx6dl-colibri-v1_1-eval-v3.dts | 31 ------------- .../boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi | 44 ------------------- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 29 +++++++++++- 4 files changed, 27 insertions(+), 78 deletions(-) delete mode 100644 arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts delete mode 100644 arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 252353fb4e3b..ae3cac8e653b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -459,7 +459,6 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ imx6dl-colibri-eval-v3.dtb \ - imx6dl-colibri-v1_1-eval-v3.dtb \ imx6dl-cubox-i.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts deleted file mode 100644 index 223275f028f1..000000000000 --- a/arch/arm/boot/dts/imx6dl-colibri-v1_1-eval-v3.dts +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2020 Toradex - */ - -/dts-v1/; - -#include "imx6dl-colibri-eval-v3.dts" -#include "imx6qdl-colibri-v1_1-uhs.dtsi" - -/ { - model = "Toradex Colibri iMX6DL/S V1.1 on Colibri Evaluation Board V3"; - compatible = "toradex,colibri_imx6dl-v1_1-eval-v3", - "toradex,colibri_imx6dl-v1_1", - "toradex,colibri_imx6dl-eval-v3", - "toradex,colibri_imx6dl", - "fsl,imx6dl"; -}; - -/* Colibri MMC */ -&usdhc1 { - status = "okay"; - /* - * Please make sure your carrier board does not pull-up any of - * the MMC/SD signals to 3.3 volt before attempting to activate - * UHS-I support. - * To let signaling voltage be changed to 1.8V, please - * delete no-1-8-v property (example below): - * /delete-property/no-1-8-v; - */ -}; diff --git a/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi b/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi deleted file mode 100644 index 7672fbfc29be..000000000000 --- a/arch/arm/boot/dts/imx6qdl-colibri-v1_1-uhs.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright 2020 Toradex - */ - -&iomuxc { - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 - >; - }; -}; - -/* Colibri MMC */ -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; - vmmc-supply = <®_module_3v3>; - vqmmc-supply = <&vgen3_reg>; - wakeup-source; - keep-power-in-suspend; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; -}; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 4e2a309c93fa..16d38bc78b2a 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -370,11 +370,14 @@ &usbotg { /* Colibri MMC */ &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ disable-wp; - vqmmc-supply = <®_module_3v3>; + vmmc-supply = <®_module_3v3>; + vqmmc-supply = <&vgen3_reg>; bus-width = <4>; no-1-8-v; status = "disabled"; @@ -692,6 +695,28 @@ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 >; }; + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 From 5f5c579a34a87117c20b411df583ae816c1ec84f Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:24 +0200 Subject: [PATCH 19/77] ARM: dts: imx6dl-colibri: Fix I2C pinmuxing Fix names of extra pingroup node and property for gpio bus recovery. Without the change i2c2 is not functional. Fixes: 56f0df6b6b58 ("ARM: dts: imx*(colibri|apalis): add missing recovery modes to i2c") Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 16d38bc78b2a..c6112b1bffd4 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2014-2020 Toradex + * Copyright 2014-2022 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ @@ -132,7 +132,7 @@ &i2c2 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-0 = <&pinctrl_i2c2_gpio>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; @@ -491,7 +491,7 @@ MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 >; }; - pinctrl_i2c2_gpio: i2c2grp { + pinctrl_i2c2_gpio: i2c2gpiogrp { fsl,pins = < MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 From 96a34c46e9dba69e4fe4b3edaaf278190f4c53be Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Mon, 11 Apr 2022 17:22:25 +0200 Subject: [PATCH 20/77] ARM: dts: imx6dl-colibri: Add gpio-line-names Add GPIO line names on module level. Those are all GPIOs which a user might use on his custom carrier board. If more meaningful names are available on the carrier board, the user can overwrite the line names in the carrier board level device tree. Signed-off-by: Oleksandr Suvorov Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 218 +++++++++++++++++++++++++ 1 file changed, 218 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index c6112b1bffd4..c92887f6af61 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -118,6 +118,224 @@ ethphy: ethernet-phy@0 { }; }; +&gpio1 { + gpio-line-names = "", + "SODIMM_67", + "SODIMM_180", + "SODIMM_196", + "SODIMM_174", + "SODIMM_176", + "SODIMM_194", + "SODIMM_55", + "SODIMM_63", + "SODIMM_28", + "SODIMM_93", + "SODIMM_69", + "SODIMM_99", + "SODIMM_130", + "SODIMM_106", + "SODIMM_98", + "SODIMM_192", + "SODIMM_49", + "SODIMM_190", + "SODIMM_51", + "SODIMM_47", + "SODIMM_53", + "", + "SODIMM_22"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_132", + "SODIMM_134", + "SODIMM_135", + "SODIMM_133", + "SODIMM_102", + "SODIMM_43", + "SODIMM_127", + "SODIMM_37", + "SODIMM_104", + "SODIMM_59", + "SODIMM_30", + "SODIMM_100", + "SODIMM_38", + "SODIMM_34", + "SODIMM_32", + "SODIMM_36", + "SODIMM_59", + "SODIMM_67", + "SODIMM_97", + "SODIMM_79", + "SODIMM_103", + "SODIMM_101", + "SODIMM_45", + "SODIMM_105", + "SODIMM_107", + "SODIMM_91", + "SODIMM_89", + "SODIMM_150", + "SODIMM_126", + "SODIMM_128", + "", + "SODIMM_94"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_111", + "SODIMM_113", + "SODIMM_115", + "SODIMM_117", + "SODIMM_119", + "SODIMM_121", + "SODIMM_123", + "SODIMM_125", + "SODIMM_110", + "SODIMM_112", + "SODIMM_114", + "SODIMM_116", + "SODIMM_118", + "SODIMM_120", + "SODIMM_122", + "SODIMM_124", + "", + "SODIMM_96", + "SODIMM_77", + "SODIMM_25", + "SODIMM_27", + "SODIMM_88", + "SODIMM_90", + "SODIMM_31", + "SODIMM_23", + "SODIMM_29", + "SODIMM_71", + "SODIMM_73", + "SODIMM_92", + "SODIMM_81", + "SODIMM_131", + "SODIMM_129"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "SODIMM_168", + "", + "", + "", + "", + "SODIMM_184", + "SODIMM_186", + "HDMI_15", + "HDMI_16", + "SODIMM_178", + "SODIMM_188", + "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "SODIMM_24", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_95", + "", + "SODIMM_86", + "", + "SODIMM_65", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_136", + "SODIMM_138", + "SODIMM_140", + "SODIMM_142", + "SODIMM_144", + "SODIMM_146", + "SODIMM_172", + "SODIMM_170", + "SODIMM_149", + "SODIMM_151", + "SODIMM_153", + "SODIMM_155", + "SODIMM_157", + "SODIMM_159", + "SODIMM_161", + "SODIMM_163", + "SODIMM_33", + "SODIMM_35", + "SODIMM_165", + "SODIMM_167"; +}; + +&gpio6 { + gpio-line-names = "SODIMM_169", + "SODIMM_171", + "SODIMM_173", + "SODIMM_175", + "SODIMM_177", + "SODIMM_179", + "SODIMM_85", + "SODIMM_166", + "SODIMM_160", + "SODIMM_162", + "SODIMM_158", + "SODIMM_164", + "", + "", + "SODIMM_156", + "SODIMM_75", + "SODIMM_154", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_152"; +}; + +&gpio7 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_19", + "SODIMM_21", + "", + "SODIMM_137"; +}; + &hdmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hdmi_ddc>; From 5ab9c76a82670f369969a08677c0afba22a8da15 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:26 +0200 Subject: [PATCH 21/77] ARM: dts: imx6dl-colibri: Disable add-on accessories The Toradex Colibri family is composed of SoM that can be plugged in various carrier board, with carrier boards allowing multiple optional add-on (e.g. display, camera, ...). Keep all the SoM specific part into the module .dtsi, disabling everything that is not self-contained on the board. The carrier board dts can reuse/enable anything that is defined in the module dtsi. Additional device tree overlays can be used for any accessories that are plugged in the carrier board. Disable parallel RGB: The parallel RGB interface (lcd_display) and all related nodes can be enabled in an overlay if used. Keep all nodes disabled in the module-level device tree. Rename display interface node to match imx6qdl-apalis to make it easier to use overlays. The pwm-backlight binding now requires the power-supply property, add it. Disable stmpe touchscreen: The touchscreen can be enabled in an overlay if used. Add labels to the stmpe sub nodes. Disable hdmi interface: HDMI can be enabled in an overlay if used. Update SPDX-License spelling to latest convention. Update Copyright year. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 59 +------------------- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 57 ++++++++++++++++++- 2 files changed, 56 insertions(+), 60 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index 7da74e6f46d9..535b5c156229 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2014-2020 Toradex + * Copyright 2014-2022 Toradex * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. */ @@ -58,53 +58,6 @@ wakeup { wakeup-source; }; }; - - lcd_display: disp0 { - compatible = "fsl,imx-parallel-display"; - #address-cells = <1>; - #size-cells = <0>; - interface-pix-fmt = "bgr666"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_lcdif>; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; -}; - -&backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; - status = "okay"; }; /* Colibri SSP */ @@ -122,10 +75,6 @@ mcp251x0: mcp251x@0 { }; }; -&hdmi { - status = "okay"; -}; - /* * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ @@ -178,10 +127,6 @@ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */ }; }; -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - &pwm1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index c92887f6af61..f6243762e918 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -13,13 +13,59 @@ / { backlight: backlight { compatible = "pwm-backlight"; + brightness-levels = <0 127 191 223 239 247 251 255>; + default-brightness-level = <1>; + enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_bl_on>; + power-supply = <®_module_3v3>; pwms = <&pwm3 0 5000000>; - enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ status = "disabled"; }; + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "bgr666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel_dpi: panel-dpi { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; regulator-name = "+V3.3"; @@ -476,7 +522,7 @@ stmpe811@41 { /* ADC converstion time: 80 clocks */ st,sample-time = <4>; - stmpe_touchscreen { + stmpe_ts: stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ st,ave-ctrl = <3>; @@ -491,9 +537,10 @@ stmpe_touchscreen { st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; + status = "disabled"; }; - stmpe_adc { + stmpe_adc: stmpe_adc { compatible = "st,stmpe-adc"; /* forbid to use ADC channels 3-0 (touch) */ st,norequest-mask = <0x0F>; @@ -514,6 +561,10 @@ &i2c3 { status = "disabled"; }; +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + /* Colibri PWM */ &pwm1 { pinctrl-names = "default"; From 4e0483652664750dc0c50d3634478fac661bfd7f Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:27 +0200 Subject: [PATCH 22/77] ARM: dts: imx6dl-colibri: Command pmic to standby for poweroff The Colibri iMX6 HW doesn't allow to use the PWR_ON_REQ signal for poweroff. Use the fsl,pmic-stby-poweroff property to command the PMIC into a low power mode in poweroff. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index f6243762e918..da52a71bb6e7 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -138,6 +138,10 @@ &can2 { status = "disabled"; }; +&clks { + fsl,pmic-stby-poweroff; +}; + /* Colibri SSP */ &ecspi4 { cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; @@ -403,6 +407,7 @@ &i2c2 { pmic: pfuze100@8 { compatible = "fsl,pfuze100"; + fsl,pmic-stby-poweroff; reg = <0x08>; regulators { From bccf73ecd098570e98177e654371542667e32cd8 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:28 +0200 Subject: [PATCH 23/77] ARM: dts: imx6dl-colibri: Add additional pingroups The Toradex board Iris V2 has an LVDS transceiver which is configured with 4 signals. Add corresponding pins into the separate pingroup to be able to manage the transceiver. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 52 ++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index da52a71bb6e7..3459bfb5c60b 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -700,6 +700,30 @@ MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 >; }; + /* CSI pins used as GPIOs */ + pinctrl_csi_gpio_1: csigpio1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + >; + }; + + pinctrl_csi_gpio_2: csigpio2grp { + fsl,pins = < + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 + >; + }; + pinctrl_ecspi4: ecspi4grp { fsl,pins = < MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 @@ -739,6 +763,25 @@ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 >; }; + pinctrl_gpio_1: gpio1grp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; + pinctrl_gpio_2: gpio2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + pinctrl_gpio_bl_on: gpioblon { fsl,pins = < MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 @@ -832,6 +875,15 @@ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1 >; }; + pinctrl_lvds_transceiver: lvdstxgrp { + fsl,pins = < + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x03030 /* SODIMM 95 */ + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0b030 /* SODIMM 55 */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x03030 /* SODIMM 63 */ + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM 99 */ + >; + }; + pinctrl_mic_gnd: gpiomicgnd { fsl,pins = < /* Controls Mic GND, PU or '1' pull Mic GND to GND */ From 1524b27c94a63713fabb53542cca2e23384f79c3 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:29 +0200 Subject: [PATCH 24/77] ARM: dts: imx6dl-colibri: Move common nodes to SoM dtsi The following two nodes define module level functionality, move them from the carrier board dts file to the SoM file. While at it, reorder the properties in the gpio-keys node alphabetical. - gpio-keys defining the wakeup pin - memory node The atmel touchscreen node can be used on any carrier board. Move it from the carrier board to the module-level device tree and keep it disabled. Set the default pinmuxing to the dedicated connector available on newer carrier boards and rename the pinctrl labels specifying the INT/Reset signal to a common pattern. pinctrl_atmel_conn - uses 107/106 pins as used on dedicated connector pinctrl_atmel_adap - uses 28/30 pins as used with jumper wires Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 49 ------------------ arch/arm/boot/dts/imx6qdl-colibri.dtsi | 53 ++++++++++++++++++++ 2 files changed, 53 insertions(+), 49 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index 535b5c156229..dff2d35e693b 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -17,12 +17,6 @@ / { compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl", "fsl,imx6dl"; - /* Will be filled by the bootloader */ - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0>; - }; - aliases { i2c0 = &i2c2; i2c1 = &i2c3; @@ -44,20 +38,6 @@ clk16m: clock-16m { clock-frequency = <16000000>; clock-output-names = "clk16m"; }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - - wakeup { - label = "Wake-Up"; - gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; }; /* Colibri SSP */ @@ -81,21 +61,6 @@ mcp251x0: mcp251x@0 { &i2c3 { status = "okay"; - /* - * Touchscreen is using SODIMM 28/30, also used for PWM, PWM, - * aka pwm2, pwm3. so if you enable touchscreen, disable the pwms - */ - touchscreen@4a { - compatible = "atmel,maxtouch"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcap_1>; - reg = <0x4a>; - interrupt-parent = <&gpio1>; - interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* SODIMM 30 */ - status = "disabled"; - }; - /* M41T0M6 real time clock on carrier board */ rtc_i2c: rtc@68 { compatible = "st,m41t0"; @@ -111,20 +76,6 @@ &pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4 &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6 &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1 >; - - pinctrl_pcap_1: pcap1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */ - >; - }; - - pinctrl_mxt_ts: mxttsgrp { - fsl,pins = < - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */ - MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */ - >; - }; }; &pwm1 { diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 3459bfb5c60b..1c49fd3e6286 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -23,6 +23,20 @@ backlight: backlight { status = "disabled"; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + debounce-interval = <10>; + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + lcd_display: disp0 { compatible = "fsl,imx-parallel-display"; interface-pix-fmt = "bgr666"; @@ -50,6 +64,12 @@ lcd_display_out: endpoint { }; }; + /* Will be filled by the bootloader */ + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0>; + }; + panel_dpi: panel-dpi { /* * edt,et057090dhu: EDT 5.7" LCD TFT @@ -564,6 +584,17 @@ &i2c3 { scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; + + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + interrupt-parent = <&gpio2>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_atmel_conn>; + reg = <0x4a>; + reset-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + status = "disabled"; + }; }; &ipu1_di0_disp0 { @@ -682,6 +713,28 @@ &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh_oc_1>; + /* Atmel MXT touchsceen + Capacitive Touch Adapter */ + /* NOTE: This pin group conflicts with pin groups + * pinctrl_pwm1/pinctrl_pwm4. Don't use them simultaneously. + */ + pinctrl_atmel_adap: atmeladaptergrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0xb0b1 /* SODIMM 28 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0xb0b1 /* SODIMM 30 */ + >; + }; + + /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ + /* NOTE: This pin group conflicts with pin groups pinctrl_weim_cs1 and + * pinctrl_weim_cs2. Don't use them simultaneously. + */ + pinctrl_atmel_conn: atmelconnectorgrp { + fsl,pins = < + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0xb0b1 /* SODIMM_107 */ + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1 /* SODIMM_106 */ + >; + }; + pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 From 965f2ca42cbd59053f93d67587c4055e994680c4 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:30 +0200 Subject: [PATCH 25/77] ARM: dts: imx6dl-colibri: Cleanup - Sort pinctrl nodes alphabetically - End all pinctrl node names in grp and avoid using dashes - Change pinctrl_usbc_id_1's node name to not use underscores - Change the pmic's node name to pmic@8 per binding requirement - Add sound-dai-cells to the codec node per binding requirement Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 2 +- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 384 ++++++++++--------- 2 files changed, 194 insertions(+), 192 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index dff2d35e693b..7272edd85a49 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -46,10 +46,10 @@ &ecspi4 { mcp251x0: mcp251x@0 { compatible = "microchip,mcp2515"; - reg = <0>; clocks = <&clk16m>; interrupt-parent = <&gpio3>; interrupts = <27 0x2>; + reg = <0>; spi-max-frequency = <10000000>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 1c49fd3e6286..1c3c34bbfe98 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -104,36 +104,36 @@ reg_module_3v3_audio: regulator-module-3v3-audio { reg_usb_host_vbus: regulator-usb-host-vbus { compatible = "regulator-fixed"; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; - regulator-name = "usb_host_vbus"; - regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ + regulator-min-microvolt = <5000000>; + regulator-name = "usb_host_vbus"; status = "disabled"; }; sound { compatible = "fsl,imx-audio-sgtl5000"; - model = "imx6dl-colibri-sgtl5000"; - ssi-controller = <&ssi1>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HP_OUT", "LINE_IN", "Line In Jack", "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias"; + model = "imx6dl-colibri-sgtl5000"; mux-int-port = <1>; mux-ext-port = <5>; + ssi-controller = <&ssi1>; }; /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ sound_spdif: sound-spdif { compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; spdif-controller = <&spdif>; spdif-in; spdif-out; + model = "imx-spdif"; status = "disabled"; }; }; @@ -171,10 +171,10 @@ &ecspi4 { }; &fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; phy-handle = <ðphy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; status = "okay"; mdio { @@ -425,61 +425,61 @@ &i2c2 { sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; - pmic: pfuze100@8 { + pmic: pmic@8 { compatible = "fsl,pfuze100"; fsl,pmic-stby-poweroff; reg = <0x08>; regulators { sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1875000>; + regulator-min-microvolt = <300000>; regulator-ramp-delay = <6250>; }; sw1c_reg: sw1c { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1875000>; + regulator-min-microvolt = <300000>; regulator-ramp-delay = <6250>; }; sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1975000>; + regulator-min-microvolt = <400000>; }; swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5150000>; + regulator-min-microvolt = <5000000>; }; snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <1000000>; }; vref_reg: vrefddr { - regulator-boot-on; regulator-always-on; + regulator-boot-on; }; /* vgen1: unused */ vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1550000>; + regulator-min-microvolt = <800000>; }; /* @@ -487,57 +487,58 @@ vgen2_reg: vgen2 { * the i.MX 6 NVCC_SD1. */ vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; }; vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; }; }; }; codec: sgtl5000@a { compatible = "fsl,sgtl5000"; - reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; + lrclk-strength = <3>; + reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_module_3v3_audio>; VDDIO-supply = <®_module_3v3>; VDDD-supply = <&vgen4_reg>; - lrclk-strength = <3>; }; /* STMPE811 touch screen controller */ stmpe811@41 { compatible = "st,stmpe811"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_touch_int>; - reg = <0x41>; + blocks = <0x5>; interrupts = <20 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio6>; interrupt-controller; id = <0>; - blocks = <0x5>; irq-trigger = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + reg = <0x41>; /* 3.25 MHz ADC clock speed */ st,adc-freq = <1>; /* 12-bit ADC */ @@ -643,27 +644,27 @@ &ssi1 { /* Colibri UART_A */ &uart1 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; - fsl,dte-mode; uart-has-rtscts; status = "disabled"; }; /* Colibri UART_B */ &uart2 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2_dte>; - fsl,dte-mode; uart-has-rtscts; status = "disabled"; }; /* Colibri UART_C */ &uart3 { + fsl,dte-mode; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3_dte>; - fsl,dte-mode; status = "disabled"; }; @@ -675,27 +676,27 @@ &usbotg { /* Colibri MMC */ &usdhc1 { + cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ + bus-width = <4>; + no-1-8-v; + disable-wp; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; - cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ - disable-wp; vmmc-supply = <®_module_3v3>; vqmmc-supply = <&vgen3_reg>; - bus-width = <4>; - no-1-8-v; status = "disabled"; }; /* eMMC */ &usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_module_3v3>; bus-width = <8>; no-1-8-v; non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vqmmc-supply = <®_module_3v3>; status = "okay"; }; @@ -737,12 +738,12 @@ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0xb0b1 /* SODIMM_106 */ pinctrl_audmux: audmuxgrp { fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 >; }; @@ -779,26 +780,26 @@ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 pinctrl_ecspi4: ecspi4grp { fsl,pins = < + /* SPI CS */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - /* SPI CS */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x000b1 >; }; pinctrl_enet: enetgrp { fsl,pins = < + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) + MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0) >; }; @@ -835,13 +836,13 @@ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 >; }; - pinctrl_gpio_bl_on: gpioblon { + pinctrl_gpio_bl_on: gpioblongrp { fsl,pins = < MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 >; }; - pinctrl_gpio_keys: gpiokeys { + pinctrl_gpio_keys: gpiokeysgrp { fsl,pins = < MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 >; @@ -856,15 +857,15 @@ MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 pinctrl_i2c2: i2c2grp { fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 >; }; pinctrl_i2c2_gpio: i2c2gpiogrp { fsl,pins = < - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 >; }; @@ -896,8 +897,8 @@ MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1 MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1 MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1 /* Disable PWM pins on camera interface */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40 + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 >; }; @@ -937,14 +938,14 @@ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x03030 /* SODIMM 99 */ >; }; - pinctrl_mic_gnd: gpiomicgnd { + pinctrl_mic_gnd: micgndgrp { fsl,pins = < /* Controls Mic GND, PU or '1' pull Mic GND to GND */ MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 >; }; - pinctrl_mmc_cd: gpiommccd { + pinctrl_mmc_cd: mmccdgrp { fsl,pins = < MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 >; @@ -958,15 +959,15 @@ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 pinctrl_pwm2: pwm2grp { fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x00040 + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 >; }; pinctrl_pwm3: pwm3grp { fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x00040 + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 >; }; @@ -983,13 +984,6 @@ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 >; }; - pinctrl_usbh_oc_1: usbhoc1grp { - fsl,pins = < - /* USBH_OC */ - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 - >; - }; - pinctrl_spdif: spdifgrp { fsl,pins = < MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 @@ -1032,9 +1026,9 @@ MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 pinctrl_uart2_dte: uart2dtegrp { fsl,pins = < MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 >; }; @@ -1049,20 +1043,27 @@ pinctrl_usbc_det: usbcdetgrp { fsl,pins = < /* USBC_DET */ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* USBC_DET_EN */ - MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 /* USBC_DET_OVERWRITE */ MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 + /* USBC_DET_EN */ + MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x0f058 >; }; - pinctrl_usbc_id_1: usbc_id-1 { + pinctrl_usbc_id_1: usbcid1grp { fsl,pins = < /* USBC_ID */ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 >; }; + pinctrl_usbh_oc_1: usbhoc1grp { + fsl,pins = < + /* USBH_OC */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 @@ -1074,7 +1075,7 @@ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 @@ -1085,7 +1086,7 @@ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 @@ -1134,13 +1135,93 @@ MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 >; }; + /* ADDRESS[16:18] [25] used as GPIO */ + pinctrl_weim_gpio_1: weimgpio1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + /* ADDRESS[19:24] used as GPIO */ + pinctrl_weim_gpio_2: weimgpio2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + >; + }; + + /* DATA[16:31] used as GPIO */ + pinctrl_weim_gpio_3: weimgpio3grp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 + >; + }; + + /* DQM[0:3] used as GPIO */ + pinctrl_weim_gpio_4: weimgpio4grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 + >; + }; + + /* RDY used as GPIO */ + pinctrl_weim_gpio_5: weimgpio5grp { + fsl,pins = < + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 + >; + }; + + /* ADDRESS[16] DATA[30] used as GPIO */ + pinctrl_weim_gpio_6: weimgpio6grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_weim_npwe: weimnpwegrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 + >; + }; + pinctrl_weim_sram: weimsramgrp { fsl,pins = < - MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 - MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 /* Data */ - MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 - MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0 @@ -1155,114 +1236,35 @@ MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0 /* Address */ - MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 - MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 - MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 - MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 - MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 - MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 - MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 - MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 - MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 - MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 - MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 - MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 - MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 - MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 - MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 + MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 + MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 + MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 + MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 + MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 + MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 + MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 + MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 + MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 + MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 + MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 + MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 + MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 + MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 + MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 + /* Ctrl */ + MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 + MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 >; }; - pinctrl_weim_rdnwr: weimrdnwr { + pinctrl_weim_rdnwr: weimrdnwrgrp { fsl,pins = < - MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x130b0 - >; - }; - - pinctrl_weim_npwe: weimnpwe { - fsl,pins = < - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x0040 - MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x130b0 - >; - }; - - /* ADDRESS[16:18] [25] used as GPIO */ - pinctrl_weim_gpio_1: weimgpio-1 { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - >; - }; - - /* ADDRESS[19:24] used as GPIO */ - pinctrl_weim_gpio_2: weimgpio-2 { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 - MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 - MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b0 - MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b0 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 - MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b0 - MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - >; - }; - - /* DATA[16:31] used as GPIO */ - pinctrl_weim_gpio_3: weimgpio-3 { - fsl,pins = < - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 - MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 - MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b0 - MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 - MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x1b0b0 - MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b0 - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - >; - }; - - /* DQM[0:3] used as GPIO */ - pinctrl_weim_gpio_4: weimgpio-4 { - fsl,pins = < - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 - MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - >; - }; - - /* RDY used as GPIO */ - pinctrl_weim_gpio_5: weimgpio-5 { - fsl,pins = < - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 - >; - }; - - /* ADDRESS[16] DATA[30] used as GPIO */ - pinctrl_weim_gpio_6: weimgpio-6 { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 + MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x0040 >; }; }; From 6cc75a081d757857a4803c1139c08837ef535c67 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:31 +0200 Subject: [PATCH 26/77] ARM: dts: imx6dl-colibri: Add usdhc1 sleep pin configuration The Toradex board Iris V2 has a SD-card slot with switchable power. Add a pinctrl sleep used when the card power is off to avoid backfeeding to the card and add the "sleep" pinctrl to the usdhc1 controller. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 1c3c34bbfe98..c383e0e4110c 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -680,10 +680,11 @@ &usdhc1 { bus-width = <4>; no-1-8-v; disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; + pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>; vmmc-supply = <®_module_3v3>; vqmmc-supply = <&vgen3_reg>; status = "disabled"; @@ -951,6 +952,12 @@ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 >; }; + pinctrl_mmc_cd_sleep: mmccdslpgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0 + >; + }; + pinctrl_pwm1: pwm1grp { fsl,pins = < MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 @@ -1097,6 +1104,18 @@ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 >; }; + /* avoid backfeeding with removed card power */ + pinctrl_usdhc1_sleep: usdhc1sleepgrp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 From 1b6e37fe919fe5174ed0f49b4bd51dd2c663a025 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:32 +0200 Subject: [PATCH 27/77] ARM: dts: imx6dl-colibri: Add support for Toradex Iris carrier boards Add support for Toradex Iris, small form-factor Pico-ITX Colibri Arm Computer Module family Carrier Board. Additional details available at https://www.toradex.com/products/carrier-board/iris-carrier-board Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts | 46 ++++++ arch/arm/boot/dts/imx6dl-colibri-iris.dts | 152 +++++++++++++++++++ 3 files changed, 200 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts create mode 100644 arch/arm/boot/dts/imx6dl-colibri-iris.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ae3cac8e653b..cb4cf5453a9f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -459,6 +459,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ imx6dl-colibri-eval-v3.dtb \ + imx6dl-colibri-iris.dtb \ + imx6dl-colibri-iris-v2.dtb \ imx6dl-cubox-i.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts new file mode 100644 index 000000000000..3a6d3889760d --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6dl-colibri-iris.dts" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Iris V2 Board"; + compatible = "toradex,colibri_imx6dl-iris-v2", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; + regulator-name = "3v3_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_iris &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1>; + + pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; +}; + +/* Colibri MMC */ +&usdhc1 { + cap-power-off-card; + /* uncomment the following to enable SD card UHS mode if you have a V1.1 module */ + /* /delete-property/ no-1-8-v; */ + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris.dts b/arch/arm/boot/dts/imx6dl-colibri-iris.dts new file mode 100644 index 000000000000..cf77d894f6d7 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-iris.dts @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include +#include +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Iris Board"; + compatible = "toradex,colibri_imx6dl-iris", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + aliases { + i2c0 = &i2c2; + i2c1 = &i2c3; + }; + + aliases { + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* Colibri SSP */ +&ecspi4 { + status = "okay"; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_forceoff &pinctrl_uart23_forceoff>; + + /* + * uart-a-on-x13-enable turns the UART transceiver for UART_A on. If one + * wants to turn the transceiver off, that property has to be deleted + * and the gpio handled in userspace. + * The same applies to uart-b-c-on-x14-enable where the UART_B and + * UART_C transceiver is turned on. + */ + uart-a-on-x13-enable-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; /* SODIMM 102 */ + output-high; + }; + + uart-b-c-on-x14-enable-hog { + gpio-hog; + gpios = <8 GPIO_ACTIVE_HIGH>; /* SODIMM 104 */ + output-high; + }; +}; + +/* + * Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) + */ +&i2c3 { + status = "okay"; + + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_gpio_iris + &pinctrl_usbh_oc_1 + &pinctrl_usbc_id_1 + >; + + pinctrl_gpio_iris: gpioirisgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + >; + }; + + pinctrl_uart1_forceoff: uart1forceoffgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + >; + }; + + pinctrl_uart23_forceoff: uart23forceoffgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + >; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +/* Colibri MMC */ +&usdhc1 { + status = "okay"; +}; From e66f62acc42d8f7a938b6f92e1feb065f2bb63cb Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 11 Apr 2022 17:22:33 +0200 Subject: [PATCH 28/77] ARM: dts: imx6dl-colibri: Add support for Toradex Aster carrier board Add support for Toradex Aster, small form-factor with header compatible with Arduino Uno and Raspberry Pi (RPi) maker boards. Additional detail available at https://www.toradex.com/products/carrier-boards/aster-carrier-board Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-colibri-aster.dts | 113 +++++++++++++++++++++ 2 files changed, 114 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-colibri-aster.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index cb4cf5453a9f..f0e5fc7e5274 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -458,6 +458,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos_7.dtb \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ + imx6dl-colibri-aster.dtb \ imx6dl-colibri-eval-v3.dtb \ imx6dl-colibri-iris.dtb \ imx6dl-colibri-iris-v2.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-colibri-aster.dts b/arch/arm/boot/dts/imx6dl-colibri-aster.dts new file mode 100644 index 000000000000..74e8a6cd8bed --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-aster.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include +#include +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Aster Board"; + compatible = "toradex,colibri_imx6dl-aster", "toradex,colibri_imx6dl", + "fsl,imx6dl"; + + aliases { + i2c0 = &i2c2; + i2c1 = &i2c3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* Colibri SSP */ +&ecspi4 { + cs-gpios = < + &gpio5 2 GPIO_ACTIVE_HIGH + &gpio5 4 GPIO_ACTIVE_HIGH + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4 &pinctrl_csi_gpio_2>; + status = "okay"; +}; + +/* Colibri I2C: I2C3_SDA/SCL on SODIMM 194/196 */ +&i2c3 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_csi_gpio_1 + &pinctrl_gpio_2 + &pinctrl_gpio_aster + &pinctrl_usbh_oc_1 + &pinctrl_usbc_id_1 + &pinctrl_weim_gpio_5 + >; + + pinctrl_gpio_aster: gpioaster { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +/* Colibri MMC */ +&usdhc1 { + status = "okay"; +}; From 17efcc33e4f5fa3ffd62f6e5ce830106484817c0 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:08 +0200 Subject: [PATCH 29/77] ARM: dts: imx6qdl-vicut1.dtsi: remove TiWi module Only the first prototypes had a TiWi module. There is no publicly available hardware where this module is fitted and there are no plan to produce any. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 51 --------------------------- 1 file changed, 51 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index ec39008c0950..fe2685642bf1 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -144,18 +144,6 @@ reg_otg_vbus: regulator-otg-vbus { enable-active-high; }; - reg_wifi: regulator-wifi { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_npd>; - regulator-name = "wifi"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <70000>; - }; - sound { compatible = "simple-audio-card"; simple-audio-card,name = "prti6q-sgtl5000"; @@ -530,26 +518,6 @@ &usdhc1 { status = "okay"; }; -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_wifi>; - non-removable; - cap-power-off-card; - keep-power-in-suspend; - no-1-8-v; - no-mmc; - no-sd; - status = "okay"; - - wifi { - compatible = "ti,wl1271"; - interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>; - ref-clock-frequency = "38400000"; - tcxo-clock-frequency = "19200000"; - }; -}; - &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -808,19 +776,6 @@ MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 >; }; - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - /* WL12xx IRQ */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x10880 - >; - }; - pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 @@ -836,10 +791,4 @@ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 >; }; - - pinctrl_wifi_npd: wifinpdgrp { - fsl,pins = < - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b8b0 - >; - }; }; From 092073263226b3f417597bb13145042c60b1ab93 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:09 +0200 Subject: [PATCH 30/77] ARM: dts: imx6qdl-vicut1.dtsi: Put nON_SWITCH in own pinctrl grp Unify nON_SWITCH pinctrl configuration with imx6dl-victgo.dts. This patch is a preparation to reduce duplicated code between vicut1 and victgo. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index fe2685642bf1..32f7eb379e60 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -72,6 +72,8 @@ counter-2 { gpio-keys { compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; autorepeat; power { @@ -621,6 +623,13 @@ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 >; }; + pinctrl_gpiokeys: gpiokeygrp { + fsl,pins = < + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + >; + }; + pinctrl_hog: hoggrp { fsl,pins = < /* ITU656_nRESET */ @@ -631,8 +640,6 @@ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* CAM_nDETECT */ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* nON_SWITCH */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 /* ISB_IN1 */ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 /* ISB_nIN2 */ From 2a0a0c5dc0764b00154f6784883ea60c69e5c275 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:10 +0200 Subject: [PATCH 31/77] ARM: dts: imx6qdl-vicut1.dtsi: Remove PCIe Only the very first prototypes had PCIe and there are no plant to add it in the future. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index 32f7eb379e60..b126ef4d5255 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -296,8 +296,8 @@ &gpio4 { &gpio5 { gpio-line-names = - "", "", "", "", "", "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_W_DIS", - "PCIE_RESET", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", "I2S_BITCLK", "I2S_DOUT", "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", @@ -439,10 +439,6 @@ lvds0_out: endpoint { }; }; -&pcie { - status = "okay"; -}; - &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; From f6d8a739b35758d6958d51e39dc760f49629047e Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:11 +0200 Subject: [PATCH 32/77] ARM: dts: imx6qdl-vicut1/victgo: Remove UART2 Only first prototype had UART2 and there are no plans to add it in the future. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 13 ------------- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 15 --------------- 2 files changed, 28 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 7dd7fb165432..9cf4df3eaeb0 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -616,12 +616,6 @@ &uart1 { status = "okay"; }; -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; @@ -905,13 +899,6 @@ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 >; }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - /* YaCO Touchscreen UART */ pinctrl_uart3: uart3grp { fsl,pins = < diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index b126ef4d5255..ea474aa93485 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -463,12 +463,6 @@ &uart1 { status = "okay"; }; -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; @@ -728,15 +722,6 @@ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 >; }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 - >; - }; - /* YaCO Touchscreen UART */ pinctrl_uart3: uart3grp { fsl,pins = < From 1a0e71889dea95fa73a5cfc1fb505952b1f099f0 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:12 +0200 Subject: [PATCH 33/77] ARM: dts: imx6qdl-vicut1.dtsi: Fix LED names The names should be consistent with the names in imx6dl-victgo.dts This patch is preparation to unify vicut1 and victgo DTs. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index ea474aa93485..b7a705b39178 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -90,21 +90,21 @@ leds { pinctrl-0 = <&pinctrl_leds>; led-0 { - label = "LED_DI0_DEBUG_0"; + label = "debug0"; function = LED_FUNCTION_HEARTBEAT; gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; led-1 { - label = "LED_DI0_DEBUG_1"; + label = "debug1"; function = LED_FUNCTION_DISK; gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "disk-activity"; }; led-2 { - label = "POWER_LED"; + label = "power_led"; function = LED_FUNCTION_POWER; gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; default-state = "on"; From c061895eb0248d3d2c250930a2c69353d4ba94c2 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:13 +0200 Subject: [PATCH 34/77] ARM: dts: imx6qdl-vicut1.dtsi: Fix debug LED gpio pins While there are LEDs connected on some variants on GPIO4 pins 16 and 17, those are not the debug LEDs that should be visible to user-space. It should be the same as in imx6dl-victgo.dtsi. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index b7a705b39178..a5f962f1028b 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -92,14 +92,14 @@ leds { led-0 { label = "debug0"; function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; led-1 { label = "debug1"; function = LED_FUNCTION_DISK; - gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "disk-activity"; }; From 4e6ab6837e326c975443168ac1aaf2b6132caf5b Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:14 +0200 Subject: [PATCH 35/77] ARM: dts: imx6qdl-vicut1.dtsi: Update GPIO line names Add some missing names and remove names to pins that have never been used and/or are not present on any hardware. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index a5f962f1028b..a93e7f8302aa 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -257,12 +257,10 @@ &gpio1 { gpio-line-names = "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", "CAM2_MIRROR", "", "", "SMBALERT", - "DEBUG_0", "DEBUG_1", "SDIO_SCK", "SDIO_CMD", "SDIO_D3", - "SDIO_D2", "SDIO_D1", "SDIO_D0", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "", "", - "", "ETH_RESET", "WIFI_PD", "WIFI_BT_RST", "ETH_INT", "", - "WL_IRQ", "ETH_MDC"; + "SD1_DATA3", "ETH_MDIO", "", + "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; }; &gpio2 { @@ -270,8 +268,8 @@ &gpio2 { "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", "", "LED_PWM", "", "", "", "", "", "", - "", "", "", "", "", "", "", "ON_SWITCH", - "POWER_LED", "", "ECSPI2_SS0", "", "", "", "", ""; + "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH", + "POWER_LED", "", "", "", "", "", "", ""; }; &gpio3 { @@ -280,7 +278,8 @@ &gpio3 { "", "", "", "", "", "", "", "", "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", - "", "", "", "", "", "", "", ""; + "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", + "YACO_RESET"; }; &gpio4 { @@ -288,8 +287,8 @@ &gpio4 { "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX", - "LED_DI0_DEBUG_0", "LED_DI0_DEBUG_1", "", "", "", "ON1_CTRL", - "ON2_CTRL", "HITCH_IN_OUT", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", "ISB_LED"; }; From 1d039a1ae2c7ccfd269ebfdb11c10085fc394aff Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:15 +0200 Subject: [PATCH 36/77] ARM: dts: imx6qdl-vicut1.dtsi: Remove conflicting pinctrl entry The function of DISP0_DAT9 is dependent on hardware revision of two particular variants. This setting should be done by the bootloader anyway, and is not needed in the kernel, so remove it from the DT. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index a93e7f8302aa..6c943ca950f4 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -655,10 +655,6 @@ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 /* DIP1_FB */ MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - - /* New in UT2: FIXME: ISB PWM should start off, PD */ - /* ISB_LED_PWM */ - MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x130b0 >; }; From 4eef8cb7dd41a47da94191fc1d191167be07a077 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:16 +0200 Subject: [PATCH 37/77] ARM: dts: imx6q-vicut1.dts: remove sata node Only the prototype had the SATA interface. There are no existing products with SATA interface and no plans to add any. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-vicut1.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-vicut1.dts b/arch/arm/boot/dts/imx6q-vicut1.dts index 0a4e251be162..e6c5d3cb48d7 100644 --- a/arch/arm/boot/dts/imx6q-vicut1.dts +++ b/arch/arm/boot/dts/imx6q-vicut1.dts @@ -11,7 +11,3 @@ / { model = "Kverneland UT1Q Board"; compatible = "kvg,vicut1q", "fsl,imx6q"; }; - -&sata { - status = "okay"; -}; From deebb9ba3a64acb8dabcedcf2845f86b48f0e7b4 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:17 +0200 Subject: [PATCH 38/77] ARM: dts: imx6dl-victgo.dts: update gpio names Following changes was made: - Add MDIO signal names - Add missing ISB_IN2 name. Also correct ISB_nIN1. These two signals were used together in older HW revisions. Later ISB_IN2 was removed. Software should still be able to use both. - Add missing CAN1 and UART line names - Add missing ON1/2_CTRL line names - fix CPU_* line names. The real signal names are without the CPU_ prefix, like on imx6qdl-vicut1.dtsi - Fix ETH_INT signal name Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 41 ++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 9cf4df3eaeb0..7fc5bb499cbc 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -408,8 +408,8 @@ &gpio1 { "CAM2_MIRROR", "", "", "SMBALERT", "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "", "", - "", "", "", "", "", "", "", ""; + "SD1_DATA3", "ETH_MDIO", "", + "", "", "", "", "", "", "", "ETH_MDC"; }; &gpio2 { @@ -417,7 +417,7 @@ &gpio2 { "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", "", "LED_PWM", "", "", "", "", "", "", - "", "", "", "", "", "", "ISB_IN1", "ON_SWITCH", + "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH", "POWER_LED", "", "", "", "", "", "", ""; }; @@ -426,18 +426,20 @@ &gpio3 { "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", - "CPU_ON1_FB", "USB_EXT1_OC", "USB_EXT1_PWR", "YACO_IRQ", + "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", "YACO_RESET"; }; &gpio4 { gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "CAN1_SR", "CAN2_SR", "CAN2_TX", "CAN2_RX", - "", "", "DIP1_FB", "", "VCAM_EN", "", "", "", - "CPU_LIGHT_ON", "", "ETH_RESET", "CPU_CONTACT_IN", "BL_EN", - "BL_PWM", "ETH_INTRP", "ISB_LED"; + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", + "CAN2_SR", "CAN2_TX", "CAN2_RX", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", + "LIGHT_ON", "", "ETH_RESET", "CONTACT_IN", "BL_EN", + "BL_PWM", "ETH_INT", "ISB_LED"; }; &gpio5 { @@ -445,11 +447,30 @@ &gpio5 { "", "", "", "", "", "", "", "", "TSC_PENIRQ", "TSC_BUSY", "ECSPI2_MOSI", "ECSPI2_MISO", "ECSPI2_SS0", "ECSPI2_SCLK", "", "", - "", "", "", "", "", "", "", "", + "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", + "I2S_BITCLK", "I2S_DOUT", "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; }; +&gpio6 { + gpio-line-names = + "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", + "ITU656_D6", "ITU656_D7", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio7 { + gpio-line-names = + "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0", + "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3", + "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "", + "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; From d380984764ad5c7c12d35f687aef843ea10f373c Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:18 +0200 Subject: [PATCH 39/77] ARM: dts: imx6dl-victgo.dts: Factor out common parts to imx6qdl-victgo.dtsi These parts are common to imx6qdl-vicut1.dtsi. This patch is preparation to unify victgo and vicut1 DTs. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 649 +------------------------ arch/arm/boot/dts/imx6qdl-victgo.dtsi | 658 ++++++++++++++++++++++++++ 2 files changed, 659 insertions(+), 648 deletions(-) create mode 100644 arch/arm/boot/dts/imx6qdl-victgo.dtsi diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 7fc5bb499cbc..6d61e87405f4 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -5,76 +5,13 @@ */ /dts-v1/; -#include -#include -#include -#include -#include -#include #include "imx6dl.dtsi" +#include "imx6qdl-victgo.dtsi" / { model = "Kverneland TGO"; compatible = "kvg,victgo", "fsl,imx6dl"; - chosen { - stdout-path = &uart4; - }; - - backlight_lcd: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm1 0 5000000 0>; - brightness-levels = <0 16 64 255>; - num-interpolated-steps = <16>; - default-brightness-level = <48>; - power-supply = <®_3v3>; - enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - }; - - backlight_led: backlight_led { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000 0>; - brightness-levels = <0 16 64 255>; - num-interpolated-steps = <16>; - default-brightness-level = <48>; - power-supply = <®_3v3>; - }; - - connector { - compatible = "composite-video-connector"; - label = "Composite0"; - sdtv-standards = ; - - port { - comp0_out: endpoint { - remote-endpoint = <&tvp5150_comp0_in>; - }; - }; - }; - - counter-0 { - compatible = "interrupt-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_counter0>; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - }; - - counter-1 { - compatible = "interrupt-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_counter1>; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - - counter-2 { - compatible = "interrupt-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_counter2>; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - }; - gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -101,33 +38,6 @@ iio-hwmon { io-channels = <&vdiv_vaccu>, <&vdiv_hitch_pos>; }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - label = "debug0"; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - label = "debug1"; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - - led-2 { - label = "power_led"; - function = LED_FUNCTION_POWER; - gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - panel { compatible = "lg,lb070wv8"; backlight = <&backlight_lcd>; @@ -146,29 +56,6 @@ clk50m_phy: phy-clock { clock-frequency = <50000000>; }; - reg_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_otg_vbus: regulator-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - rotary-encoder { compatible = "rotary-encoder"; pinctrl-0 = <&pinctrl_rotary_ch>; @@ -181,33 +68,6 @@ rotary-encoder { wakeup-source; }; - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "prti6q-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Line", "Line In Jack", - "Headphone", "Headphone Jack", - "Speaker", "External Speaker"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "External Speaker", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&ssi1>; - system-clock-frequency = <0>; - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - bitclock-master; - frame-master; - }; - }; - thermal-zones { chassis-thermal { polling-delay = <20000>; @@ -275,63 +135,6 @@ vdiv_hitch_pos: voltage-divider-hitch-pos { }; }; -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN 0 - IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TFSDIR 0 - IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - mux-pins3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) - 0 IMX_AUDMUX_V2_PDCR_TXRXEN - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - termination-ohms = <150>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - &ecspi2 { cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -412,25 +215,6 @@ &gpio1 { "", "", "", "", "", "", "", "ETH_MDC"; }; -&gpio2 { - gpio-line-names = - "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", - "", "LED_PWM", "", "", "", - "", "", "", - "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH", - "POWER_LED", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", - "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", - "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", - "YACO_RESET"; -}; - &gpio4 { gpio-line-names = "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", @@ -462,55 +246,7 @@ &gpio6 { "", "", "", "", "", "", "", ""; }; -&gpio7 { - gpio-line-names = - "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0", - "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3", - "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "", - "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - &i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: audio-codec@a { - compatible = "fsl,sgtl5000"; - reg = <0xa>; - #sound-dai-cells = <0>; - clocks = <&clks 201>; - VDDA-supply = <®_3v3>; - VDDIO-supply = <®_3v3>; - VDDD-supply = <®_1v8>; - }; - - video-decoder@5c { - compatible = "ti,tvp5150"; - reg = <0x5c>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tvp5150_comp0_in: endpoint { - remote-endpoint = <&comp0_out>; - }; - }; - - /* Output port 2 is video output pad */ - port@2 { - reg = <2>; - - tvp5151_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - }; - }; - }; - keypad@70 { compatible = "holtek,ht16k33"; pinctrl-names = "default"; @@ -534,236 +270,9 @@ MATRIX_KEY(5, 1, KEY_F3) MATRIX_KEY(6, 1, KEY_F1) >; }; - - /* additional i2c devices are added automatically by the boot loader */ -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - channel@4 { - reg = <4>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@5 { - reg = <5>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@6 { - reg = <6>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@7 { - reg = <7>; - ti,gain = <3>; - ti,datarate = <3>; - }; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - tsens0: temperature-sensor@70 { - compatible = "ti,tmp103"; - reg = <0x70>; - #thermal-sensor-cells = <0>; - }; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; - status = "okay"; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&ssi1 { - #sound-dai-cells = <0>; - fsl,mode = "ac97-slave"; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - phy_type = "utmi"; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - phy_type = "utmi"; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - no-1-8-v; - disable-wp; - cap-sd-highspeed; - no-mmc; - no-sdio; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sd; - no-sdio; - status = "okay"; }; &iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 - /* CAN1_SR */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 - /* CAN1_TERM */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 - /* CAN2_SR */ - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 - >; - }; - - pinctrl_counter0: counter0grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 - >; - }; - - pinctrl_counter1: counter1grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 - >; - }; - - pinctrl_counter2: counter2grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* CS */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - pinctrl_ecspi2: ecspi2grp { fsl,pins = < MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 @@ -802,102 +311,12 @@ MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 >; }; - pinctrl_hog: hoggrp { - fsl,pins = < - /* ITU656_nRESET */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - /* CAM1_MIRROR */ - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 - /* CAM2_MIRROR */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 - /* CAM_nDETECT */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* ISB_IN1 */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 - /* ISB_nIN2 */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 - /* WARN_LIGHT */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 - /* ON2_FB */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 - /* YACO_nIRQ */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 - /* YACO_BOOT0 */ - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 - /* YACO_nRESET */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 - /* FORCE_ON1 */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - /* AUDIO_nRESET */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 - /* ITU656_nPDN */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 - - /* New in HW revision 1 */ - /* ON1_FB */ - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 - /* DIP1_FB */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - >; - }; - pinctrl_keypad: keypadgrp { fsl,pins = < MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 >; }; - pinctrl_leds: ledsgrp { - fsl,pins = < - /* DEBUG0 */ - MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 - /* DEBUG1 */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 - /* POWER_LED */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 - >; - }; - pinctrl_rotary_ch: rotarychgrp { fsl,pins = < MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 @@ -911,70 +330,4 @@ MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b0 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 >; }; - - /* YaCO AUX Uart */ - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - /* YaCO Touchscreen UART */ - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6qdl-victgo.dtsi b/arch/arm/boot/dts/imx6qdl-victgo.dtsi new file mode 100644 index 000000000000..386e2ca39424 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-victgo.dtsi @@ -0,0 +1,658 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +#include +#include +#include +#include +#include +#include + +/ { + chosen { + stdout-path = &uart4; + }; + + backlight_lcd: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <48>; + power-supply = <®_3v3>; + enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + }; + + backlight_led: backlight_led { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000 0>; + brightness-levels = <0 16 64 255>; + num-interpolated-steps = <16>; + default-brightness-level = <48>; + power-supply = <®_3v3>; + }; + + connector { + compatible = "composite-video-connector"; + label = "Composite0"; + sdtv-standards = ; + + port { + comp0_out: endpoint { + remote-endpoint = <&tvp5150_comp0_in>; + }; + }; + }; + + counter-0 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter0>; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + }; + + counter-1 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter1>; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + counter-2 { + compatible = "interrupt-counter"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_counter2>; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + label = "debug0"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "debug1"; + function = LED_FUNCTION_DISK; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + + led-2 { + label = "power_led"; + function = LED_FUNCTION_POWER; + gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; /* Do NOT call fsl_ssi_set_dai_sysclk! */ + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + bitclock-master; + frame-master; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + termination-ohms = <150>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&gpio2 { + gpio-line-names = + "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", + "", "LED_PWM", "", "", "", + "", "", "", + "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH", + "POWER_LED", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", + "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", + "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", + "YACO_RESET"; +}; + +&gpio7 { + gpio-line-names = + "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0", + "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3", + "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "", + "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; + + video-decoder@5c { + compatible = "ti,tvp5150"; + reg = <0x5c>; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tvp5150_comp0_in: endpoint { + remote-endpoint = <&comp0_out>; + }; + }; + + /* Output port 2 is video output pad */ + port@2 { + reg = <2>; + + tvp5151_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + }; + }; + }; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@5 { + reg = <5>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@6 { + reg = <6>; + ti,gain = <3>; + ti,datarate = <3>; + }; + + channel@7 { + reg = <7>; + ti,gain = <3>; + ti,datarate = <3>; + }; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + tsens0: temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + #thermal-sensor-cells = <0>; + }; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; + status = "okay"; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + /* SGTL5000 sys_mclk */ + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 + /* CAN1_TERM */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 + /* CAN2_SR */ + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 + >; + }; + + pinctrl_counter0: counter0grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 + >; + }; + + pinctrl_counter1: counter1grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 + >; + }; + + pinctrl_counter2: counter2grp { + fsl,pins = < + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* ITU656_nRESET */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 + /* CAM1_MIRROR */ + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 + /* CAM2_MIRROR */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 + /* CAM_nDETECT */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + /* ISB_IN1 */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 + /* ISB_nIN2 */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + /* WARN_LIGHT */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 + /* ON2_FB */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 + /* YACO_nIRQ */ + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 + /* YACO_BOOT0 */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 + /* YACO_nRESET */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 + /* FORCE_ON1 */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + /* AUDIO_nRESET */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 + /* ITU656_nPDN */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 + + /* New in HW revision 1 */ + /* ON1_FB */ + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 + /* DIP1_FB */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_csi0: ipu1csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + /* DEBUG0 */ + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 + /* DEBUG1 */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 + /* POWER_LED */ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 + >; + }; + + /* YaCO AUX Uart */ + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + /* YaCO Touchscreen UART */ + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; +}; From 217390ad7423d65591745ec4957aaa30b62c3a7b Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:19 +0200 Subject: [PATCH 40/77] ARM: dts: imx6qdl-vicut1.dtsi: Move some node out to DTS files This commit will finally make this file identical to imx6qdl-victgo.dtsi. All nodes that are removed here are added as-is to the DTS files that include this file. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-vicut1.dts | 122 ++++++++++++++++++++++++++ arch/arm/boot/dts/imx6q-vicut1.dts | 122 ++++++++++++++++++++++++++ arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 120 ------------------------- arch/arm/boot/dts/imx6qp-vicutp.dts | 122 ++++++++++++++++++++++++++ 4 files changed, 366 insertions(+), 120 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-vicut1.dts b/arch/arm/boot/dts/imx6dl-vicut1.dts index 174fd913bf96..c6a904bbed01 100644 --- a/arch/arm/boot/dts/imx6dl-vicut1.dts +++ b/arch/arm/boot/dts/imx6dl-vicut1.dts @@ -10,4 +10,126 @@ / { model = "Kverneland UT1 Board"; compatible = "kvg,vicut1", "fsl,imx6dl"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + autorepeat; + + power { + label = "Power Button"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + panel { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031RNX PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", + "CAM2_MIRROR", "", "", "SMBALERT", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", + "SD1_DATA3", "ETH_MDIO", "", + "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", + "CAN2_SR", "CAN2_TX", "CAN2_RX", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", + "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", + "ISB_LED"; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", + "I2S_BITCLK", "I2S_DOUT", + "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", + "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; +}; + +&gpio6 { + gpio-line-names = + "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", + "ITU656_D6", "ITU656_D7", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", + "RGMII_TD3", + "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", + "RGMII_RD2", "RGMII_RD3", "", ""; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; + + pinctrl_gpiokeys: gpiokeygrp { + fsl,pins = < + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + >; + }; }; diff --git a/arch/arm/boot/dts/imx6q-vicut1.dts b/arch/arm/boot/dts/imx6q-vicut1.dts index e6c5d3cb48d7..8b228d5fc4a3 100644 --- a/arch/arm/boot/dts/imx6q-vicut1.dts +++ b/arch/arm/boot/dts/imx6q-vicut1.dts @@ -10,4 +10,126 @@ / { model = "Kverneland UT1Q Board"; compatible = "kvg,vicut1q", "fsl,imx6q"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + autorepeat; + + power { + label = "Power Button"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + panel { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031RNX PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", + "CAM2_MIRROR", "", "", "SMBALERT", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", + "SD1_DATA3", "ETH_MDIO", "", + "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", + "CAN2_SR", "CAN2_TX", "CAN2_RX", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", + "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", + "ISB_LED"; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", + "I2S_BITCLK", "I2S_DOUT", + "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", + "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; +}; + +&gpio6 { + gpio-line-names = + "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", + "ITU656_D6", "ITU656_D7", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", + "RGMII_TD3", + "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", + "RGMII_RD2", "RGMII_RD3", "", ""; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; + + pinctrl_gpiokeys: gpiokeygrp { + fsl,pins = < + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + >; + }; }; diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index 6c943ca950f4..2a86136a04e8 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -70,20 +70,6 @@ counter-2 { gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; }; - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - autorepeat; - - power { - label = "Power Button"; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -111,18 +97,6 @@ led-2 { }; }; - panel { - compatible = "kyo,tcg121xglp"; - backlight = <&backlight_lcd>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - reg_1v8: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "1v8"; @@ -231,38 +205,6 @@ flash@0 { }; }; -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&rgmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ9031RNX PHY */ - rgmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", - "CAM2_MIRROR", "", "", "SMBALERT", - "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", - "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "ETH_MDIO", "", - "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; -}; - &gpio2 { gpio-line-names = "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", @@ -282,38 +224,6 @@ &gpio3 { "YACO_RESET"; }; -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", - "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", - "CAN2_SR", "CAN2_TX", "CAN2_RX", - "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", - "HITCH_IN_OUT", - "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", - "ISB_LED"; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", - "I2S_BITCLK", "I2S_DOUT", - "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", - "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; -}; - -&gpio6 { - gpio-line-names = - "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", - "ITU656_D6", "ITU656_D7", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", - "RGMII_TD3", - "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", - "RGMII_RD2", "RGMII_RD3", "", ""; -}; - &gpio7 { gpio-line-names = "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0", @@ -589,36 +499,6 @@ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 >; }; - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 - /* Phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 - >; - }; - - pinctrl_gpiokeys: gpiokeygrp { - fsl,pins = < - /* nON_SWITCH */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 - >; - }; - pinctrl_hog: hoggrp { fsl,pins = < /* ITU656_nRESET */ diff --git a/arch/arm/boot/dts/imx6qp-vicutp.dts b/arch/arm/boot/dts/imx6qp-vicutp.dts index 7bad7ca6b12e..31c748e9d92f 100644 --- a/arch/arm/boot/dts/imx6qp-vicutp.dts +++ b/arch/arm/boot/dts/imx6qp-vicutp.dts @@ -10,4 +10,126 @@ / { model = "Kverneland UT1P Board"; compatible = "kvg,vicutp", "fsl,imx6qp"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + autorepeat; + + power { + label = "Power Button"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + panel { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031RNX PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", + "CAM2_MIRROR", "", "", "SMBALERT", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", + "SD1_DATA3", "ETH_MDIO", "", + "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", + "CAN2_SR", "CAN2_TX", "CAN2_RX", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", + "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", + "ISB_LED"; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", + "I2S_BITCLK", "I2S_DOUT", + "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", + "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; +}; + +&gpio6 { + gpio-line-names = + "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", + "ITU656_D6", "ITU656_D7", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", + "RGMII_TD3", + "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", + "RGMII_RD2", "RGMII_RD3", "", ""; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; + + pinctrl_gpiokeys: gpiokeygrp { + fsl,pins = < + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + >; + }; }; From 901e8f8f8b87a56e6bb6b974063e7bcb4d272e38 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:20 +0200 Subject: [PATCH 41/77] ARM: dts: Remove imx6qdl-victgo.dtsi The common base is now identical to imx6qdl-vicut1.dtsi, so we can remove one of both. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 2 +- arch/arm/boot/dts/imx6qdl-victgo.dtsi | 658 -------------------------- 2 files changed, 1 insertion(+), 659 deletions(-) delete mode 100644 arch/arm/boot/dts/imx6qdl-victgo.dtsi diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 6d61e87405f4..4f6100b2ce2d 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "imx6dl.dtsi" -#include "imx6qdl-victgo.dtsi" +#include "imx6qdl-vicut1.dtsi" / { model = "Kverneland TGO"; diff --git a/arch/arm/boot/dts/imx6qdl-victgo.dtsi b/arch/arm/boot/dts/imx6qdl-victgo.dtsi deleted file mode 100644 index 386e2ca39424..000000000000 --- a/arch/arm/boot/dts/imx6qdl-victgo.dtsi +++ /dev/null @@ -1,658 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (c) 2016 Protonic Holland - * Copyright (c) 2020 Oleksij Rempel , Pengutronix - */ - -#include -#include -#include -#include -#include -#include - -/ { - chosen { - stdout-path = &uart4; - }; - - backlight_lcd: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm1 0 5000000 0>; - brightness-levels = <0 16 64 255>; - num-interpolated-steps = <16>; - default-brightness-level = <48>; - power-supply = <®_3v3>; - enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; - }; - - backlight_led: backlight_led { - compatible = "pwm-backlight"; - pwms = <&pwm3 0 5000000 0>; - brightness-levels = <0 16 64 255>; - num-interpolated-steps = <16>; - default-brightness-level = <48>; - power-supply = <®_3v3>; - }; - - connector { - compatible = "composite-video-connector"; - label = "Composite0"; - sdtv-standards = ; - - port { - comp0_out: endpoint { - remote-endpoint = <&tvp5150_comp0_in>; - }; - }; - }; - - counter-0 { - compatible = "interrupt-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_counter0>; - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - }; - - counter-1 { - compatible = "interrupt-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_counter1>; - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - }; - - counter-2 { - compatible = "interrupt-counter"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_counter2>; - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_leds>; - - led-0 { - label = "debug0"; - function = LED_FUNCTION_HEARTBEAT; - gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - label = "debug1"; - function = LED_FUNCTION_DISK; - gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - }; - - led-2 { - label = "power_led"; - function = LED_FUNCTION_POWER; - gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - reg_1v8: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_otg_vbus: regulator-otg-vbus { - compatible = "regulator-fixed"; - regulator-name = "otg-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "prti6q-sgtl5000"; - simple-audio-card,format = "i2s"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Line", "Line In Jack", - "Headphone", "Headphone Jack", - "Speaker", "External Speaker"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT", - "External Speaker", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&ssi1>; - system-clock-frequency = <0>; /* Do NOT call fsl_ssi_set_dai_sysclk! */ - }; - - simple-audio-card,codec { - sound-dai = <&codec>; - bitclock-master; - frame-master; - }; - }; -}; - -&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; - - mux-ssi1 { - fsl,audmux-port = <0>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN 0 - IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 - IMX_AUDMUX_V2_PTCR_TFSDIR 0 - IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) - >; - }; - - mux-pins3 { - fsl,audmux-port = <2>; - fsl,port-config = < - IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) - 0 IMX_AUDMUX_V2_PDCR_TXRXEN - >; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can1>; - termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - termination-ohms = <150>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can2>; - status = "okay"; -}; - -&clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; -}; - -&ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&gpio2 { - gpio-line-names = - "YACO_WHEEL", "YACO_RADAR", "YACO_PTO", "", "", "", "", "", - "", "LED_PWM", "", "", "", - "", "", "", - "", "", "", "", "", "ISB_IN2", "ISB_nIN1", "ON_SWITCH", - "POWER_LED", "", "", "", "", "", "", ""; -}; - -&gpio3 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "ECSPI1_SCLK", "ECSPI1_MISO", "ECSPI1_MOSI", "ECSPI1_SS1", - "CPU_ON1_FB", "USB_OTG_OC", "USB_OTG_PWR", "YACO_IRQ", - "TSS_TXD", "TSS_RXD", "", "", "", "", "YACO_BOOT0", - "YACO_RESET"; -}; - -&gpio7 { - gpio-line-names = - "EMMC_DAT5", "EMMC_DAT4", "EMMC_CMD", "EMMC_CLK", "EMMC_DAT0", - "EMMC_DAT1", "EMMC_DAT2", "EMMC_DAT3", - "EMMC_RST", "", "", "", "CAM_DETECT", "", "", "", - "", "EMMC_DAT7", "EMMC_DAT6", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - codec: audio-codec@a { - compatible = "fsl,sgtl5000"; - reg = <0xa>; - #sound-dai-cells = <0>; - clocks = <&clks 201>; - VDDA-supply = <®_3v3>; - VDDIO-supply = <®_3v3>; - VDDD-supply = <®_1v8>; - }; - - video-decoder@5c { - compatible = "ti,tvp5150"; - reg = <0x5c>; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tvp5150_comp0_in: endpoint { - remote-endpoint = <&comp0_out>; - }; - }; - - /* Output port 2 is video output pad */ - port@2 { - reg = <2>; - - tvp5151_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - }; - }; - }; - - /* additional i2c devices are added automatically by the boot loader */ -}; - -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - adc@49 { - compatible = "ti,ads1015"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - - channel@4 { - reg = <4>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@5 { - reg = <5>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@6 { - reg = <6>; - ti,gain = <3>; - ti,datarate = <3>; - }; - - channel@7 { - reg = <7>; - ti,gain = <3>; - ti,datarate = <3>; - }; - }; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - tsens0: temperature-sensor@70 { - compatible = "ti,tmp103"; - reg = <0x70>; - #thermal-sensor-cells = <0>; - }; -}; - -&ipu1_csi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu1_csi0>; - status = "okay"; -}; - -&ipu1_csi0_mux_from_parallel_sensor { - remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbh1 { - pinctrl-names = "default"; - phy_type = "utmi"; - dr_mode = "host"; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - phy_type = "utmi"; - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - no-1-8-v; - disable-wp; - cap-sd-highspeed; - no-mmc; - no-sdio; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - bus-width = <8>; - no-1-8-v; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_audmux: audmuxgrp { - fsl,pins = < - /* SGTL5000 sys_mclk */ - MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - >; - }; - - pinctrl_backlight: backlightgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0 - >; - }; - - pinctrl_can1: can1grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 - /* CAN1_SR */ - MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 - /* CAN1_TERM */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b088 - >; - }; - - pinctrl_can2: can2grp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 - /* CAN2_SR */ - MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13008 - >; - }; - - pinctrl_counter0: counter0grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000 - >; - }; - - pinctrl_counter1: counter1grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000 - >; - }; - - pinctrl_counter2: counter2grp { - fsl,pins = < - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* CS */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - /* ITU656_nRESET */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 - /* CAM1_MIRROR */ - MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x130b0 - /* CAM2_MIRROR */ - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 - /* CAM_nDETECT */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 - /* ISB_IN1 */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 - /* ISB_nIN2 */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 - /* WARN_LIGHT */ - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x100b0 - /* ON2_FB */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b0 - /* YACO_nIRQ */ - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 - /* YACO_BOOT0 */ - MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x130b0 - /* YACO_nRESET */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 - /* FORCE_ON1 */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - /* AUDIO_nRESET */ - MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1f0b0 - /* ITU656_nPDN */ - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 - - /* New in HW revision 1 */ - /* ON1_FB */ - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b0 - /* DIP1_FB */ - MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_ipu1_csi0: ipu1csi0grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 - MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 - MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 - MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 - MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 - MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 - MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 - MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 - MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 - >; - }; - - pinctrl_leds: ledsgrp { - fsl,pins = < - /* DEBUG0 */ - MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 - /* DEBUG1 */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 - /* POWER_LED */ - MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0 - >; - }; - - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0 - >; - }; - - /* YaCO AUX Uart */ - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; - - /* YaCO Touchscreen UART */ - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 - /* power enable, high active */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 - MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 - MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 - >; - }; -}; From 6d8e96fbeb07fa0ac4d248cac5174e866320ce9c Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:21 +0200 Subject: [PATCH 42/77] ARM: dts: imx6qdl-vicut1: Factor out common parts of 12inch board variants Factor out common parts of vicut1 and vicutp to reduce maintenance overhead. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-vicut1.dts | 123 +----------------- arch/arm/boot/dts/imx6q-vicut1.dts | 123 +----------------- arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi | 128 +++++++++++++++++++ arch/arm/boot/dts/imx6qp-vicutp.dts | 123 +----------------- 4 files changed, 131 insertions(+), 366 deletions(-) create mode 100644 arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi diff --git a/arch/arm/boot/dts/imx6dl-vicut1.dts b/arch/arm/boot/dts/imx6dl-vicut1.dts index c6a904bbed01..5035d303447d 100644 --- a/arch/arm/boot/dts/imx6dl-vicut1.dts +++ b/arch/arm/boot/dts/imx6dl-vicut1.dts @@ -6,130 +6,9 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-vicut1.dtsi" +#include "imx6qdl-vicut1-12inch.dtsi" / { model = "Kverneland UT1 Board"; compatible = "kvg,vicut1", "fsl,imx6dl"; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - autorepeat; - - power { - label = "Power Button"; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - panel { - compatible = "kyo,tcg121xglp"; - backlight = <&backlight_lcd>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&rgmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ9031RNX PHY */ - rgmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", - "CAM2_MIRROR", "", "", "SMBALERT", - "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", - "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "ETH_MDIO", "", - "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", - "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", - "CAN2_SR", "CAN2_TX", "CAN2_RX", - "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", - "HITCH_IN_OUT", - "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", - "ISB_LED"; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", - "I2S_BITCLK", "I2S_DOUT", - "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", - "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; -}; - -&gpio6 { - gpio-line-names = - "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", - "ITU656_D6", "ITU656_D7", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", - "RGMII_TD3", - "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", - "RGMII_RD2", "RGMII_RD3", "", ""; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 - /* Phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 - >; - }; - - pinctrl_gpiokeys: gpiokeygrp { - fsl,pins = < - /* nON_SWITCH */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6q-vicut1.dts b/arch/arm/boot/dts/imx6q-vicut1.dts index 8b228d5fc4a3..dd91aff3f9e2 100644 --- a/arch/arm/boot/dts/imx6q-vicut1.dts +++ b/arch/arm/boot/dts/imx6q-vicut1.dts @@ -6,130 +6,9 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-vicut1.dtsi" +#include "imx6qdl-vicut1-12inch.dtsi" / { model = "Kverneland UT1Q Board"; compatible = "kvg,vicut1q", "fsl,imx6q"; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - autorepeat; - - power { - label = "Power Button"; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - panel { - compatible = "kyo,tcg121xglp"; - backlight = <&backlight_lcd>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&rgmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ9031RNX PHY */ - rgmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", - "CAM2_MIRROR", "", "", "SMBALERT", - "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", - "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "ETH_MDIO", "", - "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", - "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", - "CAN2_SR", "CAN2_TX", "CAN2_RX", - "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", - "HITCH_IN_OUT", - "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", - "ISB_LED"; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", - "I2S_BITCLK", "I2S_DOUT", - "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", - "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; -}; - -&gpio6 { - gpio-line-names = - "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", - "ITU656_D6", "ITU656_D7", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", - "RGMII_TD3", - "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", - "RGMII_RD2", "RGMII_RD3", "", ""; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 - /* Phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 - >; - }; - - pinctrl_gpiokeys: gpiokeygrp { - fsl,pins = < - /* nON_SWITCH */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi new file mode 100644 index 000000000000..f505f2704530 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-vicut1-12inch.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 Protonic Holland + */ + +/ { + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + autorepeat; + + power { + label = "Power Button"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + panel { + compatible = "kyo,tcg121xglp"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031RNX PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", + "CAM2_MIRROR", "", "", "SMBALERT", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", + "SD1_DATA3", "ETH_MDIO", "", + "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", + "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", + "CAN2_SR", "CAN2_TX", "CAN2_RX", + "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", + "HITCH_IN_OUT", + "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", + "ISB_LED"; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", + "I2S_BITCLK", "I2S_DOUT", + "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", + "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; +}; + +&gpio6 { + gpio-line-names = + "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", + "ITU656_D6", "ITU656_D7", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", + "RGMII_TD3", + "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", + "RGMII_RD2", "RGMII_RD3", "", ""; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + /* Phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + >; + }; + + pinctrl_gpiokeys: gpiokeygrp { + fsl,pins = < + /* nON_SWITCH */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6qp-vicutp.dts b/arch/arm/boot/dts/imx6qp-vicutp.dts index 31c748e9d92f..49ff145fffe5 100644 --- a/arch/arm/boot/dts/imx6qp-vicutp.dts +++ b/arch/arm/boot/dts/imx6qp-vicutp.dts @@ -6,130 +6,9 @@ /dts-v1/; #include "imx6qp.dtsi" #include "imx6qdl-vicut1.dtsi" +#include "imx6qdl-vicut1-12inch.dtsi" / { model = "Kverneland UT1P Board"; compatible = "kvg,vicutp", "fsl,imx6qp"; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - autorepeat; - - power { - label = "Power Button"; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - panel { - compatible = "kyo,tcg121xglp"; - backlight = <&backlight_lcd>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii-id"; - phy-handle = <&rgmii_phy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - /* Microchip KSZ9031RNX PHY */ - rgmii_phy: ethernet-phy@0 { - reg = <0>; - interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <300>; - }; - }; -}; - -&gpio1 { - gpio-line-names = - "CAN1_TERM", "SD1_CD", "ITU656_RESET", "CAM1_MIRROR", - "CAM2_MIRROR", "", "", "SMBALERT", - "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", - "SD1_DATA0", "SD1_DATA1", "SD1_CMD", "SD1_DATA2", "SD1_CLK", - "SD1_DATA3", "ETH_MDIO", "", - "", "ETH_RESET", "", "", "ETH_INT", "", "", "ETH_MDC"; -}; - -&gpio4 { - gpio-line-names = - "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", - "UART5_TXD", "UART5_RXD", "CAN1_TX", "CAN1_RX", "CAN1_SR", - "CAN2_SR", "CAN2_TX", "CAN2_RX", - "", "", "DIP1_FB", "", "VCAM_EN", "ON1_CTRL", "ON2_CTRL", - "HITCH_IN_OUT", - "LIGHT_ON", "", "", "CONTACT_IN", "BL_EN", "BL_PWM", "", - "ISB_LED"; -}; - -&gpio5 { - gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "ITU656_CLK", "I2S_MCLK", "ITU656_PDN", "AUDIO_RESET", - "I2S_BITCLK", "I2S_DOUT", - "I2S_LRCLK", "I2S_DIN", "I2C1_SDA", "I2C1_SCL", "YACO_AUX_RX", - "YACO_AUX_TX", "ITU656_D0", "ITU656_D1"; -}; - -&gpio6 { - gpio-line-names = - "ITU656_D2", "ITU656_D3", "ITU656_D4", "ITU656_D5", - "ITU656_D6", "ITU656_D7", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "RGMII_TXC", "RGMII_TD0", "RGMII_TD1", "RGMII_TD2", - "RGMII_TD3", - "RGMII_RX_CTL", "RGMII_RD0", "RGMII_TX_CTL", "RGMII_RD1", - "RGMII_RD2", "RGMII_RD3", "", ""; -}; - -&iomuxc { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 - /* Phy reset */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 - >; - }; - - pinctrl_gpiokeys: gpiokeygrp { - fsl,pins = < - /* nON_SWITCH */ - MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b0 - >; - }; }; From eac849a24e188adeecd0ba3b598ea861281da725 Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:22 +0200 Subject: [PATCH 43/77] ARM: dts: imx6dl-victgo.dts: Remove touchscreen x axis inversion X axis is not inverted in hardware. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 4f6100b2ce2d..516ec915a911 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -94,7 +94,6 @@ touchscreen { <&adc_ts 5>; io-channel-names = "y", "z1", "z2", "x"; touchscreen-min-pressure = <64687>; - touchscreen-inverted-x; touchscreen-inverted-y; touchscreen-x-plate-ohms = <300>; touchscreen-y-plate-ohms = <800>; From b456aed07944b3048d68f7daad2fd6e1155dc4fe Mon Sep 17 00:00:00 2001 From: David Jander Date: Tue, 19 Apr 2022 06:48:23 +0200 Subject: [PATCH 44/77] ARM: dts: imx6qdl-vicut1.dtsi: Add missing ISB led node Add missing ISB led node. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index 2a86136a04e8..c928bd854e92 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -95,6 +95,13 @@ led-2 { gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; default-state = "on"; }; + + led-3 { + label = "isb_led"; + function = LED_FUNCTION_POWER; + gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; }; reg_1v8: regulator-1v8 { @@ -574,6 +581,8 @@ MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b0 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0 /* POWER_LED */ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b0 + /* ISB_LED */ + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 >; }; From 7912bda4f60dbb86c5aaa41fc1d36e639780ac90 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 19 Apr 2022 06:48:24 +0200 Subject: [PATCH 45/77] ARM: dts: imx6qdl-vicut1.dtsi: add thermal zone and attach tmp103 to it. Latest version of ti,tmp103 driver supports thermal zone. So make use of it. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-vicut1.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index c928bd854e92..a1676b5d2980 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -153,6 +153,14 @@ simple-audio-card,codec { frame-master; }; }; + + thermal-zones { + chassis-thermal { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&tsens0>; + }; + }; }; &audmux { @@ -323,9 +331,10 @@ rtc@51 { reg = <0x51>; }; - temperature-sensor@70 { + tsens0: temperature-sensor@70 { compatible = "ti,tmp103"; reg = <0x70>; + #thermal-sensor-cells = <0>; }; }; From 4b9b8985f9697b5d26efe7784e4b9e51cb452020 Mon Sep 17 00:00:00 2001 From: Changming Huang Date: Wed, 20 Apr 2022 10:35:56 +0800 Subject: [PATCH 46/77] ARM: dts: Add initial LS1021A IoT board dts support The LS1021A-IoT gateway reference design is a purpose-built, small footprint hardware platform equipped with a wide array of both high-speed connectivity and low speed serial interfaces. CC: Li Yang Signed-off-by: Changming Huang Signed-off-by: Alison Wang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/ls1021a-iot.dts | 227 ++++++++++++++++++++++++++++++ 2 files changed, 228 insertions(+) create mode 100644 arch/arm/boot/dts/ls1021a-iot.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f0e5fc7e5274..32e9bbf0d13c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -753,6 +753,7 @@ dtb-$(CONFIG_SOC_IMX7ULP) += \ dtb-$(CONFIG_SOC_LAN966) += \ lan966x-pcb8291.dtb dtb-$(CONFIG_SOC_LS1021A) += \ + ls1021a-iot.dtb \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ ls1021a-tsn.dtb \ diff --git a/arch/arm/boot/dts/ls1021a-iot.dts b/arch/arm/boot/dts/ls1021a-iot.dts new file mode 100644 index 000000000000..66bcdaf4b6f9 --- /dev/null +++ b/arch/arm/boot/dts/ls1021a-iot.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021-2022 NXP + * + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "LS1021A-IOT Board"; + compatible = "fsl,ls1021a-iot", "fsl,ls1021a"; + + sys_mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + reg_3p3v: regulator-3V3 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_2p5v: regulator-2V5 { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker Ext", + "Line", "Line In Jack"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "Speaker Ext", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + frame-master; + bitclock-master; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + frame-master; + bitclock-master; + }; + }; +}; + +&can0{ + status = "disabled"; +}; + +&can1{ + status = "disabled"; +}; + +&can2{ + status = "disabled"; +}; + +&can3{ + status = "okay"; +}; + +&dcu { + display = <&display>; + status = "okay"; + + display: display@0 { + bits-per-pixel = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: mode0 { + clock-frequency = <25000000>; + hactive = <640>; + vactive = <480>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <12>; + vsync-len = <2>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; +}; + +&enet0 { + tbi-handle = <&tbi1>; + phy-handle = <&phy1>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi1>; + phy-handle = <&phy3>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet2 { + fixed-link = <0 1 1000 0 0>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + +&esdhc{ + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + pca9555: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sgtl5000: audio-codec@2a { + #sound-dai-cells=<0x0>; + compatible = "fsl,sgtl5000"; + reg = <0x2a>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_2p5v>; + clocks = <&sys_mclk>; + }; + + max1239: adc@35 { + compatible = "maxim,max1239"; + reg = <0x35>; + #io-channel-cells = <1>; + }; + + ina2201: core-monitor@44 { + compatible = "ti,ina220"; + reg = <0x44>; + shunt-resistor = <1000>; + }; + + ina2202: current-monitor@45 { + compatible = "ti,ina220"; + reg = <0x45>; + shunt-resistor = <1000>; + }; + + lm75b: thermal-monitor@48 { + compatible = "national,lm75b"; + reg = <0x48>; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + phy0: ethernet-phy@0 { + reg = <0x0>; + }; + + phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + phy3: ethernet-phy@3 { + reg = <0x3>; + }; + + tbi1: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&qspi { + num-cs = <2>; + status = "okay"; + + s25fl128s: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&sai2 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; From 1f5985b6f5d2090897918b100cad223a74dce706 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 20 Apr 2022 11:12:02 +0300 Subject: [PATCH 47/77] ARM: dts: imx51: Add generic DMA bindings for UART nodes Updates UART nodes to adopt generic DMA bindings. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 56c8d87864c3..1e20a6639e42 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -215,6 +215,8 @@ uart3: serial@7000c000 { clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 43 5 1>, <&sdma 44 5 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -426,6 +428,8 @@ uart1: serial@73fbc000 { clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 18 4 1>, <&sdma 19 4 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -436,6 +440,8 @@ uart2: serial@73fc0000 { clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 16 4 1>, <&sdma 17 4 2>; + dma-names = "rx", "tx"; status = "disabled"; }; From ae7ab0bb32bdf18b70be04c3f254caaa54187225 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 20 Apr 2022 11:12:03 +0300 Subject: [PATCH 48/77] ARM: dts: i.MX51: digi-connectcore-som: Remove unused regulators VGEN1, VGEN2 and GPO1 regulators are not used on SOM. Let's remove these entries. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index 7d4970417dce..20e89cc4c838 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -102,18 +102,6 @@ vcam_reg: vcam { regulator-always-on; }; - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - vgen3_reg: vgen3 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -124,8 +112,6 @@ vusb_reg: vusb { regulator-always-on; }; - gpo1_reg: gpo1 { }; - gpo2_reg: gpo2 { }; gpo3_reg: gpo3 { }; From 12f9fa8880f2309abc0d344a19590c9e00b3ae91 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 20 Apr 2022 11:12:04 +0300 Subject: [PATCH 49/77] ARM: dts: i.MX51: digi-connectcore-som: Update PMIC voltages This patch updates the PMIC voltages according to the module's datasheet to match both commercial and industrial variants of the module. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index 20e89cc4c838..04a47200fc73 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -34,22 +34,22 @@ pmic: mc13892@0 { regulators { sw1_reg: sw1 { - regulator-min-microvolt = <1000000>; + regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1100000>; regulator-boot-on; regulator-always-on; }; sw2_reg: sw2 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; + regulator-min-microvolt = <1175000>; + regulator-max-microvolt = <1275000>; regulator-boot-on; regulator-always-on; }; sw3_reg: sw3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1350000>; regulator-boot-on; regulator-always-on; }; From a65123d60d757255694e55d228c247fb6da5a4fb Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 20 Apr 2022 11:12:05 +0300 Subject: [PATCH 50/77] ARM: dts: i.MX51: digi-connectcore-som: Setup usbotg vbus-supply The VBUS on usbotg is connected to the PMIC SWBST, let's reflect that in the bindings. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi index 04a47200fc73..f0809a16a2ce 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi +++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi @@ -184,6 +184,7 @@ &nfc { &usbotg { phy_type = "utmi_wide"; disable-over-current; + vbus-supply = <&swbst_reg>; /* Device role is not known, keep status disabled */ }; From 4bb3894ae658d8d5217843f344dd6cd5a9388924 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 20 Apr 2022 11:12:06 +0300 Subject: [PATCH 51/77] ARM: dts: i.MX51: digi-connectcore-jsk: Use usb-nop-xceiv usbphy for USB1 Add node describing the USB1 usbphy. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts index aab8d6f137c3..10cae7c3a879 100644 --- a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts +++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts @@ -13,6 +13,13 @@ / { chosen { stdout-path = &uart1; }; + + usbphy1: usbphy1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; }; &esdhc1 { @@ -63,6 +70,7 @@ &usbotg { &usbh1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh1>; + fsl,usbphy = <&usbphy1>; dr_mode = "host"; phy_type = "ulpi"; disable-over-current; From 1c1271e3bd28f293d336d92a78cce65b59c1d2d0 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Mon, 21 Mar 2022 21:28:13 -0500 Subject: [PATCH 52/77] ARM: dts: ls1021a: remove "simple-bus" compatible from ifc node The binding of ifc device has been updated. Update dts to match accordingly. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 2e69d6eab4d1..52835d3dfa1b 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -123,7 +123,7 @@ msi2: msi-controller@1570e08 { }; ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = ; status = "disabled"; From b4269132ace84954915a6630238a9bc7194fd4a7 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Mon, 21 Mar 2022 21:28:16 -0500 Subject: [PATCH 53/77] ARM: dts: update ifc node name to be memory-controller Update the node name to be align with latest binding. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 52835d3dfa1b..dca1bfbd028e 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -122,7 +122,7 @@ msi2: msi-controller@1570e08 { interrupts = ; }; - ifc: ifc@1530000 { + ifc: memory-controller@1530000 { compatible = "fsl,ifc"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = ; From 3a70c8b607c45dfc5306771879270ba00e74160a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Apr 2022 10:27:34 -0300 Subject: [PATCH 54/77] ARM: dts: mba6ulx: Remove unnecessary #address-cells/#size-cells The following W=1 dtc warning is seen: arch/arm/boot/dts/mba6ulx.dtsi:33.26-64.4: Warning (avoid_unnecessary_addr_size): /gpio-keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Remove the unnecessary #address-cells/#size-cells to fix it. Fixes: 7b8861d8e627 ("ARM: dts: imx6ul: add TQ-Systems MBa6ULx device trees") Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/mba6ulx.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/mba6ulx.dtsi b/arch/arm/boot/dts/mba6ulx.dtsi index fc38e185a51e..aac42df9ecf6 100644 --- a/arch/arm/boot/dts/mba6ulx.dtsi +++ b/arch/arm/boot/dts/mba6ulx.dtsi @@ -32,8 +32,6 @@ beeper: beeper { gpio_buttons: gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_buttons>; From a25875276e93636a8d1878c564d635f1a18bac24 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 21 Apr 2022 22:18:20 -0300 Subject: [PATCH 55/77] ARM: dts: imx6dl-plybas: Use the standard 'uart-has-rtscts' The usage of the 'fsl,uart-has-rtscts' property is deprecated. Use the standard 'uart-has-rtscts' instead. Cc: Oleksij Rempel Signed-off-by: Fabio Estevam Reviewed-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-plybas.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-plybas.dts b/arch/arm/boot/dts/imx6dl-plybas.dts index bf72a67a9c76..c52e6caf3996 100644 --- a/arch/arm/boot/dts/imx6dl-plybas.dts +++ b/arch/arm/boot/dts/imx6dl-plybas.dts @@ -214,7 +214,7 @@ &uart1 { &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - fsl,uart-has-rtscts; + uart-has-rtscts; linux,rs485-enabled-at-boot-time; rs485-rts-delay = <0 20>; status = "okay"; From 89bbe4e4ba0ac2402ac6fd268acedeb44f387a80 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 21 Apr 2022 22:18:21 -0300 Subject: [PATCH 56/77] ARM: dts: imx6ul-kontron-n6x1x-s: Use the standard 'uart-has-rtscts' The usage of the 'fsl,uart-has-rtscts' property is deprecated. Use the standard 'uart-has-rtscts' instead. Cc: Frieder Schrempf Signed-off-by: Fabio Estevam Acked-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi index 770f59b23102..a6cf0f21c66d 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi @@ -178,7 +178,7 @@ &uart2 { &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + uart-has-rtscts; status = "okay"; }; From ce92db719adc14c7a8a5acb4bd85cb8a9d072831 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 22 Apr 2022 16:55:37 -0300 Subject: [PATCH 57/77] ARM: dts: imx6sl: Add a label for the cpu node Add a label for the cpu node, so that board devicetree files can reference to the CPU node. This is useful for describing a PMIC voltage that supplies the CPU voltage. For example: &cpu0 { cpu-supply = <&sw1_reg>; Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index c7d907c5c352..06a515121dfc 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -50,7 +50,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0x0>; From 51b9d74cdb9fe5d5492214da20ab50173c1e9b08 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 27 Apr 2022 09:53:35 +0200 Subject: [PATCH 58/77] ARM: dts: ls1021a: reduce the interrupt-map-mask Reduce the interrupt-map-mask of the external interrupt controller to 7 to align with the devicetree schema. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index dca1bfbd028e..6c88be2a7e8e 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -192,7 +192,7 @@ extirq: interrupt-controller@1ac { <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0xffffffff 0x0>; + interrupt-map-mask = <0x7 0x0>; }; }; From fcc070a44ecce5e800725136ce2e47ce00d40ca7 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 27 Apr 2022 12:42:05 +0300 Subject: [PATCH 59/77] ARM: dts: imx6qdl-phytec: Add LED labels This allows boards the option of adding properties or disabling the LEDs entirely. Signed-off-by: Alexander Shiyan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 1f2ba6f6254e..768bc0e3a2b3 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -47,12 +47,12 @@ gpio_leds: leds { pinctrl-0 = <&pinctrl_leds>; compatible = "gpio-leds"; - green { + led_green: green { label = "phyflex:green"; gpios = <&gpio1 30 0>; }; - red { + led_red: red { label = "phyflex:red"; gpios = <&gpio2 31 0>; }; From 552de48b9e429ca723cd5c3c2613769a428d98dc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 27 Apr 2022 18:15:33 +0200 Subject: [PATCH 60/77] ARM: dts: imx27: use new 'dma-channels' property The '#dma-channels' property was deprecated in favor of one defined by generic dma-common DT bindings. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx27.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index fd525c3b16fa..b660c7d05584 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -96,7 +96,7 @@ dma: dma@10001000 { <&clks IMX27_CLK_DMA_AHB_GATE>; clock-names = "ipg", "ahb"; #dma-cells = <1>; - #dma-channels = <16>; + dma-channels = <16>; }; wdog: watchdog@10002000 { From 8f2ca252ee1f848d3eec9ebbbf3c3881cb423322 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sun, 1 May 2022 18:47:13 +0100 Subject: [PATCH 61/77] ARM: dts: imx6qdl-udoo: Disable USB host to work around boot issues Attempting to boot my Udoo Dual and Quad with mainline hangs during boot after printing: [ 3.270471] imx_usb 2184000.usb: No over current polarity defined [ 3.922502] mxs_phy 20c9000.usbphy: Data pin can't make good contact. [ 3.940097] imx_usb 2184200.usb: No over current polarity defined where imx_usb 2184200.usb is usbh1 in the DT. Adding debug prints to the code seems to show that we lock up at the first read in usbmisc_imx6q_init() which in combination with the above logging about the USB controllers suggests that we lock up on the first read in usbmisc_imx6q_init(). Looking at some of the other i.MX6 boards and the warning messages that are being printed suggests that there is bitrot in the DTS for the device so disable it for now, with it disabled the board boots successfully. Clearly this is not a real fix, but it does allow some use of the board with mainline. Similar behaviour is seen all the way back as far as v4.19, I tried going back to when the board was added but had toolchain issues. Vendor provided binaries seem fine on the boards so it seems likely that the hardware is fine and the issue is with some combination of the DT and kernel. This should obviously be resolved properly but for now this at least allows the kernel to boot with reduced functionality on these systems. Signed-off-by: Mark Brown Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-udoo.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi index ccfa8e320be6..93a8123da27d 100644 --- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi +++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi @@ -295,7 +295,7 @@ &usbh1 { pinctrl-0 = <&pinctrl_usbh>; vbus-supply = <®_usb_h1_vbus>; clocks = <&clks IMX6QDL_CLK_CKO>; - status = "okay"; + status = "disabled"; }; &usbotg { From 9ac0ae97e34911177e3b59328055eccbd27cefca Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 5 May 2022 08:19:05 -0300 Subject: [PATCH 62/77] ARM: dts: imx7d-smegw01: Add support for i.MX7D SMEGW01 board Add support for the i.MX7D SMEGW01 board. This is a gateway board that supports the following peripherals: - eMMC / SD card - RTC - USB modem - Wifi via SDIO - Dual Ethernet - CAN - Serial SRAM Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx7d-smegw01.dts | 469 ++++++++++++++++++++++++++++ 2 files changed, 470 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d-smegw01.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 32e9bbf0d13c..0ad8339e07d8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -741,6 +741,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb.dtb \ imx7d-sdb-reva.dtb \ imx7d-sdb-sht11.dtb \ + imx7d-smegw01.dtb \ imx7d-zii-rmu2.dtb \ imx7d-zii-rpu2.dtb \ imx7s-colibri-aster.dtb \ diff --git a/arch/arm/boot/dts/imx7d-smegw01.dts b/arch/arm/boot/dts/imx7d-smegw01.dts new file mode 100644 index 000000000000..c6b32064a009 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-smegw01.dts @@ -0,0 +1,469 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright (C) 2020 PHYTEC Messtechnik GmbH +// Author: Jens Lang +// Copyright (C) 2021 Fabio Estevam + +/dts-v1/; +#include +#include "imx7d.dtsi" + +/ { + model = "Storopack SMEGW01 board"; + compatible = "storopack,imx7d-smegw01", "fsl,imx7d"; + + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc3; + mmc2 = &usdhc2; + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_lte_on: regulator-lte-on { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lte_on>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "lte_on"; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_lte_nreset: regulator-lte-nreset { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lte_nreset>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "LTE_nReset"; + gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + gpio = <&gpio2 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + regulator-name = "wifi_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_wlan_rfkill: regulator-wlan-rfkill { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-2 = <&pinctrl_rfkill>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "wlan_rfkill"; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_pwr_gpio>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 05 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + status = "okay"; + + sram@0 { + compatible = "microchip,48l640"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <16000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + }; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 =<&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + i2c_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + reg = <0x52>; + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_lpsr>; + dr_mode = "otg"; + vbus-supply = <®_usbotg_vbus>; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + enable-sdio-wakeup; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + non-removable; + cap-sd-highspeed; + sd-uhs-ddr50; + mmc-ddr-1_8v; + vmmc-supply = <®_wifi>; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + max-frequency = <200000000>; + bus-width = <8>; + fsl,tuning-step = <1>; + non-removable; + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x04 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x04 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x04 + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x04 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5 + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x5 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x5 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x5 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x5 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x5 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x5 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x5 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x5 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x5 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x5 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x5 + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x5 + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x08 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000004 + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000004 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0b0b0 + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x0b0b0 + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0b0b0 + >; + }; + + pinctrl_lte_on: lteongrp { + fsl,pins = < + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x17059 + >; + }; + + pinctrl_lte_nreset: ltenresetgrp { + fsl,pins = < + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x17059 + >; + }; + + pinctrl_rfkill: rfkillrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x17059 + >; + }; + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x7c + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x74 + >; + }; + + pinctrl_usbotg1_lpsr: usbotg1 { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x04 + >; + }; + + pinctrl_usbotg1_pwr: usbotg1-pwr { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__USB_OTG1_PWR 0x04 + >; + }; + + pinctrl_usbotg1_pwr_gpio: usbotg1-pwr-gpio { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x04 + >; + }; + + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x04 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + MX7D_PAD_SD2_CD_B__SD2_CD_B 0x08 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5d + MX7D_PAD_SD3_CLK__SD3_CLK 0x1d + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5e + MX7D_PAD_SD3_CLK__SD3_CLK 0x1e + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5f + MX7D_PAD_SD3_CLK__SD3_CLK 0x0f + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x04 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x04 + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; +}; From 1c4f01be3490263b73755ed24a229a5885d9ce8e Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Tue, 11 Jan 2022 16:54:14 -0500 Subject: [PATCH 63/77] ARM: dts: imx: Add i.MXRT1050-EVK support The NXP i.MXRT1050 Evaluation Kit (EVK) provides a platform for rapid evaluation of the i.MXRT, which features NXP's implementation of the Arm Cortex-M7 core. The EVK provides 32 MB SDRAM, 64 MB Quad SPI flash, Micro SD card socket, USB 2.0 OTG. This patch aims to support the preliminary booting up features as follows: GPIO LPUART SD/MMC Signed-off-by: Giulio Benetti Signed-off-by: Jesse Taube [Jesse: Add clock-parents, edma, usdhc, anatop, remove old pinctl] Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imxrt1050-evk.dts | 72 +++++++++++++ arch/arm/boot/dts/imxrt1050.dtsi | 160 ++++++++++++++++++++++++++++ 3 files changed, 234 insertions(+) create mode 100644 arch/arm/boot/dts/imxrt1050-evk.dts create mode 100644 arch/arm/boot/dts/imxrt1050.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0ad8339e07d8..b4ac94e3c9ed 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -751,6 +751,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ dtb-$(CONFIG_SOC_IMX7ULP) += \ imx7ulp-com.dtb \ imx7ulp-evk.dtb +dtb-$(CONFIG_SOC_IMXRT) += \ + imxrt1050-evk.dtb dtb-$(CONFIG_SOC_LAN966) += \ lan966x-pcb8291.dtb dtb-$(CONFIG_SOC_LS1021A) += \ diff --git a/arch/arm/boot/dts/imxrt1050-evk.dts b/arch/arm/boot/dts/imxrt1050-evk.dts new file mode 100644 index 000000000000..6a9c10decf52 --- /dev/null +++ b/arch/arm/boot/dts/imxrt1050-evk.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +/dts-v1/; +#include "imxrt1050.dtsi" +#include "imxrt1050-pinfunc.h" + +/ { + model = "NXP IMXRT1050-evk board"; + compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + mmc0 = &usdhc1; + serial0 = &lpuart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x2000000>; + }; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1 + MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000 + MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069 + MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061 + >; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi new file mode 100644 index 000000000000..77b911b06041 --- /dev/null +++ b/arch/arm/boot/dts/imxrt1050.dtsi @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#include "armv7-m.dtsi" +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + clocks { + osc: osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + osc3M: osc3M { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <3000000>; + }; + }; + + soc { + lpuart1: serial@40184000 { + compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x40184000 0x4000>; + interrupts = <20>; + clocks = <&clks IMXRT1050_CLK_LPUART1>; + clock-names = "ipg"; + status = "disabled"; + }; + + iomuxc: pinctrl@401f8000 { + compatible = "fsl,imxrt1050-iomuxc"; + reg = <0x401f8000 0x4000>; + fsl,mux_mask = <0x7>; + }; + + anatop: anatop@400d8000 { + compatible = "fsl,imxrt-anatop"; + reg = <0x400d8000 0x4000>; + }; + + clks: clock-controller@400fc000 { + compatible = "fsl,imxrt1050-ccm"; + reg = <0x400fc000 0x4000>; + interrupts = <95>, <96>; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>, + <&clks IMXRT1050_CLK_PLL1_BYPASS>, + <&clks IMXRT1050_CLK_PLL2_BYPASS>, + <&clks IMXRT1050_CLK_PLL3_BYPASS>, + <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>, + <&clks IMXRT1050_CLK_PLL2_PFD2_396M>; + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>, + <&clks IMXRT1050_CLK_PLL1_ARM>, + <&clks IMXRT1050_CLK_PLL2_SYS>, + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, + <&clks IMXRT1050_CLK_PLL2_SYS>; + }; + + edma1: dma-controller@400e8000 { + #dma-cells = <2>; + compatible = "fsl,imx7ulp-edma"; + reg = <0x400e8000 0x4000>, + <0x400ec000 0x4000>; + dma-channels = <32>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, + <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>; + clock-names = "dma", "dmamux0"; + clocks = <&clks IMXRT1050_CLK_DMA>, + <&clks IMXRT1050_CLK_DMA_MUX>; + }; + + usdhc1: mmc@402c0000 { + compatible ="fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x402c0000 0x4000>; + interrupts = <110>; + clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, + <&clks IMXRT1050_CLK_OSC>, + <&clks IMXRT1050_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,wp-controller; + no-1-8-v; + max-frequency = <4000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + gpio1: gpio@401b8000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401b8000 0x4000>; + interrupts = <80>, <81>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@401bc000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401bc000 0x4000>; + interrupts = <82>, <83>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@401c0000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401c0000 0x4000>; + interrupts = <84>, <85>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@401c4000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x401c4000 0x4000>; + interrupts = <86>, <87>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@400c0000 { + compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; + reg = <0x400c0000 0x4000>; + interrupts = <88>, <89>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpt: timer@401ec000 { + compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; + reg = <0x401ec000 0x4000>; + interrupts = <100>; + clocks = <&osc3M>; + clock-names = "per"; + }; + }; +}; From 6192cf8ac0824a87c4dac0e94ae94062a0edc811 Mon Sep 17 00:00:00 2001 From: Philip Oberfichtner Date: Fri, 6 May 2022 07:59:49 +0200 Subject: [PATCH 64/77] ARM: dts: Add bosch acc board Add device tree for the Bosch ACC board, based on i.MX6 Dual. Signed-off-by: Philip Oberfichtner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6q-bosch-acc.dts | 779 ++++++++++++++++++++++++++ 2 files changed, 780 insertions(+) create mode 100644 arch/arm/boot/dts/imx6q-bosch-acc.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b4ac94e3c9ed..b711d4423b42 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -549,6 +549,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-b450v3.dtb \ imx6q-b650v3.dtb \ imx6q-b850v3.dtb \ + imx6q-bosch-acc.dtb \ imx6q-cm-fx6.dtb \ imx6q-cubox-i.dtb \ imx6q-cubox-i-emmc-som-v15.dtb \ diff --git a/arch/arm/boot/dts/imx6q-bosch-acc.dts b/arch/arm/boot/dts/imx6q-bosch-acc.dts new file mode 100644 index 000000000000..8768222e183e --- /dev/null +++ b/arch/arm/boot/dts/imx6q-bosch-acc.dts @@ -0,0 +1,779 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Support for the i.MX6-based Bosch ACC board. + * + * Copyright (C) 2016 Garz & Fricke GmbH + * Copyright (C) 2018 DENX Software Engineering GmbH, Heiko Schocher + * Copyright (C) 2018 DENX Software Engineering GmbH, Niel Fourie + * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker + * Copyright (C) 2022 DENX Software Engineering GmbH, Philip Oberfichtner + */ + +/dts-v1/; + +#include +#include +#include "imx6q.dtsi" + +/ { + model = "Bosch ACC"; + compatible = "bosch,imx6q-acc", "fsl,imx6q"; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc4; + mmc1 = &usdhc2; + serial0 = &uart2; + serial1 = &uart1; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 200000>; + brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>; + num-interpolated-steps = <10>; + default-brightness-level = <60>; + power-supply = <®_lcd>; + }; + + panel { + compatible = "dataimage,fg1001l0dsswmg01"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + refclk: refclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "12mhz_refclk"; + assigned-clocks = <&clks IMX6QDL_CLK_CKO>, + <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_CKO2>, + <&clks IMX6QDL_CLK_CKO2_PODF>, + <&clks IMX6QDL_CLK_OSC>; + assigned-clock-rates = <0>, <12000000>, <0>; + }; + + cpus { + cpu0: cpu@0 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + + cpu1: cpu@1 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1225000 + 852000 1225000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1225000 + 996000 1175000 + 852000 1175000 + 792000 1150000 + 396000 1150000 + >; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + led_red: led-0 { + color = ; + max-brightness = <248>; + default-state = "off"; + pwms = <&pwm2 0 500000>; + }; + + led_white: led-1 { + color = ; + max-brightness = <248>; + default-state = "off"; + pwms = <&pwm3 0 500000>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_gpio_led>; + + led-2 { + color = ; + gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_5p0: regulator-5p0 { + compatible = "regulator-fixed"; + regulator-name = "5p0"; + }; + + reg_vin: regulator-vin { + compatible = "regulator-fixed"; + regulator-name = "VIN"; + regulator-min-microvolt = <4500000>; + regulator-max-microvolt = <4500000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_usb_h2_vbus: regulator-usb-h2-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_5p0> ; + regulator-always-on; + }; + + reg_vsnvs: regulator-vsnvs { + compatible = "regulator-fixed"; + regulator-name = "VSNVS_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + regulator-name = "LCD0 POWER"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_enable>; + gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + reg_dac: regulator-dac { + compatible = "regulator-fixed"; + regulator-name = "vref_dac"; + regulator-min-microvolt = <20000>; + regulator-max-microvolt = <20000>; + vin-supply = <®_5p0> ; + regulator-boot-on; + }; + + reg_sw4: regulator-sw4 { + compatible = "regulator-fixed"; + regulator-name = "SW4_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; + + reg_sys: regulator-sys { + compatible = "regulator-fixed"; + regulator-name = "SYS_4V2"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + vin-supply = <®_5p0>; + }; +}; + +®_arm { + vin-supply = <&sw2_reg>; +}; + +®_soc { + vin-supply = <&sw1c_reg>; +}; + +®_vdd1p1 { + vin-supply = <®_vsnvs>; +}; + +®_vdd2p5 { + vin-supply = <®_vsnvs>; +}; + +®_vdd3p0 { + vin-supply = <®_vsnvs>; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", "enet_out"; + phy-mode = "rmii"; + phy-supply = <®_sw4>; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + smsc,disable-energy-detect; + }; + }; +}; + +&gpu_vg { + status = "disabled"; +}; + +&gpu_2d { + status = "disabled"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1c_reg: sw1c { + regulator-name = "VDD_SOC (sw1abc)"; + regulator-min-microvolt = <1275000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-name = "VDD_ARM (sw2)"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw3a_reg: sw3a { + compatible = "regulator-fixed"; + regulator-name = "DDR_1V5a"; + regulator-boot-on; + regulator-always-on; + + }; + + sw3b_reg: sw3b { + compatible = "regulator-fixed"; + regulator-name = "DDR_1V5b"; + regulator-boot-on; + regulator-always-on; + + }; + + sw4_reg: sw4 { + regulator-name = "AUX 3V15 (sw4)"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; + status = "disabled"; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + lm75: sensor@49 { + compatible = "national,lm75b"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lm75>; + reg = <0x49>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@51 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; + status = "okay"; + + eeprom_ext: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + usb3503: usb@8 { + compatible = "smsc,usb3503"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503>; + reg = <0x08>; + connect-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* Old: 0, SS: HIGH */ + intn-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; /* Old: 1, SS: HIGH */ + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* Old: 0, SS: HIGH */ + initial-mode = <1>; + clocks = <&refclk>; + clock-names = "refclk"; + refclk-frequency = <12000000>; + }; + + exc3000: touchscreen@2a { + compatible = "eeti,exc3000"; + reg = <0x2a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctouch>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + touchscreen-size-x = <4096>; + touchscreen-size-y = <4096>; + }; + + vcnl4035: light-sensor@60 { + compatible = "vishay,vcnl4035"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_proximity>; + reg = <0x60>; + }; +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&pwm1 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + rts-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbh2 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh2_idle>; + pinctrl-1 = <&pinctrl_usbh2_active>; + vbus-supply = <®_usb_h2_vbus>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usb_otg_vbus>; + disable-over-current; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphynop1 { + clocks = <&clks IMX6QDL_CLK_USBPHY1>; + clock-names = "main_clk"; + vcc-supply = <®_usb_h1_vbus>; +}; + +&usbphynop2 { + vcc-supply = <®_usb_h2_vbus>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + voltage-ranges = <3300 3300>; + vmmc-supply = <®_sw4>; + fsl,wp-controller; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + voltage-ranges = <3300 3300>; + vmmc-supply = <®_sw4>; + fsl,wp-controller; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; + timeout-sec=<10>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 /* FEC INT */ + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_reset_gpio_led: reset-gpio-led-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b810 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b810 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_lcd_enable: lcdenablegrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* lcd enable */ + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 /* sel6_8 */ + >; + }; + + pinctrl_lm75: lm75grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + >; + }; + + pinctrl_proximity: proximitygrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x0001b0b0 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x0001b0b0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x0001b0b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x0001b0b0 + >; + }; + + pinctrl_rtc: rtc-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0 /* RTC INT */ + >; + }; + + pinctrl_ctouch: ctouch-grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* CTOUCH_INT */ + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x0001b0b0 /* CTOUCH_RESET */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x0001b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_usbh2_idle: usbh2-idle-grp { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00013018 + >; + }; + + pinctrl_usbh2_active: usbh2-active-grp { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x00013018 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x00017018 + >; + }; + + pinctrl_usb3503: usb3503-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x00000018 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* USB INT */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0001b0b0 /* USB Reset */ + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0 /* USB Connect */ + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x00017069 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x00010038 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x00017069 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x00017069 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x00017069 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x00017069 + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x0001b0b0 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x00017059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x00010059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x00017059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x00017059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x00017059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x00017059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x00017059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x00017059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x00017059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x00017059 + >; + }; + + pinctrl_wdog1: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0 + >; + }; +}; From 3f781d5c67f7f5763913cccb972598df19f80c06 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Fri, 6 May 2022 15:24:04 +0200 Subject: [PATCH 65/77] ARM: dts: imx6ull-colibri: use pull-down for adc pins Disable the keeper and enable a 100k pull-down on the ADC pins as per the following note in section 13.2 of the i.MX 6ULL Application Processor Reference Manual, Rev. 1, 11/2017 [1]: The keeper causes an undesired jump behavior in ADC. To avoid the problem, disable keeper before starting ADC. [1] https://www.nxp.com/webapp/Download?colCode=IMX6ULLRM Signed-off-by: Philippe Schenker Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-colibri.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 7f35a06dff95..84bb7574d211 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -52,6 +52,8 @@ reg_sd1_vmmc: regulator-sd1-vmmc { &adc1 { num-channels = <10>; vref-supply = <®_module_3v3_avdd>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; }; &can1 { @@ -214,6 +216,16 @@ &wdog1 { }; &iomuxc { + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */ + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */ + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */ + >; + }; + pinctrl_can_int: canint-grp { fsl,pins = < MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ From 5516144425e413f0efe92b249142b4db15ff7ec5 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Fri, 6 May 2022 15:24:05 +0200 Subject: [PATCH 66/77] ARM: dts: imx6ull-colibri: change touch i2c parameters Switch on 22 kOhm pull-ups and lower the I2C frequency to around 40 kHz to get more reliable communication. Signed-off-by: Max Krummenacher Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-colibri.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 84bb7574d211..dc947035495b 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -114,6 +114,8 @@ &i2c1 { }; &i2c2 { + /* Use low frequency to compensate for the high pull-up values. */ + clock-frequency = <40000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; @@ -405,15 +407,15 @@ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */ pinctrl_i2c2: i2c2-grp { fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0 >; }; pinctrl_i2c2_gpio: i2c2-gpio-grp { fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 - MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0 >; }; From 5f9a2cedfaf3206b64a4d6b287357ae4037ed4a9 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Fri, 6 May 2022 15:24:06 +0200 Subject: [PATCH 67/77] ARM: dts: imx6ull-colibri: add phy-supply to fec This adds the proper phy-supply to the FEC. This supply is actually switched by a clock that is now properly stated. This has the advantage to add a delay for that particular regulator which is needed. Signed-off-by: Philippe Schenker Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-colibri.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index dc947035495b..7cd912df5d19 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -47,6 +47,18 @@ reg_sd1_vmmc: regulator-sd1-vmmc { states = <1800000 0x1 3300000 0x0>; vin-supply = <®_module_3v3>; }; + + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed-clock"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "+V3.3_ETH"; + regulator-type = "voltage"; + vin-supply = <®_module_3v3>; + clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; + startup-delay-us = <150000>; + }; }; &adc1 { @@ -81,6 +93,7 @@ &fec2 { pinctrl-1 = <&pinctrl_enet2_sleep>; phy-mode = "rmii"; phy-handle = <ðphy1>; + phy-supply = <®_eth_phy>; status = "okay"; mdio { From 2aa9d6201949b07dca7951710ef3be995600216c Mon Sep 17 00:00:00 2001 From: Denys Drozdov Date: Fri, 6 May 2022 15:24:07 +0200 Subject: [PATCH 68/77] ARM: dts: imx6ull-colibri: add touchscreen device nodes Move all Atmel nodes from the board-level into the main module-level device tree and prepare the device trees for use with Atmel MXT device tree overlays. Also, add required pinmux groups. The common scheme for pin groups in touch screen overlays is as follows: - pinctrl_atmel_conn - SODIMM 106/107 pins for INT/RST signals (default) - pinctrl_atmel_adap - SODIMM 28/30 pins for INT/RST signals. Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../arm/boot/dts/imx6ull-colibri-nonwifi.dtsi | 4 +- arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 4 +- arch/arm/boot/dts/imx6ull-colibri.dtsi | 39 +++++++++++++------ 3 files changed, 31 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi index 95a11b8bcbdb..5e55a6c820bc 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi @@ -15,10 +15,10 @@ memory@80000000 { &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 - &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>; + &pinctrl_gpio4 &pinctrl_gpio6 &pinctrl_gpio7>; }; &iomuxc_snvs { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2 &pinctrl_snvs_gpio3>; + pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi index 9f1e38282bee..6e8ddb07e11d 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi @@ -26,13 +26,13 @@ &cpu0 { &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 - &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio7>; + &pinctrl_gpio4 &pinctrl_gpio7>; }; &iomuxc_snvs { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2>; + pinctrl-0 = <&pinctrl_snvs_gpio1>; }; &usdhc2 { diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 7cd912df5d19..c89b209be316 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -124,6 +124,19 @@ &i2c1 { pinctrl-1 = <&pinctrl_i2c1_gpio>; sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_atmel_conn>; + reg = <0x4a>; + interrupt-parent = <&gpio5>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */ + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */ + status = "disabled"; + }; }; &i2c2 { @@ -241,6 +254,20 @@ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */ >; }; + pinctrl_atmel_adap: atmeladapgrp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */ + MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */ + >; + }; + + pinctrl_atmel_conn: atmelconngrp { + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ + >; + }; + pinctrl_can_int: canint-grp { fsl,pins = < MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ @@ -347,12 +374,6 @@ MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */ >; }; - pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */ - fsl,pins = < - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ - >; - }; - pinctrl_gpio6: gpio6-grp { /* Wifi pins */ fsl,pins = < MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */ @@ -606,12 +627,6 @@ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ >; }; - pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */ - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ - >; - }; - pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */ fsl,pins = < MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */ From 8d386fa04d2f652d3d8e2a5d82e25f20a8467bfb Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Fri, 6 May 2022 15:24:08 +0200 Subject: [PATCH 69/77] ARM: dts: imx6ull-colibri: update usdhc1 pixmux and signaling Due to many carrier boards pulling the usdhc1 signals up to 3.3 volt we need to disable 1.8 volt signaling. Adding the no-1-8-v property basically disables UHS-I modes by default. Also pull-up the command and data lines to the +V3.3_1.8_SD rail and set them to the 200 MHz speed grade (e.g. pinmux bits 7-6: meaning 11 SPEED_3_max_200MHz). Explicitly specify a bus-width of <4> in the module-level device tree include file and drop the no-1-8-v property from the carrier boards device trees. Signed-off-by: Philippe Schenker Signed-off-by: Denys Drozdov Signed-off-by: Andrejs Cainikovs Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 14 -------- arch/arm/boot/dts/imx6ull-colibri.dtsi | 36 ++++++++++++------- 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi index a78849fd2afa..ea086b305d22 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi @@ -159,20 +159,6 @@ &usbotg2 { }; &usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; - pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - disable-wp; - wakeup-source; - keep-power-in-suspend; vmmc-supply = <®_3v3>; - vqmmc-supply = <®_sd1_vmmc>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index c89b209be316..351ea2acd5a6 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -35,7 +35,7 @@ reg_module_3v3_avdd: regulator-module-3v3-avdd { regulator-max-microvolt = <3300000>; }; - reg_sd1_vmmc: regulator-sd1-vmmc { + reg_sd1_vqmmc: regulator-sd1-vqmmc { compatible = "regulator-gpio"; gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; @@ -232,9 +232,21 @@ &usbotg2 { }; &usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>; assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; assigned-clock-rates = <0>, <198000000>; + bus-width = <4>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + disable-wp; + keep-power-in-suspend; + no-1-8-v; + vqmmc-supply = <®_sd1_vqmmc>; + wakeup-source; }; &wdog1 { @@ -550,8 +562,8 @@ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */ pinctrl_usdhc1: usdhc1-grp { fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 /* SODIMM 47 */ - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 /* SODIMM 190 */ + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */ + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */ @@ -561,8 +573,8 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */ pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 @@ -572,12 +584,12 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { fsl,pins = < - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 >; }; @@ -588,7 +600,7 @@ MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069 - MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17069 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10 >; From 233edcae449c660c3bcc49848c99f9f8e60b640c Mon Sep 17 00:00:00 2001 From: Denys Drozdov Date: Fri, 6 May 2022 15:24:09 +0200 Subject: [PATCH 70/77] ARM: dts: imx6ull-colibri: update device trees to support overlays Prepare in-tree device trees for out-of-tree device tree overlay support (eMMC SKU only). Relocate panel-dpi default to edt,et057090dhu (RGB 18bit VGA 640x480) to the module-level dtsi and remove it from the carrier board dtsi. Keep backlight, resistive touch and Atmel maxtouch nodes enabled for both eMMC and NAND modules. Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 29 ----------------- arch/arm/boot/dts/imx6ull-colibri.dtsi | 31 ++++++++++++++++--- 2 files changed, 27 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi index ea086b305d22..3c07b4273e80 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi @@ -29,17 +29,6 @@ clk16m: clk16m { clock-frequency = <16000000>; }; - panel: panel { - compatible = "edt,et057090dhu"; - backlight = <&bl>; - power-supply = <®_3v3>; - - port { - panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; - }; - }; reg_3v3: regulator-3v3 { compatible = "regulator-fixed"; @@ -71,14 +60,6 @@ &adc1 { status = "okay"; }; -&bl { - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - power-supply = <®_3v3>; - pwms = <&pwm4 0 5000000 1>; - status = "okay"; -}; - &ecspi1 { status = "okay"; @@ -107,16 +88,6 @@ m41t0m6: rtc@68 { }; }; -&lcdif { - status = "okay"; - - port { - lcdif_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; -}; - /* PWM */ &pwm4 { status = "okay"; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 351ea2acd5a6..28baffcef096 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -11,12 +11,29 @@ aliases { ethernet1 = &fec1; }; - bl: backlight { + backlight: backlight { compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_bl_on>; - enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; - status = "disabled"; + power-supply = <®_3v3>; + pwms = <&pwm4 0 5000000 1>; + status = "okay"; + }; + + panel_dpi: panel-dpi { + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + power-supply = <®_3v3>; + status = "okay"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; }; reg_module_3v3: regulator-module-3v3 { @@ -149,7 +166,7 @@ &i2c2 { scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; - ad7879@2c { + ad7879_ts: touchscreen@2c { compatible = "adi,ad7879-1"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_snvs_ad7879_int>; @@ -170,6 +187,12 @@ &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; + + port { + lcdif_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; }; &pwm4 { From c8eb30d06ee8401d21b166b6e3f0f7a5b2990971 Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Fri, 6 May 2022 15:24:10 +0200 Subject: [PATCH 71/77] ARM: dts: imx6ull-colibri: add gpio-line-names Add GPIO line names on module-level. Those are all GPIOs that a user might use on his custom carrier board. If more meaningful names are available on the carrier board, the user can overwrite the line names in the carrier board-level device tree. Signed-off-by: Oleksandr Suvorov Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../arm/boot/dts/imx6ull-colibri-nonwifi.dtsi | 137 ++++++++++++++++++ arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 136 +++++++++++++++++ 2 files changed, 273 insertions(+) diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi index 5e55a6c820bc..60f169227ad9 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi @@ -12,6 +12,143 @@ memory@80000000 { }; }; +&gpio1 { + gpio-line-names = "SODIMM_8", + "SODIMM_6", + "SODIMM_129", + "SODIMM_89", + "SODIMM_19", + "SODIMM_21", + "UNUSABLE_SODIMM_180", + "UNUSABLE_SODIMM_184", + "SODIMM_4", + "SODIMM_2", + "SODIMM_106", + "SODIMM_71", + "SODIMM_23", + "SODIMM_31", + "SODIMM_99", + "SODIMM_102", + "SODIMM_33", + "SODIMM_35", + "SODIMM_25", + "SODIMM_27", + "SODIMM_36", + "SODIMM_38", + "SODIMM_32", + "SODIMM_34", + "SODIMM_135", + "SODIMM_77", + "SODIMM_100", + "SODIMM_186", + "SODIMM_196", + "SODIMM_194"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_55", + "SODIMM_63", + "SODIMM_178", + "SODIMM_188", + "SODIMM_73", + "SODIMM_30", + "SODIMM_67", + "SODIMM_104", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_190", + "SODIMM_47", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_29", + "SODIMM_37", + "SODIMM_88", + "SODIMM_86", + "SODIMM_92", + "SODIMM_90"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_59", + "", + "", + "SODIMM_133", + "", + "SODIMM_28", + "SODIMM_75", + "SODIMM_96", + "SODIMM_81", + "SODIMM_94", + "SODIMM_101", + "SODIMM_103", + "SODIMM_79", + "SODIMM_97", + "SODIMM_69", + "SODIMM_98", + "SODIMM_85", + "SODIMM_65"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_43", + "SODIMM_45", + "SODIMM_137", + "SODIMM_95", + "SODIMM_107", + "SODIMM_131", + "SODIMM_93", + "", + "SODIMM_138", + "", + "SODIMM_105", + "SODIMM_127"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi index 6e8ddb07e11d..3c47cfa7afa5 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi @@ -23,6 +23,142 @@ &cpu0 { clock-frequency = <792000000>; }; +&gpio1 { + gpio-line-names = "SODIMM_8", + "SODIMM_6", + "SODIMM_129", + "", + "SODIMM_19", + "SODIMM_21", + "UNUSABLE_SODIMM_180", + "UNUSABLE_SODIMM_184", + "SODIMM_4", + "SODIMM_2", + "SODIMM_106", + "SODIMM_71", + "SODIMM_23", + "SODIMM_31", + "SODIMM_99", + "SODIMM_102", + "SODIMM_33", + "SODIMM_35", + "SODIMM_25", + "SODIMM_27", + "SODIMM_36", + "SODIMM_38", + "SODIMM_32", + "SODIMM_34", + "SODIMM_135", + "SODIMM_77", + "SODIMM_100", + "SODIMM_186", + "SODIMM_196", + "SODIMM_194"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_55", + "SODIMM_63", + "SODIMM_178", + "SODIMM_188", + "SODIMM_73", + "SODIMM_30", + "SODIMM_67", + "SODIMM_104", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_190", + "SODIMM_47", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_29", + "SODIMM_37", + "SODIMM_88", + "SODIMM_86", + "SODIMM_92", + "SODIMM_90"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_59", + "", + "", + "SODIMM_133", + "", + "SODIMM_28", + "SODIMM_75", + "SODIMM_96", + "", + "", + "", + "", + "", + "", + "SODIMM_69", + "SODIMM_98", + "SODIMM_85", + "SODIMM_65"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_43", + "SODIMM_45", + "SODIMM_137", + "SODIMM_95", + "SODIMM_107", + "SODIMM_131", + "", + "", + "", + "", + "SODIMM_105"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 From 613d063240538e6c9a880bb63eb62d6ad33a9352 Mon Sep 17 00:00:00 2001 From: Denys Drozdov Date: Fri, 6 May 2022 15:24:11 +0200 Subject: [PATCH 72/77] ARM: dts: imx6ull-colibri: add support for toradex iris carrier boards Add support for Toradex Iris, small form-factor Pico-ITX Colibri Arm Computer Module family carrier boards. Iris Device Trees: - imx6ull-colibri-iris.dtb - imx6ull-colibri-emmc-iris.dtb - imx6ull-colibri-wifi-iris.dtb Iris-V2 Device Trees: - imx6ull-colibri-iris-v2.dtb - imx6ull-colibri-emmc-iris-v2.dtb - imx6ull-colibri-wifi-iris-v2.dtb Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 6 + .../boot/dts/imx6ull-colibri-emmc-iris-v2.dts | 17 +++ .../boot/dts/imx6ull-colibri-emmc-iris.dts | 17 +++ .../dts/imx6ull-colibri-emmc-nonwifi.dtsi | 4 +- arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts | 6 +- .../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 5 +- arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts | 65 +++++++++ .../arm/boot/dts/imx6ull-colibri-iris-v2.dtsi | 27 ++++ arch/arm/boot/dts/imx6ull-colibri-iris.dts | 20 +++ arch/arm/boot/dts/imx6ull-colibri-iris.dtsi | 132 ++++++++++++++++++ .../arm/boot/dts/imx6ull-colibri-nonwifi.dtsi | 4 +- .../boot/dts/imx6ull-colibri-wifi-eval-v3.dts | 4 +- .../boot/dts/imx6ull-colibri-wifi-iris-v2.dts | 65 +++++++++ .../boot/dts/imx6ull-colibri-wifi-iris.dts | 20 +++ arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 4 +- arch/arm/boot/dts/imx6ull-colibri.dtsi | 4 +- 16 files changed, 385 insertions(+), 15 deletions(-) create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris.dts create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b711d4423b42..d18b5a7cc4e8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -708,8 +708,14 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-mainboard.dtb \ imx6ull-14x14-evk.dtb \ imx6ull-colibri-emmc-eval-v3.dtb \ + imx6ull-colibri-emmc-iris.dtb \ + imx6ull-colibri-emmc-iris-v2.dtb \ imx6ull-colibri-eval-v3.dtb \ + imx6ull-colibri-iris.dtb \ + imx6ull-colibri-iris-v2.dtb \ imx6ull-colibri-wifi-eval-v3.dtb \ + imx6ull-colibri-wifi-iris.dtb \ + imx6ull-colibri-wifi-iris-v2.dtb \ imx6ull-jozacp.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ imx6ull-opos6uldev.dtb \ diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts new file mode 100644 index 000000000000..b9060c2f7977 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-emmc-nonwifi.dtsi" +#include "imx6ull-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 1G (eMMC) on Colibri Iris V2"; + compatible = "toradex,colibri-imx6ull-iris-v2", + "toradex,colibri-imx6ull-emmc", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts new file mode 100644 index 000000000000..0ab71f2f5daa --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-emmc-nonwifi.dtsi" +#include "imx6ull-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Iris"; + compatible = "toradex,colibri-imx6ull-emmc-iris", + "toradex,colibri-imx6ull-emmc", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi index a099abfdfa27..1d75bc671f75 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2021 Toradex + * Copyright 2022 Toradex */ #include "imx6ull-colibri.dtsi" diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts index 08669a18349e..9bf7111d7b00 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2018 Toradex AG + * Copyright 2018-2022 Toradex */ /dts-v1/; @@ -9,6 +9,6 @@ #include "imx6ull-colibri-eval-v3.dtsi" / { - model = "Toradex Colibri iMX6ULL 256MB on Colibri Evaluation Board V3"; + model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Evaluation Board V3"; compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi index 3c07b4273e80..08197c66af12 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2017 Toradex AG + * Copyright 2017-2022 Toradex */ / { @@ -121,6 +121,7 @@ &uart5 { }; &usbotg1 { + vbus-supply = <®_usbh_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts new file mode 100644 index 000000000000..afc1e0119783 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256M/512B on Colibri Iris V2"; + compatible = "toradex,colibri-imx6ull-iris-v2", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&gpio1 { + /* This turns the LVDS transceiver on */ + lvds-power-on { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ + line-name = "LVDS_POWER_ON"; + output-high; + }; +}; + +&gpio2 { + /* + * This switches the LVDS transceiver to the single-channel + * output mode. + */ + lvds-ch-mode { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ + line-name = "LVDS_CH_MODE"; + output-high; + }; + + /* + * This switches the LVDS transceiver to the 24-bit RGB mode. + */ + lvds-rgb-mode { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ + line-name = "LVDS_RGB_MODE"; + output-low; + }; +}; + +&gpio5 { + /* + * This switches the LVDS transceiver to VESA color mapping mode. + */ + lvds-color-map { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ + line-name = "LVDS_COLOR_MAP"; + output-low; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi new file mode 100644 index 000000000000..93649cad0cc0 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +#include "imx6ull-colibri-iris.dtsi" + +/ { + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + regulator-name = "3v3_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; +}; + + +&usdhc1 { + cap-power-off-card; + vmmc-supply = <®_3v3_vmmc>; + /delete-property/ keep-power-in-suspend; + /delete-property/ no-1-8-v; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-iris.dts new file mode 100644 index 000000000000..4fb97b0fe30b --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Iris"; + compatible = "toradex,colibri-imx6ull-iris", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi new file mode 100644 index 000000000000..7f3b37baba88 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&adc1 { + status = "okay"; +}; + +&gpio1 { + /* + * uart25_tx_on turns the UART transceiver on. If one wants to turn the + * transceiver off, that property has to be deleted and the gpio handled + * in userspace. + * The same applies to uart1_tx_on. + */ + uart25_tx_on { + gpio-hog; + gpios = <15 0>; + output-high; + }; +}; + +&gpio2 { + uart1_tx_on { + gpio-hog; + gpios = <7 0>; + output-high; + }; +}; + +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + m41t0m6: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* PWM */ +&pwm4 { + status = "okay"; +}; + +/* PWM */ +&pwm5 { + status = "okay"; +}; + +/* PWM */ +&pwm6 { + status = "okay"; +}; + +/* PWM */ +&pwm7 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usdhc1 { + vmmc-supply = <®_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi index 60f169227ad9..88901db255d6 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2018 Toradex AG + * Copyright 2018-2022 Toradex */ #include "imx6ull-colibri.dtsi" diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts index df72ce1ae2cb..1d64d1a5d8a7 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2018 Toradex AG + * Copyright 2018-2022 Toradex */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts new file mode 100644 index 000000000000..ce02f8a9ddd3 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris V2"; + compatible = "toradex,colibri-imx6ull-wifi-iris-v2", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&gpio1 { + /* This turns the LVDS transceiver on */ + lvds-power-on { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ + line-name = "LVDS_POWER_ON"; + output-high; + }; +}; + +&gpio2 { + /* + * This switches the LVDS transceiver to the single-channel + * output mode. + */ + lvds-ch-mode { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ + line-name = "LVDS_CH_MODE"; + output-high; + }; + + /* + * This switches the LVDS transceiver to the 24-bit RGB mode. + */ + lvds-rgb-mode { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ + line-name = "LVDS_RGB_MODE"; + output-low; + }; +}; + +&gpio5 { + /* + * This switches the LVDS transceiver to VESA color mapping mode. + */ + lvds-color-map { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ + line-name = "LVDS_COLOR_MAP"; + output-low; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts new file mode 100644 index 000000000000..5ac1aa298ce7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris"; + compatible = "toradex,colibri-imx6ull-wifi-iris", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi index 3c47cfa7afa5..db59ee6b1c86 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2018 Toradex AG + * Copyright 2018-2022 Toradex */ #include "imx6ull-colibri.dtsi" diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 28baffcef096..e74dd98fa66a 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2018-2021 Toradex + * Copyright 2018-2022 Toradex */ #include "imx6ull.dtsi" From 015feccc772297b7d8e95361437aa9def4adba7e Mon Sep 17 00:00:00 2001 From: Denys Drozdov Date: Fri, 6 May 2022 15:24:12 +0200 Subject: [PATCH 73/77] ARM: dts: imx6ull-colibri: add support for toradex aster carrier boards Add support for Toradex Aster, small form-factor Colibri Arm Computer Module family carrier board. Aster Device Trees: - imx6ull-colibri-aster.dtb - imx6ull-colibri-emmc-aster.dtb - imx6ull-colibri-wifi-aster.dtb Signed-off-by: Denys Drozdov Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/imx6ull-colibri-aster.dts | 20 +++ arch/arm/boot/dts/imx6ull-colibri-aster.dtsi | 145 ++++++++++++++++++ .../boot/dts/imx6ull-colibri-emmc-aster.dts | 17 ++ .../boot/dts/imx6ull-colibri-wifi-aster.dts | 20 +++ 5 files changed, 205 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-colibri-aster.dts create mode 100644 arch/arm/boot/dts/imx6ull-colibri-aster.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d18b5a7cc4e8..a496c4751c86 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -707,12 +707,15 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ imx6ull-14x14-evk.dtb \ + imx6ull-colibri-aster.dtb \ + imx6ull-colibri-emmc-aster.dtb \ imx6ull-colibri-emmc-eval-v3.dtb \ imx6ull-colibri-emmc-iris.dtb \ imx6ull-colibri-emmc-iris-v2.dtb \ imx6ull-colibri-eval-v3.dtb \ imx6ull-colibri-iris.dtb \ imx6ull-colibri-iris-v2.dtb \ + imx6ull-colibri-wifi-aster.dtb \ imx6ull-colibri-wifi-eval-v3.dtb \ imx6ull-colibri-wifi-iris.dtb \ imx6ull-colibri-wifi-iris-v2.dtb \ diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-aster.dts new file mode 100644 index 000000000000..d3f2fb7c6c1e --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Aster"; + compatible = "toradex,colibri-imx6ull-aster", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi new file mode 100644 index 000000000000..c9133ba2d705 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + linux,code = ; + debounce-interval = <10>; + wakeup-source; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&adc1 { + status = "okay"; +}; + +&ecspi1 { + status = "okay"; + + num-cs = <2>; + cs-gpios = < + &gpio3 26 GPIO_ACTIVE_HIGH /* SODIMM 86 LCD_DATA21 */ + &gpio4 28 GPIO_ACTIVE_HIGH /* SODIMM 65 CSI_DATA07 */ + >; +}; + +/* + * Following SODIMM Pins should not be accessed as GPIO on Aster board: + * 134 - AIN5_SCL (no connection) + * 127 - Voltage Level Translator OE# signal (IC11 and IC12) + * + * To configure GPIO to LED5, please disable FEC2 and uncomment the following: + * &iomuxc { + * pinctrl-names = "default"; + * pinctrl-0 = < + * &pinctrl_gpio1 + * &pinctrl_gpio2 + * &pinctrl_gpio3 + * &pinctrl_gpio4 + * &pinctrl_gpio6 - for non-WiFi modules only + * &pinctrl_gpio7 + * &pinctrl_gpio_aster + * >; + * + * pinctrl_gpio_aster: gpio-aster { + * fsl,pins = < + * MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x1b0b0 + * >; + * }; + * }; + */ + +&i2c1 { + status = "okay"; + + m41t0m6: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* PWM */ +&pwm4 { + status = "okay"; +}; + +/* PWM */ +&pwm5 { + status = "okay"; +}; + +/* PWM */ +&pwm6 { + status = "okay"; +}; + +/* PWM */ +&pwm7 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usdhc1 { + vmmc-supply = <®_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts new file mode 100644 index 000000000000..919c0464d6cb --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-emmc-nonwifi.dtsi" +#include "imx6ull-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Aster"; + compatible = "toradex,colibri-imx6ull-emmc-aster", + "toradex,colibri-imx6ull-emmc", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts new file mode 100644 index 000000000000..b4f65e8c5857 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2017-2022 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Aster"; + compatible = "toradex,colibri-imx6ull-wifi-aster", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; From 548453688549a69849bb93c5090767330ff98cbe Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 6 May 2022 15:24:13 +0200 Subject: [PATCH 74/77] ARM: dts: imx6ull-colibri: fix nand bch geometry Fix NAND BCH geometry relevant mainly for U-Boot. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-colibri.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index e74dd98fa66a..5e0cee146121 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -128,6 +128,7 @@ ethphy1: ethernet-phy@2 { &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; + fsl,use-minimum-ecc; nand-on-flash-bbt; nand-ecc-mode = "hw"; nand-ecc-strength = <8>; From 17c101d839f58cc4b977706719909871765fe7b9 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 6 May 2022 15:24:14 +0200 Subject: [PATCH 75/77] ARM: dts: imx6ull-colibri: add/update some comments Add/update some comments. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../dts/imx6ull-colibri-emmc-nonwifi.dtsi | 4 ++- arch/arm/boot/dts/imx6ull-colibri.dtsi | 36 ++++++++++++++----- 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi index 1d75bc671f75..ea238525d5c0 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi @@ -8,7 +8,7 @@ / { aliases { mmc0 = &usdhc2; /* eMMC */ - mmc1 = &usdhc1; /* MMC 4bit slot */ + mmc1 = &usdhc1; /* MMC 4-bit slot */ }; memory@80000000 { @@ -154,6 +154,7 @@ &gpio5 { "SODIMM_127"; }; +/* NAND */ &gpmi { status = "disabled"; }; @@ -170,6 +171,7 @@ &iomuxc_snvs { pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>; }; +/* eMMC */ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2emmc>; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 5e0cee146121..4611fa890889 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -6,6 +6,7 @@ #include "imx6ull.dtsi" / { + /* Ethernet aliases to ensure correct MAC addresses */ aliases { ethernet0 = &fec2; ethernet1 = &fec1; @@ -104,6 +105,7 @@ &ecspi1 { pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; }; +/* Ethernet */ &fec2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_enet2>; @@ -125,6 +127,7 @@ ethphy1: ethernet-phy@2 { }; }; +/* NAND */ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; @@ -136,6 +139,7 @@ &gpmi { status = "okay"; }; +/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; @@ -157,6 +161,10 @@ atmel_mxt_ts: touchscreen@4a { }; }; +/* + * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + * touch screen controller + */ &i2c2 { /* Use low frequency to compensate for the high pull-up values. */ clock-frequency = <40000>; @@ -196,21 +204,25 @@ lcdif_out: endpoint { }; }; +/* PWM */ &pwm4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm4>; }; +/* PWM */ &pwm5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm5>; }; +/* PWM */ &pwm6 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm6>; }; +/* PWM */ &pwm7 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm7>; @@ -224,6 +236,7 @@ &snvs_pwrkey { status = "disabled"; }; +/* Colibri UART_A */ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; @@ -231,6 +244,7 @@ &uart1 { fsl,dte-mode; }; +/* Colibri UART_B */ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; @@ -238,12 +252,14 @@ &uart2 { fsl,dte-mode; }; +/* Colibri UART_C */ &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5>; fsl,dte-mode; }; +/* Colibri USBC */ &usbotg1 { dr_mode = "otg"; srp-disable; @@ -251,10 +267,12 @@ &usbotg1 { adp-disable; }; +/* Colibri USBH */ &usbotg2 { dr_mode = "host"; }; +/* Colibri MMC/SD */ &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; @@ -265,7 +283,7 @@ &usdhc1 { assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; assigned-clock-rates = <0>, <198000000>; bus-width = <4>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */ disable-wp; keep-power-in-suspend; no-1-8-v; @@ -431,7 +449,7 @@ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ /* * With an eMMC instead of a raw NAND device the following pins - * are available at SODIMM pins + * are available at SODIMM pins. */ pinctrl_gpmi_gpio: gpmi-gpio-grp { fsl,pins = < @@ -556,10 +574,10 @@ MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */ pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */ fsl,pins = < - MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 */ - MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 */ - MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 */ - MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 */ + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */ + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */ + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */ + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */ >; }; @@ -580,7 +598,7 @@ MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */ pinctrl_usbh_reg: gpio-usbh-reg { fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */ + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */ >; }; @@ -658,7 +676,7 @@ pinctrl_snvs_gpio1: snvs-gpio1-grp { MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */ - MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 */ + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ >; }; @@ -695,7 +713,7 @@ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 */ pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp { fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 */ + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */ >; }; From a5fa132bbe4f66e4b3eea1085015a281477fa905 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 6 May 2022 15:24:15 +0200 Subject: [PATCH 76/77] ARM: dts: imx6ull-colibri: move gpio-keys node to som dtsi The gpio-keys define module level wake-up pin functionality. Move it from the carrier board dts file to the Som dtsi file. While at it, also re-order the properties in the gpio-keys node alphabetically and rename to sub-node from power to wakeup. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 15 --------------- arch/arm/boot/dts/imx6ull-colibri.dtsi | 16 +++++++++++++++- 2 files changed, 15 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi index 08197c66af12..e29907428c20 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi @@ -8,20 +8,6 @@ chosen { stdout-path = "serial0:115200n8"; }; - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_snvs_gpiokeys>; - - power { - label = "Wake-Up"; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; - /* fixed crystal dedicated to mcp2515 */ clk16m: clk16m { compatible = "fixed-clock"; @@ -29,7 +15,6 @@ clk16m: clk16m { clock-frequency = <16000000>; }; - reg_3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "3.3V"; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 4611fa890889..4292311bdc6e 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -24,6 +24,20 @@ backlight: backlight { status = "okay"; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + + wakeup { + debounce-interval = <10>; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + panel_dpi: panel-dpi { compatible = "edt,et057090dhu"; backlight = <&backlight>; @@ -707,7 +721,7 @@ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0 pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp { fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 */ + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */ >; }; From 19a434aa3ebc29fda4799454afe882a5edcb1b94 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 6 May 2022 15:24:16 +0200 Subject: [PATCH 77/77] ARM: dts: imx6ull-colibri: improve pinctrl node names Improve on pinctrl node names. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-colibri.dtsi | 93 +++++++++++++------------- 1 file changed, 46 insertions(+), 47 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 4292311bdc6e..15ebabcacfc5 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -292,7 +292,7 @@ &usdhc1 { pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; - pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; assigned-clock-rates = <0>, <198000000>; @@ -312,7 +312,6 @@ &wdog1 { }; &iomuxc { - pinctrl_adc1: adc1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */ @@ -336,13 +335,13 @@ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ >; }; - pinctrl_can_int: canint-grp { + pinctrl_can_int: canintgrp { fsl,pins = < MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ >; }; - pinctrl_enet2: enet2-grp { + pinctrl_enet2: enet2grp { fsl,pins = < MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 @@ -357,7 +356,7 @@ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 >; }; - pinctrl_enet2_sleep: enet2sleepgrp { + pinctrl_enet2_sleep: enet2-sleepgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0 MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0 @@ -372,13 +371,13 @@ MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0 >; }; - pinctrl_ecspi1_cs: ecspi1-cs-grp { + pinctrl_ecspi1_cs: ecspi1csgrp { fsl,pins = < MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */ >; }; - pinctrl_ecspi1: ecspi1-grp { + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */ MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */ @@ -386,27 +385,27 @@ MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */ >; }; - pinctrl_flexcan1: flexcan1-grp { + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 >; }; - pinctrl_flexcan2: flexcan2-grp { + pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 >; }; - pinctrl_gpio_bl_on: gpio-bl-on-grp { + pinctrl_gpio_bl_on: gpioblongrp { fsl,pins = < MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */ >; }; - pinctrl_gpio1: gpio1-grp { + pinctrl_gpio1: gpio1grp { fsl,pins = < MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */ MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */ @@ -419,7 +418,7 @@ MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */ >; }; - pinctrl_gpio2: gpio2-grp { /* Camera */ + pinctrl_gpio2: gpio2grp { /* Camera */ fsl,pins = < MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */ MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */ @@ -429,20 +428,20 @@ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */ >; }; - pinctrl_gpio3: gpio3-grp { /* CAN2 */ + pinctrl_gpio3: gpio3grp { /* CAN2 */ fsl,pins = < MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */ MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */ >; }; - pinctrl_gpio4: gpio4-grp { + pinctrl_gpio4: gpio4grp { fsl,pins = < MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */ >; }; - pinctrl_gpio6: gpio6-grp { /* Wifi pins */ + pinctrl_gpio6: gpio6grp { /* Wifi pins */ fsl,pins = < MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */ MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */ @@ -454,7 +453,7 @@ MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */ >; }; - pinctrl_gpio7: gpio7-grp { /* CAN1 */ + pinctrl_gpio7: gpio7grp { /* CAN1 */ fsl,pins = < MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ @@ -465,7 +464,7 @@ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ * With an eMMC instead of a raw NAND device the following pins * are available at SODIMM pins. */ - pinctrl_gpmi_gpio: gpmi-gpio-grp { + pinctrl_gpmi_gpio: gpmigpiogrp { fsl,pins = < MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */ MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */ @@ -474,7 +473,7 @@ MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SODIMM 142 */ >; }; - pinctrl_gpmi_nand: gpmi-nand-grp { + pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 @@ -493,35 +492,35 @@ MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 >; }; - pinctrl_i2c1: i2c1-grp { + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */ >; }; - pinctrl_i2c1_gpio: i2c1-gpio-grp { + pinctrl_i2c1_gpio: i2c1-gpiogrp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */ >; }; - pinctrl_i2c2: i2c2-grp { + pinctrl_i2c2: i2c2grp { fsl,pins = < MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0 >; }; - pinctrl_i2c2_gpio: i2c2-gpio-grp { + pinctrl_i2c2_gpio: i2c2-gpiogrp { fsl,pins = < MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0 >; }; - pinctrl_lcdif_dat: lcdif-dat-grp { + pinctrl_lcdif_dat: lcdifdatgrp { fsl,pins = < MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */ @@ -544,7 +543,7 @@ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */ >; }; - pinctrl_lcdif_ctrl: lcdif-ctrl-grp { + pinctrl_lcdif_ctrl: lcdifctrlgrp { fsl,pins = < MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */ @@ -553,31 +552,31 @@ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */ >; }; - pinctrl_pwm4: pwm4-grp { + pinctrl_pwm4: pwm4grp { fsl,pins = < MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */ >; }; - pinctrl_pwm5: pwm5-grp { + pinctrl_pwm5: pwm5grp { fsl,pins = < MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */ >; }; - pinctrl_pwm6: pwm6-grp { + pinctrl_pwm6: pwm6grp { fsl,pins = < MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */ >; }; - pinctrl_pwm7: pwm7-grp { + pinctrl_pwm7: pwm7grp { fsl,pins = < MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */ >; }; - pinctrl_uart1: uart1-grp { + pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */ MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */ @@ -586,7 +585,7 @@ MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */ >; }; - pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */ + pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */ fsl,pins = < MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */ MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */ @@ -595,7 +594,7 @@ MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */ >; }; - pinctrl_uart2: uart2-grp { + pinctrl_uart2: uart2grp { fsl,pins = < MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */ MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */ @@ -603,20 +602,20 @@ MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */ MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */ >; }; - pinctrl_uart5: uart5-grp { + pinctrl_uart5: uart5grp { fsl,pins = < MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */ MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */ >; }; - pinctrl_usbh_reg: gpio-usbh-reg { + pinctrl_usbh_reg: usbhreggrp { fsl,pins = < MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */ >; }; - pinctrl_usdhc1: usdhc1-grp { + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */ @@ -627,7 +626,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */ >; }; - pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 @@ -638,7 +637,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 >; }; - pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 @@ -649,7 +648,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 >; }; - pinctrl_usdhc2: usdhc2-grp { + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069 @@ -677,7 +676,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 >; }; - pinctrl_wdog: wdog-grp { + pinctrl_wdog: wdoggrp { fsl,pins = < MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 >; @@ -685,7 +684,7 @@ MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 }; &iomuxc_snvs { - pinctrl_snvs_gpio1: snvs-gpio1-grp { + pinctrl_snvs_gpio1: snvsgpio1grp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ @@ -695,49 +694,49 @@ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ >; }; - pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */ + pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */ fsl,pins = < MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */ >; }; - pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */ + pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */ fsl,pins = < MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0 >; }; - pinctrl_snvs_reg_sd: snvs-reg-sd-grp { + pinctrl_snvs_reg_sd: snvsregsdgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0 >; }; - pinctrl_snvs_usbc_det: snvs-usbc-det-grp { + pinctrl_snvs_usbc_det: snvsusbcdetgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0 >; }; - pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp { + pinctrl_snvs_gpiokeys: snvsgpiokeysgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */ >; }; - pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp { + pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */ >; }; - pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-grp-slp { + pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 >; }; - pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp { + pinctrl_snvs_wifi_pdn: snvswifipdngrp { fsl,pins = < MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 >;