From 2ea9fe3021d0bcfe9f3df15fae317c7376c3ab97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Wed, 24 Jun 2026 09:38:29 +0200 Subject: [PATCH] drm/amdgpu: Fix typos in comments for IP block soft reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These typos were accidentally overlooked. Let's fix them now. Signed-off-by: Timur Kristóf Reviewed-by: Tvrtko Ursulin Link: https://patch.msgid.link/20260624073829.40835-2-timur.kristof@gmail.com Signed-off-by: Mario Limonciello Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 6e6aadba006c..4d417c4a5cd2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -996,7 +996,7 @@ void amdgpu_multi_ring_reset_helper_begin(const u32 ring_type_mask, * Give some time for non-guilty rings to finish their * current submission, to try to minimize collateral damage. * - * Note that this just a best effort, but really there + * Note that this is just a best effort, but really there * is no way to really know which ring is actually responsible * because different rings may share resources, eg. a compute * ring may hog shader engines, causing a graphics ring to hang. @@ -1057,12 +1057,12 @@ void amdgpu_multi_ring_reset_helper_begin(const u32 ring_type_mask, * @guilty_ring: The ring which is guilty of causing a reset. * @ret: Return code from the reset function. * - * After calling amdgpu_multi_ring_reset_helper_end() + * After calling amdgpu_multi_ring_reset_helper_begin() * and executing the actual reset method, call this * function to restore normal operation. * * In case the reset failed, this function should still - * be called to restore some state, but it won't attempt to + * be called to restore preemption state, but it won't attempt to * fully restore the ring contents. */ int amdgpu_multi_ring_reset_helper_end(const u32 ring_type_mask, @@ -1086,7 +1086,7 @@ int amdgpu_multi_ring_reset_helper_end(const u32 ring_type_mask, /* Flush HDP cache so the GPU can see the updated COND_EXEC values */ amdgpu_device_flush_hdp(adev, NULL); - /* If the reset was unsuccessful, return without restoring anything. */ + /* If the reset was unsuccessful, return without restoring anything else. */ if (ret) return ret;