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Merge tag 'pinctrl-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij: "Core changes: - Use DEFINE_SHOW_STORE_ATTRIBUTE() in debugfs entries New drivers: - Qualcomm PMIH0108, PMD8028, PMXR2230 and PM6450 pin control support Improvements: - Serious cleanup of the recently merged aw9523 driver - Fix PIN_CONFIG_BIAS_DISABLE handling in pinctrl-single - A slew of device tree binding cleanups - Support a bus clock in the Samsung driver" * tag 'pinctrl-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits) pinctrl: bcm2835: Make pin freeing behavior configurable dt-bindings: pinctrl: qcom,pmic-gpio: Fix "comptaible" typo for PMIH0108 pinctrl: qcom: pinctrl-sm7150: Fix sdc1 and ufs special pins regs dt-bindings: pinctrl: mediatek: mt7622: add "antsel" function dt-bindings: pinctrl: mediatek: mt7622: fix array properties pinctrl: samsung: drop redundant drvdata assignment pinctrl: samsung: support a bus clock dt-bindings: pinctrl: samsung: google,gs101-pinctrl needs a clock pinctrl: renesas: rzg2l: Limit 2.5V power supply to Ethernet interfaces pinctrl: renesas: r8a779h0: Add INTC-EX pins, groups, and function pinctrl: renesas: r8a779h0: Fix IRQ suffixes pinctrl: renesas: rzg2l: Remove extra space in function parameter dt-bindings: pinctrl: qcom,pmic-mpp: add support for PM8901 pinctrl: pinconf-generic: print hex value pinctrl: realtek: fix module autoloading pinctrl: qcom: sm7150: fix module autoloading pinctrl: loongson2: fix module autoloading pinctrl: mediatek: fix module autoloading pinctrl: freescale: imx8ulp: fix module autoloading dt-bindings: pinctrl: qcom,pmic-gpio: Allow gpio-hog nodes ...
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Linus Torvalds
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Samsung's Exynos pinctrl bindings
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*
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* Copyright (c) 2016 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Author: Krzysztof Kozlowski <krzk@kernel.org>
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*/
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#ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__
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#define __DT_BINDINGS_PINCTRL_SAMSUNG_H__
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/*
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* These bindings are deprecated, because they do not match the actual
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* concept of bindings but rather contain pure register values.
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* Instead include the header in the DTS source directory.
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*/
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#warning "These bindings are deprecated. Instead use the header in the DTS source directory."
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#define EXYNOS_PIN_PULL_NONE 0
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#define EXYNOS_PIN_PULL_DOWN 1
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#define EXYNOS_PIN_PULL_UP 3
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#define S3C64XX_PIN_PULL_NONE 0
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#define S3C64XX_PIN_PULL_DOWN 1
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#define S3C64XX_PIN_PULL_UP 2
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/* Pin function in power down mode */
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#define EXYNOS_PIN_PDN_OUT0 0
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#define EXYNOS_PIN_PDN_OUT1 1
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#define EXYNOS_PIN_PDN_INPUT 2
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#define EXYNOS_PIN_PDN_PREV 3
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/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */
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#define EXYNOS4_PIN_DRV_LV1 0
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#define EXYNOS4_PIN_DRV_LV2 2
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#define EXYNOS4_PIN_DRV_LV3 1
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#define EXYNOS4_PIN_DRV_LV4 3
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/* Drive strengths for Exynos5260 */
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#define EXYNOS5260_PIN_DRV_LV1 0
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#define EXYNOS5260_PIN_DRV_LV2 1
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#define EXYNOS5260_PIN_DRV_LV4 2
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#define EXYNOS5260_PIN_DRV_LV6 3
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/*
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* Drive strengths for Exynos5410, Exynos542x, Exynos5800 and Exynos850 (except
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* GPIO_HSI block)
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*/
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#define EXYNOS5420_PIN_DRV_LV1 0
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#define EXYNOS5420_PIN_DRV_LV2 1
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#define EXYNOS5420_PIN_DRV_LV3 2
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#define EXYNOS5420_PIN_DRV_LV4 3
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/* Drive strengths for Exynos5433 */
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#define EXYNOS5433_PIN_DRV_FAST_SR1 0
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#define EXYNOS5433_PIN_DRV_FAST_SR2 1
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#define EXYNOS5433_PIN_DRV_FAST_SR3 2
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#define EXYNOS5433_PIN_DRV_FAST_SR4 3
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#define EXYNOS5433_PIN_DRV_FAST_SR5 4
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#define EXYNOS5433_PIN_DRV_FAST_SR6 5
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#define EXYNOS5433_PIN_DRV_SLOW_SR1 8
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#define EXYNOS5433_PIN_DRV_SLOW_SR2 9
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#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa
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#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb
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#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc
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#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf
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/* Drive strengths for Exynos850 GPIO_HSI block */
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#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */
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#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */
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#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */
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#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */
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#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */
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#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */
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#define EXYNOS_PIN_FUNC_INPUT 0
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#define EXYNOS_PIN_FUNC_OUTPUT 1
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#define EXYNOS_PIN_FUNC_2 2
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#define EXYNOS_PIN_FUNC_3 3
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#define EXYNOS_PIN_FUNC_4 4
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#define EXYNOS_PIN_FUNC_5 5
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#define EXYNOS_PIN_FUNC_6 6
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#define EXYNOS_PIN_FUNC_EINT 0xf
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#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT
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/* Drive strengths for Exynos7 FSYS1 block */
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#define EXYNOS7_FSYS1_PIN_DRV_LV1 0
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#define EXYNOS7_FSYS1_PIN_DRV_LV2 4
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#define EXYNOS7_FSYS1_PIN_DRV_LV3 2
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#define EXYNOS7_FSYS1_PIN_DRV_LV4 6
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#define EXYNOS7_FSYS1_PIN_DRV_LV5 1
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#define EXYNOS7_FSYS1_PIN_DRV_LV6 5
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#endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */
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