From 9f30b6b1a957b3d4cbfd97738ef2b02291aaf394 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Fri, 25 May 2018 15:42:06 +0800 Subject: [PATCH 01/96] ARM: dts: imx: Add basic dtsi file for imx6sll Add dtsi file for imx6sll. Signed-off-by: Bai Ping Reviewed-by: Rob Herring Acked-by: Dong Aisheng Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-pinfunc.h | 880 ++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6sll.dtsi | 780 ++++++++++++++++++++++++ 2 files changed, 1660 insertions(+) create mode 100644 arch/arm/boot/dts/imx6sll-pinfunc.h create mode 100644 arch/arm/boot/dts/imx6sll.dtsi diff --git a/arch/arm/boot/dts/imx6sll-pinfunc.h b/arch/arm/boot/dts/imx6sll-pinfunc.h new file mode 100644 index 000000000000..b1c40dcdb42f --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-pinfunc.h @@ -0,0 +1,880 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + */ + +#ifndef __DTS_IMX6SLL_PINFUNC_H +#define __DTS_IMX6SLL_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0 +#define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0 +#define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0 +#define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0 +#define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0 +#define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0 +#define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0 +#define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_24M__SD3_WP 0x0018 0x02E0 0x0794 0x6 0x0 +#define MX6SLL_PAD_REF_CLK_32K__XTALOSC_REF_CLK_32K 0x001C 0x02E4 0x0000 0x0 0x0 +#define MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x001C 0x02E4 0x0690 0x1 0x0 +#define MX6SLL_PAD_REF_CLK_32K__PWM4_OUT 0x001C 0x02E4 0x0000 0x2 0x0 +#define MX6SLL_PAD_REF_CLK_32K__USB_OTG1_ID 0x001C 0x02E4 0x055C 0x3 0x0 +#define MX6SLL_PAD_REF_CLK_32K__SD1_LCTL 0x001C 0x02E4 0x0000 0x4 0x0 +#define MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x001C 0x02E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_REF_CLK_32K__SD3_CD_B 0x001C 0x02E4 0x0780 0x6 0x0 +#define MX6SLL_PAD_PWM1__PWM1_OUT 0x0020 0x02E8 0x0000 0x0 0x0 +#define MX6SLL_PAD_PWM1__CCM_CLKO 0x0020 0x02E8 0x0000 0x1 0x0 +#define MX6SLL_PAD_PWM1__AUDIO_CLK_OUT 0x0020 0x02E8 0x0000 0x2 0x0 +#define MX6SLL_PAD_PWM1__CSI_MCLK 0x0020 0x02E8 0x0000 0x4 0x0 +#define MX6SLL_PAD_PWM1__GPIO3_IO23 0x0020 0x02E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_PWM1__EPIT1_OUT 0x0020 0x02E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL0__KEY_COL0 0x0024 0x02EC 0x06A0 0x0 0x0 +#define MX6SLL_PAD_KEY_COL0__I2C2_SCL 0x0024 0x02EC 0x0684 0x1 0x0 +#define MX6SLL_PAD_KEY_COL0__LCD_DATA00 0x0024 0x02EC 0x06D8 0x2 0x0 +#define MX6SLL_PAD_KEY_COL0__SD1_CD_B 0x0024 0x02EC 0x0770 0x4 0x1 +#define MX6SLL_PAD_KEY_COL0__GPIO3_IO24 0x0024 0x02EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW0__KEY_ROW0 0x0028 0x02F0 0x06C0 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW0__I2C2_SDA 0x0028 0x02F0 0x0688 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW0__LCD_DATA01 0x0028 0x02F0 0x06DC 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW0__SD1_WP 0x0028 0x02F0 0x0774 0x4 0x1 +#define MX6SLL_PAD_KEY_ROW0__GPIO3_IO25 0x0028 0x02F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL1__KEY_COL1 0x002C 0x02F4 0x06A4 0x0 0x0 +#define MX6SLL_PAD_KEY_COL1__ECSPI4_MOSI 0x002C 0x02F4 0x0658 0x1 0x1 +#define MX6SLL_PAD_KEY_COL1__LCD_DATA02 0x002C 0x02F4 0x06E0 0x2 0x0 +#define MX6SLL_PAD_KEY_COL1__SD3_DATA4 0x002C 0x02F4 0x0784 0x4 0x0 +#define MX6SLL_PAD_KEY_COL1__GPIO3_IO26 0x002C 0x02F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW1__KEY_ROW1 0x0030 0x02F8 0x06C4 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW1__ECSPI4_MISO 0x0030 0x02F8 0x0654 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW1__LCD_DATA03 0x0030 0x02F8 0x06E4 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW1__CSI_FIELD 0x0030 0x02F8 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW1__SD3_DATA5 0x0030 0x02F8 0x0788 0x4 0x0 +#define MX6SLL_PAD_KEY_ROW1__GPIO3_IO27 0x0030 0x02F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL2__KEY_COL2 0x0034 0x02FC 0x06A8 0x0 0x0 +#define MX6SLL_PAD_KEY_COL2__ECSPI4_SS0 0x0034 0x02FC 0x065C 0x1 0x1 +#define MX6SLL_PAD_KEY_COL2__LCD_DATA04 0x0034 0x02FC 0x06E8 0x2 0x0 +#define MX6SLL_PAD_KEY_COL2__CSI_DATA12 0x0034 0x02FC 0x05B8 0x3 0x1 +#define MX6SLL_PAD_KEY_COL2__SD3_DATA6 0x0034 0x02FC 0x078C 0x4 0x0 +#define MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x0034 0x02FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW2__KEY_ROW2 0x0038 0x0300 0x06C8 0x0 0x0 +#define MX6SLL_PAD_KEY_ROW2__ECSPI4_SCLK 0x0038 0x0300 0x0650 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW2__LCD_DATA05 0x0038 0x0300 0x06EC 0x2 0x0 +#define MX6SLL_PAD_KEY_ROW2__CSI_DATA13 0x0038 0x0300 0x05BC 0x3 0x1 +#define MX6SLL_PAD_KEY_ROW2__SD3_DATA7 0x0038 0x0300 0x0790 0x4 0x0 +#define MX6SLL_PAD_KEY_ROW2__GPIO3_IO29 0x0038 0x0300 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL3__KEY_COL3 0x003C 0x0304 0x06AC 0x0 0x0 +#define MX6SLL_PAD_KEY_COL3__AUD6_RXFS 0x003C 0x0304 0x05A0 0x1 0x1 +#define MX6SLL_PAD_KEY_COL3__LCD_DATA06 0x003C 0x0304 0x06F0 0x2 0x0 +#define MX6SLL_PAD_KEY_COL3__CSI_DATA14 0x003C 0x0304 0x05C0 0x3 0x1 +#define MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x003C 0x0304 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL3__SD1_RESET 0x003C 0x0304 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW3__KEY_ROW3 0x0040 0x0308 0x06CC 0x0 0x1 +#define MX6SLL_PAD_KEY_ROW3__AUD6_RXC 0x0040 0x0308 0x059C 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW3__LCD_DATA07 0x0040 0x0308 0x06F4 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW3__CSI_DATA15 0x0040 0x0308 0x05C4 0x3 0x2 +#define MX6SLL_PAD_KEY_ROW3__GPIO3_IO31 0x0040 0x0308 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW3__SD1_VSELECT 0x0040 0x0308 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL4__KEY_COL4 0x0044 0x030C 0x06B0 0x0 0x1 +#define MX6SLL_PAD_KEY_COL4__AUD6_RXD 0x0044 0x030C 0x0594 0x1 0x1 +#define MX6SLL_PAD_KEY_COL4__LCD_DATA08 0x0044 0x030C 0x06F8 0x2 0x1 +#define MX6SLL_PAD_KEY_COL4__CSI_DATA16 0x0044 0x030C 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x0044 0x030C 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL4__USB_OTG1_PWR 0x0044 0x030C 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW4__KEY_ROW4 0x0048 0x0310 0x06D0 0x0 0x1 +#define MX6SLL_PAD_KEY_ROW4__AUD6_TXC 0x0048 0x0310 0x05A4 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW4__LCD_DATA09 0x0048 0x0310 0x06FC 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW4__CSI_DATA17 0x0048 0x0310 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW4__GPIO4_IO01 0x0048 0x0310 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW4__USB_OTG1_OC 0x0048 0x0310 0x076C 0x6 0x2 +#define MX6SLL_PAD_KEY_COL5__KEY_COL5 0x004C 0x0314 0x0694 0x0 0x1 +#define MX6SLL_PAD_KEY_COL5__AUD6_TXFS 0x004C 0x0314 0x05A8 0x1 0x1 +#define MX6SLL_PAD_KEY_COL5__LCD_DATA10 0x004C 0x0314 0x0700 0x2 0x0 +#define MX6SLL_PAD_KEY_COL5__CSI_DATA18 0x004C 0x0314 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x004C 0x0314 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL5__USB_OTG2_PWR 0x004C 0x0314 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW5__KEY_ROW5 0x0050 0x0318 0x06B4 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW5__AUD6_TXD 0x0050 0x0318 0x0598 0x1 0x1 +#define MX6SLL_PAD_KEY_ROW5__LCD_DATA11 0x0050 0x0318 0x0704 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW5__CSI_DATA19 0x0050 0x0318 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x0050 0x0318 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW5__USB_OTG2_OC 0x0050 0x0318 0x0768 0x6 0x3 +#define MX6SLL_PAD_KEY_COL6__KEY_COL6 0x0054 0x031C 0x0698 0x0 0x2 +#define MX6SLL_PAD_KEY_COL6__UART4_DCE_RX 0x0054 0x031C 0x075C 0x1 0x2 +#define MX6SLL_PAD_KEY_COL6__UART4_DTE_TX 0x0054 0x031C 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_COL6__LCD_DATA12 0x0054 0x031C 0x0708 0x2 0x1 +#define MX6SLL_PAD_KEY_COL6__CSI_DATA20 0x0054 0x031C 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x0054 0x031C 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL6__SD3_RESET 0x0054 0x031C 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_ROW6__KEY_ROW6 0x0058 0x0320 0x06B8 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW6__UART4_DCE_TX 0x0058 0x0320 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW6__UART4_DTE_RX 0x0058 0x0320 0x075C 0x1 0x3 +#define MX6SLL_PAD_KEY_ROW6__LCD_DATA13 0x0058 0x0320 0x070C 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW6__CSI_DATA21 0x0058 0x0320 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW6__GPIO4_IO05 0x0058 0x0320 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW6__SD3_VSELECT 0x0058 0x0320 0x0000 0x6 0x0 +#define MX6SLL_PAD_KEY_COL7__KEY_COL7 0x005C 0x0324 0x069C 0x0 0x2 +#define MX6SLL_PAD_KEY_COL7__UART4_DCE_RTS 0x005C 0x0324 0x0758 0x1 0x2 +#define MX6SLL_PAD_KEY_COL7__UART4_DTE_CTS 0x005C 0x0324 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_COL7__LCD_DATA14 0x005C 0x0324 0x0710 0x2 0x1 +#define MX6SLL_PAD_KEY_COL7__CSI_DATA22 0x005C 0x0324 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_COL7__GPIO4_IO06 0x005C 0x0324 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_COL7__SD1_WP 0x005C 0x0324 0x0774 0x6 0x3 +#define MX6SLL_PAD_KEY_ROW7__KEY_ROW7 0x0060 0x0328 0x06BC 0x0 0x2 +#define MX6SLL_PAD_KEY_ROW7__UART4_DCE_CTS 0x0060 0x0328 0x0000 0x1 0x0 +#define MX6SLL_PAD_KEY_ROW7__UART4_DTE_RTS 0x0060 0x0328 0x0758 0x1 0x3 +#define MX6SLL_PAD_KEY_ROW7__LCD_DATA15 0x0060 0x0328 0x0714 0x2 0x1 +#define MX6SLL_PAD_KEY_ROW7__CSI_DATA23 0x0060 0x0328 0x0000 0x3 0x0 +#define MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x0060 0x0328 0x0000 0x5 0x0 +#define MX6SLL_PAD_KEY_ROW7__SD1_CD_B 0x0060 0x0328 0x0770 0x6 0x3 +#define MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x0064 0x032C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA00__ECSPI4_MOSI 0x0064 0x032C 0x0658 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA00__LCD_DATA24 0x0064 0x032C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA00__CSI_DATA00 0x0064 0x032C 0x05C8 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA00__GPIO1_IO07 0x0064 0x032C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x0068 0x0330 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA01__ECSPI4_MISO 0x0068 0x0330 0x0654 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA01__LCD_DATA25 0x0068 0x0330 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA01__CSI_DATA01 0x0068 0x0330 0x05CC 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA01__GPIO1_IO08 0x0068 0x0330 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x006C 0x0334 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA02__ECSPI4_SS0 0x006C 0x0334 0x065C 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA02__LCD_DATA26 0x006C 0x0334 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x006C 0x0334 0x05D0 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA02__GPIO1_IO09 0x006C 0x0334 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x0070 0x0338 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA03__ECSPI4_SCLK 0x0070 0x0338 0x0650 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA03__LCD_DATA27 0x0070 0x0338 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x0070 0x0338 0x05D4 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA03__GPIO1_IO10 0x0070 0x0338 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x0074 0x033C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA04__ECSPI4_SS1 0x0074 0x033C 0x0660 0x1 0x1 +#define MX6SLL_PAD_EPDC_DATA04__LCD_DATA28 0x0074 0x033C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x0074 0x033C 0x05D8 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA04__GPIO1_IO11 0x0074 0x033C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x0078 0x0340 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA05__ECSPI4_SS2 0x0078 0x0340 0x0664 0x1 0x1 +#define MX6SLL_PAD_EPDC_DATA05__LCD_DATA29 0x0078 0x0340 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x0078 0x0340 0x05DC 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA05__GPIO1_IO12 0x0078 0x0340 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x007C 0x0344 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA06__ECSPI4_SS3 0x007C 0x0344 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA06__LCD_DATA30 0x007C 0x0344 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x007C 0x0344 0x05E0 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA06__GPIO1_IO13 0x007C 0x0344 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x0080 0x0348 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA07__ECSPI4_RDY 0x0080 0x0348 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA07__LCD_DATA31 0x0080 0x0348 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x0080 0x0348 0x05E4 0x3 0x2 +#define MX6SLL_PAD_EPDC_DATA07__GPIO1_IO14 0x0080 0x0348 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x0084 0x034C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA08__ECSPI3_MOSI 0x0084 0x034C 0x063C 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA08__EPDC_PWR_CTRL0 0x0084 0x034C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA08__GPIO1_IO15 0x0084 0x034C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x0088 0x0350 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA09__ECSPI3_MISO 0x0088 0x0350 0x0638 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA09__EPDC_PWR_CTRL1 0x0088 0x0350 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA09__GPIO1_IO16 0x0088 0x0350 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x008C 0x0354 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA10__ECSPI3_SS0 0x008C 0x0354 0x0648 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA10__EPDC_PWR_CTRL2 0x008C 0x0354 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA10__GPIO1_IO17 0x008C 0x0354 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x0090 0x0358 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA11__ECSPI3_SCLK 0x0090 0x0358 0x0630 0x1 0x2 +#define MX6SLL_PAD_EPDC_DATA11__EPDC_PWR_CTRL3 0x0090 0x0358 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA11__GPIO1_IO18 0x0090 0x0358 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x0094 0x035C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA12__UART2_DCE_RX 0x0094 0x035C 0x074C 0x1 0x4 +#define MX6SLL_PAD_EPDC_DATA12__UART2_DTE_TX 0x0094 0x035C 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA12__EPDC_PWR_COM 0x0094 0x035C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA12__GPIO1_IO19 0x0094 0x035C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA12__ECSPI3_SS1 0x0094 0x035C 0x064C 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x0098 0x0360 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA13__UART2_DCE_TX 0x0098 0x0360 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA13__UART2_DTE_RX 0x0098 0x0360 0x074C 0x1 0x5 +#define MX6SLL_PAD_EPDC_DATA13__EPDC_PWR_IRQ 0x0098 0x0360 0x0668 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA13__GPIO1_IO20 0x0098 0x0360 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA13__ECSPI3_SS2 0x0098 0x0360 0x0640 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x009C 0x0364 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA14__UART2_DCE_RTS 0x009C 0x0364 0x0748 0x1 0x4 +#define MX6SLL_PAD_EPDC_DATA14__UART2_DTE_CTS 0x009C 0x0364 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA14__EPDC_PWR_STAT 0x009C 0x0364 0x066C 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA14__GPIO1_IO21 0x009C 0x0364 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA14__ECSPI3_SS3 0x009C 0x0364 0x0644 0x6 0x1 +#define MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x00A0 0x0368 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_DATA15__UART2_DCE_CTS 0x00A0 0x0368 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_DATA15__UART2_DTE_RTS 0x00A0 0x0368 0x0748 0x1 0x5 +#define MX6SLL_PAD_EPDC_DATA15__EPDC_PWR_WAKE 0x00A0 0x0368 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_DATA15__GPIO1_IO22 0x00A0 0x0368 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_DATA15__ECSPI3_RDY 0x00A0 0x0368 0x0634 0x6 0x1 +#define MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x00A4 0x036C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCLK__ECSPI2_MOSI 0x00A4 0x036C 0x0624 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__I2C2_SCL 0x00A4 0x036C 0x0684 0x2 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x00A4 0x036C 0x05E8 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDCLK__GPIO1_IO23 0x00A4 0x036C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x00A8 0x0370 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDLE__ECSPI2_MISO 0x00A8 0x0370 0x0620 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDLE__I2C2_SDA 0x00A8 0x0370 0x0688 0x2 0x2 +#define MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x00A8 0x0370 0x05EC 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDLE__GPIO1_IO24 0x00A8 0x0370 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x00AC 0x0374 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDOE__ECSPI2_SS0 0x00AC 0x0374 0x0628 0x1 0x1 +#define MX6SLL_PAD_EPDC_SDOE__CSI_DATA10 0x00AC 0x0374 0x05B0 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x00AC 0x0374 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x00B0 0x0378 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__ECSPI2_SCLK 0x00B0 0x0378 0x061C 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDSHR__EPDC_SDCE4 0x00B0 0x0378 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDSHR__CSI_DATA11 0x00B0 0x0378 0x05B4 0x3 0x2 +#define MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x00B0 0x0378 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x00B4 0x037C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__ECSPI2_SS1 0x00B4 0x037C 0x062C 0x1 0x1 +#define MX6SLL_PAD_EPDC_SDCE0__PWM3_OUT 0x00B4 0x037C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE0__GPIO1_IO27 0x00B4 0x037C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x00B8 0x0380 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__WDOG2_B 0x00B8 0x0380 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__PWM4_OUT 0x00B8 0x0380 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE1__GPIO1_IO28 0x00B8 0x0380 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x00BC 0x0384 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x00BC 0x0384 0x068C 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCE2__PWM1_OUT 0x00BC 0x0384 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x00BC 0x0384 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__EPDC_SDCE3 0x00C0 0x0388 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x00C0 0x0388 0x0690 0x1 0x2 +#define MX6SLL_PAD_EPDC_SDCE3__PWM2_OUT 0x00C0 0x0388 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x00C0 0x0388 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x00C4 0x038C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__ECSPI2_SS2 0x00C4 0x038C 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x00C4 0x038C 0x05F4 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDCLK__GPIO1_IO31 0x00C4 0x038C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDCLK__SD2_RESET 0x00C4 0x038C 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x00C8 0x0390 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDOE__ECSPI2_SS3 0x00C8 0x0390 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x00C8 0x0390 0x05F0 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDOE__GPIO2_IO00 0x00C8 0x0390 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDOE__SD2_VSELECT 0x00C8 0x0390 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x00CC 0x0394 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDRL__ECSPI2_RDY 0x00CC 0x0394 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x00CC 0x0394 0x0000 0x3 0x0 +#define MX6SLL_PAD_EPDC_GDRL__GPIO2_IO01 0x00CC 0x0394 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDRL__SD2_WP 0x00CC 0x0394 0x077C 0x6 0x2 +#define MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x00D0 0x0398 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_GDSP__PWM4_OUT 0x00D0 0x0398 0x0000 0x1 0x0 +#define MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x00D0 0x0398 0x05F8 0x3 0x2 +#define MX6SLL_PAD_EPDC_GDSP__GPIO2_IO02 0x00D0 0x0398 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_GDSP__SD2_CD_B 0x00D0 0x0398 0x0778 0x6 0x2 +#define MX6SLL_PAD_EPDC_VCOM0__EPDC_VCOM0 0x00D4 0x039C 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__AUD5_RXFS 0x00D4 0x039C 0x0588 0x1 0x1 +#define MX6SLL_PAD_EPDC_VCOM0__UART3_DCE_RX 0x00D4 0x039C 0x0754 0x2 0x4 +#define MX6SLL_PAD_EPDC_VCOM0__UART3_DTE_TX 0x00D4 0x039C 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x00D4 0x039C 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_VCOM0__EPDC_SDCE5 0x00D4 0x039C 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__EPDC_VCOM1 0x00D8 0x03A0 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__AUD5_RXD 0x00D8 0x03A0 0x057C 0x1 0x1 +#define MX6SLL_PAD_EPDC_VCOM1__UART3_DCE_TX 0x00D8 0x03A0 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__UART3_DTE_RX 0x00D8 0x03A0 0x0754 0x2 0x5 +#define MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x00D8 0x03A0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_VCOM1__EPDC_SDCE6 0x00D8 0x03A0 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_BDR0__EPDC_BDR0 0x00DC 0x03A4 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_BDR0__UART3_DCE_RTS 0x00DC 0x03A4 0x0750 0x2 0x2 +#define MX6SLL_PAD_EPDC_BDR0__UART3_DTE_CTS 0x00DC 0x03A4 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_BDR0__GPIO2_IO05 0x00DC 0x03A4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_BDR0__EPDC_SDCE7 0x00DC 0x03A4 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_BDR1__EPDC_BDR1 0x00E0 0x03A8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_BDR1__UART3_DCE_CTS 0x00E0 0x03A8 0x0000 0x2 0x0 +#define MX6SLL_PAD_EPDC_BDR1__UART3_DTE_RTS 0x00E0 0x03A8 0x0750 0x2 0x3 +#define MX6SLL_PAD_EPDC_BDR1__GPIO2_IO06 0x00E0 0x03A8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_BDR1__EPDC_SDCE8 0x00E0 0x03A8 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__EPDC_PWR_CTRL0 0x00E4 0x03AC 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__AUD5_RXC 0x00E4 0x03AC 0x0584 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__LCD_DATA16 0x00E4 0x03AC 0x0718 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x00E4 0x03AC 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__EPDC_PWR_CTRL1 0x00E8 0x03B0 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__AUD5_TXFS 0x00E8 0x03B0 0x0590 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__LCD_DATA17 0x00E8 0x03B0 0x071C 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x00E8 0x03B0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__EPDC_PWR_CTRL2 0x00EC 0x03B4 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__AUD5_TXD 0x00EC 0x03B4 0x0580 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__LCD_DATA18 0x00EC 0x03B4 0x0720 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x00EC 0x03B4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__EPDC_PWR_CTRL3 0x00F0 0x03B8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__AUD5_TXC 0x00F0 0x03B8 0x058C 0x1 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__LCD_DATA19 0x00F0 0x03B8 0x0724 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x00F0 0x03B8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00F4 0x03BC 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__LCD_DATA20 0x00F4 0x03BC 0x0728 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x00F4 0x03BC 0x055C 0x4 0x4 +#define MX6SLL_PAD_EPDC_PWR_COM__GPIO2_IO11 0x00F4 0x03BC 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_COM__SD3_RESET 0x00F4 0x03BC 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_IRQ__EPDC_PWR_IRQ 0x00F8 0x03C0 0x0668 0x0 0x1 +#define MX6SLL_PAD_EPDC_PWR_IRQ__LCD_DATA21 0x00F8 0x03C0 0x072C 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_IRQ__USB_OTG2_ID 0x00F8 0x03C0 0x0560 0x4 0x3 +#define MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x00F8 0x03C0 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_IRQ__SD3_VSELECT 0x00F8 0x03C0 0x0000 0x6 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00FC 0x03C4 0x066C 0x0 0x1 +#define MX6SLL_PAD_EPDC_PWR_STAT__LCD_DATA22 0x00FC 0x03C4 0x0730 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_STAT__ARM_EVENTI 0x00FC 0x03C4 0x0000 0x4 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x00FC 0x03C4 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_STAT__SD3_WP 0x00FC 0x03C4 0x0794 0x6 0x2 +#define MX6SLL_PAD_EPDC_PWR_WAKE__EPDC_PWR_WAKE 0x0100 0x03C8 0x0000 0x0 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__LCD_DATA23 0x0100 0x03C8 0x0734 0x2 0x1 +#define MX6SLL_PAD_EPDC_PWR_WAKE__ARM_EVENTO 0x0100 0x03C8 0x0000 0x4 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x0100 0x03C8 0x0000 0x5 0x0 +#define MX6SLL_PAD_EPDC_PWR_WAKE__SD3_CD_B 0x0100 0x03C8 0x0780 0x6 0x2 +#define MX6SLL_PAD_LCD_CLK__LCD_CLK 0x0104 0x03CC 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_CLK__LCD_WR_RWN 0x0104 0x03CC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_CLK__PWM4_OUT 0x0104 0x03CC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x0104 0x03CC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x0108 0x03D0 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_ENABLE__LCD_RD_E 0x0108 0x03D0 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_ENABLE__UART2_DCE_RX 0x0108 0x03D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_ENABLE__UART2_DTE_TX 0x0108 0x03D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x0108 0x03D0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x010C 0x03D4 0x06D4 0x0 0x0 +#define MX6SLL_PAD_LCD_HSYNC__LCD_CS 0x010C 0x03D4 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_HSYNC__UART2_DCE_TX 0x010C 0x03D4 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_HSYNC__UART2_DTE_RX 0x010C 0x03D4 0x074C 0x4 0x1 +#define MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x010C 0x03D4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_HSYNC__ARM_TRACE_CLK 0x010C 0x03D4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x0110 0x03D8 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_VSYNC__LCD_RS 0x0110 0x03D8 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_VSYNC__UART2_DCE_RTS 0x0110 0x03D8 0x0748 0x4 0x0 +#define MX6SLL_PAD_LCD_VSYNC__UART2_DTE_CTS 0x0110 0x03D8 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x0110 0x03D8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_VSYNC__ARM_TRACE_CTL 0x0110 0x03D8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_RESET__LCD_RESET 0x0114 0x03DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_LCD_RESET__LCD_BUSY 0x0114 0x03DC 0x06D4 0x2 0x1 +#define MX6SLL_PAD_LCD_RESET__UART2_DCE_CTS 0x0114 0x03DC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_RESET__UART2_DTE_RTS 0x0114 0x03DC 0x0748 0x4 0x1 +#define MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x0114 0x03DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_RESET__CCM_PMIC_READY 0x0114 0x03DC 0x05AC 0x6 0x2 +#define MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x0118 0x03E0 0x06D8 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA00__ECSPI1_MOSI 0x0118 0x03E0 0x0608 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA00__USB_OTG2_ID 0x0118 0x03E0 0x0560 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03E0 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA00__UART5_DTR_B 0x0118 0x03E0 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA00__GPIO2_IO20 0x0118 0x03E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA00__ARM_TRACE00 0x0118 0x03E0 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA00__SRC_BOOT_CFG00 0x0118 0x03E0 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x011C 0x03E4 0x06DC 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA01__ECSPI1_MISO 0x011C 0x03E4 0x0604 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA01__USB_OTG1_ID 0x011C 0x03E4 0x055C 0x2 0x3 +#define MX6SLL_PAD_LCD_DATA01__PWM2_OUT 0x011C 0x03E4 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA01__AUD4_RXFS 0x011C 0x03E4 0x0570 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x011C 0x03E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA01__ARM_TRACE01 0x011C 0x03E4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA01__SRC_BOOT_CFG01 0x011C 0x03E4 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x0120 0x03E8 0x06E0 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA02__ECSPI1_SS0 0x0120 0x03E8 0x0614 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA02__EPIT2_OUT 0x0120 0x03E8 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03E8 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA02__AUD4_RXC 0x0120 0x03E8 0x056C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA02__GPIO2_IO22 0x0120 0x03E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA02__ARM_TRACE02 0x0120 0x03E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA02__SRC_BOOT_CFG02 0x0120 0x03E8 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x0124 0x03EC 0x06E4 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA03__ECSPI1_SCLK 0x0124 0x03EC 0x05FC 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA03__UART5_DSR_B 0x0124 0x03EC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03EC 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA03__AUD4_RXD 0x0124 0x03EC 0x0564 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA03__GPIO2_IO23 0x0124 0x03EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA03__ARM_TRACE03 0x0124 0x03EC 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA03__SRC_BOOT_CFG03 0x0124 0x03EC 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x0128 0x03F0 0x06E8 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA04__ECSPI1_SS1 0x0128 0x03F0 0x060C 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA04__CSI_VSYNC 0x0128 0x03F0 0x05F8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA04__WDOG2_RESET_B_DEB 0x0128 0x03F0 0x0000 0x3 0x0 +#define MX6SLL_PAD_LCD_DATA04__AUD4_TXC 0x0128 0x03F0 0x0574 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x0128 0x03F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA04__ARM_TRACE04 0x0128 0x03F0 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA04__SRC_BOOT_CFG04 0x0128 0x03F0 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x012C 0x03F4 0x06EC 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA05__ECSPI1_SS2 0x012C 0x03F4 0x0610 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA05__CSI_HSYNC 0x012C 0x03F4 0x05F0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA05__AUD4_TXFS 0x012C 0x03F4 0x0578 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x012C 0x03F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA05__ARM_TRACE05 0x012C 0x03F4 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA05__SRC_BOOT_CFG05 0x012C 0x03F4 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x0130 0x03F8 0x06F0 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA06__ECSPI1_SS3 0x0130 0x03F8 0x0618 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA06__CSI_PIXCLK 0x0130 0x03F8 0x05F4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA06__AUD4_TXD 0x0130 0x03F8 0x0568 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x0130 0x03F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA06__ARM_TRACE06 0x0130 0x03F8 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA06__SRC_BOOT_CFG06 0x0130 0x03F8 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x0134 0x03FC 0x06F4 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA07__ECSPI1_RDY 0x0134 0x03FC 0x0600 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA07__CSI_MCLK 0x0134 0x03FC 0x0000 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA07__AUDIO_CLK_OUT 0x0134 0x03FC 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x0134 0x03FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA07__ARM_TRACE07 0x0134 0x03FC 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA07__SRC_BOOT_CFG07 0x0134 0x03FC 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x0138 0x0400 0x06F8 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA08__KEY_COL0 0x0138 0x0400 0x06A0 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA08__CSI_DATA09 0x0138 0x0400 0x05EC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA08__ECSPI2_SCLK 0x0138 0x0400 0x061C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x0138 0x0400 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA08__ARM_TRACE08 0x0138 0x0400 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA08__SRC_BOOT_CFG08 0x0138 0x0400 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x013C 0x0404 0x06FC 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA09__KEY_ROW0 0x013C 0x0404 0x06C0 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA09__CSI_DATA08 0x013C 0x0404 0x05E8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA09__ECSPI2_MOSI 0x013C 0x0404 0x0624 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x013C 0x0404 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA09__ARM_TRACE09 0x013C 0x0404 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA09__SRC_BOOT_CFG09 0x013C 0x0404 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x0140 0x0408 0x0700 0x0 0x1 +#define MX6SLL_PAD_LCD_DATA10__KEY_COL1 0x0140 0x0408 0x06A4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA10__CSI_DATA07 0x0140 0x0408 0x05E4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA10__ECSPI2_MISO 0x0140 0x0408 0x0620 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x0140 0x0408 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA10__ARM_TRACE10 0x0140 0x0408 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x0140 0x0408 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x0144 0x040C 0x0704 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA11__KEY_ROW1 0x0144 0x040C 0x06C4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA11__CSI_DATA06 0x0144 0x040C 0x05E0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA11__ECSPI2_SS1 0x0144 0x040C 0x062C 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x0144 0x040C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA11__ARM_TRACE11 0x0144 0x040C 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x0144 0x040C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x0148 0x0410 0x0708 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA12__KEY_COL2 0x0148 0x0410 0x06A8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA12__CSI_DATA05 0x0148 0x0410 0x05DC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA12__UART5_DCE_RTS 0x0148 0x0410 0x0760 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA12__UART5_DTE_CTS 0x0148 0x0410 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x0148 0x0410 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA12__ARM_TRACE12 0x0148 0x0410 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x0148 0x0410 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x014C 0x0414 0x070C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA13__KEY_ROW2 0x014C 0x0414 0x06C8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA13__CSI_DATA04 0x014C 0x0414 0x05D8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA13__UART5_DCE_CTS 0x014C 0x0414 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA13__UART5_DTE_RTS 0x014C 0x0414 0x0760 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x014C 0x0414 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA13__ARM_TRACE13 0x014C 0x0414 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x014C 0x0414 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x0150 0x0418 0x0710 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA14__KEY_COL3 0x0150 0x0418 0x06AC 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA14__CSI_DATA03 0x0150 0x0418 0x05D4 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA14__UART5_DCE_RX 0x0150 0x0418 0x0764 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA14__UART5_DTE_TX 0x0150 0x0418 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x0150 0x0418 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA14__ARM_TRACE14 0x0150 0x0418 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0150 0x0418 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x0154 0x041C 0x0714 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA15__KEY_ROW3 0x0154 0x041C 0x06CC 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA15__CSI_DATA02 0x0154 0x041C 0x05D0 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA15__UART5_DCE_TX 0x0154 0x041C 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA15__UART5_DTE_RX 0x0154 0x041C 0x0764 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x0154 0x041C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA15__ARM_TRACE15 0x0154 0x041C 0x0000 0x6 0x0 +#define MX6SLL_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0154 0x041C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x0158 0x0420 0x0718 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA16__KEY_COL4 0x0158 0x0420 0x06B0 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x0420 0x05CC 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA16__I2C2_SCL 0x0158 0x0420 0x0684 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x0158 0x0420 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA16__SRC_BOOT_CFG24 0x0158 0x0420 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x015C 0x0424 0x071C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA17__KEY_ROW4 0x015C 0x0424 0x06D0 0x1 0x0 +#define MX6SLL_PAD_LCD_DATA17__CSI_DATA00 0x015C 0x0424 0x05C8 0x2 0x0 +#define MX6SLL_PAD_LCD_DATA17__I2C2_SDA 0x015C 0x0424 0x0688 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x015C 0x0424 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA17__SRC_BOOT_CFG25 0x015C 0x0424 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x0160 0x0428 0x0720 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA18__KEY_COL5 0x0160 0x0428 0x0694 0x1 0x2 +#define MX6SLL_PAD_LCD_DATA18__CSI_DATA15 0x0160 0x0428 0x05C4 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA18__GPT_CAPTURE1 0x0160 0x0428 0x0670 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x0160 0x0428 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA18__SRC_BOOT_CFG26 0x0160 0x0428 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x0164 0x042C 0x0724 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA19__KEY_ROW5 0x0164 0x042C 0x06B4 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA19__CSI_DATA14 0x0164 0x042C 0x05C0 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA19__GPT_CAPTURE2 0x0164 0x042C 0x0674 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x0164 0x042C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA19__SRC_BOOT_CFG27 0x0164 0x042C 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x0168 0x0430 0x0728 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA20__KEY_COL6 0x0168 0x0430 0x0698 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA20__CSI_DATA13 0x0168 0x0430 0x05BC 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA20__GPT_COMPARE1 0x0168 0x0430 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x0168 0x0430 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA20__SRC_BOOT_CFG28 0x0168 0x0430 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x016C 0x0434 0x072C 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA21__KEY_ROW6 0x016C 0x0434 0x06B8 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA21__CSI_DATA12 0x016C 0x0434 0x05B8 0x2 0x2 +#define MX6SLL_PAD_LCD_DATA21__GPT_COMPARE2 0x016C 0x0434 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x016C 0x0434 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA21__SRC_BOOT_CFG29 0x016C 0x0434 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x0170 0x0438 0x0730 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA22__KEY_COL7 0x0170 0x0438 0x069C 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA22__CSI_DATA11 0x0170 0x0438 0x05B4 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA22__GPT_COMPARE3 0x0170 0x0438 0x0000 0x4 0x0 +#define MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x0170 0x0438 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA22__SRC_BOOT_CFG30 0x0170 0x0438 0x0000 0x7 0x0 +#define MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x0174 0x043C 0x0734 0x0 0x0 +#define MX6SLL_PAD_LCD_DATA23__KEY_ROW7 0x0174 0x043C 0x06BC 0x1 0x1 +#define MX6SLL_PAD_LCD_DATA23__CSI_DATA10 0x0174 0x043C 0x05B0 0x2 0x1 +#define MX6SLL_PAD_LCD_DATA23__GPT_CLKIN 0x0174 0x043C 0x0678 0x4 0x1 +#define MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x0174 0x043C 0x0000 0x5 0x0 +#define MX6SLL_PAD_LCD_DATA23__SRC_BOOT_CFG31 0x0174 0x043C 0x0000 0x7 0x0 +#define MX6SLL_PAD_AUD_RXFS__AUD3_RXFS 0x0178 0x0440 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXFS__I2C1_SCL 0x0178 0x0440 0x067C 0x1 0x1 +#define MX6SLL_PAD_AUD_RXFS__UART3_DCE_RX 0x0178 0x0440 0x0754 0x2 0x0 +#define MX6SLL_PAD_AUD_RXFS__UART3_DTE_TX 0x0178 0x0440 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x0178 0x0440 0x068C 0x4 0x1 +#define MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x0178 0x0440 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_RXFS__ECSPI3_SS0 0x0178 0x0440 0x0648 0x6 0x0 +#define MX6SLL_PAD_AUD_RXFS__MBIST_BEND 0x0178 0x0440 0x0000 0x7 0x0 +#define MX6SLL_PAD_AUD_RXC__AUD3_RXC 0x017C 0x0444 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXC__I2C1_SDA 0x017C 0x0444 0x0680 0x1 0x1 +#define MX6SLL_PAD_AUD_RXC__UART3_DCE_TX 0x017C 0x0444 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXC__UART3_DTE_RX 0x017C 0x0444 0x0754 0x2 0x1 +#define MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x017C 0x0444 0x0690 0x4 0x1 +#define MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x017C 0x0444 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_RXC__ECSPI3_SS1 0x017C 0x0444 0x064C 0x6 0x0 +#define MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x0180 0x0448 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_RXD__ECSPI3_MOSI 0x0180 0x0448 0x063C 0x1 0x0 +#define MX6SLL_PAD_AUD_RXD__UART4_DCE_RX 0x0180 0x0448 0x075C 0x2 0x0 +#define MX6SLL_PAD_AUD_RXD__UART4_DTE_TX 0x0180 0x0448 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_RXD__SD1_LCTL 0x0180 0x0448 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_RXD__GPIO1_IO02 0x0180 0x0448 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x0184 0x044C 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXC__ECSPI3_MISO 0x0184 0x044C 0x0638 0x1 0x0 +#define MX6SLL_PAD_AUD_TXC__UART4_DCE_TX 0x0184 0x044C 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXC__UART4_DTE_RX 0x0184 0x044C 0x075C 0x2 0x1 +#define MX6SLL_PAD_AUD_TXC__SD2_LCTL 0x0184 0x044C 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_TXC__GPIO1_IO03 0x0184 0x044C 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x0188 0x0450 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXFS__PWM3_OUT 0x0188 0x0450 0x0000 0x1 0x0 +#define MX6SLL_PAD_AUD_TXFS__UART4_DCE_RTS 0x0188 0x0450 0x0758 0x2 0x0 +#define MX6SLL_PAD_AUD_TXFS__UART4_DTE_CTS 0x0188 0x0450 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXFS__SD3_LCTL 0x0188 0x0450 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_TXFS__GPIO1_IO04 0x0188 0x0450 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x018C 0x0454 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_TXD__ECSPI3_SCLK 0x018C 0x0454 0x0630 0x1 0x0 +#define MX6SLL_PAD_AUD_TXD__UART4_DCE_CTS 0x018C 0x0454 0x0000 0x2 0x0 +#define MX6SLL_PAD_AUD_TXD__UART4_DTE_RTS 0x018C 0x0454 0x0758 0x2 0x1 +#define MX6SLL_PAD_AUD_TXD__GPIO1_IO05 0x018C 0x0454 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x0190 0x0458 0x0000 0x0 0x0 +#define MX6SLL_PAD_AUD_MCLK__PWM4_OUT 0x0190 0x0458 0x0000 0x1 0x0 +#define MX6SLL_PAD_AUD_MCLK__ECSPI3_RDY 0x0190 0x0458 0x0634 0x2 0x0 +#define MX6SLL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x0190 0x0458 0x0000 0x4 0x0 +#define MX6SLL_PAD_AUD_MCLK__GPIO1_IO06 0x0190 0x0458 0x0000 0x5 0x0 +#define MX6SLL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x0190 0x0458 0x073C 0x6 0x1 +#define MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x0194 0x045C 0x0744 0x0 0x0 +#define MX6SLL_PAD_UART1_RXD__UART1_DTE_TX 0x0194 0x045C 0x0000 0x0 0x0 +#define MX6SLL_PAD_UART1_RXD__PWM1_OUT 0x0194 0x045C 0x0000 0x1 0x0 +#define MX6SLL_PAD_UART1_RXD__UART4_DCE_RX 0x0194 0x045C 0x075C 0x2 0x4 +#define MX6SLL_PAD_UART1_RXD__UART4_DTE_TX 0x0194 0x045C 0x0000 0x2 0x0 +#define MX6SLL_PAD_UART1_RXD__UART5_DCE_RX 0x0194 0x045C 0x0764 0x4 0x6 +#define MX6SLL_PAD_UART1_RXD__UART5_DTE_TX 0x0194 0x045C 0x0000 0x4 0x0 +#define MX6SLL_PAD_UART1_RXD__GPIO3_IO16 0x0194 0x045C 0x0000 0x5 0x0 +#define MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x0198 0x0460 0x0000 0x0 0x0 +#define MX6SLL_PAD_UART1_TXD__UART1_DTE_RX 0x0198 0x0460 0x0744 0x0 0x1 +#define MX6SLL_PAD_UART1_TXD__PWM2_OUT 0x0198 0x0460 0x0000 0x1 0x0 +#define MX6SLL_PAD_UART1_TXD__UART4_DCE_TX 0x0198 0x0460 0x0000 0x2 0x0 +#define MX6SLL_PAD_UART1_TXD__UART4_DTE_RX 0x0198 0x0460 0x075C 0x2 0x5 +#define MX6SLL_PAD_UART1_TXD__UART5_DCE_TX 0x0198 0x0460 0x0000 0x4 0x0 +#define MX6SLL_PAD_UART1_TXD__UART5_DTE_RX 0x0198 0x0460 0x0764 0x4 0x7 +#define MX6SLL_PAD_UART1_TXD__GPIO3_IO17 0x0198 0x0460 0x0000 0x5 0x0 +#define MX6SLL_PAD_UART1_TXD__UART5_DCD_B 0x0198 0x0460 0x0000 0x7 0x0 +#define MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x019C 0x0464 0x067C 0x0 0x0 +#define MX6SLL_PAD_I2C1_SCL__UART1_DCE_RTS 0x019C 0x0464 0x0740 0x1 0x0 +#define MX6SLL_PAD_I2C1_SCL__UART1_DTE_CTS 0x019C 0x0464 0x0000 0x1 0x0 +#define MX6SLL_PAD_I2C1_SCL__ECSPI3_SS2 0x019C 0x0464 0x0640 0x2 0x0 +#define MX6SLL_PAD_I2C1_SCL__SD3_RESET 0x019C 0x0464 0x0000 0x4 0x0 +#define MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x019C 0x0464 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C1_SCL__ECSPI1_SS1 0x019C 0x0464 0x060C 0x6 0x0 +#define MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x01A0 0x0468 0x0680 0x0 0x0 +#define MX6SLL_PAD_I2C1_SDA__UART1_DCE_CTS 0x01A0 0x0468 0x0000 0x1 0x0 +#define MX6SLL_PAD_I2C1_SDA__UART1_DTE_RTS 0x01A0 0x0468 0x0740 0x1 0x1 +#define MX6SLL_PAD_I2C1_SDA__ECSPI3_SS3 0x01A0 0x0468 0x0644 0x2 0x0 +#define MX6SLL_PAD_I2C1_SDA__SD3_VSELECT 0x01A0 0x0468 0x0000 0x4 0x0 +#define MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x01A0 0x0468 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C1_SDA__ECSPI1_SS2 0x01A0 0x0468 0x0610 0x6 0x0 +#define MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x01A4 0x046C 0x0684 0x0 0x3 +#define MX6SLL_PAD_I2C2_SCL__AUD4_RXFS 0x01A4 0x046C 0x0570 0x1 0x2 +#define MX6SLL_PAD_I2C2_SCL__SPDIF_IN 0x01A4 0x046C 0x0738 0x2 0x2 +#define MX6SLL_PAD_I2C2_SCL__SD3_WP 0x01A4 0x046C 0x0794 0x4 0x3 +#define MX6SLL_PAD_I2C2_SCL__GPIO3_IO14 0x01A4 0x046C 0x0000 0x5 0x0 +#define MX6SLL_PAD_I2C2_SCL__ECSPI1_RDY 0x01A4 0x046C 0x0600 0x6 0x1 +#define MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x01A8 0x0470 0x0688 0x0 0x3 +#define MX6SLL_PAD_I2C2_SDA__AUD4_RXC 0x01A8 0x0470 0x056C 0x1 0x2 +#define MX6SLL_PAD_I2C2_SDA__SPDIF_OUT 0x01A8 0x0470 0x0000 0x2 0x0 +#define MX6SLL_PAD_I2C2_SDA__SD3_CD_B 0x01A8 0x0470 0x0780 0x4 0x3 +#define MX6SLL_PAD_I2C2_SDA__GPIO3_IO15 0x01A8 0x0470 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x01AC 0x0474 0x05FC 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_SCLK__AUD4_TXD 0x01AC 0x0474 0x0568 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DCE_RX 0x01AC 0x0474 0x0764 0x2 0x2 +#define MX6SLL_PAD_ECSPI1_SCLK__UART5_DTE_TX 0x01AC 0x0474 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__EPDC_VCOM0 0x01AC 0x0474 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__SD2_RESET 0x01AC 0x0474 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x01AC 0x0474 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x01AC 0x0474 0x0768 0x6 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x01B0 0x0478 0x0608 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__AUD4_TXC 0x01B0 0x0478 0x0574 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DCE_TX 0x01B0 0x0478 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__UART5_DTE_RX 0x01B0 0x0478 0x0764 0x2 0x3 +#define MX6SLL_PAD_ECSPI1_MOSI__EPDC_VCOM1 0x01B0 0x0478 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__SD2_VSELECT 0x01B0 0x0478 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x01B0 0x0478 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x01B4 0x047C 0x0604 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_MISO__AUD4_TXFS 0x01B4 0x047C 0x0578 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_MISO__UART5_DCE_RTS 0x01B4 0x047C 0x0760 0x2 0x2 +#define MX6SLL_PAD_ECSPI1_MISO__UART5_DTE_CTS 0x01B4 0x047C 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__EPDC_BDR0 0x01B4 0x047C 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__SD2_WP 0x01B4 0x047C 0x077C 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_MISO__GPIO4_IO10 0x01B4 0x047C 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__ECSPI1_SS0 0x01B8 0x0480 0x0614 0x0 0x1 +#define MX6SLL_PAD_ECSPI1_SS0__AUD4_RXD 0x01B8 0x0480 0x0564 0x1 0x1 +#define MX6SLL_PAD_ECSPI1_SS0__UART5_DCE_CTS 0x01B8 0x0480 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__UART5_DTE_RTS 0x01B8 0x0480 0x0760 0x2 0x3 +#define MX6SLL_PAD_ECSPI1_SS0__EPDC_BDR1 0x01B8 0x0480 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__SD2_CD_B 0x01B8 0x0480 0x0778 0x4 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x01B8 0x0480 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI1_SS0__USB_OTG2_PWR 0x01B8 0x0480 0x0000 0x6 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x01BC 0x0484 0x061C 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_SCLK__SPDIF_EXT_CLK 0x01BC 0x0484 0x073C 0x1 0x2 +#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DCE_RX 0x01BC 0x0484 0x0754 0x2 0x2 +#define MX6SLL_PAD_ECSPI2_SCLK__UART3_DTE_TX 0x01BC 0x0484 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__CSI_PIXCLK 0x01BC 0x0484 0x05F4 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_SCLK__SD1_RESET 0x01BC 0x0484 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__GPIO4_IO12 0x01BC 0x0484 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x01BC 0x0484 0x0768 0x6 0x2 +#define MX6SLL_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x01C0 0x0488 0x0624 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_MOSI__SDMA_EXT_EVENT1 0x01C0 0x0488 0x0000 0x1 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DCE_TX 0x01C0 0x0488 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__UART3_DTE_RX 0x01C0 0x0488 0x0754 0x2 0x3 +#define MX6SLL_PAD_ECSPI2_MOSI__CSI_HSYNC 0x01C0 0x0488 0x05F0 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_MOSI__SD1_VSELECT 0x01C0 0x0488 0x0000 0x4 0x0 +#define MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x01C0 0x0488 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__ECSPI2_MISO 0x01C4 0x048C 0x0620 0x0 0x1 +#define MX6SLL_PAD_ECSPI2_MISO__SDMA_EXT_EVENT0 0x01C4 0x048C 0x0000 0x1 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__UART3_DCE_RTS 0x01C4 0x048C 0x0750 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__UART3_DTE_CTS 0x01C4 0x048C 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__CSI_MCLK 0x01C4 0x048C 0x0000 0x3 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__SD1_WP 0x01C4 0x048C 0x0774 0x4 0x2 +#define MX6SLL_PAD_ECSPI2_MISO__GPIO4_IO14 0x01C4 0x048C 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_MISO__USB_OTG1_OC 0x01C4 0x048C 0x076C 0x6 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__ECSPI2_SS0 0x01C8 0x0490 0x0628 0x0 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__ECSPI1_SS3 0x01C8 0x0490 0x0618 0x1 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__UART3_DCE_CTS 0x01C8 0x0490 0x0000 0x2 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__UART3_DTE_RTS 0x01C8 0x0490 0x0750 0x2 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__CSI_VSYNC 0x01C8 0x0490 0x05F8 0x3 0x1 +#define MX6SLL_PAD_ECSPI2_SS0__SD1_CD_B 0x01C8 0x0490 0x0770 0x4 0x2 +#define MX6SLL_PAD_ECSPI2_SS0__GPIO4_IO15 0x01C8 0x0490 0x0000 0x5 0x0 +#define MX6SLL_PAD_ECSPI2_SS0__USB_OTG1_PWR 0x01C8 0x0490 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD1_CLK__SD1_CLK 0x01CC 0x0494 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_CLK__KEY_COL0 0x01CC 0x0494 0x06A0 0x2 0x2 +#define MX6SLL_PAD_SD1_CLK__EPDC_SDCE4 0x01CC 0x0494 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_CLK__GPIO5_IO15 0x01CC 0x0494 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_CMD__SD1_CMD 0x01D0 0x0498 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_CMD__KEY_ROW0 0x01D0 0x0498 0x06C0 0x2 0x2 +#define MX6SLL_PAD_SD1_CMD__EPDC_SDCE5 0x01D0 0x0498 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_CMD__GPIO5_IO14 0x01D0 0x0498 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x01D4 0x049C 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA0__KEY_COL1 0x01D4 0x049C 0x06A4 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA0__EPDC_SDCE6 0x01D4 0x049C 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA0__GPIO5_IO11 0x01D4 0x049C 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x01D8 0x04A0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA1__KEY_ROW1 0x01D8 0x04A0 0x06C4 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA1__EPDC_SDCE7 0x01D8 0x04A0 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x01D8 0x04A0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x01DC 0x04A4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA2__KEY_COL2 0x01DC 0x04A4 0x06A8 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA2__EPDC_SDCE8 0x01DC 0x04A4 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x01DC 0x04A4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x01E0 0x04A8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA3__KEY_ROW2 0x01E0 0x04A8 0x06C8 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA3__EPDC_SDCE9 0x01E0 0x04A8 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x01E0 0x04A8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x01E4 0x04AC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA4__KEY_COL3 0x01E4 0x04AC 0x06AC 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA4__EPDC_SDCLK_N 0x01E4 0x04AC 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA4__UART4_DCE_RX 0x01E4 0x04AC 0x075C 0x4 0x6 +#define MX6SLL_PAD_SD1_DATA4__UART4_DTE_TX 0x01E4 0x04AC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA4__GPIO5_IO12 0x01E4 0x04AC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x01E8 0x04B0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA5__KEY_ROW3 0x01E8 0x04B0 0x06CC 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA5__EPDC_SDOED 0x01E8 0x04B0 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA5__UART4_DCE_TX 0x01E8 0x04B0 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA5__UART4_DTE_RX 0x01E8 0x04B0 0x075C 0x4 0x7 +#define MX6SLL_PAD_SD1_DATA5__GPIO5_IO09 0x01E8 0x04B0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x01EC 0x04B4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA6__KEY_COL4 0x01EC 0x04B4 0x06B0 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA6__EPDC_SDOEZ 0x01EC 0x04B4 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD1_DATA6__UART4_DCE_RTS 0x01EC 0x04B4 0x0758 0x4 0x4 +#define MX6SLL_PAD_SD1_DATA6__UART4_DTE_CTS 0x01EC 0x04B4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA6__GPIO5_IO07 0x01EC 0x04B4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x01F0 0x04B8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD1_DATA7__KEY_ROW4 0x01F0 0x04B8 0x06D0 0x2 0x2 +#define MX6SLL_PAD_SD1_DATA7__CCM_PMIC_READY 0x01F0 0x04B8 0x05AC 0x3 0x3 +#define MX6SLL_PAD_SD1_DATA7__UART4_DCE_CTS 0x01F0 0x04B8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD1_DATA7__UART4_DTE_RTS 0x01F0 0x04B8 0x0758 0x4 0x5 +#define MX6SLL_PAD_SD1_DATA7__GPIO5_IO10 0x01F0 0x04B8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_RESET__SD2_RESET 0x01F4 0x04BC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_RESET__WDOG2_B 0x01F4 0x04BC 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x01F4 0x04BC 0x0000 0x3 0x0 +#define MX6SLL_PAD_SD2_RESET__CSI_MCLK 0x01F4 0x04BC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x01F4 0x04BC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_CLK__SD2_CLK 0x01F8 0x04C0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_CLK__AUD4_RXFS 0x01F8 0x04C0 0x0570 0x1 0x1 +#define MX6SLL_PAD_SD2_CLK__ECSPI3_SCLK 0x01F8 0x04C0 0x0630 0x2 0x1 +#define MX6SLL_PAD_SD2_CLK__CSI_DATA00 0x01F8 0x04C0 0x05C8 0x3 0x1 +#define MX6SLL_PAD_SD2_CLK__GPIO5_IO05 0x01F8 0x04C0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_CMD__SD2_CMD 0x01FC 0x04C4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_CMD__AUD4_RXC 0x01FC 0x04C4 0x056C 0x1 0x1 +#define MX6SLL_PAD_SD2_CMD__ECSPI3_SS0 0x01FC 0x04C4 0x0648 0x2 0x1 +#define MX6SLL_PAD_SD2_CMD__CSI_DATA01 0x01FC 0x04C4 0x05CC 0x3 0x1 +#define MX6SLL_PAD_SD2_CMD__EPIT1_OUT 0x01FC 0x04C4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_CMD__GPIO5_IO04 0x01FC 0x04C4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x0200 0x04C8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA0__AUD4_RXD 0x0200 0x04C8 0x0564 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA0__ECSPI3_MOSI 0x0200 0x04C8 0x063C 0x2 0x1 +#define MX6SLL_PAD_SD2_DATA0__CSI_DATA02 0x0200 0x04C8 0x05D0 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA0__UART5_DCE_RTS 0x0200 0x04C8 0x0760 0x4 0x4 +#define MX6SLL_PAD_SD2_DATA0__UART5_DTE_CTS 0x0200 0x04C8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA0__GPIO5_IO01 0x0200 0x04C8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x0204 0x04CC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA1__AUD4_TXC 0x0204 0x04CC 0x0574 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA1__ECSPI3_MISO 0x0204 0x04CC 0x0638 0x2 0x1 +#define MX6SLL_PAD_SD2_DATA1__CSI_DATA03 0x0204 0x04CC 0x05D4 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA1__UART5_DCE_CTS 0x0204 0x04CC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA1__UART5_DTE_RTS 0x0204 0x04CC 0x0760 0x4 0x5 +#define MX6SLL_PAD_SD2_DATA1__GPIO4_IO30 0x0204 0x04CC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x0208 0x04D0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA2__AUD4_TXFS 0x0208 0x04D0 0x0578 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA2__CSI_DATA04 0x0208 0x04D0 0x05D8 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA2__UART5_DCE_RX 0x0208 0x04D0 0x0764 0x4 0x4 +#define MX6SLL_PAD_SD2_DATA2__UART5_DTE_TX 0x0208 0x04D0 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA2__GPIO5_IO03 0x0208 0x04D0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x020C 0x04D4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA3__AUD4_TXD 0x020C 0x04D4 0x0568 0x1 0x2 +#define MX6SLL_PAD_SD2_DATA3__CSI_DATA05 0x020C 0x04D4 0x05DC 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA3__UART5_DCE_TX 0x020C 0x04D4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA3__UART5_DTE_RX 0x020C 0x04D4 0x0764 0x4 0x5 +#define MX6SLL_PAD_SD2_DATA3__GPIO4_IO28 0x020C 0x04D4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x0210 0x04D8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA4__SD3_DATA4 0x0210 0x04D8 0x0784 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA4__UART2_DCE_RX 0x0210 0x04D8 0x074C 0x2 0x2 +#define MX6SLL_PAD_SD2_DATA4__UART2_DTE_TX 0x0210 0x04D8 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA4__CSI_DATA06 0x0210 0x04D8 0x05E0 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA4__SPDIF_OUT 0x0210 0x04D8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD2_DATA4__GPIO5_IO02 0x0210 0x04D8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x0214 0x04DC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA5__SD3_DATA5 0x0214 0x04DC 0x0788 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA5__UART2_DCE_TX 0x0214 0x04DC 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA5__UART2_DTE_RX 0x0214 0x04DC 0x074C 0x2 0x3 +#define MX6SLL_PAD_SD2_DATA5__CSI_DATA07 0x0214 0x04DC 0x05E4 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA5__SPDIF_IN 0x0214 0x04DC 0x0738 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA5__GPIO4_IO31 0x0214 0x04DC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x0218 0x04E0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA6__SD3_DATA6 0x0218 0x04E0 0x078C 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA6__UART2_DCE_RTS 0x0218 0x04E0 0x0748 0x2 0x2 +#define MX6SLL_PAD_SD2_DATA6__UART2_DTE_CTS 0x0218 0x04E0 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA6__CSI_DATA08 0x0218 0x04E0 0x05E8 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA6__SD2_WP 0x0218 0x04E0 0x077C 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x0218 0x04E0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x021C 0x04E4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD2_DATA7__SD3_DATA7 0x021C 0x04E4 0x0790 0x1 0x1 +#define MX6SLL_PAD_SD2_DATA7__UART2_DCE_CTS 0x021C 0x04E4 0x0000 0x2 0x0 +#define MX6SLL_PAD_SD2_DATA7__UART2_DTE_RTS 0x021C 0x04E4 0x0748 0x2 0x3 +#define MX6SLL_PAD_SD2_DATA7__CSI_DATA09 0x021C 0x04E4 0x05EC 0x3 0x1 +#define MX6SLL_PAD_SD2_DATA7__SD2_CD_B 0x021C 0x04E4 0x0778 0x4 0x1 +#define MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x021C 0x04E4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CLK__SD3_CLK 0x0220 0x04E8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_CLK__AUD5_RXFS 0x0220 0x04E8 0x0588 0x1 0x0 +#define MX6SLL_PAD_SD3_CLK__KEY_COL5 0x0220 0x04E8 0x0694 0x2 0x0 +#define MX6SLL_PAD_SD3_CLK__CSI_DATA10 0x0220 0x04E8 0x05B0 0x3 0x0 +#define MX6SLL_PAD_SD3_CLK__WDOG1_RESET_B_DEB 0x0220 0x04E8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x0220 0x04E8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CLK__USB_OTG1_PWR 0x0220 0x04E8 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_CMD__SD3_CMD 0x0224 0x04EC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_CMD__AUD5_RXC 0x0224 0x04EC 0x0584 0x1 0x0 +#define MX6SLL_PAD_SD3_CMD__KEY_ROW5 0x0224 0x04EC 0x06B4 0x2 0x0 +#define MX6SLL_PAD_SD3_CMD__CSI_DATA11 0x0224 0x04EC 0x05B4 0x3 0x0 +#define MX6SLL_PAD_SD3_CMD__USB_OTG2_ID 0x0224 0x04EC 0x0560 0x4 0x1 +#define MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x0224 0x04EC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_CMD__USB_OTG2_PWR 0x0224 0x04EC 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x0228 0x04F0 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA0__AUD5_RXD 0x0228 0x04F0 0x057C 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA0__KEY_COL6 0x0228 0x04F0 0x0698 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA0__CSI_DATA12 0x0228 0x04F0 0x05B8 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA0__USB_OTG1_ID 0x0228 0x04F0 0x055C 0x4 0x1 +#define MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x0228 0x04F0 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x022C 0x04F4 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA1__AUD5_TXC 0x022C 0x04F4 0x058C 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA1__KEY_ROW6 0x022C 0x04F4 0x06B8 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA1__CSI_DATA13 0x022C 0x04F4 0x05BC 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA1__SD1_VSELECT 0x022C 0x04F4 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x022C 0x04F4 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA1__JTAG_DE_B 0x022C 0x04F4 0x0000 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x0230 0x04F8 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA2__AUD5_TXFS 0x0230 0x04F8 0x0590 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA2__KEY_COL7 0x0230 0x04F8 0x069C 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA2__CSI_DATA14 0x0230 0x04F8 0x05C0 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA2__EPIT1_OUT 0x0230 0x04F8 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x0230 0x04F8 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA2__USB_OTG2_OC 0x0230 0x04F8 0x0768 0x6 0x0 +#define MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x0234 0x04FC 0x0000 0x0 0x0 +#define MX6SLL_PAD_SD3_DATA3__AUD5_TXD 0x0234 0x04FC 0x0580 0x1 0x0 +#define MX6SLL_PAD_SD3_DATA3__KEY_ROW7 0x0234 0x04FC 0x06BC 0x2 0x0 +#define MX6SLL_PAD_SD3_DATA3__CSI_DATA15 0x0234 0x04FC 0x05C4 0x3 0x0 +#define MX6SLL_PAD_SD3_DATA3__EPIT2_OUT 0x0234 0x04FC 0x0000 0x4 0x0 +#define MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x0234 0x04FC 0x0000 0x5 0x0 +#define MX6SLL_PAD_SD3_DATA3__USB_OTG1_OC 0x0234 0x04FC 0x076C 0x6 0x0 +#define MX6SLL_PAD_GPIO4_IO20__SD1_STROBE 0x0238 0x0500 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO20__AUD6_RXFS 0x0238 0x0500 0x05A0 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO20__ECSPI4_SS0 0x0238 0x0500 0x065C 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO20__GPT_CAPTURE1 0x0238 0x0500 0x0670 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x0238 0x0500 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x023C 0x0504 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO21__AUD6_RXC 0x023C 0x0504 0x059C 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO21__ECSPI4_SCLK 0x023C 0x0504 0x0650 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO21__GPT_CAPTURE2 0x023C 0x0504 0x0674 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x023C 0x0504 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO19__SD3_STROBE 0x0240 0x0508 0x0000 0x0 0x0 +#define MX6SLL_PAD_GPIO4_IO19__AUD6_RXD 0x0240 0x0508 0x0594 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO19__ECSPI4_MOSI 0x0240 0x0508 0x0658 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO19__GPT_COMPARE1 0x0240 0x0508 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x0240 0x0508 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO25__AUD6_TXC 0x0244 0x050C 0x05A4 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO25__ECSPI4_MISO 0x0244 0x050C 0x0654 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO25__GPT_COMPARE2 0x0244 0x050C 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x0244 0x050C 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO18__AUD6_TXFS 0x0248 0x0510 0x05A8 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO18__ECSPI4_SS1 0x0248 0x0510 0x0660 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO18__GPT_COMPARE3 0x0248 0x0510 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x0248 0x0510 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO24__AUD6_TXD 0x024C 0x0514 0x0598 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO24__ECSPI4_SS2 0x024C 0x0514 0x0664 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO24__GPT_CLKIN 0x024C 0x0514 0x0678 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x024C 0x0514 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO23__AUDIO_CLK_OUT 0x0250 0x0518 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO23__SD1_RESET 0x0250 0x0518 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO23__SD3_RESET 0x0250 0x0518 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x0250 0x0518 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO17__USB_OTG1_ID 0x0254 0x051C 0x055C 0x2 0x2 +#define MX6SLL_PAD_GPIO4_IO17__SD1_VSELECT 0x0254 0x051C 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO17__SD3_VSELECT 0x0254 0x051C 0x0000 0x4 0x0 +#define MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x0254 0x051C 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SPDIF_IN 0x0258 0x0520 0x0738 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SD1_WP 0x0258 0x0520 0x0774 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO22__SD3_WP 0x0258 0x0520 0x0794 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x0258 0x0520 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SPDIF_OUT 0x025C 0x0524 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SD1_CD_B 0x025C 0x0524 0x0770 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO16__SD3_CD_B 0x025C 0x0524 0x0780 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO16__GPIO4_IO16 0x025C 0x0524 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO26__WDOG1_B 0x0260 0x0528 0x0000 0x2 0x0 +#define MX6SLL_PAD_GPIO4_IO26__PWM4_OUT 0x0260 0x0528 0x0000 0x3 0x0 +#define MX6SLL_PAD_GPIO4_IO26__CCM_PMIC_READY 0x0260 0x0528 0x05AC 0x4 0x1 +#define MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x0260 0x0528 0x0000 0x5 0x0 +#define MX6SLL_PAD_GPIO4_IO26__SPDIF_EXT_CLK 0x0260 0x0528 0x073C 0x6 0x0 + +#endif /* __DTS_IMX6SLL_PINFUNC_H */ diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi new file mode 100644 index 000000000000..c9b0ccc0e2e2 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -0,0 +1,780 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + */ + +#include +#include +#include +#include "imx6sll-pinfunc.h" + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi3 = &ecspi3; + spi4 = &ecspi4; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6SLL_CLK_ARM>, + <&clks IMX6SLL_CLK_PLL2_PFD2>, + <&clks IMX6SLL_CLK_STEP>, + <&clks IMX6SLL_CLK_PLL1_SW>, + <&clks IMX6SLL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + }; + }; + + intc: interrupt-controller@a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + interrupt-parent = <&intc>; + }; + + ckil: clock-ckil { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + ipp_di0: clock-ipp-di0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; + + ipp_di1: clock-ipp-di1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; + + tempmon: temperature-sensor { + compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon"; + interrupts = ; + interrupt-parent = <&gpc>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + ocram: sram@900000 { + compatible = "mmio-sram"; + reg = <0x00900000 0x20000>; + }; + + L2: l2-cache@a02000 { + compatible = "arm,pl310-cache"; + reg = <0x00a02000 0x1000>; + interrupts = ; + cache-unified; + cache-level = <2>; + arm,tag-latency = <4 2 3>; + arm,data-latency = <4 2 3>; + }; + + aips1: aips-bus@2000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba: spba-bus@2000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif: spdif@2004000 { + compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif"; + reg = <0x02004000 0x4000>; + interrupts = ; + dmas = <&sdma 14 18 0>, <&sdma 15 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>, + <&clks IMX6SLL_CLK_OSC>, + <&clks IMX6SLL_CLK_SPDIF>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_IPG>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "dma"; + status = "disabled"; + }; + + ecspi1: spi@2008000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = ; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI1>, + <&clks IMX6SLL_CLK_ECSPI1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: spi@200c000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = ; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI2>, + <&clks IMX6SLL_CLK_ECSPI2>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: spi@2010000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = ; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI3>, + <&clks IMX6SLL_CLK_ECSPI3>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi4: spi@2014000 { + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = ; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_ECSPI4>, + <&clks IMX6SLL_CLK_ECSPI4>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart4: serial@2018000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02018000 0x4000>; + interrupts =; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART4_IPG>, + <&clks IMX6SLL_CLK_UART4_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@2020000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = ; + dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART1_IPG>, + <&clks IMX6SLL_CLK_UART1_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@2024000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02024000 0x4000>; + interrupts = ; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART2_IPG>, + <&clks IMX6SLL_CLK_UART2_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ssi1: ssi-controller@2028000 { + compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; + reg = <0x02028000 0x4000>; + interrupts = ; + dmas = <&sdma 37 22 0>, <&sdma 38 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI1_IPG>, + <&clks IMX6SLL_CLK_SSI1>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + ssi2: ssi-controller@202c000 { + compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; + reg = <0x0202c000 0x4000>; + interrupts = ; + dmas = <&sdma 41 22 0>, <&sdma 42 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI2_IPG>, + <&clks IMX6SLL_CLK_SSI2>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + ssi3: ssi-controller@2030000 { + compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; + reg = <0x02030000 0x4000>; + interrupts = ; + dmas = <&sdma 45 22 0>, <&sdma 46 22 0>; + dma-names = "rx", "tx"; + fsl,fifo-depth = <15>; + clocks = <&clks IMX6SLL_CLK_SSI3_IPG>, + <&clks IMX6SLL_CLK_SSI3>; + clock-names = "ipg", "baud"; + status = "disabled"; + }; + + uart3: serial@2034000 { + compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x02034000 0x4000>; + interrupts = ; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-name = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART3_IPG>, + <&clks IMX6SLL_CLK_UART3_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + pwm1: pwm@2080000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM1>, + <&clks IMX6SLL_CLK_PWM1>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm2: pwm@2084000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM2>, + <&clks IMX6SLL_CLK_PWM2>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm3: pwm@2088000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM3>, + <&clks IMX6SLL_CLK_PWM3>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm4: pwm@208c000 { + compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_PWM4>, + <&clks IMX6SLL_CLK_PWM4>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + gpt1: timer@2098000 { + compatible = "fsl,imx6sl-gpt"; + reg = <0x02098000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_GPT_BUS>, + <&clks IMX6SLL_CLK_GPT_SERIAL>; + clock-names = "ipg", "per"; + }; + + gpio1: gpio@209c000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@20a0000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@20a4000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@20a8000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@20ac000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@20b0000 { + compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio"; + reg = <0x020b0000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + kpp: keypad@20b8000 { + compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp"; + reg = <0x020b8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_KPP>; + status = "disabled"; + }; + + wdog1: watchdog@20bc000 { + compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_WDOG1>; + }; + + wdog2: watchdog@20c0000 { + compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_WDOG2>; + status = "disabled"; + }; + + clks: clock-controller@20c4000 { + compatible = "fsl,imx6sll-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + + assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>; + assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>; + }; + + anatop: anatop@20c8000 { + compatible = "fsl,imx6sll-anatop", + "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x020c8000 0x4000>; + interrupts = , + , + ; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p0: regulator-3p0@20c8120 { + compatible = "fsl,anatop-regulator"; + reg = <0x20c8120>; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + }; + + usbphy1: usb-phy@20c9000 { + compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", + "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usb-phy@20ca000 { + compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy", + "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBPHY2>; + phy-reg_3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + snvs: snvs@20cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = , + ; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x61>; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup-source; + }; + }; + + src: reset-controller@20d8000 { + compatible = "fsl,imx6sll-src"; + reg = <0x020d8000 0x4000>; + interrupts = , + ; + #reset-cells = <1>; + }; + + gpc: interrupt-controller@20dc000 { + compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>; + }; + + iomuxc: pinctrl@20e0000 { + compatible = "fsl,imx6sll-iomuxc"; + reg = <0x020e0000 0x4000>; + }; + + gpr: iomuxc-gpr@20e4000 { + compatible = "fsl,imx6sll-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x020e4000 0x4000>; + }; + + csi: csi@20e8000 { + compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi"; + reg = <0x020e8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_DUMMY>, + <&clks IMX6SLL_CLK_CSI>, + <&clks IMX6SLL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + sdma: dma-controller@20ec000 { + compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_SDMA>, + <&clks IMX6SLL_CLK_SDMA>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + iram = <&ocram>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + }; + + lcdif: lcd-controller@20f8000 { + compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; + reg = <0x020f8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>, + <&clks IMX6SLL_CLK_LCDIF_APB>, + <&clks IMX6SLL_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + }; + + dcp: dcp@20fc000 { + compatible = "fsl,imx28-dcp"; + reg = <0x020fc000 0x4000>; + interrupts = , + , + ; + clocks = <&clks IMX6SLL_CLK_DCP>; + clock-names = "dcp"; + }; + }; + + aips2: aips-bus@2100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + usbotg1: usb@2184000 { + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", + "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + fsl,anatop = <&anatop>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbotg2: usb@2184200 { + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", + "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbmisc: usbmisc@2184800 { + #index-cells = <1>; + compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + }; + + usdhc1: mmc@2190000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USDHC1>, + <&clks IMX6SLL_CLK_USDHC1>, + <&clks IMX6SLL_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + usdhc2: mmc@2194000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USDHC2>, + <&clks IMX6SLL_CLK_USDHC2>, + <&clks IMX6SLL_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + usdhc3: mmc@2198000 { + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02198000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USDHC3>, + <&clks IMX6SLL_CLK_USDHC3>, + <&clks IMX6SLL_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; + status = "disabled"; + }; + + i2c1: i2c@21a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@21a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@21a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_I2C3>; + status = "disabled"; + }; + + mmdc: memory-controller@21b0000 { + compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + }; + + ocotp: ocotp-ctrl@21bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx6sll-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6SLL_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; + }; + + audmux: audmux@21d8000 { + compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux"; + reg = <0x021d8000 0x4000>; + status = "disabled"; + }; + + uart5: serial@21f4000 { + compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", + "fsl,imx21-uart"; + reg = <0x021f4000 0x4000>; + interrupts =; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6SLL_CLK_UART5_IPG>, + <&clks IMX6SLL_CLK_UART5_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + }; +}; From 26bd0e5964deb4ee326689911a089889734bd409 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Fri, 25 May 2018 15:42:07 +0800 Subject: [PATCH 02/96] ARM: dts: imx: Add basic dts support for imx6sll EVK board Add dts file support for imx6sll EVK board. Signed-off-by: Bai Ping Reviewed-by: Rob Herring Acked-by: Dong Aisheng Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.txt | 4 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6sll-evk.dts | 315 ++++++++++++++++++ 3 files changed, 321 insertions(+) create mode 100644 arch/arm/boot/dts/imx6sll-evk.dts diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index cdb9dd705754..8a1baa2b9723 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt @@ -53,6 +53,10 @@ i.MX6 Quad SABRE Automotive Board Required root node properties: - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; +i.MX6SLL EVK board +Required root node properties: + - compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; + Generic i.MX boards ------------------- diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de760d40..30379d342cd6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -521,6 +521,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ dtb-$(CONFIG_SOC_IMX6SL) += \ imx6sl-evk.dtb \ imx6sl-warp.dtb +dtb-$(CONFIG_SOC_IMX6SLL) += \ + imx6sll-evk.dtb dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-nitrogen6sx.dtb \ imx6sx-sabreauto.dtb \ diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts new file mode 100644 index 000000000000..4684ac4a816b --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP. + * + */ + +/dts-v1/; + +#include +#include +#include "imx6sll.dtsi" + +/ { + model = "Freescale i.MX6SLL EVK Board"; + compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; + + memory@80000000 { + reg = <0x80000000 0x80000000>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + reg_usb_otg1_vbus: regulator-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator-otg2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2_vbus>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_aud3v: regulator-aud3v { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply-3v15"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-boot-on; + }; + + reg_aud4v: regulator-aud4v { + compatible = "regulator-fixed"; + regulator-name = "wm8962-supply-4v2"; + regulator-min-microvolt = <4325000>; + regulator-max-microvolt = <4325000>; + regulator-boot-on; + }; + + reg_lcd: regulator-lcd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd>; + regulator-name = "lcd-pwr"; + gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_sd1_vmmc>; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1c_reg>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pfuze100: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl_usb_otg1_vbus: vbus1grp { + fsl,pins = < + MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 + >; + }; + + pinctrl_usb_otg2_vbus: vbus2grp { + fsl,pins = < + MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 + >; + }; + + pinctrl_reg_lcd: reglcdgrp { + fsl,pins = < + MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x17059 + >; + }; + + pinctrl_reg_sd1_vmmc: sd1vmmcgrp { + fsl,pins = < + MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 + MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 + >; + }; +}; From 5ebc384a15e4a315d7b50576799653e2ec5402f7 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Wed, 23 May 2018 10:30:12 +0200 Subject: [PATCH 03/96] ARM: dts: imx6: make edt-ft5x06 a wakeup source for imx6 boards The touchscreen driver no longer configures the device as wakeup source by default. A "wakeup-source" property is needed. Signed-off-by: Daniel Mack Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-var-dt6customboard.dts | 1 + arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 1 + arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 1 + arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 1 + arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts index f2368a073d07..c54362fcc508 100644 --- a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts +++ b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts @@ -177,6 +177,7 @@ touchscreen@38 { touchscreen-size-y = <480>; touchscreen-inverted-x; touchscreen-inverted-y; + wakeup-source; }; rtc@68 { diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index aab088f318e8..aef4a756ca81 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -292,6 +292,7 @@ touchscreen@38 { reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; }; rtc@6f { diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index 87ca6ead4098..9cb464b65be1 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -442,6 +442,7 @@ touchscreen@38 { reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi index f5b763d39285..5e4da6d6fcff 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -360,6 +360,7 @@ touchscreen@38 { reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 596866b0a0d2..a14872436c5e 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -370,6 +370,7 @@ touchscreen@38 { reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; }; }; From 52f2b531948db99c2dc5aaa8f81163c67921ed08 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Tue, 12 Jun 2018 15:32:08 +0200 Subject: [PATCH 04/96] ARM: dts: imx53: Add support for imx53 HSC/DDC boards from K+P This commit provides support for HSC and DDC boards from Kieback&Peter GmbH vendor. Signed-off-by: Lukasz Majewski Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx53-kp-ddc.dts | 146 ++++++++++++++++++++++ arch/arm/boot/dts/imx53-kp-hsc.dts | 52 ++++++++ arch/arm/boot/dts/imx53-kp.dtsi | 189 +++++++++++++++++++++++++++++ 4 files changed, 389 insertions(+) create mode 100644 arch/arm/boot/dts/imx53-kp-ddc.dts create mode 100644 arch/arm/boot/dts/imx53-kp-hsc.dts create mode 100644 arch/arm/boot/dts/imx53-kp.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 30379d342cd6..8b0e081b225d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -362,6 +362,8 @@ dtb-$(CONFIG_SOC_IMX51) += \ dtb-$(CONFIG_SOC_IMX53) += \ imx53-ard.dtb \ imx53-cx9020.dtb \ + imx53-kp-ddc.dtb \ + imx53-kp-hsc.dtb \ imx53-m53evk.dtb \ imx53-mba53.dtb \ imx53-ppd.dtb \ diff --git a/arch/arm/boot/dts/imx53-kp-ddc.dts b/arch/arm/boot/dts/imx53-kp-ddc.dts new file mode 100644 index 000000000000..0e7f071fd10e --- /dev/null +++ b/arch/arm/boot/dts/imx53-kp-ddc.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx53-kp.dtsi" + +/ { + model = "K+P imx53 DDC"; + compatible = "kiebackpeter,imx53-ddc", "fsl,imx53"; + + backlight_lcd: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 50000>; + power-supply = <®_backlight>; + brightness-levels = <0 24 28 32 36 + 40 44 48 52 56 + 60 64 68 72 76 + 80 84 88 92 96 100>; + default-brightness-level = <20>; + }; + + lcd_display: display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp>; + + port@0 { + reg = <0>; + + display1_in: endpoint { + remote-endpoint = <&ipu_di1_disp1>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + lcd_panel: lcd-panel { + compatible = "koe,tx14d24vm1bpa"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "backlight-supply"; + regulator-min-microvolt = <15000000>; + regulator-max-microvolt = <15000000>; + regulator-always-on; + }; +}; + +&fec { + status = "okay"; +}; + +&i2c3 { + adc@48 { + compatible = "ti,ads1015"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <2>; + ti,datarate = <4>; + }; + + channel@6 { + reg = <6>; + ti,gain = <2>; + ti,datarate = <4>; + }; + }; + + gpio-expander2@21 { + compatible = "nxp,pcf8574"; + reg = <0x21>; + interrupts = <109>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&iomuxc { + imx53-kp-ddc { + pinctrl_disp: dispgrp { + fsl,pins = < + MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x4 + MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x4 + MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x4 + MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x4 + MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x4 + MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x4 + MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x4 + MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x4 + MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x4 + MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x4 + MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x4 + MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x4 + MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x4 + MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x4 + MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x4 + MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x4 + MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x4 + MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x4 + MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x4 + MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x4 + MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x4 + MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x4 + MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x4 + MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x4 + MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x4 + MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x4 + MX53_PAD_GPIO_1__PWM2_PWMO 0x4 + >; + }; + }; +}; + +&ipu_di1_disp1 { + remote-endpoint = <&display1_in>; +}; + +&pmic { + fsl,mc13xxx-uses-touch; +}; diff --git a/arch/arm/boot/dts/imx53-kp-hsc.dts b/arch/arm/boot/dts/imx53-kp-hsc.dts new file mode 100644 index 000000000000..6e3d71baac0f --- /dev/null +++ b/arch/arm/boot/dts/imx53-kp-hsc.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx53-kp.dtsi" + +/ { + model = "K+P imx53 HSC"; + compatible = "kiebackpeter,imx53-hsc", "fsl,imx53"; +}; + +&fec { + status = "okay"; + + fixed-link { /* RMII fixed link to LAN9303 */ + speed = <100>; + full-duplex; + }; +}; + +&i2c3 { + switch: switch@a { + compatible = "smsc,lan9303-i2c"; + reg = <0xa>; + reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + reset-duration = <400>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { /* RMII fixed link to master */ + reg = <0>; + label = "cpu"; + ethernet = <&fec>; + }; + + port@1 { /* external port 1 */ + reg = <1>; + label = "lan1"; + }; + + port@2 { /* external port 2 */ + reg = <2>; + label = "lan2"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx53-kp.dtsi b/arch/arm/boot/dts/imx53-kp.dtsi new file mode 100644 index 000000000000..8b25416a5303 --- /dev/null +++ b/arch/arm/boot/dts/imx53-kp.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx53-tqma53.dtsi" +#include + +/ { + buzzer { + compatible = "pwm-beeper"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_buzzer>; + pwms = <&pwm1 0 500000>; + }; + + gpio-buttons { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiobuttons>; + + button-kalt { + label = "Kaltstart"; + linux,code = ; + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + }; + + button-pwr { + label = "PowerFailInterrupt"; + linux,code = ; + gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-bus { + label = "bus"; + gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + + led-error { + label = "error"; + gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + default-state = "off"; + }; + + led-flash { + label = "flash"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + gpio-expander1@22 { + compatible = "nxp,pcf8574"; + reg = <0x22>; + interrupts = <109>; + #gpio-cells = <2>; + gpio-controller; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kp_common>; + + imx53-kp-common { + pinctrl_buzzer: buzzergrp { + fsl,pins = < + MX53_PAD_SD1_DATA3__PWM1_PWMO 0x1e4 + >; + }; + + pinctrl_gpiobuttons: gpiobuttonsgrp { + fsl,pins = < + MX53_PAD_EIM_RW__GPIO2_26 0x1e4 + MX53_PAD_EIM_D22__GPIO3_22 0x1e4 + >; + }; + + pinctrl_kp_common: kpcommongrp { + fsl,pins = < + MX53_PAD_EIM_CS0__GPIO2_23 0x1e4 + MX53_PAD_GPIO_19__GPIO4_5 0x1e4 + MX53_PAD_PATA_DATA6__GPIO2_6 0x1e4 + MX53_PAD_PATA_DATA7__GPIO2_7 0xe0 + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1e4 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1e4 + MX53_PAD_CSI0_DAT18__GPIO6_4 0x1e4 + MX53_PAD_EIM_D17__GPIO3_17 0x1e4 + MX53_PAD_EIM_D18__GPIO3_18 0x1e4 + MX53_PAD_EIM_D21__GPIO3_21 0x1e4 + MX53_PAD_EIM_D29__GPIO3_29 0x1e4 + MX53_PAD_EIM_DA11__GPIO3_11 0x1e4 + MX53_PAD_EIM_DA13__GPIO3_13 0x1e4 + MX53_PAD_EIM_DA14__GPIO3_14 0x1e4 + MX53_PAD_SD1_DATA0__GPIO1_16 0x1e4 + MX53_PAD_SD1_CMD__GPIO1_18 0x1e4 + MX53_PAD_SD1_CLK__GPIO1_20 0x1e4 + >; + }; + + pinctrl_leds: ledgrp { + fsl,pins = < + MX53_PAD_EIM_EB2__GPIO2_30 0x1d4 + MX53_PAD_EIM_D28__GPIO3_28 0x1d4 + MX53_PAD_EIM_WAIT__GPIO5_0 0x1d4 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX53_PAD_CSI0_DAT12__UART4_TXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT13__UART4_RXD_MUX 0x1e4 + >; + }; + }; +}; + +&pinctrl_uart1 { + fsl,pins = < + MX53_PAD_EIM_D23__GPIO3_23 0x1e4 + MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 + MX53_PAD_EIM_D24__GPIO3_24 0x1e4 + MX53_PAD_EIM_D25__GPIO3_25 0x1e4 + MX53_PAD_EIM_D19__GPIO3_19 0x1e4 + MX53_PAD_EIM_D20__GPIO3_20 0x1e4 + >; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy0 { + status = "disabled"; +}; From 6e21e4c215a6e088c0d49fc107fd56361b1fdf22 Mon Sep 17 00:00:00 2001 From: Nikita Yushchenko Date: Thu, 17 May 2018 22:19:23 +0300 Subject: [PATCH 05/96] ARM: dts: imx51-zii-rdu1: add rave-sp subdevices This adds rave-sp powerbutton and backlight devices to RDU1 device tree. Signed-off-by: Nikita Yushchenko Tested-by: Chris Healy Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index df9eca94d812..ad2445dfa91d 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -582,6 +582,14 @@ rave-sp { watchdog { compatible = "zii,rave-sp-watchdog"; }; + + backlight { + compatible = "zii,rave-sp-backlight"; + }; + + pwrbutton { + compatible = "zii,rave-sp-pwrbutton"; + }; }; }; From bcf1477468143170ab98638a09162a3cac221367 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Fri, 25 May 2018 19:12:38 -0700 Subject: [PATCH 06/96] ARM: dts: imx51-zii-rdu1: Make sure SD1_WP is low Make sure that MX51_PAD_GPIO1_1 does not remain configure as ALT0/SD1_WP (it is out of reset). This is needed because of external pull-up resistor attached to that pad that, when left unchanged, will drive SD1_WP high preventing eSDHC1/eMMC from working correctly. To fix that add a pinmux configuration line configureing the pad to function as a GPIO. While we are at it, add a corresponding output-high GPIO hog in an effort to minimize current consumption. Cc: Nikita Yushchenko Cc: Fabio Estevam Cc: Lucas Stach Cc: Chris Healy Cc: Rob Herring Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Tested-By: Nikita Yushchenko Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index ad2445dfa91d..27ea581f7789 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -476,6 +476,17 @@ &fec { status = "okay"; }; +&gpio1 { + unused-sd3-wp-gpio { + /* + * See pinctrl_esdhc1 below for more details on this + */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; @@ -668,6 +679,23 @@ MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + /* + * GPIO1_1 is not directly used by eSDHC1 in + * any capacity, but earlier versions of RDU1 + * used that pin as WP GPIO for eSDHC3 and + * because of that that pad has an external + * pull-up resistor. This is problematic + * because out of reset the pad is configured + * as ALT0 which serves as SD1_WP, which, when + * pulled high by and external pull-up, will + * inhibit execution of any write request to + * attached eMMC device. + * + * To avoid this problem we configure the pad + * to ALT1/GPIO and avoid driving SD1_WP + * signal high. + */ + MX51_PAD_GPIO1_1__GPIO1_1 0x0000 >; }; From 9d1b8418b4773add2ec6ae29cfbd953cf07cc042 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Tue, 29 May 2018 06:20:18 +0000 Subject: [PATCH 07/96] ARM: dts: imx6qdl-wandboard: remove regulators bus node To match the convention, move all regulator-fixed nodes directly into the root node. Signed-off-by: Alexander Kurz Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 40 ++++++++++-------------- 1 file changed, 16 insertions(+), 24 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index e1afa54404d0..52baf6d1a956 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -8,30 +8,6 @@ #include / { - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - sound { compatible = "fsl,imx6-wandboard-sgtl5000", "fsl,imx-audio-sgtl5000"; @@ -52,6 +28,22 @@ sound-spdif { spdif-controller = <&spdif>; spdif-out; }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; &audmux { From d8d5f9dc40e7cf74a78f8e4164854b4eb5e45d8c Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Tue, 29 May 2018 06:20:19 +0000 Subject: [PATCH 08/96] ARM: dts: imx6dl-riotboard: remove regulators bus node To match the convention, move regulator-fixed nodes directly into the root node. Signed-off-by: Alexander Kurz Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-riotboard.dts | 55 +++++++++++--------------- 1 file changed, 23 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 2e98c92adff7..a6851bfebbdb 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -19,38 +19,6 @@ memory@10000000 { reg = <0x10000000 0x40000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - }; - leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -82,6 +50,29 @@ sound { mux-int-port = <1>; mux-ext-port = <3>; }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &audmux { From e732f6d26eeab94a4988a556951bbc015b0c3d16 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Tue, 29 May 2018 06:20:20 +0000 Subject: [PATCH 09/96] ARM: dts: imx6qdl-wandboard: enable USB OTG Enable USB OTG (dual-role) on the Wandboard. Note, that the USB_OTG_VBUS current is quite limited due to a 22R resistor in the power line. Hence, the overcurrent signal of 1A will never be triggered on this board. Signed-off-by: Alexander Kurz Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index 52baf6d1a956..381bf61fcd28 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -44,6 +44,16 @@ reg_3p3v: regulator-3p3v { regulator-max-microvolt = <3300000>; regulator-always-on; }; + + reg_usb_otg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotgvbus>; + gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; + }; }; &audmux { @@ -166,6 +176,12 @@ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 >; }; + pinctrl_usbotgvbus: usbotgvbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 @@ -240,10 +256,11 @@ &usbh1 { }; &usbotg { + vbus-supply = <®_usb_otg_vbus>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; - dr_mode = "peripheral"; + dr_mode = "otg"; status = "okay"; }; From dcae11de22c9da83755d03f2631d7ddf4db00293 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Tue, 29 May 2018 06:20:21 +0000 Subject: [PATCH 10/96] ARM: dts: imx6dl-riotboard: fix OTG regulator polarity USB OTG power is switched on when the GPIO is pulled low. Signed-off-by: Alexander Kurz Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-riotboard.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index a6851bfebbdb..89b06e20480d 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -70,8 +70,7 @@ reg_usb_otg_vbus: regulator-usbotgvbus { regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; + gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; }; }; From 39143301bed9cae5ce1c1c65b0c482ea650bf367 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 6 Jun 2018 11:30:45 +0200 Subject: [PATCH 11/96] ARM: dts: imx6: RDU2: correct touchscreen axis inversion The RMI4 touchscreen driver applied inversion and axis swap in the wrong order, violating the DT binding for those properties. This is fixed now, so correct the RDU2 DT to apply the inversion to the correct axis. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 19a075aee19e..8e154c9bf814 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -569,14 +569,14 @@ rmi4-f01@1 { rmi4-f11@11 { reg = <0x11>; - touchscreen-inverted-y; + touchscreen-inverted-x; touchscreen-swapped-x-y; syna,sensor-type = <1>; }; rmi4-f12@12 { reg = <0x12>; - touchscreen-inverted-y; + touchscreen-inverted-x; touchscreen-swapped-x-y; syna,sensor-type = <1>; }; From a8039f2dd0899a41d869ba2cc0f73a29b519d268 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 7 Jun 2018 19:21:31 +0530 Subject: [PATCH 12/96] ARM: dts: imx6dl: Add Engicam i.CoreM6 1.5 Quad/Dual MIPI starter kit support i.CoreM6 1.5 is an another i.CoreM6 QDL cpu modules which can be connected to EDIMM starter kit design with eMMC and MIPI-CSI interfaces suitable for Android and video capture application. notable features: CPU NXP i.MX6 S/DL/D/Q, Up to 4 x Cortex-A9@800MHz Memory Up to 2 GB DDR3-1066 Video Interfaces Up to 1 Parallel Up to 2 LVDS HDMI 1.4 port 8 bit CSI INPUT MIPI-CSI INPUT 1 x 10/100 Ethernet interface, 2 x USB, 1 x PCIe, 1 x I2S etc Signed-off-by: Jagan Teki Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-icore-mipi.dts | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-icore-mipi.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8b0e081b225d..bc63b4c81dfe 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -402,6 +402,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-hummingboard2-emmc-som-v15.dtb \ imx6dl-hummingboard2-som-v15.dtb \ imx6dl-icore.dtb \ + imx6dl-icore-mipi.dtb \ imx6dl-icore-rqs.dtb \ imx6dl-mamoj.dtb \ imx6dl-nit6xlite.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-icore-mipi.dts b/arch/arm/boot/dts/imx6dl-icore-mipi.dts new file mode 100644 index 000000000000..bf53f0552aa1 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-icore-mipi.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Engicam S.r.l. + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-icore.dtsi" + +/ { + model = "Engicam i.CoreM6 DualLite/Solo MIPI Starter Kit"; + compatible = "engicam,imx6-icore", "fsl,imx6dl"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; From 3992516af3846bc2dcba002de5d7c908be5c06de Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 7 Jun 2018 19:21:32 +0530 Subject: [PATCH 13/96] ARM: dts: imx6q-icore-mipi: Add OV5640 Camera sensor OV5640 Camera sensor is connected in i.CoreM6 1.5 Quad/Dual MIPI starter kit. This patch also move MX6QDL_PAD_GPIO_0__CCM_CLKO1 pinctrl from i2c3 to ov5640 pinctrl. Signed-off-by: Jagan Teki Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-icore-mipi.dts | 8 +++++ arch/arm/boot/dts/imx6qdl-icore.dtsi | 46 +++++++++++++++++++++++++- 2 files changed, 53 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6q-icore-mipi.dts b/arch/arm/boot/dts/imx6q-icore-mipi.dts index acd3d33476d4..95b2efda17b4 100644 --- a/arch/arm/boot/dts/imx6q-icore-mipi.dts +++ b/arch/arm/boot/dts/imx6q-icore-mipi.dts @@ -20,6 +20,14 @@ &hdmi { status = "okay"; }; +&mipi_csi { + status = "okay"; +}; + +&ov5640 { + status = "okay"; +}; + &usdhc3 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi index 0a1574998fc6..be8aa55c973e 100644 --- a/arch/arm/boot/dts/imx6qdl-icore.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi @@ -215,6 +215,29 @@ &i2c3 { pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; + ov5640: camera@3c { + compatible = "ovti,ov5640"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + reg = <0x3c>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "xclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_3p3v>; + DVDD-supply = <®_3p3v>; + powerdown-gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>; + status = "disabled"; + + port { + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + sgtl5000: codec@a { #sound-dai-cells = <0>; compatible = "fsl,sgtl5000"; @@ -226,6 +249,20 @@ sgtl5000: codec@a { }; }; +&mipi_csi { + status = "disabled"; + + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; +}; + &pwm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; @@ -353,7 +390,14 @@ pinctrl_i2c3: i2c3grp { fsl,pins = < MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_ov5640: ov5640grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 >; }; From f3af1e5c0c6fe20cd2cc3ae5512c79d8e2dfbfba Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Thu, 7 Jun 2018 19:21:33 +0530 Subject: [PATCH 14/96] ARM: dts: imx6qdl-icore: Fix wrong reg_2p5 regulator node name - in reg_2p5, fix regulator node name as regulator-2p5v - remove exctra line Signed-off-by: Jagan Teki Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-icore.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-icore.dtsi b/arch/arm/boot/dts/imx6qdl-icore.dtsi index be8aa55c973e..9ce993776160 100644 --- a/arch/arm/boot/dts/imx6qdl-icore.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore.dtsi @@ -65,8 +65,7 @@ reg_1p8v: regulator-1p8v { regulator-always-on; }; - - reg_2p5v: regulator-3p3v { + reg_2p5v: regulator-2p5v { compatible = "regulator-fixed"; regulator-name = "2P5V"; regulator-min-microvolt = <2500000>; From a211b8c55f3ce54423bd1daf1bca82271b08ac2f Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Mon, 18 Jun 2018 11:15:44 +0300 Subject: [PATCH 15/96] ARM: dts: imx6qdl-sabreauto: Add sensors The following sensors are on I2C3 on the baseboard: * isil,isl29023 light sensor * fsl,mag3110 magnetometer * fsl,mma8451 accelerometer Added under i2cmux/i2c@1 because they're not otherwise accessible. These are all supported by iio with following configs: * CONFIG_SENSORS_ISL29018 * CONFIG_MAG3110 * CONFIG_MMA8452 Tested with raw reads from iio sysfs. Signed-off-by: Leonard Crestez Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 0e28e36ddbb2..a59a0fd1eb02 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -155,6 +155,27 @@ max7310_c: gpio@34 { gpio-controller; #gpio-cells = <2>; }; + + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_EDGE_FALLING>; + }; + + magnetometer@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + interrupt-parent = <&gpio2>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + }; + + accelerometer@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + interrupt-parent = <&gpio6>; + interrupts = <31 IRQ_TYPE_LEVEL_LOW>; + }; }; }; }; From 13d8f1762bf64c564317695b573b0b2528a90af9 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Mon, 18 Jun 2018 16:11:09 +0300 Subject: [PATCH 16/96] ARM: dts: imx7d-sdb: Remove duplicate regulator-can2-3v3 Two different regulators are defined with the same name and label but distinct properties. The first definition was added with the first board dts and the second was added when upstream added flexcan support. Looking at schematics it is indeed gpio2 14 connected to the STB pin of the CAN transceiver so remove the first definition. The second definition entirely overrides the first so this already worked and this patch results in no DTB change, just a cleanup. Signed-off-by: Leonard Crestez Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-sdb.dts | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 940849163104..9f9e6a1e3b72 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -71,14 +71,6 @@ reg_usb_otg2_vbus: regulator-usb-otg2-vbus { enable-active-high; }; - reg_can2_3v3: regulator-can2-3v3 { - compatible = "regulator-fixed"; - regulator-name = "can2-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; - }; - reg_vref_1v8: regulator-vref-1v8 { compatible = "regulator-fixed"; regulator-name = "vref-1v8"; From 328bd82526156fbc42372d22ff1967dc145d81c8 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Wed, 13 Dec 2017 15:24:06 +0100 Subject: [PATCH 17/96] ARM: dts: imx51: add CodaHx4 VPU Add the CodaHx4 VPU to the i.MX51 device tree. Signed-off-by: Philipp Zabel Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index fe01b890c715..3f65492c6589 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -588,6 +588,17 @@ fec: ethernet@83fec000 { clock-names = "ipg", "ahb", "ptp"; status = "disabled"; }; + + vpu@83ff4000 { + compatible = "fsl,imx51-vpu", "cnm,codahx4"; + reg = <0x83ff4000 0x1000>; + interrupts = <9>; + clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, + <&clks IMX5_CLK_VPU_GATE>; + clock-names = "per", "ahb"; + resets = <&src 1>; + iram = <&iram>; + }; }; }; }; From f3d80deb080f422ff1df4a715444f156bb51adc1 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 8 Jun 2018 11:06:40 +0200 Subject: [PATCH 18/96] ARM: dts: imx: add cooling-cells for cpufreq cooling device Add #cooling-cells for i.MX6/7 SoCs for cpufreq cooling device usage. Signed-off-by: Anson Huang Signed-off-by: Bastian Stender Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl.dtsi | 1 + arch/arm/boot/dts/imx6q.dtsi | 1 + arch/arm/boot/dts/imx6sl.dtsi | 1 + arch/arm/boot/dts/imx6sx.dtsi | 1 + arch/arm/boot/dts/imx6ul.dtsi | 1 + arch/arm/boot/dts/imx7d.dtsi | 1 + 6 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index b384913c34dd..a1acd4ddcb1a 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -33,6 +33,7 @@ cpu@0 { 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6QDL_CLK_ARM>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 70483ce72ba6..894401c5db09 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -38,6 +38,7 @@ cpu0: cpu@0 { 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6QDL_CLK_ARM>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 994e48dc1df0..81f48116c5b1 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -60,6 +60,7 @@ cpu@0 { 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PLL1_SYS>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index d8b94f47498b..7130ab8a7518 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -79,6 +79,7 @@ cpu0: cpu@0 { 198000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6SX_CLK_ARM>, <&clks IMX6SX_CLK_PLL2_PFD2>, <&clks IMX6SX_CLK_STEP>, diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 47a3453a4211..36572b62a4af 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -62,6 +62,7 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0>; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; operating-points = < /* kHz uV */ 696000 1275000 diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 8d3d123d0a5c..7cbc2ffa4b3a 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -11,6 +11,7 @@ cpus { cpu0: cpu@0 { clock-frequency = <996000000>; operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; }; cpu1: cpu@1 { From fdfbd7d125fd8e2536954fdd63a5738bceb7896f Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Mon, 18 Jun 2018 17:42:57 +0200 Subject: [PATCH 19/96] ARM: dts: imx6: RIoTboard Add chosen stdout-path property The RIoTboard debug uart is connected to serial1. Add a chosen property in the DTS so OS knows what serial port to use for the console. Signed-off-by: Emmanuel Vadot Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-riotboard.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 89b06e20480d..dd3226fe5ecd 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -19,6 +19,10 @@ memory@10000000 { reg = <0x10000000 0x40000000>; }; + chosen { + stdout-path = "serial1:115200n8"; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; From eecd78bc7805964527acdaba5f2b91d7b317aeea Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 20 Jun 2018 16:38:37 +0800 Subject: [PATCH 20/96] ARM: dts: imx6sll: declare src module to be compatible to imx51's src i.MX6SLL uses same SRC module as i.MX51, add "fsl,imx51-src" compatible string to enable SRC driver to support setting CPU resume address for cpu-idle and suspend/resume. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index c9b0ccc0e2e2..000e6136a9d6 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -548,7 +548,7 @@ snvs_pwrkey: snvs-powerkey { }; src: reset-controller@20d8000 { - compatible = "fsl,imx6sll-src"; + compatible = "fsl,imx6sll-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = , ; From 4a23e6ee9f691cfbd6bfc99c2c5aa8d23d8c1662 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Wed, 20 Jun 2018 13:41:16 +0300 Subject: [PATCH 21/96] ARM: dts: imx7d-sdb: Restore pwm backlight support This was removed in commit 5eaeaccdaedb ("ARM: dts: imx7d-sdb: Pass 'enable-gpios' and 'power-supply' properties") with a note claiming that GPIO1_IO01 is connected to a pin labeled as "PWREN" on the connector. Despite that label this pin does actually work as a PWM controlling brightness. So restore pwm functionality. Signed-off-by: Leonard Crestez Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-sdb.dts | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 9f9e6a1e3b72..8d137acb9f07 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -108,10 +108,17 @@ reg_can2_3v3: regulator-can2-3v3 { gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + panel { compatible = "innolux,at043tn24"; - pinctrl-0 = <&pinctrl_backlight>; - enable-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; power-supply = <®_lcd_3v3>; port { @@ -704,6 +711,12 @@ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b }; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + &iomuxc_lpsr { pinctrl_wdog: wdoggrp { fsl,pins = < @@ -711,9 +724,9 @@ MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 >; }; - pinctrl_backlight: backlightgrp { + pinctrl_pwm1: pwm1grp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x110b0 + MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 >; }; }; From ba72b5a49957d92bfa7101a67e2414e166847291 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 20 Jun 2018 15:06:19 -0300 Subject: [PATCH 22/96] ARM: dts: imx51: Add aipstz nodes Currently when trying to use the 'devmem' tool to read/write registers the following bus error is observed: [ 82.689185] Unhandled fault: external abort on non-linefetch (0x1018) at 0xb6ff10c4 [ 82.697071] pgd = (ptrval) [ 82.699920] [b6ff10c4] *pgd=a87c5831, *pte=73fa8383, *ppte=73fa8a33 Bus error Add the aipstz nodes, so that the following function from imx51_dt_init() can work properly: imx_aips_allow_unprivileged_access("fsl,imx51-aipstz"); After adding these nodes, 'devmem' tool can work correctly, which is very useful for debugging purposes. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 3f65492c6589..d5ba31e3cd50 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -250,6 +250,11 @@ esdhc4: esdhc@70024000 { }; }; + aipstz1: bridge@73f00000 { + compatible = "fsl,imx51-aipstz"; + reg = <0x73f00000 0x60>; + }; + usbotg: usb@73f80000 { compatible = "fsl,imx51-usb", "fsl,imx27-usb"; reg = <0x73f80000 0x0200>; @@ -435,6 +440,11 @@ aips@80000000 { /* AIPS2 */ reg = <0x80000000 0x10000000>; ranges; + aipstz2: bridge@83f00000 { + compatible = "fsl,imx51-aipstz"; + reg = <0x83f00000 0x60>; + }; + iim: iim@83f98000 { compatible = "fsl,imx51-iim", "fsl,imx27-iim"; reg = <0x83f98000 0x4000>; From ff6f5a691cd9f346e323c2a74937c1af5025f751 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Sun, 24 Jun 2018 05:59:29 +0000 Subject: [PATCH 23/96] ARM: dts: imx50: fix KPP pin definition typos iMX50 pin mux options for pads KEY_COL2 and KEY_COL3 allow muxing the same KEY_COL instances as the pad name. Fix typos shifting KEY_COL instances. Signed-off-by: Alexander Kurz Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50-pinfunc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx50-pinfunc.h b/arch/arm/boot/dts/imx50-pinfunc.h index 97e6e7f4ebdd..43863347362e 100644 --- a/arch/arm/boot/dts/imx50-pinfunc.h +++ b/arch/arm/boot/dts/imx50-pinfunc.h @@ -34,7 +34,7 @@ #define MX50_PAD_KEY_ROW1__EIM_NANDF_CEN_1 0x02c 0x2d8 0x000 0x2 0x0 #define MX50_PAD_KEY_ROW1__CTI_TRIGOUT_ACK7 0x02c 0x2d8 0x000 0x6 0x0 #define MX50_PAD_KEY_ROW1__USBPHY1_RXERROR 0x02c 0x2d8 0x000 0x7 0x0 -#define MX50_PAD_KEY_COL2__KPP_COL_1 0x030 0x2dc 0x000 0x0 0x0 +#define MX50_PAD_KEY_COL2__KPP_COL_2 0x030 0x2dc 0x000 0x0 0x0 #define MX50_PAD_KEY_COL2__GPIO4_4 0x030 0x2dc 0x000 0x1 0x0 #define MX50_PAD_KEY_COL2__EIM_NANDF_CEN_2 0x030 0x2dc 0x000 0x2 0x0 #define MX50_PAD_KEY_COL2__CTI_TRIGOUT6 0x030 0x2dc 0x000 0x6 0x0 @@ -44,7 +44,7 @@ #define MX50_PAD_KEY_ROW2__EIM_NANDF_CEN_3 0x034 0x2e0 0x000 0x2 0x0 #define MX50_PAD_KEY_ROW2__CTI_TRIGOUT7 0x034 0x2e0 0x000 0x6 0x0 #define MX50_PAD_KEY_ROW2__USBPHY1_LINESTATE_0 0x034 0x2e0 0x000 0x7 0x0 -#define MX50_PAD_KEY_COL3__KPP_COL_2 0x038 0x2e4 0x000 0x0 0x0 +#define MX50_PAD_KEY_COL3__KPP_COL_3 0x038 0x2e4 0x000 0x0 0x0 #define MX50_PAD_KEY_COL3__GPIO4_6 0x038 0x2e4 0x000 0x1 0x0 #define MX50_PAD_KEY_COL3__EIM_NANDF_READY0 0x038 0x2e4 0x7b4 0x2 0x0 #define MX50_PAD_KEY_COL3__SDMA_EXT_EVENT_0 0x038 0x2e4 0x7b8 0x6 0x0 From 54c43959ab7066fb2acf0427d6a1bb983d9971b4 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Sun, 24 Jun 2018 06:15:38 +0000 Subject: [PATCH 24/96] ARM: dts: imx50: remove non-existent USB instances According to the i.MX50 Reference Manual, the SoC features one USB OTG and one host controller. Remove the non-existent instances from the DTS which probably got initially copied from the mx53 DTS. Signed-off-by: Alexander Kurz Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50-evk.dts | 8 -------- arch/arm/boot/dts/imx50.dtsi | 18 ------------------ 2 files changed, 26 deletions(-) diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts index f0622ec4ba9c..682a99783ee6 100644 --- a/arch/arm/boot/dts/imx50-evk.dts +++ b/arch/arm/boot/dts/imx50-evk.dts @@ -98,14 +98,6 @@ &usbh1 { status = "okay"; }; -&usbh2 { - status = "okay"; -}; - -&usbh3 { - status = "okay"; -}; - &usbotg { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index a9b712db9f6c..7fae2ffb76fe 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -209,24 +209,6 @@ usbh1: usb@53f80200 { status = "disabled"; }; - usbh2: usb@53f80400 { - compatible = "fsl,imx50-usb", "fsl,imx27-usb"; - reg = <0x53f80400 0x0200>; - interrupts = <16>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - dr_mode = "host"; - status = "disabled"; - }; - - usbh3: usb@53f80600 { - compatible = "fsl,imx50-usb", "fsl,imx27-usb"; - reg = <0x53f80600 0x0200>; - interrupts = <17>; - clocks = <&clks IMX5_CLK_USBOH3_GATE>; - dr_mode = "host"; - status = "disabled"; - }; - gpio1: gpio@53f84000 { compatible = "fsl,imx50-gpio", "fsl,imx35-gpio"; reg = <0x53f84000 0x4000>; From 76744502ff328a0a00ca46601da871a96539997d Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Mon, 25 Jun 2018 23:09:32 +0300 Subject: [PATCH 25/96] ARM: dts: imx: Add missing chosen/stdout-path This makes it possible to enable earlycon for debugging by just passing an empty "earlycon" argument on the kernel command-line. Signed-off-by: Leonard Crestez Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 ++++ arch/arm/boot/dts/imx6sl-evk.dts | 4 ++++ arch/arm/boot/dts/imx6sll-evk.dts | 4 ++++ arch/arm/boot/dts/imx7d-sdb.dts | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index a59a0fd1eb02..9f11f1fcc3e6 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -6,6 +6,10 @@ #include / { + chosen { + stdout-path = &uart4; + }; + memory@10000000 { reg = <0x10000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 92ad01f676e3..50bdc65670a3 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -12,6 +12,10 @@ / { model = "Freescale i.MX6 SoloLite EVK Board"; compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; + chosen { + stdout-path = &uart1; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index 4684ac4a816b..25438ea03092 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -15,6 +15,10 @@ / { model = "Freescale i.MX6SLL EVK Board"; compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; + chosen { + stdout-path = &uart1; + }; + memory@80000000 { reg = <0x80000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 8d137acb9f07..c9b3c60b0eb2 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -10,6 +10,10 @@ / { model = "Freescale i.MX7 SabreSD Board"; compatible = "fsl,imx7d-sdb", "fsl,imx7d"; + chosen { + stdout-path = &uart1; + }; + memory@80000000 { reg = <0x80000000 0x80000000>; }; From 10d11dad4a4e343652fca86bda3b10684be30d4e Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 26 Jun 2018 16:52:41 +0200 Subject: [PATCH 26/96] ARM: dts: imx6qdl-colibri: mux SD/MMC card detect explicitly Do not rely on reset/boot defaults and use a default GPIO setting with pull-up enabled. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 76035db96f67..83d7c7d48c3f 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -567,7 +567,7 @@ MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x1b0b0 pinctrl_mmc_cd: gpiommccd { fsl,pins = < - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 >; }; From c768224360094b3e3b11c81a4163a9e1c7bd3336 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 26 Jun 2018 16:52:42 +0200 Subject: [PATCH 27/96] ARM: dts: imx6qdl-colibri: move card detect to module device tree Muxing the card detect only in the carrier board device tree overwrites the USDHC muxing in the module level device tree. Move card detect to the module level device tree since this is also a default pinout of the Colibri standard. If a carrier board requires a different setting it still can overwrite the nodes in the carrier board specific device tree. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts | 3 --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 3 ++- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index 3dee3af1a4c1..9de45a717356 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -221,9 +221,6 @@ &usbotg { /* Colibri MMC */ &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc_cd>; - cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 83d7c7d48c3f..55c90c2fbf69 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -385,7 +385,8 @@ &usbotg { /* Colibri MMC */ &usdhc1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ vqmmc-supply = <®_3p3v>; bus-width = <4>; voltage-ranges = <3300 3300>; From c4288946d43ed2d76247ab757581ce428c90d9ef Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 26 Jun 2018 16:52:43 +0200 Subject: [PATCH 28/96] ARM: dts: imx6qdl-colibri: use pull-down on wake-up pin The wake-up pin is pulled low with 100kOhm on the carrier board. The current configuration of 100kOhm pull-up caused lots of interrupts, especially during boot up. Make sure the pin is at a reasonable level at startup by pulling it low on SoC side too. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 55c90c2fbf69..6e937ca20869 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -480,8 +480,7 @@ MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 pinctrl_gpio_keys: gpiokeys { fsl,pins = < - /* Power button */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 >; }; From 9152743b298ef67619766eb55a6ac31055eb5b46 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 26 Jun 2018 20:18:52 -0300 Subject: [PATCH 29/96] ARM: dts: imx51: Add sahara crypto support The sahara crypto block on i.MX51 has the same IP version as the one on i.MX53. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index d5ba31e3cd50..5bb727a5b6a3 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -609,6 +609,15 @@ vpu@83ff4000 { resets = <&src 1>; iram = <&iram>; }; + + sahara: crypto@83ff8000 { + compatible = "fsl,imx53-sahara", "fsl,imx51-sahara"; + reg = <0x83ff8000 0x4000>; + interrupts = <19 20>; + clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, + <&clks IMX5_CLK_SAHARA_IPG_GATE>; + clock-names = "ipg", "ahb"; + }; }; }; }; From 3428d14d8a912b5231e9672261013fdd1bede2de Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 26 Jun 2018 21:05:01 -0300 Subject: [PATCH 30/96] ARM: dts: imx6ull: Switch to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull.dtsi | 43 +++------------------------------- 1 file changed, 3 insertions(+), 40 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index ebc25c98e5e1..70a28628e9b0 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -1,43 +1,6 @@ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright 2016 Freescale Semiconductor, Inc. #include "imx6ul.dtsi" #include "imx6ull-pinfunc.h" From 3d177f483e2bc1852e119f9f9a58b7d7d65ef18d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 26 Jun 2018 21:34:22 -0300 Subject: [PATCH 31/96] ARM: dts: imx53-qsb: Let the codec control MCLK pinctrl The hog pinctrl hog is meant for pins that do not have an associated driver. The MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK pin is the one that provides the MCLK signal to the SGTL5000 codec, so a better represenation is to move it under the codec node. While at it, change the pinctrl value from 0x80000000 to the POR reset value of register IOMUXC_SW_PAD_CTL_PAD_GPIO_0. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-qsb-common.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi index ef7658a78836..7423d462d1e4 100644 --- a/arch/arm/boot/dts/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi @@ -153,7 +153,6 @@ &iomuxc { imx53-qsb { pinctrl_hog: hoggrp { fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 MX53_PAD_GPIO_8__GPIO1_8 0x80000000 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 @@ -180,6 +179,12 @@ MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 >; }; + pinctrl_codec: codecgrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 + >; + }; + pinctrl_esdhc1: esdhc1grp { fsl,pins = < MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 @@ -310,6 +315,8 @@ &i2c2 { sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; #sound-dai-cells = <0>; VDDA-supply = <®_3p2v>; VDDIO-supply = <®_3p2v>; From 6e1a8a621ed1b9f170172fa13b6855d1b69774ca Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Wed, 27 Jun 2018 21:24:21 -0700 Subject: [PATCH 32/96] ARM: dts: imx51-zii-rdu1: Populate RAVE SP EEPROM nodes ZII's RDU1s come with up to 3 EEPROMs attached to RAVE SP. Add corresponding nodes to make them availible. Cc: Fabio Estevam Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index 27ea581f7789..3d2baf1eeb4b 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -589,6 +589,8 @@ &uart3 { rave-sp { compatible = "zii,rave-sp-rdu1"; current-speed = <38400>; + #address-cells = <1>; + #size-cells = <1>; watchdog { compatible = "zii,rave-sp-watchdog"; @@ -601,6 +603,33 @@ backlight { pwrbutton { compatible = "zii,rave-sp-pwrbutton"; }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "dds-eeprom"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + + eeprom@ae { + compatible = "zii,rave-sp-eeprom"; + reg = <0xae 0x200>; + zii,eeprom-name = "switch-eeprom"; + /* + * Not all RDU1s have this functionality, so we + * rely on the bootloader to enable this + */ + status = "disabled"; + }; }; }; From ec84fd24cfaec7bb4782a2983e933cbf8500ab8b Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Wed, 27 Jun 2018 21:24:22 -0700 Subject: [PATCH 33/96] ARM: dts: imx6qdl-zii-rdu2: Populate RAVE SP EEPROM nodes ZII's RDU2s come with two EEPROMs attached to RAVE SP. Add corresponding nodes to make them availible. Cc: Fabio Estevam Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 8e154c9bf814..1d38257be27a 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -320,10 +320,28 @@ &uart4 { rave-sp { compatible = "zii,rave-sp-rdu2"; current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; watchdog { compatible = "zii,rave-sp-watchdog"; }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "dds-eeprom"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; }; }; From 8cbcf1d2dbc006baa42fc1656d6ede1631e72b1c Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Wed, 27 Jun 2018 21:24:23 -0700 Subject: [PATCH 34/96] ARM: dts: imx6qdl-zii-rdu2: Populate RAVE SP backlight node RAVE SP found on RDU2 implements backlight control compatible with the rave-sp-backlight driver. Add a node to make it availible. Cc: Fabio Estevam Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 1d38257be27a..edb5d11c5f4b 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -327,6 +327,10 @@ watchdog { compatible = "zii,rave-sp-watchdog"; }; + backlight { + compatible = "zii,rave-sp-backlight"; + }; + eeprom@a3 { compatible = "zii,rave-sp-eeprom"; reg = <0xa3 0x4000>; From 4508a44da371f38a0beceb6ff82028359dd8cdaa Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Wed, 27 Jun 2018 21:24:24 -0700 Subject: [PATCH 35/96] ARM: dts: imx6qdl-zii-rdu2: Populate RAVE SP power button node RAVE SP found on RDU2 implements power button control compatible with the rave-sp-pwrbutton driver. Add a node to make it availible. Cc: Fabio Estevam Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index edb5d11c5f4b..87c60a853f8b 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -331,6 +331,10 @@ backlight { compatible = "zii,rave-sp-backlight"; }; + pwrbutton { + compatible = "zii,rave-sp-pwrbutton"; + }; + eeprom@a3 { compatible = "zii,rave-sp-eeprom"; reg = <0xa3 0x4000>; From 2d0b768bd1a8a1b83ac3ce3c5600075ee115fb21 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 28 Jun 2018 09:04:27 +0800 Subject: [PATCH 36/96] ARM: dts: imx6sll-evk: enable usdhc3 slot On i.MX6SLL EVK board, SD3 slot can be used for WiFi and other SD accessories, enable it. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-evk.dts | 65 +++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index 25438ea03092..bc8d155cbfbc 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -88,6 +88,17 @@ reg_sd1_vmmc: regulator-sd1-vmmc { gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_sd3_vmmc: regulator-sd3-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_sd3_vmmc>; + regulator-name = "SD3_WIFI"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &cpu0 { @@ -239,7 +250,25 @@ &usbotg2 { status = "okay"; }; +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd3_vmmc>; + status = "okay"; +}; + &iomuxc { + pinctrl_reg_sd3_vmmc: sd3vmmcgrp { + fsl,pins = < + MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 + >; + }; + pinctrl_usb_otg1_vbus: vbus1grp { fsl,pins = < MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 @@ -310,6 +339,42 @@ MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 >; }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17061 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13061 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17061 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17061 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17061 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17061 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170a1 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170a1 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170a1 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170a1 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170e9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170e9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170e9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170e9 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 From 47768f372eae030db6fab5225f9504a820d2c07f Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 25 May 2018 16:01:48 +0530 Subject: [PATCH 37/96] ARM: dts: ls1021a: Add missing cooling device properties for CPUs The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Signed-off-by: Viresh Kumar Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index c55d479971cc..f18490548c78 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -84,6 +84,7 @@ cpu1: cpu@f01 { device_type = "cpu"; reg = <0xf01>; clocks = <&clockgen 1 0>; + #cooling-cells = <2>; }; }; From cc3aba48e0d4f79ca1623248aefb7e83bb8680c8 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Tue, 3 Jul 2018 13:43:47 +0800 Subject: [PATCH 38/96] ARM: dts: imx51-babbage: Make use of pinctrl_usbh1reg Pinctrl_usbh1reg defines pinmux setting for reset GPIO used by usbh1phy, but is not referenced by that node. Fix that. Signed-off-by: Andrey Smirnov Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index b8ca73d3d379..4fb0d4d480a8 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -177,6 +177,8 @@ usbphy { usbh1phy: usbh1phy@0 { compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1reg>; reg = <0>; clocks = <&clk_usb>; clock-names = "main_clk"; From 5bb59c8003650993f89a0c99090ac1a8d37fb63e Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 28 Jun 2018 18:36:38 +0200 Subject: [PATCH 39/96] ARM: dts: imx53-ppd: Add fixed-regulator information Add information about 3V3 power rail to avoid kernel warnings, that dummy regulators have been added. Signed-off-by: Sebastian Reichel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-ppd.dts | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts index 3aa6f693fa9f..30bbe0d740ee 100644 --- a/arch/arm/boot/dts/imx53-ppd.dts +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -140,6 +140,25 @@ reg_tsiref: regulator-tsiref { regulator-always-on; }; + reg_3v3: regulator-3v3 { + /* TPS54320 */ + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_3v3_lcd: regulator-3v3-lcd { + /* MIC2009 */ + compatible = "regulator-fixed"; + regulator-name = "LCD_3V3"; + vin-supply = <®_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + pwm_bl: backlight { compatible = "pwm-backlight"; pwms = <&pwm2 0 50000>; @@ -154,6 +173,7 @@ pwm_bl: backlight { 234 237 239 242 244 247 249 252 255>; default-brightness-level = <0>; enable-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3_lcd>; }; leds { @@ -200,6 +220,7 @@ touch-lock-button { usbphy2: usbphy2 { compatible = "usb-nop-xceiv"; + vcc-supply = <®_3v3>; reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; clock-names = "main_clk"; clock-frequency = <24000000>; @@ -210,6 +231,7 @@ usbphy2: usbphy2 { usbphy3: usbphy3 { compatible = "usb-nop-xceiv"; + vcc-supply = <®_3v3>; reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; clock-names = "main_clk"; @@ -221,6 +243,7 @@ usbphy3: usbphy3 { panel-lvds0 { compatible = "nvd,9128"; + power-supply = <®_3v3_lcd>; port { panel_in_lvds0: endpoint { @@ -230,6 +253,14 @@ panel_in_lvds0: endpoint { }; }; +&usbphy0 { + vcc-supply = <®_3v3>; +}; + +&usbphy1 { + vcc-supply = <®_3v3>; +}; + &audmux { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; @@ -414,6 +445,7 @@ &esdhc3 { &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; + phy-supply = <®_3v3>; phy-mode = "rmii"; phy-reset-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; status = "okay"; From 5180ee394fe81849e65bc89bfb54a6ec5fe88c75 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 28 Jun 2018 18:36:39 +0200 Subject: [PATCH 40/96] ARM: dts: imx53-ppd: Rename usbphy nodes This renames usbphy nodes 2 & 3, so that they follow the same format as usbphy node 0 & 1 from imx53.dtsi. Signed-off-by: Sebastian Reichel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-ppd.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts index 30bbe0d740ee..444ec84cf342 100644 --- a/arch/arm/boot/dts/imx53-ppd.dts +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -218,7 +218,7 @@ touch-lock-button { }; }; - usbphy2: usbphy2 { + usbphy2: usbphy-2 { compatible = "usb-nop-xceiv"; vcc-supply = <®_3v3>; reset-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; @@ -229,7 +229,7 @@ usbphy2: usbphy2 { assigned-clock-parents = <&clks IMX5_CLK_OSC>; }; - usbphy3: usbphy3 { + usbphy3: usbphy-3 { compatible = "usb-nop-xceiv"; vcc-supply = <®_3v3>; reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; From 5128666b17b4c64c6f9911ea78f578dbaf153bbb Mon Sep 17 00:00:00 2001 From: Nick Dyer Date: Thu, 28 Jun 2018 23:56:26 +0100 Subject: [PATCH 41/96] ARM: dts: imx51-zii-rdu1: correct touchscreen axis inversion The RMI4 touchscreen driver applied inversion and axis swap in the wrong order, violating the DT binding for those properties. This was fixed in 645a397, so correct the RDU1 DT to apply the inversion to the correct axis. Tested on Zii RDU1 00-5105-30 rev B Signed-off-by: Nick Dyer Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index 3d2baf1eeb4b..aede622c47a5 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -553,7 +553,7 @@ rmi4-f01@1 { rmi4-f11@11 { reg = <0x11>; - touchscreen-inverted-y; + touchscreen-inverted-x; touchscreen-swapped-x-y; syna,sensor-type = <1>; }; From 7d034c5c6106b6f9ae13a67eaa98f558f430e33b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Szymanski?= Date: Fri, 29 Jun 2018 16:52:21 +0200 Subject: [PATCH 42/96] ARM: dts: imx6ull: add operating points MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit i.MX6ULL has different operating ranges than i.MX6UL so add the operating points for the i.MX6ULL and remove them from board device trees. A 25mV offset is added to the minimum allowed values like for the i.MX6UL. The valid frequencies are now selected by the cpufreq driver according to ratings stored in fuses since commit 0aa9abd4c212 ("cpufreq: imx6q: check speed grades for i.MX6ULL") Signed-off-by: Sébastien Szymanski Acked-by: Viresh Kumar Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 14 -------------- arch/arm/boot/dts/imx6ull.dtsi | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi index 3dffbcd50bf6..183193e8580d 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi @@ -20,20 +20,6 @@ wifi_pwrseq: sdio-pwrseq { &cpu0 { clock-frequency = <792000000>; - operating-points = < - /* kHz uV */ - 792000 1225000 - 528000 1175000 - 396000 1025000 - 198000 950000 - >; - fsl,soc-operating-points = < - /* KHz uV */ - 792000 1175000 - 528000 1175000 - 396000 1175000 - 198000 1175000 - >; }; &iomuxc { diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index 70a28628e9b0..cd1776a7015a 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -11,6 +11,25 @@ /* Delete CAAM node in AIPS-2 (i.MX6UL specific) */ /delete-node/ &crypto; +&cpu0 { + operating-points = < + /* kHz uV */ + 900000 1275000 + 792000 1225000 + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 900000 1175000 + 792000 1175000 + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + / { soc { aips3: aips-bus@2200000 { From e878647ec4dd662f16df1d7fcbfac68a9b20ea81 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 1 Jul 2018 19:56:01 -0300 Subject: [PATCH 43/96] ARM: dts: imx6sll: Fix the SPDX notation for header file Per Documentation/process/license-rules.rst the SPDX notation for header file should be /* */ style, so fix it accordingly. Fixes: 9f30b6b1a957 ("ARM: dts: imx: Add basic dtsi file for imx6sll") Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-pinfunc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6sll-pinfunc.h b/arch/arm/boot/dts/imx6sll-pinfunc.h index b1c40dcdb42f..713a346f4c89 100644 --- a/arch/arm/boot/dts/imx6sll-pinfunc.h +++ b/arch/arm/boot/dts/imx6sll-pinfunc.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright 2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP. From 77cf8a009df8a47ba0c8f32b0d6bb6cbfb55a17e Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 2 Jul 2018 10:04:36 +0800 Subject: [PATCH 44/96] ARM: dts: imx6: correct anatop regulators range According to i.MX6 datasheet, the LDO_1P1's typical programming operating range is 1.0V to 1.2V, and the LDO_2P5's typical programming operating range is 2.25V to 2.75V, correct LDO_1P1 and LDO_2P5's regulator range settings for i.MX6 SoCs. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 8 ++++---- arch/arm/boot/dts/imx6sx.dtsi | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 81f48116c5b1..c64bd906ad55 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -524,8 +524,8 @@ anatop: anatop@20c8000 { regulator-1p1 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1375000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; regulator-always-on; anatop-reg-offset = <0x110>; anatop-vol-bit-shift = <8>; @@ -554,8 +554,8 @@ regulator-3p0 { regulator-2p5 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2850000>; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <2750000>; regulator-always-on; anatop-reg-offset = <0x130>; anatop-vol-bit-shift = <8>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 7130ab8a7518..596763c2fe33 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -592,8 +592,8 @@ anatop: anatop@20c8000 { regulator-1p1 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1375000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; regulator-always-on; anatop-reg-offset = <0x110>; anatop-vol-bit-shift = <8>; @@ -622,8 +622,8 @@ regulator-3p0 { regulator-2p5 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2875000>; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <2750000>; regulator-always-on; anatop-reg-offset = <0x130>; anatop-vol-bit-shift = <8>; From b97872d4eb226fa853d0f69c72b24a711e388757 Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Fri, 25 May 2018 16:02:01 +0530 Subject: [PATCH 45/96] ARM: dts: imx: Add missing OPP properties for CPUs The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing properties (like clocks, supply, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl.dtsi | 23 ++++++++ arch/arm/boot/dts/imx6q-cm-fx6.dts | 66 +++++++++++++++++++++++ arch/arm/boot/dts/imx6q.dtsi | 87 ++++++++++++++++++++++++++++-- arch/arm/boot/dts/imx7d.dtsi | 5 ++ 4 files changed, 178 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index a1acd4ddcb1a..f0607eb41df4 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -51,6 +51,29 @@ cpu@1 { device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index 65ef4cacbc71..18ae4f3be6e3 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -187,6 +187,72 @@ &cpu0 { >; }; +&cpu1 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&cpu2 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + +&cpu3 { + /* + * Although the imx6q fuse indicates that 1.2GHz operation is possible, + * the module behaves unstable at this frequency. Hence, remove the + * 1.2GHz operation point here. + */ + operating-points = < + /* kHz uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; +}; + &ecspi1 { cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 894401c5db09..bbe65616e16a 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -51,25 +51,106 @@ cpu0: cpu@0 { soc-supply = <®_soc>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 7cbc2ffa4b3a..9a772fc9e3b8 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -18,6 +18,11 @@ cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + operating-points = < + /* KHz uV */ + 996000 1075000 + 792000 975000 + >; clock-frequency = <996000000>; operating-points-v2 = <&cpu0_opp_table>; }; From 82210bfd942b891c502afe471cda16eccf565ed5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 3 Jul 2018 10:05:54 -0300 Subject: [PATCH 46/96] ARM: dts: imx51: Fix USB PHY duplicate unit-address Currently the following DTC warnings are seen with W=1: arch/arm/boot/dts/imx51-babbage.dtb: Warning (unique_unit_address): /usbphy/usbphy@0: duplicate unit-address (also used in node /usbphy/usbh1phy@0) arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dtb: Warning (unique_unit_address): /usbphy/usbphy@0: duplicate unit-address (also used in node /usbphy/usbh1phy@0) Fix it by moving the USB PHY nodes outside of simple-bus and drop the unneeded unit-address, which matches the bindings documentation at Documentation/devicetree/bindings/usb/usb-nop-xceiv.txt While at it rename the USB PHY node to usbphy1 for consistency. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 27 +++++++------------ .../dts/imx51-eukrea-mbimxsd51-baseboard.dts | 21 +++++---------- arch/arm/boot/dts/imx51.dtsi | 17 ++++-------- 3 files changed, 22 insertions(+), 43 deletions(-) diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index 4fb0d4d480a8..a4a6d4a6b55b 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -170,22 +170,15 @@ sound { mux-ext-port = <3>; }; - usbphy { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - usbh1phy: usbh1phy@0 { - compatible = "usb-nop-xceiv"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1reg>; - reg = <0>; - clocks = <&clk_usb>; - clock-names = "main_clk"; - reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - vcc-supply = <&vusb_reg>; - #phy-cells = <0>; - }; + usbphy1: usbphy1 { + compatible = "usb-nop-xceiv"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1reg>; + clocks = <&clk_usb>; + clock-names = "main_clk"; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + vcc-supply = <&vusb_reg>; + #phy-cells = <0>; }; }; @@ -431,7 +424,7 @@ &usbh1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh1>; vbus-supply = <®_hub_reset>; - fsl,usbphy = <&usbh1phy>; + fsl,usbphy = <&usbphy1>; phy_type = "ulpi"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts index b3d952f37cdc..e9e819f2b0b7 100644 --- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts +++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts @@ -83,19 +83,12 @@ sound { fsl,mux-ext-port = <3>; }; - usbphy { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - usbh1phy: usbh1phy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - clocks = <&clks IMX5_CLK_USB_PHY_GATE>; - clock-names = "main_clk"; - clock-frequency = <19200000>; - #phy-cells = <0>; - }; + usbphy1: usbphy1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY_GATE>; + clock-names = "main_clk"; + clock-frequency = <19200000>; + #phy-cells = <0>; }; }; @@ -275,7 +268,7 @@ &uart3 { &usbh1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh1>; - fsl,usbphy = <&usbh1phy>; + fsl,usbphy = <&usbphy1>; dr_mode = "host"; phy_type = "ulpi"; status = "okay"; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 5bb727a5b6a3..66e4187022be 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -93,18 +93,11 @@ cpu: cpu@0 { }; }; - usbphy { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - usbphy0: usbphy@0 { - compatible = "usb-nop-xceiv"; - reg = <0>; - clocks = <&clks IMX5_CLK_USB_PHY_GATE>; - clock-names = "main_clk"; - #phy-cells = <0>; - }; + usbphy0: usbphy0 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; }; display-subsystem { From 465b3d77b1f8c88d3d28f9da6e4cdd75ce66b6b3 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 5 Jul 2018 22:05:49 +0300 Subject: [PATCH 47/96] ARM: dts: imx31: add device tree description of basic controllers The change adds a number of basic peripherals found on i.MX31 SoC: * GPIO controllers, * I2C master controllers, * SPI master controllers, * ATA controller, * SDHC controllers, * RTC, watchdog and PWM contollers, * SDMA, * IRAM, * NAND and WEIM controllers on EMI. The added controller devices were tested on Freescale i.MX31 powered LogicPD Lite SoM and baseboard. DMA functionality was tested on SDHC and SPI controllers so far, thus dmas properties are added to those device nodes only. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx31.dtsi | 223 +++++++++++++++++++++++++++++++++++ 1 file changed, 223 insertions(+) diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 4642c8169a65..ca1419ca303c 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ // +// Copyright 2016-2018 Vladimir Zapolskiy // Copyright 2012 Denis 'GNUtoo' Carikli / { @@ -15,11 +16,20 @@ / { memory { device_type = "memory"; }; aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; + spi0 = &spi1; + spi1 = &spi2; + spi2 = &spi3; }; cpus { @@ -47,6 +57,14 @@ soc { interrupt-parent = <&avic>; ranges; + iram: iram@1fffc000 { + compatible = "mmio-sram"; + reg = <0x1fffc000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1fffc000 0x4000>; + }; + aips@43f00000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -54,6 +72,34 @@ aips@43f00000 { /* AIPS1 */ reg = <0x43f00000 0x100000>; ranges; + i2c1: i2c@43f80000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f80000 0x4000>; + interrupts = <10>; + clocks = <&clks 33>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@43f84000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f84000 0x4000>; + interrupts = <3>; + clocks = <&clks 35>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ata: ata@43f8c000 { + compatible = "fsl,imx31-pata", "fsl,imx27-pata"; + reg = <0x43f8c000 0x4000>; + interrupts = <15>; + clocks = <&clks 26>; + status = "disabled"; + }; + uart1: serial@43f90000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43f90000 0x4000>; @@ -72,6 +118,29 @@ uart2: serial@43f94000 { status = "disabled"; }; + i2c2: i2c@43f98000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f98000 0x4000>; + interrupts = <4>; + clocks = <&clks 34>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@43fa4000 { + compatible = "fsl,imx31-cspi"; + reg = <0x43fa4000 0x4000>; + interrupts = <14>; + clocks = <&clks 10>, <&clks 53>; + clock-names = "ipg", "per"; + dmas = <&sdma 8 8 0>, <&sdma 9 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + kpp: kpp@43fa8000 { compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; reg = <0x43fa8000 0x4000>; @@ -106,6 +175,28 @@ spba@50000000 { reg = <0x50000000 0x100000>; ranges; + sdhci1: sdhci@50004000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50004000 0x4000>; + interrupts = <9>; + clocks = <&clks 10>, <&clks 20>; + clock-names = "ipg", "per"; + dmas = <&sdma 20 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + sdhci2: sdhci@50008000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50008000 0x4000>; + interrupts = <8>; + clocks = <&clks 10>, <&clks 21>; + clock-names = "ipg", "per"; + dmas = <&sdma 21 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + uart3: serial@5000c000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x5000c000 0x4000>; @@ -115,6 +206,19 @@ uart3: serial@5000c000 { status = "disabled"; }; + spi2: cspi@50010000 { + compatible = "fsl,imx31-cspi"; + reg = <0x50010000 0x4000>; + interrupts = <13>; + clocks = <&clks 10>, <&clks 54>; + clock-names = "ipg", "per"; + dmas = <&sdma 6 8 0>, <&sdma 7 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + iim: iim@5001c000 { compatible = "fsl,imx31-iim", "fsl,imx27-iim"; reg = <0x5001c000 0x1000>; @@ -137,6 +241,19 @@ clks: ccm@53f80000{ #clock-cells = <1>; }; + spi3: cspi@53f84000 { + compatible = "fsl,imx31-cspi"; + reg = <0x53f84000 0x4000>; + interrupts = <17>; + clocks = <&clks 10>, <&clks 28>; + clock-names = "ipg", "per"; + dmas = <&sdma 10 8 0>, <&sdma 11 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpt: timer@53f90000 { compatible = "fsl,imx31-gpt"; reg = <0x53f90000 0x4000>; @@ -144,6 +261,112 @@ gpt: timer@53f90000 { clocks = <&clks 10>, <&clks 22>; clock-names = "ipg", "per"; }; + + gpio3: gpio@53fa4000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fa4000 0x4000>; + interrupts = <56>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + rng@53fb0000 { + compatible = "fsl,imx31-rnga"; + reg = <0x53fb0000 0x4000>; + interrupts = <22>; + clocks = <&clks 29>; + }; + + gpio1: gpio@53fcc000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fcc000 0x4000>; + interrupts = <52>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@53fd0000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fd0000 0x4000>; + interrupts = <51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sdma: sdma@53fd4000 { + compatible = "fsl,imx31-sdma"; + reg = <0x53fd4000 0x4000>; + interrupts = <34>; + clocks = <&clks 10>, <&clks 27>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin"; + }; + + rtc: rtc@53fd8000 { + compatible = "fsl,imx31-rtc", "fsl,imx21-rtc"; + reg = <0x53fd8000 0x4000>; + interrupts = <25>; + clocks = <&clks 2>, <&clks 40>; + clock-names = "ref", "ipg"; + }; + + wdog: wdog@53fdc000 { + compatible = "fsl,imx31-wdt", "fsl,imx21-wdt"; + reg = <0x53fdc000 0x4000>; + clocks = <&clks 41>; + }; + + pwm: pwm@53fe0000 { + compatible = "fsl,imx31-pwm", "fsl,imx27-pwm"; + reg = <0x53fe0000 0x4000>; + interrupts = <26>; + clocks = <&clks 10>, <&clks 42>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + }; + + emi@b8000000 { /* External Memory Interface */ + compatible = "simple-bus"; + reg = <0xb8000000 0x5000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + nfc: nand@b8000000 { + compatible = "fsl,imx31-nand", "fsl,imx27-nand"; + reg = <0xb8000000 0x1000>; + interrupts = <33>; + clocks = <&clks 9>; + dmas = <&sdma 30 17 0>; + dma-names = "rx-tx"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + weim: weim@b8002000 { + compatible = "fsl,imx31-weim", "fsl,imx27-weim"; + reg = <0xb8002000 0x1000>; + clocks = <&clks 56>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xa0000000 0x08000000 + 1 0 0xa8000000 0x08000000 + 2 0 0xb0000000 0x02000000 + 3 0 0xb2000000 0x02000000 + 4 0 0xb4000000 0x02000000 + 5 0 0xb6000000 0x02000000>; + status = "disabled"; + }; }; }; }; From caaac8cde914ebab128295240cb489841d224170 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Tue, 3 Jul 2018 22:29:34 +0300 Subject: [PATCH 48/96] ARM: dts: imx31: add LogicPD MX31Lite board description The added DTS contains a combined description of LogicPD MX31 Lite SoM devices, peripherals are routed to ports on a baseboard: * PATA controller, * SD/MMC controller, * 2 GPIO LEDs, * UART controllers, * Freescale MC13783 MFD connected over SPI, * SMSC LAN9117, * ST Micro NAND SLC, 64 MiB, * Intel NOR flash, 16 MiB. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx31-lite.dts | 177 +++++++++++++++++++++++++++++++ 2 files changed, 179 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx31-lite.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bc63b4c81dfe..fd2f82b09df2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -345,7 +345,8 @@ dtb-$(CONFIG_SOC_IMX27) += \ imx27-phytec-phycore-rdk.dtb \ imx27-phytec-phycard-s-rdk.dtb dtb-$(CONFIG_SOC_IMX31) += \ - imx31-bug.dtb + imx31-bug.dtb \ + imx31-lite.dtb dtb-$(CONFIG_SOC_IMX35) += \ imx35-eukrea-mbimxsd35-baseboard.dtb \ imx35-pdk.dtb diff --git a/arch/arm/boot/dts/imx31-lite.dts b/arch/arm/boot/dts/imx31-lite.dts new file mode 100644 index 000000000000..db52ddccabc3 --- /dev/null +++ b/arch/arm/boot/dts/imx31-lite.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2016-2018 Vladimir Zapolskiy + +/dts-v1/; + +#include "imx31.dtsi" + +#include +#include + +/ { + model = "LogicPD i.MX31 Lite"; + compatible = "logicpd,imx31-lite", "fsl,imx31"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + reg = <0x80000000 0x8000000>; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + led1 { + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ata { + status = "okay"; +}; + +&nfc { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&sdhci1 { + bus-width = <4>; + cd-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13783"; + reg = <0>; + spi-cs-high; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + + fsl,mc13xxx-uses-adc; + fsl,mc13xxx-uses-rtc; + + regulators { + sw1a { /* QVCC */ + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + sw1b { /* QVCC */ + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + sw2a { /* 1.8V_DDR, NVCC2, NVCC21 and NVCC22 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + sw2b { /* NVCC10 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + violo { /* NVCC1 and NVCC7 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + viohi { /* VIOHI */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vaudio { /* VAUDIO */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vcam { /* NVCC4 */ + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vgen { /* NVCC5 / NVCC8 and NVCC6 / NVCC9 */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc2 { /* NVCC3 */ + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&uart1 { + uart-has-rtscts; + status = "okay"; +}; + +/* Routed to the extension board */ +&uart2 { + uart-has-rtscts; + status = "okay"; +}; + +/* Routed to the extension board */ +&uart3 { + uart-has-rtscts; + status = "okay"; +}; + +&weim { + status = "okay"; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0x0 0x200000>; + bank-width = <2>; + linux,mtd-name = "physmap-flash.0"; + fsl,weim-cs-timing = <0x0000cf03 0xa0330d01 0x00220800>; + }; + + ethernet@4,0 { + compatible = "smsc,lan9117", "smsc,lan9115"; + reg = <4 0x0 0x100>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + phy-mode = "mii"; + reg-io-width = <2>; + smsc,irq-push-pull; + fsl,weim-cs-timing = <0x00008701 0x04000541 0x00010000>; + }; +}; From 2db286d7361ecde6cb336cc8f10582afa9c09374 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 4 Jul 2018 14:52:50 -0300 Subject: [PATCH 49/96] ARM: dts: imx: Remove optional 'fsl,sec-era' property Since commit 654f2b937b38 ("crypto: caam - allow retrieving 'era' from register") the CAAM driver is capable of obtaining the era version by reading the appropriate CAAM registers, so let the CAAM driver discover the era version in run-time instead of hardcoding such information in the device tree. According to Documentation/devicetree/bindings/crypto/fsl-sec4.txt the 'fsl,sec-era' is an optional property and this can be safely removed now. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 1 - arch/arm/boot/dts/imx6sx.dtsi | 1 - arch/arm/boot/dts/imx7s.dtsi | 1 - 3 files changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 911141e24681..61d2d26afbf4 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -922,7 +922,6 @@ aips-bus@2100000 { /* AIPS2 */ crypto: caam@2100000 { compatible = "fsl,sec-v4.0"; - fsl,sec-era = <4>; #address-cells = <1>; #size-cells = <1>; reg = <0x2100000 0x10000>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 596763c2fe33..881c0dd8d09a 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -815,7 +815,6 @@ aips2: aips-bus@2100000 { crypto: caam@2100000 { compatible = "fsl,sec-v4.0"; - fsl,sec-era = <4>; #address-cells = <1>; #size-cells = <1>; reg = <0x2100000 0x10000>; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 9ced589bfa96..a052198f6e96 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -842,7 +842,6 @@ sai3: sai@308c0000 { crypto: caam@30900000 { compatible = "fsl,sec-v4.0"; - fsl,sec-era = <8>; #address-cells = <1>; #size-cells = <1>; reg = <0x30900000 0x40000>; From b31cd4377286904d8dd7f45b0846c1dfe79ceb04 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Fri, 6 Jul 2018 19:49:02 -0700 Subject: [PATCH 50/96] ARM: dts: imx: Add ZII SCU2 Mezz board Add support for the Zodiac Inflight Innovations SCU2 Mezz board (i.MX51-based). Cc: Fabio Estevam Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Fabio Estevam Signed-off-by: Andrey Gusakov Signed-off-by: Andrey Smirnov Tested-by: Chris Healy Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx51-zii-scu2-mezz.dts | 448 ++++++++++++++++++++++ 2 files changed, 450 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx51-zii-scu2-mezz.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index fd2f82b09df2..b000f917f336 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -359,7 +359,8 @@ dtb-$(CONFIG_SOC_IMX51) += \ imx51-digi-connectcore-jsk.dtb \ imx51-eukrea-mbimxsd51-baseboard.dtb \ imx51-ts4800.dtb \ - imx51-zii-rdu1.dtb + imx51-zii-rdu1.dtb \ + imx51-zii-scu2-mezz.dtb dtb-$(CONFIG_SOC_IMX53) += \ imx53-ard.dtb \ imx53-cx9020.dtb \ diff --git a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts new file mode 100644 index 000000000000..26cf08549df4 --- /dev/null +++ b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts @@ -0,0 +1,448 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +/dts-v1/; + +#include "imx51.dtsi" + +/ { + model = "ZII SCU2 Mezz Board"; + compatible = "zii,imx51-scu2-mezz", "fsl,imx51"; + + chosen { + stdout-path = &uart1; + }; + + /* Will be filled by the bootloader */ + memory@90000000 { + reg = <0x90000000 0>; + }; + + aliases { + mdio-gpio0 = &mdio_gpio; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_mmc_reset>; + gpio = <&gpio3 13 GPIO_ACTIVE_LOW>; + startup-delay-us = <150000>; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + mdio_gpio: mdio-gpio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_swmdio>; + gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>, /* mdc */ + <&gpio2 6 GPIO_ACTIVE_HIGH>; /* mdio */ + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "marvell,mv88e6085"; + reg = <0>; + dsa,member = <0 0>; + eeprom-length = <512>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "port4"; + }; + + port@1 { + reg = <1>; + label = "port5"; + }; + + port@2 { + reg = <2>; + label = "port6"; + }; + + port@3 { + reg = <3>; + label = "port7"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&fec>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@5 { + reg = <5>; + label = "mezz2esb"; + phy-mode = "sgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&cpu { + cpu-supply = <&sw1_reg>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, + <&gpio4 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13892"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + spi-max-frequency = <6000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-adc; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vusb_reg: vusb { + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + }; + + leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0x0 0x0 0x3f83f8 0x0>; + + sysled3: led3@3 { + reg = <3>; + label = "system:red:power"; + linux,default-trigger = "default-on"; + }; + + sysled4: led4@4 { + reg = <4>; + label = "system:green:act"; + linux,default-trigger = "heartbeat"; + }; + }; + }; + + flash@1 { + compatible = "atmel,at45", "atmel,dataflash"; + reg = <1>; + spi-max-frequency = <25000000>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <8>; + non-removable; + no-1-8-v; + no-sdio; + no-sd; + status = "okay"; +}; + +&esdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc4>; + bus-width = <4>; + no-1-8-v; + no-sdio; + cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + status = "okay"; + phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + phy-supply = <&vgen3_reg>; + phy-handle = <ðphy>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + reg = <0>; + max-speed = <100>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-mezz"; + current-speed = <57600>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog-legacy"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&usbotg { + dr_mode = "host"; + disable-over-current; + phy_type = "utmi_wide"; + vbus-supply = <&usb_vbus>; + status = "okay"; +}; + +&usbphy0 { + vcc-supply = <&vusb2_reg>; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 + MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 + MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 + MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 + MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 + >; + }; + + pinctrl_esdhc4: esdhc4grp { + fsl,pins = < + MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 + MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 + MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 + MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 + MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 + MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 + MX51_PAD_NANDF_D0__GPIO4_8 0x100 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 + MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 + MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x20a4 + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 + MX51_PAD_DI_GP3__FEC_TX_ER 0x2004 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 + MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 + MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 + MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 + MX51_PAD_EIM_A20__GPIO2_14 0x0085 + MX51_PAD_EIM_A21__GPIO2_15 0x00e5 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX51_PAD_GPIO1_4__GPIO1_4 0x85 + MX51_PAD_GPIO1_8__GPIO1_8 0xe5 + >; + }; + + pinctrl_swmdio: swmdiogrp { + fsl,pins = < + MX51_PAD_EIM_D22__GPIO2_6 0x100 + MX51_PAD_EIM_D23__GPIO2_7 0x100 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + + pinctrl_usb_mmc_reset: usbmmcgrp { + fsl,pins = < + MX51_PAD_CSI1_D9__GPIO3_13 0x85 + >; + }; +}; From 6c74366b8db6fc70b65266bf52c58a89ebc946f1 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:41 +0200 Subject: [PATCH 51/96] ARM: dts: imx6q-apalis: add chosen node Add Apalis UART1 as default serial console. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-apalis-eval.dts | 4 ++++ arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 4 ++++ arch/arm/boot/dts/imx6q-apalis-ixora.dts | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts index aa0e631f3c0a..621d9709effa 100644 --- a/arch/arm/boot/dts/imx6q-apalis-eval.dts +++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts @@ -62,6 +62,10 @@ aliases { rtc1 = &snvs_rtc; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts index e8dccf552122..4e1c8feaef82 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts @@ -63,6 +63,10 @@ aliases { rtc1 = &snvs_rtc; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index 6831dfd24cc1..469e3d0e2827 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -62,6 +62,10 @@ aliases { rtc1 = &snvs_rtc; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; From 5780acda81d3f5378b71d8dead95b8d052dc22ae Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:42 +0200 Subject: [PATCH 52/96] ARM: dts: imx6q-apalis-eval: add carrier board 3.3V supply Add the 3.3V main supply on the carrier board. Currently as a fixed supply since not all consumer are modeled yet. This gets also rid of some missing supply warnings. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-apalis-eval.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts index 621d9709effa..707ac9a46115 100644 --- a/arch/arm/boot/dts/imx6q-apalis-eval.dts +++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts @@ -113,6 +113,7 @@ panel: panel { */ compatible = "edt,et057090dhu"; backlight = <&backlight>; + power-supply = <®_3v3_sw>; port { lcd_panel_in: endpoint { @@ -131,19 +132,30 @@ reg_pcie_switch: regulator-pcie-switch { enable-active-high; status = "okay"; }; + + reg_3v3_sw: regulator-3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; &backlight { brightness-levels = <0 127 191 223 239 247 251 255>; default-brightness-level = <1>; + power-supply = <®_3v3_sw>; status = "okay"; }; &can1 { + xceiver-supply = <®_3v3_sw>; status = "okay"; }; &can2 { + xceiver-supply = <®_3v3_sw>; status = "okay"; }; From 3b1147a952cf9efb36144c1f7fd847d5a99adb7a Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:43 +0200 Subject: [PATCH 53/96] ARM: dts: imx6qdl-apalis/-colibri: prevent 1.8V modes Use no-1-8-v device tree property to indicate that the board does not support 1.8V signaling. The property voltage-ranges seems not appropriate in our case since we do not have level shifters in place. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 6 +++--- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 64fbee61de44..55bcea245df6 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -457,7 +457,7 @@ &usdhc1 { pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>; vqmmc-supply = <®_3p3v>; bus-width = <8>; - voltage-ranges = <3300 3300>; + no-1-8-v; status = "disabled"; }; @@ -467,7 +467,7 @@ &usdhc2 { pinctrl-0 = <&pinctrl_usdhc2>; vqmmc-supply = <®_3p3v>; bus-width = <4>; - voltage-ranges = <3300 3300>; + no-1-8-v; status = "disabled"; }; @@ -477,7 +477,7 @@ &usdhc3 { pinctrl-0 = <&pinctrl_usdhc3>; vqmmc-supply = <®_3p3v>; bus-width = <8>; - voltage-ranges = <3300 3300>; + no-1-8-v; non-removable; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 6e937ca20869..bb44829dacbe 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -389,7 +389,7 @@ &usdhc1 { cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ vqmmc-supply = <®_3p3v>; bus-width = <4>; - voltage-ranges = <3300 3300>; + no-1-8-v; status = "disabled"; }; @@ -399,7 +399,7 @@ &usdhc3 { pinctrl-0 = <&pinctrl_usdhc3>; vqmmc-supply = <®_3p3v>; bus-width = <8>; - voltage-ranges = <3300 3300>; + no-1-8-v; non-removable; status = "okay"; }; From 147299a8fc3a70f02984a6d6a042d0cbf53c46f9 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:44 +0200 Subject: [PATCH 54/96] ARM: dts: imx6qdl-apalis/-colibri: disable read-only switch Use the disable-wp to indicate that Apalis and Colibri iMX6 do not make use of the native write-protect signal available on the i.MX 6 SoCs. This prevents warnings: mmc0: host does not support reading read-only switch, assuming write-enable Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 2 ++ arch/arm/boot/dts/imx6qdl-colibri.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 55bcea245df6..f9bacc9ff2b6 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -457,6 +457,7 @@ &usdhc1 { pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>; vqmmc-supply = <®_3p3v>; bus-width = <8>; + disable-wp; no-1-8-v; status = "disabled"; }; @@ -467,6 +468,7 @@ &usdhc2 { pinctrl-0 = <&pinctrl_usdhc2>; vqmmc-supply = <®_3p3v>; bus-width = <4>; + disable-wp; no-1-8-v; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index bb44829dacbe..8ae17fdf6cf6 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -387,6 +387,7 @@ &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ + disable-wp; vqmmc-supply = <®_3p3v>; bus-width = <4>; no-1-8-v; From 7034de41186f3b49fe987b4626ae1a151760a609 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:45 +0200 Subject: [PATCH 55/96] ARM: dts: imx6qdl-apalis/-colibri: remove 1.8V regulator The fixed 1.8V regulator is not used, and there is in fact no fixed 1.8V regulator on the module. Remove it. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 8 -------- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 8 -------- 2 files changed, 16 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index f9bacc9ff2b6..2f711fffa06e 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -61,14 +61,6 @@ backlight: backlight { status = "disabled"; }; - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - reg_2p5v: regulator-2p5v { compatible = "regulator-fixed"; regulator-name = "2P5V"; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 8ae17fdf6cf6..1a147cb0bed0 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -56,14 +56,6 @@ backlight: backlight { status = "disabled"; }; - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - reg_2p5v: regulator-2p5v { compatible = "regulator-fixed"; regulator-name = "2P5V"; From 7060066d3e9920a4d96e106243e544c14ba0fd79 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:46 +0200 Subject: [PATCH 56/96] ARM: dts: imx6qdl-apalis/-colibri: fix on-module regulators Remove the 2.5V regulator, it does not exist. There is 3.3V and 3.3V_AUDIO provided to the module through the edge connector, model those as fixed regulators like we use to do in other Colibri device trees. The SGTL5000 uses 3.3V_AUDIO as VDDA. Note that the driver derives the analog ground voltage (VAG) from this supply. The new value should allow higher output swings before clipping occurs. Refer to the SGTL5000 datasheet for details. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 22 +++++++++++----------- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 20 ++++++++++---------- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 2f711fffa06e..6813f4326807 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -61,17 +61,17 @@ backlight: backlight { status = "disabled"; }; - reg_2p5v: regulator-2p5v { + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_3p3v: regulator-3p3v { + reg_module_3v3_audio: regulator-module-3v3-audio { compatible = "regulator-fixed"; - regulator-name = "3P3V"; + regulator-name = "+V3.3_AUDIO"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -314,8 +314,8 @@ codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; + VDDA-supply = <®_module_3v3_audio>; + VDDIO-supply = <®_module_3v3>; }; /* STMPE811 touch screen controller */ @@ -447,7 +447,7 @@ &usbotg { &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <8>; disable-wp; no-1-8-v; @@ -458,7 +458,7 @@ &usdhc1 { &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <4>; disable-wp; no-1-8-v; @@ -469,7 +469,7 @@ &usdhc2 { &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <8>; no-1-8-v; non-removable; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 1a147cb0bed0..9a3bac5be5e2 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -56,17 +56,17 @@ backlight: backlight { status = "disabled"; }; - reg_2p5v: regulator-2p5v { + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_3p3v: regulator-3p3v { + reg_module_3v3_audio: regulator-module-3v3-audio { compatible = "regulator-fixed"; - regulator-name = "3P3V"; + regulator-name = "+V3.3_AUDIO"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; @@ -244,8 +244,8 @@ codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; + VDDA-supply = <®_module_3v3_audio>; + VDDIO-supply = <®_module_3v3>; lrclk-strength = <3>; }; @@ -380,7 +380,7 @@ &usdhc1 { pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ disable-wp; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <4>; no-1-8-v; status = "disabled"; @@ -390,7 +390,7 @@ &usdhc1 { &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <8>; no-1-8-v; non-removable; From 330f85598e87497974431c0f6f736e413ccf2d27 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:47 +0200 Subject: [PATCH 57/96] ARM: dts: imx6qdl-apalis/-colibri: assign VDDD to SGTL5000 VDDD is connected to VGEN4 of the PF0100. This rail should only run at 1.8V since there are multiple consumer and they all expect the rail to be at 1.8V. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 3 ++- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 6813f4326807..8c04f42fdb71 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -289,7 +289,7 @@ vgen3_reg: vgen3 { vgen4_reg: vgen4 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; @@ -316,6 +316,7 @@ codec: sgtl5000@a { clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_module_3v3_audio>; VDDIO-supply = <®_module_3v3>; + VDDD-supply = <&vgen4_reg>; }; /* STMPE811 touch screen controller */ diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 9a3bac5be5e2..6821ea511051 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -219,7 +219,7 @@ vgen2_reg: vgen2 { vgen4_reg: vgen4 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; @@ -246,6 +246,7 @@ codec: sgtl5000@a { clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_module_3v3_audio>; VDDIO-supply = <®_module_3v3>; + VDDD-supply = <&vgen4_reg>; lrclk-strength = <3>; }; From b074f057ac60d32f604e0ca3120064e688e9a622 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 9 Jul 2018 17:48:48 +0200 Subject: [PATCH 58/96] ARM: dts: imx6qdl-apalis/-colibri: remove unused pinctrl groups 100/200MHz states for USDHC3 are not required since the SoC does not support modes faster than DDR52 for the on board eMMC. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 34 -------------------------- arch/arm/boot/dts/imx6qdl-colibri.dtsi | 34 -------------------------- 2 files changed, 68 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 8c04f42fdb71..05f07ea3e8c8 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -947,38 +947,4 @@ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 >; }; - - pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3200mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 6821ea511051..87e15e7cb32b 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -692,40 +692,6 @@ MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 >; }; - pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3200mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9 - >; - }; - pinctrl_weim_cs0: weimcs0grp { fsl,pins = < /* nEXT_CS0 */ From ba4446d4faeb8e60a78915c4f19645beb5f7e6ad Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 11 Jul 2018 08:58:59 +0800 Subject: [PATCH 59/96] ARM: dts: imx6sx: add ocram_s support i.MX6SX has a 16KB always-on ocram bank called ocram_s, enable it as another mmio sram. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 881c0dd8d09a..ae10225e8061 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -166,6 +166,12 @@ soc { interrupt-parent = <&gpc>; ranges; + ocram_s: sram@8f8000 { + compatible = "mmio-sram"; + reg = <0x008f8000 0x4000>; + clocks = <&clks IMX6SX_CLK_OCRAM_S>; + }; + ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; From 13211eec7b0e1b7b341b482811f69333c940f64c Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Wed, 11 Jul 2018 15:11:17 +0300 Subject: [PATCH 60/96] ARM: dts: imx6sl: Convert gpc to new bindings With old bindings imx_gpc_onecell_data always sets num_domains to 2 so the DISPMIX domain can't actually be referenced. The pd is still defined and pm core shuts it down as "unused" so display can't work. Fix this by converting to new gpc bindings by adding pgc nodes and referencing the newly-defined &pu_disp domain from &lcdif. Signed-off-by: Leonard Crestez Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index c64bd906ad55..a6b5ca48298f 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -681,10 +681,36 @@ gpc: gpc@20dc000 { #interrupt-cells = <3>; interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - pu-supply = <®_pu>; - clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, - <&clks IMX6SL_CLK_GPU2D_PODF>; - #power-domain-cells = <1>; + clocks = <&clks IMX6SL_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + + pd_pu: power-domain@1 { + reg = <1>; + #power-domain-cells = <0>; + power-supply = <®_pu>; + clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, + <&clks IMX6SL_CLK_GPU2D_PODF>; + }; + + pd_disp: power-domain@2 { + reg = <2>; + #power-domain-cells = <0>; + clocks = <&clks IMX6SL_CLK_LCDIF_AXI>, + <&clks IMX6SL_CLK_LCDIF_PIX>, + <&clks IMX6SL_CLK_EPDC_AXI>, + <&clks IMX6SL_CLK_EPDC_PIX>, + <&clks IMX6SL_CLK_PXP_AXI>; + }; + }; }; gpr: iomuxc-gpr@20e0000 { @@ -739,6 +765,7 @@ lcdif: lcdif@20f8000 { <&clks IMX6SL_CLK_DUMMY>; clock-names = "pix", "axi", "disp_axi"; status = "disabled"; + power-domains = <&pd_disp>; }; dcp: dcp@20fc000 { From 996b1b611e2f604b542e60596e614ee340820eb7 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Tue, 10 Jul 2018 22:07:04 -0700 Subject: [PATCH 61/96] ARM: dts: imx: Add ZII SCU3 ESB Add support for the Zodiac Inflight Innovations i.MX51-base SCU3 Ethernet Switch Board (ESB) Cc: Fabio Estevam Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Fabio Estevam Signed-off-by: Andrey Gusakov Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 459 +++++++++++++++++++++++ 2 files changed, 461 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx51-zii-scu3-esb.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b000f917f336..46d9edca187b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -360,7 +360,8 @@ dtb-$(CONFIG_SOC_IMX51) += \ imx51-eukrea-mbimxsd51-baseboard.dtb \ imx51-ts4800.dtb \ imx51-zii-rdu1.dtb \ - imx51-zii-scu2-mezz.dtb + imx51-zii-scu2-mezz.dtb \ + imx51-zii-scu3-esb.dtb dtb-$(CONFIG_SOC_IMX53) += \ imx53-ard.dtb \ imx53-cx9020.dtb \ diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts new file mode 100644 index 000000000000..07bc5fc05076 --- /dev/null +++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +/dts-v1/; + +#include "imx51.dtsi" + +/ { + model = "ZII SCU3 ESB board"; + compatible = "zii,imx51-scu3-esb", "fsl,imx51"; + + chosen { + stdout-path = &uart1; + }; + + /* Will be filled by the bootloader */ + memory@90000000 { + reg = <0x90000000 0>; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_mmc_reset>; + gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; + startup-delay-us = <150000>; + }; +}; + +&cpu { + cpu-supply = <&sw1_reg>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, + <&gpio4 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13892"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + spi-max-frequency = <6000000>; + spi-cs-high; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-adc; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + vpll_reg: vpll { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdig_reg: vdig { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + }; + + vsd_reg: vsd { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3150000>; + }; + + vusb_reg: vusb { + regulator-always-on; + }; + + vusb2_reg: vusb2 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2775000>; + regulator-boot-on; + regulator-always-on; + }; + + vvideo_reg: vvideo { + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vaudio_reg: vaudio { + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <3000000>; + }; + + vcam_reg: vcam { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; + }; + + leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0x0 0x0 0x3f83f8 0x0>; + + sysled3: led3@3 { + reg = <3>; + label = "system:red:power"; + linux,default-trigger = "default-on"; + }; + + sysled4: led4@4 { + reg = <4>; + label = "system:green:act"; + linux,default-trigger = "heartbeat"; + }; + }; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <25000000>; + reg = <1>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <8>; + non-removable; + no-1-8-v; + no-sdio; + no-sd; + status = "okay"; +}; + +&esdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc4>; + bus-width = <4>; + no-1-8-v; + no-sdio; + cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "mii"; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + fec_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch@0 { + compatible = "marvell,mv88e6085"; + reg = <0>; + dsa,member = <0 0>; + eeprom-length = <512>; + interrupt-parent = <&gpio4>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "port1"; + }; + + port@1 { + reg = <1>; + label = "port2"; + }; + + port@2 { + reg = <2>; + label = "port3"; + }; + + port@3 { + reg = <3>; + label = "scu2scu"; + }; + + port@4 { + reg = <4>; + label = "esb2host"; + }; + + port@5 { + reg = <5>; + label = "esb2mezz"; + phy-mode = "sgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + label = "cpu"; + phy-mode = "mii"; + ethernet = <&fec>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&ipu { + status = "disabled"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x50>; + }; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-esb"; + current-speed = <57600>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchodg-legacy"; + }; + + eeprom@a4 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa4 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&usbotg { + dr_mode = "host"; + disable-over-current; + phy_type = "utmi_wide"; + vbus-supply = <&usb_vbus>; + status = "okay"; +}; + +&usbphy0 { + vcc-supply = <&vusb2_reg>; +}; + +&wdog1 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185 + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185 + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185 + MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 + MX51_PAD_CSPI1_SS1__GPIO4_25 0x85 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 + MX51_PAD_SD1_CLK__SD1_CLK 0x20d5 + MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5 + MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5 + MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5 + MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5 + MX51_PAD_SD2_DATA0__SD1_DAT4 0x20d5 + MX51_PAD_SD2_DATA1__SD1_DAT5 0x20d5 + MX51_PAD_SD2_DATA2__SD1_DAT6 0x20d5 + MX51_PAD_SD2_DATA3__SD1_DAT7 0x20d5 + >; + }; + + pinctrl_esdhc4: esdhc4grp { + fsl,pins = < + MX51_PAD_NANDF_RB1__SD4_CMD 0x400020d5 + MX51_PAD_NANDF_CS2__SD4_CLK 0x20d5 + MX51_PAD_NANDF_CS3__SD4_DAT0 0x20d5 + MX51_PAD_NANDF_CS4__SD4_DAT1 0x20d5 + MX51_PAD_NANDF_CS5__SD4_DAT2 0x20d5 + MX51_PAD_NANDF_CS6__SD4_DAT3 0x20d5 + MX51_PAD_NANDF_D0__GPIO4_8 0x100 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x2004 + MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x2004 + MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x2004 + MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x2004 + MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x2004 + MX51_PAD_DISP2_DAT10__FEC_COL 0x0180 + MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x0180 + MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x20a4 + + MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x2180 + MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x2180 + MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x0085 + MX51_PAD_DI_GP4__FEC_RDATA2 0x0085 + MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x0085 + MX51_PAD_DI2_PIN2__FEC_MDC 0x2004 + MX51_PAD_DI2_PIN3__FEC_MDIO 0x01f5 + MX51_PAD_DI2_PIN4__FEC_CRS 0x0180 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed + MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX51_PAD_GPIO1_4__GPIO1_4 0x85 + MX51_PAD_GPIO1_8__GPIO1_8 0xe5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 + MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 + MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 + MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX51_PAD_UART2_RXD__UART2_RXD 0x1c5 + MX51_PAD_UART2_TXD__UART2_TXD 0x1c5 + MX51_PAD_USBH1_DATA0__UART2_CTS 0x1c5 + MX51_PAD_USBH1_DATA3__UART2_RTS 0x1c5 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 + MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 + >; + }; + + pinctrl_usb_mmc_reset: usbmmcgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_RXD__GPIO4_19 0x100 + >; + }; +}; From ad780dd3655b500c51e6de36448568e3456f4226 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 9 Jul 2018 15:19:13 -0300 Subject: [PATCH 62/96] dt-bindings: freescale: Add bindings for the M4IF module Add bindings for the M4IF module present on i.MX51. Signed-off-by: Fabio Estevam Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/freescale/m4if.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/freescale/m4if.txt diff --git a/Documentation/devicetree/bindings/arm/freescale/m4if.txt b/Documentation/devicetree/bindings/arm/freescale/m4if.txt new file mode 100644 index 000000000000..93bd7b867a53 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/m4if.txt @@ -0,0 +1,12 @@ +* Freescale Multi Master Multi Memory Interface (M4IF) module + +Required properties: +- compatible : Should be "fsl,imx51-m4if" +- reg : Address and length of the register set for the device + +Example: + +m4if: m4if@83fd8000 { + compatible = "fsl,imx51-m4if"; + reg = <0x83fd8000 0x1000>; +}; From b6b93a3fe7ed12f0b80800be5df798c19adcc4ee Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 9 Jul 2018 15:19:14 -0300 Subject: [PATCH 63/96] ARM: dts: imx51: Add M4IF support As per the i.MX51 Reference Manual the M4IF register region starts at 0x83fd8000 and has a 4kB address range. Add support for it. Signed-off-by: Fabio Estevam Tested-by: Sergey Lapin Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 66e4187022be..b417c39f3772 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -531,6 +531,11 @@ audmux: audmux@83fd0000 { status = "disabled"; }; + m4if: m4if@83fd8000 { + compatible = "fsl,imx51-m4if"; + reg = <0x83fd8000 0x1000>; + }; + weim: weim@83fda000 { #address-cells = <2>; #size-cells = <1>; From 168a7bb7f126c7a057dd77f6f7c93459ed780fa9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 10 Jul 2018 13:31:43 -0300 Subject: [PATCH 64/96] dt-bindings: freescale: Add bindings for the tigerp module Add bindings for the tigerp module present on i.MX51. Signed-off-by: Fabio Estevam Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/freescale/tigerp.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/freescale/tigerp.txt diff --git a/Documentation/devicetree/bindings/arm/freescale/tigerp.txt b/Documentation/devicetree/bindings/arm/freescale/tigerp.txt new file mode 100644 index 000000000000..19e2aad63d6e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/tigerp.txt @@ -0,0 +1,12 @@ +* Freescale Tigerp platform module + +Required properties: +- compatible : Should be "fsl,imx51-tigerp" +- reg : Address and length of the register set for the device + +Example: + +tigerp: tigerp@83fa0000 { + compatible = "fsl,imx51-tigerp"; + reg = <0x83fa0000 0x28>; +}; From 4b301223d0574e6c390a174183d5ffa17cd6a12c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 10 Jul 2018 13:31:44 -0300 Subject: [PATCH 65/96] ARM: dts: imx51: Add PMU support Add PMU support in the device tree. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index b417c39f3772..0205db56d913 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -93,6 +93,12 @@ cpu: cpu@0 { }; }; + pmu: pmu { + compatible = "arm,cortex-a8-pmu"; + interrupt-parent = <&tzic>; + interrupts = <77>; + }; + usbphy0: usbphy0 { compatible = "usb-nop-xceiv"; clocks = <&clks IMX5_CLK_USB_PHY_GATE>; From f2254a39f6225b6dc1173412cfd0f6def0dbcb42 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 10 Jul 2018 13:31:45 -0300 Subject: [PATCH 66/96] ARM: dts: imx51: Add tigerp support As per the i.MX51 Reference Manual add an entry for the 'tigerp' region in the device tree. This is needed for accessing the ARM_GPC register to set the DBGEN bit, so that the debug clocks can be turned on. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 0205db56d913..5c4ba91e43ba 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -451,6 +451,11 @@ iim: iim@83f98000 { clocks = <&clks IMX5_CLK_IIM_GATE>; }; + tigerp: tigerp@83fa0000 { + compatible = "fsl,imx51-tigerp"; + reg = <0x83fa0000 0x28>; + }; + owire: owire@83fa4000 { compatible = "fsl,imx51-owire", "fsl,imx21-owire"; reg = <0x83fa4000 0x4000>; From e548eac2b70423590cf7375a7aee5aaeefdfd638 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 10 Jul 2018 13:31:46 -0300 Subject: [PATCH 67/96] ARM: dts: imx53: Add tigerp support As per the i.MX53 Reference Manual add an entry for the 'tigerp' region in the device tree. This is needed for accessing the ARM_GPC register to set the DBGEN bit, so that the debug clocks can be turned on. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 1a7a7bb3df45..3fd553c9cf8b 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -672,6 +672,11 @@ uart5: serial@63f90000 { status = "disabled"; }; + tigerp: tigerp@63fa0000 { + compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp"; + reg = <0x63fa0000 0x28>; + }; + owire: owire@63fa4000 { compatible = "fsl,imx53-owire", "fsl,imx21-owire"; reg = <0x63fa4000 0x4000>; From 4a2190aa2e92ba66d46e6bfdb8c68431e0ed9ced Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 10 Jul 2018 13:31:47 -0300 Subject: [PATCH 68/96] ARM: dts: imx53: Add a label for the PMU node Add a label for the PMU node so that the board dts may be able to pass the 'secure-reg-access' property like this: &pmu { secure-reg-access; }; This also makes it consistent with the PMU node in imx6qdl.dtsi Signed-off-by: Fabio Estevam Reviewed-by: Sebastian Reichel Tested-by: Sebastian Reichel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 3fd553c9cf8b..6386185ae234 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -113,7 +113,7 @@ osc { }; }; - pmu { + pmu: pmu { compatible = "arm,cortex-a8-pmu"; interrupt-parent = <&tzic>; interrupts = <77>; From 497f6ee16b05621bf118517dd4b7848836d9767e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 11 Jul 2018 18:34:27 -0300 Subject: [PATCH 69/96] ARM: dts: imx51-zii-rdu1: Disable internal watchdog imx51-zii-rdu1 has an external watchdog in the environment microcontroller, so disable the internal one. This aligns with what was done in commit 7055f714032c ("ARM: dts: imx6: RDU2: disable internal watchdog") for imx6 rdu2 board. Signed-off-by: Fabio Estevam Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index aede622c47a5..1217e196b93a 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -668,6 +668,10 @@ &usbotg { status = "okay"; }; +&wdog1 { + status = "disabled"; +}; + &iomuxc { pinctrl_ampgpio: ampgpiogrp { fsl,pins = < From 0b9c89e213d227d3649a1cb77bb6b912fbd532f9 Mon Sep 17 00:00:00 2001 From: Alex Gonzalez Date: Thu, 12 Jul 2018 10:20:35 +0200 Subject: [PATCH 70/96] ARM: dts: imx6ul: Add DTS for ConnectCore 6UL System-On-Module (SOM) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ConnectCore 6UL System-On-Module has the following hardware specification: * Based on a NXP i.MX6UL SoC * Industrial temperature ranges (-40ºC to +85ºC) * Up to 1GB DDR3 memory * Up to 2GB NAND flash * Dual Ethernet * On module 802.11 WiFi and Bluetooth 4.2 (QCA6564) * On module NXP Kinetis KL03 * On module Microchip ATECC508A crypto element Signed-off-by: Alex Gonzalez Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi | 201 ++++++++++++++++++++++ 1 file changed, 201 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi new file mode 100644 index 000000000000..c71a84da1af0 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsom.dtsi @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Digi International's ConnectCore 6UL System-On-Module device tree source + * + * Copyright 2018 Digi International, Inc. + * + */ + +/ { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x4000000>; + linux,cma-default; + }; + }; +}; + +&adc1 { + vref-supply = <&vdda_adc_3v3>; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pfuze3000: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + int_3v3: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <6250>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_arm_soc_in: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-ramp-delay = <6250>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <925000>; + }; + }; + + ext_3v3: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <6250>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr3: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1300000>; + }; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + vdd_snvs_3v3: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vdda_adc_3v3: vldo1 { + compatible = "regulator-fixed"; + regulator-name = "vref-adc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo2_ext: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vdda_wlan: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_high_in: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_int: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo4_ext: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vcoin_chg: vcoin { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmigrp { + fsl,pins = < + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; +}; + +®_arm { + vin-supply = <&vdd_arm_soc_in>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&vdd_arm_soc_in>; + regulator-allow-bypass; +}; From 8c7725829989d2711875f60356d22bc5af981ac0 Mon Sep 17 00:00:00 2001 From: Alex Gonzalez Date: Thu, 12 Jul 2018 10:20:36 +0200 Subject: [PATCH 71/96] ARM: dts: imx6ul: Add DTS for ConnectCore 6UL SBC Express The ConnectCore 6UL Single Board Computer (SBC) Express contains the ConnectCore 6UL System-On-Module. Its hardware specifications are: * 256MB DDR3 memory * 256MB NAND flash * Single Ethernet * USB Host and USB-OTG * MicroSD external storage * Groove connectors and Raspberry Pi Hat compatible expansion header Signed-off-by: Alex Gonzalez Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ul-ccimx6ulsbcexpress.dts | 200 ++++++++++++++++++ 2 files changed, 201 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 46d9edca187b..d459e2330307 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -541,6 +541,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-udoo-neo-full.dtb dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-14x14-evk.dtb \ + imx6ul-ccimx6ulsbcexpress.dtb \ imx6ul-geam.dtb \ imx6ul-isiot-emmc.dtb \ imx6ul-isiot-nand.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts new file mode 100644 index 000000000000..3792679c0c90 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Digi International's ConnectCore6UL SBC Express board device tree source + * + * Copyright 2018 Digi International, Inc. + * + */ + +/dts-v1/; +#include +#include +#include "imx6ul.dtsi" +#include "imx6ul-ccimx6ulsom.dtsi" + +/ { + model = "Digi International ConnectCore 6UL SBC Express."; + compatible = "digi,ccimx6ulsbcexpress", "digi,ccimx6ulsom", + "fsl,imx6ul"; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <&ext_3v3>; + status = "okay"; +}; + +&ecspi3 { + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3_master>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + smsc,disable-energy-detect; + reg = <0>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + broken-cd; /* no carrier detect line (use polling) */ + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_adc1: adc1grp { + fsl,pins = < + /* GPIO1_4/ADC1_IN4 (pin 7 of the expansion header) */ + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_ecspi3_master: ecspi3grp1 { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 /* Chip Select */ + >; + }; + + pinctrl_ecspi3_slave: ecspi3grp2 { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 + MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x10b0 /* Chip Select */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x10b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10071 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + /* General purpose pinctrl */ + pinctrl_hog: hoggrp { + fsl,pins = < + /* GPIOs BANK 3 */ + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xf030 + >; + }; +}; From dd769b09003ec92f088fef1be96bfe90cf44d640 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Thu, 12 Jul 2018 10:02:36 -0300 Subject: [PATCH 72/96] ARM: dts: imx53-ppd: Enable secure-reg-access Add 'secure-reg-access' property to enable PMU and hardware counters so that they can be properly used with the 'perf' tool. Signed-off-by: Sebastian Reichel [fabio: kept the change only in imx53-ppd context] Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-ppd.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts index 444ec84cf342..cdb90bee7b4a 100644 --- a/arch/arm/boot/dts/imx53-ppd.dts +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -594,6 +594,10 @@ lvds0_out: endpoint { }; }; +&pmu { + secure-reg-access; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; From 3ec14f5eb58f5c77713f39159e73422c187f9ca4 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 12 Jul 2018 10:02:37 -0300 Subject: [PATCH 73/96] ARM: dts: imx51-babbage: Enable secure-reg-access Add 'secure-reg-access' property to enable PMU and hardware counters so that they can be properly used with the 'perf' tool. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-babbage.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index a4a6d4a6b55b..ba60b0cb3cc1 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -396,6 +396,10 @@ MATRIX_KEY(3, 3, KEY_POWER) status = "okay"; }; +&pmu { + secure-reg-access; +}; + &ssi2 { status = "okay"; }; From b4d5f09fbc00463cee21c28485080e9537c48508 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 12 Jul 2018 10:02:38 -0300 Subject: [PATCH 74/96] ARM: dts: imx51-zii-rdu1: Enable secure-reg-access Add 'secure-reg-access' property to enable PMU and hardware counters so that they can be properly used with the 'perf' tool. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index 1217e196b93a..60b4d71c0dfe 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -565,6 +565,10 @@ &ipu_di0_disp1 { remote-endpoint = <&display_in>; }; +&pmu { + secure-reg-access; +}; + &ssi2 { status = "okay"; }; From a046e7662dcf2ddd28b84552e20baa03355d8423 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 13 Jul 2018 15:58:25 +0800 Subject: [PATCH 75/96] ARM: dts: imx6sll-evk: enable PWM1 for backlight driver Enable pwm1 module on i.MX6SLL EVK board to make backlight driver really work with LCD panel connected. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-evk.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index bc8d155cbfbc..cc5cf5e666fd 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -213,6 +213,12 @@ vgen6_reg: vgen6 { }; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -381,4 +387,10 @@ MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 >; }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 + >; + }; }; From e449d3780368364507b19524f8c660dc0409c053 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 13 Jul 2018 15:58:26 +0800 Subject: [PATCH 76/96] ARM: dts: imx6sll-evk: correct lcd regulator GPIO pin On i.MX6SLL EVK board, lcd regulator is controlled by GPIO4 IO03 using MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 pin, NOT MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08, correct it. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-evk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index cc5cf5e666fd..41e87e626926 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -74,7 +74,7 @@ reg_lcd: regulator-lcd { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_lcd>; regulator-name = "lcd-pwr"; - gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -289,7 +289,7 @@ MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 pinctrl_reg_lcd: reglcdgrp { fsl,pins = < - MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x17059 + MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 >; }; From 0ad26ef12f570e79871b9be9528ce4bb4ed173d1 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 13 Jul 2018 15:58:27 +0800 Subject: [PATCH 77/96] ARM: dts: imx6sll-evk: enable SEIKO 43WVF1G lcdif panel Enable SEIKO 43WVF1G lcdif panel for DRM driver, add necessary properties according to SEIKO 43WVF1G driver's requirement, such as "dvdd-supply", "avdd-supply" and "backlight" etc.. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-evk.dts | 76 +++++++++++++++++++++++++++++-- 1 file changed, 71 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index 41e87e626926..dc34da511c9c 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -23,7 +23,7 @@ memory@80000000 { reg = <0x80000000 0x80000000>; }; - backlight { + backlight_display: backlight-display { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -69,15 +69,22 @@ reg_aud4v: regulator-aud4v { regulator-boot-on; }; - reg_lcd: regulator-lcd { + reg_lcd_3v3: regulator-lcd-3v3 { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lcd>; - regulator-name = "lcd-pwr"; + pinctrl-0 = <&pinctrl_reg_lcd_3v3>; + regulator-name = "lcd-3v3"; gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; enable-active-high; }; + reg_lcd_5v: regulator-lcd-5v { + compatible = "regulator-fixed"; + regulator-name = "lcd-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + reg_sd1_vmmc: regulator-sd1-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -99,6 +106,19 @@ reg_sd3_vmmc: regulator-sd3-vmmc { gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + panel { + compatible = "sii,43wvf1g"; + backlight = <&backlight_display>; + dvdd-supply = <®_lcd_3v3>; + avdd-supply = <®_lcd_5v>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; }; &cpu0 { @@ -213,6 +233,18 @@ vgen6_reg: vgen6 { }; }; +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; @@ -287,7 +319,7 @@ MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 >; }; - pinctrl_reg_lcd: reglcdgrp { + pinctrl_reg_lcd_3v3: reglcd3v3grp { fsl,pins = < MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 >; @@ -388,6 +420,40 @@ MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 >; }; + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 + MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79 + MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79 + MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79 + MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79 + MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79 + MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79 + MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79 + MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79 + MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79 + MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79 + MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79 + MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79 + >; + }; + pinctrl_pwm1: pmw1grp { fsl,pins = < MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 From 282706a681634d5e42cfa4dde909be931d4105a4 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Fri, 13 Jul 2018 12:39:35 +0300 Subject: [PATCH 78/96] ARM: dts: imx6sl: Add vivante gpu nodes The imx6sl soc has gpu_2d and gpu_vg, no 3d support: etnaviv-gpu 2200000.gpu: model: GC320, revision: 5007 etnaviv-gpu 2204000.gpu: model: GC355, revision: 1215 The IP blocks seem to be already supported. Signed-off-by: Leonard Crestez Reviewed-by: Lucas Stach Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index a6b5ca48298f..7a4f5dace902 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -949,5 +949,25 @@ audmux: audmux@21d8000 { status = "disabled"; }; }; + + gpu_2d: gpu@2200000 { + compatible = "vivante,gc"; + reg = <0x02200000 0x4000>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_GPU2D_OVG>; + clock-names = "bus", "core"; + power-domains = <&pd_pu>; + }; + + gpu_vg: gpu@2204000 { + compatible = "vivante,gc"; + reg = <0x02204000 0x4000>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_GPU2D_OVG>; + clock-names = "bus", "core"; + power-domains = <&pd_pu>; + }; }; }; From 3221ceeede8af762d823fe7a9ae7883f89e4dfb2 Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Fri, 13 Jul 2018 14:49:02 +0200 Subject: [PATCH 79/96] ARM: dts: imx: Switch Boundary Devices boards to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Gary Bisson Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-nit6xlite.dts | 38 +----------------- arch/arm/boot/dts/imx6dl-nitrogen6x.dts | 38 +----------------- arch/arm/boot/dts/imx6q-nitrogen6_max.dts | 38 +----------------- arch/arm/boot/dts/imx6q-nitrogen6_som2.dts | 38 +----------------- arch/arm/boot/dts/imx6q-nitrogen6x.dts | 38 +----------------- arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 38 +----------------- arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 38 +----------------- arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 38 +----------------- arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 38 +----------------- arch/arm/boot/dts/imx6qp-nitrogen6_max.dts | 39 +------------------ arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts | 39 +------------------ arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 38 +----------------- arch/arm/boot/dts/imx7d-nitrogen7.dts | 39 +------------------ 13 files changed, 13 insertions(+), 484 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-nit6xlite.dts b/arch/arm/boot/dts/imx6dl-nit6xlite.dts index 30ce2c0cec2b..61fa30991d67 100644 --- a/arch/arm/boot/dts/imx6dl-nit6xlite.dts +++ b/arch/arm/boot/dts/imx6dl-nit6xlite.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts index ec53d7a09572..ef58d3b0ea0d 100644 --- a/arch/arm/boot/dts/imx6dl-nitrogen6x.dts +++ b/arch/arm/boot/dts/imx6dl-nitrogen6x.dts @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2013 Boundary Devices, Inc. * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_max.dts b/arch/arm/boot/dts/imx6q-nitrogen6_max.dts index 2a3c44f98eed..03bec0c53063 100644 --- a/arch/arm/boot/dts/imx6q-nitrogen6_max.dts +++ b/arch/arm/boot/dts/imx6q-nitrogen6_max.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts index c5d59baa1a07..eb4eecb6ed22 100644 --- a/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts +++ b/arch/arm/boot/dts/imx6q-nitrogen6_som2.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-nitrogen6x.dts b/arch/arm/boot/dts/imx6q-nitrogen6x.dts index df8ff397a914..435445a34ad0 100644 --- a/arch/arm/boot/dts/imx6q-nitrogen6x.dts +++ b/arch/arm/boot/dts/imx6q-nitrogen6x.dts @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2013 Boundary Devices, Inc. * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index aef4a756ca81..29baf25ae5d0 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include #include diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index 9cb464b65be1..39200e5dc896 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2015 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include #include diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi index 5e4da6d6fcff..572abd7499b1 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include #include diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index a14872436c5e..98384a6c5d12 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2013 Boundary Devices, Inc. * Copyright 2011 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include #include diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts b/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts index a39b86036581..741d1ed338ca 100644 --- a/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts +++ b/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts b/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts index 011726c836cd..1593ac86b2a4 100644 --- a/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts +++ b/arch/arm/boot/dts/imx6qp-nitrogen6_som2.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2017 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index 59e52f504922..f81ddfa46ace 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright (C) 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index 70c53e50b2fc..9c6a3fdfcf78 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -1,43 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 /* * Copyright 2016 Boundary Devices, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; From ac270caa1c420cc57ad2ba37679c2cf52c450781 Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Fri, 13 Jul 2018 14:49:03 +0200 Subject: [PATCH 80/96] ARM: dts: imx7d-nitrogen7: use OF graph to describe the display To make use of the new eLCDIF DRM driver OF graph description is required. Describe the display using OF graph nodes. Signed-off-by: Gary Bisson Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-nitrogen7.dts | 48 +++++++++------------------ 1 file changed, 15 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index 9c6a3fdfcf78..d8aac4a2d02a 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -11,11 +11,6 @@ / { model = "Boundary Devices i.MX7 Nitrogen7 Board"; compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d"; - aliases { - fb-lcd = &lcdif; - t-lcd = &t_lcd; - }; - memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -28,7 +23,7 @@ backlight-j9 { default-on; }; - backlight-j20 { + backlight_lcd: backlight-j20 { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -36,6 +31,17 @@ backlight-j20 { status = "okay"; }; + panel-lcd { + compatible = "okaya,rs800480t-7x0gp"; + backlight = <&backlight_lcd>; + + port { + panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { compatible = "regulator-fixed"; regulator-name = "usb_otg1_vbus"; @@ -280,35 +286,11 @@ codec: wm8960@1a { }; &lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat - &pinctrl_lcdif_ctrl>; - lcd-supply = <®_vref_3v3>; - display = <&display0>; status = "okay"; - display0: lcd-display { - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&t_lcd>; - t_lcd: t_lcd_default { - /* default to Okaya display */ - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <48>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; + port { + lcdif_out: endpoint { + remote-endpoint = <&panel_in>; }; }; }; From 2da6b9ce6a634773d22f157461d1119cd69e2672 Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Fri, 13 Jul 2018 14:49:04 +0200 Subject: [PATCH 81/96] ARM: dts: imx6sx-nitrogen6sx: remove obsolete display configuration This display configuration isn't working as-is as it depends on the tfp410 LCD to HDMI bridge. This will need to be updated later once the DRM MXSFB driver will be the default. Signed-off-by: Gary Bisson Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 71 ------------------------ 1 file changed, 71 deletions(-) diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts index f81ddfa46ace..adb5cc7d8ce2 100644 --- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -11,11 +11,6 @@ / { model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board"; compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx"; - aliases { - fb-lcd = &lcdif1; - t-lcd = &t_lcd; - }; - memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -225,38 +220,6 @@ &i2c3 { status = "okay"; }; -&lcdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif1>; - lcd-supply = <®_3p3v>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <24>; - - display-timings { - native-mode = <&t_lcd>; - t_lcd: t_lcd_default { - clock-frequency = <74160000>; - hactive = <1280>; - vactive = <720>; - hback-porch = <220>; - hfront-porch = <110>; - vback-porch = <20>; - vfront-porch = <5>; - hsync-len = <40>; - vsync-len = <5>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; - &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; @@ -488,40 +451,6 @@ MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 >; }; - pinctrl_lcdif1: lcdif1grp { - fsl,pins = < - MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 - MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 - MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 - MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 - MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 - MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 - MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 - MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 - MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 - MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 - MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 - MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 - MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 - MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 - MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 - MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 - MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 - MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 - MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 - MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 - MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 - MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 - MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 - MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 - MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 - MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 - MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 - MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 - >; - }; - pinctrl_pcie: pciegrp { fsl,pins = < MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0xb0b0 From a1a30f892894ff27b747a04d032fee72ade1bdca Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Fri, 13 Jul 2018 10:30:04 -0700 Subject: [PATCH 82/96] ARM: dts: imx51-zii-scu3-esb: Add switch IRQ line pinumx config Instead of relying on default values, configure PAD_AUD3_BB_CK to be a GPIO explicitly. While at, it change the pad configuration to enable a 100K pull-down (the pin is used as IRQ_TYPE_LEVEL_HIGH). Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Andrew Lunn Reviewed-by: Andrew Lunn Signed-off-by: Andrey Smirnov Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts index 07bc5fc05076..a7ede537e12a 100644 --- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts +++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts @@ -221,6 +221,8 @@ switch@0 { interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; ports { #address-cells = <1>; @@ -426,6 +428,12 @@ MX51_PAD_GPIO1_8__GPIO1_8 0xe5 >; }; + pinctrl_switch: switchgrp { + fsl,pins = < + MX51_PAD_AUD3_BB_CK__GPIO4_20 0xc5 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 From 129e96672f03cfd0181a0fb65446d61d05c2aa58 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Tue, 17 Jul 2018 14:44:38 +0800 Subject: [PATCH 83/96] ARM: dts: imx51-zii-scu3-esb: Fix RAVE SP watchdog compatible string It looks like I made a nasty typo in the original patch which resulted in missing watchdog device. Fix it. Cc: Nikita Yushchenko Cc: Lucas Stach Cc: cphealy@gmail.com Cc: Rob Herring Cc: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Andrew Lunn Signed-off-by: Andrey Smirnov Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-scu3-esb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts index a7ede537e12a..e6ebac8f43e4 100644 --- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts +++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts @@ -325,7 +325,7 @@ rave-sp { #size-cells = <1>; watchdog { - compatible = "zii,rave-sp-watchodg-legacy"; + compatible = "zii,rave-sp-watchdog-legacy"; }; eeprom@a4 { From 929d1b09cae21da94a1829f0f3032152f6ec0784 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Sat, 14 Jul 2018 09:53:58 +0800 Subject: [PATCH 84/96] ARM: dts: imx6sl-evk: add missing GPIO iomux setting On i.MX6SL EVK board, the MX6SL_PAD_KEY_ROW5 pin is used as lcd 3v3 regulator control pin, need to make sure MX6SL_PAD_KEY_ROW5 is muxed as GPIO function for controlling lcd 3v3 regulator. Signed-off-by: Anson Huang Reviewed-by; Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl-evk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 50bdc65670a3..046cfabc37e5 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -77,6 +77,8 @@ reg_aud4v: regulator-aud4v { reg_lcd_3v3: regulator-lcd-3v3 { compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd_3v3>; regulator-name = "lcd-3v3"; gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; enable-active-high; @@ -410,6 +412,12 @@ MX6SL_PAD_PWM1__PWM1_OUT 0x110b0 >; }; + pinctrl_reg_lcd_3v3: reglcd3v3grp { + fsl,pins = < + MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 From 9896b67eaf4b72b31481aa17266790d28c9c0a6c Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 17 Jul 2018 13:12:02 +0800 Subject: [PATCH 85/96] ARM: dts: imx6qdl-sabresd: make pfuze100 sw4 always on On i.MX6QDL Sabre-SD board, pfuze100 sw4 supplies GPS, touch and RGMII etc., these modules do NOT implement power domain control, so pfuze100 sw4 needs to be always on to make sure these modules work normally. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 15744ad52535..6e46a195b399 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -341,6 +341,7 @@ sw3b_reg: sw3b { sw4_reg: sw4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; swbst_reg: swbst { From 4de4238133f439790c3abd41523ae44dba826bd8 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 17 Jul 2018 13:12:03 +0800 Subject: [PATCH 86/96] ARM: dts: imx6sx-sdb-reva: make pfuze100 sw4 always on On i.MX6SX SDB Rev-A board, pfuze100 sw4 supplies csi, audio codec and i2c etc., these modules do NOT implement power domain control, so pfuze100 sw4 needs to be always on to make sure these modules work normally. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-sdb-reva.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6sx-sdb-reva.dts b/arch/arm/boot/dts/imx6sx-sdb-reva.dts index e3533e74ccc8..9cc6ff206aea 100644 --- a/arch/arm/boot/dts/imx6sx-sdb-reva.dts +++ b/arch/arm/boot/dts/imx6sx-sdb-reva.dts @@ -63,6 +63,7 @@ sw3b_reg: sw3b { sw4_reg: sw4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; swbst_reg: swbst { From 2afad1be58098e3f661428a0a70060f935f0b5dc Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 17 Jul 2018 13:12:04 +0800 Subject: [PATCH 87/96] ARM: dts: imx6sll-evk: make pfuze100 sw4 always on On i.MX6SLL EVK board, pfuze100 sw4 supplies LPDDR3 which is critical for system, must be always on. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll-evk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index dc34da511c9c..c8e115564ba2 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -177,6 +177,7 @@ sw3b_reg: sw3b { sw4_reg: sw4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; swbst_reg: swbst { From 0982a24f2401d8ac89e4694a21af3c118354f6ef Mon Sep 17 00:00:00 2001 From: Robin Gong Date: Tue, 17 Jul 2018 13:12:05 +0800 Subject: [PATCH 88/96] ARM: dts: imx6sl-evk: make pfuze100 sw4 always on On i.MX6SL EVK board, pfuze100 sw4 supplies LPDDR2 which is critical for system, must be always on. Signed-off-by: Robin Gong Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl-evk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 046cfabc37e5..679b4482ab13 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -201,6 +201,7 @@ sw3b_reg: sw3b { sw4_reg: sw4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; swbst_reg: swbst { From 25cd17a2360ee285a314e55affcfb0d7fa6aac0d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 16 Jul 2018 23:08:45 -0300 Subject: [PATCH 89/96] ARM: dts: imx6ul-pico-hobbit: Do not hardcode the memory size There are two variants of imx6ul-pico boards: one with 256MB and another one with 512MB of RAM. Do not hardcode the memory size in the device tree and let the bootloader fill the correct value instead. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-pico-hobbit.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts index 47682b8c023c..0c09420f9951 100644 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -51,8 +51,9 @@ / { model = "Technexion Pico i.MX6UL Board"; compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul"; + /* Will be filled by the bootloader */ memory@80000000 { - reg = <0x80000000 0x10000000>; + reg = <0x80000000 0>; }; chosen { From 56962b44a59a870b665dfa31f549fb37995a7624 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 16 Jul 2018 21:06:51 -0700 Subject: [PATCH 90/96] ARM: dts: vf610: Add ZII SSMB SPU3 board Add support for Zodiac Inflight Innovations SSMB SPU3 board (VF610-based). Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrew Lunn Signed-off-by: Andrey Smirnov Tested-by: Chris Healy Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 343 ++++++++++++++++++++++ 2 files changed, 345 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d459e2330307..6e25bae58492 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -577,7 +577,8 @@ dtb-$(CONFIG_SOC_VF610) += \ vf610m4-cosmic.dtb \ vf610-twr.dtb \ vf610-zii-dev-rev-b.dtb \ - vf610-zii-dev-rev-c.dtb + vf610-zii-dev-rev-c.dtb \ + vf610-zii-ssmb-spu3.dtb dtb-$(CONFIG_ARCH_MXS) += \ imx23-evk.dtb \ imx23-olinuxino.dtb \ diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts new file mode 100644 index 000000000000..b692117d7839 --- /dev/null +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Device tree file for ZII's SSMB SPU3 board + * + * SSMB - SPU3 Switch Management Board + * SPU - Seat Power Unit + * + * Copyright (C) 2015, 2016 Zodiac Inflight Innovations + * + * Based on an original 'vf610-twr.dts' which is Copyright 2015, + * Freescale Semiconductor, Inc. + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 SSMB SPU3 Board"; + compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + max-brightness = <1>; + }; + }; + + reg_vcc_3v3_mcu: regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; + /* + * Some SPU3s come with SPI-NOR chip DNPed, so we leave this + * node disabled by default and rely on bootloader to enable + * it when appropriate. + */ + status = "disabled"; + + m25p128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + + partition@0 { + label = "m25p128-0"; + reg = <0x0 0x01000000>; + }; + }; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6190"; + pinctrl-0 = <&pinctrl_gpio_switch0>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom-length = <65536>; + reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "eth_cu_1000_1"; + }; + + port@2 { + reg = <2>; + label = "eth_cu_1000_2"; + }; + + port@3 { + reg = <3>; + label = "eth_cu_1000_3"; + }; + + port@4 { + reg = <4>; + label = "eth_cu_1000_4"; + }; + + port@5 { + reg = <5>; + label = "eth_cu_1000_5"; + }; + + port@6 { + reg = <6>; + label = "eth_cu_1000_6"; + }; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + gpio6: pca9505@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + at24c04@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "nameplate"; + }; + + at24c04@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&iomuxc { + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTD4__DSPI1_CS1 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_gpio_switch0: pinctrl-gpio-switch0 { + fsl,pins = < + VF610_PAD_PTE2__GPIO_107 0x31c2 + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD3__GPIO_82 0x31c2 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB23__UART1_TX 0x21a2 + VF610_PAD_PTB24__UART1_RX 0x21a1 + >; + }; +}; From ea8f1d7af608a333989ef60cbe9d1edd84fe6080 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 17 Jul 2018 14:55:24 +0530 Subject: [PATCH 91/96] ARM: dts: imx6dl-mamoj: Add parallel display support This patch adds parallel display support for i.MX6DL Mamoj board along with relevant backlight through pwm. LCD power sequence is added by 'Michael Trimarchi'. Signed-off-by: Simone CIANNI Signed-off-by: Raffaele RECALCATI Signed-off-by: Michael Trimarchi Signed-off-by: Jagan Teki Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-mamoj.dts | 185 +++++++++++++++++++++++++++++ 1 file changed, 185 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-mamoj.dts b/arch/arm/boot/dts/imx6dl-mamoj.dts index 6b2d29138bed..38e94fd11a3f 100644 --- a/arch/arm/boot/dts/imx6dl-mamoj.dts +++ b/arch/arm/boot/dts/imx6dl-mamoj.dts @@ -6,11 +6,133 @@ /dts-v1/; +#include #include "imx6dl.dtsi" / { model = "BTicino i.MX6DL Mamoj board"; compatible = "bticino,imx6dl-mamoj", "fsl,imx6dl"; + + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 25000>; /* 25000ns -> 40kHz */ + brightness-levels = <0 4 8 16 32 64 128 160 192 224 255>; + default-brightness-level = <7>; + }; + + display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel-lcd { + compatible = "rocktech,rk070er9427"; + backlight = <&backlight_lcd>; + power-supply = <®_lcd_lr>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif_pwr>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_lcd_3v3: regulator-lcd-dvdd { + compatible = "regulator-fixed"; + regulator-name = "lcd-dvdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 1 0>; + enable-active-high; + startup-delay-us = <21000>; + }; + + reg_lcd_power: regulator-lcd-power { + compatible = "regulator-fixed"; + regulator-name = "lcd-enable"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 6 0>; + enable-active-high; + vin-supply = <®_lcd_3v3>; + }; + + reg_lcd_vgl: regulator-lcd-vgl { + compatible = "regulator-fixed"; + regulator-name = "lcd-vgl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + startup-delay-us = <6000>; + enable-active-high; + vin-supply = <®_lcd_power>; + }; + + reg_lcd_vgh: regulator-lcd-vgh { + compatible = "regulator-fixed"; + regulator-name = "lcd-vgh"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <6000>; + enable-active-high; + vin-supply = <®_lcd_avdd>; + }; + + reg_lcd_vcom: regulator-lcd-vcom { + compatible = "regulator-fixed"; + regulator-name = "lcd-vcom"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>; + startup-delay-us = <11000>; + enable-active-high; + vin-supply = <®_lcd_vgh>; + }; + + reg_lcd_lr: regulator-lcd-lr { + compatible = "regulator-fixed"; + regulator-name = "lcd-lr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_lcd_vcom>; + }; + + reg_lcd_avdd: regulator-lcd-avdd { + compatible = "regulator-fixed"; + regulator-name = "lcd-avdd"; + regulator-min-microvolt = <10280000>; + regulator-max-microvolt = <10280000>; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + startup-delay-us = <6000>; + enable-active-high; + vin-supply = <®_lcd_vgl>; + }; }; &fec { @@ -147,6 +269,16 @@ vgen6_reg: vgen6 { }; }; +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; @@ -200,6 +332,59 @@ MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 >; }; + pinctrl_ipu1_lcdif: pinctrlipu1lcdif { /* parallel port 24-bit */ + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */ + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* VDOUT_HSYNC */ + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VDOUT_VSYNC */ + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* VDOUT_RESET */ + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ipu1_lcdif_pwr: ipu1lcdifpwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x40013058 /* EN_LCD33V */ + MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x4001b0b0 /* EN_AVDD */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x40013058 /* ENVGH */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x40013058 /* ENVGL */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x40013058 /* LCD_POWER */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x40013058 /* EN_VCOM_LCD */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x40013058 /* LCD_L_R */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x40013058 /* LCD_U_D */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 From faed0d59c587615fb01b3729d03aea83b00ac1c2 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 17 Jul 2018 14:55:25 +0530 Subject: [PATCH 92/96] ARM: dts: imx6dl-mamoj: Add Wifi support Add TI WL18XX Wifi for BTicino i.MX6DL board. Signed-off-by: Simone CIANNI Signed-off-by: Raffaele RECALCATI Signed-off-by: Michael Trimarchi Signed-off-by: Jagan Teki Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-mamoj.dts | 53 ++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-mamoj.dts b/arch/arm/boot/dts/imx6dl-mamoj.dts index 38e94fd11a3f..530cb20ccc86 100644 --- a/arch/arm/boot/dts/imx6dl-mamoj.dts +++ b/arch/arm/boot/dts/imx6dl-mamoj.dts @@ -133,6 +133,18 @@ reg_lcd_avdd: regulator-lcd-avdd { enable-active-high; vin-supply = <®_lcd_vgl>; }; + + reg_wl18xx_vmmc: regulator-wl18xx-vmcc { + compatible = "regulator-fixed"; + regulator-name = "vwl1807"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio6 21 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; }; &fec { @@ -285,6 +297,30 @@ &uart3 { status = "okay"; }; +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + vmmc-supply = <®_wl18xx_vmmc>; + no-1-8-v; + non-removable; + wakeup-source; + keep-power-in-suspend; + cap-power-off-card; + max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + interrupt-parent = <&gpio6>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + tcxo-clock-frequency = <26000000>; + }; +}; + &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -392,6 +428,17 @@ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 >; }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17069 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10079 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17069 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17069 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17069 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17069 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 @@ -406,4 +453,10 @@ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 >; }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x4001b0b0 + >; + }; }; From af1cab82109c31a41a3d24bafea9e1e9bcd0f981 Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Tue, 17 Jul 2018 14:55:26 +0530 Subject: [PATCH 93/96] ARM: dts: imx6dl-mamoj: Add usb host and device support Add USB host and device support for BTicino i.MX6DL Mamoj board. Signed-off-by: Simone CIANNI Signed-off-by: Raffaele RECALCATI Signed-off-by: Michael Trimarchi Signed-off-by: Jagan Teki Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-mamoj.dts | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-mamoj.dts b/arch/arm/boot/dts/imx6dl-mamoj.dts index 530cb20ccc86..df8607fe4142 100644 --- a/arch/arm/boot/dts/imx6dl-mamoj.dts +++ b/arch/arm/boot/dts/imx6dl-mamoj.dts @@ -134,6 +134,17 @@ reg_lcd_avdd: regulator-lcd-avdd { vin-supply = <®_lcd_vgl>; }; + reg_usb_host: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbhost-vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhost>; + regulator-min-microvolt = <50000000>; + regulator-max-microvolt = <50000000>; + gpio = <&gpio6 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_wl18xx_vmmc: regulator-wl18xx-vmcc { compatible = "regulator-fixed"; regulator-name = "vwl1807"; @@ -297,6 +308,16 @@ &uart3 { status = "okay"; }; +&usbh1 { + vbus-supply = <®_usb_host>; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -428,6 +449,12 @@ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 >; }; + pinctrl_usbhost: usbhostgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17069 From 19fddda14765dc72b0a5ed9ce9ea5940587c6403 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 19 Jul 2018 12:57:24 -0700 Subject: [PATCH 94/96] ARM: dts: vf610: Add ZII CFU1 board Add support for the Zodiac Inflight Innovations CFU1 board (VF610-based). Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrew Lunn Signed-off-by: Andrey Smirnov Tested-by: Chris Healy Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/vf610-zii-cfu1.dts | 305 +++++++++++++++++++++++++++ 2 files changed, 306 insertions(+) create mode 100644 arch/arm/boot/dts/vf610-zii-cfu1.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6e25bae58492..1bb5a1d526eb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -576,6 +576,7 @@ dtb-$(CONFIG_SOC_VF610) += \ vf610-cosmic.dtb \ vf610m4-cosmic.dtb \ vf610-twr.dtb \ + vf610-zii-cfu1.dtb \ vf610-zii-dev-rev-b.dtb \ vf610-zii-dev-rev-c.dtb \ vf610-zii-ssmb-spu3.dtb diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts new file mode 100644 index 000000000000..37777cf22e67 --- /dev/null +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Copyright (C) 2018 Zodiac Inflight Innovations + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 CFU1 Board"; + compatible = "zii,vf610cfu1", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + max-brightness = <1>; + }; + + led-fail { + label = "zii:red:fail"; + gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + max-brightness = <1>; + }; + + led-status { + label = "zii:green:status"; + gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + max-brightness = <1>; + }; + + led-debug-a { + label = "zii:green:debug_a"; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + max-brightness = <1>; + }; + + led-debug-b { + label = "zii:green:debug_b"; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + max-brightness = <1>; + }; + }; + + reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; + status = "okay"; + + m25p128@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + + partition@0 { + label = "m25p128-0"; + reg = <0x0 0x01000000>; + }; + }; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6085"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; + reg = <0>; + eeprom-length = <512>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "eth_cu_1000_1"; + }; + + port@1 { + reg = <1>; + label = "eth_cu_1000_2"; + }; + + port@2 { + reg = <2>; + label = "eth_cu_1000_3"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + pca9554@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + }; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + at24c04@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + label = "nvm"; + }; + + at24c04@54 { + compatible = "atmel,24c04"; + reg = <0x54>; + label = "nameplate"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&iomuxc { + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30fe + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD3__GPIO_82 0x31c2 + VF610_PAD_PTE3__GPIO_108 0x31c2 + VF610_PAD_PTE4__GPIO_109 0x31c2 + VF610_PAD_PTE5__GPIO_110 0x31c2 + VF610_PAD_PTE6__GPIO_111 0x31c2 + >; + }; + + pinctrl_switch: switch-grp { + fsl,pins = < + VF610_PAD_PTB28__GPIO_98 0x3061 + VF610_PAD_PTE2__GPIO_107 0x1042 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; +}; From 55e20919709878d2391eab20252a0a0b9d1fe20a Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 19 Jul 2018 13:00:02 -0700 Subject: [PATCH 95/96] ARM: dts: vf610-zii-ssmb-spu3: Fix W=1 level warnings Fix a couple of things that were causing warning when building DTB with W=1. Cc: Fabio Estevam Cc: cphealy@gmail.com Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index b692117d7839..fe357668865b 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -23,7 +23,7 @@ chosen { stdout-path = &uart0; }; - memory { + memory@80000000 { reg = <0x80000000 0x20000000>; }; @@ -128,8 +128,6 @@ switch0: switch0@0 { compatible = "marvell,mv88e6190"; pinctrl-0 = <&pinctrl_gpio_switch0>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; reg = <0>; eeprom-length = <65536>; reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; From 33a8d5a595dd0f9b7f801c1cddb26dc05bc33a73 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 19 Jul 2018 16:24:19 +0800 Subject: [PATCH 96/96] ARM: dts: imx7d: remove "operating-points" property for cpu1 Commit b97872d4eb22 ("ARM: dts: imx: Add missing OPP properties for CPUs") added "operating-points" property for all CPUs, but i.MX7D already has "operating-points-v2" property on both CPUs, so no need to add "operating-points" property again, this patch removes it. Fixes: b97872d4eb22 ("ARM: dts: imx: Add missing OPP properties for CPUs") Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 9a772fc9e3b8..7cbc2ffa4b3a 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -18,11 +18,6 @@ cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; - operating-points = < - /* KHz uV */ - 996000 1075000 - 792000 975000 - >; clock-frequency = <996000000>; operating-points-v2 = <&cpu0_opp_table>; };