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ARM: dts: qcom: Fix sdhci node names - use 'mmc@'

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Since the Qualcomm sdhci-msm device-tree binding has been converted
to yaml format, 'make dtbs_check' reports issues with
inconsistent 'sdhci@' convention used for specifying the
sdhci nodes. The generic mmc bindings expect 'mmc@' format
instead.

Fix the same.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[bjorn: Extracted from combined arm64 patch]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220514215424.1007718-2-bhupesh.sharma@linaro.org
This commit is contained in:
Bhupesh Sharma
2022-05-15 03:24:19 +05:30
committed by Bjorn Andersson
parent fe5651cc8e
commit 2477d81901
6 changed files with 11 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/qcom-apq8084.dtsi
View File

@@ -419,7 +419,7 @@ blsp2_uart2: serial@f995e000 {
status = "disabled";
};
sdhci@f9824900 {
mmc@f9824900 {
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
@@ -432,7 +432,7 @@ sdhci@f9824900 {
status = "disabled";
};
sdhci@f98a4900 {
mmc@f98a4900 {
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";

2
arch/arm/boot/dts/qcom-ipq4019.dtsi
View File

@@ -221,7 +221,7 @@ vqmmc: regulator@1948000 {
status = "disabled";
};
sdhci: sdhci@7824900 {
sdhci: mmc@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x11c>, <0x7824000 0x800>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

6
arch/arm/boot/dts/qcom-msm8226.dtsi
View File

@@ -134,7 +134,7 @@ apcs: syscon@f9011000 {
reg = <0xf9011000 0x1000>;
};
sdhc_1: sdhci@f9824900 {
sdhc_1: mmc@f9824900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
@@ -150,7 +150,7 @@ sdhc_1: sdhci@f9824900 {
status = "disabled";
};
sdhc_2: sdhci@f98a4900 {
sdhc_2: mmc@f98a4900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";
@@ -166,7 +166,7 @@ sdhc_2: sdhci@f98a4900 {
status = "disabled";
};
sdhc_3: sdhci@f9864900 {
sdhc_3: mmc@f9864900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
reg-names = "hc_mem", "core_mem";

6
arch/arm/boot/dts/qcom-msm8974.dtsi
View File

@@ -436,7 +436,7 @@ acc3: clock-controller@f90b8000 {
reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
};
sdhc_1: sdhci@f9824900 {
sdhc_1: mmc@f9824900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
@@ -453,7 +453,7 @@ sdhc_1: sdhci@f9824900 {
status = "disabled";
};
sdhc_3: sdhci@f9864900 {
sdhc_3: mmc@f9864900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
reg-names = "hc_mem", "core_mem";
@@ -472,7 +472,7 @@ sdhc_3: sdhci@f9864900 {
status = "disabled";
};
sdhc_2: sdhci@f98a4900 {
sdhc_2: mmc@f98a4900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";

2
arch/arm/boot/dts/qcom-sdx55.dtsi
View File

@@ -388,7 +388,7 @@ tcsr: syscon@1fcb000 {
reg = <0x01fc0000 0x1000>;
};
sdhc_1: sdhci@8804000 {
sdhc_1: mmc@8804000 {
compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm/boot/dts/qcom-sdx65.dtsi
View File

@@ -331,7 +331,7 @@ glink-edge {
};
};
sdhc_1: sdhci@8804000 {
sdhc_1: mmc@8804000 {
compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
reg-names = "hc_mem";