From c16cc6a0667262dcf7bec9f74c9740079a46802d Mon Sep 17 00:00:00 2001 From: Biao Huang Date: Wed, 29 Jun 2022 11:17:34 +0800 Subject: [PATCH 01/10] net: ethernet: mtk-star-emac: store bit_clk_div in compat structure Not all the SoC are using the same clock divider. Move the divider into a compat structure specific to the SoCs. Signed-off-by: Biao Huang Signed-off-by: Fabien Parent Signed-off-by: David S. Miller --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 23 +++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c index 95839fd84dab..9c54043f7866 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -231,6 +232,10 @@ struct mtk_star_ring { unsigned int tail; }; +struct mtk_star_compat { + unsigned char bit_clk_div; +}; + struct mtk_star_priv { struct net_device *ndev; @@ -256,6 +261,8 @@ struct mtk_star_priv { int duplex; int pause; + const struct mtk_star_compat *compat_data; + /* Protects against concurrent descriptor access. */ spinlock_t lock; @@ -898,7 +905,7 @@ static void mtk_star_init_config(struct mtk_star_priv *priv) regmap_write(priv->regs, MTK_STAR_REG_SYS_CONF, val); regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CLK_CONF, MTK_STAR_MSK_MAC_CLK_CONF, - MTK_STAR_BIT_CLK_DIV_10); + priv->compat_data->bit_clk_div); } static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv) @@ -1460,6 +1467,7 @@ static int mtk_star_probe(struct platform_device *pdev) priv = netdev_priv(ndev); priv->ndev = ndev; + priv->compat_data = of_device_get_match_data(&pdev->dev); SET_NETDEV_DEV(ndev, dev); platform_set_drvdata(pdev, ndev); @@ -1556,10 +1564,17 @@ static int mtk_star_probe(struct platform_device *pdev) } #ifdef CONFIG_OF +static const struct mtk_star_compat mtk_star_mt8516_compat = { + .bit_clk_div = MTK_STAR_BIT_CLK_DIV_10, +}; + static const struct of_device_id mtk_star_of_match[] = { - { .compatible = "mediatek,mt8516-eth", }, - { .compatible = "mediatek,mt8518-eth", }, - { .compatible = "mediatek,mt8175-eth", }, + { .compatible = "mediatek,mt8516-eth", + .data = &mtk_star_mt8516_compat }, + { .compatible = "mediatek,mt8518-eth", + .data = &mtk_star_mt8516_compat }, + { .compatible = "mediatek,mt8175-eth", + .data = &mtk_star_mt8516_compat }, { } }; MODULE_DEVICE_TABLE(of, mtk_star_of_match); From 9ccbfdefe716ede5ece0a7331df7903d3879dbb7 Mon Sep 17 00:00:00 2001 From: Biao Huang Date: Wed, 29 Jun 2022 11:17:35 +0800 Subject: [PATCH 02/10] net: ethernet: mtk-star-emac: modify IRQ trigger flags If the flags in request_irq() is IRQF_TRIGGER_NONE, the trigger method is determined by "interrupt" property in dts. So, modify the flag from IRQF_TRIGGER_FALLING to IRQF_TRIGGER_NONE. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan Reviewed-by: Bartosz Golaszewski Signed-off-by: David S. Miller --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c index 9c54043f7866..f161a55bd09a 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -958,7 +958,7 @@ static int mtk_star_enable(struct net_device *ndev) /* Request the interrupt */ ret = request_irq(ndev->irq, mtk_star_handle_irq, - IRQF_TRIGGER_FALLING, ndev->name, ndev); + IRQF_TRIGGER_NONE, ndev->name, ndev); if (ret) goto err_free_skbs; From 6cde23b3ace57c339e380484b29820348aadd9b4 Mon Sep 17 00:00:00 2001 From: Biao Huang Date: Wed, 29 Jun 2022 11:17:36 +0800 Subject: [PATCH 03/10] net: ethernet: mtk-star-emac: add support for MT8365 SoC Add Ethernet driver support for MT8365 SoC. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan Signed-off-by: Fabien Parent Signed-off-by: David S. Miller --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 75 ++++++++++++++++--- 1 file changed, 64 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c index f161a55bd09a..3776af9ac1ff 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -150,6 +150,7 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" }; #define MTK_STAR_REG_MAC_CLK_CONF 0x00ac #define MTK_STAR_MSK_MAC_CLK_CONF GENMASK(7, 0) #define MTK_STAR_BIT_CLK_DIV_10 0x0a +#define MTK_STAR_BIT_CLK_DIV_50 0x32 /* Counter registers. */ #define MTK_STAR_REG_C_RXOKPKT 0x0100 @@ -182,9 +183,11 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" }; #define MTK_STAR_REG_C_RX_TWIST 0x0218 /* Ethernet CFG Control */ -#define MTK_PERICFG_REG_NIC_CFG_CON 0x03c4 -#define MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII GENMASK(3, 0) -#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII BIT(0) +#define MTK_PERICFG_REG_NIC_CFG0_CON 0x03c4 +#define MTK_PERICFG_REG_NIC_CFG1_CON 0x03c8 +#define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10 +#define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0) +#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1 /* Represents the actual structure of descriptors used by the MAC. We can * reuse the same structure for both TX and RX - the layout is the same, only @@ -233,6 +236,7 @@ struct mtk_star_ring { }; struct mtk_star_compat { + int (*set_interface_mode)(struct net_device *ndev); unsigned char bit_clk_div; }; @@ -908,13 +912,6 @@ static void mtk_star_init_config(struct mtk_star_priv *priv) priv->compat_data->bit_clk_div); } -static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv) -{ - regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON, - MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII, - MTK_PERICFG_BIT_NIC_CFG_CON_RMII); -} - static int mtk_star_enable(struct net_device *ndev) { struct mtk_star_priv *priv = netdev_priv(ndev); @@ -1530,7 +1527,13 @@ static int mtk_star_probe(struct platform_device *pdev) return -ENODEV; } - mtk_star_set_mode_rmii(priv); + if (priv->compat_data->set_interface_mode) { + ret = priv->compat_data->set_interface_mode(ndev); + if (ret) { + dev_err(dev, "Failed to set phy interface, err = %d\n", ret); + return -EINVAL; + } + } ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret) { @@ -1564,10 +1567,58 @@ static int mtk_star_probe(struct platform_device *pdev) } #ifdef CONFIG_OF +static int mt8516_set_interface_mode(struct net_device *ndev) +{ + struct mtk_star_priv *priv = netdev_priv(ndev); + struct device *dev = mtk_star_get_dev(priv); + unsigned int intf_val; + + switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_RMII: + intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + break; + default: + dev_err(dev, "This interface not supported\n"); + return -EINVAL; + } + + return regmap_update_bits(priv->pericfg, + MTK_PERICFG_REG_NIC_CFG0_CON, + MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, + intf_val); +} + +static int mt8365_set_interface_mode(struct net_device *ndev) +{ + struct mtk_star_priv *priv = netdev_priv(ndev); + struct device *dev = mtk_star_get_dev(priv); + unsigned int intf_val; + + switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_RMII: + intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + break; + default: + dev_err(dev, "This interface not supported\n"); + return -EINVAL; + } + + return regmap_update_bits(priv->pericfg, + MTK_PERICFG_REG_NIC_CFG_CON_V2, + MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, + intf_val); +} + static const struct mtk_star_compat mtk_star_mt8516_compat = { + .set_interface_mode = mt8516_set_interface_mode, .bit_clk_div = MTK_STAR_BIT_CLK_DIV_10, }; +static const struct mtk_star_compat mtk_star_mt8365_compat = { + .set_interface_mode = mt8365_set_interface_mode, + .bit_clk_div = MTK_STAR_BIT_CLK_DIV_50, +}; + static const struct of_device_id mtk_star_of_match[] = { { .compatible = "mediatek,mt8516-eth", .data = &mtk_star_mt8516_compat }, @@ -1575,6 +1626,8 @@ static const struct of_device_id mtk_star_of_match[] = { .data = &mtk_star_mt8516_compat }, { .compatible = "mediatek,mt8175-eth", .data = &mtk_star_mt8516_compat }, + { .compatible = "mediatek,mt8365-eth", + .data = &mtk_star_mt8365_compat }, { } }; MODULE_DEVICE_TABLE(of, mtk_star_of_match); From 43360697a27618dab2565bbdf0360a6441326dc5 Mon Sep 17 00:00:00 2001 From: Biao Huang Date: Wed, 29 Jun 2022 11:17:37 +0800 Subject: [PATCH 04/10] dt-bindings: net: mtk-star-emac: add support for MT8365 Add binding document for Ethernet on MT8365. Signed-off-by: Biao Huang Reviewed-by: Bartosz Golaszewski Acked-by: Rob Herring Signed-off-by: David S. Miller --- Documentation/devicetree/bindings/net/mediatek,star-emac.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml index def994c9cbb4..6b0769e831a6 100644 --- a/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml @@ -23,6 +23,7 @@ properties: - mediatek,mt8516-eth - mediatek,mt8518-eth - mediatek,mt8175-eth + - mediatek,mt8365-eth reg: maxItems: 1 From 85ef60330d37f8213ca6709559c7c7376d246a26 Mon Sep 17 00:00:00 2001 From: Biao Huang Date: Wed, 29 Jun 2022 11:17:38 +0800 Subject: [PATCH 05/10] net: ethernet: mtk-star-emac: add clock pad selection for RMII This patch add a new dts property named "mediatek,rmii-rxc" parsing in driver, which will configure MAC to select which pin the RMII reference clock is connected to, TXC or RXC. TXC pad is the default reference clock pin. If user wants to use RXC pad instead, add "mediatek,rmii-rxc" to corresponding device node. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan Signed-off-by: David S. Miller --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c index 3776af9ac1ff..b4d37728be69 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -188,6 +188,8 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" }; #define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10 #define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0) #define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1 +#define MTK_PERICFG_BIT_NIC_CFG_CON_CLK BIT(0) +#define MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2 BIT(8) /* Represents the actual structure of descriptors used by the MAC. We can * reuse the same structure for both TX and RX - the layout is the same, only @@ -264,6 +266,7 @@ struct mtk_star_priv { int speed; int duplex; int pause; + bool rmii_rxc; const struct mtk_star_compat *compat_data; @@ -1527,6 +1530,8 @@ static int mtk_star_probe(struct platform_device *pdev) return -ENODEV; } + priv->rmii_rxc = of_property_read_bool(of_node, "mediatek,rmii-rxc"); + if (priv->compat_data->set_interface_mode) { ret = priv->compat_data->set_interface_mode(ndev); if (ret) { @@ -1571,17 +1576,25 @@ static int mt8516_set_interface_mode(struct net_device *ndev) { struct mtk_star_priv *priv = netdev_priv(ndev); struct device *dev = mtk_star_get_dev(priv); - unsigned int intf_val; + unsigned int intf_val, ret, rmii_rxc; switch (priv->phy_intf) { case PHY_INTERFACE_MODE_RMII: intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + rmii_rxc = priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK; break; default: dev_err(dev, "This interface not supported\n"); return -EINVAL; } + ret = regmap_update_bits(priv->pericfg, + MTK_PERICFG_REG_NIC_CFG1_CON, + MTK_PERICFG_BIT_NIC_CFG_CON_CLK, + rmii_rxc); + if (ret) + return ret; + return regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG0_CON, MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, @@ -1597,6 +1610,7 @@ static int mt8365_set_interface_mode(struct net_device *ndev) switch (priv->phy_intf) { case PHY_INTERFACE_MODE_RMII: intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII; + intf_val |= priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2; break; default: dev_err(dev, "This interface not supported\n"); @@ -1605,7 +1619,8 @@ static int mt8365_set_interface_mode(struct net_device *ndev) return regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON_V2, - MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF, + MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF | + MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2, intf_val); } From 769c197b097c9fd433b73374cd5ebc57c0220977 Mon Sep 17 00:00:00 2001 From: Biao Huang Date: Wed, 29 Jun 2022 11:17:39 +0800 Subject: [PATCH 06/10] net: ethernet: mtk-star-emac: add timing adjustment support Add simple clock inversion for timing adjustment in driver. Add property "mediatek,txc-inverse" or "mediatek,rxc-inverse" to device node when necessary. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan Signed-off-by: David S. Miller --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c index b4d37728be69..05ce62202180 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -130,6 +130,11 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" }; #define MTK_STAR_REG_INT_MASK 0x0054 #define MTK_STAR_BIT_INT_MASK_FNRC BIT(6) +/* Delay-Macro Register */ +#define MTK_STAR_REG_TEST0 0x0058 +#define MTK_STAR_BIT_INV_RX_CLK BIT(30) +#define MTK_STAR_BIT_INV_TX_CLK BIT(31) + /* Misc. Config Register */ #define MTK_STAR_REG_TEST1 0x005c #define MTK_STAR_BIT_TEST1_RST_HASH_MBIST BIT(31) @@ -267,6 +272,8 @@ struct mtk_star_priv { int duplex; int pause; bool rmii_rxc; + bool rx_inv; + bool tx_inv; const struct mtk_star_compat *compat_data; @@ -1449,6 +1456,24 @@ static void mtk_star_clk_disable_unprepare(void *data) clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks); } +static int mtk_star_set_timing(struct mtk_star_priv *priv) +{ + struct device *dev = mtk_star_get_dev(priv); + unsigned int delay_val = 0; + + switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_RMII: + delay_val |= FIELD_PREP(MTK_STAR_BIT_INV_RX_CLK, priv->rx_inv); + delay_val |= FIELD_PREP(MTK_STAR_BIT_INV_TX_CLK, priv->tx_inv); + break; + default: + dev_err(dev, "This interface not supported\n"); + return -EINVAL; + } + + return regmap_write(priv->regs, MTK_STAR_REG_TEST0, delay_val); +} + static int mtk_star_probe(struct platform_device *pdev) { struct device_node *of_node; @@ -1531,6 +1556,8 @@ static int mtk_star_probe(struct platform_device *pdev) } priv->rmii_rxc = of_property_read_bool(of_node, "mediatek,rmii-rxc"); + priv->rx_inv = of_property_read_bool(of_node, "mediatek,rxc-inverse"); + priv->tx_inv = of_property_read_bool(of_node, "mediatek,txc-inverse"); if (priv->compat_data->set_interface_mode) { ret = priv->compat_data->set_interface_mode(ndev); @@ -1540,6 +1567,12 @@ static int mtk_star_probe(struct platform_device *pdev) } } + ret = mtk_star_set_timing(priv); + if (ret) { + dev_err(dev, "Failed to set timing, err = %d\n", ret); + return -EINVAL; + } + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); if (ret) { dev_err(dev, "unsupported DMA mask\n"); From 320c49fe31b0e567a785f37391c50e35b90e3240 Mon Sep 17 00:00:00 2001 From: Biao Huang Date: Wed, 29 Jun 2022 11:17:40 +0800 Subject: [PATCH 07/10] dt-bindings: net: mtk-star-emac: add description for new properties Add description for new properties which will be parsed in driver. Signed-off-by: Biao Huang Acked-by: Rob Herring Signed-off-by: David S. Miller --- .../bindings/net/mediatek,star-emac.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml index 6b0769e831a6..64c893c98d80 100644 --- a/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml @@ -48,6 +48,22 @@ properties: Phandle to the device containing the PERICFG register range. This is used to control the MII mode. + mediatek,rmii-rxc: + type: boolean + description: + If present, indicates that the RMII reference clock, which is from external + PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin. + + mediatek,rxc-inverse: + type: boolean + description: + If present, indicates that clock on RXC pad will be inversed. + + mediatek,txc-inverse: + type: boolean + description: + If present, indicates that clock on TXC pad will be inversed. + mdio: $ref: mdio.yaml# unevaluatedProperties: false From 0027340a239bf7b7d370dde4a00be06fbe7e80e6 Mon Sep 17 00:00:00 2001 From: Biao Huang Date: Wed, 29 Jun 2022 11:17:41 +0800 Subject: [PATCH 08/10] net: ethernet: mtk-star-emac: add support for MII interface Add support for MII interface. If user wants to use MII, assign "MII" to "phy-mode" property in dts. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan Signed-off-by: David S. Miller --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c index 05ce62202180..a1165f293494 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -192,6 +192,7 @@ static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" }; #define MTK_PERICFG_REG_NIC_CFG1_CON 0x03c8 #define MTK_PERICFG_REG_NIC_CFG_CON_V2 0x0c10 #define MTK_PERICFG_REG_NIC_CFG_CON_CFG_INTF GENMASK(3, 0) +#define MTK_PERICFG_BIT_NIC_CFG_CON_MII 0 #define MTK_PERICFG_BIT_NIC_CFG_CON_RMII 1 #define MTK_PERICFG_BIT_NIC_CFG_CON_CLK BIT(0) #define MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2 BIT(8) @@ -1462,6 +1463,7 @@ static int mtk_star_set_timing(struct mtk_star_priv *priv) unsigned int delay_val = 0; switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_RMII: delay_val |= FIELD_PREP(MTK_STAR_BIT_INV_RX_CLK, priv->rx_inv); delay_val |= FIELD_PREP(MTK_STAR_BIT_INV_TX_CLK, priv->tx_inv); @@ -1543,7 +1545,8 @@ static int mtk_star_probe(struct platform_device *pdev) ret = of_get_phy_mode(of_node, &priv->phy_intf); if (ret) { return ret; - } else if (priv->phy_intf != PHY_INTERFACE_MODE_RMII) { + } else if (priv->phy_intf != PHY_INTERFACE_MODE_RMII && + priv->phy_intf != PHY_INTERFACE_MODE_MII) { dev_err(dev, "unsupported phy mode: %s\n", phy_modes(priv->phy_intf)); return -EINVAL; @@ -1612,6 +1615,10 @@ static int mt8516_set_interface_mode(struct net_device *ndev) unsigned int intf_val, ret, rmii_rxc; switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_MII: + intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_MII; + rmii_rxc = 0; + break; case PHY_INTERFACE_MODE_RMII: intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII; rmii_rxc = priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK; @@ -1641,6 +1648,9 @@ static int mt8365_set_interface_mode(struct net_device *ndev) unsigned int intf_val; switch (priv->phy_intf) { + case PHY_INTERFACE_MODE_MII: + intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_MII; + break; case PHY_INTERFACE_MODE_RMII: intf_val = MTK_PERICFG_BIT_NIC_CFG_CON_RMII; intf_val |= priv->rmii_rxc ? 0 : MTK_PERICFG_BIT_NIC_CFG_CON_CLK_V2; From 0a8bd81fd6aaace14979152e0540da8ff158a00a Mon Sep 17 00:00:00 2001 From: Biao Huang Date: Wed, 29 Jun 2022 11:17:42 +0800 Subject: [PATCH 09/10] net: ethernet: mtk-star-emac: separate tx/rx handling with two NAPIs Current driver may lost tx interrupts under bidirectional test with iperf3, which leads to some unexpected issues. This patch let rx/tx interrupt enable/disable separately, and rx/tx are handled in different NAPIs. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan Signed-off-by: David S. Miller --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 338 ++++++++++-------- 1 file changed, 198 insertions(+), 140 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c index a1165f293494..87c6c9bc221d 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -33,6 +33,7 @@ #define MTK_STAR_SKB_ALIGNMENT 16 #define MTK_STAR_HASHTABLE_MC_LIMIT 256 #define MTK_STAR_HASHTABLE_SIZE_MAX 512 +#define MTK_STAR_DESC_NEEDED (MAX_SKB_FRAGS + 4) /* Normally we'd use NET_IP_ALIGN but on arm64 its value is 0 and it doesn't * work for this controller. @@ -228,7 +229,8 @@ struct mtk_star_ring_desc_data { struct sk_buff *skb; }; -#define MTK_STAR_RING_NUM_DESCS 128 +#define MTK_STAR_RING_NUM_DESCS 512 +#define MTK_STAR_TX_THRESH (MTK_STAR_RING_NUM_DESCS / 4) #define MTK_STAR_NUM_TX_DESCS MTK_STAR_RING_NUM_DESCS #define MTK_STAR_NUM_RX_DESCS MTK_STAR_RING_NUM_DESCS #define MTK_STAR_NUM_DESCS_TOTAL (MTK_STAR_RING_NUM_DESCS * 2) @@ -263,7 +265,8 @@ struct mtk_star_priv { struct mtk_star_ring rx_ring; struct mii_bus *mii; - struct napi_struct napi; + struct napi_struct tx_napi; + struct napi_struct rx_napi; struct device_node *phy_node; phy_interface_t phy_intf; @@ -379,19 +382,16 @@ mtk_star_ring_push_head_tx(struct mtk_star_ring *ring, mtk_star_ring_push_head(ring, desc_data, flags); } -static unsigned int mtk_star_ring_num_used_descs(struct mtk_star_ring *ring) +static unsigned int mtk_star_tx_ring_avail(struct mtk_star_ring *ring) { - return abs(ring->head - ring->tail); -} + u32 avail; -static bool mtk_star_ring_full(struct mtk_star_ring *ring) -{ - return mtk_star_ring_num_used_descs(ring) == MTK_STAR_RING_NUM_DESCS; -} + if (ring->tail > ring->head) + avail = ring->tail - ring->head - 1; + else + avail = MTK_STAR_RING_NUM_DESCS - ring->head + ring->tail - 1; -static bool mtk_star_ring_descs_available(struct mtk_star_ring *ring) -{ - return mtk_star_ring_num_used_descs(ring) > 0; + return avail; } static dma_addr_t mtk_star_dma_map_rx(struct mtk_star_priv *priv, @@ -436,6 +436,36 @@ static void mtk_star_nic_disable_pd(struct mtk_star_priv *priv) MTK_STAR_BIT_MAC_CFG_NIC_PD); } +static void mtk_star_enable_dma_irq(struct mtk_star_priv *priv, + bool rx, bool tx) +{ + u32 value; + + regmap_read(priv->regs, MTK_STAR_REG_INT_MASK, &value); + + if (tx) + value &= ~MTK_STAR_BIT_INT_STS_TNTC; + if (rx) + value &= ~MTK_STAR_BIT_INT_STS_FNRC; + + regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, value); +} + +static void mtk_star_disable_dma_irq(struct mtk_star_priv *priv, + bool rx, bool tx) +{ + u32 value; + + regmap_read(priv->regs, MTK_STAR_REG_INT_MASK, &value); + + if (tx) + value |= MTK_STAR_BIT_INT_STS_TNTC; + if (rx) + value |= MTK_STAR_BIT_INT_STS_FNRC; + + regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, value); +} + /* Unmask the three interrupts we care about, mask all others. */ static void mtk_star_intr_enable(struct mtk_star_priv *priv) { @@ -451,20 +481,11 @@ static void mtk_star_intr_disable(struct mtk_star_priv *priv) regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, ~0); } -static unsigned int mtk_star_intr_read(struct mtk_star_priv *priv) -{ - unsigned int val; - - regmap_read(priv->regs, MTK_STAR_REG_INT_STS, &val); - - return val; -} - static unsigned int mtk_star_intr_ack_all(struct mtk_star_priv *priv) { unsigned int val; - val = mtk_star_intr_read(priv); + regmap_read(priv->regs, MTK_STAR_REG_INT_STS, &val); regmap_write(priv->regs, MTK_STAR_REG_INT_STS, val); return val; @@ -736,25 +757,44 @@ static void mtk_star_free_tx_skbs(struct mtk_star_priv *priv) mtk_star_ring_free_skbs(priv, ring, mtk_star_dma_unmap_tx); } -/* All processing for TX and RX happens in the napi poll callback. - * - * FIXME: The interrupt handling should be more fine-grained with each - * interrupt enabled/disabled independently when needed. Unfortunatly this - * turned out to impact the driver's stability and until we have something - * working properly, we're disabling all interrupts during TX & RX processing - * or when resetting the counter registers. - */ +/** + * mtk_star_handle_irq - Interrupt Handler. + * @irq: interrupt number. + * @data: pointer to a network interface device structure. + * Description : this is the driver interrupt service routine. + * it mainly handles: + * 1. tx complete interrupt for frame transmission. + * 2. rx complete interrupt for frame reception. + * 3. MAC Management Counter interrupt to avoid counter overflow. + **/ static irqreturn_t mtk_star_handle_irq(int irq, void *data) { - struct mtk_star_priv *priv; - struct net_device *ndev; + struct net_device *ndev = data; + struct mtk_star_priv *priv = netdev_priv(ndev); + unsigned int intr_status = mtk_star_intr_ack_all(priv); + bool rx, tx; - ndev = data; - priv = netdev_priv(ndev); + rx = (intr_status & MTK_STAR_BIT_INT_STS_FNRC) && + napi_schedule_prep(&priv->rx_napi); + tx = (intr_status & MTK_STAR_BIT_INT_STS_TNTC) && + napi_schedule_prep(&priv->tx_napi); - if (netif_running(ndev)) { - mtk_star_intr_disable(priv); - napi_schedule(&priv->napi); + if (rx || tx) { + spin_lock(&priv->lock); + /* mask Rx and TX Complete interrupt */ + mtk_star_disable_dma_irq(priv, rx, tx); + spin_unlock(&priv->lock); + + if (rx) + __napi_schedule(&priv->rx_napi); + if (tx) + __napi_schedule(&priv->tx_napi); + } + + /* interrupt is triggered once any counters reach 0x8000000 */ + if (intr_status & MTK_STAR_REG_INT_STS_MIB_CNT_TH) { + mtk_star_update_stats(priv); + mtk_star_reset_counters(priv); } return IRQ_HANDLED; @@ -970,7 +1010,8 @@ static int mtk_star_enable(struct net_device *ndev) if (ret) goto err_free_skbs; - napi_enable(&priv->napi); + napi_enable(&priv->tx_napi); + napi_enable(&priv->rx_napi); mtk_star_intr_ack_all(priv); mtk_star_intr_enable(priv); @@ -1003,7 +1044,8 @@ static void mtk_star_disable(struct net_device *ndev) struct mtk_star_priv *priv = netdev_priv(ndev); netif_stop_queue(ndev); - napi_disable(&priv->napi); + napi_disable(&priv->tx_napi); + napi_disable(&priv->rx_napi); mtk_star_intr_disable(priv); mtk_star_dma_disable(priv); mtk_star_intr_ack_all(priv); @@ -1035,13 +1077,45 @@ static int mtk_star_netdev_ioctl(struct net_device *ndev, return phy_mii_ioctl(ndev->phydev, req, cmd); } -static int mtk_star_netdev_start_xmit(struct sk_buff *skb, - struct net_device *ndev) +static int __mtk_star_maybe_stop_tx(struct mtk_star_priv *priv, u16 size) +{ + netif_stop_queue(priv->ndev); + + /* Might race with mtk_star_tx_poll, check again */ + smp_mb(); + if (likely(mtk_star_tx_ring_avail(&priv->tx_ring) < size)) + return -EBUSY; + + netif_start_queue(priv->ndev); + + return 0; +} + +static inline int mtk_star_maybe_stop_tx(struct mtk_star_priv *priv, u16 size) +{ + if (likely(mtk_star_tx_ring_avail(&priv->tx_ring) >= size)) + return 0; + + return __mtk_star_maybe_stop_tx(priv, size); +} + +static netdev_tx_t mtk_star_netdev_start_xmit(struct sk_buff *skb, + struct net_device *ndev) { struct mtk_star_priv *priv = netdev_priv(ndev); struct mtk_star_ring *ring = &priv->tx_ring; struct device *dev = mtk_star_get_dev(priv); struct mtk_star_ring_desc_data desc_data; + int nfrags = skb_shinfo(skb)->nr_frags; + + if (unlikely(mtk_star_tx_ring_avail(ring) < nfrags + 1)) { + if (!netif_queue_stopped(ndev)) { + netif_stop_queue(ndev); + /* This is a hard error, log it. */ + pr_err_ratelimited("Tx ring full when queue awake\n"); + } + return NETDEV_TX_BUSY; + } desc_data.dma_addr = mtk_star_dma_map_tx(priv, skb); if (dma_mapping_error(dev, desc_data.dma_addr)) @@ -1049,17 +1123,11 @@ static int mtk_star_netdev_start_xmit(struct sk_buff *skb, desc_data.skb = skb; desc_data.len = skb->len; - - spin_lock_bh(&priv->lock); - mtk_star_ring_push_head_tx(ring, &desc_data); netdev_sent_queue(ndev, skb->len); - if (mtk_star_ring_full(ring)) - netif_stop_queue(ndev); - - spin_unlock_bh(&priv->lock); + mtk_star_maybe_stop_tx(priv, MTK_STAR_DESC_NEEDED); mtk_star_dma_resume_tx(priv); @@ -1091,31 +1159,40 @@ static int mtk_star_tx_complete_one(struct mtk_star_priv *priv) return ret; } -static void mtk_star_tx_complete_all(struct mtk_star_priv *priv) +static int mtk_star_tx_poll(struct napi_struct *napi, int budget) { + struct mtk_star_priv *priv = container_of(napi, struct mtk_star_priv, + tx_napi); + int ret = 0, pkts_compl = 0, bytes_compl = 0, count = 0; struct mtk_star_ring *ring = &priv->tx_ring; struct net_device *ndev = priv->ndev; - int ret, pkts_compl, bytes_compl; - bool wake = false; - - spin_lock(&priv->lock); - - for (pkts_compl = 0, bytes_compl = 0;; - pkts_compl++, bytes_compl += ret, wake = true) { - if (!mtk_star_ring_descs_available(ring)) - break; + unsigned int head = ring->head; + unsigned int entry = ring->tail; + while (entry != head && count < (MTK_STAR_RING_NUM_DESCS - 1)) { ret = mtk_star_tx_complete_one(priv); if (ret < 0) break; + + count++; + pkts_compl++; + bytes_compl += ret; + entry = ring->tail; } netdev_completed_queue(ndev, pkts_compl, bytes_compl); - if (wake && netif_queue_stopped(ndev)) + if (unlikely(netif_queue_stopped(ndev)) && + (mtk_star_tx_ring_avail(ring) > MTK_STAR_TX_THRESH)) netif_wake_queue(ndev); - spin_unlock(&priv->lock); + if (napi_complete(napi)) { + spin_lock(&priv->lock); + mtk_star_enable_dma_irq(priv, false, true); + spin_unlock(&priv->lock); + } + + return 0; } static void mtk_star_netdev_get_stats64(struct net_device *ndev, @@ -1195,7 +1272,7 @@ static const struct ethtool_ops mtk_star_ethtool_ops = { .set_link_ksettings = phy_ethtool_set_link_ksettings, }; -static int mtk_star_receive_packet(struct mtk_star_priv *priv) +static int mtk_star_rx(struct mtk_star_priv *priv, int budget) { struct mtk_star_ring *ring = &priv->rx_ring; struct device *dev = mtk_star_get_dev(priv); @@ -1203,107 +1280,85 @@ static int mtk_star_receive_packet(struct mtk_star_priv *priv) struct net_device *ndev = priv->ndev; struct sk_buff *curr_skb, *new_skb; dma_addr_t new_dma_addr; - int ret; + int ret, count = 0; - spin_lock(&priv->lock); - ret = mtk_star_ring_pop_tail(ring, &desc_data); - spin_unlock(&priv->lock); - if (ret) - return -1; + while (count < budget) { + ret = mtk_star_ring_pop_tail(ring, &desc_data); + if (ret) + return -1; - curr_skb = desc_data.skb; + curr_skb = desc_data.skb; - if ((desc_data.flags & MTK_STAR_DESC_BIT_RX_CRCE) || - (desc_data.flags & MTK_STAR_DESC_BIT_RX_OSIZE)) { - /* Error packet -> drop and reuse skb. */ - new_skb = curr_skb; - goto push_new_skb; - } + if ((desc_data.flags & MTK_STAR_DESC_BIT_RX_CRCE) || + (desc_data.flags & MTK_STAR_DESC_BIT_RX_OSIZE)) { + /* Error packet -> drop and reuse skb. */ + new_skb = curr_skb; + goto push_new_skb; + } - /* Prepare new skb before receiving the current one. Reuse the current - * skb if we fail at any point. - */ - new_skb = mtk_star_alloc_skb(ndev); - if (!new_skb) { - ndev->stats.rx_dropped++; - new_skb = curr_skb; - goto push_new_skb; - } + /* Prepare new skb before receiving the current one. + * Reuse the current skb if we fail at any point. + */ + new_skb = mtk_star_alloc_skb(ndev); + if (!new_skb) { + ndev->stats.rx_dropped++; + new_skb = curr_skb; + goto push_new_skb; + } - new_dma_addr = mtk_star_dma_map_rx(priv, new_skb); - if (dma_mapping_error(dev, new_dma_addr)) { - ndev->stats.rx_dropped++; - dev_kfree_skb(new_skb); - new_skb = curr_skb; - netdev_err(ndev, "DMA mapping error of RX descriptor\n"); - goto push_new_skb; - } + new_dma_addr = mtk_star_dma_map_rx(priv, new_skb); + if (dma_mapping_error(dev, new_dma_addr)) { + ndev->stats.rx_dropped++; + dev_kfree_skb(new_skb); + new_skb = curr_skb; + netdev_err(ndev, "DMA mapping error of RX descriptor\n"); + goto push_new_skb; + } - /* We can't fail anymore at this point: it's safe to unmap the skb. */ - mtk_star_dma_unmap_rx(priv, &desc_data); + /* We can't fail anymore at this point: + * it's safe to unmap the skb. + */ + mtk_star_dma_unmap_rx(priv, &desc_data); - skb_put(desc_data.skb, desc_data.len); - desc_data.skb->ip_summed = CHECKSUM_NONE; - desc_data.skb->protocol = eth_type_trans(desc_data.skb, ndev); - desc_data.skb->dev = ndev; - netif_receive_skb(desc_data.skb); + skb_put(desc_data.skb, desc_data.len); + desc_data.skb->ip_summed = CHECKSUM_NONE; + desc_data.skb->protocol = eth_type_trans(desc_data.skb, ndev); + desc_data.skb->dev = ndev; + netif_receive_skb(desc_data.skb); - /* update dma_addr for new skb */ - desc_data.dma_addr = new_dma_addr; + /* update dma_addr for new skb */ + desc_data.dma_addr = new_dma_addr; push_new_skb: - desc_data.len = skb_tailroom(new_skb); - desc_data.skb = new_skb; - spin_lock(&priv->lock); - mtk_star_ring_push_head_rx(ring, &desc_data); - spin_unlock(&priv->lock); + count++; - return 0; -} - -static int mtk_star_process_rx(struct mtk_star_priv *priv, int budget) -{ - int received, ret; - - for (received = 0, ret = 0; received < budget && ret == 0; received++) - ret = mtk_star_receive_packet(priv); + desc_data.len = skb_tailroom(new_skb); + desc_data.skb = new_skb; + mtk_star_ring_push_head_rx(ring, &desc_data); + } mtk_star_dma_resume_rx(priv); - return received; + return count; } -static int mtk_star_poll(struct napi_struct *napi, int budget) +static int mtk_star_rx_poll(struct napi_struct *napi, int budget) { struct mtk_star_priv *priv; - unsigned int status; - int received = 0; + int work_done = 0; - priv = container_of(napi, struct mtk_star_priv, napi); + priv = container_of(napi, struct mtk_star_priv, rx_napi); - status = mtk_star_intr_read(priv); - mtk_star_intr_ack_all(priv); - - if (status & MTK_STAR_BIT_INT_STS_TNTC) - /* Clean-up all TX descriptors. */ - mtk_star_tx_complete_all(priv); - - if (status & MTK_STAR_BIT_INT_STS_FNRC) - /* Receive up to $budget packets. */ - received = mtk_star_process_rx(priv, budget); - - if (unlikely(status & MTK_STAR_REG_INT_STS_MIB_CNT_TH)) { - mtk_star_update_stats(priv); - mtk_star_reset_counters(priv); + work_done = mtk_star_rx(priv, budget); + if (work_done < budget) { + napi_complete_done(napi, work_done); + spin_lock(&priv->lock); + mtk_star_enable_dma_irq(priv, true, false); + spin_unlock(&priv->lock); } - if (received < budget) - napi_complete_done(napi, received); - - mtk_star_intr_enable(priv); - - return received; + return work_done; } static void mtk_star_mdio_rwok_clear(struct mtk_star_priv *priv) @@ -1602,7 +1657,10 @@ static int mtk_star_probe(struct platform_device *pdev) ndev->netdev_ops = &mtk_star_netdev_ops; ndev->ethtool_ops = &mtk_star_ethtool_ops; - netif_napi_add(ndev, &priv->napi, mtk_star_poll, NAPI_POLL_WEIGHT); + netif_napi_add(ndev, &priv->rx_napi, mtk_star_rx_poll, + NAPI_POLL_WEIGHT); + netif_tx_napi_add(ndev, &priv->tx_napi, mtk_star_tx_poll, + NAPI_POLL_WEIGHT); return devm_register_netdev(dev, ndev); } From 02e9ce07d8b8e508d3276a73c056d26d30d76450 Mon Sep 17 00:00:00 2001 From: Biao Huang Date: Wed, 29 Jun 2022 11:17:43 +0800 Subject: [PATCH 10/10] net: ethernet: mtk-star-emac: enable half duplex hardware support Current driver doesn't support half duplex correctly. This patch enable half duplex capability in hardware. Signed-off-by: Biao Huang Signed-off-by: Yinghua Pan Signed-off-by: David S. Miller --- drivers/net/ethernet/mediatek/mtk_star_emac.c | 34 ++++++++----------- 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c index 87c6c9bc221d..21c3668194eb 100644 --- a/drivers/net/ethernet/mediatek/mtk_star_emac.c +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c @@ -883,32 +883,26 @@ static void mtk_star_phy_config(struct mtk_star_priv *priv) val <<= MTK_STAR_OFF_PHY_CTRL1_FORCE_SPD; val |= MTK_STAR_BIT_PHY_CTRL1_AN_EN; - val |= MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_RX; - val |= MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_TX; - /* Only full-duplex supported for now. */ - val |= MTK_STAR_BIT_PHY_CTRL1_FORCE_DPX; - + if (priv->pause) { + val |= MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_RX; + val |= MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_TX; + val |= MTK_STAR_BIT_PHY_CTRL1_FORCE_DPX; + } else { + val &= ~MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_RX; + val &= ~MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_TX; + val &= ~MTK_STAR_BIT_PHY_CTRL1_FORCE_DPX; + } regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL1, val); - if (priv->pause) { - val = MTK_STAR_VAL_FC_CFG_SEND_PAUSE_TH_2K; - val <<= MTK_STAR_OFF_FC_CFG_SEND_PAUSE_TH; - val |= MTK_STAR_BIT_FC_CFG_UC_PAUSE_DIR; - } else { - val = 0; - } - + val = MTK_STAR_VAL_FC_CFG_SEND_PAUSE_TH_2K; + val <<= MTK_STAR_OFF_FC_CFG_SEND_PAUSE_TH; + val |= MTK_STAR_BIT_FC_CFG_UC_PAUSE_DIR; regmap_update_bits(priv->regs, MTK_STAR_REG_FC_CFG, MTK_STAR_MSK_FC_CFG_SEND_PAUSE_TH | MTK_STAR_BIT_FC_CFG_UC_PAUSE_DIR, val); - if (priv->pause) { - val = MTK_STAR_VAL_EXT_CFG_SND_PAUSE_RLS_1K; - val <<= MTK_STAR_OFF_EXT_CFG_SND_PAUSE_RLS; - } else { - val = 0; - } - + val = MTK_STAR_VAL_EXT_CFG_SND_PAUSE_RLS_1K; + val <<= MTK_STAR_OFF_EXT_CFG_SND_PAUSE_RLS; regmap_update_bits(priv->regs, MTK_STAR_REG_EXT_CFG, MTK_STAR_MSK_EXT_CFG_SND_PAUSE_RLS, val); }