From b32b3cabf91e9569c070490821999008eb709d12 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 6 May 2026 13:19:57 +0300 Subject: [PATCH 01/38] Revert "drm/i915: replace select with dependency for visible DEBUG_OBJECTS" This reverts commit 025f89b01ed8d5e65d87ed54f231e10c6ac08188. 025f89b01ed8 ("drm/i915: replace select with dependency for visible DEBUG_OBJECTS") breaks the build in certain scenarios, presumably because config DRM_I915_DEBUG selects DRM_I915_SW_FENCE_DEBUG_OBJECTS without looking at its dependencies, allowing DRM_I915_SW_FENCE_DEBUG_OBJECTS=y and DEBUG_OBJECTS=n. Fixes: 025f89b01ed8 ("drm/i915: replace select with dependency for visible DEBUG_OBJECTS") Cc: Julian Braha Acked-by: Tvrtko Ursulin Link: https://patch.msgid.link/20260506101957.202271-1-jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/Kconfig.debug | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug index 9a2a49284876..3562a02ef7ad 100644 --- a/drivers/gpu/drm/i915/Kconfig.debug +++ b/drivers/gpu/drm/i915/Kconfig.debug @@ -153,7 +153,7 @@ config DRM_I915_TRACE_GTT config DRM_I915_SW_FENCE_DEBUG_OBJECTS bool "Enable additional driver debugging for fence objects" depends on DRM_I915 - depends on DEBUG_OBJECTS + select DEBUG_OBJECTS default n help Choose this option to turn on extra driver debugging that may affect From bdf5c2aaa5dd4096eafc4112f630f6104be4c0be Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 5 May 2026 11:41:50 +0300 Subject: [PATCH 02/38] drm/i915/irq: drop unnecessary forward declarations and includes The i915_irq.h header has a bunch of leftover forward declarations and includes. Remove them. Reviewed-by: Suraj Kandpal Link: https://patch.msgid.link/20260505084150.3346378-1-jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_irq.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h index 5c87d6d41c74..108a187618de 100644 --- a/drivers/gpu/drm/i915/i915_irq.h +++ b/drivers/gpu/drm/i915/i915_irq.h @@ -6,18 +6,11 @@ #ifndef __I915_IRQ_H__ #define __I915_IRQ_H__ -#include #include #include "i915_reg_defs.h" -enum pipe; -struct drm_crtc; -struct drm_device; -struct drm_display_mode; struct drm_i915_private; -struct intel_crtc; -struct intel_encoder; struct intel_uncore; void intel_irq_init(struct drm_i915_private *dev_priv); From 53bfcc08aff9a6d6354b0306d3060ac9507133ad Mon Sep 17 00:00:00 2001 From: Tvrtko Ursulin Date: Thu, 30 Apr 2026 18:46:01 +0300 Subject: [PATCH 03/38] drm/xe: Use fb cached min alignment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of just looking at the first plane use the fb cached overall minimum alignment. This aligns with how the i915 version of intel_plane_pin_fb works. Signed-off-by: Tvrtko Ursulin [vsyrjala: Rebase due to pin_params] Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260430154602.11393-1-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila --- drivers/gpu/drm/xe/display/xe_fb_pin.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index 5d7b30f62930..9dc8d66d0faa 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -458,6 +458,14 @@ static bool reuse_vma(struct intel_plane_state *new_plane_state, return true; } +static unsigned int +intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state) +{ + const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); + + return fb->min_alignment; +} + int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, const struct intel_plane_state *old_plane_state) { @@ -468,7 +476,7 @@ int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); struct intel_fb_pin_params pin_params = { .view = &new_plane_state->view.gtt, - .alignment = plane->min_alignment(plane, fb, 0), + .alignment = intel_plane_fb_min_alignment(new_plane_state), .needs_cpu_lmem_access = intel_fb_needs_cpu_access(fb), }; From 775fb670745015d679a65f948b3da0fbff3f100c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Thu, 30 Apr 2026 18:46:02 +0300 Subject: [PATCH 04/38] drm/xe: Respect pin_params.alignment for GGTT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix __xe_pin_fb_vma_ggtt() to actually respect the GGTT alignment specified by the display code. Misalignment can cause GTT faults etc. Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260430154602.11393-2-ville.syrjala@linux.intel.com Reviewed-by: Juha-Pekka Heikkila --- drivers/gpu/drm/xe/display/xe_fb_pin.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index 9dc8d66d0faa..f1082382d759 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -285,7 +285,7 @@ static int __xe_pin_fb_vma_ggtt(struct drm_gem_object *obj, */ guard(xe_pm_runtime_noresume)(xe); - align = XE_PAGE_SIZE; + align = max(XE_PAGE_SIZE, pin_params->alignment); if (xe_bo_is_vram(bo) && xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K) align = max(align, SZ_64K); From 0161e2c2016337a2f22ef79dff0aee43c0841bce Mon Sep 17 00:00:00 2001 From: Suraj Kandpal Date: Tue, 5 May 2026 15:10:22 +0530 Subject: [PATCH 05/38] drm/i915/hdcp: Skip inactive MST connectors when building stream list intel_hdcp_required_content_stream() walks every connector on the digital port to populate hdcp_port_data->streams[]. The only filter is connector_status_disconnected, which reflects physical presence on the MST topology, not whether the connector currently drives a stream. On a multi-sink MST setup where only a subset of sinks are modeset, the loop can pick a sibling MST connector that is connected but has no active CRTC / VC payload. intel_conn_to_vcpi() then logs "MST Payload not present" and returns 0, and the bogus StreamID=0 is written to the repeater in RepeaterAuth_Stream_Manage (DPCD 0x693F0). Authentication completes, but the repeater shortly raises LINK_INTEGRITY_FAILURE (RxStatus 0x69493 bit4) because the StreamID does not match any stream on its input. The HDCP check work then tears the link down, the Content Protection property drops back to DESIRED, and userspace observes a spurious HDCP enable failure. Filter the connector iteration to only those with a CRTC assigned in the new atomic state, so intel_conn_to_vcpi() is called for the connector actually being enabled and reads its real VCPI from the MST topology state. Signed-off-by: Suraj Kandpal Reviewed-by: Santhosh Reddy Guddati Link: https://patch.msgid.link/20260505094022.4064256-1-suraj.kandpal@intel.com --- drivers/gpu/drm/i915/display/intel_hdcp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 982f698e9814..25aca99682fd 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -113,6 +113,7 @@ intel_hdcp_required_content_stream(struct intel_atomic_state *state, { struct intel_display *display = to_intel_display(state); struct drm_connector_list_iter conn_iter; + struct drm_connector_state *new_conn_state; struct intel_digital_port *conn_dig_port; struct intel_connector *connector; struct hdcp_port_data *data = &dig_port->hdcp.port_data; @@ -139,6 +140,11 @@ intel_hdcp_required_content_stream(struct intel_atomic_state *state, if (conn_dig_port != dig_port) continue; + new_conn_state = drm_atomic_get_new_connector_state(&state->base, + &connector->base); + if (!new_conn_state || !new_conn_state->crtc) + continue; + data->streams[data->k].stream_id = intel_conn_to_vcpi(state, connector); data->k++; From dae483da59657eba80efa0437b72f14d221e1f03 Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Thu, 30 Apr 2026 18:42:16 +0530 Subject: [PATCH 06/38] drm/i915/intel_sdvo: Check fixed_mode->clock against max_dotclock in mode_valid For LVDS SDVO, mode validation checks the requested mode against the pipe max dotclock, but does not validate the selected fixed mode clock. After intel_panel_mode_valid(), get the fixed mode and validate its clock against the max dotclock. Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal Link: https://patch.msgid.link/20260430131220.3891497-2-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_sdvo.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index 2e1af9e869de..e7aaa5b203fd 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -1967,10 +1967,16 @@ intel_sdvo_mode_valid(struct drm_connector *connector, if (IS_LVDS(intel_sdvo_connector)) { enum drm_mode_status status; + const struct drm_display_mode *fixed_mode; status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode); if (status != MODE_OK) return status; + + fixed_mode = intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); + + if (fixed_mode && fixed_mode->clock > max_dotclk) + return MODE_CLOCK_HIGH; } return MODE_OK; From 9cdd4ec956b6a0fbfaaa88145478ebe680d4dbfd Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Thu, 30 Apr 2026 18:42:17 +0530 Subject: [PATCH 07/38] drm/i915/intel_panel: Avoid calls to intel_panel_fixed_mode() in mode_valid Currently, most callers of intel_panel_mode_valid() also call intel_panel_fixed_mode(). This is done either to check for the presence of a fixed mode for the connector or to get the clock of the fixed mode, which is then compared against the max dotclock for the pipe. Since intel_panel_mode_valid() already calls intel_panel_fixed_mode() internally, we can avoid yet another call to intel_panel_fixed_mode() from the caller. Remove the redundant call to intel_panel_fixed_mode() in mode_valid paths. To get the clock for the fixed mode, extend the helper intel_panel_mode_valid() to accept 'target_clock' as an out param. The 'target_clock' can then be used by the callers to check against the max dotclock. Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal Link: https://patch.msgid.link/20260430131220.3891497-3-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 8 ++------ drivers/gpu/drm/i915/display/intel_dsi.c | 7 +++---- drivers/gpu/drm/i915/display/intel_dvo.c | 15 +++------------ drivers/gpu/drm/i915/display/intel_lvds.c | 7 +++---- drivers/gpu/drm/i915/display/intel_panel.c | 9 ++++++++- drivers/gpu/drm/i915/display/intel_panel.h | 3 ++- drivers/gpu/drm/i915/display/intel_sdvo.c | 8 +++----- 7 files changed, 24 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 98df93884e9a..77791845d5da 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1571,7 +1571,6 @@ intel_dp_mode_valid(struct drm_connector *_connector, struct intel_connector *connector = to_intel_connector(_connector); const struct drm_display_info *info = &connector->base.display_info; struct intel_dp *intel_dp = intel_attached_dp(connector); - const struct drm_display_mode *fixed_mode; int target_clock = mode->clock; enum drm_mode_status status; @@ -1588,13 +1587,10 @@ intel_dp_mode_valid(struct drm_connector *_connector, if (intel_dp_hdisplay_bad(display, mode->hdisplay)) return MODE_H_ILLEGAL; - fixed_mode = intel_panel_fixed_mode(connector, mode); - if (intel_dp_is_edp(intel_dp) && fixed_mode) { - status = intel_panel_mode_valid(connector, mode); + if (intel_dp_is_edp(intel_dp)) { + status = intel_panel_mode_valid(connector, mode, &target_clock); if (status != MODE_OK) return status; - - target_clock = fixed_mode->clock; } /* diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c index 9005c1f5d857..3a111f041071 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi.c +++ b/drivers/gpu/drm/i915/display/intel_dsi.c @@ -63,18 +63,17 @@ enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector, { struct intel_display *display = to_intel_display(connector->dev); struct intel_connector *intel_connector = to_intel_connector(connector); - const struct drm_display_mode *fixed_mode = - intel_panel_fixed_mode(intel_connector, mode); int max_dotclk = display->cdclk.max_dotclk_freq; enum drm_mode_status status; + int target_clock; drm_dbg_kms(display->drm, "\n"); - status = intel_panel_mode_valid(intel_connector, mode); + status = intel_panel_mode_valid(intel_connector, mode, &target_clock); if (status != MODE_OK) return status; - if (fixed_mode->clock > max_dotclk) + if (target_clock > max_dotclk) return MODE_CLOCK_HIGH; return intel_mode_valid_max_plane_size(display, mode, 1); diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c index 405b33aca9dd..65015477abed 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo.c +++ b/drivers/gpu/drm/i915/display/intel_dvo.c @@ -223,8 +223,6 @@ intel_dvo_mode_valid(struct drm_connector *_connector, struct intel_display *display = to_intel_display(_connector->dev); struct intel_connector *connector = to_intel_connector(_connector); struct intel_dvo *intel_dvo = intel_attached_dvo(connector); - const struct drm_display_mode *fixed_mode = - intel_panel_fixed_mode(connector, mode); int max_dotclk = display->cdclk.max_dotclk_freq; int target_clock = mode->clock; enum drm_mode_status status; @@ -234,16 +232,9 @@ intel_dvo_mode_valid(struct drm_connector *_connector, return status; /* XXX: Validate clock range */ - - if (fixed_mode) { - enum drm_mode_status status; - - status = intel_panel_mode_valid(connector, mode); - if (status != MODE_OK) - return status; - - target_clock = fixed_mode->clock; - } + status = intel_panel_mode_valid(connector, mode, &target_clock); + if (status != MODE_OK) + return status; if (target_clock > max_dotclk) return MODE_CLOCK_HIGH; diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index cc6d4bfcff10..ab6ba08ac091 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -395,20 +395,19 @@ intel_lvds_mode_valid(struct drm_connector *_connector, { struct intel_display *display = to_intel_display(_connector->dev); struct intel_connector *connector = to_intel_connector(_connector); - const struct drm_display_mode *fixed_mode = - intel_panel_fixed_mode(connector, mode); int max_pixclk = display->cdclk.max_dotclk_freq; enum drm_mode_status status; + int target_clock; status = intel_cpu_transcoder_mode_valid(display, mode); if (status != MODE_OK) return status; - status = intel_panel_mode_valid(connector, mode); + status = intel_panel_mode_valid(connector, mode, &target_clock); if (status != MODE_OK) return status; - if (fixed_mode->clock > max_pixclk) + if (target_clock > max_pixclk) return MODE_CLOCK_HIGH; return MODE_OK; diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 2a20aaaaac39..20c548eea6da 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -396,11 +396,15 @@ intel_panel_detect(struct drm_connector *connector, bool force) enum drm_mode_status intel_panel_mode_valid(struct intel_connector *connector, - const struct drm_display_mode *mode) + const struct drm_display_mode *mode, + int *target_clock) { const struct drm_display_mode *fixed_mode = intel_panel_fixed_mode(connector, mode); + if (target_clock) + *target_clock = mode->clock; + if (!fixed_mode) return MODE_OK; @@ -413,6 +417,9 @@ intel_panel_mode_valid(struct intel_connector *connector, if (drm_mode_vrefresh(mode) != drm_mode_vrefresh(fixed_mode)) return MODE_PANEL; + if (target_clock) + *target_clock = fixed_mode->clock; + return MODE_OK; } diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h index 56a6412cf0fb..23bd227826c9 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.h +++ b/drivers/gpu/drm/i915/display/intel_panel.h @@ -43,7 +43,8 @@ int intel_panel_get_modes(struct intel_connector *connector); enum drrs_type intel_panel_drrs_type(struct intel_connector *connector); enum drm_mode_status intel_panel_mode_valid(struct intel_connector *connector, - const struct drm_display_mode *mode); + const struct drm_display_mode *mode, + int *target_clock); int intel_panel_compute_config(struct intel_connector *connector, struct drm_display_mode *adjusted_mode); void intel_panel_add_edid_fixed_modes(struct intel_connector *connector, diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index e7aaa5b203fd..7843eb13f2e3 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -1967,15 +1967,13 @@ intel_sdvo_mode_valid(struct drm_connector *connector, if (IS_LVDS(intel_sdvo_connector)) { enum drm_mode_status status; - const struct drm_display_mode *fixed_mode; + int target_clock; - status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode); + status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode, &target_clock); if (status != MODE_OK) return status; - fixed_mode = intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); - - if (fixed_mode && fixed_mode->clock > max_dotclk) + if (target_clock > max_dotclk) return MODE_CLOCK_HIGH; } From c6aeb1229dc282d04cc738bc4ac7f9d673fbaf24 Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Thu, 30 Apr 2026 18:42:18 +0530 Subject: [PATCH 08/38] drm/i915/intel_dvo: Drop call to intel_panel_fixed_mode() from compute_config The function intel_dvo_compute_config() calls intel_panel_fixed_mode() only to check if there is a valid fixed_mode and based on that it then calls intel_panel_compute_config(). However, since the intel_panel_compute_config() already checks for fixed_mode and we can drop the call to intel_panel_fixed_mode(). Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal Link: https://patch.msgid.link/20260430131220.3891497-4-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_dvo.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c index 65015477abed..dd1a995c2979 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo.c +++ b/drivers/gpu/drm/i915/display/intel_dvo.c @@ -246,11 +246,9 @@ static int intel_dvo_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) { - struct intel_dvo *intel_dvo = enc_to_dvo(encoder); struct intel_connector *connector = to_intel_connector(conn_state->connector); struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; - const struct drm_display_mode *fixed_mode = - intel_panel_fixed_mode(intel_dvo->attached_connector, adjusted_mode); + int ret; /* * If we have timings from the BIOS for the panel, put them in @@ -258,13 +256,9 @@ static int intel_dvo_compute_config(struct intel_encoder *encoder, * with the panel scaling set up to source from the H/VDisplay * of the original mode. */ - if (fixed_mode) { - int ret; - - ret = intel_panel_compute_config(connector, adjusted_mode); - if (ret) - return ret; - } + ret = intel_panel_compute_config(connector, adjusted_mode); + if (ret) + return ret; if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) return -EINVAL; From 90d8acc6d8b780822aa3fa7ff6f1614d0454fd58 Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Thu, 30 Apr 2026 18:42:19 +0530 Subject: [PATCH 09/38] drm/i915/intel_sdvo: Drop call to intel_panel_fixed_mode() from compute_config Currently, in intel_sdvo_compute_config(), intel_panel_fixed_mode() is called to get the fixed mode. However, since the call is made after intel_panel_compute_config, that copies the selected fixed mode to the adjusted mode, we can directly use the crtc_state->hw.adjusted_mode. So remove the extra call to intel_panel_fixed_mode() and use adjusted mode instead. Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal Link: https://patch.msgid.link/20260430131220.3891497-5-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_sdvo.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index 7843eb13f2e3..c18e7d5e9c34 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -1395,8 +1395,7 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder, adjusted_mode); pipe_config->sdvo_tv_clock = true; } else if (IS_LVDS(intel_sdvo_connector)) { - const struct drm_display_mode *fixed_mode = - intel_panel_fixed_mode(&intel_sdvo_connector->base, mode); + const struct drm_display_mode *fixed_mode; int ret; ret = intel_panel_compute_config(&intel_sdvo_connector->base, @@ -1404,6 +1403,8 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder, if (ret) return ret; + fixed_mode = &pipe_config->hw.adjusted_mode; + if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, intel_sdvo_connector, fixed_mode)) From 5b9eb61b37749438997b17c57a9b9212e7d12543 Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Thu, 30 Apr 2026 18:42:20 +0530 Subject: [PATCH 10/38] drm/i915/dp: Drop call to intel_panel_fixed_mode() from compute_config At the moment, in intel_dp_compute_config(), intel_panel_fixed_mode() is called to check if the panel has any fixed mode or not. If it is an eDP and has the fixed mode, then intel_panel_compute_config() is called. However, the intel_panel_compute_config already checks if the panel supports a fixed mode and returns early if it doesn't. This makes the earlier check in the caller redundant. Remove this extra check for intel_panel_fixed_mode(). Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal Link: https://patch.msgid.link/20260430131220.3891497-6-ankit.k.nautiyal@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 77791845d5da..450098e08faa 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3589,12 +3589,10 @@ intel_dp_compute_config(struct intel_encoder *encoder, struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - const struct drm_display_mode *fixed_mode; struct intel_connector *connector = intel_dp->attached_connector; int ret = 0, link_bpp_x16; - fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode); - if (intel_dp_is_edp(intel_dp) && fixed_mode) { + if (intel_dp_is_edp(intel_dp)) { ret = intel_panel_compute_config(connector, adjusted_mode); if (ret) return ret; From d7a189c0b6c0c7081b0e424780da3d0d5fa14556 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 7 May 2026 09:59:39 +0300 Subject: [PATCH 11/38] drm/i915/ddi: Fix cleanup after DP connector init failure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix the error path during DDI encoder/connector initialization by calling the missing TC port cleanup function. This fixes the leaked TC port state. Reviewed-by: Jouni Högander Signed-off-by: Imre Deak Link: https://patch.msgid.link/20260507065940.2046690-1-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 2681940a5cfe..e37cc32ee83e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -5411,7 +5411,7 @@ void intel_ddi_init(struct intel_display *display, if (need_aux_ch(encoder, init_dp)) { dig_port->aux_ch = intel_dp_aux_ch(encoder); if (dig_port->aux_ch == AUX_CH_NONE) - goto err; + goto err_aux_ch_init; } /* @@ -5447,7 +5447,7 @@ void intel_ddi_init(struct intel_display *display, dig_port->unlock = intel_tc_port_unlock; if (intel_tc_port_init(dig_port, is_legacy) < 0) - goto err; + goto err_aux_ch_init; } drm_WARN_ON(display->drm, port > PORT_I); @@ -5478,7 +5478,7 @@ void intel_ddi_init(struct intel_display *display, if (init_dp) { if (intel_ddi_init_dp_connector(dig_port)) - goto err; + goto err_dp_connector_init; dig_port->hpd_pulse = intel_dp_hpd_pulse; @@ -5492,12 +5492,15 @@ void intel_ddi_init(struct intel_display *display, */ if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { if (intel_ddi_init_hdmi_connector(dig_port)) - goto err; + goto err_dp_connector_init; } return; -err: +err_dp_connector_init: + if (intel_encoder_is_tc(encoder)) + intel_tc_port_cleanup(dig_port); +err_aux_ch_init: drm_encoder_cleanup(&encoder->base); kfree(dig_port); } From ae951de6bc00491d013b38e38408b6f5dd90ba92 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 7 May 2026 09:59:40 +0300 Subject: [PATCH 12/38] drm/i915/ddi: Fix cleanup after HDMI connector init failure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Perform the missing DDI DP connector cleanup steps after HDMI connector initialization failure during DDI encoder/connector initialization. This fixes the leaked DP MST encoder, AUX state, and connector object. Reported-by: Sashiko Reviewed-by: Jouni Högander Signed-off-by: Imre Deak Link: https://patch.msgid.link/20260507065940.2046690-2-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_ddi.c | 14 +++++++++++++- drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 3 +++ 3 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index e37cc32ee83e..cd61ddb7f469 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4729,6 +4729,15 @@ static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) return 0; } +static void intel_ddi_cleanup_dp_connector(struct intel_digital_port *dig_port) +{ + struct intel_dp *intel_dp = &dig_port->dp; + struct intel_connector *connector = intel_dp->attached_connector; + + intel_dp_cleanup_connector(dig_port, connector); + kfree(connector); +} + static int intel_hdmi_reset_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx) { @@ -5492,11 +5501,14 @@ void intel_ddi_init(struct intel_display *display, */ if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { if (intel_ddi_init_hdmi_connector(dig_port)) - goto err_dp_connector_init; + goto err_hdmi_connector_init; } return; +err_hdmi_connector_init: + if (init_dp) + intel_ddi_cleanup_dp_connector(dig_port); err_dp_connector_init: if (intel_encoder_is_tc(encoder)) intel_tc_port_cleanup(dig_port); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 450098e08faa..408846fb98f0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -7340,6 +7340,19 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, return false; } +void intel_dp_cleanup_connector(struct intel_digital_port *dig_port, + struct intel_connector *connector) +{ + struct intel_display *display = to_intel_display(connector); + struct intel_dp *intel_dp = &dig_port->dp; + + intel_display_power_flush_work(display); + + intel_dp_mst_encoder_cleanup(dig_port); + intel_dp_aux_fini(intel_dp); + drm_connector_cleanup(&connector->base); +} + void intel_dp_mst_suspend(struct intel_display *display) { struct intel_encoder *encoder; diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 2849b9ecdc71..f41480d24714 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -48,6 +48,9 @@ intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state); bool intel_dp_init_connector(struct intel_digital_port *dig_port, struct intel_connector *intel_connector); +void intel_dp_cleanup_connector(struct intel_digital_port *dig_port, + struct intel_connector *connector); + void intel_dp_connector_sync_state(struct intel_connector *connector, const struct intel_crtc_state *crtc_state); void intel_dp_set_link_params(struct intel_dp *intel_dp, From 931744602993be96385ed1b9deb40d5675306d28 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 8 May 2026 13:20:47 +0300 Subject: [PATCH 13/38] Documentation/gpu: add dedicated documentation for Intel display Nowadays, the display support for drm/i915 and drm/xe is shared between the drivers, even though the code is located under drm/i915/display. The drm/i915 documentation has everything, including display topics, in one huge page, while the drm/xe documentation is well-organized but hardly mentions display. It's not great, to put it mildly. Split out the Intel display documentation to a dedicated directory, Documentation/gpu/intel-display. Also directly split the functionality/feature documentation to dedicated pages to keep the main index page high level and readable. We'll want to organize this further, but just sort them alphabetically for starters. Drop the boilerplate documentation sections that don't actually document anything. Cross-reference drm/i915, drm/xe, and intel-display. Tested-by: Randy Dunlap Reviewed-by: Rodrigo Vivi Link: https://patch.msgid.link/21bfa7777eb0926eadd309d4c6f5c9cf48405cf0.1778235406.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- Documentation/gpu/drivers.rst | 1 + Documentation/gpu/drm-kms.rst | 3 + Documentation/gpu/i915.rst | 202 +----------------- .../gpu/intel-display/async-flip.rst | 8 + Documentation/gpu/intel-display/audio.rst | 23 ++ Documentation/gpu/intel-display/cdclk.rst | 11 + Documentation/gpu/intel-display/dmc.rst | 26 +++ Documentation/gpu/intel-display/dpio.rst | 8 + Documentation/gpu/intel-display/dpll.rst | 14 ++ Documentation/gpu/intel-display/drrs.rst | 11 + Documentation/gpu/intel-display/dsb.rst | 11 + Documentation/gpu/intel-display/fbc.rst | 11 + .../gpu/intel-display/fifo-underrun.rst | 11 + .../gpu/intel-display/frontbuffer.rst | 14 ++ Documentation/gpu/intel-display/hotplug.rst | 11 + Documentation/gpu/intel-display/index.rst | 40 ++++ Documentation/gpu/intel-display/plane.rst | 11 + Documentation/gpu/intel-display/psr.rst | 11 + Documentation/gpu/intel-display/vbt.rst | 14 ++ Documentation/gpu/xe/index.rst | 5 + 20 files changed, 251 insertions(+), 195 deletions(-) create mode 100644 Documentation/gpu/intel-display/async-flip.rst create mode 100644 Documentation/gpu/intel-display/audio.rst create mode 100644 Documentation/gpu/intel-display/cdclk.rst create mode 100644 Documentation/gpu/intel-display/dmc.rst create mode 100644 Documentation/gpu/intel-display/dpio.rst create mode 100644 Documentation/gpu/intel-display/dpll.rst create mode 100644 Documentation/gpu/intel-display/drrs.rst create mode 100644 Documentation/gpu/intel-display/dsb.rst create mode 100644 Documentation/gpu/intel-display/fbc.rst create mode 100644 Documentation/gpu/intel-display/fifo-underrun.rst create mode 100644 Documentation/gpu/intel-display/frontbuffer.rst create mode 100644 Documentation/gpu/intel-display/hotplug.rst create mode 100644 Documentation/gpu/intel-display/index.rst create mode 100644 Documentation/gpu/intel-display/plane.rst create mode 100644 Documentation/gpu/intel-display/psr.rst create mode 100644 Documentation/gpu/intel-display/vbt.rst diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst index 2e13e0ad7e88..20d2c454aa1d 100644 --- a/Documentation/gpu/drivers.rst +++ b/Documentation/gpu/drivers.rst @@ -8,6 +8,7 @@ GPU Driver Documentation amdgpu/index i915 imagination/index + intel-display/index mcde meson nouveau diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst index 2292e65f044c..7e79d4127aec 100644 --- a/Documentation/gpu/drm-kms.rst +++ b/Documentation/gpu/drm-kms.rst @@ -1,3 +1,6 @@ + +.. _drm-kms: + ========================= Kernel Mode Setting (KMS) ========================= diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index eba09c3ddce4..0c9d68758533 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -1,3 +1,6 @@ + +.. _drm/i915: + =========================== drm/i915 Intel GFX Driver =========================== @@ -7,6 +10,9 @@ models) integrated GFX chipsets with both Intel display and rendering blocks. This excludes a set of SoC platforms with an SGX rendering unit, those have basic support through the gma500 drm driver. +The display, or :ref:`drm-kms`, support for drm/i915 is provided by +:ref:`drm/intel-display`, and shared with :ref:`drm/xe `. + Core Driver Infrastructure ========================== @@ -64,200 +70,6 @@ Workarounds .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c :doc: Hardware workarounds -Display Hardware Handling -========================= - -This section covers everything related to the display hardware including -the mode setting infrastructure, plane, sprite and cursor handling and -display, output probing and related topics. - -Mode Setting Infrastructure ---------------------------- - -The i915 driver is thus far the only DRM driver which doesn't use the -common DRM helper code to implement mode setting sequences. Thus it has -its own tailor-made infrastructure for executing a display configuration -change. - -Frontbuffer Tracking --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c - :doc: frontbuffer tracking - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h - :internal: - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c - :internal: - -Display FIFO Underrun Reporting -------------------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c - :doc: fifo underrun handling - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c - :internal: - -Plane Configuration -------------------- - -This section covers plane configuration and composition with the primary -plane, sprites, cursors and overlays. This includes the infrastructure -to do atomic vsync'ed updates of all this state and also tightly coupled -topics like watermark setup and computation, framebuffer compression and -panel self refresh. - -Atomic Plane Helpers --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c - :doc: atomic plane helpers - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c - :internal: - -Asynchronous Page Flip ----------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c - :doc: asynchronous flip implementation - -Output Probing --------------- - -This section covers output probing and related infrastructure like the -hotplug interrupt storm detection and mitigation code. Note that the -i915 driver still uses most of the common DRM helper code for output -probing, so those sections fully apply. - -Hotplug -------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c - :doc: Hotplug - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c - :internal: - -High Definition Audio ---------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c - :doc: High Definition Audio over HDMI and Display Port - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c - :internal: - -.. kernel-doc:: include/drm/intel/i915_component.h - :internal: - -Intel HDMI LPE Audio Support ----------------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c - :doc: LPE Audio integration for HDMI or DP playback - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c - :internal: - -Panel Self Refresh PSR (PSR/SRD) --------------------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c - :doc: Panel Self Refresh (PSR/SRD) - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c - :internal: - -Frame Buffer Compression (FBC) ------------------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c - :doc: Frame Buffer Compression (FBC) - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c - :internal: - -Display Refresh Rate Switching (DRRS) -------------------------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c - :doc: Display Refresh Rate Switching (DRRS) - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c - :internal: - -DPIO ----- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c - :doc: DPIO - -DMC Firmware Support --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c - :doc: DMC Firmware Support - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c - :internal: - -DMC Flip Queue --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_flipq.c - :doc: DMC Flip Queue - -DMC wakelock support --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c - :doc: DMC wakelock support - -Video BIOS Table (VBT) ----------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c - :doc: Video BIOS Table (VBT) - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c - :internal: - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h - :internal: - -Display clocks --------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c - :doc: CDCLK / RAWCLK - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c - :internal: - -Display PLLs ------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c - :doc: Display PLLs - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c - :internal: - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h - :internal: - -Display State Buffer --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c - :doc: DSB - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c - :internal: - GT Programming ============== @@ -568,7 +380,7 @@ The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_ DMC --- -See `DMC Firmware Support`_ +See :ref:`drm/intel-display/dmc`. Tracing ======= diff --git a/Documentation/gpu/intel-display/async-flip.rst b/Documentation/gpu/intel-display/async-flip.rst new file mode 100644 index 000000000000..e4ae4012efc5 --- /dev/null +++ b/Documentation/gpu/intel-display/async-flip.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Asynchronous Page Flip +---------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c + :doc: asynchronous flip implementation diff --git a/Documentation/gpu/intel-display/audio.rst b/Documentation/gpu/intel-display/audio.rst new file mode 100644 index 000000000000..7d3c1b514b0e --- /dev/null +++ b/Documentation/gpu/intel-display/audio.rst @@ -0,0 +1,23 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +High Definition Audio +--------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c + :doc: High Definition Audio over HDMI and Display Port + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c + :internal: + +.. kernel-doc:: include/drm/intel/i915_component.h + :internal: + +Intel HDMI LPE Audio Support +---------------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c + :doc: LPE Audio integration for HDMI or DP playback + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c + :internal: diff --git a/Documentation/gpu/intel-display/cdclk.rst b/Documentation/gpu/intel-display/cdclk.rst new file mode 100644 index 000000000000..231b22a733e7 --- /dev/null +++ b/Documentation/gpu/intel-display/cdclk.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Display clocks +-------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c + :doc: CDCLK / RAWCLK + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c + :internal: diff --git a/Documentation/gpu/intel-display/dmc.rst b/Documentation/gpu/intel-display/dmc.rst new file mode 100644 index 000000000000..2fcdbd457d79 --- /dev/null +++ b/Documentation/gpu/intel-display/dmc.rst @@ -0,0 +1,26 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +.. _drm/intel-display/dmc: + +DMC Firmware Support +-------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c + :doc: DMC Firmware Support + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c + :internal: + + +DMC Flip Queue +-------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_flipq.c + :doc: DMC Flip Queue + +DMC wakelock support +-------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c + :doc: DMC wakelock support diff --git a/Documentation/gpu/intel-display/dpio.rst b/Documentation/gpu/intel-display/dpio.rst new file mode 100644 index 000000000000..32e6f299f256 --- /dev/null +++ b/Documentation/gpu/intel-display/dpio.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +DPIO +---- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c + :doc: DPIO diff --git a/Documentation/gpu/intel-display/dpll.rst b/Documentation/gpu/intel-display/dpll.rst new file mode 100644 index 000000000000..35e8168ccfb9 --- /dev/null +++ b/Documentation/gpu/intel-display/dpll.rst @@ -0,0 +1,14 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Display PLLs +------------ + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c + :doc: Display PLLs + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c + :internal: + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h + :internal: diff --git a/Documentation/gpu/intel-display/drrs.rst b/Documentation/gpu/intel-display/drrs.rst new file mode 100644 index 000000000000..adb413f300f1 --- /dev/null +++ b/Documentation/gpu/intel-display/drrs.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Display Refresh Rate Switching (DRRS) +------------------------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c + :doc: Display Refresh Rate Switching (DRRS) + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c + :internal: diff --git a/Documentation/gpu/intel-display/dsb.rst b/Documentation/gpu/intel-display/dsb.rst new file mode 100644 index 000000000000..cbd40b0a4e7b --- /dev/null +++ b/Documentation/gpu/intel-display/dsb.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Display State Buffer +-------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c + :doc: DSB + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c + :internal: diff --git a/Documentation/gpu/intel-display/fbc.rst b/Documentation/gpu/intel-display/fbc.rst new file mode 100644 index 000000000000..40f9d16bdebd --- /dev/null +++ b/Documentation/gpu/intel-display/fbc.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Frame Buffer Compression (FBC) +------------------------------ + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c + :doc: Frame Buffer Compression (FBC) + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c + :internal: diff --git a/Documentation/gpu/intel-display/fifo-underrun.rst b/Documentation/gpu/intel-display/fifo-underrun.rst new file mode 100644 index 000000000000..50731f3a1f03 --- /dev/null +++ b/Documentation/gpu/intel-display/fifo-underrun.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Display FIFO Underrun Reporting +------------------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c + :doc: fifo underrun handling + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c + :internal: diff --git a/Documentation/gpu/intel-display/frontbuffer.rst b/Documentation/gpu/intel-display/frontbuffer.rst new file mode 100644 index 000000000000..2a1bc63ba6b4 --- /dev/null +++ b/Documentation/gpu/intel-display/frontbuffer.rst @@ -0,0 +1,14 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Frontbuffer Tracking +-------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c + :doc: frontbuffer tracking + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c + :internal: diff --git a/Documentation/gpu/intel-display/hotplug.rst b/Documentation/gpu/intel-display/hotplug.rst new file mode 100644 index 000000000000..4cd9dd5ac8fc --- /dev/null +++ b/Documentation/gpu/intel-display/hotplug.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Hotplug +------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c + :doc: Hotplug + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c + :internal: diff --git a/Documentation/gpu/intel-display/index.rst b/Documentation/gpu/intel-display/index.rst new file mode 100644 index 000000000000..8d40363b8f90 --- /dev/null +++ b/Documentation/gpu/intel-display/index.rst @@ -0,0 +1,40 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +.. _drm/intel-display: + +==================== +Intel Display Driver +==================== + +The Intel display driver provides the display, or :ref:`drm-kms`, support for +both the :ref:`drm/xe ` and :ref:`drm/i915 ` Intel GPU +drivers. + +The source code currently resides under ``drivers/gpu/drm/i915/display`` due to +historical reasons, and it's compiled separately into both drm/xe and drm/i915 +kernel modules. + +The drm/xe and drm/i915 drivers are the "core" or "parent" drivers for display, +as they initialize and own the drm device, and pass that on to the display +driver. The display driver isn't an independent driver in that sense. + +.. toctree:: + :maxdepth: 1 + :caption: Detailed display topics + + async-flip + audio + cdclk + dmc + dpio + dpll + drrs + dsb + fbc + fifo-underrun + frontbuffer + hotplug + plane + psr + vbt diff --git a/Documentation/gpu/intel-display/plane.rst b/Documentation/gpu/intel-display/plane.rst new file mode 100644 index 000000000000..41cf6571aab0 --- /dev/null +++ b/Documentation/gpu/intel-display/plane.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Atomic Plane Helpers +-------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c + :doc: atomic plane helpers + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c + :internal: diff --git a/Documentation/gpu/intel-display/psr.rst b/Documentation/gpu/intel-display/psr.rst new file mode 100644 index 000000000000..134c905f500e --- /dev/null +++ b/Documentation/gpu/intel-display/psr.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Panel Self Refresh PSR (PSR/SRD) +-------------------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c + :doc: Panel Self Refresh (PSR/SRD) + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c + :internal: diff --git a/Documentation/gpu/intel-display/vbt.rst b/Documentation/gpu/intel-display/vbt.rst new file mode 100644 index 000000000000..bbc7ee183f1b --- /dev/null +++ b/Documentation/gpu/intel-display/vbt.rst @@ -0,0 +1,14 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Video BIOS Table (VBT) +---------------------- + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c + :doc: Video BIOS Table (VBT) + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c + :internal: + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h + :internal: diff --git a/Documentation/gpu/xe/index.rst b/Documentation/gpu/xe/index.rst index bc432c95d1a3..08f62217d4f6 100644 --- a/Documentation/gpu/xe/index.rst +++ b/Documentation/gpu/xe/index.rst @@ -1,5 +1,7 @@ .. SPDX-License-Identifier: (GPL-2.0+ OR MIT) +.. _drm/xe: + ======================= drm/xe Intel GFX Driver ======================= @@ -8,6 +10,9 @@ The drm/xe driver supports some future GFX cards with rendering, display, compute and media. Support for currently available platforms like TGL, ADL, DG2, etc is provided to prototype the driver. +The display, or :ref:`drm-kms`, support for drm/xe is provided by +:ref:`drm/intel-display`, and shared with :ref:`drm/i915 `. + .. toctree:: :titlesonly: From bd30515d208fb0d03befa647497243c55b1c11a8 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 8 May 2026 13:20:48 +0300 Subject: [PATCH 14/38] Documentation/gpu: use === for Intel display section heading underlines Prefer to use === instead of --- for top level section heading underlines to allow using the latter for sub-headings later. While at it, fix the underline lenghts where needed. Acked-by: Randy Dunlap Tested-by: Randy Dunlap Reviewed-by: Rodrigo Vivi Link: https://patch.msgid.link/f49968792220ca3ff24efde813550850340d092e.1778235406.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- Documentation/gpu/intel-display/async-flip.rst | 2 +- Documentation/gpu/intel-display/audio.rst | 4 ++-- Documentation/gpu/intel-display/cdclk.rst | 2 +- Documentation/gpu/intel-display/dmc.rst | 6 +++--- Documentation/gpu/intel-display/dpio.rst | 2 +- Documentation/gpu/intel-display/dpll.rst | 2 +- Documentation/gpu/intel-display/drrs.rst | 2 +- Documentation/gpu/intel-display/dsb.rst | 2 +- Documentation/gpu/intel-display/fbc.rst | 2 +- Documentation/gpu/intel-display/fifo-underrun.rst | 2 +- Documentation/gpu/intel-display/frontbuffer.rst | 2 +- Documentation/gpu/intel-display/hotplug.rst | 2 +- Documentation/gpu/intel-display/plane.rst | 2 +- Documentation/gpu/intel-display/psr.rst | 2 +- Documentation/gpu/intel-display/vbt.rst | 2 +- 15 files changed, 18 insertions(+), 18 deletions(-) diff --git a/Documentation/gpu/intel-display/async-flip.rst b/Documentation/gpu/intel-display/async-flip.rst index e4ae4012efc5..40f93e885bb7 100644 --- a/Documentation/gpu/intel-display/async-flip.rst +++ b/Documentation/gpu/intel-display/async-flip.rst @@ -2,7 +2,7 @@ .. Copyright © 2026 Intel Corporation Asynchronous Page Flip ----------------------- +====================== .. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c :doc: asynchronous flip implementation diff --git a/Documentation/gpu/intel-display/audio.rst b/Documentation/gpu/intel-display/audio.rst index 7d3c1b514b0e..eef95df75f8d 100644 --- a/Documentation/gpu/intel-display/audio.rst +++ b/Documentation/gpu/intel-display/audio.rst @@ -2,7 +2,7 @@ .. Copyright © 2026 Intel Corporation High Definition Audio ---------------------- +===================== .. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c :doc: High Definition Audio over HDMI and Display Port @@ -14,7 +14,7 @@ High Definition Audio :internal: Intel HDMI LPE Audio Support ----------------------------- +============================ .. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c :doc: LPE Audio integration for HDMI or DP playback diff --git a/Documentation/gpu/intel-display/cdclk.rst b/Documentation/gpu/intel-display/cdclk.rst index 231b22a733e7..a66d623b0ec9 100644 --- a/Documentation/gpu/intel-display/cdclk.rst +++ b/Documentation/gpu/intel-display/cdclk.rst @@ -2,7 +2,7 @@ .. Copyright © 2026 Intel Corporation Display clocks --------------- +============== .. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c :doc: CDCLK / RAWCLK diff --git a/Documentation/gpu/intel-display/dmc.rst b/Documentation/gpu/intel-display/dmc.rst index 2fcdbd457d79..4368da4c7048 100644 --- a/Documentation/gpu/intel-display/dmc.rst +++ b/Documentation/gpu/intel-display/dmc.rst @@ -4,7 +4,7 @@ .. _drm/intel-display/dmc: DMC Firmware Support --------------------- +==================== .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c :doc: DMC Firmware Support @@ -14,13 +14,13 @@ DMC Firmware Support DMC Flip Queue --------------------- +============== .. kernel-doc:: drivers/gpu/drm/i915/display/intel_flipq.c :doc: DMC Flip Queue DMC wakelock support --------------------- +==================== .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c :doc: DMC wakelock support diff --git a/Documentation/gpu/intel-display/dpio.rst b/Documentation/gpu/intel-display/dpio.rst index 32e6f299f256..84d92ac162f8 100644 --- a/Documentation/gpu/intel-display/dpio.rst +++ b/Documentation/gpu/intel-display/dpio.rst @@ -2,7 +2,7 @@ .. Copyright © 2026 Intel Corporation DPIO ----- +==== .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c :doc: DPIO diff --git a/Documentation/gpu/intel-display/dpll.rst b/Documentation/gpu/intel-display/dpll.rst index 35e8168ccfb9..c750352e0ae5 100644 --- a/Documentation/gpu/intel-display/dpll.rst +++ b/Documentation/gpu/intel-display/dpll.rst @@ -2,7 +2,7 @@ .. Copyright © 2026 Intel Corporation Display PLLs ------------- +============ .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c :doc: Display PLLs diff --git a/Documentation/gpu/intel-display/drrs.rst b/Documentation/gpu/intel-display/drrs.rst index adb413f300f1..a5aaba63d6b9 100644 --- a/Documentation/gpu/intel-display/drrs.rst +++ b/Documentation/gpu/intel-display/drrs.rst @@ -2,7 +2,7 @@ .. Copyright © 2026 Intel Corporation Display Refresh Rate Switching (DRRS) -------------------------------------- +===================================== .. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c :doc: Display Refresh Rate Switching (DRRS) diff --git a/Documentation/gpu/intel-display/dsb.rst b/Documentation/gpu/intel-display/dsb.rst index cbd40b0a4e7b..857aca59995a 100644 --- a/Documentation/gpu/intel-display/dsb.rst +++ b/Documentation/gpu/intel-display/dsb.rst @@ -2,7 +2,7 @@ .. Copyright © 2026 Intel Corporation Display State Buffer --------------------- +==================== .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c :doc: DSB diff --git a/Documentation/gpu/intel-display/fbc.rst b/Documentation/gpu/intel-display/fbc.rst index 40f9d16bdebd..de9e19021f50 100644 --- a/Documentation/gpu/intel-display/fbc.rst +++ b/Documentation/gpu/intel-display/fbc.rst @@ -2,7 +2,7 @@ .. Copyright © 2026 Intel Corporation Frame Buffer Compression (FBC) ------------------------------- +============================== .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c :doc: Frame Buffer Compression (FBC) diff --git a/Documentation/gpu/intel-display/fifo-underrun.rst b/Documentation/gpu/intel-display/fifo-underrun.rst index 50731f3a1f03..5d8f01921506 100644 --- a/Documentation/gpu/intel-display/fifo-underrun.rst +++ b/Documentation/gpu/intel-display/fifo-underrun.rst @@ -2,7 +2,7 @@ .. Copyright © 2026 Intel Corporation Display FIFO Underrun Reporting -------------------------------- +=============================== .. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c :doc: fifo underrun handling diff --git a/Documentation/gpu/intel-display/frontbuffer.rst b/Documentation/gpu/intel-display/frontbuffer.rst index 2a1bc63ba6b4..7ae38e0827bf 100644 --- a/Documentation/gpu/intel-display/frontbuffer.rst +++ b/Documentation/gpu/intel-display/frontbuffer.rst @@ -2,7 +2,7 @@ .. Copyright © 2026 Intel Corporation Frontbuffer Tracking --------------------- +==================== .. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c :doc: frontbuffer tracking diff --git a/Documentation/gpu/intel-display/hotplug.rst b/Documentation/gpu/intel-display/hotplug.rst index 4cd9dd5ac8fc..f33bc0087c27 100644 --- a/Documentation/gpu/intel-display/hotplug.rst +++ b/Documentation/gpu/intel-display/hotplug.rst @@ -2,7 +2,7 @@ .. Copyright © 2026 Intel Corporation Hotplug -------- +======= .. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c :doc: Hotplug diff --git a/Documentation/gpu/intel-display/plane.rst b/Documentation/gpu/intel-display/plane.rst index 41cf6571aab0..59932a82051b 100644 --- a/Documentation/gpu/intel-display/plane.rst +++ b/Documentation/gpu/intel-display/plane.rst @@ -2,7 +2,7 @@ .. Copyright © 2026 Intel Corporation Atomic Plane Helpers --------------------- +==================== .. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c :doc: atomic plane helpers diff --git a/Documentation/gpu/intel-display/psr.rst b/Documentation/gpu/intel-display/psr.rst index 134c905f500e..63e56abcdd56 100644 --- a/Documentation/gpu/intel-display/psr.rst +++ b/Documentation/gpu/intel-display/psr.rst @@ -2,7 +2,7 @@ .. Copyright © 2026 Intel Corporation Panel Self Refresh PSR (PSR/SRD) --------------------------------- +================================ .. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c :doc: Panel Self Refresh (PSR/SRD) diff --git a/Documentation/gpu/intel-display/vbt.rst b/Documentation/gpu/intel-display/vbt.rst index bbc7ee183f1b..be69f7fd7b39 100644 --- a/Documentation/gpu/intel-display/vbt.rst +++ b/Documentation/gpu/intel-display/vbt.rst @@ -2,7 +2,7 @@ .. Copyright © 2026 Intel Corporation Video BIOS Table (VBT) ----------------------- +====================== .. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c :doc: Video BIOS Table (VBT) From 158fcf1b3994b661f6bf8f61d347ff9d7fc104d8 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 8 May 2026 13:20:49 +0300 Subject: [PATCH 15/38] Documentation/gpu: add remaining DOC: comments to Intel display documentation Not all of the overview DOC: comments in the display driver are incorporated into the documentation. Add the missing ones, including some function documentation. Reviewed-by: Rodrigo Vivi Link: https://patch.msgid.link/589c46cf9a46763f4fbb7e1756656e6d71ba1431.1778235406.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- Documentation/gpu/intel-display/atomic.rst | 11 +++++++++++ Documentation/gpu/intel-display/casf.rst | 8 ++++++++ Documentation/gpu/intel-display/cmtg.rst | 8 ++++++++ Documentation/gpu/intel-display/index.rst | 4 ++++ Documentation/gpu/intel-display/snps-phy.rst | 8 ++++++++ 5 files changed, 39 insertions(+) create mode 100644 Documentation/gpu/intel-display/atomic.rst create mode 100644 Documentation/gpu/intel-display/casf.rst create mode 100644 Documentation/gpu/intel-display/cmtg.rst create mode 100644 Documentation/gpu/intel-display/snps-phy.rst diff --git a/Documentation/gpu/intel-display/atomic.rst b/Documentation/gpu/intel-display/atomic.rst new file mode 100644 index 000000000000..43a473181e7a --- /dev/null +++ b/Documentation/gpu/intel-display/atomic.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Atomic Modeset Support +====================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic.c + :doc: atomic modeset support + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic.c + :internal: diff --git a/Documentation/gpu/intel-display/casf.rst b/Documentation/gpu/intel-display/casf.rst new file mode 100644 index 000000000000..406778ccd94c --- /dev/null +++ b/Documentation/gpu/intel-display/casf.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Content Adaptive Sharpness Filter (CASF) +======================================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_casf.c + :doc: Content Adaptive Sharpness Filter (CASF) diff --git a/Documentation/gpu/intel-display/cmtg.rst b/Documentation/gpu/intel-display/cmtg.rst new file mode 100644 index 000000000000..04edd0bd165d --- /dev/null +++ b/Documentation/gpu/intel-display/cmtg.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Common Primary Timing Generator (CMTG) +====================================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cmtg.c + :doc: Common Primary Timing Generator (CMTG) diff --git a/Documentation/gpu/intel-display/index.rst b/Documentation/gpu/intel-display/index.rst index 8d40363b8f90..01c3d1e576b7 100644 --- a/Documentation/gpu/intel-display/index.rst +++ b/Documentation/gpu/intel-display/index.rst @@ -24,8 +24,11 @@ driver. The display driver isn't an independent driver in that sense. :caption: Detailed display topics async-flip + atomic audio + casf cdclk + cmtg dmc dpio dpll @@ -37,4 +40,5 @@ driver. The display driver isn't an independent driver in that sense. hotplug plane psr + snps-phy vbt diff --git a/Documentation/gpu/intel-display/snps-phy.rst b/Documentation/gpu/intel-display/snps-phy.rst new file mode 100644 index 000000000000..c9e333fa7f62 --- /dev/null +++ b/Documentation/gpu/intel-display/snps-phy.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Synopsis PHY support +==================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_snps_phy.c + :doc: Synopsis PHY support From 38e10ddae6f8d42a2e8437fcd25a1cac51106c64 Mon Sep 17 00:00:00 2001 From: Chaitanya Kumar Borah Date: Tue, 5 May 2026 14:39:20 +0530 Subject: [PATCH 16/38] drm/i915/dp: Fix VSC dynamic range signaling for RGB formats For RGB, set dynamic_range to CTA or VESA based on crtc_state->limited_color_range so sinks apply correct quantization. YCbCr remains limited (CTA) range. (DP v1.4, Table 5-1) v2: - Added Reported-by and Tested-by tags v3: - Add back YCbCr comment(Suraj) Cc: stable@vger.kernel.org #v5.8+ Reported-by: DeepChirp Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/15874 Tested-by: DeepChirp Fixes: 9799c4c3b76e ("drm/i915/dp: Add compute routine for DP VSC SDP") Assisted-by: GitHub-Copilot:GPT-5.4 Signed-off-by: Chaitanya Kumar Borah Reviewed-by: Suraj Kandpal Signed-off-by: Suraj Kandpal Link: https://patch.msgid.link/20260505090920.2479112-1-chaitanya.kumar.borah@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 408846fb98f0..5bdeed14267e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3159,8 +3159,13 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc drm_WARN_ON(display->drm, vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); - /* all YCbCr are always limited range */ - vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; + /* All YCbCr formats are always limited range. */ + if (vsc->pixelformat == DP_PIXELFORMAT_RGB) + vsc->dynamic_range = crtc_state->limited_color_range ? + DP_DYNAMIC_RANGE_CTA : DP_DYNAMIC_RANGE_VESA; + else + vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; + vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; } From c2b4b6075d5155c83889bdf7b8c509df9b5b47ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:11 +0300 Subject: [PATCH 17/38] drm/i915: Introduce intel_parent_fb_pin_get_map() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce the "fb_pin" parent interface, as the first trivial step move the *_get_map() stuff there. The whole "fb_pin" as an interface might not really make sense, and perhaps this (and other stuff) should just be collected into some kind of "bo" interface. But let's go with "fb_pin" for now to match where things are implemented, and possibly restructure it later. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-2-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_fb_pin.h | 1 - drivers/gpu/drm/i915/display/intel_fbdev.c | 7 +++++-- drivers/gpu/drm/i915/display/intel_fbdev.h | 4 ++-- drivers/gpu/drm/i915/display/intel_parent.c | 7 +++++++ drivers/gpu/drm/i915/display/intel_parent.h | 5 +++++ drivers/gpu/drm/i915/display/intel_plane.c | 4 ++-- drivers/gpu/drm/i915/i915_driver.c | 2 ++ drivers/gpu/drm/i915/i915_fb_pin.c | 8 +++++++- drivers/gpu/drm/i915/i915_fb_pin.h | 9 +++++++++ drivers/gpu/drm/xe/display/xe_display.c | 2 ++ drivers/gpu/drm/xe/display/xe_fb_pin.c | 8 +++++++- drivers/gpu/drm/xe/display/xe_fb_pin.h | 9 +++++++++ include/drm/intel/display_parent_interface.h | 8 ++++++++ 13 files changed, 65 insertions(+), 9 deletions(-) create mode 100644 drivers/gpu/drm/i915/i915_fb_pin.h create mode 100644 drivers/gpu/drm/xe/display/xe_fb_pin.h diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h b/drivers/gpu/drm/i915/display/intel_fb_pin.h index 5825503c38ea..805e23067004 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.h +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h @@ -35,6 +35,5 @@ void intel_fb_unpin_vma(struct i915_vma *vma, int fence_id); int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, const struct intel_plane_state *old_plane_state); void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state); -void intel_fb_get_map(struct i915_vma *vma, struct iosys_map *map); #endif diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 9ab0ac49abb7..ce4082da30e8 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -55,6 +55,7 @@ #include "intel_fb_pin.h" #include "intel_fbdev.h" #include "intel_frontbuffer.h" +#include "intel_parent.h" #include "intel_plane.h" struct intel_fbdev { @@ -563,7 +564,9 @@ struct i915_vma *intel_fbdev_vma_pointer(struct intel_fbdev *fbdev) return fbdev ? fbdev->vma : NULL; } -void intel_fbdev_get_map(struct intel_fbdev *fbdev, struct iosys_map *map) +void intel_fbdev_get_map(struct intel_display *display, struct iosys_map *map) { - intel_fb_get_map(fbdev->vma, map); + struct intel_fbdev *fbdev = display->fbdev.fbdev; + + intel_parent_fb_pin_get_map(display, fbdev->vma, map); } diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.h b/drivers/gpu/drm/i915/display/intel_fbdev.h index 150cc5f45bb3..edaf5d16a456 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.h +++ b/drivers/gpu/drm/i915/display/intel_fbdev.h @@ -23,7 +23,7 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, void intel_fbdev_setup(struct intel_display *display); struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbdev); struct i915_vma *intel_fbdev_vma_pointer(struct intel_fbdev *fbdev); -void intel_fbdev_get_map(struct intel_fbdev *fbdev, struct iosys_map *map); +void intel_fbdev_get_map(struct intel_display *display, struct iosys_map *map); #else #define INTEL_FBDEV_DRIVER_OPS \ .fbdev_probe = NULL @@ -40,7 +40,7 @@ static inline struct i915_vma *intel_fbdev_vma_pointer(struct intel_fbdev *fbdev return NULL; } -static inline void intel_fbdev_get_map(struct intel_fbdev *fbdev, struct iosys_map *map) +static inline void intel_fbdev_get_map(struct intel_display *display, struct iosys_map *map) { } #endif diff --git a/drivers/gpu/drm/i915/display/intel_parent.c b/drivers/gpu/drm/i915/display/intel_parent.c index 67b21a42d354..070cc60f49b3 100644 --- a/drivers/gpu/drm/i915/display/intel_parent.c +++ b/drivers/gpu/drm/i915/display/intel_parent.c @@ -52,6 +52,13 @@ void intel_parent_dpt_resume(struct intel_display *display, struct intel_dpt *dp display->parent->dpt->resume(dpt); } +/* fb_pin */ +void intel_parent_fb_pin_get_map(struct intel_display *display, + struct i915_vma *vma, struct iosys_map *map) +{ + return display->parent->fb_pin->get_map(vma, map); +} + /* frontbuffer */ struct intel_frontbuffer *intel_parent_frontbuffer_get(struct intel_display *display, struct drm_gem_object *obj) { diff --git a/drivers/gpu/drm/i915/display/intel_parent.h b/drivers/gpu/drm/i915/display/intel_parent.h index 5f0c835b9416..2b9e829e7f47 100644 --- a/drivers/gpu/drm/i915/display/intel_parent.h +++ b/drivers/gpu/drm/i915/display/intel_parent.h @@ -18,6 +18,7 @@ struct intel_frontbuffer; struct intel_hdcp_gsc_context; struct intel_panic; struct intel_stolen_node; +struct iosys_map; /* dpt */ struct intel_dpt *intel_parent_dpt_create(struct intel_display *display, @@ -26,6 +27,10 @@ void intel_parent_dpt_destroy(struct intel_display *display, struct intel_dpt *d void intel_parent_dpt_suspend(struct intel_display *display, struct intel_dpt *dpt); void intel_parent_dpt_resume(struct intel_display *display, struct intel_dpt *dpt); +/* fb_pin */ +void intel_parent_fb_pin_get_map(struct intel_display *display, + struct i915_vma *vma, struct iosys_map *map); + /* frontbuffer */ struct intel_frontbuffer *intel_parent_frontbuffer_get(struct intel_display *display, struct drm_gem_object *obj); void intel_parent_frontbuffer_ref(struct intel_display *display, struct intel_frontbuffer *front); diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c index c2b58d3b9c23..e50e1a15410a 100644 --- a/drivers/gpu/drm/i915/display/intel_plane.c +++ b/drivers/gpu/drm/i915/display/intel_plane.c @@ -1404,7 +1404,7 @@ static void intel_panic_flush(struct drm_plane *_plane) if (fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) { struct iosys_map map; - intel_fbdev_get_map(display->fbdev.fbdev, &map); + intel_fbdev_get_map(display, &map); drm_clflush_virt_range(map.vaddr, fb->base.pitches[0] * fb->base.height); return; } @@ -1462,7 +1462,7 @@ static int intel_get_scanout_buffer(struct drm_plane *plane, return -ENODEV; if (fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) { - intel_fbdev_get_map(display->fbdev.fbdev, &sb->map[0]); + intel_fbdev_get_map(display, &sb->map[0]); } else { int ret; /* Can't disable tiling if DPT is in use */ diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index a4bd4f8e18b2..f06b2e8cf7d4 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -99,6 +99,7 @@ #include "i915_drv.h" #include "i915_dsb_buffer.h" #include "i915_edram.h" +#include "i915_fb_pin.h" #include "i915_file_private.h" #include "i915_getparam.h" #include "i915_gmch.h" @@ -768,6 +769,7 @@ static const struct intel_display_parent_interface parent = { .bo = &i915_display_bo_interface, .dpt = &i915_display_dpt_interface, .dsb = &i915_display_dsb_interface, + .fb_pin = &i915_display_fb_pin_interface, .frontbuffer = &i915_display_frontbuffer_interface, .hdcp = &i915_display_hdcp_interface, .initial_plane = &i915_display_initial_plane_interface, diff --git a/drivers/gpu/drm/i915/i915_fb_pin.c b/drivers/gpu/drm/i915/i915_fb_pin.c index b0e121462ca3..b800b55530a5 100644 --- a/drivers/gpu/drm/i915/i915_fb_pin.c +++ b/drivers/gpu/drm/i915/i915_fb_pin.c @@ -8,6 +8,7 @@ */ #include +#include #include "display/intel_display_core.h" #include "display/intel_display_types.h" @@ -18,6 +19,7 @@ #include "gem/i915_gem_domain.h" #include "gem/i915_gem_object.h" +#include "i915_fb_pin.h" #include "i915_dpt.h" #include "i915_drv.h" #include "i915_vma.h" @@ -352,7 +354,11 @@ void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) } } -void intel_fb_get_map(struct i915_vma *vma, struct iosys_map *map) +static void i915_fb_pin_get_map(struct i915_vma *vma, struct iosys_map *map) { iosys_map_set_vaddr_iomem(map, i915_vma_get_iomap(vma)); } + +const struct intel_display_fb_pin_interface i915_display_fb_pin_interface = { + .get_map = i915_fb_pin_get_map, +}; diff --git a/drivers/gpu/drm/i915/i915_fb_pin.h b/drivers/gpu/drm/i915/i915_fb_pin.h new file mode 100644 index 000000000000..18c6c0b61ab8 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_fb_pin.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2026 Intel Corporation */ + +#ifndef __I915_FB_PIN_H__ +#define __I915_FB_PIN_H__ + +extern const struct intel_display_fb_pin_interface i915_display_fb_pin_interface; + +#endif /* __I915_FB_PIN_H__ */ diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c index 0747044f7c2a..aa73023b7398 100644 --- a/drivers/gpu/drm/xe/display/xe_display.c +++ b/drivers/gpu/drm/xe/display/xe_display.c @@ -40,6 +40,7 @@ #include "xe_display_pcode.h" #include "xe_display_rpm.h" #include "xe_dsb_buffer.h" +#include "xe_fb_pin.h" #include "xe_frontbuffer.h" #include "xe_hdcp_gsc.h" #include "xe_initial_plane.h" @@ -553,6 +554,7 @@ static bool has_auxccs(struct drm_device *drm) static const struct intel_display_parent_interface parent = { .bo = &xe_display_bo_interface, .dsb = &xe_display_dsb_interface, + .fb_pin = &xe_display_fb_pin_interface, .frontbuffer = &xe_display_frontbuffer_interface, .hdcp = &xe_display_hdcp_interface, .initial_plane = &xe_display_initial_plane_interface, diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index f1082382d759..0da1fbcb82d5 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -3,6 +3,7 @@ * Copyright © 2021 Intel Corporation */ +#include #include #include "intel_display_core.h" @@ -13,6 +14,7 @@ #include "xe_bo.h" #include "xe_device.h" #include "xe_display_vma.h" +#include "xe_fb_pin.h" #include "xe_ggtt.h" #include "xe_pm.h" #include "xe_vram_types.h" @@ -505,7 +507,11 @@ void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) old_plane_state->ggtt_vma = NULL; } -void intel_fb_get_map(struct i915_vma *vma, struct iosys_map *map) +static void xe_fb_pin_get_map(struct i915_vma *vma, struct iosys_map *map) { *map = vma->bo->vmap; } + +const struct intel_display_fb_pin_interface xe_display_fb_pin_interface = { + .get_map = xe_fb_pin_get_map, +}; diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.h b/drivers/gpu/drm/xe/display/xe_fb_pin.h new file mode 100644 index 000000000000..8a42d4009f5d --- /dev/null +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2026 Intel Corporation */ + +#ifndef __XE_FB_PIN_H__ +#define __XE_FB_PIN_H__ + +extern const struct intel_display_fb_pin_interface xe_display_fb_pin_interface; + +#endif /* __XE_FB_PIN_H__ */ diff --git a/include/drm/intel/display_parent_interface.h b/include/drm/intel/display_parent_interface.h index 270dc028bec2..ee2e9572bfca 100644 --- a/include/drm/intel/display_parent_interface.h +++ b/include/drm/intel/display_parent_interface.h @@ -24,6 +24,7 @@ struct intel_hdcp_gsc_context; struct intel_initial_plane_config; struct intel_panic; struct intel_stolen_node; +struct iosys_map; struct ref_tracker; struct seq_file; struct vm_area_struct; @@ -69,6 +70,10 @@ struct intel_display_dsb_interface { void (*flush_map)(struct intel_dsb_buffer *dsb_buf); }; +struct intel_display_fb_pin_interface { + void (*get_map)(struct i915_vma *vma, struct iosys_map *map); +}; + struct intel_display_frontbuffer_interface { struct intel_frontbuffer *(*get)(struct drm_gem_object *obj); void (*ref)(struct intel_frontbuffer *front); @@ -211,6 +216,9 @@ struct intel_display_parent_interface { /** @dsb: DSB buffer interface */ const struct intel_display_dsb_interface *dsb; + /** @fb_pin: Framebuffer pin interface */ + const struct intel_display_fb_pin_interface *fb_pin; + /** @frontbuffer: Frontbuffer interface */ const struct intel_display_frontbuffer_interface *frontbuffer; From 65585c16d9d9e9b96341059f8be497c5f9b8c019 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:12 +0300 Subject: [PATCH 18/38] drm/i915: Move intel_fb_pin_params to the parent interface MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit strut intel_fb_pin_params will be an important part of the fb_pin interface, so move the definition to the parent interface file. Or maybe we should have a separate header for this kind of stuff since the users of the parent interface will need the struct definition but not the parent interface vfunc struct definitions? Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-3-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_fb_pin.h | 12 +----------- drivers/gpu/drm/i915/display/intel_fbdev.c | 1 + include/drm/intel/display_parent_interface.h | 12 ++++++++++++ 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h b/drivers/gpu/drm/i915/display/intel_fb_pin.h index 805e23067004..84530f20d7d1 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.h +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h @@ -10,21 +10,11 @@ struct drm_gem_object; struct i915_vma; +struct intel_fb_pin_params; struct intel_plane_state; struct i915_gtt_view; struct iosys_map; -struct intel_fb_pin_params { - const struct i915_gtt_view *view; - unsigned int alignment; - unsigned int phys_alignment; - unsigned int vtd_guard; - bool needs_cpu_lmem_access; - bool needs_low_address; - bool needs_physical; - bool needs_fence; -}; - struct i915_vma * intel_fb_pin_to_ggtt(struct drm_gem_object *obj, const struct intel_fb_pin_params *pin_params, diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index ce4082da30e8..aa2701795caa 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -38,6 +38,7 @@ #include #include +#include #include #include #include diff --git a/include/drm/intel/display_parent_interface.h b/include/drm/intel/display_parent_interface.h index ee2e9572bfca..b363d6a85dfe 100644 --- a/include/drm/intel/display_parent_interface.h +++ b/include/drm/intel/display_parent_interface.h @@ -16,6 +16,7 @@ struct drm_mode_fb_cmd2; struct drm_plane_state; struct drm_scanout_buffer; struct fb_info; +struct i915_gtt_view; struct i915_vma; struct intel_dpt; struct intel_dsb_buffer; @@ -29,6 +30,17 @@ struct ref_tracker; struct seq_file; struct vm_area_struct; +struct intel_fb_pin_params { + const struct i915_gtt_view *view; + unsigned int alignment; + unsigned int phys_alignment; + unsigned int vtd_guard; + bool needs_cpu_lmem_access; + bool needs_low_address; + bool needs_physical; + bool needs_fence; +}; + /* Keep struct definitions sorted */ struct intel_display_bo_interface { From ef2b2e7c10ff6a1d077fda977b01f1802a1d5415 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:13 +0300 Subject: [PATCH 19/38] drm/i915: Move the i915_dpt_offset()==0 assert MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the i915_dpt_offset() check into the lower level intel_fb_pin_to_dpt() function. Clears out some of the unnecessary junk from the higher level code, making it easier to introduce the new fb_pin parent interface. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-4-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/i915_fb_pin.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_fb_pin.c b/drivers/gpu/drm/i915/i915_fb_pin.c index b800b55530a5..400ad8768c11 100644 --- a/drivers/gpu/drm/i915/i915_fb_pin.c +++ b/drivers/gpu/drm/i915/i915_fb_pin.c @@ -101,6 +101,12 @@ intel_fb_pin_to_dpt(struct drm_gem_object *_obj, struct intel_dpt *dpt, i915_gem_object_flush_if_display(obj); i915_vma_get(vma); + + /* + * The DPT object contains only one vma, and there is no VT-d + * guard, so the VMA's offset within the DPT is always 0. + */ + drm_WARN_ON(&i915->drm, i915_dpt_offset(vma)); err: atomic_dec(&i915->pending_fb_pin); @@ -255,7 +261,6 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, const struct intel_plane_state *old_plane_state) { struct intel_display *display = to_intel_display(plane_state); - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); @@ -304,12 +309,6 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, plane_state->dpt_vma = vma; WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma); - - /* - * The DPT object contains only one vma, and there is no VT-d - * guard, so the VMA's offset within the DPT is always 0. - */ - drm_WARN_ON(&i915->drm, i915_dpt_offset(plane_state->dpt_vma)); } /* From 57aa886e99278bb3edc0bdd4de80321b0efe14d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:14 +0300 Subject: [PATCH 20/38] drm/i915: Reorganize intel_plane_pin_fb() a bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move most of the plane state stuff out from the inner parts of intel_plane_pin_fb(). The plan is to take those inner parts and abstract them into the new fb_pin parent interface, and we don't want any plane_state stuff there. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-5-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/i915_fb_pin.c | 67 +++++++++++++++--------------- 1 file changed, 33 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_fb_pin.c b/drivers/gpu/drm/i915/i915_fb_pin.c index 400ad8768c11..bc2e185b4573 100644 --- a/drivers/gpu/drm/i915/i915_fb_pin.c +++ b/drivers/gpu/drm/i915/i915_fb_pin.c @@ -264,7 +264,10 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); - struct i915_vma *vma; + struct i915_vma *ggtt_vma = NULL; + struct i915_vma *dpt_vma = NULL; + int fence_id = -1; + u32 offset; if (!intel_fb_uses_dpt(&fb->base)) { struct intel_fb_pin_params pin_params = { @@ -277,15 +280,25 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, .needs_physical = intel_plane_needs_physical(plane), .needs_fence = intel_plane_needs_fence(display), }; - int fence_id = -1; - vma = intel_fb_pin_to_ggtt(intel_fb_bo(&fb->base), &pin_params, - intel_plane_uses_fence(plane_state) ? &fence_id : NULL); - if (IS_ERR(vma)) - return PTR_ERR(vma); + ggtt_vma = intel_fb_pin_to_ggtt(intel_fb_bo(&fb->base), &pin_params, + intel_plane_uses_fence(plane_state) ? &fence_id : NULL); + if (IS_ERR(ggtt_vma)) + return PTR_ERR(ggtt_vma); - plane_state->ggtt_vma = vma; - plane_state->fence_id = fence_id; + /* + * Pre-populate the dma address before we enter the vblank + * evade critical section as i915_gem_object_get_dma_address() + * will trigger might_sleep() even if it won't actually sleep, + * which is the case when the fb has already been pinned. + */ + if (intel_plane_needs_physical(plane)) { + struct drm_i915_gem_object *obj = to_intel_bo(intel_fb_bo(&fb->base)); + + offset = i915_gem_object_get_dma_address(obj, 0); + } else { + offset = i915_ggtt_offset(ggtt_vma); + } } else { struct intel_fb_pin_params pin_params = { .view = &plane_state->view.gtt, @@ -293,39 +306,25 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, .needs_cpu_lmem_access = intel_fb_needs_cpu_access(&fb->base), }; - vma = i915_dpt_pin_to_ggtt(fb->dpt, pin_params.alignment / 512); - if (IS_ERR(vma)) - return PTR_ERR(vma); + ggtt_vma = i915_dpt_pin_to_ggtt(fb->dpt, pin_params.alignment / 512); + if (IS_ERR(ggtt_vma)) + return PTR_ERR(ggtt_vma); - plane_state->ggtt_vma = vma; - - vma = intel_fb_pin_to_dpt(intel_fb_bo(&fb->base), fb->dpt, &pin_params); - if (IS_ERR(vma)) { + dpt_vma = intel_fb_pin_to_dpt(intel_fb_bo(&fb->base), fb->dpt, &pin_params); + if (IS_ERR(dpt_vma)) { i915_dpt_unpin_from_ggtt(fb->dpt); - plane_state->ggtt_vma = NULL; - return PTR_ERR(vma); + return PTR_ERR(dpt_vma); } - plane_state->dpt_vma = vma; + WARN_ON(ggtt_vma == dpt_vma); - WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma); + offset = i915_ggtt_offset(ggtt_vma); } - /* - * Pre-populate the dma address before we enter the vblank - * evade critical section as i915_gem_object_get_dma_address() - * will trigger might_sleep() even if it won't actually sleep, - * which is the case when the fb has already been pinned. - */ - if (intel_plane_needs_physical(plane)) { - struct drm_i915_gem_object *obj = to_intel_bo(intel_fb_bo(&fb->base)); - - plane_state->surf = i915_gem_object_get_dma_address(obj, 0) + - plane->surf_offset(plane_state); - } else { - plane_state->surf = i915_ggtt_offset(plane_state->ggtt_vma) + - plane->surf_offset(plane_state); - } + plane_state->dpt_vma = dpt_vma; + plane_state->ggtt_vma = ggtt_vma; + plane_state->fence_id = fence_id; + plane_state->surf = offset + plane->surf_offset(plane_state); return 0; } From a8425a9100e3e73450d013741fa24c01a1c66bee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:15 +0300 Subject: [PATCH 21/38] drm/i915: Introduce i915_fb_pin_dpt_(un)pin() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extract the inner DPT parts of intel_plane_(un)pin() into the i915_fb_pin_dpt_(un)pin(). These will become part of the new fb_pin parent interface. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-6-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/i915_fb_pin.c | 76 ++++++++++++++++++++++-------- 1 file changed, 56 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_fb_pin.c b/drivers/gpu/drm/i915/i915_fb_pin.c index bc2e185b4573..0019f570d843 100644 --- a/drivers/gpu/drm/i915/i915_fb_pin.c +++ b/drivers/gpu/drm/i915/i915_fb_pin.c @@ -257,6 +257,49 @@ intel_plane_fb_vtd_guard(const struct intel_plane_state *plane_state) plane_state->hw.rotation); } +static int i915_fb_pin_dpt_pin(struct drm_gem_object *obj, struct intel_dpt *dpt, + const struct intel_fb_pin_params *pin_params, + struct i915_vma **out_dpt_vma, + struct i915_vma **out_ggtt_vma, + u32 *out_offset) +{ + struct i915_vma *ggtt_vma, *dpt_vma; + + WARN_ON(!dpt); + + ggtt_vma = i915_dpt_pin_to_ggtt(dpt, pin_params->alignment / 512); + if (IS_ERR(ggtt_vma)) + return PTR_ERR(ggtt_vma); + + dpt_vma = intel_fb_pin_to_dpt(obj, dpt, pin_params); + if (IS_ERR(dpt_vma)) { + i915_dpt_unpin_from_ggtt(dpt); + return PTR_ERR(dpt_vma); + } + + drm_WARN_ON(obj->dev, ggtt_vma == dpt_vma); + + *out_ggtt_vma = ggtt_vma; + *out_dpt_vma = dpt_vma; + + *out_offset = i915_ggtt_offset(ggtt_vma); + + return 0; +} + +static void i915_fb_pin_dpt_unpin(struct intel_dpt *dpt, + struct i915_vma *dpt_vma, + struct i915_vma *ggtt_vma) +{ + WARN_ON(!dpt); + WARN_ON(!!dpt_vma != !!ggtt_vma); + + if (dpt_vma) + intel_fb_unpin_vma(dpt_vma, -1); + if (ggtt_vma) + i915_dpt_unpin_from_ggtt(dpt); +} + int intel_plane_pin_fb(struct intel_plane_state *plane_state, const struct intel_plane_state *old_plane_state) { @@ -268,6 +311,7 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, struct i915_vma *dpt_vma = NULL; int fence_id = -1; u32 offset; + int ret; if (!intel_fb_uses_dpt(&fb->base)) { struct intel_fb_pin_params pin_params = { @@ -306,19 +350,11 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, .needs_cpu_lmem_access = intel_fb_needs_cpu_access(&fb->base), }; - ggtt_vma = i915_dpt_pin_to_ggtt(fb->dpt, pin_params.alignment / 512); - if (IS_ERR(ggtt_vma)) - return PTR_ERR(ggtt_vma); - - dpt_vma = intel_fb_pin_to_dpt(intel_fb_bo(&fb->base), fb->dpt, &pin_params); - if (IS_ERR(dpt_vma)) { - i915_dpt_unpin_from_ggtt(fb->dpt); - return PTR_ERR(dpt_vma); - } - - WARN_ON(ggtt_vma == dpt_vma); - - offset = i915_ggtt_offset(ggtt_vma); + ret = i915_fb_pin_dpt_pin(intel_fb_bo(&fb->base), fb->dpt, + &pin_params, &dpt_vma, + &ggtt_vma, &offset); + if (ret) + return ret; } plane_state->dpt_vma = dpt_vma; @@ -333,22 +369,22 @@ void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) { const struct intel_framebuffer *fb = to_intel_framebuffer(old_plane_state->hw.fb); - struct i915_vma *vma; if (!intel_fb_uses_dpt(&fb->base)) { + struct i915_vma *vma; + vma = fetch_and_zero(&old_plane_state->ggtt_vma); if (vma) { intel_fb_unpin_vma(vma, old_plane_state->fence_id); old_plane_state->fence_id = -1; } } else { - vma = fetch_and_zero(&old_plane_state->dpt_vma); - if (vma) - intel_fb_unpin_vma(vma, -1); + i915_fb_pin_dpt_unpin(fb->dpt, + old_plane_state->dpt_vma, + old_plane_state->ggtt_vma); - vma = fetch_and_zero(&old_plane_state->ggtt_vma); - if (vma) - i915_dpt_unpin_from_ggtt(fb->dpt); + old_plane_state->dpt_vma = NULL; + old_plane_state->ggtt_vma = NULL; } } From da5c2fc64eb55c38ab42fc653f70316bf3e66f4c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:16 +0300 Subject: [PATCH 22/38] drm/i915: Introduce i915_fb_pin_ggtt_(un)pin() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extract the inner DPT parts of intel_plane_(un)pin() into the i915_fb_pin_ggtt_(un)pin(). These will become part of the new fb_pin parent interface. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-7-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/i915_fb_pin.c | 68 +++++++++++++++++++----------- 1 file changed, 44 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_fb_pin.c b/drivers/gpu/drm/i915/i915_fb_pin.c index 0019f570d843..e14d2c1fb81f 100644 --- a/drivers/gpu/drm/i915/i915_fb_pin.c +++ b/drivers/gpu/drm/i915/i915_fb_pin.c @@ -257,6 +257,41 @@ intel_plane_fb_vtd_guard(const struct intel_plane_state *plane_state) plane_state->hw.rotation); } +static int i915_fb_pin_ggtt_pin(struct drm_gem_object *obj, + const struct intel_fb_pin_params *pin_params, + struct i915_vma **out_ggtt_vma, + u32 *out_offset, + int *out_fence_id) +{ + struct i915_vma *ggtt_vma; + + ggtt_vma = intel_fb_pin_to_ggtt(obj, pin_params, out_fence_id); + if (IS_ERR(ggtt_vma)) + return PTR_ERR(ggtt_vma); + + *out_ggtt_vma = ggtt_vma; + + /* + * Pre-populate the dma address before we enter the vblank + * evade critical section as i915_gem_object_get_dma_address() + * will trigger might_sleep() even if it won't actually sleep, + * which is the case when the fb has already been pinned. + */ + if (pin_params->needs_physical) + *out_offset = i915_gem_object_get_dma_address(to_intel_bo(obj), 0); + else + *out_offset = i915_ggtt_offset(ggtt_vma); + + return 0; +} + +static void i915_fb_pin_ggtt_unpin(struct i915_vma *ggtt_vma, + int fence_id) +{ + if (ggtt_vma) + intel_fb_unpin_vma(ggtt_vma, fence_id); +} + static int i915_fb_pin_dpt_pin(struct drm_gem_object *obj, struct intel_dpt *dpt, const struct intel_fb_pin_params *pin_params, struct i915_vma **out_dpt_vma, @@ -325,24 +360,11 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, .needs_fence = intel_plane_needs_fence(display), }; - ggtt_vma = intel_fb_pin_to_ggtt(intel_fb_bo(&fb->base), &pin_params, - intel_plane_uses_fence(plane_state) ? &fence_id : NULL); - if (IS_ERR(ggtt_vma)) - return PTR_ERR(ggtt_vma); - - /* - * Pre-populate the dma address before we enter the vblank - * evade critical section as i915_gem_object_get_dma_address() - * will trigger might_sleep() even if it won't actually sleep, - * which is the case when the fb has already been pinned. - */ - if (intel_plane_needs_physical(plane)) { - struct drm_i915_gem_object *obj = to_intel_bo(intel_fb_bo(&fb->base)); - - offset = i915_gem_object_get_dma_address(obj, 0); - } else { - offset = i915_ggtt_offset(ggtt_vma); - } + ret = i915_fb_pin_ggtt_pin(intel_fb_bo(&fb->base), + &pin_params, &ggtt_vma, &offset, + intel_plane_uses_fence(plane_state) ? &fence_id : NULL); + if (ret) + return ret; } else { struct intel_fb_pin_params pin_params = { .view = &plane_state->view.gtt, @@ -371,13 +393,11 @@ void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) to_intel_framebuffer(old_plane_state->hw.fb); if (!intel_fb_uses_dpt(&fb->base)) { - struct i915_vma *vma; + i915_fb_pin_ggtt_unpin(old_plane_state->ggtt_vma, + old_plane_state->fence_id); - vma = fetch_and_zero(&old_plane_state->ggtt_vma); - if (vma) { - intel_fb_unpin_vma(vma, old_plane_state->fence_id); - old_plane_state->fence_id = -1; - } + old_plane_state->ggtt_vma = NULL; + old_plane_state->fence_id = -1; } else { i915_fb_pin_dpt_unpin(fb->dpt, old_plane_state->dpt_vma, From 77f00edf435ed8359a074682d87b5bd1f3375638 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:17 +0300 Subject: [PATCH 23/38] drm/xe: Move the FORCE_WC assert into __xe_pin_fb_vma() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No need to bother the higher level pinning code with the FORCE_WC assert. Move it into the lower level function. This also introduces the check to intel_fb_pin_to_ggtt(), which (for the moment) is still used for the fbdev bo setup. But this is all display stuff we're talking about here so having the check is correct everywhere. v2: Pimp the commit message a bit (Jani) Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-8-ville.syrjala@linux.intel.com --- drivers/gpu/drm/xe/display/xe_fb_pin.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index 0da1fbcb82d5..21cc38dadb18 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -328,6 +328,9 @@ static struct i915_vma *__xe_pin_fb_vma(struct drm_gem_object *obj, bool is_dpt, struct drm_exec exec; int ret = 0; + /* We reject creating !SCANOUT fb's, so this is weird.. */ + drm_WARN_ON(bo->ttm.base.dev, !(bo->flags & XE_BO_FLAG_FORCE_WC)); + if (!vma) return ERR_PTR(-ENODEV); @@ -473,7 +476,6 @@ int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, { struct drm_framebuffer *fb = new_plane_state->hw.fb; struct drm_gem_object *obj = intel_fb_bo(fb); - struct xe_bo *bo = gem_to_xe_bo(obj); struct i915_vma *vma; struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); struct intel_fb_pin_params pin_params = { @@ -485,9 +487,6 @@ int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, if (reuse_vma(new_plane_state, old_plane_state)) return 0; - /* We reject creating !SCANOUT fb's, so this is weird.. */ - drm_WARN_ON(bo->ttm.base.dev, !(bo->flags & XE_BO_FLAG_FORCE_WC)); - vma = __xe_pin_fb_vma(obj, intel_fb_uses_dpt(fb), &pin_params); if (IS_ERR(vma)) From d6297f49a62e5ed3b8ea89ae82e7430c11bc3f00 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:18 +0300 Subject: [PATCH 24/38] drm/xe: Kill the fbdev vma reuse hack MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fbdev vma reuse hacks is a massive layering violation. It really does not belong in the fb pinning code. And it's in the way of properly abstracting this stuff, so kill it. I don't think this hack even does anything useful because the normal view will just use bo->ggtt_node when present, and the fbdev bo will be permanenly pinned with xe_bo_create_pin_map_at_novm() which does set up bo->ggtt_node. So we should never end up rebuilding the PTEs for the fbdev bo, even without the reuse hack. v2: Pimp the commit message a a bit (Jani) v3: Also nuke intel_fbdev_vma_pointer() Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-9-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_fbdev.c | 5 ----- drivers/gpu/drm/i915/display/intel_fbdev.h | 7 ------- drivers/gpu/drm/xe/display/xe_fb_pin.c | 10 ---------- 3 files changed, 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index aa2701795caa..1ae7f62842fc 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -560,11 +560,6 @@ struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbdev) return fbdev->fb; } -struct i915_vma *intel_fbdev_vma_pointer(struct intel_fbdev *fbdev) -{ - return fbdev ? fbdev->vma : NULL; -} - void intel_fbdev_get_map(struct intel_display *display, struct iosys_map *map) { struct intel_fbdev *fbdev = display->fbdev.fbdev; diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.h b/drivers/gpu/drm/i915/display/intel_fbdev.h index edaf5d16a456..0ae36d321c77 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.h +++ b/drivers/gpu/drm/i915/display/intel_fbdev.h @@ -22,7 +22,6 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, .fbdev_probe = intel_fbdev_driver_fbdev_probe void intel_fbdev_setup(struct intel_display *display); struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbdev); -struct i915_vma *intel_fbdev_vma_pointer(struct intel_fbdev *fbdev); void intel_fbdev_get_map(struct intel_display *display, struct iosys_map *map); #else #define INTEL_FBDEV_DRIVER_OPS \ @@ -34,12 +33,6 @@ static inline struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbd { return NULL; } - -static inline struct i915_vma *intel_fbdev_vma_pointer(struct intel_fbdev *fbdev) -{ - return NULL; -} - static inline void intel_fbdev_get_map(struct intel_display *display, struct iosys_map *map) { } diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index 21cc38dadb18..52ddb73f8a0c 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -10,7 +10,6 @@ #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_pin.h" -#include "intel_fbdev.h" #include "xe_bo.h" #include "xe_device.h" #include "xe_display_vma.h" @@ -431,10 +430,7 @@ void intel_fb_unpin_vma(struct i915_vma *vma, int fence_id) static bool reuse_vma(struct intel_plane_state *new_plane_state, const struct intel_plane_state *old_plane_state) { - struct intel_framebuffer *fb = to_intel_framebuffer(new_plane_state->hw.fb); struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); - struct xe_device *xe = to_xe_device(fb->base.dev); - struct intel_display *display = xe->display; struct i915_vma *vma; if (old_plane_state->hw.fb == new_plane_state->hw.fb && @@ -445,12 +441,6 @@ static bool reuse_vma(struct intel_plane_state *new_plane_state, goto found; } - if (fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) { - vma = intel_fbdev_vma_pointer(display->fbdev.fbdev); - if (vma) - goto found; - } - return false; found: From a47b5cf41f9f76d613ad5fa058d12b7d9c694cfc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:19 +0300 Subject: [PATCH 25/38] drm/xe: Reorganize intel_plane_pin_fb() a bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move most of the plane state stuff out from the inner parts of intel_plane_pin_fb(). The plan is to take those inner parts and abstract them into the new fb_pin parent interface, and we don't want any plane_state stuff there. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-10-ville.syrjala@linux.intel.com --- drivers/gpu/drm/xe/display/xe_fb_pin.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index 52ddb73f8a0c..9e466ae0e566 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -466,26 +466,30 @@ int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, { struct drm_framebuffer *fb = new_plane_state->hw.fb; struct drm_gem_object *obj = intel_fb_bo(fb); - struct i915_vma *vma; struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); struct intel_fb_pin_params pin_params = { .view = &new_plane_state->view.gtt, .alignment = intel_plane_fb_min_alignment(new_plane_state), .needs_cpu_lmem_access = intel_fb_needs_cpu_access(fb), }; + struct i915_vma *ggtt_vma = NULL; + struct i915_vma *dpt_vma = NULL; + int fence_id = -1; + u32 offset; if (reuse_vma(new_plane_state, old_plane_state)) return 0; - vma = __xe_pin_fb_vma(obj, intel_fb_uses_dpt(fb), &pin_params); + ggtt_vma = __xe_pin_fb_vma(obj, intel_fb_uses_dpt(fb), &pin_params); + if (IS_ERR(ggtt_vma)) + return PTR_ERR(ggtt_vma); - if (IS_ERR(vma)) - return PTR_ERR(vma); + offset = xe_ggtt_node_addr(ggtt_vma->node); - new_plane_state->ggtt_vma = vma; - - new_plane_state->surf = xe_ggtt_node_addr(new_plane_state->ggtt_vma->node) + - plane->surf_offset(new_plane_state); + new_plane_state->dpt_vma = dpt_vma; + new_plane_state->ggtt_vma = ggtt_vma; + new_plane_state->fence_id = fence_id; + new_plane_state->surf = offset + plane->surf_offset(new_plane_state); return 0; } From 85348bdc8c7a7bc4b1ed8c60beb7aa372aba1368 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:20 +0300 Subject: [PATCH 26/38] drm/xe: Introduce xe_fb_pin_dpt_(un)pin() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extract the inner DPT parts of intel_plane_(un)pin() into the xe_fb_pin_dpt_(un)pin(). These will become part of the new fb_pin parent interface. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-11-ville.syrjala@linux.intel.com --- drivers/gpu/drm/xe/display/xe_fb_pin.c | 67 ++++++++++++++++++++++---- 1 file changed, 58 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index 9e466ae0e566..f06c72518760 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -427,6 +427,36 @@ void intel_fb_unpin_vma(struct i915_vma *vma, int fence_id) __xe_unpin_fb_vma(vma); } +static int xe_fb_pin_dpt_pin(struct drm_gem_object *obj, struct intel_dpt *dpt, + const struct intel_fb_pin_params *pin_params, + struct i915_vma **out_dpt_vma, + struct i915_vma **out_ggtt_vma, + u32 *out_offset) +{ + struct i915_vma *ggtt_vma; + + WARN_ON(dpt); + + ggtt_vma = __xe_pin_fb_vma(obj, true, pin_params); + if (IS_ERR(ggtt_vma)) + return PTR_ERR(ggtt_vma); + + *out_dpt_vma = NULL; /* not used on xe */ + *out_ggtt_vma = ggtt_vma; + *out_offset = xe_ggtt_node_addr(ggtt_vma->node); + + return 0; +} + +static void xe_fb_pin_dpt_unpin(struct intel_dpt *dpt, + struct i915_vma *dpt_vma, + struct i915_vma *ggtt_vma) +{ + WARN_ON(dpt || dpt_vma); + + __xe_unpin_fb_vma(ggtt_vma); +} + static bool reuse_vma(struct intel_plane_state *new_plane_state, const struct intel_plane_state *old_plane_state) { @@ -464,27 +494,35 @@ intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state) int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, const struct intel_plane_state *old_plane_state) { - struct drm_framebuffer *fb = new_plane_state->hw.fb; - struct drm_gem_object *obj = intel_fb_bo(fb); + struct intel_framebuffer *fb = to_intel_framebuffer(new_plane_state->hw.fb); + struct drm_gem_object *obj = intel_fb_bo(&fb->base); struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); struct intel_fb_pin_params pin_params = { .view = &new_plane_state->view.gtt, .alignment = intel_plane_fb_min_alignment(new_plane_state), - .needs_cpu_lmem_access = intel_fb_needs_cpu_access(fb), + .needs_cpu_lmem_access = intel_fb_needs_cpu_access(&fb->base), }; struct i915_vma *ggtt_vma = NULL; struct i915_vma *dpt_vma = NULL; int fence_id = -1; u32 offset; + int ret; if (reuse_vma(new_plane_state, old_plane_state)) return 0; - ggtt_vma = __xe_pin_fb_vma(obj, intel_fb_uses_dpt(fb), &pin_params); - if (IS_ERR(ggtt_vma)) - return PTR_ERR(ggtt_vma); + if (!intel_fb_uses_dpt(&fb->base)) { + ggtt_vma = __xe_pin_fb_vma(obj, false, &pin_params); + if (IS_ERR(ggtt_vma)) + return PTR_ERR(ggtt_vma); - offset = xe_ggtt_node_addr(ggtt_vma->node); + offset = xe_ggtt_node_addr(ggtt_vma->node); + } else { + ret = xe_fb_pin_dpt_pin(obj, fb->dpt, &pin_params, + &dpt_vma, &ggtt_vma, &offset); + if (ret) + return ret; + } new_plane_state->dpt_vma = dpt_vma; new_plane_state->ggtt_vma = ggtt_vma; @@ -496,8 +534,19 @@ int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) { - __xe_unpin_fb_vma(old_plane_state->ggtt_vma); - old_plane_state->ggtt_vma = NULL; + const struct intel_framebuffer *fb = to_intel_framebuffer(old_plane_state->hw.fb); + + if (!intel_fb_uses_dpt(&fb->base)) { + __xe_unpin_fb_vma(old_plane_state->ggtt_vma); + + old_plane_state->ggtt_vma = NULL; + } else { + xe_fb_pin_dpt_unpin(fb->dpt, old_plane_state->dpt_vma, + old_plane_state->ggtt_vma); + + old_plane_state->dpt_vma = NULL; + old_plane_state->ggtt_vma = NULL; + } } static void xe_fb_pin_get_map(struct i915_vma *vma, struct iosys_map *map) From 4f5a4f64d7fcc7be9ca791cb272e61acec95bea4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:21 +0300 Subject: [PATCH 27/38] drm/xe: Introduce xe_fb_pin_ggtt_(un)pin() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extract the inner DPT parts of intel_plane_(un)pin() into the xe_fb_pin_ggtt_(un)pin(). These will become part of the new fb_pin parent interface. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-12-ville.syrjala@linux.intel.com --- drivers/gpu/drm/xe/display/xe_fb_pin.c | 41 ++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index f06c72518760..0bb797ad7bff 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -427,6 +427,34 @@ void intel_fb_unpin_vma(struct i915_vma *vma, int fence_id) __xe_unpin_fb_vma(vma); } +static int xe_fb_pin_ggtt_pin(struct drm_gem_object *obj, + const struct intel_fb_pin_params *pin_params, + struct i915_vma **out_ggtt_vma, + u32 *out_offset, + int *out_fence_id) +{ + struct i915_vma *ggtt_vma; + + ggtt_vma = __xe_pin_fb_vma(obj, false, pin_params); + if (IS_ERR(ggtt_vma)) + return PTR_ERR(ggtt_vma); + + *out_ggtt_vma = ggtt_vma; + *out_offset = xe_ggtt_node_addr(ggtt_vma->node); + if (out_fence_id) + *out_fence_id = -1; + + return 0; +} + +static void xe_fb_pin_ggtt_unpin(struct i915_vma *ggtt_vma, + int fence_id) +{ + WARN_ON(fence_id >= 0); + + __xe_unpin_fb_vma(ggtt_vma); +} + static int xe_fb_pin_dpt_pin(struct drm_gem_object *obj, struct intel_dpt *dpt, const struct intel_fb_pin_params *pin_params, struct i915_vma **out_dpt_vma, @@ -512,11 +540,10 @@ int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, return 0; if (!intel_fb_uses_dpt(&fb->base)) { - ggtt_vma = __xe_pin_fb_vma(obj, false, &pin_params); - if (IS_ERR(ggtt_vma)) - return PTR_ERR(ggtt_vma); - - offset = xe_ggtt_node_addr(ggtt_vma->node); + ret = xe_fb_pin_ggtt_pin(obj, &pin_params, + &ggtt_vma, &offset, NULL); + if (ret) + return ret; } else { ret = xe_fb_pin_dpt_pin(obj, fb->dpt, &pin_params, &dpt_vma, &ggtt_vma, &offset); @@ -537,9 +564,11 @@ void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) const struct intel_framebuffer *fb = to_intel_framebuffer(old_plane_state->hw.fb); if (!intel_fb_uses_dpt(&fb->base)) { - __xe_unpin_fb_vma(old_plane_state->ggtt_vma); + xe_fb_pin_ggtt_unpin(old_plane_state->ggtt_vma, + old_plane_state->fence_id); old_plane_state->ggtt_vma = NULL; + old_plane_state->fence_id = -1; } else { xe_fb_pin_dpt_unpin(fb->dpt, old_plane_state->dpt_vma, old_plane_state->ggtt_vma); From 4b17676627fdde3ec9e7a8cc12b7829319e94805 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:22 +0300 Subject: [PATCH 28/38] drm/xe: Restructure reuse_vma() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Restructure reuse_vma() into a form that doesn't need the plane state structs, and rename the result to xe_fb_pin_reuse_vma(). This will become the new fb_pin parent interface. v2: Fix memcmp() arguments Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-13-ville.syrjala@linux.intel.com --- drivers/gpu/drm/xe/display/xe_fb_pin.c | 48 ++++++++++++++------------ 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index 0bb797ad7bff..e6812ab5c469 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -485,30 +485,24 @@ static void xe_fb_pin_dpt_unpin(struct intel_dpt *dpt, __xe_unpin_fb_vma(ggtt_vma); } -static bool reuse_vma(struct intel_plane_state *new_plane_state, - const struct intel_plane_state *old_plane_state) +static struct i915_vma * +xe_fb_pin_reuse_vma(struct i915_vma *old_ggtt_vma, + struct drm_gem_object *old_obj, + const struct i915_gtt_view *old_view, + struct drm_gem_object *new_obj, + const struct i915_gtt_view *new_view, + u32 *out_offset) { - struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); - struct i915_vma *vma; + if (old_ggtt_vma && old_obj == new_obj && + !memcmp(old_view, new_view, sizeof(*new_view))) { + refcount_inc(&old_ggtt_vma->ref); - if (old_plane_state->hw.fb == new_plane_state->hw.fb && - !memcmp(&old_plane_state->view.gtt, - &new_plane_state->view.gtt, - sizeof(new_plane_state->view.gtt))) { - vma = old_plane_state->ggtt_vma; - goto found; + *out_offset = xe_ggtt_node_addr(old_ggtt_vma->node); + + return old_ggtt_vma; } - return false; - -found: - refcount_inc(&vma->ref); - new_plane_state->ggtt_vma = vma; - - new_plane_state->surf = xe_ggtt_node_addr(new_plane_state->ggtt_vma->node) + - plane->surf_offset(new_plane_state); - - return true; + return NULL; } static unsigned int @@ -522,7 +516,8 @@ intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state) int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, const struct intel_plane_state *old_plane_state) { - struct intel_framebuffer *fb = to_intel_framebuffer(new_plane_state->hw.fb); + const struct intel_framebuffer *fb = to_intel_framebuffer(new_plane_state->hw.fb); + const struct intel_framebuffer *old_fb = to_intel_framebuffer(old_plane_state->hw.fb); struct drm_gem_object *obj = intel_fb_bo(&fb->base); struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); struct intel_fb_pin_params pin_params = { @@ -536,8 +531,14 @@ int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, u32 offset; int ret; - if (reuse_vma(new_plane_state, old_plane_state)) - return 0; + ggtt_vma = xe_fb_pin_reuse_vma(old_plane_state->ggtt_vma, + intel_fb_bo(&old_fb->base), + &old_plane_state->view.gtt, + intel_fb_bo(&fb->base), + &new_plane_state->view.gtt, + &offset); + if (ggtt_vma) + goto got_vma; if (!intel_fb_uses_dpt(&fb->base)) { ret = xe_fb_pin_ggtt_pin(obj, &pin_params, @@ -551,6 +552,7 @@ int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, return ret; } +got_vma: new_plane_state->dpt_vma = dpt_vma; new_plane_state->ggtt_vma = ggtt_vma; new_plane_state->fence_id = fence_id; From f225861a0feee6acd5c303ff3fa8566ae2876ccf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:23 +0300 Subject: [PATCH 29/38] drm/i915: Introduce the main fb_pin parent interface MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce the main part of the new fb_pin parent interface: - intel_parent_fb_pin_ggtt_(un)pin() - intel_parent_fb_pin_dpt_(un)pin() - intel_parent_fb_pin_reuse_vma() Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-14-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_parent.c | 53 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_parent.h | 29 +++++++++++ drivers/gpu/drm/i915/i915_fb_pin.c | 29 +++++++---- drivers/gpu/drm/xe/display/xe_fb_pin.c | 40 +++++++++------ include/drm/intel/display_parent_interface.h | 22 ++++++++ 5 files changed, 148 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_parent.c b/drivers/gpu/drm/i915/display/intel_parent.c index 070cc60f49b3..a5816561be40 100644 --- a/drivers/gpu/drm/i915/display/intel_parent.c +++ b/drivers/gpu/drm/i915/display/intel_parent.c @@ -53,6 +53,59 @@ void intel_parent_dpt_resume(struct intel_display *display, struct intel_dpt *dp } /* fb_pin */ +int intel_parent_fb_pin_ggtt_pin(struct intel_display *display, + struct drm_gem_object *obj, + const struct intel_fb_pin_params *pin_params, + struct i915_vma **out_ggtt_vma, + u32 *out_offset, + int *out_fence_id) +{ + return display->parent->fb_pin->ggtt_pin(obj, pin_params, + out_ggtt_vma, out_offset, out_fence_id); +} + +void intel_parent_fb_pin_ggtt_unpin(struct intel_display *display, + struct i915_vma *ggtt_vma, + int fence_id) +{ + return display->parent->fb_pin->ggtt_unpin(ggtt_vma, fence_id); +} + +int intel_parent_fb_pin_dpt_pin(struct intel_display *display, + struct drm_gem_object *obj, + struct intel_dpt *dpt, + const struct intel_fb_pin_params *pin_params, + struct i915_vma **out_dpt_vma, + struct i915_vma **out_ggtt_vma, + u32 *out_offset) +{ + return display->parent->fb_pin->dpt_pin(obj, dpt, pin_params, + out_dpt_vma, out_ggtt_vma, out_offset); +} + +void intel_parent_fb_pin_dpt_unpin(struct intel_display *display, + struct intel_dpt *dpt, + struct i915_vma *dpt_vma, + struct i915_vma *ggtt_vma) +{ + return display->parent->fb_pin->dpt_unpin(dpt, dpt_vma, ggtt_vma); +} + +struct i915_vma *intel_parent_fb_pin_reuse_vma(struct intel_display *display, + struct i915_vma *old_ggtt_vma, + struct drm_gem_object *old_obj, + const struct i915_gtt_view *old_view, + struct drm_gem_object *new_obj, + const struct i915_gtt_view *new_view, + u32 *out_offset) +{ + if (!display->parent->fb_pin->reuse_vma) + return NULL; + + return display->parent->fb_pin->reuse_vma(old_ggtt_vma, old_obj, old_view, + new_obj, new_view, out_offset); +} + void intel_parent_fb_pin_get_map(struct intel_display *display, struct i915_vma *vma, struct iosys_map *map) { diff --git a/drivers/gpu/drm/i915/display/intel_parent.h b/drivers/gpu/drm/i915/display/intel_parent.h index 2b9e829e7f47..27e35f891a6b 100644 --- a/drivers/gpu/drm/i915/display/intel_parent.h +++ b/drivers/gpu/drm/i915/display/intel_parent.h @@ -11,9 +11,11 @@ struct dma_fence; struct drm_file; struct drm_gem_object; struct drm_scanout_buffer; +struct i915_gtt_view; struct i915_vma; struct intel_display; struct intel_dpt; +struct intel_fb_pin_params; struct intel_frontbuffer; struct intel_hdcp_gsc_context; struct intel_panic; @@ -28,6 +30,33 @@ void intel_parent_dpt_suspend(struct intel_display *display, struct intel_dpt *d void intel_parent_dpt_resume(struct intel_display *display, struct intel_dpt *dpt); /* fb_pin */ +int intel_parent_fb_pin_ggtt_pin(struct intel_display *display, + struct drm_gem_object *obj, + const struct intel_fb_pin_params *pin_params, + struct i915_vma **out_ggtt_vma, + u32 *out_offset, + int *out_fence_id); +void intel_parent_fb_pin_ggtt_unpin(struct intel_display *display, + struct i915_vma *ggtt_vma, + int fence_id); +int intel_parent_fb_pin_dpt_pin(struct intel_display *display, + struct drm_gem_object *obj, + struct intel_dpt *dpt, + const struct intel_fb_pin_params *pin_params, + struct i915_vma **out_dpt_vma, + struct i915_vma **out_ggtt_vma, + u32 *out_offset); +void intel_parent_fb_pin_dpt_unpin(struct intel_display *display, + struct intel_dpt *dpt, + struct i915_vma *dpt_vma, + struct i915_vma *ggtt_vma); +struct i915_vma *intel_parent_fb_pin_reuse_vma(struct intel_display *display, + struct i915_vma *old_ggtt_vma, + struct drm_gem_object *old_obj, + const struct i915_gtt_view *old_view, + struct drm_gem_object *new_obj, + const struct i915_gtt_view *new_view, + u32 *out_offset); void intel_parent_fb_pin_get_map(struct intel_display *display, struct i915_vma *vma, struct iosys_map *map); diff --git a/drivers/gpu/drm/i915/i915_fb_pin.c b/drivers/gpu/drm/i915/i915_fb_pin.c index e14d2c1fb81f..1f08e364d569 100644 --- a/drivers/gpu/drm/i915/i915_fb_pin.c +++ b/drivers/gpu/drm/i915/i915_fb_pin.c @@ -14,6 +14,7 @@ #include "display/intel_display_types.h" #include "display/intel_fb.h" #include "display/intel_fb_pin.h" +#include "display/intel_parent.h" #include "display/intel_plane.h" #include "gem/i915_gem_domain.h" @@ -360,9 +361,9 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, .needs_fence = intel_plane_needs_fence(display), }; - ret = i915_fb_pin_ggtt_pin(intel_fb_bo(&fb->base), - &pin_params, &ggtt_vma, &offset, - intel_plane_uses_fence(plane_state) ? &fence_id : NULL); + ret = intel_parent_fb_pin_ggtt_pin(display, intel_fb_bo(&fb->base), + &pin_params, &ggtt_vma, &offset, + intel_plane_uses_fence(plane_state) ? &fence_id : NULL); if (ret) return ret; } else { @@ -372,9 +373,9 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, .needs_cpu_lmem_access = intel_fb_needs_cpu_access(&fb->base), }; - ret = i915_fb_pin_dpt_pin(intel_fb_bo(&fb->base), fb->dpt, - &pin_params, &dpt_vma, - &ggtt_vma, &offset); + ret = intel_parent_fb_pin_dpt_pin(display, intel_fb_bo(&fb->base), + fb->dpt, &pin_params, + &dpt_vma, &ggtt_vma, &offset); if (ret) return ret; } @@ -389,19 +390,21 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) { + struct intel_display *display = to_intel_display(old_plane_state); const struct intel_framebuffer *fb = to_intel_framebuffer(old_plane_state->hw.fb); if (!intel_fb_uses_dpt(&fb->base)) { - i915_fb_pin_ggtt_unpin(old_plane_state->ggtt_vma, - old_plane_state->fence_id); + intel_parent_fb_pin_ggtt_unpin(display, + old_plane_state->ggtt_vma, + old_plane_state->fence_id); old_plane_state->ggtt_vma = NULL; old_plane_state->fence_id = -1; } else { - i915_fb_pin_dpt_unpin(fb->dpt, - old_plane_state->dpt_vma, - old_plane_state->ggtt_vma); + intel_parent_fb_pin_dpt_unpin(display, fb->dpt, + old_plane_state->dpt_vma, + old_plane_state->ggtt_vma); old_plane_state->dpt_vma = NULL; old_plane_state->ggtt_vma = NULL; @@ -414,5 +417,9 @@ static void i915_fb_pin_get_map(struct i915_vma *vma, struct iosys_map *map) } const struct intel_display_fb_pin_interface i915_display_fb_pin_interface = { + .ggtt_pin = i915_fb_pin_ggtt_pin, + .ggtt_unpin = i915_fb_pin_ggtt_unpin, + .dpt_pin = i915_fb_pin_dpt_pin, + .dpt_unpin = i915_fb_pin_dpt_unpin, .get_map = i915_fb_pin_get_map, }; diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index e6812ab5c469..a8f8d639e7d6 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -10,6 +10,7 @@ #include "intel_display_types.h" #include "intel_fb.h" #include "intel_fb_pin.h" +#include "intel_parent.h" #include "xe_bo.h" #include "xe_device.h" #include "xe_display_vma.h" @@ -516,6 +517,7 @@ intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state) int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, const struct intel_plane_state *old_plane_state) { + struct intel_display *display = to_intel_display(new_plane_state); const struct intel_framebuffer *fb = to_intel_framebuffer(new_plane_state->hw.fb); const struct intel_framebuffer *old_fb = to_intel_framebuffer(old_plane_state->hw.fb); struct drm_gem_object *obj = intel_fb_bo(&fb->base); @@ -531,23 +533,25 @@ int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, u32 offset; int ret; - ggtt_vma = xe_fb_pin_reuse_vma(old_plane_state->ggtt_vma, - intel_fb_bo(&old_fb->base), - &old_plane_state->view.gtt, - intel_fb_bo(&fb->base), - &new_plane_state->view.gtt, - &offset); + ggtt_vma = intel_parent_fb_pin_reuse_vma(display, + old_plane_state->ggtt_vma, + intel_fb_bo(&old_fb->base), + &old_plane_state->view.gtt, + intel_fb_bo(&fb->base), + &new_plane_state->view.gtt, + &offset); if (ggtt_vma) goto got_vma; if (!intel_fb_uses_dpt(&fb->base)) { - ret = xe_fb_pin_ggtt_pin(obj, &pin_params, - &ggtt_vma, &offset, NULL); + ret = intel_parent_fb_pin_ggtt_pin(display, obj, &pin_params, + &ggtt_vma, &offset, NULL); if (ret) return ret; } else { - ret = xe_fb_pin_dpt_pin(obj, fb->dpt, &pin_params, - &dpt_vma, &ggtt_vma, &offset); + ret = intel_parent_fb_pin_dpt_pin(display, obj, fb->dpt, + &pin_params, &dpt_vma, + &ggtt_vma, &offset); if (ret) return ret; } @@ -563,17 +567,20 @@ int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) { + struct intel_display *display = to_intel_display(old_plane_state); const struct intel_framebuffer *fb = to_intel_framebuffer(old_plane_state->hw.fb); if (!intel_fb_uses_dpt(&fb->base)) { - xe_fb_pin_ggtt_unpin(old_plane_state->ggtt_vma, - old_plane_state->fence_id); + intel_parent_fb_pin_ggtt_unpin(display, + old_plane_state->ggtt_vma, + old_plane_state->fence_id); old_plane_state->ggtt_vma = NULL; old_plane_state->fence_id = -1; } else { - xe_fb_pin_dpt_unpin(fb->dpt, old_plane_state->dpt_vma, - old_plane_state->ggtt_vma); + intel_parent_fb_pin_dpt_unpin(display, fb->dpt, + old_plane_state->dpt_vma, + old_plane_state->ggtt_vma); old_plane_state->dpt_vma = NULL; old_plane_state->ggtt_vma = NULL; @@ -586,5 +593,10 @@ static void xe_fb_pin_get_map(struct i915_vma *vma, struct iosys_map *map) } const struct intel_display_fb_pin_interface xe_display_fb_pin_interface = { + .ggtt_pin = xe_fb_pin_ggtt_pin, + .ggtt_unpin = xe_fb_pin_ggtt_unpin, + .dpt_pin = xe_fb_pin_dpt_pin, + .dpt_unpin = xe_fb_pin_dpt_unpin, + .reuse_vma = xe_fb_pin_reuse_vma, .get_map = xe_fb_pin_get_map, }; diff --git a/include/drm/intel/display_parent_interface.h b/include/drm/intel/display_parent_interface.h index b363d6a85dfe..39991afeb173 100644 --- a/include/drm/intel/display_parent_interface.h +++ b/include/drm/intel/display_parent_interface.h @@ -83,6 +83,28 @@ struct intel_display_dsb_interface { }; struct intel_display_fb_pin_interface { + int (*ggtt_pin)(struct drm_gem_object *obj, + const struct intel_fb_pin_params *pin_params, + struct i915_vma **out_ggtt_vma, + u32 *out_offset, + int *out_fence_id); + void (*ggtt_unpin)(struct i915_vma *ggtt_vma, + int fence_id); + int (*dpt_pin)(struct drm_gem_object *obj, + struct intel_dpt *dpt, + const struct intel_fb_pin_params *pin_params, + struct i915_vma **out_dpt_vma, + struct i915_vma **out_ggtt_vma, + u32 *out_offset); + void (*dpt_unpin)(struct intel_dpt *dpt, + struct i915_vma *dpt_vma, + struct i915_vma *ggtt_vma); + struct i915_vma *(*reuse_vma)(struct i915_vma *old_ggtt_vma, + struct drm_gem_object *old_obj, + const struct i915_gtt_view *old_view, + struct drm_gem_object *new_obj, + const struct i915_gtt_view *new_view, + u32 *out_offset); void (*get_map)(struct i915_vma *vma, struct iosys_map *map); }; From eadbb52a178147efe7fdbbb906e0767b5fe8a5b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:24 +0300 Subject: [PATCH 30/38] drm/i915/fbdev: Use intel_parent_fb_pin_ggtt_(un)pin() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace the intel_fb_pin_to_ggtt() and intel_fb_unpin_vma() with the new abstract parent interface (intel_parent_fb_pin_ggtt_(un)pin()). xe no longer needs intel_fb_unpin_vma(), and in i915 it now becomes and internal function to i915_fb_pin. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-15-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_fb_pin.h | 2 -- drivers/gpu/drm/i915/display/intel_fbdev.c | 14 +++++++------- drivers/gpu/drm/i915/i915_fb_pin.c | 2 +- drivers/gpu/drm/xe/display/xe_fb_pin.c | 5 ----- 4 files changed, 8 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h b/drivers/gpu/drm/i915/display/intel_fb_pin.h index 84530f20d7d1..6ff17d3e2cf5 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.h +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h @@ -20,8 +20,6 @@ intel_fb_pin_to_ggtt(struct drm_gem_object *obj, const struct intel_fb_pin_params *pin_params, int *out_fence_id); -void intel_fb_unpin_vma(struct i915_vma *vma, int fence_id); - int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, const struct intel_plane_state *old_plane_state); void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state); diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 1ae7f62842fc..df1d3d9dc3e5 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -53,7 +53,6 @@ #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_fb.h" -#include "intel_fb_pin.h" #include "intel_fbdev.h" #include "intel_frontbuffer.h" #include "intel_parent.h" @@ -133,6 +132,7 @@ static int intel_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma) static void intel_fbdev_fb_destroy(struct fb_info *info) { struct drm_fb_helper *fb_helper = info->par; + struct intel_display *display = to_intel_display(fb_helper->client.dev); struct intel_fbdev *ifbdev = to_intel_fbdev(fb_helper); drm_fb_helper_fini(fb_helper); @@ -142,7 +142,7 @@ static void intel_fbdev_fb_destroy(struct fb_info *info) * the info->screen_base mmaping. Leaking the VMA is simpler than * trying to rectify all the possible error paths leading here. */ - intel_fb_unpin_vma(ifbdev->vma, -1); + intel_parent_fb_pin_ggtt_unpin(display, ifbdev->vma, -1); drm_framebuffer_remove(fb_helper->fb); drm_client_release(&fb_helper->client); @@ -274,6 +274,7 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, struct i915_vma *vma; bool prealloc = false; struct drm_gem_object *obj; + u32 offset; int ret; ifbdev->fb = NULL; @@ -321,11 +322,10 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, DRM_MODE_ROTATE_0); pin_params.needs_low_address = intel_plane_needs_low_address(display); - vma = intel_fb_pin_to_ggtt(obj, &pin_params, NULL); - if (IS_ERR(vma)) { - ret = PTR_ERR(vma); + ret = intel_parent_fb_pin_ggtt_pin(display, obj, &pin_params, + &vma, &offset, NULL); + if (ret) goto out_unlock; - } helper->funcs = &intel_fb_helper_funcs; helper->fb = &fb->base; @@ -356,7 +356,7 @@ int intel_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, return 0; out_unpin: - intel_fb_unpin_vma(vma, -1); + intel_parent_fb_pin_ggtt_unpin(display, vma, -1); out_unlock: intel_display_rpm_put(display, wakeref); diff --git a/drivers/gpu/drm/i915/i915_fb_pin.c b/drivers/gpu/drm/i915/i915_fb_pin.c index 1f08e364d569..cedefee46fbf 100644 --- a/drivers/gpu/drm/i915/i915_fb_pin.c +++ b/drivers/gpu/drm/i915/i915_fb_pin.c @@ -222,7 +222,7 @@ intel_fb_pin_to_ggtt(struct drm_gem_object *_obj, return vma; } -void intel_fb_unpin_vma(struct i915_vma *vma, int fence_id) +static void intel_fb_unpin_vma(struct i915_vma *vma, int fence_id) { if (fence_id >= 0) i915_vma_unpin_fence(vma); diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index a8f8d639e7d6..496715b62e1d 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -423,11 +423,6 @@ intel_fb_pin_to_ggtt(struct drm_gem_object *obj, return __xe_pin_fb_vma(obj, false, pin_params); } -void intel_fb_unpin_vma(struct i915_vma *vma, int fence_id) -{ - __xe_unpin_fb_vma(vma); -} - static int xe_fb_pin_ggtt_pin(struct drm_gem_object *obj, const struct intel_fb_pin_params *pin_params, struct i915_vma **out_ggtt_vma, From 37744ae79b6702b9ffe589977fdb42090bf668d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:25 +0300 Subject: [PATCH 31/38] drm/xe: Use xe_fb_pin_ggtt_pin() for the initial FB pin MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use xe_fb_pin_ggtt_pin() instead of intel_fb_pin_to_ggtt() for the initial FB pin. We want to get rid of intel_fb_pin_to_ggtt() and just use the new fb_pin parent interface. This still isn't quite the final solution since we bypass the actual parent interface and call the implementation directly. But sorting that out will require more cleanup to the initial FB code. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-16-ville.syrjala@linux.intel.com --- drivers/gpu/drm/xe/display/xe_fb_pin.c | 21 +++++-------------- drivers/gpu/drm/xe/display/xe_fb_pin.h | 12 +++++++++++ drivers/gpu/drm/xe/display/xe_initial_plane.c | 18 ++++++++++------ 3 files changed, 29 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index 496715b62e1d..760c213e6278 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -412,22 +412,11 @@ static void __xe_unpin_fb_vma(struct i915_vma *vma) kfree(vma); } -struct i915_vma * -intel_fb_pin_to_ggtt(struct drm_gem_object *obj, - const struct intel_fb_pin_params *pin_params, - int *out_fence_id) -{ - if (out_fence_id) - *out_fence_id = -1; - - return __xe_pin_fb_vma(obj, false, pin_params); -} - -static int xe_fb_pin_ggtt_pin(struct drm_gem_object *obj, - const struct intel_fb_pin_params *pin_params, - struct i915_vma **out_ggtt_vma, - u32 *out_offset, - int *out_fence_id) +int xe_fb_pin_ggtt_pin(struct drm_gem_object *obj, + const struct intel_fb_pin_params *pin_params, + struct i915_vma **out_ggtt_vma, + u32 *out_offset, + int *out_fence_id) { struct i915_vma *ggtt_vma; diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.h b/drivers/gpu/drm/xe/display/xe_fb_pin.h index 8a42d4009f5d..20dd8a99a25f 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.h +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.h @@ -4,6 +4,18 @@ #ifndef __XE_FB_PIN_H__ #define __XE_FB_PIN_H__ +#include + +struct drm_gem_object; +struct i915_vma; +struct intel_fb_pin_params; + +int xe_fb_pin_ggtt_pin(struct drm_gem_object *obj, + const struct intel_fb_pin_params *pin_params, + struct i915_vma **out_ggtt_vma, + u32 *out_offset, + int *out_fence_id); + extern const struct intel_display_fb_pin_interface xe_display_fb_pin_interface; #endif /* __XE_FB_PIN_H__ */ diff --git a/drivers/gpu/drm/xe/display/xe_initial_plane.c b/drivers/gpu/drm/xe/display/xe_initial_plane.c index 8e3c0c4b81fe..02b46cc3b6df 100644 --- a/drivers/gpu/drm/xe/display/xe_initial_plane.c +++ b/drivers/gpu/drm/xe/display/xe_initial_plane.c @@ -7,12 +7,16 @@ #include "regs/xe_gtt_defs.h" -#include "intel_display_types.h" +/* FIXME move intel_remapped_info_size() & co. */ #include "intel_fb.h" -#include "intel_fb_pin.h" + +/* FIXME move intel_initial_plane_config */ +#include "intel_display_types.h" + #include "xe_bo.h" #include "xe_display_bo.h" #include "xe_display_vma.h" +#include "xe_fb_pin.h" #include "xe_ggtt.h" #include "xe_mmio.h" #include "xe_vram_types.h" @@ -137,14 +141,16 @@ xe_initial_plane_setup(struct drm_plane_state *_plane_state, struct intel_fb_pin_params pin_params = { .view = &plane_state->view.gtt, }; + u32 offset; + int ret; - vma = intel_fb_pin_to_ggtt(intel_fb_bo(fb), &pin_params, NULL); - if (IS_ERR(vma)) - return PTR_ERR(vma); + ret = xe_fb_pin_ggtt_pin(intel_fb_bo(fb), &pin_params, &vma, &offset, NULL); + if (ret) + return ret; plane_state->ggtt_vma = vma; - plane_state->surf = xe_ggtt_node_addr(plane_state->ggtt_vma->node); + plane_state->surf = offset; plane_config->vma = vma; From 24c100b8ede4b94106ce376bc9c0ed52bbe6bbf6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 8 May 2026 17:34:26 +0300 Subject: [PATCH 32/38] drm/i915: Consolidate the intel_plane_(un)pin_fb() implementations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently i915 and xe each implement their own versions of intel_plane_(un)pin(). Now that we have the fb_pin parent interface we can consolidate this to a single implementation. The result is a mixture of the i915 and xe implementations. The reuse_vma() hack comes from xe (and i915 doesn't implement that part of the parent interface, and the pin_params are taken from i915 since the platforms supported by i915 need more things. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260508143426.26504-17-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_cursor.c | 1 - drivers/gpu/drm/i915/display/intel_fb_pin.h | 27 ----- drivers/gpu/drm/i915/display/intel_plane.c | 118 +++++++++++++++++++- drivers/gpu/drm/i915/display/intel_plane.h | 3 + drivers/gpu/drm/i915/i915_fb_pin.c | 116 +------------------ drivers/gpu/drm/xe/display/xe_fb_pin.c | 90 +-------------- 6 files changed, 126 insertions(+), 229 deletions(-) delete mode 100644 drivers/gpu/drm/i915/display/intel_fb_pin.h diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 18d1014de361..52347668f27d 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -21,7 +21,6 @@ #include "intel_display_utils.h" #include "intel_display_wa.h" #include "intel_fb.h" -#include "intel_fb_pin.h" #include "intel_frontbuffer.h" #include "intel_plane.h" #include "intel_psr.h" diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h b/drivers/gpu/drm/i915/display/intel_fb_pin.h deleted file mode 100644 index 6ff17d3e2cf5..000000000000 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2021 Intel Corporation - */ - -#ifndef __INTEL_FB_PIN_H__ -#define __INTEL_FB_PIN_H__ - -#include - -struct drm_gem_object; -struct i915_vma; -struct intel_fb_pin_params; -struct intel_plane_state; -struct i915_gtt_view; -struct iosys_map; - -struct i915_vma * -intel_fb_pin_to_ggtt(struct drm_gem_object *obj, - const struct intel_fb_pin_params *pin_params, - int *out_fence_id); - -int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, - const struct intel_plane_state *old_plane_state); -void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state); - -#endif diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c index e50e1a15410a..f132fa955d21 100644 --- a/drivers/gpu/drm/i915/display/intel_plane.c +++ b/drivers/gpu/drm/i915/display/intel_plane.c @@ -44,6 +44,7 @@ #include #include #include +#include #include "i9xx_plane_regs.h" #include "intel_cdclk.h" @@ -53,7 +54,6 @@ #include "intel_display_trace.h" #include "intel_display_types.h" #include "intel_fb.h" -#include "intel_fb_pin.h" #include "intel_fbdev.h" #include "intel_parent.h" #include "intel_plane.h" @@ -1191,6 +1191,122 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) return 0; } +static unsigned int +intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state) +{ + const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); + + return fb->min_alignment; +} + +static unsigned int +intel_plane_fb_min_phys_alignment(const struct intel_plane_state *plane_state) +{ + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); + const struct drm_framebuffer *fb = plane_state->hw.fb; + + if (!intel_plane_needs_physical(plane)) + return 0; + + return plane->min_alignment(plane, fb, 0); +} + +static unsigned int +intel_plane_fb_vtd_guard(const struct intel_plane_state *plane_state) +{ + return intel_fb_view_vtd_guard(plane_state->hw.fb, + &plane_state->view, + plane_state->hw.rotation); +} + +int intel_plane_pin_fb(struct intel_plane_state *plane_state, + const struct intel_plane_state *old_plane_state) +{ + struct intel_display *display = to_intel_display(plane_state); + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); + const struct intel_framebuffer *fb = + to_intel_framebuffer(plane_state->hw.fb); + const struct intel_framebuffer *old_fb = + to_intel_framebuffer(old_plane_state->hw.fb); + struct i915_vma *ggtt_vma = NULL; + struct i915_vma *dpt_vma = NULL; + int fence_id = -1; + u32 offset = 0; + int ret; + + /* hack for xe since it can't keep track of vmas properly */ + ggtt_vma = intel_parent_fb_pin_reuse_vma(display, + old_plane_state->ggtt_vma, + intel_fb_bo(&old_fb->base), + &old_plane_state->view.gtt, + intel_fb_bo(&fb->base), + &plane_state->view.gtt, + &offset); + if (ggtt_vma) + goto got_vma; + + if (!intel_fb_uses_dpt(&fb->base)) { + struct intel_fb_pin_params pin_params = { + .view = &plane_state->view.gtt, + .alignment = intel_plane_fb_min_alignment(plane_state), + .phys_alignment = intel_plane_fb_min_phys_alignment(plane_state), + .vtd_guard = intel_plane_fb_vtd_guard(plane_state), + .needs_cpu_lmem_access = intel_fb_needs_cpu_access(&fb->base), + .needs_low_address = intel_plane_needs_low_address(display), + .needs_physical = intel_plane_needs_physical(plane), + .needs_fence = intel_plane_needs_fence(display), + }; + + ret = intel_parent_fb_pin_ggtt_pin(display, intel_fb_bo(&fb->base), + &pin_params, &ggtt_vma, &offset, + intel_plane_uses_fence(plane_state) ? &fence_id : NULL); + } else { + struct intel_fb_pin_params pin_params = { + .view = &plane_state->view.gtt, + .alignment = intel_plane_fb_min_alignment(plane_state), + .needs_cpu_lmem_access = intel_fb_needs_cpu_access(&fb->base), + }; + + ret = intel_parent_fb_pin_dpt_pin(display, intel_fb_bo(&fb->base), + fb->dpt, &pin_params, + &dpt_vma, &ggtt_vma, &offset); + } + if (ret) + return ret; + +got_vma: + plane_state->dpt_vma = dpt_vma; + plane_state->ggtt_vma = ggtt_vma; + plane_state->fence_id = fence_id; + + plane_state->surf = offset + plane->surf_offset(plane_state); + + return 0; +} + +void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) +{ + struct intel_display *display = to_intel_display(old_plane_state); + const struct intel_framebuffer *fb = + to_intel_framebuffer(old_plane_state->hw.fb); + + if (!intel_fb_uses_dpt(&fb->base)) { + intel_parent_fb_pin_ggtt_unpin(display, + old_plane_state->ggtt_vma, + old_plane_state->fence_id); + + old_plane_state->ggtt_vma = NULL; + old_plane_state->fence_id = -1; + } else { + intel_parent_fb_pin_dpt_unpin(display, fb->dpt, + old_plane_state->dpt_vma, + old_plane_state->ggtt_vma); + + old_plane_state->dpt_vma = NULL; + old_plane_state->ggtt_vma = NULL; + } +} + static int add_dma_resv_fences(struct dma_resv *resv, struct drm_plane_state *new_plane_state) { diff --git a/drivers/gpu/drm/i915/display/intel_plane.h b/drivers/gpu/drm/i915/display/intel_plane.h index 7b5456f56f42..a6338bba72d9 100644 --- a/drivers/gpu/drm/i915/display/intel_plane.h +++ b/drivers/gpu/drm/i915/display/intel_plane.h @@ -92,5 +92,8 @@ int intel_plane_atomic_check(struct intel_atomic_state *state); bool intel_plane_format_mod_supported_async(struct drm_plane *plane, u32 format, u64 modifier); +int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, + const struct intel_plane_state *old_plane_state); +void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state); #endif /* __INTEL_PLANE_H__ */ diff --git a/drivers/gpu/drm/i915/i915_fb_pin.c b/drivers/gpu/drm/i915/i915_fb_pin.c index cedefee46fbf..1034cb767e9f 100644 --- a/drivers/gpu/drm/i915/i915_fb_pin.c +++ b/drivers/gpu/drm/i915/i915_fb_pin.c @@ -3,20 +3,9 @@ * Copyright © 2021 Intel Corporation */ -/** - * DOC: display pinning helpers - */ - #include #include -#include "display/intel_display_core.h" -#include "display/intel_display_types.h" -#include "display/intel_fb.h" -#include "display/intel_fb_pin.h" -#include "display/intel_parent.h" -#include "display/intel_plane.h" - #include "gem/i915_gem_domain.h" #include "gem/i915_gem_object.h" @@ -114,7 +103,7 @@ intel_fb_pin_to_dpt(struct drm_gem_object *_obj, struct intel_dpt *dpt, return vma; } -struct i915_vma * +static struct i915_vma * intel_fb_pin_to_ggtt(struct drm_gem_object *_obj, const struct intel_fb_pin_params *pin_params, int *out_fence_id) @@ -230,34 +219,6 @@ static void intel_fb_unpin_vma(struct i915_vma *vma, int fence_id) i915_vma_put(vma); } -static unsigned int -intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state) -{ - const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); - - return fb->min_alignment; -} - -static unsigned int -intel_plane_fb_min_phys_alignment(const struct intel_plane_state *plane_state) -{ - struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - const struct drm_framebuffer *fb = plane_state->hw.fb; - - if (!intel_plane_needs_physical(plane)) - return 0; - - return plane->min_alignment(plane, fb, 0); -} - -static unsigned int -intel_plane_fb_vtd_guard(const struct intel_plane_state *plane_state) -{ - return intel_fb_view_vtd_guard(plane_state->hw.fb, - &plane_state->view, - plane_state->hw.rotation); -} - static int i915_fb_pin_ggtt_pin(struct drm_gem_object *obj, const struct intel_fb_pin_params *pin_params, struct i915_vma **out_ggtt_vma, @@ -336,81 +297,6 @@ static void i915_fb_pin_dpt_unpin(struct intel_dpt *dpt, i915_dpt_unpin_from_ggtt(dpt); } -int intel_plane_pin_fb(struct intel_plane_state *plane_state, - const struct intel_plane_state *old_plane_state) -{ - struct intel_display *display = to_intel_display(plane_state); - struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - const struct intel_framebuffer *fb = - to_intel_framebuffer(plane_state->hw.fb); - struct i915_vma *ggtt_vma = NULL; - struct i915_vma *dpt_vma = NULL; - int fence_id = -1; - u32 offset; - int ret; - - if (!intel_fb_uses_dpt(&fb->base)) { - struct intel_fb_pin_params pin_params = { - .view = &plane_state->view.gtt, - .alignment = intel_plane_fb_min_alignment(plane_state), - .phys_alignment = intel_plane_fb_min_phys_alignment(plane_state), - .vtd_guard = intel_plane_fb_vtd_guard(plane_state), - .needs_cpu_lmem_access = intel_fb_needs_cpu_access(&fb->base), - .needs_low_address = intel_plane_needs_low_address(display), - .needs_physical = intel_plane_needs_physical(plane), - .needs_fence = intel_plane_needs_fence(display), - }; - - ret = intel_parent_fb_pin_ggtt_pin(display, intel_fb_bo(&fb->base), - &pin_params, &ggtt_vma, &offset, - intel_plane_uses_fence(plane_state) ? &fence_id : NULL); - if (ret) - return ret; - } else { - struct intel_fb_pin_params pin_params = { - .view = &plane_state->view.gtt, - .alignment = intel_plane_fb_min_alignment(plane_state), - .needs_cpu_lmem_access = intel_fb_needs_cpu_access(&fb->base), - }; - - ret = intel_parent_fb_pin_dpt_pin(display, intel_fb_bo(&fb->base), - fb->dpt, &pin_params, - &dpt_vma, &ggtt_vma, &offset); - if (ret) - return ret; - } - - plane_state->dpt_vma = dpt_vma; - plane_state->ggtt_vma = ggtt_vma; - plane_state->fence_id = fence_id; - plane_state->surf = offset + plane->surf_offset(plane_state); - - return 0; -} - -void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) -{ - struct intel_display *display = to_intel_display(old_plane_state); - const struct intel_framebuffer *fb = - to_intel_framebuffer(old_plane_state->hw.fb); - - if (!intel_fb_uses_dpt(&fb->base)) { - intel_parent_fb_pin_ggtt_unpin(display, - old_plane_state->ggtt_vma, - old_plane_state->fence_id); - - old_plane_state->ggtt_vma = NULL; - old_plane_state->fence_id = -1; - } else { - intel_parent_fb_pin_dpt_unpin(display, fb->dpt, - old_plane_state->dpt_vma, - old_plane_state->ggtt_vma); - - old_plane_state->dpt_vma = NULL; - old_plane_state->ggtt_vma = NULL; - } -} - static void i915_fb_pin_get_map(struct i915_vma *vma, struct iosys_map *map) { iosys_map_set_vaddr_iomem(map, i915_vma_get_iomap(vma)); diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index 760c213e6278..62855d35cd6e 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -6,11 +6,12 @@ #include #include -#include "intel_display_core.h" -#include "intel_display_types.h" +/* FIXME move the types to parent interface? */ +#include "i915_gtt_view_types.h" + +/* FIXME move intel_remapped_info_size() & co. to parent interface? */ #include "intel_fb.h" -#include "intel_fb_pin.h" -#include "intel_parent.h" + #include "xe_bo.h" #include "xe_device.h" #include "xe_display_vma.h" @@ -490,87 +491,6 @@ xe_fb_pin_reuse_vma(struct i915_vma *old_ggtt_vma, return NULL; } -static unsigned int -intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state) -{ - const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); - - return fb->min_alignment; -} - -int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, - const struct intel_plane_state *old_plane_state) -{ - struct intel_display *display = to_intel_display(new_plane_state); - const struct intel_framebuffer *fb = to_intel_framebuffer(new_plane_state->hw.fb); - const struct intel_framebuffer *old_fb = to_intel_framebuffer(old_plane_state->hw.fb); - struct drm_gem_object *obj = intel_fb_bo(&fb->base); - struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); - struct intel_fb_pin_params pin_params = { - .view = &new_plane_state->view.gtt, - .alignment = intel_plane_fb_min_alignment(new_plane_state), - .needs_cpu_lmem_access = intel_fb_needs_cpu_access(&fb->base), - }; - struct i915_vma *ggtt_vma = NULL; - struct i915_vma *dpt_vma = NULL; - int fence_id = -1; - u32 offset; - int ret; - - ggtt_vma = intel_parent_fb_pin_reuse_vma(display, - old_plane_state->ggtt_vma, - intel_fb_bo(&old_fb->base), - &old_plane_state->view.gtt, - intel_fb_bo(&fb->base), - &new_plane_state->view.gtt, - &offset); - if (ggtt_vma) - goto got_vma; - - if (!intel_fb_uses_dpt(&fb->base)) { - ret = intel_parent_fb_pin_ggtt_pin(display, obj, &pin_params, - &ggtt_vma, &offset, NULL); - if (ret) - return ret; - } else { - ret = intel_parent_fb_pin_dpt_pin(display, obj, fb->dpt, - &pin_params, &dpt_vma, - &ggtt_vma, &offset); - if (ret) - return ret; - } - -got_vma: - new_plane_state->dpt_vma = dpt_vma; - new_plane_state->ggtt_vma = ggtt_vma; - new_plane_state->fence_id = fence_id; - new_plane_state->surf = offset + plane->surf_offset(new_plane_state); - - return 0; -} - -void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) -{ - struct intel_display *display = to_intel_display(old_plane_state); - const struct intel_framebuffer *fb = to_intel_framebuffer(old_plane_state->hw.fb); - - if (!intel_fb_uses_dpt(&fb->base)) { - intel_parent_fb_pin_ggtt_unpin(display, - old_plane_state->ggtt_vma, - old_plane_state->fence_id); - - old_plane_state->ggtt_vma = NULL; - old_plane_state->fence_id = -1; - } else { - intel_parent_fb_pin_dpt_unpin(display, fb->dpt, - old_plane_state->dpt_vma, - old_plane_state->ggtt_vma); - - old_plane_state->dpt_vma = NULL; - old_plane_state->ggtt_vma = NULL; - } -} - static void xe_fb_pin_get_map(struct i915_vma *vma, struct iosys_map *map) { *map = vma->bo->vmap; From e8308fb5e05ca08ddfb8b46f6d947a6e3fd80cd7 Mon Sep 17 00:00:00 2001 From: Chaitanya Kumar Borah Date: Mon, 11 May 2026 11:02:10 +0530 Subject: [PATCH 33/38] drm/i915/display: Copy color pipeline from plane in the primary joiner pipe When copying plane color state in a joiner configuration, use the plane in the primary joiner pipe since it carries the pipeline number selected by the user-space. This assumes that all pipes in the joiner are symmetric in their plane color capabilities. Cc: stable@vger.kernel.org # v6.19+ Fixes: a78f1b6baf4d ("drm/i915/color: Add framework to program CSC") Tested-by: Vidya Srinivas Signed-off-by: Chaitanya Kumar Borah Reviewed-by: Uma Shankar Signed-off-by: Ankit Nautiyal Link: https://patch.msgid.link/20260511053213.3122314-2-chaitanya.kumar.borah@intel.com --- drivers/gpu/drm/i915/display/intel_plane.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c index f132fa955d21..dcda0767d3b5 100644 --- a/drivers/gpu/drm/i915/display/intel_plane.c +++ b/drivers/gpu/drm/i915/display/intel_plane.c @@ -396,7 +396,7 @@ intel_plane_color_copy_uapi_to_hw_state(struct intel_plane_state *plane_state, bool changed = false; int i = 0; - iter_colorop = plane_state->uapi.color_pipeline; + iter_colorop = from_plane_state->uapi.color_pipeline; while (iter_colorop) { for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) { From e892c68bba23d3e5be72933186fb74034a8e1bfe Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 5 May 2026 12:16:45 +0300 Subject: [PATCH 34/38] drm/i915/display: add typedef for intel_reg_t and use it MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a typedef alias intel_reg_t for i915_reg_t, and use it exclusively in display code. The goal is to eventually define a distinct type for display, but for now just use an alias. In a handful of places include intel_display_reg_defs.h instead of i915_reg_defs.h to get the definition, and isolate the i915_reg_defs.h include there. Reviewed-by: Michał Grzelak Acked-by: Ville Syrjälä Link: https://patch.msgid.link/f5bb0122143c39ce7f9ce8a1605a7637e569f7f8.1777972548.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/g4x_dp.c | 4 +- drivers/gpu/drm/i915/display/g4x_dp.h | 10 ++-- drivers/gpu/drm/i915/display/g4x_hdmi.c | 2 +- drivers/gpu/drm/i915/display/g4x_hdmi.h | 6 +-- drivers/gpu/drm/i915/display/icl_dsi.c | 2 +- drivers/gpu/drm/i915/display/intel_audio.c | 2 +- drivers/gpu/drm/i915/display/intel_color.c | 4 +- .../gpu/drm/i915/display/intel_combo_phy.c | 2 +- drivers/gpu/drm/i915/display/intel_crt.c | 6 +-- drivers/gpu/drm/i915/display/intel_crt.h | 6 +-- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +- drivers/gpu/drm/i915/display/intel_ddi.c | 26 +++++----- drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-- drivers/gpu/drm/i915/display/intel_de.c | 30 ++++++------ drivers/gpu/drm/i915/display/intel_de.h | 48 +++++++++---------- drivers/gpu/drm/i915/display/intel_display.c | 8 ++-- drivers/gpu/drm/i915/display/intel_display.h | 10 ++-- .../gpu/drm/i915/display/intel_display_irq.c | 10 ++-- .../drm/i915/display/intel_display_power.c | 4 +- .../i915/display/intel_display_power_well.c | 8 ++-- .../drm/i915/display/intel_display_reg_defs.h | 2 + .../drm/i915/display/intel_display_types.h | 8 ++-- drivers/gpu/drm/i915/display/intel_dmc.c | 24 +++++----- drivers/gpu/drm/i915/display/intel_dmc_wl.c | 8 ++-- drivers/gpu/drm/i915/display/intel_dmc_wl.h | 6 +-- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dp_aux.c | 28 +++++------ drivers/gpu/drm/i915/display/intel_dpio_phy.c | 8 ++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 28 +++++------ drivers/gpu/drm/i915/display/intel_dsb.c | 12 ++--- drivers/gpu/drm/i915/display/intel_dsb.h | 10 ++-- drivers/gpu/drm/i915/display/intel_dvo_dev.h | 2 +- drivers/gpu/drm/i915/display/intel_fdi.c | 12 ++--- .../drm/i915/display/intel_fifo_underrun.c | 4 +- drivers/gpu/drm/i915/display/intel_gmbus.c | 4 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 28 +++++------ drivers/gpu/drm/i915/display/intel_lt_phy.c | 6 +-- drivers/gpu/drm/i915/display/intel_lvds.c | 6 +-- drivers/gpu/drm/i915/display/intel_lvds.h | 6 +-- drivers/gpu/drm/i915/display/intel_mchbar.c | 10 ++-- drivers/gpu/drm/i915/display/intel_mchbar.h | 8 ++-- .../gpu/drm/i915/display/intel_pch_display.c | 14 +++--- drivers/gpu/drm/i915/display/intel_pps.c | 32 ++++++------- drivers/gpu/drm/i915/display/intel_psr.c | 36 +++++++------- drivers/gpu/drm/i915/display/intel_sdvo.c | 6 +-- drivers/gpu/drm/i915/display/intel_sdvo.h | 10 ++-- drivers/gpu/drm/i915/display/intel_snps_phy.c | 4 +- drivers/gpu/drm/i915/display/intel_tc.c | 10 ++-- drivers/gpu/drm/i915/display/intel_vblank.c | 2 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 10 ++-- drivers/gpu/drm/i915/display/intel_vga.c | 4 +- drivers/gpu/drm/i915/display/vlv_dsi.c | 16 +++---- 53 files changed, 283 insertions(+), 281 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 5e74d8a3ba5c..5ff1cdf4581a 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -273,7 +273,7 @@ static bool cpt_dp_port_selected(struct intel_display *display, } bool g4x_dp_port_enabled(struct intel_display *display, - i915_reg_t dp_reg, enum port port, + intel_reg_t dp_reg, enum port port, enum pipe *pipe) { bool ret; @@ -1280,7 +1280,7 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = { }; bool g4x_dp_init(struct intel_display *display, - i915_reg_t output_reg, enum port port) + intel_reg_t output_reg, enum port port) { const struct intel_bios_encoder_data *devdata; struct intel_digital_port *dig_port; diff --git a/drivers/gpu/drm/i915/display/g4x_dp.h b/drivers/gpu/drm/i915/display/g4x_dp.h index 0b28951b8365..99de690ebe7f 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.h +++ b/drivers/gpu/drm/i915/display/g4x_dp.h @@ -8,7 +8,7 @@ #include -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" enum pipe; enum port; @@ -20,23 +20,23 @@ struct intel_encoder; #ifdef I915 const struct dpll *vlv_get_dpll(struct intel_display *display); bool g4x_dp_port_enabled(struct intel_display *display, - i915_reg_t dp_reg, enum port port, + intel_reg_t dp_reg, enum port port, enum pipe *pipe); bool g4x_dp_init(struct intel_display *display, - i915_reg_t output_reg, enum port port); + intel_reg_t output_reg, enum port port); #else static inline const struct dpll *vlv_get_dpll(struct intel_display *display) { return NULL; } static inline bool g4x_dp_port_enabled(struct intel_display *display, - i915_reg_t dp_reg, int port, + intel_reg_t dp_reg, int port, enum pipe *pipe) { return false; } static inline bool g4x_dp_init(struct intel_display *display, - i915_reg_t output_reg, int port) + intel_reg_t output_reg, int port) { return false; } diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c index 5fe5067c4237..9ea90a6d906f 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c @@ -666,7 +666,7 @@ static bool assert_hdmi_port_valid(struct intel_display *display, enum port port } bool g4x_hdmi_init(struct intel_display *display, - i915_reg_t hdmi_reg, enum port port) + intel_reg_t hdmi_reg, enum port port) { const struct intel_bios_encoder_data *devdata; struct intel_digital_port *dig_port; diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.h b/drivers/gpu/drm/i915/display/g4x_hdmi.h index 039d2bdba06c..0557322efe5a 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.h +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.h @@ -8,7 +8,7 @@ #include -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" enum port; struct drm_atomic_state; @@ -17,12 +17,12 @@ struct intel_display; #ifdef I915 bool g4x_hdmi_init(struct intel_display *display, - i915_reg_t hdmi_reg, enum port port); + intel_reg_t hdmi_reg, enum port port); int g4x_hdmi_connector_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state); #else static inline bool g4x_hdmi_init(struct intel_display *display, - i915_reg_t hdmi_reg, int port) + intel_reg_t hdmi_reg, int port) { return false; } diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index afbaa0465842..a549f1fac810 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -296,7 +296,7 @@ static void configure_dual_link_mode(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); - i915_reg_t dss_ctl1_reg, dss_ctl2_reg; + intel_reg_t dss_ctl1_reg, dss_ctl2_reg; u32 dss_ctl1; /* FIXME: Move all DSS handling to intel_vdsc.c */ diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index 2a6476ccc85b..77e54cac56e2 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -595,7 +595,7 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder, } struct ibx_audio_regs { - i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; + intel_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; }; static void ibx_audio_regs_init(struct intel_display *display, diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 0531c60e5e5d..2d318e922671 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1348,7 +1348,7 @@ static void i965_load_luts(const struct intel_crtc_state *crtc_state) } static void ilk_lut_write(const struct intel_crtc_state *crtc_state, - i915_reg_t reg, u32 val) + intel_reg_t reg, u32 val) { struct intel_display *display = to_intel_display(crtc_state); @@ -1359,7 +1359,7 @@ static void ilk_lut_write(const struct intel_crtc_state *crtc_state, } static void ilk_lut_write_indexed(const struct intel_crtc_state *crtc_state, - i915_reg_t reg, u32 val) + intel_reg_t reg, u32 val) { struct intel_display *display = to_intel_display(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index f401558ac14e..9b4ecfbbed4f 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -92,7 +92,7 @@ static void icl_set_procmon_ref_values(struct intel_display *display, } static bool check_phy_reg(struct intel_display *display, - enum phy phy, i915_reg_t reg, u32 mask, + enum phy phy, intel_reg_t reg, u32 mask, u32 expected_val) { u32 val = intel_de_read(display, reg); diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 6aa6a1dd6e1b..c19e0c591a3c 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -77,7 +77,7 @@ struct intel_crt { struct intel_encoder base; bool force_hotplug_required; - i915_reg_t adpa_reg; + intel_reg_t adpa_reg; }; static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) @@ -91,7 +91,7 @@ static struct intel_crt *intel_attached_crt(struct intel_connector *connector) } bool intel_crt_port_enabled(struct intel_display *display, - i915_reg_t adpa_reg, enum pipe *pipe) + intel_reg_t adpa_reg, enum pipe *pipe) { u32 val; @@ -1011,7 +1011,7 @@ void intel_crt_init(struct intel_display *display) { struct intel_connector *connector; struct intel_crt *crt; - i915_reg_t adpa_reg; + intel_reg_t adpa_reg; u8 ddc_pin; u32 adpa; diff --git a/drivers/gpu/drm/i915/display/intel_crt.h b/drivers/gpu/drm/i915/display/intel_crt.h index e0abfe96a3d2..7d0ae8d8c28d 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.h +++ b/drivers/gpu/drm/i915/display/intel_crt.h @@ -6,7 +6,7 @@ #ifndef __INTEL_CRT_H__ #define __INTEL_CRT_H__ -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" enum pipe; struct drm_encoder; @@ -14,12 +14,12 @@ struct intel_display; #ifdef I915 bool intel_crt_port_enabled(struct intel_display *display, - i915_reg_t adpa_reg, enum pipe *pipe); + intel_reg_t adpa_reg, enum pipe *pipe); void intel_crt_init(struct intel_display *display); void intel_crt_reset(struct drm_encoder *encoder); #else static inline bool intel_crt_port_enabled(struct intel_display *display, - i915_reg_t adpa_reg, enum pipe *pipe) + intel_reg_t adpa_reg, enum pipe *pipe) { return false; } diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index d832e44ef62a..24a51ab21b55 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2980,7 +2980,7 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; enum phy phy = intel_encoder_to_phy(encoder); - i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port); + intel_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port); int lane; intel_de_rmw(display, buf_ctl2_reg, diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index cd61ddb7f469..86520848892e 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -188,7 +188,7 @@ static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, trans->entries[level].hsw.trans2); } -static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) +static intel_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port) { if (DISPLAY_VER(display) >= 14) return XELPDP_PORT_BUF_CTL1(display, port); @@ -1556,7 +1556,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder, intel_de_posting_read(display, DDI_BUF_CTL(port)); } -static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, +static void _icl_ddi_enable_clock(struct intel_display *display, intel_reg_t reg, u32 clk_sel_mask, u32 clk_sel, u32 clk_off) { mutex_lock(&display->dpll.lock); @@ -1572,7 +1572,7 @@ static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg, mutex_unlock(&display->dpll.lock); } -static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg, +static void _icl_ddi_disable_clock(struct intel_display *display, intel_reg_t reg, u32 clk_off) { mutex_lock(&display->dpll.lock); @@ -1582,14 +1582,14 @@ static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg mutex_unlock(&display->dpll.lock); } -static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg, +static bool _icl_ddi_is_clock_enabled(struct intel_display *display, intel_reg_t reg, u32 clk_off) { return !(intel_de_read(display, reg) & clk_off); } static struct intel_dpll * -_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg, +_icl_ddi_get_pll(struct intel_display *display, intel_reg_t reg, u32 clk_sel_mask, u32 clk_sel_shift) { enum intel_dpll_id id; @@ -2270,8 +2270,8 @@ tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) return crtc_state->cpu_transcoder; } -i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +intel_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); @@ -2282,8 +2282,8 @@ i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, return DP_TP_CTL(encoder->port); } -static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +static intel_reg_t dp_tp_status_reg(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); @@ -2559,7 +2559,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - i915_reg_t reg; + intel_reg_t reg; u32 set_bits, wait_bits; int ret; @@ -3059,7 +3059,7 @@ mtl_ddi_disable_d2d(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - i915_reg_t reg; + intel_reg_t reg; u32 clr_bits, wait_bits; int ret; @@ -3386,7 +3386,7 @@ static void intel_ddi_enable_dp(struct intel_atomic_state *state, trans_port_sync_stop_link_train(state, encoder, crtc_state); } -static i915_reg_t +static intel_reg_t gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) { static const enum transcoder trans[] = { @@ -3439,7 +3439,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, * the bits affect a specific DDI port rather than * a specific transcoder. */ - i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); + intel_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); u32 val; val = intel_de_read(display, reg); diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index f6f511bb0431..580ecb09b8b6 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -6,7 +6,7 @@ #ifndef __INTEL_DDI_H__ #define __INTEL_DDI_H__ -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" struct drm_connector_state; struct intel_atomic_state; @@ -23,8 +23,8 @@ enum pipe; enum port; enum transcoder; -i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state); +intel_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); void intel_ddi_clear_act_sent(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_de.c b/drivers/gpu/drm/i915/display/intel_de.c index a96e83d76eaa..6daee9e82503 100644 --- a/drivers/gpu/drm/i915/display/intel_de.c +++ b/drivers/gpu/drm/i915/display/intel_de.c @@ -10,9 +10,9 @@ #include "intel_de.h" static int __intel_de_wait_for_register(struct intel_display *display, - i915_reg_t reg, u32 mask, u32 value, + intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_us, - u32 (*read)(struct intel_display *display, i915_reg_t reg), + u32 (*read)(struct intel_display *display, intel_reg_t reg), u32 *out_val, bool is_atomic) { const ktime_t end = ktime_add_us(ktime_get_raw(), timeout_us); @@ -61,10 +61,10 @@ static int __intel_de_wait_for_register(struct intel_display *display, } static int intel_de_wait_for_register(struct intel_display *display, - i915_reg_t reg, u32 mask, u32 value, + intel_reg_t reg, u32 mask, u32 value, unsigned int fast_timeout_us, unsigned int slow_timeout_us, - u32 (*read)(struct intel_display *display, i915_reg_t reg), + u32 (*read)(struct intel_display *display, intel_reg_t reg), u32 *out_value, bool is_atomic) { int ret = -EINVAL; @@ -82,7 +82,7 @@ static int intel_de_wait_for_register(struct intel_display *display, return ret; } -int intel_de_wait_us(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_us(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_us, u32 *out_value) { @@ -100,7 +100,7 @@ int intel_de_wait_us(struct intel_display *display, i915_reg_t reg, return ret; } -int intel_de_wait_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_ms(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value) { @@ -118,7 +118,7 @@ int intel_de_wait_ms(struct intel_display *display, i915_reg_t reg, return ret; } -int intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_fw_ms(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value) { @@ -128,7 +128,7 @@ int intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg, out_value, false); } -int intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_fw_us_atomic(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_us, u32 *out_value) { @@ -138,31 +138,31 @@ int intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg, out_value, true); } -int intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_set_us(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_us) { return intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL); } -int intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_clear_us(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_us) { return intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL); } -int intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_set_ms(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_ms) { return intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL); } -int intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_clear_ms(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_ms) { return intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL); } -u8 intel_de_read8(struct intel_display *display, i915_reg_t reg) +u8 intel_de_read8(struct intel_display *display, intel_reg_t reg) { /* this is only used on VGA registers (possible on pre-g4x) */ drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x); @@ -170,14 +170,14 @@ u8 intel_de_read8(struct intel_display *display, i915_reg_t reg) return intel_uncore_read8(__to_uncore(display), reg); } -void intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val) +void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val) { drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 5 || display->platform.g4x); intel_uncore_write8(__to_uncore(display), reg, val); } -u16 intel_de_read16(struct intel_display *display, i915_reg_t reg) +u16 intel_de_read16(struct intel_display *display, intel_reg_t reg) { /* this is only used on MCHBAR registers on pre-SNB */ drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 6); diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h index 14f9dc7b6dfd..d17f14843f98 100644 --- a/drivers/gpu/drm/i915/display/intel_de.h +++ b/drivers/gpu/drm/i915/display/intel_de.h @@ -17,12 +17,12 @@ static inline struct intel_uncore *__to_uncore(struct intel_display *display) return to_intel_uncore(display->drm); } -u8 intel_de_read8(struct intel_display *display, i915_reg_t reg); -void intel_de_write8(struct intel_display *display, i915_reg_t reg, u8 val); -u16 intel_de_read16(struct intel_display *display, i915_reg_t reg); +u8 intel_de_read8(struct intel_display *display, intel_reg_t reg); +void intel_de_write8(struct intel_display *display, intel_reg_t reg, u8 val); +u16 intel_de_read16(struct intel_display *display, intel_reg_t reg); static inline u32 -intel_de_read(struct intel_display *display, i915_reg_t reg) +intel_de_read(struct intel_display *display, intel_reg_t reg) { u32 val; @@ -37,7 +37,7 @@ intel_de_read(struct intel_display *display, i915_reg_t reg) static inline u64 intel_de_read64_2x32_volatile(struct intel_display *display, - i915_reg_t lower_reg, i915_reg_t upper_reg) + intel_reg_t lower_reg, intel_reg_t upper_reg) { u64 val; @@ -54,9 +54,9 @@ intel_de_read64_2x32_volatile(struct intel_display *display, } static inline u64 -intel_de_read64_2x32(struct intel_display *display, i915_reg_t reg) +intel_de_read64_2x32(struct intel_display *display, intel_reg_t reg) { - i915_reg_t upper_reg = _MMIO(i915_mmio_reg_offset(reg) + 4); + intel_reg_t upper_reg = _MMIO(i915_mmio_reg_offset(reg) + 4); u32 lower, upper; lower = intel_de_read(display, reg); @@ -66,7 +66,7 @@ intel_de_read64_2x32(struct intel_display *display, i915_reg_t reg) } static inline void -intel_de_posting_read(struct intel_display *display, i915_reg_t reg) +intel_de_posting_read(struct intel_display *display, intel_reg_t reg) { intel_dmc_wl_get(display, reg); @@ -76,7 +76,7 @@ intel_de_posting_read(struct intel_display *display, i915_reg_t reg) } static inline void -intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val) +intel_de_write(struct intel_display *display, intel_reg_t reg, u32 val) { intel_dmc_wl_get(display, reg); @@ -86,7 +86,7 @@ intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val) } static inline u32 -intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) +intel_de_rmw(struct intel_display *display, intel_reg_t reg, u32 clear, u32 set) { u32 val; @@ -99,25 +99,25 @@ intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) return val; } -int intel_de_wait_us(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_us(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_us, u32 *out_value); -int intel_de_wait_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_ms(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value); -int intel_de_wait_fw_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_fw_ms(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_ms, u32 *out_value); -int intel_de_wait_fw_us_atomic(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_fw_us_atomic(struct intel_display *display, intel_reg_t reg, u32 mask, u32 value, unsigned int timeout_us, u32 *out_value); -int intel_de_wait_for_set_us(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_set_us(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_us); -int intel_de_wait_for_clear_us(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_clear_us(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_us); -int intel_de_wait_for_set_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_set_ms(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_ms); -int intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg, +int intel_de_wait_for_clear_ms(struct intel_display *display, intel_reg_t reg, u32 mask, unsigned int timeout_ms); /* @@ -129,7 +129,7 @@ int intel_de_wait_for_clear_ms(struct intel_display *display, i915_reg_t reg, * a more localised lock guarding all access to that bank of registers. */ static inline u32 -intel_de_read_fw(struct intel_display *display, i915_reg_t reg) +intel_de_read_fw(struct intel_display *display, intel_reg_t reg) { u32 val; @@ -140,14 +140,14 @@ intel_de_read_fw(struct intel_display *display, i915_reg_t reg) } static inline void -intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val) +intel_de_write_fw(struct intel_display *display, intel_reg_t reg, u32 val) { trace_i915_reg_rw(true, reg, val, sizeof(val), true); intel_uncore_write_fw(__to_uncore(display), reg, val); } static inline u32 -intel_de_rmw_fw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 set) +intel_de_rmw_fw(struct intel_display *display, intel_reg_t reg, u32 clear, u32 set) { u32 old, val; @@ -159,20 +159,20 @@ intel_de_rmw_fw(struct intel_display *display, i915_reg_t reg, u32 clear, u32 se } static inline u32 -intel_de_read_notrace(struct intel_display *display, i915_reg_t reg) +intel_de_read_notrace(struct intel_display *display, intel_reg_t reg) { return intel_uncore_read_notrace(__to_uncore(display), reg); } static inline void -intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val) +intel_de_write_notrace(struct intel_display *display, intel_reg_t reg, u32 val) { intel_uncore_write_notrace(__to_uncore(display), reg, val); } static __always_inline void intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb, - i915_reg_t reg, u32 val) + intel_reg_t reg, u32 val) { if (dsb) intel_dsb_reg_write(dsb, reg, val); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 2fa10f858279..30e68e3b9b11 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2579,8 +2579,8 @@ void intel_zero_m_n(struct intel_link_m_n *m_n) void intel_set_m_n(struct intel_display *display, const struct intel_link_m_n *m_n, - i915_reg_t data_m_reg, i915_reg_t data_n_reg, - i915_reg_t link_m_reg, i915_reg_t link_n_reg) + intel_reg_t data_m_reg, intel_reg_t data_n_reg, + intel_reg_t link_m_reg, intel_reg_t link_n_reg) { intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); intel_de_write(display, data_n_reg, m_n->data_n); @@ -3342,8 +3342,8 @@ int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) void intel_get_m_n(struct intel_display *display, struct intel_link_m_n *m_n, - i915_reg_t data_m_reg, i915_reg_t data_n_reg, - i915_reg_t link_m_reg, i915_reg_t link_n_reg) + intel_reg_t data_m_reg, intel_reg_t data_n_reg, + intel_reg_t link_m_reg, intel_reg_t link_n_reg) { m_n->link_m = intel_de_read(display, link_m_reg) & DATA_LINK_M_N_MASK; m_n->link_n = intel_de_read(display, link_n_reg) & DATA_LINK_M_N_MASK; diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 1e76a455d7c4..43b2d6de833c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -27,7 +27,7 @@ #include -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" #include "intel_display_limits.h" struct drm_atomic_state; @@ -426,12 +426,12 @@ bool intel_fuzzy_clock_check(int clock1, int clock2); void intel_zero_m_n(struct intel_link_m_n *m_n); void intel_set_m_n(struct intel_display *display, const struct intel_link_m_n *m_n, - i915_reg_t data_m_reg, i915_reg_t data_n_reg, - i915_reg_t link_m_reg, i915_reg_t link_n_reg); + intel_reg_t data_m_reg, intel_reg_t data_n_reg, + intel_reg_t link_m_reg, intel_reg_t link_n_reg); void intel_get_m_n(struct intel_display *display, struct intel_link_m_n *m_n, - i915_reg_t data_m_reg, i915_reg_t data_n_reg, - i915_reg_t link_m_reg, i915_reg_t link_n_reg); + intel_reg_t data_m_reg, intel_reg_t data_n_reg, + intel_reg_t link_m_reg, intel_reg_t link_n_reg); bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, enum transcoder transcoder); void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index b5bfdebc66ca..9bd72a99db2b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -47,7 +47,7 @@ static void irq_reset(struct intel_display *display, struct i915_irq_regs regs) /* * We should clear IMR at preinstall/uninstall, and just check at postinstall. */ -static void assert_iir_is_zero(struct intel_display *display, i915_reg_t reg) +static void assert_iir_is_zero(struct intel_display *display, intel_reg_t reg) { u32 val = intel_de_read(display, reg); @@ -343,7 +343,7 @@ u32 i915_pipestat_enable_mask(struct intel_display *display, void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask) { - i915_reg_t reg = PIPESTAT(display, pipe); + intel_reg_t reg = PIPESTAT(display, pipe); u32 enable_mask; drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, @@ -366,7 +366,7 @@ void i915_enable_pipestat(struct intel_display *display, void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask) { - i915_reg_t reg = PIPESTAT(display, pipe); + intel_reg_t reg = PIPESTAT(display, pipe); u32 enable_mask; drm_WARN_ONCE(display->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, @@ -543,7 +543,7 @@ void i9xx_pipestat_irq_ack(struct intel_display *display, } for_each_pipe(display, pipe) { - i915_reg_t reg; + intel_reg_t reg; u32 status_mask, enable_mask, iir_bit = 0; /* @@ -1284,7 +1284,7 @@ gen8_de_misc_irq_handler(struct intel_display *display, u32 iir) if (iir & GEN8_DE_EDP_PSR) { struct intel_encoder *encoder; u32 psr_iir; - i915_reg_t iir_reg; + intel_reg_t iir_reg; for_each_intel_encoder_with_psr(display->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 80ecf373fb19..751e6b7d4a29 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1069,7 +1069,7 @@ static void intel_power_domains_sync_hw(struct intel_display *display) static void gen9_dbuf_slice_set(struct intel_display *display, enum dbuf_slice slice, bool enable) { - i915_reg_t reg = DBUF_CTL_S(slice); + intel_reg_t reg = DBUF_CTL_S(slice); bool state; intel_de_rmw(display, reg, DBUF_POWER_REQUEST, @@ -1426,7 +1426,7 @@ static void hsw_disable_pc8(struct intel_display *display) static void intel_pch_reset_handshake(struct intel_display *display, bool enable) { - i915_reg_t reg; + intel_reg_t reg; u32 reset_bits; if (DISPLAY_VER(display) >= 35) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 6fbfd46461b0..04bd0dde5bed 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -49,10 +49,10 @@ static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_id } struct i915_power_well_regs { - i915_reg_t bios; - i915_reg_t driver; - i915_reg_t kvmr; - i915_reg_t debug; + intel_reg_t bios; + intel_reg_t driver; + intel_reg_t kvmr; + intel_reg_t debug; }; struct i915_power_well_ops { diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index 175334b41bba..cb46863693cd 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -8,6 +8,8 @@ #include "i915_reg_defs.h" +typedef i915_reg_t intel_reg_t; + #define VLV_DISPLAY_BASE 0x180000 /* diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index c81916761850..7fcee3ee319c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1662,7 +1662,7 @@ struct intel_plane { container_of_const((fb), struct intel_framebuffer, base) struct intel_hdmi { - i915_reg_t hdmi_reg; + intel_reg_t hdmi_reg; struct { enum drm_dp_dual_mode_type type; int max_tmds_clock; @@ -1792,7 +1792,7 @@ struct intel_psr { }; struct intel_dp { - i915_reg_t output_reg; + intel_reg_t output_reg; u32 DP; int link_rate; u8 lane_count; @@ -1889,8 +1889,8 @@ struct intel_dp { u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes, u32 aux_clock_divider); - i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); - i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); + intel_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp); + intel_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index); /* This is called before a link training is starterd */ void (*prepare_link_retrain)(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 0df4f42ba3e3..6a39ad19b339 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -71,7 +71,7 @@ struct intel_dmc { } dc6_allowed; struct dmc_fw_info { u32 mmio_count; - i915_reg_t mmioaddr[20]; + intel_reg_t mmioaddr[20]; u32 mmiodata[20]; u32 dmc_offset; u32 start_mmioaddr; @@ -434,7 +434,7 @@ static void gen9_set_dc_state_debugmask(struct intel_display *display) } static void disable_event_handler(struct intel_display *display, - i915_reg_t ctl_reg, i915_reg_t htp_reg) + intel_reg_t ctl_reg, intel_reg_t htp_reg) { intel_de_write(display, ctl_reg, REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, @@ -538,7 +538,7 @@ static u32 dmc_evt_ctl_disable(u32 dmc_evt_ctl) } static bool is_dmc_evt_ctl_reg(struct intel_display *display, - enum intel_dmc_id dmc_id, i915_reg_t reg) + enum intel_dmc_id dmc_id, intel_reg_t reg) { u32 offset = i915_mmio_reg_offset(reg); u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); @@ -548,7 +548,7 @@ static bool is_dmc_evt_ctl_reg(struct intel_display *display, } static bool is_dmc_evt_htp_reg(struct intel_display *display, - enum intel_dmc_id dmc_id, i915_reg_t reg) + enum intel_dmc_id dmc_id, intel_reg_t reg) { u32 offset = i915_mmio_reg_offset(reg); u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); @@ -560,7 +560,7 @@ static bool is_dmc_evt_htp_reg(struct intel_display *display, static bool is_event_handler(struct intel_display *display, enum intel_dmc_id dmc_id, unsigned int event_id, - i915_reg_t reg, u32 data) + intel_reg_t reg, u32 data) { return is_dmc_evt_ctl_reg(display, dmc_id, reg) && REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id; @@ -568,8 +568,8 @@ static bool is_event_handler(struct intel_display *display, static bool fixup_dmc_evt(struct intel_display *display, enum intel_dmc_id dmc_id, - i915_reg_t reg_ctl, u32 *data_ctl, - i915_reg_t reg_htp, u32 *data_htp) + intel_reg_t reg_ctl, u32 *data_ctl, + intel_reg_t reg_htp, u32 *data_htp) { if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl)) return false; @@ -613,7 +613,7 @@ static bool fixup_dmc_evt(struct intel_display *display, static bool disable_dmc_evt(struct intel_display *display, enum intel_dmc_id dmc_id, - i915_reg_t reg, u32 data) + intel_reg_t reg, u32 data) { if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) return false; @@ -696,7 +696,7 @@ static void assert_dmc_loaded(struct intel_display *display, dmc_id, expected, found); for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { - i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; + intel_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; found = intel_de_read(display, reg); expected = dmc_mmiodata(display, dmc, dmc_id, i); @@ -847,7 +847,7 @@ static void dmc_configure_event(struct intel_display *display, int i; for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { - i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; + intel_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; u32 data = dmc->dmc_info[dmc_id].mmiodata[i]; if (!is_event_handler(display, dmc_id, event_id, reg, data)) @@ -1618,7 +1618,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) struct intel_display *display = m->private; struct intel_dmc *dmc = display_to_dmc(display); struct ref_tracker *wakeref; - i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; + intel_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; u32 dc6_allowed_count; if (!HAS_DMC(display)) @@ -1647,7 +1647,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) DMC_VERSION_MINOR(dmc->version)); if (DISPLAY_VER(display) >= 12) { - i915_reg_t dc3co_reg; + intel_reg_t dc3co_reg; if (display->platform.dgfx || DISPLAY_VER(display) >= 14) { dc3co_reg = DG1_DMC_DEBUG3; diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c index ddf1a1f1ebc3..82afb60fa973 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -224,7 +224,7 @@ static void __intel_dmc_wl_take(struct intel_display *display) wl->taken = true; } -static bool intel_dmc_wl_reg_in_range(i915_reg_t reg, +static bool intel_dmc_wl_reg_in_range(intel_reg_t reg, const struct intel_dmc_wl_range ranges[]) { u32 offset = i915_mmio_reg_offset(reg); @@ -240,7 +240,7 @@ static bool intel_dmc_wl_reg_in_range(i915_reg_t reg, } static bool intel_dmc_wl_check_range(struct intel_display *display, - i915_reg_t reg, + intel_reg_t reg, u32 dc_state) { const struct intel_dmc_wl_range *ranges; @@ -431,7 +431,7 @@ void intel_dmc_wl_flush_release_work(struct intel_display *display) flush_delayed_work(&wl->work); } -void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg) +void intel_dmc_wl_get(struct intel_display *display, intel_reg_t reg) { struct intel_dmc_wl *wl = &display->wl; unsigned long flags; @@ -464,7 +464,7 @@ void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg) spin_unlock_irqrestore(&wl->lock, flags); } -void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg) +void intel_dmc_wl_put(struct intel_display *display, intel_reg_t reg) { struct intel_dmc_wl *wl = &display->wl; unsigned long flags; diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h b/drivers/gpu/drm/i915/display/intel_dmc_wl.h index 5488fbdf29b8..215107f0a4f9 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.h +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.h @@ -10,7 +10,7 @@ #include #include -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" struct intel_display; @@ -33,8 +33,8 @@ void intel_dmc_wl_init(struct intel_display *display); void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state); void intel_dmc_wl_disable(struct intel_display *display); void intel_dmc_wl_flush_release_work(struct intel_display *display); -void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg); -void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg); +void intel_dmc_wl_get(struct intel_display *display, intel_reg_t reg); +void intel_dmc_wl_put(struct intel_display *display, intel_reg_t reg); void intel_dmc_wl_get_noreg(struct intel_display *display); void intel_dmc_wl_put_noreg(struct intel_display *display); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5bdeed14267e..a2522dd0066b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5317,7 +5317,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder); + intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder); u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index b20ec3e589fa..ef33ecd81f28 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -58,7 +58,7 @@ static u32 intel_dp_aux_wait_done(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); + intel_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); const unsigned int timeout_ms = 10; u32 status; bool done; @@ -244,7 +244,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; - i915_reg_t ch_ctl, ch_data[5]; + intel_reg_t ch_ctl, ch_data[5]; u32 aux_clock_divider; enum intel_display_power_domain aux_domain; struct ref_tracker *aux_wakeref; @@ -554,7 +554,7 @@ intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) return ret; } -static i915_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp) +static intel_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -570,7 +570,7 @@ static i915_reg_t vlv_aux_ctl_reg(struct intel_dp *intel_dp) } } -static i915_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index) +static intel_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -586,7 +586,7 @@ static i915_reg_t vlv_aux_data_reg(struct intel_dp *intel_dp, int index) } } -static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) +static intel_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -602,7 +602,7 @@ static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) } } -static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) +static intel_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -618,7 +618,7 @@ static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) } } -static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) +static intel_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -636,7 +636,7 @@ static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) } } -static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) +static intel_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -654,7 +654,7 @@ static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) } } -static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) +static intel_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -673,7 +673,7 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) } } -static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) +static intel_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -692,7 +692,7 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) } } -static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) +static intel_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -714,7 +714,7 @@ static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) } } -static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) +static intel_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum aux_ch aux_ch = dig_port->aux_ch; @@ -736,7 +736,7 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) } } -static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) +static intel_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); @@ -756,7 +756,7 @@ static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) } } -static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) +static intel_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) { struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 68802b652316..8055f6ccc5c8 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -279,8 +279,8 @@ void bxt_port_to_phy_channel(struct intel_display *display, enum port port, * writes to the group register to write the same value to all the lanes. */ static u32 bxt_dpio_phy_rmw_grp(struct intel_display *display, - i915_reg_t reg_single, - i915_reg_t reg_group, + intel_reg_t reg_single, + intel_reg_t reg_group, u32 clear, u32 set) { u32 old, val; @@ -512,7 +512,7 @@ void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy) static bool __printf(6, 7) __phy_reg_verify_state(struct intel_display *display, enum dpio_phy phy, - i915_reg_t reg, u32 mask, u32 expected, + intel_reg_t reg, u32 mask, u32 expected, const char *reg_fmt, ...) { struct va_format vaf; @@ -1172,7 +1172,7 @@ void vlv_wait_port_ready(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); u32 port_mask; - i915_reg_t dpll_reg; + intel_reg_t dpll_reg; u32 val; switch (encoder->port) { diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index e97b38f5d98e..6acdfa97deaa 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -220,7 +220,7 @@ enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port p } } -static i915_reg_t +static intel_reg_t intel_combo_pll_enable_reg(struct intel_display *display, struct intel_dpll *pll) { @@ -233,7 +233,7 @@ intel_combo_pll_enable_reg(struct intel_display *display, return ICL_DPLL_ENABLE(pll->info->id); } -static i915_reg_t +static intel_reg_t intel_tc_pll_enable_reg(struct intel_display *display, struct intel_dpll *pll) { @@ -1350,7 +1350,7 @@ static const struct intel_dpll_mgr hsw_pll_mgr = { }; struct skl_dpll_regs { - i915_reg_t ctl, cfgcr1, cfgcr2; + intel_reg_t ctl, cfgcr1, cfgcr2; }; /* this array is indexed by the *shared* pll id */ @@ -3603,7 +3603,7 @@ static bool mg_pll_get_hw_state(struct intel_display *display, bool ret = false; u32 val; - i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); + intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_DISPLAY_CORE); @@ -3734,7 +3734,7 @@ static bool dkl_pll_get_hw_state(struct intel_display *display, static bool icl_pll_get_hw_state(struct intel_display *display, struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state, - i915_reg_t enable_reg) + intel_reg_t enable_reg) { struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; const enum intel_dpll_id id = pll->info->id; @@ -3796,7 +3796,7 @@ static bool combo_pll_get_hw_state(struct intel_display *display, struct intel_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) { - i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); + intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg); } @@ -3813,7 +3813,7 @@ static void icl_dpll_write(struct intel_display *display, const struct icl_dpll_hw_state *hw_state) { const enum intel_dpll_id id = pll->info->id; - i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG; + intel_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG; if (display->platform.alderlake_s) { cfgcr0_reg = ADLS_DPLL_CFGCR0(id); @@ -3960,7 +3960,7 @@ static void dkl_pll_write(struct intel_display *display, static void icl_pll_power_enable(struct intel_display *display, struct intel_dpll *pll, - i915_reg_t enable_reg) + intel_reg_t enable_reg) { intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE); @@ -3975,7 +3975,7 @@ static void icl_pll_power_enable(struct intel_display *display, static void icl_pll_enable(struct intel_display *display, struct intel_dpll *pll, - i915_reg_t enable_reg) + intel_reg_t enable_reg) { intel_de_rmw(display, enable_reg, 0, PLL_ENABLE); @@ -4013,7 +4013,7 @@ static void combo_pll_enable(struct intel_display *display, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; - i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); + intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); icl_pll_power_enable(display, pll, enable_reg); @@ -4058,7 +4058,7 @@ static void mg_pll_enable(struct intel_display *display, const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; - i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); + intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); icl_pll_power_enable(display, pll, enable_reg); @@ -4080,7 +4080,7 @@ static void mg_pll_enable(struct intel_display *display, static void icl_pll_disable(struct intel_display *display, struct intel_dpll *pll, - i915_reg_t enable_reg) + intel_reg_t enable_reg) { /* The first steps are done by intel_ddi_post_disable(). */ @@ -4112,7 +4112,7 @@ static void icl_pll_disable(struct intel_display *display, static void combo_pll_disable(struct intel_display *display, struct intel_dpll *pll) { - i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); + intel_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll); icl_pll_disable(display, pll, enable_reg); } @@ -4126,7 +4126,7 @@ static void icl_tbt_pll_disable(struct intel_display *display, static void mg_pll_disable(struct intel_display *display, struct intel_dpll *pll) { - i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); + intel_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll); icl_pll_disable(display, pll, enable_reg); } diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index c8d3968f659f..ce4d452ae695 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -326,7 +326,7 @@ static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw) } static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, - u32 opcode, i915_reg_t reg) + u32 opcode, intel_reg_t reg) { u32 prev_opcode, prev_reg; @@ -344,7 +344,7 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg); } -static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg) +static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, intel_reg_t reg) { return intel_dsb_prev_ins_is_write(dsb, DSB_OPCODE_INDEXED_WRITE << DSB_OPCODE_SHIFT, @@ -365,7 +365,7 @@ static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_ * register. */ void intel_dsb_reg_write_indexed(struct intel_dsb *dsb, - i915_reg_t reg, u32 val) + intel_reg_t reg, u32 val) { /* * For example the buffer will look like below for 3 dwords for auto @@ -402,7 +402,7 @@ void intel_dsb_reg_write_indexed(struct intel_dsb *dsb, } void intel_dsb_reg_write(struct intel_dsb *dsb, - i915_reg_t reg, u32 val) + intel_reg_t reg, u32 val) { intel_dsb_emit(dsb, val, (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | @@ -420,7 +420,7 @@ static u32 intel_dsb_mask_to_byte_en(u32 mask) /* Note: mask implemented via byte enables! */ void intel_dsb_reg_write_masked(struct intel_dsb *dsb, - i915_reg_t reg, u32 mask, u32 val) + intel_reg_t reg, u32 mask, u32 val) { intel_dsb_emit(dsb, val, (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | @@ -550,7 +550,7 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, } void intel_dsb_poll(struct intel_dsb *dsb, - i915_reg_t reg, u32 mask, u32 val, + intel_reg_t reg, u32 mask, u32 val, int wait_us, int count) { struct intel_crtc *crtc = dsb->crtc; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index 386a5a942572..3dcca9ed5371 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -8,7 +8,7 @@ #include -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" struct intel_atomic_state; struct intel_crtc; @@ -37,11 +37,11 @@ void intel_dsb_gosub_finish(struct intel_dsb *dsb); void intel_dsb_cleanup(struct intel_dsb *dsb); int intel_dsb_exec_time_us(void); void intel_dsb_reg_write(struct intel_dsb *dsb, - i915_reg_t reg, u32 val); + intel_reg_t reg, u32 val); void intel_dsb_reg_write_indexed(struct intel_dsb *dsb, - i915_reg_t reg, u32 val); + intel_reg_t reg, u32 val); void intel_dsb_reg_write_masked(struct intel_dsb *dsb, - i915_reg_t reg, u32 mask, u32 val); + intel_reg_t reg, u32 mask, u32 val); void intel_dsb_noop(struct intel_dsb *dsb, int count); void intel_dsb_nonpost_start(struct intel_dsb *dsb); void intel_dsb_nonpost_end(struct intel_dsb *dsb); @@ -59,7 +59,7 @@ void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, void intel_dsb_vblank_evade(struct intel_atomic_state *state, struct intel_dsb *dsb); void intel_dsb_poll(struct intel_dsb *dsb, - i915_reg_t reg, u32 mask, u32 val, + intel_reg_t reg, u32 mask, u32 val, int wait_us, int count); void intel_dsb_gosub(struct intel_dsb *dsb, struct intel_dsb *sub_dsb); diff --git a/drivers/gpu/drm/i915/display/intel_dvo_dev.h b/drivers/gpu/drm/i915/display/intel_dvo_dev.h index f1e939aaf7fa..1f049f79a534 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo_dev.h +++ b/drivers/gpu/drm/i915/display/intel_dvo_dev.h @@ -23,7 +23,7 @@ #ifndef __INTEL_DVO_DEV_H__ #define __INTEL_DVO_DEV_H__ -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" #include "intel_display_limits.h" diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index f5094655a63b..c41881a2be15 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -439,7 +439,7 @@ void intel_fdi_normal_train(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; u32 temp; /* enable normal train */ @@ -480,7 +480,7 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc, { struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; u32 temp, tries; /* @@ -581,7 +581,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, { struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; u32 temp, i, retry; /* @@ -716,7 +716,7 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, { struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; u32 temp, i, j; ivb_update_fdi_bc_bifurcation(crtc_state); @@ -997,7 +997,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state) struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; u32 temp; /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ @@ -1050,7 +1050,7 @@ void ilk_fdi_disable(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; u32 temp; /* disable CPU FDI tx and PCH FDI rx */ diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c index bf047180def9..02013e89d8f2 100644 --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c @@ -189,7 +189,7 @@ static bool cpt_can_enable_serr_int(struct intel_display *display) static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); - i915_reg_t reg = PIPESTAT(display, crtc->pipe); + intel_reg_t reg = PIPESTAT(display, crtc->pipe); u32 enable_mask; lockdep_assert_held(&display->irq.lock); @@ -209,7 +209,7 @@ static void i9xx_set_fifo_underrun_reporting(struct intel_display *display, enum pipe pipe, bool enable, bool old) { - i915_reg_t reg = PIPESTAT(display, pipe); + intel_reg_t reg = PIPESTAT(display, pipe); lockdep_assert_held(&display->irq.lock); diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index ea5cf8f51b31..049157c41fe2 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -48,7 +48,7 @@ struct intel_gmbus { #define GMBUS_FORCE_BIT_RETRY (1U << 31) u32 force_bit; u32 reg0; - i915_reg_t gpio_reg; + intel_reg_t gpio_reg; struct i2c_algo_bit_data bit_algo; struct intel_display *display; }; @@ -368,7 +368,7 @@ intel_gpio_post_xfer(struct i2c_adapter *adapter) } static void -intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) +intel_gpio_setup(struct intel_gmbus *bus, intel_reg_t gpio_reg) { struct i2c_algo_bit_data *algo; diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 25aca99682fd..e88fec24af49 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -46,7 +46,7 @@ intel_hdcp_adjust_hdcp_line_rekeying(struct intel_encoder *encoder, bool enable) { struct intel_display *display = to_intel_display(encoder); - i915_reg_t rekey_reg; + intel_reg_t rekey_reg; u32 rekey_bit = 0; /* Here we assume HDMI is in TMDS mode of operation */ diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 874076a29da4..a8eab7af3706 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -173,7 +173,7 @@ static u32 hsw_infoframe_enable(unsigned int type) } } -static i915_reg_t +static intel_reg_t hsw_dip_data_reg(struct intel_display *display, enum transcoder cpu_transcoder, unsigned int type, @@ -298,7 +298,7 @@ static void ibx_write_infoframe(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); const u32 *data = frame; struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); + intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); u32 val = intel_de_read(display, reg); int i; @@ -351,7 +351,7 @@ static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; - i915_reg_t reg = TVIDEO_DIP_CTL(pipe); + intel_reg_t reg = TVIDEO_DIP_CTL(pipe); u32 val = intel_de_read(display, reg); if ((val & VIDEO_DIP_ENABLE) == 0) @@ -373,7 +373,7 @@ static void cpt_write_infoframe(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); const u32 *data = frame; struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); + intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); u32 val = intel_de_read(display, reg); int i; @@ -447,7 +447,7 @@ static void vlv_write_infoframe(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); const u32 *data = frame; struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); + intel_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); u32 val = intel_de_read(display, reg); int i; @@ -523,7 +523,7 @@ void hsw_write_infoframe(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); const u32 *data = frame; enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder); + intel_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder); int data_size; int i; u32 val = intel_de_read(display, ctl_reg); @@ -884,7 +884,7 @@ static void g4x_set_infoframes(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &dig_port->hdmi; - i915_reg_t reg = VIDEO_DIP_CTL; + intel_reg_t reg = VIDEO_DIP_CTL; u32 val = intel_de_read(display, reg); u32 port = VIDEO_DIP_PORT(encoder->port); @@ -995,7 +995,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - i915_reg_t reg; + intel_reg_t reg; if ((crtc_state->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) @@ -1020,7 +1020,7 @@ void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - i915_reg_t reg; + intel_reg_t reg; if ((crtc_state->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) @@ -1069,7 +1069,7 @@ static void ibx_set_infoframes(struct intel_encoder *encoder, struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &dig_port->hdmi; - i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); + intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); u32 val = intel_de_read(display, reg); u32 port = VIDEO_DIP_PORT(encoder->port); @@ -1127,7 +1127,7 @@ static void cpt_set_infoframes(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); - i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); + intel_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); u32 val = intel_de_read(display, reg); assert_hdmi_port_disabled(intel_hdmi); @@ -1176,7 +1176,7 @@ static void vlv_set_infoframes(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); - i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); + intel_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); u32 val = intel_de_read(display, reg); u32 port = VIDEO_DIP_PORT(encoder->port); @@ -1231,7 +1231,7 @@ void intel_hdmi_fastset_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, + intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder); u32 val = intel_de_read(display, reg); @@ -1256,7 +1256,7 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(encoder); - i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, + intel_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder); u32 val = intel_de_read(display, reg); diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c index e2f9e1a2745f..615ee980470e 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c @@ -1007,7 +1007,7 @@ assert_dc_off(struct intel_display *display) static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder, int lane, u16 addr, u8 data, - i915_reg_t mac_reg_addr, + intel_reg_t mac_reg_addr, u8 expected_mac_val) { struct intel_display *display = to_intel_display(encoder); @@ -1062,7 +1062,7 @@ static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder, static void __intel_lt_phy_p2p_write(struct intel_encoder *encoder, int lane, u16 addr, u8 data, - i915_reg_t mac_reg_addr, + intel_reg_t mac_reg_addr, u8 expected_mac_val) { struct intel_display *display = to_intel_display(encoder); @@ -1086,7 +1086,7 @@ static void __intel_lt_phy_p2p_write(struct intel_encoder *encoder, static void intel_lt_phy_p2p_write(struct intel_encoder *encoder, u8 lane_mask, u16 addr, u8 data, - i915_reg_t mac_reg_addr, + intel_reg_t mac_reg_addr, u8 expected_mac_val) { int lane; diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index ab6ba08ac091..c8098104d853 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -70,7 +70,7 @@ struct intel_lvds_encoder { struct intel_encoder base; bool is_dual_link; - i915_reg_t reg; + intel_reg_t reg; u32 a3_power; struct intel_lvds_pps init_pps; @@ -85,7 +85,7 @@ static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder) } bool intel_lvds_port_enabled(struct intel_display *display, - i915_reg_t lvds_reg, enum pipe *pipe) + intel_reg_t lvds_reg, enum pipe *pipe) { u32 val; @@ -845,7 +845,7 @@ void intel_lvds_init(struct intel_display *display) struct intel_connector *connector; const struct drm_edid *drm_edid; struct intel_encoder *encoder; - i915_reg_t lvds_reg; + intel_reg_t lvds_reg; u32 lvds; u8 ddc_pin; diff --git a/drivers/gpu/drm/i915/display/intel_lvds.h b/drivers/gpu/drm/i915/display/intel_lvds.h index a6db1706a97c..6ac70d5e8ce6 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.h +++ b/drivers/gpu/drm/i915/display/intel_lvds.h @@ -8,20 +8,20 @@ #include -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" enum pipe; struct intel_display; #ifdef I915 bool intel_lvds_port_enabled(struct intel_display *display, - i915_reg_t lvds_reg, enum pipe *pipe); + intel_reg_t lvds_reg, enum pipe *pipe); void intel_lvds_init(struct intel_display *display); struct intel_encoder *intel_get_lvds_encoder(struct intel_display *display); bool intel_is_dual_link_lvds(struct intel_display *display); #else static inline bool intel_lvds_port_enabled(struct intel_display *display, - i915_reg_t lvds_reg, enum pipe *pipe) + intel_reg_t lvds_reg, enum pipe *pipe) { return false; } diff --git a/drivers/gpu/drm/i915/display/intel_mchbar.c b/drivers/gpu/drm/i915/display/intel_mchbar.c index a0d0a796c6bb..8cfcee4a08a4 100644 --- a/drivers/gpu/drm/i915/display/intel_mchbar.c +++ b/drivers/gpu/drm/i915/display/intel_mchbar.c @@ -41,7 +41,7 @@ static u32 mchbar_mirror_len(struct intel_display *display) return mchbar_mirror_end(display) - mchbar_mirror_base(display) + 1; } -static bool is_mchbar_reg(struct intel_display *display, i915_reg_t reg) +static bool is_mchbar_reg(struct intel_display *display, intel_reg_t reg) { return has_mchbar_mirror(display) && in_range32(i915_mmio_reg_offset(reg), @@ -49,28 +49,28 @@ static bool is_mchbar_reg(struct intel_display *display, i915_reg_t reg) mchbar_mirror_len(display)); } -static void assert_is_mchbar_reg(struct intel_display *display, i915_reg_t reg) +static void assert_is_mchbar_reg(struct intel_display *display, intel_reg_t reg) { drm_WARN(display->drm, !is_mchbar_reg(display, reg), "Reading non-MCHBAR register 0x%x\n", i915_mmio_reg_offset(reg)); } -u16 intel_mchbar_read16(struct intel_display *display, i915_reg_t reg) +u16 intel_mchbar_read16(struct intel_display *display, intel_reg_t reg) { assert_is_mchbar_reg(display, reg); return intel_de_read16(display, reg); } -u32 intel_mchbar_read(struct intel_display *display, i915_reg_t reg) +u32 intel_mchbar_read(struct intel_display *display, intel_reg_t reg) { assert_is_mchbar_reg(display, reg); return intel_de_read(display, reg); } -u64 intel_mchbar_read64_2x32(struct intel_display *display, i915_reg_t reg) +u64 intel_mchbar_read64_2x32(struct intel_display *display, intel_reg_t reg) { assert_is_mchbar_reg(display, reg); diff --git a/drivers/gpu/drm/i915/display/intel_mchbar.h b/drivers/gpu/drm/i915/display/intel_mchbar.h index fb645c64796c..1ced5dc8a8fd 100644 --- a/drivers/gpu/drm/i915/display/intel_mchbar.h +++ b/drivers/gpu/drm/i915/display/intel_mchbar.h @@ -10,12 +10,12 @@ #include -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" struct intel_display; -u16 intel_mchbar_read16(struct intel_display *display, i915_reg_t reg); -u32 intel_mchbar_read(struct intel_display *display, i915_reg_t reg); -u64 intel_mchbar_read64_2x32(struct intel_display *display, i915_reg_t reg); +u16 intel_mchbar_read16(struct intel_display *display, intel_reg_t reg); +u32 intel_mchbar_read(struct intel_display *display, intel_reg_t reg); +u64 intel_mchbar_read64_2x32(struct intel_display *display, intel_reg_t reg); #endif /* __INTEL_MCHBAR_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 69c7952a1413..2fcf6c9c84cc 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -40,7 +40,7 @@ enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) static void assert_pch_dp_disabled(struct intel_display *display, enum pipe pipe, enum port port, - i915_reg_t dp_reg) + intel_reg_t dp_reg) { enum pipe port_pipe; bool state; @@ -59,7 +59,7 @@ static void assert_pch_dp_disabled(struct intel_display *display, static void assert_pch_hdmi_disabled(struct intel_display *display, enum pipe pipe, enum port port, - i915_reg_t hdmi_reg) + intel_reg_t hdmi_reg) { enum pipe port_pipe; bool state; @@ -115,7 +115,7 @@ static void assert_pch_transcoder_disabled(struct intel_display *display, } static void ibx_sanitize_pch_hdmi_port(struct intel_display *display, - enum port port, i915_reg_t hdmi_reg) + enum port port, intel_reg_t hdmi_reg) { u32 val = intel_de_read(display, hdmi_reg); @@ -134,7 +134,7 @@ static void ibx_sanitize_pch_hdmi_port(struct intel_display *display, } static void ibx_sanitize_pch_dp_port(struct intel_display *display, - enum port port, i915_reg_t dp_reg) + enum port port, intel_reg_t dp_reg) { u32 val = intel_de_read(display, dp_reg); @@ -247,7 +247,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; u32 val, pipeconf_val; /* Make sure PCH DPLL is enabled */ @@ -313,7 +313,7 @@ static void ilk_disable_pch_transcoder(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe; - i915_reg_t reg; + intel_reg_t reg; /* FDI relies on the transcoder */ assert_fdi_tx_disabled(display, pipe); @@ -417,7 +417,7 @@ void ilk_pch_enable(struct intel_atomic_state *state, &crtc_state->hw.adjusted_mode; u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe)) & TRANSCONF_BPC_MASK) >> 5; - i915_reg_t reg = TRANS_DP_CTL(pipe); + intel_reg_t reg = TRANS_DP_CTL(pipe); enum port port; temp = intel_de_read(display, reg); diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 2d799af73bb7..ea5e8f75acef 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -488,11 +488,11 @@ void bxt_pps_reset_all(struct intel_display *display) } struct pps_registers { - i915_reg_t pp_ctrl; - i915_reg_t pp_stat; - i915_reg_t pp_on; - i915_reg_t pp_off; - i915_reg_t pp_div; + intel_reg_t pp_ctrl; + intel_reg_t pp_stat; + intel_reg_t pp_on; + intel_reg_t pp_off; + intel_reg_t pp_div; }; static void intel_pps_get_registers(struct intel_dp *intel_dp, @@ -523,7 +523,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, regs->pp_div = PP_DIVISOR(display, pps_idx); } -static i915_reg_t +static intel_reg_t _pp_ctrl_reg(struct intel_dp *intel_dp) { struct pps_registers regs; @@ -533,7 +533,7 @@ _pp_ctrl_reg(struct intel_dp *intel_dp) return regs.pp_ctrl; } -static i915_reg_t +static intel_reg_t _pp_stat_reg(struct intel_dp *intel_dp) { struct pps_registers regs; @@ -607,7 +607,7 @@ static void wait_panel_status(struct intel_dp *intel_dp, { struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - i915_reg_t pp_stat_reg, pp_ctrl_reg; + intel_reg_t pp_stat_reg, pp_ctrl_reg; int ret; u32 val; @@ -744,7 +744,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp) struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; - i915_reg_t pp_stat_reg, pp_ctrl_reg; + intel_reg_t pp_stat_reg, pp_ctrl_reg; bool need_to_disable = !intel_dp->pps.want_panel_vdd; if (!intel_dp_is_edp(intel_dp)) @@ -826,7 +826,7 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp) struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; - i915_reg_t pp_stat_reg, pp_ctrl_reg; + intel_reg_t pp_stat_reg, pp_ctrl_reg; lockdep_assert_held(&display->pps.mutex); @@ -955,7 +955,7 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); u32 pp; - i915_reg_t pp_ctrl_reg; + intel_reg_t pp_ctrl_reg; lockdep_assert_held(&display->pps.mutex); @@ -1028,7 +1028,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp) struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); u32 pp; - i915_reg_t pp_ctrl_reg; + intel_reg_t pp_ctrl_reg; lockdep_assert_held(&display->pps.mutex); @@ -1091,7 +1091,7 @@ void intel_pps_backlight_on(struct intel_dp *intel_dp) wait_backlight_on(intel_dp); with_intel_pps_lock(intel_dp) { - i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); + intel_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); u32 pp; pp = ilk_get_pp_control(intel_dp); @@ -1111,7 +1111,7 @@ void intel_pps_backlight_off(struct intel_dp *intel_dp) return; with_intel_pps_lock(intel_dp) { - i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); + intel_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); u32 pp; pp = ilk_get_pp_control(intel_dp); @@ -1155,7 +1155,7 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) struct intel_display *display = to_intel_display(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); enum pipe pipe = intel_dp->pps.vlv_pps_pipe; - i915_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe); + intel_reg_t pp_on_reg = PP_ON_DELAYS(display, pipe); drm_WARN_ON(display->drm, intel_dp->pps.vlv_active_pipe != INVALID_PIPE); @@ -1814,7 +1814,7 @@ void intel_pps_connector_debugfs_add(struct intel_connector *connector) void assert_pps_unlocked(struct intel_display *display, enum pipe pipe) { - i915_reg_t pp_reg; + intel_reg_t pp_reg; u32 val; enum pipe panel_pipe = INVALID_PIPE; bool locked = true; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index d1bae7d32617..248832f812cf 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -303,8 +303,8 @@ static u32 psr_irq_mask_get(struct intel_dp *intel_dp) EDP_PSR_MASK(intel_dp->psr.transcoder); } -static i915_reg_t psr_ctl_reg(struct intel_display *display, - enum transcoder cpu_transcoder) +static intel_reg_t psr_ctl_reg(struct intel_display *display, + enum transcoder cpu_transcoder) { if (DISPLAY_VER(display) >= 8) return EDP_PSR_CTL(display, cpu_transcoder); @@ -312,8 +312,8 @@ static i915_reg_t psr_ctl_reg(struct intel_display *display, return HSW_SRD_CTL; } -static i915_reg_t psr_debug_reg(struct intel_display *display, - enum transcoder cpu_transcoder) +static intel_reg_t psr_debug_reg(struct intel_display *display, + enum transcoder cpu_transcoder) { if (DISPLAY_VER(display) >= 8) return EDP_PSR_DEBUG(display, cpu_transcoder); @@ -321,8 +321,8 @@ static i915_reg_t psr_debug_reg(struct intel_display *display, return HSW_SRD_DEBUG; } -static i915_reg_t psr_perf_cnt_reg(struct intel_display *display, - enum transcoder cpu_transcoder) +static intel_reg_t psr_perf_cnt_reg(struct intel_display *display, + enum transcoder cpu_transcoder) { if (DISPLAY_VER(display) >= 8) return EDP_PSR_PERF_CNT(display, cpu_transcoder); @@ -330,8 +330,8 @@ static i915_reg_t psr_perf_cnt_reg(struct intel_display *display, return HSW_SRD_PERF_CNT; } -static i915_reg_t psr_status_reg(struct intel_display *display, - enum transcoder cpu_transcoder) +static intel_reg_t psr_status_reg(struct intel_display *display, + enum transcoder cpu_transcoder) { if (DISPLAY_VER(display) >= 8) return EDP_PSR_STATUS(display, cpu_transcoder); @@ -339,8 +339,8 @@ static i915_reg_t psr_status_reg(struct intel_display *display, return HSW_SRD_STATUS; } -static i915_reg_t psr_imr_reg(struct intel_display *display, - enum transcoder cpu_transcoder) +static intel_reg_t psr_imr_reg(struct intel_display *display, + enum transcoder cpu_transcoder) { if (DISPLAY_VER(display) >= 12) return TRANS_PSR_IMR(display, cpu_transcoder); @@ -348,8 +348,8 @@ static i915_reg_t psr_imr_reg(struct intel_display *display, return EDP_PSR_IMR; } -static i915_reg_t psr_iir_reg(struct intel_display *display, - enum transcoder cpu_transcoder) +static intel_reg_t psr_iir_reg(struct intel_display *display, + enum transcoder cpu_transcoder) { if (DISPLAY_VER(display) >= 12) return TRANS_PSR_IIR(display, cpu_transcoder); @@ -357,8 +357,8 @@ static i915_reg_t psr_iir_reg(struct intel_display *display, return EDP_PSR_IIR; } -static i915_reg_t psr_aux_ctl_reg(struct intel_display *display, - enum transcoder cpu_transcoder) +static intel_reg_t psr_aux_ctl_reg(struct intel_display *display, + enum transcoder cpu_transcoder) { if (DISPLAY_VER(display) >= 8) return EDP_PSR_AUX_CTL(display, cpu_transcoder); @@ -366,8 +366,8 @@ static i915_reg_t psr_aux_ctl_reg(struct intel_display *display, return HSW_SRD_AUX_CTL; } -static i915_reg_t psr_aux_data_reg(struct intel_display *display, - enum transcoder cpu_transcoder, int i) +static intel_reg_t psr_aux_data_reg(struct intel_display *display, + enum transcoder cpu_transcoder, int i) { if (DISPLAY_VER(display) >= 8) return EDP_PSR_AUX_DATA(display, cpu_transcoder, i); @@ -2319,7 +2319,7 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; - i915_reg_t psr_status; + intel_reg_t psr_status; u32 psr_status_mask; if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || @@ -3350,7 +3350,7 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; - i915_reg_t reg; + intel_reg_t reg; u32 mask; int err; diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index c18e7d5e9c34..9803d6dc7be4 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -101,7 +101,7 @@ struct intel_sdvo { struct intel_sdvo_ddc ddc[3]; /* Register for the SDVO device: SDVOB or SDVOC */ - i915_reg_t sdvo_reg; + intel_reg_t sdvo_reg; /* * Capabilities of the SDVO device returned by @@ -1666,7 +1666,7 @@ static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) } bool intel_sdvo_port_enabled(struct intel_display *display, - i915_reg_t sdvo_reg, enum pipe *pipe) + intel_reg_t sdvo_reg, enum pipe *pipe) { u32 val; @@ -3382,7 +3382,7 @@ static bool assert_sdvo_port_valid(struct intel_display *display, enum port port } bool intel_sdvo_init(struct intel_display *display, - i915_reg_t sdvo_reg, enum port port) + intel_reg_t sdvo_reg, enum port port) { struct intel_encoder *intel_encoder; struct intel_sdvo *intel_sdvo; diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.h b/drivers/gpu/drm/i915/display/intel_sdvo.h index 1a9e40fdd8a8..d1e1083de037 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.h +++ b/drivers/gpu/drm/i915/display/intel_sdvo.h @@ -8,7 +8,7 @@ #include -#include "i915_reg_defs.h" +#include "intel_display_reg_defs.h" enum pipe; enum port; @@ -16,17 +16,17 @@ struct intel_display; #ifdef I915 bool intel_sdvo_port_enabled(struct intel_display *display, - i915_reg_t sdvo_reg, enum pipe *pipe); + intel_reg_t sdvo_reg, enum pipe *pipe); bool intel_sdvo_init(struct intel_display *display, - i915_reg_t reg, enum port port); + intel_reg_t reg, enum port port); #else static inline bool intel_sdvo_port_enabled(struct intel_display *display, - i915_reg_t sdvo_reg, enum pipe *pipe) + intel_reg_t sdvo_reg, enum pipe *pipe) { return false; } static inline bool intel_sdvo_init(struct intel_display *display, - i915_reg_t reg, enum port port) + intel_reg_t reg, enum port port) { return false; } diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index 5e5dde8f3e3a..bf9df566630f 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -1822,7 +1822,7 @@ void intel_mpllb_enable(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb; enum phy phy = intel_encoder_to_phy(encoder); - i915_reg_t enable_reg = (phy <= PHY_D ? + intel_reg_t enable_reg = (phy <= PHY_D ? DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); /* @@ -1879,7 +1879,7 @@ void intel_mpllb_disable(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - i915_reg_t enable_reg = (phy <= PHY_D ? + intel_reg_t enable_reg = (phy <= PHY_D ? DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0)); /* diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index a21dd4e3fe4c..ef1cf62749ec 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -294,7 +294,7 @@ get_pin_assignment(struct intel_tc_port *tc) struct intel_display *display = to_intel_display(tc->dig_port); enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); enum intel_tc_pin_assignment pin_assignment; - i915_reg_t reg; + intel_reg_t reg; u32 mask; u32 val; @@ -1034,7 +1034,7 @@ xelpdp_tc_phy_tcss_power_is_enabled(struct intel_tc_port *tc) { struct intel_display *display = to_intel_display(tc->dig_port); enum port port = tc->dig_port->base.port; - i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); + intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); assert_tc_cold_blocked(tc); @@ -1094,7 +1094,7 @@ static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool ena { struct intel_display *display = to_intel_display(tc->dig_port); enum port port = tc->dig_port->base.port; - i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); + intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); u32 val; assert_tc_cold_blocked(tc); @@ -1141,7 +1141,7 @@ static void xelpdp_tc_phy_take_ownership(struct intel_tc_port *tc, bool take) { struct intel_display *display = to_intel_display(tc->dig_port); enum port port = tc->dig_port->base.port; - i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); + intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); u32 val; assert_tc_cold_blocked(tc); @@ -1158,7 +1158,7 @@ static bool xelpdp_tc_phy_is_owned(struct intel_tc_port *tc) { struct intel_display *display = to_intel_display(tc->dig_port); enum port port = tc->dig_port->base.port; - i915_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); + intel_reg_t reg = XELPDP_PORT_BUF_CTL1(display, port); assert_tc_cold_blocked(tc); diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 0726a2abed38..28d81199792e 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -482,7 +482,7 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc) static bool pipe_scanline_is_moving(struct intel_display *display, enum pipe pipe) { - i915_reg_t reg = PIPEDSL(display, pipe); + intel_reg_t reg = PIPEDSL(display, pipe); u32 line1, line2; line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK; diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 6c09c6d99ffe..8f06c3a4d56d 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -483,7 +483,7 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state) } static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps, - i915_reg_t *dsc_reg, int dsc_reg_num) + intel_reg_t *dsc_reg, int dsc_reg_num) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; @@ -506,7 +506,7 @@ static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state, int pps, u32 pps_val) { struct intel_display *display = to_intel_display(crtc_state); - i915_reg_t dsc_reg[3]; + intel_reg_t dsc_reg[3]; int i, vdsc_per_pipe, dsc_reg_num; vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); @@ -843,13 +843,13 @@ void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_en intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val); } -static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) +static intel_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) { return is_pipe_dsc(crtc, cpu_transcoder) ? ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1; } -static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) +static intel_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder) { return is_pipe_dsc(crtc, cpu_transcoder) ? ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2; @@ -929,7 +929,7 @@ static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps, bool *all_equal) { struct intel_display *display = to_intel_display(crtc_state); - i915_reg_t dsc_reg[3]; + intel_reg_t dsc_reg[3]; int i, vdsc_per_pipe, dsc_reg_num; u32 val; diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index 9832a4ade318..4966fd7eea92 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -35,7 +35,7 @@ static bool intel_vga_decode_is_enabled(struct intel_display *display) return !(gmch_ctrl & INTEL_GMCH_VGA_DISABLE); } -static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display) +static intel_reg_t intel_vga_cntrl_reg(struct intel_display *display) { if (display->platform.valleyview || display->platform.cherryview) return VLV_VGACNTRL; @@ -179,7 +179,7 @@ static void intel_vga_write(struct intel_display *display, u16 reg, u8 val, bool void intel_vga_disable(struct intel_display *display) { struct pci_dev *pdev = to_pci_dev(display->drm->dev); - i915_reg_t vga_reg = intel_vga_cntrl_reg(display); + intel_reg_t vga_reg = intel_vga_cntrl_reg(display); bool mmio = has_vga_mmio_access(display); bool io_decode; u8 msr, sr1; diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index 76e8cd0f65a4..877eab75f19a 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -99,7 +99,7 @@ void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) } static void write_data(struct intel_display *display, - i915_reg_t reg, + intel_reg_t reg, const u8 *data, u32 len) { u32 i, j; @@ -115,7 +115,7 @@ static void write_data(struct intel_display *display, } static void read_data(struct intel_display *display, - i915_reg_t reg, + intel_reg_t reg, u8 *data, u32 len) { u32 i, j; @@ -138,7 +138,7 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, struct mipi_dsi_packet packet; ssize_t ret; const u8 *header; - i915_reg_t data_reg, ctrl_reg; + intel_reg_t data_reg, ctrl_reg; u32 data_mask, ctrl_mask; ret = mipi_dsi_create_packet(&packet, msg); @@ -559,7 +559,7 @@ static void glk_dsi_clear_device_ready(struct intel_encoder *encoder) glk_dsi_disable_mipi_io(encoder); } -static i915_reg_t port_ctrl_reg(struct intel_display *display, enum port port) +static intel_reg_t port_ctrl_reg(struct intel_display *display, enum port port) { return display->platform.geminilake || display->platform.broxton ? BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(port); @@ -574,7 +574,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) drm_dbg_kms(display->drm, "\n"); for_each_dsi_port(port, intel_dsi->ports) { /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ - i915_reg_t port_ctrl = display->platform.broxton ? + intel_reg_t port_ctrl = display->platform.broxton ? BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A); intel_de_write(display, MIPI_DEVICE_READY(display, port), @@ -631,7 +631,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, } for_each_dsi_port(port, intel_dsi->ports) { - i915_reg_t port_ctrl = port_ctrl_reg(display, port); + intel_reg_t port_ctrl = port_ctrl_reg(display, port); u32 temp; temp = intel_de_read(display, port_ctrl); @@ -666,7 +666,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) enum port port; for_each_dsi_port(port, intel_dsi->ports) { - i915_reg_t port_ctrl = port_ctrl_reg(display, port); + intel_reg_t port_ctrl = port_ctrl_reg(display, port); /* de-assert ip_tg_enable signal */ intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0); @@ -957,7 +957,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, /* XXX: this only works for one DSI output */ for_each_dsi_port(port, intel_dsi->ports) { - i915_reg_t port_ctrl = port_ctrl_reg(display, port); + intel_reg_t port_ctrl = port_ctrl_reg(display, port); bool enabled = intel_de_read(display, port_ctrl) & DPI_ENABLE; /* From 7091eef6443bf51c215d8a7ff77252bb7390f605 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 5 May 2026 12:16:46 +0300 Subject: [PATCH 35/38] drm/i915/display: add struct intel_irq_regs and use it MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add struct intel_irq_regs, a display version of struct i915_irq_regs, and use it. The goal is to reduce the dependency on i915 core types and headers. Reviewed-by: Michał Grzelak Acked-by: Ville Syrjälä Link: https://patch.msgid.link/56118c2e40e171e898034a7bea6c8d14f515f5c1.1777972548.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- .../gpu/drm/i915/display/intel_display_irq.c | 4 +- .../drm/i915/display/intel_display_reg_defs.h | 10 ++++ .../gpu/drm/i915/display/intel_display_regs.h | 48 +++++++++---------- 3 files changed, 36 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 9bd72a99db2b..0c9c21b1290b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -30,7 +30,7 @@ #include "intel_psr.h" #include "intel_psr_regs.h" -static void irq_reset(struct intel_display *display, struct i915_irq_regs regs) +static void irq_reset(struct intel_display *display, struct intel_irq_regs regs) { intel_de_write(display, regs.imr, 0xffffffff); intel_de_posting_read(display, regs.imr); @@ -63,7 +63,7 @@ static void assert_iir_is_zero(struct intel_display *display, intel_reg_t reg) intel_de_posting_read(display, reg); } -static void irq_init(struct intel_display *display, struct i915_irq_regs regs, +static void irq_init(struct intel_display *display, struct intel_irq_regs regs, u32 imr_val, u32 ier_val) { assert_iir_is_zero(display, regs.iir); diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index cb46863693cd..d044967aa6d9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -10,6 +10,16 @@ typedef i915_reg_t intel_reg_t; +/* A triplet for IMR/IER/IIR registers. */ +struct intel_irq_regs { + intel_reg_t imr; + intel_reg_t ier; + intel_reg_t iir; +}; + +#define INTEL_IRQ_REGS(_imr, _ier, _iir) \ + ((const struct intel_irq_regs){ .imr = (_imr), .ier = (_ier), .iir = (_iir) }) + #define VLV_DISPLAY_BASE 0x180000 /* diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index bc508995ad8b..d1387d98e364 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -105,9 +105,9 @@ #define ERR_INT_FIFO_UNDERRUN_A (1 << 0) #define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3)) -#define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \ - VLV_IER, \ - VLV_IIR) +#define VLV_IRQ_REGS INTEL_IRQ_REGS(VLV_IMR, \ + VLV_IER, \ + VLV_IIR) #define VLV_EIR _MMIO(VLV_DISPLAY_BASE + 0x20b0) #define VLV_EMR _MMIO(VLV_DISPLAY_BASE + 0x20b4) @@ -1147,9 +1147,9 @@ #define DEIIR _MMIO(0x44008) #define DEIER _MMIO(0x4400c) -#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \ - DEIER, \ - DEIIR) +#define DE_IRQ_REGS INTEL_IRQ_REGS(DEIMR, \ + DEIER, \ + DEIIR) #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) @@ -1438,9 +1438,9 @@ #define GEN8_PIPE_VSYNC REG_BIT(1) #define GEN8_PIPE_VBLANK REG_BIT(0) -#define GEN8_DE_PIPE_IRQ_REGS(pipe) I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \ - GEN8_DE_PIPE_IER(pipe), \ - GEN8_DE_PIPE_IIR(pipe)) +#define GEN8_DE_PIPE_IRQ_REGS(pipe) INTEL_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \ + GEN8_DE_PIPE_IER(pipe), \ + GEN8_DE_PIPE_IIR(pipe)) #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A) #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1) @@ -1477,9 +1477,9 @@ #define TGL_DE_PORT_AUX_DDIB REG_BIT(1) #define TGL_DE_PORT_AUX_DDIA REG_BIT(0) -#define GEN8_DE_PORT_IRQ_REGS I915_IRQ_REGS(GEN8_DE_PORT_IMR, \ - GEN8_DE_PORT_IER, \ - GEN8_DE_PORT_IIR) +#define GEN8_DE_PORT_IRQ_REGS INTEL_IRQ_REGS(GEN8_DE_PORT_IMR, \ + GEN8_DE_PORT_IER, \ + GEN8_DE_PORT_IIR) /* interrupts */ #define DE_MASTER_IRQ_CONTROL (1 << 31) @@ -1530,9 +1530,9 @@ #define XELPDP_PMDEMAND_RSP REG_BIT(3) #define XE2LPD_DBUF_OVERLAP_DETECTED REG_BIT(1) -#define GEN8_DE_MISC_IRQ_REGS I915_IRQ_REGS(GEN8_DE_MISC_IMR, \ - GEN8_DE_MISC_IER, \ - GEN8_DE_MISC_IIR) +#define GEN8_DE_MISC_IRQ_REGS INTEL_IRQ_REGS(GEN8_DE_MISC_IMR, \ + GEN8_DE_MISC_IER, \ + GEN8_DE_MISC_IIR) #define GEN11_DISPLAY_INT_CTL _MMIO(0x44200) #define GEN11_DISPLAY_IRQ_ENABLE (1 << 31) @@ -1564,9 +1564,9 @@ GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \ GEN11_TBT_HOTPLUG(HPD_PORT_TC1)) -#define GEN11_DE_HPD_IRQ_REGS I915_IRQ_REGS(GEN11_DE_HPD_IMR, \ - GEN11_DE_HPD_IER, \ - GEN11_DE_HPD_IIR) +#define GEN11_DE_HPD_IRQ_REGS INTEL_IRQ_REGS(GEN11_DE_HPD_IMR, \ + GEN11_DE_HPD_IER, \ + GEN11_DE_HPD_IIR) #define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030) #define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038) @@ -1588,9 +1588,9 @@ #define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin)) #define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0) -#define PICAINTERRUPT_IRQ_REGS I915_IRQ_REGS(PICAINTERRUPT_IMR, \ - PICAINTERRUPT_IER, \ - PICAINTERRUPT_IIR) +#define PICAINTERRUPT_IRQ_REGS INTEL_IRQ_REGS(PICAINTERRUPT_IMR, \ + PICAINTERRUPT_IER, \ + PICAINTERRUPT_IIR) #define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200)) #define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6) @@ -1906,9 +1906,9 @@ #define SDEIIR _MMIO(0xc4008) #define SDEIER _MMIO(0xc400c) -#define SDE_IRQ_REGS I915_IRQ_REGS(SDEIMR, \ - SDEIER, \ - SDEIIR) +#define SDE_IRQ_REGS INTEL_IRQ_REGS(SDEIMR, \ + SDEIER, \ + SDEIIR) #define SERR_INT _MMIO(0xc4040) #define SERR_INT_POISON (1 << 31) From 1abb4a4e6dca55f2557f345dedec2c7a7045f64d Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 5 May 2026 12:16:47 +0300 Subject: [PATCH 36/38] drm/i915/display: add struct intel_error_regs and use it MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add struct intel_error_regs, a display version of struct i915_error_regs, and use it. The goal is to reduce the dependency on i915 core types and headers. Reviewed-by: Michał Grzelak Acked-by: Ville Syrjälä Link: https://patch.msgid.link/7f909c6b1f7ae623792b5abc3d31d4a682006e24.1777972548.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 4 ++-- drivers/gpu/drm/i915/display/intel_display_reg_defs.h | 8 ++++++++ drivers/gpu/drm/i915/display/intel_display_regs.h | 2 +- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 0c9c21b1290b..b679992cb1e6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -73,7 +73,7 @@ static void irq_init(struct intel_display *display, struct intel_irq_regs regs, intel_de_posting_read(display, regs.imr); } -static void error_reset(struct intel_display *display, struct i915_error_regs regs) +static void error_reset(struct intel_display *display, struct intel_error_regs regs) { intel_de_write(display, regs.emr, 0xffffffff); intel_de_posting_read(display, regs.emr); @@ -84,7 +84,7 @@ static void error_reset(struct intel_display *display, struct i915_error_regs re intel_de_posting_read(display, regs.eir); } -static void error_init(struct intel_display *display, struct i915_error_regs regs, +static void error_init(struct intel_display *display, struct intel_error_regs regs, u32 emr_val) { intel_de_write(display, regs.eir, 0xffffffff); diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index d044967aa6d9..a56f8ed055f6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -20,6 +20,14 @@ struct intel_irq_regs { #define INTEL_IRQ_REGS(_imr, _ier, _iir) \ ((const struct intel_irq_regs){ .imr = (_imr), .ier = (_ier), .iir = (_iir) }) +struct intel_error_regs { + intel_reg_t emr; + intel_reg_t eir; +}; + +#define INTEL_ERROR_REGS(_emr, _eir) \ + ((const struct intel_error_regs){ .emr = (_emr), .eir = (_eir) }) + #define VLV_DISPLAY_BASE 0x180000 /* diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index d1387d98e364..4321f8b529da 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -117,7 +117,7 @@ #define VLV_ERROR_PAGE_TABLE (1 << 4) #define VLV_ERROR_CLAIM (1 << 0) -#define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR) +#define VLV_ERROR_REGS INTEL_ERROR_REGS(VLV_EMR, VLV_EIR) #define _MBUS_ABOX0_CTL 0x45038 #define _MBUS_ABOX1_CTL 0x45048 From d1dc0c08e25172819c0490791f48490a6c43b58e Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 5 May 2026 12:16:48 +0300 Subject: [PATCH 37/38] drm/i915/display: define and use intel_reg_{offset, equal, valid}() helpers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add display specific helpers for getting the register offset, checking for equality and validity. Add them as static inlines for increased type safety. Reviewed-by: Michał Grzelak Acked-by: Ville Syrjälä Link: https://patch.msgid.link/7fe12d4e5465778209ccf29359767a197b031dd9.1777972548.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_de.h | 2 +- .../drm/i915/display/intel_display_device.c | 2 +- .../gpu/drm/i915/display/intel_display_irq.c | 2 +- .../drm/i915/display/intel_display_reg_defs.h | 15 +++++++++++ .../drm/i915/display/intel_display_types.h | 4 +-- drivers/gpu/drm/i915/display/intel_dmc.c | 26 +++++++++---------- drivers/gpu/drm/i915/display/intel_dmc_wl.c | 6 ++--- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 +-- drivers/gpu/drm/i915/display/intel_dsb.c | 10 +++---- drivers/gpu/drm/i915/display/intel_mchbar.c | 4 +-- drivers/gpu/drm/i915/display/intel_pps.c | 6 ++--- 11 files changed, 48 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h index d17f14843f98..102979019429 100644 --- a/drivers/gpu/drm/i915/display/intel_de.h +++ b/drivers/gpu/drm/i915/display/intel_de.h @@ -56,7 +56,7 @@ intel_de_read64_2x32_volatile(struct intel_display *display, static inline u64 intel_de_read64_2x32(struct intel_display *display, intel_reg_t reg) { - intel_reg_t upper_reg = _MMIO(i915_mmio_reg_offset(reg) + 4); + intel_reg_t upper_reg = _MMIO(intel_reg_offset(reg) + 4); u32 lower, upper; lower = intel_de_read(display, reg); diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 7260990038dd..69a9f782935c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -1525,7 +1525,7 @@ probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver * u32 val; int i; - addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); + addr = pci_iomap_range(pdev, 0, intel_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); if (!addr) { drm_err(display->drm, "Cannot map MMIO BAR to read display GMD_ID\n"); diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index b679992cb1e6..27fb72e5cefb 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -56,7 +56,7 @@ static void assert_iir_is_zero(struct intel_display *display, intel_reg_t reg) drm_WARN(display->drm, 1, "Interrupt register 0x%x is not zero: 0x%08x\n", - i915_mmio_reg_offset(reg), val); + intel_reg_offset(reg), val); intel_de_write(display, reg, 0xffffffff); intel_de_posting_read(display, reg); intel_de_write(display, reg, 0xffffffff); diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index a56f8ed055f6..9220fcbfcb24 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -10,6 +10,21 @@ typedef i915_reg_t intel_reg_t; +static inline u32 intel_reg_offset(intel_reg_t r) +{ + return r.reg; +} + +static inline bool intel_reg_equal(intel_reg_t a, intel_reg_t b) +{ + return intel_reg_offset(a) == intel_reg_offset(b); +} + +static inline bool intel_reg_valid(intel_reg_t r) +{ + return !intel_reg_equal(r, INVALID_MMIO_REG); +} + /* A triplet for IMR/IER/IIR registers. */ struct intel_irq_regs { intel_reg_t imr; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 7fcee3ee319c..c9e69f8a3626 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -2117,7 +2117,7 @@ static inline bool intel_encoder_is_dp(struct intel_encoder *encoder) return true; case INTEL_OUTPUT_DDI: /* Skip pure HDMI/DVI DDI encoders */ - return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg); + return intel_reg_valid(enc_to_intel_dp(encoder)->output_reg); default: return false; } @@ -2130,7 +2130,7 @@ static inline bool intel_encoder_is_hdmi(struct intel_encoder *encoder) return true; case INTEL_OUTPUT_DDI: /* See if the HDMI encoder is valid. */ - return i915_mmio_reg_valid(enc_to_intel_hdmi(encoder)->hdmi_reg); + return intel_reg_valid(enc_to_intel_hdmi(encoder)->hdmi_reg); default: return false; } diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 6a39ad19b339..481fb65b7110 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -540,9 +540,9 @@ static u32 dmc_evt_ctl_disable(u32 dmc_evt_ctl) static bool is_dmc_evt_ctl_reg(struct intel_display *display, enum intel_dmc_id dmc_id, intel_reg_t reg) { - u32 offset = i915_mmio_reg_offset(reg); - u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); - u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); + u32 offset = intel_reg_offset(reg); + u32 start = intel_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); + u32 end = intel_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); return offset >= start && offset < end; } @@ -550,9 +550,9 @@ static bool is_dmc_evt_ctl_reg(struct intel_display *display, static bool is_dmc_evt_htp_reg(struct intel_display *display, enum intel_dmc_id dmc_id, intel_reg_t reg) { - u32 offset = i915_mmio_reg_offset(reg); - u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); - u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); + u32 offset = intel_reg_offset(reg); + u32 start = intel_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); + u32 end = intel_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); return offset >= start && offset < end; } @@ -578,8 +578,8 @@ static bool fixup_dmc_evt(struct intel_display *display, return false; /* make sure reg_ctl and reg_htp are for the same event */ - if (i915_mmio_reg_offset(reg_ctl) - i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) != - i915_mmio_reg_offset(reg_htp) - i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0))) + if (intel_reg_offset(reg_ctl) - intel_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) != + intel_reg_offset(reg_htp) - intel_reg_offset(DMC_EVT_HTP(display, dmc_id, 0))) return false; /* @@ -703,7 +703,7 @@ static void assert_dmc_loaded(struct intel_display *display, drm_WARN(display->drm, found != expected, "DMC %d mmio[%d]/0x%x incorrect (expected 0x%x, current 0x%x)\n", - dmc_id, i, i915_mmio_reg_offset(reg), expected, found); + dmc_id, i, intel_reg_offset(reg), expected, found); } } @@ -1146,17 +1146,17 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc, drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_CTL)\n", - i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]), + i, intel_reg_offset(dmc_info->mmioaddr[i]), orig_mmiodata[0], dmc_info->mmiodata[i]); drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_HTP)\n", - i+1, i915_mmio_reg_offset(dmc_info->mmioaddr[i+1]), + i+1, intel_reg_offset(dmc_info->mmioaddr[i+1]), orig_mmiodata[1], dmc_info->mmiodata[i+1]); } for (i = 0; i < mmio_count; i++) { drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", - i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]), dmc_info->mmiodata[i], + i, intel_reg_offset(dmc_info->mmioaddr[i]), dmc_info->mmiodata[i], is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], @@ -1672,7 +1672,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count)) seq_printf(m, "DC5 -> DC6 allowed count: %d\n", dc6_allowed_count); - else if (i915_mmio_reg_valid(dc6_reg)) + else if (intel_reg_valid(dc6_reg)) seq_printf(m, "DC5 -> DC6 count: %d\n", intel_de_read(display, dc6_reg)); diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c index 82afb60fa973..605a4a555601 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -227,7 +227,7 @@ static void __intel_dmc_wl_take(struct intel_display *display) static bool intel_dmc_wl_reg_in_range(intel_reg_t reg, const struct intel_dmc_wl_range ranges[]) { - u32 offset = i915_mmio_reg_offset(reg); + u32 offset = intel_reg_offset(reg); for (int i = 0; ranges[i].start; i++) { u32 end = ranges[i].end ?: ranges[i].start; @@ -441,7 +441,7 @@ void intel_dmc_wl_get(struct intel_display *display, intel_reg_t reg) spin_lock_irqsave(&wl->lock, flags); - if (i915_mmio_reg_valid(reg) && + if (intel_reg_valid(reg) && !intel_dmc_wl_check_range(display, reg, wl->dc_state)) goto out_unlock; @@ -474,7 +474,7 @@ void intel_dmc_wl_put(struct intel_display *display, intel_reg_t reg) spin_lock_irqsave(&wl->lock, flags); - if (i915_mmio_reg_valid(reg) && + if (intel_reg_valid(reg) && !intel_dmc_wl_check_range(display, reg, wl->dc_state)) goto out_unlock; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 6acdfa97deaa..e2e2a1c2a6e3 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3842,9 +3842,9 @@ static void icl_dpll_write(struct intel_display *display, intel_de_write(display, cfgcr0_reg, hw_state->cfgcr0); intel_de_write(display, cfgcr1_reg, hw_state->cfgcr1); drm_WARN_ON_ONCE(display->drm, display->vbt.override_afc_startup && - !i915_mmio_reg_valid(div0_reg)); + !intel_reg_valid(div0_reg)); if (display->vbt.override_afc_startup && - i915_mmio_reg_valid(div0_reg)) + intel_reg_valid(div0_reg)) intel_de_rmw(display, div0_reg, TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0); intel_de_posting_read(display, cfgcr1_reg); diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index ce4d452ae695..fec8a56e21ea 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -341,7 +341,7 @@ static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, prev_opcode = dsb->ins[1] & ~DSB_REG_VALUE_MASK; prev_reg = dsb->ins[1] & DSB_REG_VALUE_MASK; - return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg); + return prev_opcode == opcode && prev_reg == intel_reg_offset(reg); } static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, intel_reg_t reg) @@ -386,7 +386,7 @@ void intel_dsb_reg_write_indexed(struct intel_dsb *dsb, if (!intel_dsb_prev_ins_is_indexed_write(dsb, reg)) intel_dsb_emit(dsb, 0, /* count */ (DSB_OPCODE_INDEXED_WRITE << DSB_OPCODE_SHIFT) | - i915_mmio_reg_offset(reg)); + intel_reg_offset(reg)); if (!assert_dsb_has_room(dsb)) return; @@ -407,7 +407,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, intel_dsb_emit(dsb, val, (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) | - i915_mmio_reg_offset(reg)); + intel_reg_offset(reg)); } static u32 intel_dsb_mask_to_byte_en(u32 mask) @@ -425,7 +425,7 @@ void intel_dsb_reg_write_masked(struct intel_dsb *dsb, intel_dsb_emit(dsb, val, (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | (intel_dsb_mask_to_byte_en(mask) << DSB_BYTE_EN_SHIFT) | - i915_mmio_reg_offset(reg)); + intel_reg_offset(reg)); } void intel_dsb_noop(struct intel_dsb *dsb, int count) @@ -565,7 +565,7 @@ void intel_dsb_poll(struct intel_dsb *dsb, intel_dsb_emit(dsb, val, (DSB_OPCODE_POLL << DSB_OPCODE_SHIFT) | - i915_mmio_reg_offset(reg)); + intel_reg_offset(reg)); } static void intel_dsb_align_tail(struct intel_dsb *dsb) diff --git a/drivers/gpu/drm/i915/display/intel_mchbar.c b/drivers/gpu/drm/i915/display/intel_mchbar.c index 8cfcee4a08a4..a3a69e11c390 100644 --- a/drivers/gpu/drm/i915/display/intel_mchbar.c +++ b/drivers/gpu/drm/i915/display/intel_mchbar.c @@ -44,7 +44,7 @@ static u32 mchbar_mirror_len(struct intel_display *display) static bool is_mchbar_reg(struct intel_display *display, intel_reg_t reg) { return has_mchbar_mirror(display) && - in_range32(i915_mmio_reg_offset(reg), + in_range32(intel_reg_offset(reg), mchbar_mirror_base(display), mchbar_mirror_len(display)); } @@ -53,7 +53,7 @@ static void assert_is_mchbar_reg(struct intel_display *display, intel_reg_t reg) { drm_WARN(display->drm, !is_mchbar_reg(display, reg), "Reading non-MCHBAR register 0x%x\n", - i915_mmio_reg_offset(reg)); + intel_reg_offset(reg)); } u16 intel_mchbar_read16(struct intel_display *display, intel_reg_t reg) diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index ea5e8f75acef..d4c98b150fa2 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -1388,7 +1388,7 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct intel_pps_delays *s seq->backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); seq->power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); - if (i915_mmio_reg_valid(regs.pp_div)) { + if (intel_reg_valid(regs.pp_div)) { u32 pp_div; pp_div = intel_de_read(display, regs.pp_div); @@ -1647,7 +1647,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd /* * Compute the divisor for the pp clock, simply match the Bspec formula. */ - if (i915_mmio_reg_valid(regs.pp_div)) + if (intel_reg_valid(regs.pp_div)) intel_de_write(display, regs.pp_div, REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | @@ -1662,7 +1662,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", intel_de_read(display, regs.pp_on), intel_de_read(display, regs.pp_off), - i915_mmio_reg_valid(regs.pp_div) ? + intel_reg_valid(regs.pp_div) ? intel_de_read(display, regs.pp_div) : (intel_de_read(display, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); } From ae27befd097f1ddaec61b231ba775d0768aab859 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 13 May 2026 11:01:03 +0300 Subject: [PATCH 38/38] drm/i915/sdvo: use the i2c bus locking functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use i2c_lock_bus(), i2c_trylock_bus(), and i2c_unlock_bus() instead of poking at i2c adapter's lock_ops directly. Reviewed-by: Ville Syrjälä Link: https://patch.msgid.link/20260513080103.169402-1-jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_sdvo.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index 9803d6dc7be4..ac37af45cecf 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -3319,7 +3319,7 @@ static void proxy_lock_bus(struct i2c_adapter *adapter, struct intel_sdvo_ddc *ddc = adapter->algo_data; struct intel_sdvo *sdvo = ddc->sdvo; - sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags); + i2c_lock_bus(sdvo->i2c, flags); } static int proxy_trylock_bus(struct i2c_adapter *adapter, @@ -3328,7 +3328,7 @@ static int proxy_trylock_bus(struct i2c_adapter *adapter, struct intel_sdvo_ddc *ddc = adapter->algo_data; struct intel_sdvo *sdvo = ddc->sdvo; - return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags); + return i2c_trylock_bus(sdvo->i2c, flags); } static void proxy_unlock_bus(struct i2c_adapter *adapter, @@ -3337,7 +3337,7 @@ static void proxy_unlock_bus(struct i2c_adapter *adapter, struct intel_sdvo_ddc *ddc = adapter->algo_data; struct intel_sdvo *sdvo = ddc->sdvo; - sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags); + i2c_unlock_bus(sdvo->i2c, flags); } static const struct i2c_lock_operations proxy_lock_ops = {