From 629c635eafbaf18260c8083360745c71674640d2 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Thu, 15 Feb 2024 16:09:29 +0530 Subject: [PATCH 001/110] arm64: dts: qcom: qcm6490-idp: add display and panel Enable Display Subsystem with Novatek NT36672E Panel on qcm6490 idp platform. Signed-off-by: Ritesh Kumar Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240215103929.19357-3-quic_riteshk@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 92 ++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index e4bfad50a669..5bbe8aa63927 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -10,6 +10,7 @@ #define PM7250B_SID1 9 #include +#include #include #include "sc7280.dtsi" #include "pm7250b.dtsi" @@ -35,10 +36,29 @@ aliases { serial0 = &uart5; }; + pm8350c_pwm_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pm8350c_pwm 3 65535>; + enable-gpios = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pmic_lcd_bl_en>; + pinctrl-names = "default"; + }; + chosen { stdout-path = "serial0:115200n8"; }; + lcd_disp_bias: regulator-lcd-disp-bias { + compatible = "regulator-fixed"; + regulator-name = "lcd_disp_bias"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + gpio = <&pm7250b_gpios 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <&lcd_disp_bias_en>; + pinctrl-names = "default"; + }; + reserved-memory { xbl_mem: xbl@80700000 { reg = <0x0 0x80700000 0x0 0x100000>; @@ -421,7 +441,79 @@ vreg_bob_3p296: bob { }; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi { + vdda-supply = <&vreg_l6b_1p2>; + status = "okay"; + + panel@0 { + compatible = "novatek,nt36672e"; + reg = <0>; + + reset-gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>; + + vddi-supply = <&vreg_l8c_1p62>; + avdd-supply = <&lcd_disp_bias>; + avee-supply = <&lcd_disp_bias>; + + backlight = <&pm8350c_pwm_backlight>; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi_phy { + vdds-supply = <&vreg_l10c_0p88>; + status = "okay"; +}; + +&pm7250b_gpios { + lcd_disp_bias_en: lcd-disp-bias-en-state { + pins = "gpio2"; + function = "func1"; + bias-disable; + qcom,drive-strength = ; + input-disable; + output-enable; + power-source = <0>; + }; +}; + +&pm8350c_gpios { + pmic_lcd_bl_en: pmic-lcd-bl-en-state { + pins = "gpio7"; + function = "normal"; + bias-disable; + qcom,drive-strength = ; + output-low; + power-source = <0>; + }; + + pmic_lcd_bl_pwm: pmic-lcd-bl-pwm-state { + pins = "gpio8"; + function = "func1"; + bias-disable; + qcom,drive-strength = ; + output-low; + power-source = <0>; + }; +}; + &pm8350c_pwm { + pinctrl-0 = <&pmic_lcd_bl_pwm>; + pinctrl-names = "default"; status = "okay"; multi-led { From 9fa6a0bad7077cac60ba98d801e13a74581ec46a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 17 Feb 2024 14:00:07 +0100 Subject: [PATCH 002/110] arm64: dts: qcom: sc8280xp: Add missing LMH interrupts Hook up the interrupts that signal the Limits Management Hardware has started some sort of throttling action. In testing, you may notice the A78C cluster throttle IRQ fire count stays at zero. After an hour of painful experiments on an X13s, I was able to get that cluster to heat up near 90 degC, after which the IRQ has indeed fired. So it stands to reason that the heat output difference between the A78C and X1C clusters is so massive that LMH rarely decides to throttle the "little" one based on its power metrics. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240217-topic-8280_lmh-v1-1-d72dd4fedfb8@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index a5b194813079..daaf054efca3 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4966,6 +4966,11 @@ cpufreq_hw: cpufreq@18591000 { <0 0x18592000 0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; From 2b621971554a94094cf489314dc1c2b65401965c Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 6 Mar 2024 10:56:50 +0100 Subject: [PATCH 003/110] arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP Add the missing PCIe CX performance level votes to avoid relying on other drivers (e.g. USB or UFS) to maintain the nominal performance level required for Gen3 speeds. Fixes: 813e83157001 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes") Cc: stable@vger.kernel.org # 6.2 Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20240306095651.4551-5-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index daaf054efca3..f42fc469af73 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1774,6 +1774,7 @@ pcie4: pcie@1c00000 { reset-names = "pci"; power-domains = <&gcc PCIE_4_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie4_phy>; phy-names = "pciephy"; @@ -1872,6 +1873,7 @@ pcie3b: pcie@1c08000 { reset-names = "pci"; power-domains = <&gcc PCIE_3B_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie3b_phy>; phy-names = "pciephy"; @@ -1970,6 +1972,7 @@ pcie3a: pcie@1c10000 { reset-names = "pci"; power-domains = <&gcc PCIE_3A_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie3a_phy>; phy-names = "pciephy"; @@ -2071,6 +2074,7 @@ pcie2b: pcie@1c18000 { reset-names = "pci"; power-domains = <&gcc PCIE_2B_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie2b_phy>; phy-names = "pciephy"; @@ -2169,6 +2173,7 @@ pcie2a: pcie@1c20000 { reset-names = "pci"; power-domains = <&gcc PCIE_2A_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie2a_phy>; phy-names = "pciephy"; From 81051f14a66c3913f1d219bd97e47002f1dc91de Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 6 Mar 2024 10:56:51 +0100 Subject: [PATCH 004/110] arm64: dts: qcom: sc8280xp: enable GICv3 ITS for PCIe The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS). Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. Note that using the GIC ITS on SC8280XP will cause Advanced Error Reporting (AER) interrupts to be received on errors unlike when using the internal MSI controller. This will specifically lead to notifications about Correctable Errors being logged for the Wi-Fi controller on the Lenovo ThinkPad X13s when ASPM L0s is enabled. Suggested-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20240306095651.4551-6-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index f42fc469af73..f3eb39f22702 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1731,6 +1731,8 @@ pcie4: pcie@1c00000 { linux,pci-domain = <6>; num-lanes = <1>; + msi-map = <0x0 &its 0xe0000 0x10000>; + interrupts = , , , @@ -1832,6 +1834,8 @@ pcie3b: pcie@1c08000 { linux,pci-domain = <5>; num-lanes = <2>; + msi-map = <0x0 &its 0xd0000 0x10000>; + interrupts = , , , @@ -1931,6 +1935,8 @@ pcie3a: pcie@1c10000 { linux,pci-domain = <4>; num-lanes = <4>; + msi-map = <0x0 &its 0xc0000 0x10000>; + interrupts = , , , @@ -2033,6 +2039,8 @@ pcie2b: pcie@1c18000 { linux,pci-domain = <3>; num-lanes = <2>; + msi-map = <0x0 &its 0xb0000 0x10000>; + interrupts = , , , @@ -2132,6 +2140,8 @@ pcie2a: pcie@1c20000 { linux,pci-domain = <2>; num-lanes = <4>; + msi-map = <0x0 &its 0xa0000 0x10000>; + interrupts = , , , @@ -4804,7 +4814,7 @@ intc: interrupt-controller@17a00000 { #size-cells = <2>; ranges; - msi-controller@17a40000 { + its: msi-controller@17a40000 { compatible = "arm,gic-v3-its"; reg = <0 0x17a40000 0 0x20000>; msi-controller; From 91905d8368c69bea3fb85f5c76334274a232612d Mon Sep 17 00:00:00 2001 From: Jianhua Lu Date: Sat, 2 Mar 2024 21:10:25 +0800 Subject: [PATCH 005/110] arm64: dts: qcom: sm8250-xiaomi-elish: add usb pd negotiation support Add usb pd negotiation, but charging is controlled by pm8150b pmic, so it can only charge battery with 5W, Signed-off-by: Jianhua Lu Link: https://lore.kernel.org/r/20240302131025.13741-1-lujianhua000@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 6f54f50a70b0..2042020eb0dd 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -636,7 +636,8 @@ &pm8150b_typec { connector { compatible = "usb-c-connector"; - power-role = "source"; + op-sink-microwatt = <10000000>; + power-role = "dual"; data-role = "dual"; self-powered; @@ -645,6 +646,12 @@ PDO_FIXED_DUAL_ROLE | PDO_FIXED_USB_COMM | PDO_FIXED_DATA_SWAP)>; + sink-pdos = ; + ports { #address-cells = <1>; #size-cells = <0>; From dc6cb3854c44de4c7ac9fd173208f5d19ed5d882 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 7 Mar 2024 21:25:55 +0100 Subject: [PATCH 006/110] arm64: dts: qcom: sc8280xp: Add QFPROM node Describe the QFPROM NVMEM block. Also, add a subnode to represent the GPU speed bin region within it. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240307-topic-8280_nodes-v1-2-4eba20e08902@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index f3eb39f22702..eb19ae4e486f 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -862,6 +862,18 @@ ipcc: mailbox@408000 { #mbox-cells = <2>; }; + qfprom: efuse@784000 { + compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@18b { + reg = <0x18b 0x1>; + bits = <5 3>; + }; + }; + qup2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x2000>; From 865ff2e6f5daf4ea822120c873f4ba43eb2d8db7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 7 Mar 2024 21:25:56 +0100 Subject: [PATCH 007/110] arm64: dts: qcom: sc8280xp: Add PS_HOLD restart Killing the platform with a single write and no firmware involvement is pretty cool, add support for it. Note that due to restart notifier priority settings, PSCI reset will be used instead, unless: a) PSCI is not exposed by the firmware (e.g. because the fw was replaced) or b) PSCI restart fails for some reason Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240307-topic-8280_nodes-v1-3-4eba20e08902@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index eb19ae4e486f..93f5c02b06da 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4475,6 +4475,11 @@ tsens0: thermal-sensor@c263000 { #thermal-sensor-cells = <1>; }; + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0 0x0c264000 0 0x4>; + }; + tsens1: thermal-sensor@c265000 { compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; reg = <0 0x0c265000 0 0x1ff>, /* TM */ From 27ef06ebd289992ad4469632b440cd0b072be562 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 7 Mar 2024 21:25:57 +0100 Subject: [PATCH 008/110] arm64: dts: qcom: sc8280xp: Describe TCSR download mode register To allow for swift EDL reboots, describe the respective register under the scm node. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240307-topic-8280_nodes-v1-4-4eba20e08902@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 93f5c02b06da..9d54c63c20cd 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -300,6 +300,7 @@ firmware { scm: scm { compatible = "qcom,scm-sc8280xp", "qcom,scm"; interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + qcom,dload-mode = <&tcsr 0x13000>; }; }; From 7d6d561fa934594faf359f6fffee0e2dd59f8110 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Sat, 9 Mar 2024 14:15:04 +0100 Subject: [PATCH 009/110] arm64: dts: qcom: qcm2290: Add LMH node Add a node for the Limits Management Hardware to ensure it can be configured by the operating system. Signed-off-by: Loic Poulain [Konrad: add commit msg, rebase] Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240308-topic-rb1_lmh-v2-3-bac3914b0fe3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 89beac833d43..1aacad50e7fc 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -1858,7 +1858,7 @@ cpufreq_hw: cpufreq@f521000 { compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0x0 0x0f521000 0x0 0x1000>; reg-names = "freq-domain0"; - interrupts = ; + interrupts-extended = <&lmh_cluster 0>; interrupt-names = "dcvsh-irq-0"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; clock-names = "xo", "alternate"; @@ -1866,6 +1866,18 @@ cpufreq_hw: cpufreq@f521000 { #freq-domain-cells = <1>; #clock-cells = <1>; }; + + lmh_cluster: lmh@f550800 { + compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh"; + reg = <0x0 0x0f550800 0x0 0x400>; + interrupts = ; + cpus = <&CPU0>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; }; thermal-zones { From d4fac32cbe95046bfe303a51dc2486db215cf86d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Feb 2024 15:27:23 +0100 Subject: [PATCH 010/110] arm64: dts: qcom: x1e80100: correct SWR1 pack mode Correct the SWR1 Soundwire controller port block pack mode to match reference code. Not sure if this has any impact. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240227142725.625561-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 8e517f76189e..26d779ade489 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3088,7 +3088,7 @@ swr1: soundwire@6ad0000 { qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; - qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; From 76cbe23e4399bc0130572981ab330e59d823696d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Feb 2024 15:27:24 +0100 Subject: [PATCH 011/110] arm64: dts: qcom: x1e80100-crd: switch WSA8845 speakers to shared reset-gpio Each pair of WSA8845 speakers share the powerdown SD_N GPIO, thus this GPIO is specified twice in each WSA8845 device node. Such DTS was added hoping non-exclusive GPIO usage would be accepted, but it turned out otherwise: it is not supported by the Linux kernel. Linux kernel however supports sharing reset GPIOs, when used bia the reset controller framework as implemented in commit 26c8a435fce6 ("ASoC: dt-bindings: qcom,wsa8840: Add reset-gpios for shared line") and commit c721f189e89c ("reset: Instantiate reset GPIO controller for shared reset-gpios"). Convert the property with shutdown GPIO to "reset-gpios" to use mentioned Linux kernel feature. This allows to bring all four speakers out of reset. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240227142725.625561-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index 6a0a54532e5f..dfdb31227e8b 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -683,13 +683,14 @@ &remoteproc_cdsp { &swr0 { status = "okay"; + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + /* WSA8845, Left Woofer */ left_woofer: speaker@0,0 { compatible = "sdw20217020400"; reg = <0 0>; - pinctrl-0 = <&spkr_01_sd_n_active>; - pinctrl-names = "default"; - powerdown-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "WooferLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; @@ -700,8 +701,7 @@ left_woofer: speaker@0,0 { left_tweeter: speaker@0,1 { compatible = "sdw20217020400"; reg = <0 1>; - /* pinctrl in left_woofer node because of sharing the GPIO*/ - powerdown-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "TwitterLeft"; vdd-1p8-supply = <&vreg_l15b_1p8>; @@ -734,13 +734,14 @@ wcd_tx: codec@0,3 { &swr3 { status = "okay"; + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + /* WSA8845, Right Woofer */ right_woofer: speaker@0,0 { compatible = "sdw20217020400"; reg = <0 0>; - pinctrl-0 = <&spkr_23_sd_n_active>; - pinctrl-names = "default"; - powerdown-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "WooferRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; @@ -751,8 +752,7 @@ right_woofer: speaker@0,0 { right_tweeter: speaker@0,1 { compatible = "sdw20217020400"; reg = <0 1>; - /* pinctrl in right_woofer node because of sharing the GPIO*/ - powerdown-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; #sound-dai-cells = <0>; sound-name-prefix = "TwitterRight"; vdd-1p8-supply = <&vreg_l15b_1p8>; From 6e995a1b53444d09f7707f4f79b752213343b05c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 27 Feb 2024 09:39:54 -0800 Subject: [PATCH 012/110] arm64: dts: qcom: qcs6490-rb3gen2: Name the regulators Without explicitly specifying names for the regulators they are named based on the DeviceTree node name. This results in multiple regulators with the same name, making debug prints and regulator_summary impossible to reason about. Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240227-rb3gen2-regulator-names-v1-1-63ceb845dcc8@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 41 ++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 97824c769ba3..63ebe0774f1d 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -153,129 +153,151 @@ regulators-0 { vdd-l14-l16-supply = <&vreg_s8b_1p272>; vreg_s1b_1p872: smps1 { + regulator-name = "vreg_s1b_1p872"; regulator-min-microvolt = <1840000>; regulator-max-microvolt = <2040000>; }; vreg_s2b_0p876: smps2 { + regulator-name = "vreg_s2b_0p876"; regulator-min-microvolt = <570070>; regulator-max-microvolt = <1050000>; }; vreg_s7b_0p972: smps7 { + regulator-name = "vreg_s7b_0p972"; regulator-min-microvolt = <535000>; regulator-max-microvolt = <1120000>; }; vreg_s8b_1p272: smps8 { + regulator-name = "vreg_s8b_1p272"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1500000>; regulator-initial-mode = ; }; vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; regulator-min-microvolt = <825000>; regulator-max-microvolt = <925000>; regulator-initial-mode = ; }; vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l3b_0p504: ldo3 { + regulator-name = "vreg_l3b_0p504"; regulator-min-microvolt = <312000>; regulator-max-microvolt = <910000>; regulator-initial-mode = ; }; vreg_l4b_0p752: ldo4 { + regulator-name = "vreg_l4b_0p752"; regulator-min-microvolt = <752000>; regulator-max-microvolt = <820000>; regulator-initial-mode = ; }; reg_l5b_0p752: ldo5 { + regulator-name = "reg_l5b_0p752"; regulator-min-microvolt = <552000>; regulator-max-microvolt = <832000>; regulator-initial-mode = ; }; vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; regulator-min-microvolt = <1140000>; regulator-max-microvolt = <1260000>; regulator-initial-mode = ; }; vreg_l7b_2p952: ldo7 { + regulator-name = "vreg_l7b_2p952"; regulator-min-microvolt = <2400000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; regulator-min-microvolt = <870000>; regulator-max-microvolt = <970000>; regulator-initial-mode = ; }; vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = ; }; vreg_l11b_1p504: ldo11 { + regulator-name = "vreg_l11b_1p504"; regulator-min-microvolt = <1504000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l12b_0p751: ldo12 { + regulator-name = "vreg_l12b_0p751"; regulator-min-microvolt = <751000>; regulator-max-microvolt = <824000>; regulator-initial-mode = ; }; vreg_l13b_0p53: ldo13 { + regulator-name = "vreg_l13b_0p53"; regulator-min-microvolt = <530000>; regulator-max-microvolt = <824000>; regulator-initial-mode = ; }; vreg_l14b_1p08: ldo14 { + regulator-name = "vreg_l14b_1p08"; regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = ; }; vreg_l15b_0p765: ldo15 { + regulator-name = "vreg_l15b_0p765"; regulator-min-microvolt = <765000>; regulator-max-microvolt = <1020000>; regulator-initial-mode = ; }; vreg_l16b_1p1: ldo16 { + regulator-name = "vreg_l16b_1p1"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1300000>; regulator-initial-mode = ; }; vreg_l17b_1p7: ldo17 { + regulator-name = "vreg_l17b_1p7"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <1900000>; regulator-initial-mode = ; }; vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; @@ -304,109 +326,128 @@ regulators-1 { vdd-bob-supply = <&vph_pwr>; vreg_s1c_2p19: smps1 { + regulator-name = "vreg_s1c_2p19"; regulator-min-microvolt = <2190000>; regulator-max-microvolt = <2210000>; }; vreg_s2c_0p752: smps2 { + regulator-name = "vreg_s2c_0p752"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <800000>; }; vreg_s5c_0p752: smps5 { + regulator-name = "vreg_s5c_0p752"; regulator-min-microvolt = <465000>; regulator-max-microvolt = <1050000>; }; vreg_s7c_0p752: smps7 { + regulator-name = "vreg_s7c_0p752"; regulator-min-microvolt = <465000>; regulator-max-microvolt = <800000>; }; vreg_s9c_1p084: smps9 { + regulator-name = "vreg_s9c_1p084"; regulator-min-microvolt = <1010000>; regulator-max-microvolt = <1170000>; }; vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = ; }; vreg_l2c_1p62: ldo2 { + regulator-name = "vreg_l2c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = ; }; vreg_l3c_2p8: ldo3 { + regulator-name = "vreg_l3c_2p8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3540000>; regulator-initial-mode = ; }; vreg_l4c_1p62: ldo4 { + regulator-name = "vreg_l4c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = ; }; vreg_l5c_1p62: ldo5 { + regulator-name = "vreg_l5c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = ; }; vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l8c_1p62: ldo8 { + regulator-name = "vreg_l8c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <35440000>; regulator-initial-mode = ; }; vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1050000>; regulator-initial-mode = ; }; vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l12c_1p65: ldo12 { + regulator-name = "vreg_l12c_1p65"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l13c_2p7: ldo13 { + regulator-name = "vreg_l13c_2p7"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3960000>; }; From 033fbfa0eb60e519f50e97ef93baec270cd28a88 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 27 Feb 2024 13:53:04 +0100 Subject: [PATCH 013/110] arm64: dts: qcom: sm8450: add missing qcom,non-secure-domain property By default the DSP domains are non secure, add the missing qcom,non-secure-domain property to mark them as non-secure. Fixes: 91d70eb70867 ("arm64: dts: qcom: sm8450: add fastrpc nodes") Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240227-topic-sm8x50-upstream-fastrpc-non-secure-domain-v1-1-15c4c864310f@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index b86be34a912b..92b052f7b20e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2363,6 +2363,7 @@ fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "sdsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; @@ -2665,6 +2666,7 @@ fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; @@ -2731,6 +2733,7 @@ fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "cdsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; From 49c50ad9e6cbaa6a3da59cdd85d4ffb354ef65f4 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 27 Feb 2024 13:53:05 +0100 Subject: [PATCH 014/110] arm64: dts: qcom: sm8550: add missing qcom,non-secure-domain property By default the DSP domains are non secure, add the missing qcom,non-secure-domain property to mark them as non-secure. Fixes: d0c061e366ed ("arm64: dts: qcom: sm8550: add adsp, cdsp & mdss nodes") Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240227-topic-sm8x50-upstream-fastrpc-non-secure-domain-v1-2-15c4c864310f@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 3904348075f6..5cae8d773cec 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -4316,6 +4316,7 @@ fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; @@ -4454,6 +4455,7 @@ fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "cdsp"; + qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; From 039d379490eabf798baded4de2d698a7324ab7e6 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 27 Feb 2024 13:53:06 +0100 Subject: [PATCH 015/110] arm64: dts: qcom: sm8650: add missing qcom,non-secure-domain property By default the DSP domains are non secure, add the missing qcom,non-secure-domain property to mark them as non-secure. Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240227-topic-sm8x50-upstream-fastrpc-non-secure-domain-v1-3-15c4c864310f@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index ba72d8f38420..1bfcf069c9ae 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4845,6 +4845,8 @@ fastrpc { label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; #size-cells = <0>; @@ -5002,6 +5004,8 @@ fastrpc { label = "cdsp"; + qcom,non-secure-domain; + #address-cells = <1>; #size-cells = <0>; From 232490b925272d54dd91847a183bdbc2deec904b Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Thu, 8 Feb 2024 19:16:44 -0500 Subject: [PATCH 016/110] arm64: dts: qcom: sdm670-google-sargo: add panel Add the panel used in the Google Pixel 3a. Signed-off-by: Richard Acayan Link: https://lore.kernel.org/r/20240209001639.387374-9-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm670-google-sargo.dts | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index 32a7bd59e1ec..176b0119fe6d 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -441,6 +441,47 @@ rmi4-f12@12 { }; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l1a_1p225>; + status = "okay"; + + panel@0 { + compatible = "samsung,s6e3fa7-ams559nk06"; + reg = <0>; + + reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_default>; + + power-supply = <&vreg_l6b_3p3>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1b_0p925>; + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &pm660l_gpios { vol_up_pin: vol-up-state { pins = "gpio7"; @@ -481,6 +522,29 @@ &sdhc_1 { &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; + panel_default: panel-default-state { + te-pins { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + reset-pins { + pins = "gpio75"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + mode-pins { + pins = "gpio76"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + }; + touchscreen_default: ts-default-state { ts-reset-pins { pins = "gpio99"; From 4aa609a922e3ce387d18d8e7327d3912f0a85653 Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sat, 3 Feb 2024 21:11:55 +0200 Subject: [PATCH 017/110] arm64: dts: qcom: sc8180x-lenovo-flex-5g: fix GPU firmware path Fix GPU firmware path so it uses model-specific directory. Signed-off-by: Anton Bambura Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240203191200.99185-2-jenneron@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 0c22f3efec20..49b740c54674 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -350,7 +350,7 @@ &gpu { zap-shader { memory-region = <&gpu_mem>; - firmware-name = "qcom/sc8180x/qcdxkmsuc8180.mbn"; + firmware-name = "qcom/sc8180x/LENOVO/82AK/qcdxkmsuc8180.mbn"; }; }; From 8c28575a4aba092feb5a5ca0b446eb8a0fa39396 Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sat, 3 Feb 2024 21:11:56 +0200 Subject: [PATCH 018/110] arm64: dts: qcom: sc8180x-lenovo-flex-5g: set names for i2c hid nodes Set names, so they correspond to devices connected to these interfaces. Signed-off-by: Anton Bambura Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240203191200.99185-3-jenneron@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 49b740c54674..af61acf58d68 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -362,7 +362,7 @@ &i2c1 { status = "okay"; - hid@10 { + touchscreen@10 { compatible = "hid-over-i2c"; reg = <0x10>; hid-descr-addr = <0x1>; @@ -379,7 +379,7 @@ &i2c7 { status = "okay"; - hid@5 { + keyboard@5 { compatible = "hid-over-i2c"; reg = <0x5>; hid-descr-addr = <0x20>; @@ -387,7 +387,7 @@ hid@5 { interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_LOW>; }; - hid@2c { + touchpad@2c { compatible = "hid-over-i2c"; reg = <0x2c>; hid-descr-addr = <0x20>; From 0d76ffe33e5eb5b0a7bd09e4fa8a72f7f4cfbc0d Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sat, 3 Feb 2024 21:11:57 +0200 Subject: [PATCH 019/110] arm64: dts: qcom: sc8180x-lenovo-flex-5g: move pinctrl to appropriate nodes Split keyboard and touchpad pinctrl nodes since they are for different devices and move keyboard, touchpad and touchscreen pinctrl references to appropriate nodes. Signed-off-by: Anton Bambura Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240203191200.99185-4-jenneron@postmarketos.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 41 +++++++++++++------ 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index af61acf58d68..6ae6cb030b70 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -357,7 +357,7 @@ zap-shader { &i2c1 { clock-frequency = <100000>; - pinctrl-0 = <&i2c1_active>, <&i2c1_hid_active>; + pinctrl-0 = <&i2c1_active>; pinctrl-names = "default"; status = "okay"; @@ -368,13 +368,16 @@ touchscreen@10 { hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 122 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts_int_default>; + pinctrl-names = "default"; }; }; &i2c7 { clock-frequency = <100000>; - pinctrl-0 = <&i2c7_active>, <&i2c7_hid_active>; + pinctrl-0 = <&i2c7_active>; pinctrl-names = "default"; status = "okay"; @@ -385,6 +388,9 @@ keyboard@5 { hid-descr-addr = <0x20>; interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kb_int_default>; + pinctrl-names = "default"; }; touchpad@2c { @@ -393,6 +399,9 @@ touchpad@2c { hid-descr-addr = <0x20>; interrupts-extended = <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tp_int_default>; + pinctrl-names = "default"; }; }; @@ -669,14 +678,6 @@ i2c1_active: i2c1-active-state { drive-strength = <2>; }; - i2c1_hid_active: i2c1-hid-active-state { - pins = "gpio122"; - function = "gpio"; - - bias-pull-up; - drive-strength = <2>; - }; - i2c7_active: i2c7-active-state { pins = "gpio98", "gpio99"; function = "qup7"; @@ -685,8 +686,8 @@ i2c7_active: i2c7-active-state { drive-strength = <2>; }; - i2c7_hid_active: i2c7-hid-active-state { - pins = "gpio37", "gpio24"; + kb_int_default: kb-int-default-state { + pins = "gpio37"; function = "gpio"; bias-pull-up; @@ -718,6 +719,22 @@ wake-n-pins { }; }; + tp_int_default: tp-int-default-state { + pins = "gpio24"; + function = "gpio"; + + bias-pull-up; + drive-strength = <2>; + }; + + ts_int_default: ts-int-default-state { + pins = "gpio122"; + function = "gpio"; + + bias-pull-up; + drive-strength = <2>; + }; + usbprim_sbu_default: usbprim-sbu-state { oe-n-pins { pins = "gpio152"; From 46c2f36e76a018c269d236ec1a1cca03fe5bb47b Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sat, 3 Feb 2024 21:11:59 +0200 Subject: [PATCH 020/110] arm64: dts: qcom: sc8180x-lenovo-flex-5g: set touchpad i2c frequency to 1 MHz This solves the issue when touchpad gets stuck on right or middle click. This also makes touchpad working smoother. Signed-off-by: Anton Bambura Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240203191200.99185-6-jenneron@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 6ae6cb030b70..5f07933183e1 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -375,7 +375,7 @@ touchscreen@10 { }; &i2c7 { - clock-frequency = <100000>; + clock-frequency = <1000000>; pinctrl-0 = <&i2c7_active>; pinctrl-names = "default"; From 42ee55cb2e27d8bf3d26b8c4199727df029a5878 Mon Sep 17 00:00:00 2001 From: Anton Bambura Date: Sat, 3 Feb 2024 21:12:00 +0200 Subject: [PATCH 021/110] arm64: dts: qcom: sc8180x-lenovo-flex-5g: Allow UFS regulators load/mode setting The UFS driver expects to be able to set load (and by extension, mode) on the supplied regulators. Add the necessary properties to make that possible. Based on https://lore.kernel.org/r/20231214-topic-sc8180_fixes-v1-6-421904863006@linaro.org Signed-off-by: Anton Bambura Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240203191200.99185-7-jenneron@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 5f07933183e1..6f2e1c732ed3 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -329,12 +329,18 @@ vreg_l7e_1p8: ldo7 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-allowed-modes = ; + regulator-allow-set-load; }; vreg_l10e_2p9: ldo10 { regulator-min-microvolt = <2904000>; regulator-max-microvolt = <2904000>; regulator-initial-mode = ; + regulator-allowed-modes = ; + regulator-allow-set-load; }; vreg_l16e_3p0: ldo16 { From 343dfe6206b2793f7f5196b849dfbb4efcc5c048 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Mon, 19 Feb 2024 13:27:20 +0530 Subject: [PATCH 022/110] arm64: dts: qcom: sc8280xp: Add missing hs_phy_irq in USB nodes Recent binding update [1] indicates that there are hs_phy_irq present in primary and secondary usb controllers of sc8280xp. Add the missing hs_phy_irq for these controllers. Since the driver doesn't use this interrupt, this change has been only compile tested. [1]: https://lore.kernel.org/all/20231227091951.685-2-quic_kriskura@quicinc.com/ Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240219075720.640529-1-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 9d54c63c20cd..75fa7ac5b60a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3389,10 +3389,12 @@ usb_0: usb@a6f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -3449,10 +3451,12 @@ usb_1: usb@a8f8800 { assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; From fd5afa5d7e5259cb2320fbe2cf60250f7336f439 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 19 Feb 2024 11:16:02 +0100 Subject: [PATCH 023/110] arm64: dts: qcom: sm6350: Add Crypto Engine Add crypto engine (CE) and CE BAM related nodes and definitions for this SoC. For reference: [ 2.297419] qcrypto 1dfa000.crypto: Crypto device found, version 5.5.1 Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240219-sm6350-qce-v2-1-7acb8838f248@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 24bcec3366ef..4864bd33e448 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1205,6 +1205,37 @@ ufs_mem_phy: phy@1d87000 { status = "disabled"; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <16>; + qcom,num-ees = <4>; + iommus = <&apps_smmu 0x426 0x11>, + <&apps_smmu 0x432 0x0>, + <&apps_smmu 0x436 0x11>, + <&apps_smmu 0x438 0x1>, + <&apps_smmu 0x43f 0x0>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x426 0x11>, + <&apps_smmu 0x432 0x0>, + <&apps_smmu 0x436 0x11>, + <&apps_smmu 0x438 0x1>, + <&apps_smmu 0x43f 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + }; + ipa: ipa@1e40000 { compatible = "qcom,sm6350-ipa"; From 90053b1574f8cff3a3b53accc496246ad2e0aec3 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 20 Feb 2024 13:01:22 +0100 Subject: [PATCH 024/110] arm64: dts: qcom: sdm632-fairphone-fp3: enable USB-C port handling Add the definition for the USB-C connector found on this phone and hook up the relevant bits. This enables USB role switching. Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240220-fp3-typec-v1-1-1930cad81139@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 14 +++++++++ .../boot/dts/qcom/sdm632-fairphone-fp3.dts | 31 +++++++++++++++++-- 2 files changed, 43 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index f1011bb641c6..5d818fe057dd 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -1323,6 +1323,20 @@ usb3_dwc3: usb@7000000 { snps,hird-threshold = /bits/ 8 <0x00>; maximum-speed = "high-speed"; + + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 057579ae3013..e2708c74e95a 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -116,6 +116,33 @@ led@3 { }; }; +&pmi632_typec { + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "dual"; + data-role = "dual"; + self-powered; + + typec-power-opmode = "default"; + pd-disable; + + port { + pmi632_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + }; +}; + +&pmi632_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <1000000>; + status = "okay"; +}; + &sdhc_1 { status = "okay"; vmmc-supply = <&pm8953_l8>; @@ -240,8 +267,8 @@ &usb3 { status = "okay"; }; -&usb3_dwc3 { - dr_mode = "peripheral"; +&usb_dwc3_hs { + remote-endpoint = <&pmi632_hs_in>; }; &wcnss { From 601feafa7dad3a1de094ea524b6c2e1315a738d2 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Tue, 20 Feb 2024 23:21:47 +0300 Subject: [PATCH 025/110] arm64: dts: qcom: pm6150: define USB-C related blocks Define VBUS regulator and the Type-C handling block as present on the Qualcomm PM6150 PMIC. Signed-off-by: Danila Tikhonov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240220202147.228911-3-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6150.dtsi | 46 ++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index ddbaf7280b03..11158c2bd524 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -63,6 +63,52 @@ pm6150_resin: resin { }; }; + pm6150_vbus: usb-vbus-regulator@1100 { + compatible = "qcom,pm6150-vbus-reg, + qcom,pm8150b-vbus-reg"; + reg = <0x1100>; + status = "disabled"; + }; + + pm6150_typec: typec@1500 { + compatible = "qcom,pm6150-typec, + qcom,pm8150b-typec"; + reg = <0x1500>, <0x1700>; + interrupts = <0x0 0x15 0x00 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x01 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x02 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x03 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x04 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x05 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x06 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x07 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x00 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x01 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x02 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x03 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x04 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x05 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x06 IRQ_TYPE_EDGE_RISING>, + <0x0 0x17 0x07 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "or-rid-detect-change", + "vpd-detect", + "cc-state-change", + "vconn-oc", + "vbus-change", + "attach-detach", + "legacy-cable-detect", + "try-snk-src-detect", + "sig-tx", + "sig-rx", + "msg-tx", + "msg-rx", + "msg-tx-failed", + "msg-tx-discarded", + "msg-rx-discarded", + "fr-swap"; + status = "disabled"; + }; + pm6150_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; From 53fdae5e086b699a66c6927395fa66c0116ec7ac Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 22 Feb 2024 16:19:19 +0200 Subject: [PATCH 026/110] arm64: dts: qcom: x1e80100: Add SPMI support The X1E80100 platform implements the v7 SPMI arbiter, which means it implements two separate buses. The difference, when compared to existing platforms that also implement v7 SPMI arbiter, is that this is the first platform that actually has boards with secondary bus populated with some PMICs. This is why it needs to have 2 separate buses as child nodes of the arbiter. Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20240222-x1e80100-dts-smb2360-v3-1-85a691d4f68a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 42 ++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 26d779ade489..fa04a24173a7 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4221,6 +4221,48 @@ aoss_qmp: power-management@c300000 { #clock-cells = <0>; }; + spmi: arbiter@c400000 { + compatible = "qcom,x1e80100-spmi-pmic-arb"; + reg = <0 0x0c400000 0 0x3000>, + <0 0x0c500000 0 0x400000>, + <0 0x0c440000 0 0x80000>; + reg-names = "core", "chnls", "obsrvr"; + + qcom,ee = <0>; + qcom,channel = <0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + spmi_bus0: spmi@c42d000 { + reg = <0 0x0c42d000 0 0x4000>, + <0 0x0c4c0000 0 0x10000>; + reg-names = "cnfg", "intr"; + + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + + spmi_bus1: spmi@c432000 { + reg = <0 0x0c432000 0 0x4000>, + <0 0x0c4d0000 0 0x10000>; + reg-names = "cnfg", "intr"; + + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + }; tlmm: pinctrl@f100000 { compatible = "qcom,x1e80100-tlmm"; From 3298d47894b0f30a42a4f93c36dae4838f638dba Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 22 Feb 2024 16:19:20 +0200 Subject: [PATCH 027/110] arm64: dts: qcom: x1e80100: Add dedicated pmic dtsi Add dedicated file for x1e80100 PMICs, add the all 3 smb2360 PMIC nodes with the eUSB2 repeater nodes. Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20240222-x1e80100-dts-smb2360-v3-2-85a691d4f68a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 51 ++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi diff --git a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi new file mode 100644 index 000000000000..04301f772fbd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Linaro Limited + */ + +#include +#include + +/ { +}; + +&spmi_bus1 { + smb2360_0: pmic@7 { + compatible = "qcom,smb2360", "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2360_0_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2360-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; + + smb2360_1: pmic@a { + compatible = "qcom,smb2360", "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2360_1_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2360-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; + + smb2360_2: pmic@b { + compatible = "qcom,smb2360", "qcom,spmi-pmic"; + reg = <0xb SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + smb2360_2_eusb2_repeater: phy@fd00 { + compatible = "qcom,smb2360-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +}; From 3930056f30d374967746876e01e8dca10fbc7ff9 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 22 Feb 2024 16:19:21 +0200 Subject: [PATCH 028/110] arm64: dts: qcom: x1e80100-crd: Add repeater nodes Include the PMIC dedicated file and add regulators to each one of those 3 eUSB2 repeaters. Tie up the repeaters to their corresponding USB HS PHY. Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20240222-x1e80100-dts-smb2360-v3-3-85a691d4f68a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index dfdb31227e8b..d4198fa204fd 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -9,6 +9,7 @@ #include #include "x1e80100.dtsi" +#include "x1e80100-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. X1E80100 CRD"; @@ -680,6 +681,21 @@ &remoteproc_cdsp { status = "okay"; }; +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + &swr0 { status = "okay"; @@ -817,6 +833,8 @@ &usb_1_ss0_hsphy { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_0_eusb2_repeater>; + status = "okay"; }; @@ -837,6 +855,8 @@ &usb_1_ss1_hsphy { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_1_eusb2_repeater>; + status = "okay"; }; @@ -857,6 +877,8 @@ &usb_1_ss2_hsphy { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_2_eusb2_repeater>; + status = "okay"; }; From 04124220d8ce77409a5fa8cdea75dc2be999c932 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 22 Feb 2024 16:19:22 +0200 Subject: [PATCH 029/110] arm64: dts: qcom: x1e80100-qcp: Add repeater nodes Include the PMIC dedicated file and add regulators to each one of those 3 eUSB2 repeaters. Tie up the repeaters to their corresponding USB HS PHY. Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20240222-x1e80100-dts-smb2360-v3-4-85a691d4f68a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index e76d29053d79..35580ac3430d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -9,6 +9,7 @@ #include #include "x1e80100.dtsi" +#include "x1e80100-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. X1E80100 QCP"; @@ -491,6 +492,21 @@ &remoteproc_cdsp { status = "okay"; }; +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + &tlmm { gpio-reserved-ranges = <33 3>, /* Unused */ <44 4>, /* SPI (TPM) */ @@ -513,6 +529,8 @@ &usb_1_ss0_hsphy { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_0_eusb2_repeater>; + status = "okay"; }; @@ -533,6 +551,8 @@ &usb_1_ss1_hsphy { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_1_eusb2_repeater>; + status = "okay"; }; @@ -553,6 +573,8 @@ &usb_1_ss2_hsphy { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&smb2360_2_eusb2_repeater>; + status = "okay"; }; From 08429b4ef46080c79534c4eee427ee2e6012877c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Owoc?= Date: Thu, 29 Feb 2024 21:54:16 +0100 Subject: [PATCH 030/110] arm64: dts: qcom: ipq8074: Add QUP UART6 node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add node to support the QUP UART6 controller inside of IPQ8074. Used by some routers to communicate with a Bluetooth controller. Signed-off-by: PaweÅ‚ Owoc Link: https://lore.kernel.org/r/20240229205426.232205-1-frut3k7@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 87a192de7a68..50f725053b96 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -323,6 +323,13 @@ serial_4_pins: serial4-state { bias-disable; }; + serial_5_pins: serial5-state { + pins = "gpio9", "gpio16"; + function = "blsp5_uart"; + drive-strength = <8>; + bias-disable; + }; + i2c_0_pins: i2c-0-state { pins = "gpio42", "gpio43"; function = "blsp1_i2c"; @@ -471,6 +478,18 @@ blsp1_uart5: serial@78b3000 { status = "disabled"; }; + blsp1_uart6: serial@78b4000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b4000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-0 = <&serial_5_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + blsp1_spi1: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; From c39c5aed65d428f2a1c2364851c8b44702e9d7db Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 4 Mar 2024 11:26:11 +0200 Subject: [PATCH 031/110] arm64: dts: qcom: qrb2210-rb1: enable USB-C port handling Plug in USB-C related bits and pieces to enable USB role switching and USB-C orientation handling for the Qualcomm RB1 board. Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240304-pm4125-typec-v4-2-f3601a16f9ea@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 42 +++++++++++++++++ arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 60 ++++++++++++++++++++---- 2 files changed, 94 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 1aacad50e7fc..8221336a8212 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -694,10 +694,31 @@ usb_qmpphy: phy@1615000 { clock-output-names = "usb3_phy_pipe_clk_src"; #phy-cells = <0>; + orientation-switch; qcom,tcsr-reg = <&tcsr_regs 0xb244>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + }; }; system_noc: interconnect@1880000 { @@ -1380,6 +1401,27 @@ usb_dwc3: usb@4e00000 { snps,usb3_lpm_capable; maximum-speed = "super-speed"; dr_mode = "otg"; + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dwc3_ss: endpoint { + remote-endpoint = <&usb_qmpphy_usb_ss_in>; + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 6e9dd0312adc..fca341300521 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -262,6 +262,46 @@ &pm4125_resin { status = "okay"; }; +&pm4125_typec { + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "dual"; + data-role = "dual"; + self-powered; + + typec-power-opmode = "default"; + pd-disable; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + pm4125_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + pm4125_ss_in: endpoint { + remote-endpoint = <&usb_qmpphy_out>; + }; + }; + }; + }; +}; + +&pm4125_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <500000>; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -535,14 +575,8 @@ &usb { status = "okay"; }; -&usb_qmpphy { - vdda-phy-supply = <&pm4125_l12>; - vdda-pll-supply = <&pm4125_l13>; - status = "okay"; -}; - -&usb_dwc3 { - dr_mode = "host"; +&usb_dwc3_hs { + remote-endpoint = <&pm4125_hs_in>; }; &usb_hsphy { @@ -552,6 +586,16 @@ &usb_hsphy { status = "okay"; }; +&usb_qmpphy { + vdda-phy-supply = <&pm4125_l12>; + vdda-pll-supply = <&pm4125_l13>; + status = "okay"; +}; + +&usb_qmpphy_out { + remote-endpoint = <&pm4125_ss_in>; +}; + &wifi { vdd-0.8-cx-mx-supply = <&pm4125_l7>; vdd-1.8-xo-supply = <&pm4125_l13>; From 9b1e891179cacd12aa77d27a2c00b75fdbef4823 Mon Sep 17 00:00:00 2001 From: Elliot Berman Date: Mon, 4 Mar 2024 14:41:15 -0800 Subject: [PATCH 032/110] arm64: dts: qcom: sm8650: Add missing reserved memory for chipinfo Add missing reserved memory for chipinfo region. Cc: Patrick Daly Cc: Neil Armstrong Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi") Signed-off-by: Elliot Berman Reviewed-by: Mukesh Ojha Link: https://lore.kernel.org/r/20240304-sm8650-missing-chipinfo-region-v1-1-8a0b41dd8308@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 1bfcf069c9ae..32c0a7b9aded 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -485,9 +485,9 @@ aop_cmd_db_mem: aop-cmd-db@81c60000 { no-map; }; - /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ + /* Merged aop_config, tme_crash_dump, tme_log, uefi_log, and chipinfo regions */ aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { - reg = <0 0x81c80000 0 0x74000>; + reg = <0 0x81c80000 0 0x75000>; no-map; }; From 511b4858dc8a1b4d857dc847976a5481c9b367fa Mon Sep 17 00:00:00 2001 From: Hui Liu Date: Mon, 11 Mar 2024 18:09:31 +0800 Subject: [PATCH 033/110] arm64: dts: qcom: qcm6490-idp: enable PMIC Volume and Power buttons The Volume Down & Power buttons are controlled by the PMIC via the PON hardware, and the Volume Up is connected to a PMIC gpio. Enable the necessary hardware and setup the GPIO state for the Volume Up gpio key. Signed-off-by: Hui Liu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240311-gpio-keys-v5-1-08823582f6c9@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 5bbe8aa63927..f8f8a43f638d 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -9,6 +9,7 @@ #define PM7250B_SID 8 #define PM7250B_SID1 9 +#include #include #include #include @@ -59,6 +60,22 @@ lcd_disp_bias: regulator-lcd-disp-bias { pinctrl-names = "default"; }; + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&key_vol_up_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume_up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + linux,can-disable; + }; + }; + reserved-memory { xbl_mem: xbl@80700000 { reg = <0x0 0x80700000 0x0 0x100000>; @@ -511,6 +528,16 @@ pmic_lcd_bl_pwm: pmic-lcd-bl-pwm-state { }; }; +&pm7325_gpios { + key_vol_up_default: key-vol-up-state { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = ; + }; +}; + &pm8350c_pwm { pinctrl-0 = <&pmic_lcd_bl_pwm>; pinctrl-names = "default"; @@ -540,6 +567,15 @@ led@3 { }; }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; From 5582e357d0c6bfdc889773ca3c9b7b0dd31dc334 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 28 Mar 2024 08:45:44 +0100 Subject: [PATCH 034/110] arm64: dts: qcom: pm6150: correct Type-C compatible The first part of the compatible of Type-C node misses ending quote, thus we have one long compatible consisting of two compatible strings leading to dtbs_check warnings: sc7180-idp.dtb: usb-vbus-regulator@1100: compatible:0: 'qcom,pm6150-vbus-reg,\n qcom,pm8150b-vbus-reg' does not match '^[a-zA-Z0-9][a-zA-Z0-9,+\\-._/]+$' sc7180-idp.dtb: /soc@0/spmi@c440000/pmic@0/usb-vbus-regulator@1100: failed to match any schema with compatible: ['qcom,pm6150-vbus-reg,\n qcom,pm8150b-vbus-reg'] Reported-by: Rob Herring Fixes: f81c2f01cad6 ("arm64: dts: qcom: pm6150: define USB-C related blocks") Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240328074544.5076-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6150.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 11158c2bd524..b20a639cddf3 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -71,8 +71,8 @@ pm6150_vbus: usb-vbus-regulator@1100 { }; pm6150_typec: typec@1500 { - compatible = "qcom,pm6150-typec, - qcom,pm8150b-typec"; + compatible = "qcom,pm6150-typec", + "qcom,pm8150b-typec"; reg = <0x1500>, <0x1700>; interrupts = <0x0 0x15 0x00 IRQ_TYPE_EDGE_RISING>, <0x0 0x15 0x01 IRQ_TYPE_EDGE_BOTH>, From 7fb5680b589d5eae64ada1d917b6ff2dab82f5ae Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 2 Apr 2024 05:57:16 +0300 Subject: [PATCH 035/110] arm64: dts: qcom: sc8180x: drop legacy property #stream-id-cells The property #stream-id-cells is legacy, it is not documented as valid for the GPU. Drop it now. Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240402-fd-fix-schema-v3-2-817ea6ddf775@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 32afc78d5b76..99462b42cfc5 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2225,7 +2225,6 @@ tcsr_mutex: hwlock@1f40000 { gpu: gpu@2c00000 { compatible = "qcom,adreno-680.1", "qcom,adreno"; - #stream-id-cells = <16>; reg = <0 0x02c00000 0 0x40000>; reg-names = "kgsl_3d0_reg_memory"; From 580701ec27f61e0996dd5fcd23b091b6bf6933e3 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 2 Apr 2024 05:57:17 +0300 Subject: [PATCH 036/110] arm64: dts: qcom: sc8180x: Drop flags for mdss irqs The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240402-fd-fix-schema-v3-3-817ea6ddf775@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 99462b42cfc5..6d74867d3b61 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2804,7 +2804,7 @@ mdss_mdp: mdp@ae01000 { power-domains = <&rpmhpd SC8180X_MMCX>; interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0>; ports { #address-cells = <1>; @@ -2877,7 +2877,7 @@ mdss_dsi0: dsi@ae94000 { reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <4>; clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, @@ -2963,7 +2963,7 @@ mdss_dsi1: dsi@ae96000 { reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <5>; clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, From 1106ea2266d11ebd97c3493a0c36a45272bfb67a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 2 Apr 2024 05:57:18 +0300 Subject: [PATCH 037/110] arm64: dts: qcom: sc8180x: add dp_p1 register blocks to DP nodes DisplayPort nodes must declare the dp_p1 register space in addition to dp_p0. Add corresponding resource to DisplayPort DT nodes. Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes") Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240402-fd-fix-schema-v3-4-817ea6ddf775@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 6d74867d3b61..019104bd70fb 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3029,7 +3029,8 @@ mdss_dp0: displayport-controller@ae90000 { reg = <0 0xae90000 0 0x200>, <0 0xae90200 0 0x200>, <0 0xae90400 0 0x600>, - <0 0xae90a00 0 0x400>; + <0 0xae90a00 0 0x400>, + <0 0xae91000 0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, @@ -3105,7 +3106,8 @@ mdss_dp1: displayport-controller@ae98000 { reg = <0 0xae98000 0 0x200>, <0 0xae98200 0 0x200>, <0 0xae98400 0 0x600>, - <0 0xae98a00 0 0x400>; + <0 0xae98a00 0 0x400>, + <0 0xae99000 0 0x400>; interrupt-parent = <&mdss>; interrupts = <13>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, From cb69e758d5918cc03e449e159162e263e8bc7ec1 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 28 Feb 2024 17:28:26 -0800 Subject: [PATCH 038/110] arm64: dts: qcom: sc7180: Disable pmic pinctrl node on Trogdor We don't use this pmic pinctrl node on any Trogdor devices. The AP_SUSPEND pin is here, but this pinctrl device isn't a supplier to anything in the devicetrees that include this file. Disable this device node in the DTS so that we don't waste time or memory on this device. Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20240229012828.438020-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index f3a6da8b2890..f0a7de8f4b7f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -1165,6 +1165,7 @@ &pm6150_gpios { }; &pm6150l_gpios { + status = "disabled"; /* No GPIOs are consumed or configured */ gpio-line-names = "AP_SUSPEND", "", "", From 9f618cdce29d7bef10c2f4c8cbf58bc5cb778d6a Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 28 Feb 2024 17:35:01 -0800 Subject: [PATCH 039/110] arm64: dts: qcom: sc7180: Disable DCC node by default We don't use this device on Trogdor boards. If we did, it would be enabled in the sc7180-trogdor.dtsi file. Let's disable this here so that boards with t he sc7180 SoC can decide to enable or disable this device. Cc: Souradeep Chowdhury Fixes: add74cad7c9d ("arm64: dts: qcom: sc7180: Add Data Capture and Compare(DCC) support node") Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20240229013503.483651-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 2b481e20ae38..3215709a7001 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2309,6 +2309,7 @@ dma@10a2000 { compatible = "qcom,sc7180-dcc", "qcom,dcc"; reg = <0x0 0x010a2000 0x0 0x1000>, <0x0 0x010ae000 0x0 0x2000>; + status = "disabled"; }; stm@6002000 { From cb06e2b406279f65890233af103c638d3752d328 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 13 Mar 2024 03:32:09 +0200 Subject: [PATCH 040/110] arm64: dts: qcom: sm8350: Add interconnects to UFS To ensure that UFS doesn't get disconnected from NoC, add interconnect properties to the UFS controller. Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240313-sm8350-ufs-icc-v1-1-73fa2da99779@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a5e7dbbd8c6c..a878f5ac5bb5 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -1730,6 +1731,11 @@ ufs_mem_hc: ufshc@1d84000 { <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ufs-ddr", "cpu-ufs"; freq-table-hz = <75000000 300000000>, <0 0>, From 5f78d9213ae753e2242b0f6a5d4a5e98e55ddc76 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Owoc?= Date: Wed, 13 Mar 2024 11:27:06 +0100 Subject: [PATCH 041/110] arm64: dts: qcom: ipq8074: Remove unused gpio from QPIC pins MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit gpio16 will only be used for LCD support, as its NAND/LCDC data[8] so its bit 9 of the parallel QPIC interface, and ONFI NAND is only 8 or 16-bit with only 8-bit one being supported in our case so that pin is unused. It should be dropped from the default NAND pinctrl configuration as its unused and only needed for LCD. Signed-off-by: PaweÅ‚ Owoc Reviewed-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20240313102713.1727458-1-frut3k7@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 7e4e6a5a02d5..bed405559866 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -356,7 +356,7 @@ qpic_pins: qpic-state { "gpio5", "gpio6", "gpio7", "gpio8", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", - "gpio15", "gpio16", "gpio17"; + "gpio15", "gpio17"; function = "qpic"; drive-strength = <8>; bias-disable; From dfd5ee7b34bb7611d4d2f4f3cb37152baeaae96d Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 13 Mar 2024 13:53:15 +0100 Subject: [PATCH 042/110] arm64: dts: qcom: sc7280: Add inline crypto engine Add the ICE found on sc7280 and link it to the UFS node. For reference: [ 0.261424] qcom-ice 1d88000.crypto: Found QC Inline Crypto Engine (ICE) v3.2.0 Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240313-sc7280-ice-v1-2-3fa089fb7a27@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 7e7f0f0fb41b..6518c9c3a07f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2352,6 +2352,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <0 0>, <0 0>, <0 0>; + qcom,ice = <&ice>; + status = "disabled"; }; @@ -2374,6 +2376,13 @@ ufs_mem_phy: phy@1d87000 { status = "disabled"; }; + ice: crypto@1d88000 { + compatible = "qcom,sc7280-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d88000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; From 88d0e4e10d77bb4e575b74ac0f6dd3140ecc3bcd Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 14 Mar 2024 03:42:48 +0200 Subject: [PATCH 043/110] dt-bindings: arm: qcom: drop dtbTool-specific compatibles Drop two board compatibles that were used by the skales dtbTool to index device tree blobs. It was required to boot those devices with the original bootloader, however all users should have switched to the lk2nd bootloader by now. Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240314-msm8916-drop-compats-v2-1-5a4b40f832d3@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 66beaac60e1d..66c98a1c8ac6 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -187,11 +187,6 @@ properties: - const: qcom,msm8974pro - const: qcom,msm8974 - - items: - - const: qcom,msm8916-mtp - - const: qcom,msm8916-mtp/1 - - const: qcom,msm8916 - - items: - enum: - acer,a1-724 @@ -200,6 +195,8 @@ properties: - gplus,fl8005a - huawei,g7 - longcheer,l8910 + - longcheer,l8150 + - qcom,msm8916-mtp - samsung,a3u-eur - samsung,a5u-eur - samsung,e5 @@ -220,11 +217,6 @@ properties: - yiming,uz801-v3 - const: qcom,msm8916 - - items: - - const: longcheer,l8150 - - const: qcom,msm8916-v1-qrd/9-v1 - - const: qcom,msm8916 - - items: - enum: - motorola,potter From 3867ad6d39cd97875aca7e5f1b17ea6dd5b1107a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 14 Mar 2024 03:42:49 +0200 Subject: [PATCH 044/110] arm64: dts: qcom: msm8916: drop dtbTool-specific compatibles Drop two board compatibles that were used by the skales dtbTool to index device tree blobs. It was required to boot those devices with the original bootloader, however all users should have switched to the lk2nd bootloader by now. Suggested-by: Stephan Gerhold Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240314-msm8916-drop-compats-v2-2-5a4b40f832d3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts | 2 +- arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 3a3e794c022f..7f0c2c1b8a94 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -12,7 +12,7 @@ / { model = "Longcheer L8150"; - compatible = "longcheer,l8150", "qcom,msm8916-v1-qrd/9-v1", "qcom,msm8916"; + compatible = "longcheer,l8150", "qcom,msm8916"; chassis-type = "handset"; aliases { diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts index ac527a3a0826..c11a845e91bb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts @@ -9,7 +9,7 @@ / { model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; - compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", "qcom,msm8916"; + compatible = "qcom,msm8916-mtp", "qcom,msm8916"; chassis-type = "handset"; aliases { From 9f42f7380f6757ce7f0cab5bad56fb350941d32b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 14 Mar 2024 09:53:06 +0100 Subject: [PATCH 045/110] arm64: dts: qcom: sm8650: fix usb interrupts properties Update the usb interrupts properties to fix the following bindings check errors: usb@a6f8800: interrupt-names:0: 'pwr_event' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# usb@a6f8800: interrupt-names:1: 'hs_phy_irq' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# usb@a6f8800: interrupt-names:2: 'dp_hs_phy_irq' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# usb@a6f8800: interrupt-names:3: 'dm_hs_phy_irq' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# usb@a6f8800: interrupt-names: ['hs_phy_irq', 'ss_phy_irq', 'dm_hs_phy_irq', 'dp_hs_phy_irq'] is too short from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# Cc: Krishna Kurapati Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240314-topic-sm8650-upstream-usb-dt-irq-fix-v1-1-ea8ab2051869@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 32c0a7b9aded..fc057ea41d56 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3584,14 +3584,16 @@ usb_1: usb@a6f8800 { compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>, <&pdc 15 IRQ_TYPE_EDGE_RISING>, - <&pdc 14 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", - "dp_hs_phy_irq"; + "ss_phy_irq"; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, From 216e62744b91c9716228fe13f564e83381a1342e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 14 Mar 2024 12:26:57 +0100 Subject: [PATCH 046/110] arm64: dts: qcom: apq8016-sbc: correct GPIO LEDs node names Individual LEDs in a GPIO LEDs device node are not addressable, thus unit address is not correct. dtc is also not happy: Warning (unit_address_vs_reg): /leds/led@5: node has a unit name, but no reg or ranges property Reported-by: Sumit Garg Closes: https://lore.kernel.org/all/CAFA6WYNRwF7GqhBk2B7i-deT3aLxNQckhnOasjip2TYm4HZgAw@mail.gmail.com/ Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sumit Garg Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240314112657.167006-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 9ffad7d1f2b6..aba08424aa38 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -91,7 +91,7 @@ leds { compatible = "gpio-leds"; - led@1 { + led-1 { label = "apq8016-sbc:green:user1"; function = LED_FUNCTION_HEARTBEAT; color = ; @@ -100,7 +100,7 @@ led@1 { default-state = "off"; }; - led@2 { + led-2 { label = "apq8016-sbc:green:user2"; function = LED_FUNCTION_DISK_ACTIVITY; color = ; @@ -109,7 +109,7 @@ led@2 { default-state = "off"; }; - led@3 { + led-3 { label = "apq8016-sbc:green:user3"; function = LED_FUNCTION_DISK_ACTIVITY; color = ; @@ -118,7 +118,7 @@ led@3 { default-state = "off"; }; - led@4 { + led-4 { label = "apq8016-sbc:green:user4"; color = ; gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>; @@ -127,7 +127,7 @@ led@4 { default-state = "off"; }; - led@5 { + led-5 { label = "apq8016-sbc:yellow:wlan"; function = LED_FUNCTION_WLAN; color = ; @@ -136,7 +136,7 @@ led@5 { default-state = "off"; }; - led@6 { + led-6 { label = "apq8016-sbc:blue:bt"; function = LED_FUNCTION_BLUETOOTH; color = ; From d2209f6730051cf9caec1877699329a9c0cd6ac6 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 14 Mar 2024 19:56:23 +0100 Subject: [PATCH 047/110] dt-bindings: arm: qcom: Add Sony Xperia Z3 Add the compatible for this Sony smartphone. Acked-by: Krzysztof Kozlowski Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240314-shinano-common-v2-2-a0fce1c72c74@z3ntu.xyz Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 66c98a1c8ac6..1646e5bd23d8 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -184,6 +184,7 @@ properties: - oneplus,bacon - samsung,klte - sony,xperia-castor + - sony,xperia-leo - const: qcom,msm8974pro - const: qcom,msm8974 From 0fba148c3ac0fb8bc3d2a788c19b2ede4e5d3695 Mon Sep 17 00:00:00 2001 From: Sebastian Raase Date: Fri, 15 Mar 2024 09:59:25 +0100 Subject: [PATCH 048/110] arm64: dts: qcom: sdm630-nile: add pinctrl for camera key Add pinctrl configuration for gpio-keys. Without this, camera button half-presses are not detected. Tested on discovery and pioneer. Fixes: e781633b6067 ("arm64: dts: qcom: Add support for Sony Xperia XA2/Plus/Ultra (Nile platform)") Signed-off-by: Sebastian Raase Link: https://lore.kernel.org/r/20240315085934.1511722-1-linux@sraa.de Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 819a5f8825e7..a4b722e0fc1e 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -90,6 +90,8 @@ cam_vana_rear_vreg: cam-vana-rear-regulator { gpio-keys { compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; key-camera-focus { label = "Camera Focus"; @@ -645,6 +647,13 @@ ts_lcd_id_active: ts-lcd-id-active-state { bias-disable; }; + gpio_keys_default: gpio-keys-default-state { + pins = "gpio64", "gpio113"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + imx300_vana_default: imx300-vana-default-state { pins = "gpio50"; function = "gpio"; From 83ef6a5afc1d5e2270797a164972a3de3bd2ea52 Mon Sep 17 00:00:00 2001 From: Sebastian Raase Date: Fri, 15 Mar 2024 23:52:29 +0100 Subject: [PATCH 049/110] arm64: dts: qcom: msm8998-yoshino: fix volume-up key The volume-up key is connected to gpio6 on yoshino. Fix button node ordering while at it. Disable pm8998_resin, since it is now unused. Tested on maple and lilac. Fixes: 390883af89d2e ("arm64: dts: qcom: msm8998: Introduce support for Sony Yoshino platform") Signed-off-by: Sebastian Raase Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240315225237.1616550-1-linux@sraa.de Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 44 +++++++++++-------- 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 876c6921ddf0..fdd3953938d9 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -98,30 +98,35 @@ extcon_usb: extcon-usb { gpio-keys { compatible = "gpio-keys"; label = "Side buttons"; + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &vol_up_n>; pinctrl-names = "default"; - pinctrl-0 = <&vol_down_n &focus_n &snapshot_n>; - button-vol-down { - label = "Volume Down"; - gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - wakeup-source; + button-camera-focus { + label = "Camera Focus"; + gpios = <&pm8998_gpios 8 GPIO_ACTIVE_LOW>; + linux,code = ; debounce-interval = <15>; }; button-camera-snapshot { label = "Camera Snapshot"; gpios = <&pm8998_gpios 7 GPIO_ACTIVE_LOW>; - linux,input-type = ; linux,code = ; debounce-interval = <15>; }; - button-camera-focus { - label = "Camera Focus"; - gpios = <&pm8998_gpios 8 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; + button-vol-down { + label = "Volume Down"; + gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + button-vol-up { + label = "Volume Up"; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; debounce-interval = <15>; }; }; @@ -345,6 +350,14 @@ vol_down_n: vol-down-n-state { qcom,drive-strength = ; }; + vol_up_n: vol-up-n-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-pull-up; + input-enable; + qcom,drive-strength = ; + }; + focus_n: focus-n-state { pins = "gpio7"; function = PMIC_GPIO_FUNC_NORMAL; @@ -405,11 +418,6 @@ vib_ldo_en: vib-ldo-en-state { }; }; -&pm8998_resin { - linux,code = ; - status = "okay"; -}; - &qusb2phy { status = "okay"; From 7c2a774f028f6e2acc40bf969fcac288d3143c7f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 16 Mar 2024 13:10:46 +0100 Subject: [PATCH 050/110] arm64: dts: qcom: msm8998-yoshino: Enable RGB led Add the multicolor description and enable the PMI8998 LPG to expose the RGB notification LED. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240316-topic-maple_led-v1-1-ca3430fd9dc5@linaro.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index fdd3953938d9..d8cc0d729e99 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -418,6 +418,35 @@ vib_ldo_en: vib-ldo-en-state { }; }; +&pmi8998_lpg { + qcom,power-source = <1>; + + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@3 { + reg = <3>; + color = ; + }; + + led@4 { + reg = <4>; + color = ; + }; + + led@5 { + reg = <5>; + color = ; + }; + }; +}; + &qusb2phy { status = "okay"; From d0d6230aa9652afc2c96a83eb2d217761683cad8 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 26 Mar 2024 19:04:18 -0700 Subject: [PATCH 051/110] arm64: dts: qcom: sc7280: Enable MDP turbo mode The max frequency listed in the DPU opp-table is 506MHz, this is not sufficient to drive a 4k@60 display, resulting in constant underrun. Add the missing MDP_CLK turbo frequency of 608MHz to the opp-table to fix this. Acked-by: Douglas Anderson Reviewed-by: Abhinav Kumar Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20240326-rb3gen2-dp-connector-v2-1-a9f1bc32ecaf@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 6518c9c3a07f..bd9b1898d7a7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4467,6 +4467,11 @@ opp-506666667 { opp-hz = /bits/ 64 <506666667>; required-opps = <&rpmhpd_opp_nom>; }; + + opp-608000000 { + opp-hz = /bits/ 64 <608000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; }; }; From 756efb7cb7293b0d971f661405e044cceab13d99 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 26 Mar 2024 19:04:19 -0700 Subject: [PATCH 052/110] arm64: dts: qcom: qcs6490-rb3gen2: Add DP output The RB3Gen2 board comes with a mini DP connector, describe this, enable MDSS, DP controller and the PHY that drives this. Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240326-rb3gen2-dp-connector-v2-2-a9f1bc32ecaf@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 40 ++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 63ebe0774f1d..f90bf3518e98 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -39,6 +39,20 @@ chosen { stdout-path = "serial0:115200n8"; }; + dp-connector { + compatible = "dp-connector"; + label = "DP"; + type = "mini"; + + hpd-gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; + + port { + dp_connector_in: endpoint { + remote-endpoint = <&mdss_edp_out>; + }; + }; + }; + reserved-memory { xbl_mem: xbl@80700000 { reg = <0x0 0x80700000 0x0 0x100000>; @@ -471,6 +485,25 @@ &gcc { ; }; +&mdss { + status = "okay"; +}; + +&mdss_edp { + status = "okay"; +}; + +&mdss_edp_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&dp_connector_in>; +}; + +&mdss_edp_phy { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -511,3 +544,10 @@ &usb_1_qmpphy { &wifi { memory-region = <&wlan_fw_mem>; }; + +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + +&edp_hot_plug_det { + function = "gpio"; + bias-disable; +}; From 3eb0b024decf99f917509db124f399dc47894075 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 26 Mar 2024 19:04:20 -0700 Subject: [PATCH 053/110] arm64: dts: qcom: qcs6490-rb3gen2: Enable adsp and cdsp Define firmware paths and enable the ADSP and CDSP remoteprocs. Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240326-rb3gen2-dp-connector-v2-3-a9f1bc32ecaf@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index f90bf3518e98..5b267a94a282 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -508,6 +508,16 @@ &qupv3_id_0 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/qcs6490/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs6490/cdsp.mbn"; + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ From a1615efb7c775adbee5400739a5e0a0d7a548dd8 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 26 Mar 2024 19:04:21 -0700 Subject: [PATCH 054/110] arm64: dts: qcom: qcs6490-rb3gen2: Introduce USB redriver The RB3gen2 has a USB redriver on APPS_I2C, enable the bus and introduce the redriver. The plumbing with other components is kept separate for clarity. Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240326-rb3gen2-dp-connector-v2-4-a9f1bc32ecaf@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 5b267a94a282..2f94b1b865e7 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -485,6 +485,20 @@ &gcc { ; }; +&i2c1 { + status = "okay"; + + typec-mux@1c { + compatible = "onnn,nb7vpq904m"; + reg = <0x1c>; + + vcc-supply = <&vreg_l18b_1p8>; + + retimer-switch; + orientation-switch; + }; +}; + &mdss { status = "okay"; }; From c3d9acc529d581e3391dac3578812a7402e21c8a Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 26 Mar 2024 19:04:22 -0700 Subject: [PATCH 055/110] arm64: dts: qcom: qcs6490-rb3gen2: Enable USB Type-C display With the ADSP remoteproc loaded pmic_glink can be introduced and together with the redriver wired up to provide role and orientation switching signals as well as USB Type-C display on the RB3gen2. Reviewed-by: Neil Armstrong Tested-By: Krishna Kurapati PSSNV Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240326-rb3gen2-dp-connector-v2-5-a9f1bc32ecaf@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 107 ++++++++++++++++++- 1 file changed, 106 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 2f94b1b865e7..3cc19ccff90c 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -135,6 +135,49 @@ debug_vm_mem: debug-vm@d0600000 { }; }; + pmic-glink { + compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&redriver_usb_con_ss>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu_in: endpoint { + remote-endpoint = <&redriver_usb_con_sbu>; + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -496,6 +539,36 @@ typec-mux@1c { retimer-switch; orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + redriver_usb_con_ss: endpoint { + remote-endpoint = <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + redriver_phy_con_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + data-lanes = <0 1 2 3>; + }; + }; + + port@2 { + reg = <2>; + + redriver_usb_con_sbu: endpoint { + remote-endpoint = <&pmic_glink_sbu_in>; + }; + }; + }; }; }; @@ -503,6 +576,15 @@ &mdss { status = "okay"; }; +&mdss_dp { + status = "okay"; +}; + +&mdss_dp_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_dp_qmpphy_dp_in>; +}; + &mdss_edp { status = "okay"; }; @@ -547,7 +629,16 @@ &usb_1 { }; &usb_1_dwc3 { - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; &usb_1_hsphy { @@ -562,9 +653,23 @@ &usb_1_qmpphy { vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p912>; + orientation-switch; + status = "okay"; }; +&usb_dp_qmpphy_out { + remote-endpoint = <&redriver_phy_con_ss>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + +&usb_dp_qmpphy_dp_in { + remote-endpoint = <&mdss_dp_out>; +}; + &wifi { memory-region = <&wlan_fw_mem>; }; From f8dddefcb90eaa339c77b2cb3f5a87dec8b1e3b5 Mon Sep 17 00:00:00 2001 From: Joe Mason Date: Thu, 4 Apr 2024 12:17:44 +0000 Subject: [PATCH 056/110] arm64: dts: qcom: msm8916-samsung-fortuna: Add touchscreen Like msm8916-samsung-a3u-eur, the Grand Prime uses a Zinitix BT541 touchscreen. Add it together with the necessary fixed-regulator to the device tree. Signed-off-by: Joe Mason [Raymond: Move to fortuna-common. Use interrupts-extended] Signed-off-by: Raymond Hackley Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240404121703.17086-2-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- .../qcom/msm8916-samsung-fortuna-common.dtsi | 47 +++++++++++++++++++ .../qcom/msm8916-samsung-rossa-common.dtsi | 3 ++ 2 files changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi index c2800ad2dd5b..6c66a24ef1af 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi @@ -66,6 +66,19 @@ reg_motor_vdd: regulator-motor-vdd { pinctrl-0 = <&motor_en_default>; pinctrl-names = "default"; }; + + reg_vdd_tsp_a: regulator-vdd-tsp-a { + compatible = "regulator-fixed"; + regulator-name = "vdd_tsp_a"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tsp_en_default>; + pinctrl-names = "default"; + }; }; &blsp_i2c1 { @@ -94,6 +107,26 @@ fuel-gauge@35 { }; }; +&blsp_i2c5 { + status = "okay"; + + touchscreen: touchscreen@20 { + compatible = "zinitix,bt541"; + reg = <0x20>; + + interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <540>; + touchscreen-size-y = <960>; + + vcca-supply = <®_vdd_tsp_a>; + vdd-supply = <&pm8916_l6>; + + pinctrl-0 = <&tsp_int_default>; + pinctrl-names = "default"; + }; +}; + &blsp_uart2 { status = "okay"; }; @@ -200,4 +233,18 @@ sdc2_cd_default: sdc2-cd-default-state { drive-strength = <2>; bias-disable; }; + + tsp_en_default: tsp-en-default-state { + pins = "gpio73"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_default: tsp-int-default-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi index 42843771ae2a..4048b72efcdc 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi @@ -5,6 +5,9 @@ /* SM5504 MUIC instead of SM5502 */ /delete-node/ &muic; +/* Touchscreen varies depending on model variant */ +/delete-node/ &touchscreen; + &blsp_i2c1 { muic: extcon@14 { compatible = "siliconmitus,sm5504-muic"; From 05c65922bd58cc3fc057b37628b143f76e524496 Mon Sep 17 00:00:00 2001 From: Siddharth Manthan Date: Thu, 4 Apr 2024 12:17:57 +0000 Subject: [PATCH 057/110] arm64: dts: qcom: msm8916-samsung-fortuna: Add PWM backlight Most of the Galaxy Grand Prime use backlight drivers controlled with PWM signal. To simplify the description, add the backlight with the necessary clk-pwm to the common dtsi. Signed-off-by: Siddharth Manthan [Stephan: Move to fortuna-common and disable on rossa-common] Signed-off-by: Stephan Gerhold [Raymond: Add the commit message] Signed-off-by: Raymond Hackley Link: https://lore.kernel.org/r/20240404121703.17086-3-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- .../qcom/msm8916-samsung-fortuna-common.dtsi | 36 +++++++++++++++++++ .../qcom/msm8916-samsung-rossa-common.dtsi | 9 +++++ 2 files changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi index 6c66a24ef1af..5e933fb8b363 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-fortuna-common.dtsi @@ -26,6 +26,30 @@ tz-apps@85a00000 { }; }; + clk_pwm_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&clk_pwm 0 100000>; + + enable-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <128>; + + pinctrl-0 = <&backlight_en_default>; + pinctrl-names = "default"; + }; + + clk_pwm: pwm { + compatible = "clk-pwm"; + #pwm-cells = <2>; + + clocks = <&gcc GCC_GP2_CLK>; + + pinctrl-0 = <&backlight_pwm_default>; + pinctrl-names = "default"; + }; + gpio-keys { compatible = "gpio-keys"; @@ -199,6 +223,18 @@ &wcnss_mem { }; &tlmm { + backlight_en_default: backlight-en-default-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + backlight_pwm_default: backlight-pwm-default-state { + pins = "gpio50"; + function = "gcc_gp2_clk_a"; + }; + fg_alert_default: fg-alert-default-state { pins = "gpio121"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi index 4048b72efcdc..b438fa81886c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-rossa-common.dtsi @@ -17,3 +17,12 @@ muic: extcon@14 { pinctrl-names = "default"; }; }; + +/* On rossa backlight is controlled with MIPI DCS commands */ +&clk_pwm { + status = "disabled"; +}; + +&clk_pwm_backlight { + status = "disabled"; +}; From e5fd6512f6e842d8c5883b9fa4d72c8a5295efdc Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 3 Apr 2024 20:10:12 +0300 Subject: [PATCH 058/110] arm64: dts: qcom: sm8150-hdk: enable WiFI support Enable modem DSP and WiFI devices on the SM8150 HDK device. The HDK is manufactured by Lantronix, but it attributed to Qualcomm, so the calibration string uses Qualcomm as manufacturer. For reference: ath10k_snoc 18800000.wifi: qmi chip_id 0x30224 chip_family 0x4001 board_id 0x55 soc_id 0x40060000 ath10k_snoc 18800000.wifi: qmi fw_version 0x32040163 fw_build_timestamp 2019-10-08 05:42 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.3.2.0-00355-QCAHLSWMTPLZ-1 ath10k_snoc 18800000.wifi: wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 ath10k_snoc 18800000.wifi: kconfig debug 1 debugfs 0 tracing 0 dfs 0 testmode 0 ath10k_snoc 18800000.wifi: firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi crc32 b3d4b790 ath10k_snoc 18800000.wifi: htt-ver 3.73 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 ath10k_snoc 18800000.wifi: invalid MAC address; choosing random Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240403-sm8150-hdk-wifi-v1-1-8da3063829c2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index de670b407ef1..6cb6f503fdac 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -609,6 +609,11 @@ &remoteproc_cdsp { firmware-name = "qcom/sm8150/cdsp.mbn"; }; +&remoteproc_mpss { + firmware-name = "qcom/sm8150/modem.mbn"; + status = "okay"; +}; + &remoteproc_slpi { status = "okay"; @@ -713,3 +718,14 @@ &usb_1_dwc3_ss { &usb_2_dwc3 { dr_mode = "host"; }; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l1a_0p75>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l2c_1p3>; + vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; + + qcom,ath10k-calibration-variant = "Qualcomm_sm8150hdk"; +}; From 58dc9622d5de6ce0b80969b136e8e09a7645eca5 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 27 Mar 2024 19:01:13 -0700 Subject: [PATCH 059/110] arm64: dts: qcom: qcs6490-rb3gen2: Enable UFS The rb3gen2 has UFS memory, adjust the necessary supply voltage and add the controller and phy nodes to enable this. Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240327-rb3gen2-ufs-v2-1-3de6b5dd78dd@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 28 +++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 3cc19ccff90c..c98c41f8f3b1 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -278,8 +278,8 @@ vreg_l6b_1p2: ldo6 { vreg_l7b_2p952: ldo7 { regulator-name = "vreg_l7b_2p952"; - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <3544000>; + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; regulator-initial-mode = ; }; @@ -293,8 +293,11 @@ vreg_l8b_0p904: ldo8 { vreg_l9b_1p2: ldo9 { regulator-name = "vreg_l9b_1p2"; regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1304000>; + regulator-max-microvolt = <1200000>; regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; }; vreg_l11b_1p504: ldo11 { @@ -670,6 +673,25 @@ &usb_dp_qmpphy_dp_in { remote-endpoint = <&mdss_dp_out>; }; +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l7b_2p952>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; + vccq2-supply = <&vreg_l9b_1p2>; + vccq2-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + &wifi { memory-region = <&wlan_fw_mem>; }; From 6c747d0fe72a85157ec9b95a3100fb98c81ad456 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Mon, 1 Apr 2024 21:22:40 +0300 Subject: [PATCH 060/110] arm64: dts: qcom: sc7180: Fix UFS PHY clocks QMP PHY used in SC7180 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Signed-off-by: Danila Tikhonov Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20240401182240.55282-3-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 3215709a7001..4774a859bd7e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1585,9 +1585,12 @@ ufs_mem_phy: phy@1d87000 { compatible = "qcom,sc7180-qmp-ufs-phy", "qcom,sm7150-qmp-ufs-phy"; reg = <0 0x01d87000 0 0x1000>; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - clock-names = "ref", "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>; + clock-names = "ref", + "ref_aux", + "qref"; power-domains = <&gcc UFS_PHY_GDSC>; resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; From 212729551c4186a1a1cbd80379375b1b54488369 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:10 +0100 Subject: [PATCH 061/110] dt-bindings: arm: qcom: Add Xperia 1 V Document the SM8550 SONY Xperia 1 V (PDX234) board. Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240210-topic-1v-v1-2-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1646e5bd23d8..bdc4a8d5388c 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -996,6 +996,7 @@ properties: - qcom,sm8550-hdk - qcom,sm8550-mtp - qcom,sm8550-qrd + - sony,pdx234 - const: qcom,sm8550 - items: From 91fc74458d833dbc999aa04ca34c2a197711a0b6 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:11 +0100 Subject: [PATCH 062/110] arm64: dts: qcom: sm8550: Mark QUPs and GPI dma-coherent These peripherals are DMA-coherent on 8550. Mark them as such. Interestingly enough, the I2C master hubs are not. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240210-topic-1v-v1-3-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 5cae8d773cec..463fc1e8bc91 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -812,6 +812,7 @@ gpi_dma2: dma-controller@800000 { dma-channels = <12>; dma-channel-mask = <0x3e>; iommus = <&apps_smmu 0x436 0>; + dma-coherent; status = "disabled"; }; @@ -823,6 +824,7 @@ qupv3_id_1: geniqup@8c0000 { clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; iommus = <&apps_smmu 0x423 0>; + dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled"; @@ -1322,6 +1324,7 @@ gpi_dma1: dma-controller@a00000 { dma-channels = <12>; dma-channel-mask = <0x1e>; iommus = <&apps_smmu 0xb6 0>; + dma-coherent; status = "disabled"; }; @@ -1335,6 +1338,7 @@ qupv3_id_0: geniqup@ac0000 { iommus = <&apps_smmu 0xa3 0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; interconnect-names = "qup-core"; + dma-coherent; #address-cells = <2>; #size-cells = <2>; status = "disabled"; From 93395f9a8d52b89868d75e278adaf002f99dec22 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:12 +0100 Subject: [PATCH 063/110] arm64: dts: qcom: sm8550: Mark APPS SMMU as dma-coherent Like on earlier flagship Qualcomm SoCs, the SMMU is dma-coherent. Mark it as such. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240210-topic-1v-v1-4-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 463fc1e8bc91..d60984d5ae4d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3972,6 +3972,7 @@ apps_smmu: iommu@15000000 { , , ; + dma-coherent; }; intc: interrupt-controller@17100000 { From d18b5477dcea7775a562b3ba7aaa68772c8980ba Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:13 +0100 Subject: [PATCH 064/110] arm64: dts: qcom: sm8550: Add missing DWC3 quirks As expected, Qualcomm DWC3 implementation come with a sizable number of quirks. Make sure to account for all of them. Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes") Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240210-topic-1v-v1-5-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index d60984d5ae4d..a72627f4d8cd 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3231,12 +3231,20 @@ usb_1_dwc3: usb@a600000 { reg = <0x0 0x0a600000 0x0 0xcd00>; interrupts = ; iommus = <&apps_smmu 0x40 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,usb3_lpm_capable; phys = <&usb_1_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; ports { #address-cells = <1>; From 6e4f7e53991ca7e70dc7d5d9d66c833091e1f6ae Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:14 +0100 Subject: [PATCH 065/110] arm64: dts: qcom: sm8550: Mark DWC3 as dma-coherent In a fairly new development, Qualcomm somehow made the DWC3 block cache-coherent. Annotate that. Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes") Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240210-topic-1v-v1-6-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index a72627f4d8cd..5adb9b178b05 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3245,6 +3245,7 @@ usb_1_dwc3: usb@a600000 { snps,usb2-lpm-disable; snps,has-lpm-erratum; tx-fifo-resize; + dma-coherent; ports { #address-cells = <1>; From 39c596304e44781c1950ea0cbf178d6433ff9c71 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 12 Feb 2024 14:10:15 +0100 Subject: [PATCH 066/110] arm64: dts: qcom: Add SM8550 Xperia 1 V Add support for Sony Xperia 1 V, a.k.a PDX234. This device is a part of the SoMC SM8550 Yodo platform. This commit brings support for: * Remoteprocs (sans modem for now) * Flash LED (the notification LED is gone :((((() * SD Card * USB (*including SuperSpeed*) + PMIC_GLINK (it's funky, requires a replug with an cable flip sometimes..) * Most regulators * Part of I2C-connected peripherals (notably no touch due to a driver bug) * PCIe0 (PCIe1 is unused) Do note display via simplefb is not supported, as the display is blanked upon exiting XBL. To create a working boot image, you need to run: cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/sm8550-sony-xperia-\ yodo-pdx234.dtb > .Image.gz-dtb mkbootimg \ --kernel .Image.gz-dtb \ --ramdisk some_initrd.img \ --pagesize 4096 \ --base 0x0 \ --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 \ --tags_offset 0x100 \ --cmdline "SOME_CMDLINE" \ --dtb_offset 0x1f00000 \ --header_version 2 \ -o boot.img-sony-xperia-pdx234 Then, you need to flash it on the device and get rid of all the vendor_boot/dtbo mess: // You have to either pull vbmeta{"","_system"} from // /dev/block/bootdevice/by-name/ or build one as a part of AOSP build process fastboot --disable-verity --disable-verification flash vbmeta vbmeta.img fastboot --disable-verity --disable-verification flash vbmeta_system \ vbmeta_system.img fastboot flash boot boot.img-sony-xperia-pdx234 fastboot erase vendor_boot fastboot erase recovery fastboot flash dtbo emptydtbo.img fastboot erase init_boot // ? I don't remember if it's necessary, sorry fastboot continue Where emptydtbo.img is a tiny file that consists of 2 bytes (all zeroes), doing a "fastboot erase" won't cut it, the bootloader will go crazy and things will fall apart when it tries to overlay random bytes from an empty partition onto a perfectly good appended DTB. Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240210-topic-1v-v1-7-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../qcom/sm8550-sony-xperia-yodo-pdx234.dts | 779 ++++++++++++++++++ 2 files changed, 780 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7d40ec5e7d21..f63abb43e9fe 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -241,6 +241,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts new file mode 100644 index 000000000000..85e0d3d66e16 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -0,0 +1,779 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "sm8550.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 5 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +/* TODO: Only one SID of PMR735D seems accessible? */ + +/delete-node/ &hwfence_shbuf; +/delete-node/ &mpss_mem; +/delete-node/ &rmtfs_mem; +/ { + model = "Sony Xperia 1 V"; + compatible = "sony,pdx234", "qcom,sm8550"; + chassis-type = "handset"; + + aliases { + i2c0 = &i2c0; + i2c4 = &i2c4; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c16 = &i2c_hub_2; + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n>; + pinctrl-names = "default"; + + key-camera-focus { + label = "Camera Focus"; + linux,code = ; + gpios = <&pm8550b_gpios 8 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-camera-snapshot { + label = "Camera Snapshot"; + gpios = <&pm8550b_gpios 7 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + linux,code = ; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; + }; + }; + + reserved-memory { + mpss_mem: mpss-region@89800000 { + reg = <0x0 0x89800000 0x0 0x10800000>; + no-map; + }; + + splash@b8000000 { + reg = <0x0 0xb8000000 0x0 0x2b00000>; + no-map; + }; + + hwfence_shbuf: hwfence-shbuf-region@e6440000 { + reg = <0x0 0xe6440000 0x0 0x2dd000>; + no-map; + }; + + rmtfs_mem: memory@f8b00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xf8b00000 0x0 0x280000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + + ramoops@ffd00000 { + compatible = "ramoops"; + reg = <0x0 0xffd00000 0x0 0xc0000>; + console-size = <0x40000>; + record-size = <0x1000>; + pmsg-size = <0x40000>; + ecc-size = <16>; + }; + + rdtag-store-region@ffdc0000 { + reg = <0x0 0xffdc0000 0x0 0x40000>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + pm8550_bob1: bob1 { + regulator-name = "pm8550_bob1"; + regulator-min-microvolt = <3416000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + /* TODO: bob2 @ 2.704-3.008V doesn't fall into the vreg driver constraints */ + + pm8550_l1: ldo1 { + regulator-name = "pm8550_l1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8550_l2: ldo2 { + regulator-name = "pm8550_l2"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + /* L4 exists in cmd-db, but the board seems to crash on access */ + + pm8550_l5: ldo5 { + regulator-name = "pm8550_l5"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + pm8550_l6: ldo6 { + regulator-name = "pm8550_l6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + pm8550_l7: ldo7 { + regulator-name = "pm8550_l7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + pm8550_l8: ldo8 { + regulator-name = "pm8550_l8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + pm8550_l9: ldo9 { + regulator-name = "pm8550_l9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + pm8550_l10: ldo10 { + regulator-name = "pm8550_l10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8550_l11: ldo11 { + regulator-name = "pm8550_l11"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + }; + + pm8550_l12: ldo12 { + regulator-name = "pm8550_l12"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8550_l13: ldo13 { + regulator-name = "pm8550_l13"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + pm8550_l14: ldo14 { + regulator-name = "pm8550_l14"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + pm8550_l15: ldo15 { + regulator-name = "pm8550_l15"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + pm8550_l16: ldo16 { + regulator-name = "pm8550_l16"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + pm8550_l17: ldo17 { + regulator-name = "pm8550_l17"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "c"; + + pm8550vs_0_l1: ldo1 { + regulator-name = "pm8550vs_0_l1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + pm8550vs_0_l3: ldo3 { + regulator-name = "pm8550vs_0_l3"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "d"; + + pm8550vs_1_l1: ldo1 { + regulator-name = "pm8550vs_1_l1"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + /* L3 exists in cmd-db, but the board seems to crash on access */ + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "e"; + + pm8550vs_2_s4: smps4 { + regulator-name = "pm8550vs_2_s4"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = ; + }; + + pm8550vs_2_s5: smps5 { + regulator-name = "pm8550vs_2_s5"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + pm8550vs_2_l1: ldo1 { + regulator-name = "pm8550vs_2_l1"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + pm8550vs_2_l2: ldo2 { + regulator-name = "pm8550vs_2_l2"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <968000>; + regulator-initial-mode = ; + }; + + pm8550vs_2_l3: ldo3 { + regulator-name = "pm8550vs_2_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "f"; + + pm8550ve_s4: smps4 { + regulator-name = "pm8550ve_s4"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = ; + }; + + pm8550ve_l1: ldo1 { + regulator-name = "pm8550ve_l1"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + pm8550ve_l2: ldo2 { + regulator-name = "pm8550ve_l2"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + pm8550ve_l3: ldo3 { + regulator-name = "pm8550ve_l3"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "g"; + + pm8550vs_3_s1: smps1 { + regulator-name = "pm8550vs_3_s1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_s2: smps2 { + regulator-name = "pm8550vs_3_s2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1036000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_s3: smps3 { + regulator-name = "pm8550vs_3_s3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_s4: smps4 { + regulator-name = "pm8550vs_3_s4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_s5: smps5 { + regulator-name = "pm8550vs_3_s5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_s6: smps6 { + regulator-name = "pm8550vs_3_s6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_l1: ldo1 { + regulator-name = "pm8550vs_3_l1"; + regulator-min-microvolt = <1144000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_l2: ldo2 { + regulator-name = "pm8550vs_3_l2"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + pm8550vs_3_l3: ldo3 { + regulator-name = "pm8550vs_3_l3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + /* TODO: Unknown PMIC @ k, l, PM8010 @ m, n */ +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&i2c_hub_2 { + clock-frequency = <400000>; + status = "okay"; + + pmic@75 { + compatible = "dlg,slg51000"; + reg = <0x75>; + dlg,cs-gpios = <&pm8550vs_g_gpios 4 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&cam_pwr_a_cs>; + pinctrl-names = "default"; + + regulators { + slg51000_a_ldo1: ldo1 { + regulator-name = "slg51000_a_ldo1"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo2: ldo2 { + regulator-name = "slg51000_a_ldo2"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo3: ldo3 { + regulator-name = "slg51000_a_ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo4: ldo4 { + regulator-name = "slg51000_a_ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo5: ldo5 { + regulator-name = "slg51000_a_ldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo6: ldo6 { + regulator-name = "slg51000_a_ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo7: ldo7 { + regulator-name = "slg51000_a_ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + }; + }; +}; + +&i2c_master_hub_0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <1000000>; + status = "okay"; + + /* NXP NFC @ 28 */ +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + /* LX Semi SW82907 touchscreen @ 28 */ +}; + +&i2c10 { + clock-frequency = <1000000>; + status = "okay"; + + /* Cirrus Logic CS40L25A boosted haptics driver @ 40 */ +}; + +&i2c11 { + clock-frequency = <1000000>; + status = "okay"; + + cs35l41_l: speaker-amp@30 { + compatible = "cirrus,cs35l45"; + reg = <0x30>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 183 GPIO_ACTIVE_HIGH>; + cirrus,asp-sdout-hiz-ctrl = <(CS35L45_ASP_TX_HIZ_UNUSED | CS35L45_ASP_TX_HIZ_DISABLED)>; + #sound-dai-cells = <1>; + + cirrus,gpio-ctrl2 { + gpio-ctrl = <0x2>; + }; + }; + + cs35l41_r: speaker-amp@31 { + compatible = "cirrus,cs35l45"; + reg = <0x31>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 183 GPIO_ACTIVE_HIGH>; + cirrus,asp-sdout-hiz-ctrl = <(CS35L45_ASP_TX_HIZ_UNUSED | CS35L45_ASP_TX_HIZ_DISABLED)>; + #sound-dai-cells = <1>; + + cirrus,gpio-ctrl2 { + gpio-ctrl = <0x2>; + }; + }; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&pm8550vs_2_l1>; + vdda-pll-supply = <&pm8550vs_2_l3>; + + status = "okay"; +}; + +&pm8550_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <0>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <1>; + }; +}; + +&pm8550_gpios { + vol_down_n: volume-down-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio12"; + function = "normal"; + power-source = <1>; + bias-pull-down; + output-disable; + input-enable; + }; +}; + +&pm8550b_gpios { + snapshot_n: snapshot-n-state { + pins = "gpio7"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; + + focus_n: focus-n-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm8550vs_g_gpios { + cam_pwr_a_cs: cam-pwr-a-cs-state { + pins = "gpio4"; + function = "normal"; + power-source = <0x01>; + drive-push-pull; + output-low; + qcom,drive-strength = ; + }; +}; + +&pm8550b_eusb2_repeater { + qcom,tune-usb2-disc-thres = /bits/ 8 <0x6>; + qcom,tune-usb2-amplitude = /bits/ 8 <0xf>; + qcom,tune-usb2-preem = /bits/ 8 <0x7>; + vdd18-supply = <&pm8550_l15>; + vdd3-supply = <&pm8550_l5>; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8550/Sony/yodo/adsp.mbn", + "qcom/sm8550/Sony/yodo/adsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8550/Sony/yodo/cdsp.mbn", + "qcom/sm8550/Sony/yodo/cdsp_dtb.mbn"; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&pm8550_l9>; + vqmmc-supply = <&pm8550_l8>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + gpio-reserved-ranges = <32 8>; +}; + +&uart7 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&pm8550vs_2_l1>; + vdda12-supply = <&pm8550vs_2_l3>; + phys = <&pm8550b_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&pm8550vs_2_l3>; + vdda-pll-supply = <&pm8550ve_l3>; + orientation-switch; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + +&xo_board { + clock-frequency = <76800000>; +}; From 8a2a43a978e51bcddfe8a89bb2acebcf24f1d767 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 19 Apr 2024 19:13:56 +0300 Subject: [PATCH 067/110] arm64: dts: qcom: x1e80100: Drop the link-frequencies from mdss_dp3_in The link-frequencies belong in mdss_dp3_out. Drop them from mdss_dp3_in. Fixes: 1940c25eaa63 ("arm64: dts: qcom: x1e80100: Add display nodes") Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240419-x1e80100-dts-fix-mdss-dp3-v2-1-10f4ed7a09b4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index fa04a24173a7..a8dfd8146706 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -4095,8 +4095,6 @@ port@0 { mdss_dp3_in: endpoint { remote-endpoint = <&mdss_intf5_out>; - - link-frequencies = /bits/ 64 <8100000000>; }; }; From 2351d205081cf4e7d960c0dbc5891e5fbda0b1f0 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 19 Apr 2024 19:13:57 +0300 Subject: [PATCH 068/110] arm64: dts: qcom: x1e80100-crd: Add data-lanes and link-frequencies to DP3 The data-lanes are a property of the out remote endpoint, so move them from mdss_dp3 to the mdss_dp3_out. Also add the link-frequencies to mdss_dp3_out and make sure to include all frequencies. Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support") Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240419-x1e80100-dts-fix-mdss-dp3-v2-2-10f4ed7a09b4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index d4198fa204fd..c5c2895b37c7 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -599,8 +599,6 @@ &mdss_dp3 { compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; - data-lanes = <0 1 2 3>; - status = "okay"; aux-bus { @@ -620,6 +618,9 @@ ports { port@1 { reg = <1>; mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&edp_panel_in>; }; }; From 78a4407ca834cc448cb015e714ca230ec6bb4503 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 19 Apr 2024 19:13:58 +0300 Subject: [PATCH 069/110] arm64: dts: qcom: x1e80100-qcp: Add data-lanes and link-frequencies to DP3 The data-lanes are a property of the out remote endpoint, so move them from mdss_dp3 to the mdss_dp3_out. Also add the link-frequencies to mdss_dp3_out and make sure to include all frequencies. Fixes: f9a9c11471da ("arm64: dts: qcom: x1e80100-qcp: Enable more support") Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240419-x1e80100-dts-fix-mdss-dp3-v2-3-10f4ed7a09b4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 35580ac3430d..2061fbe7b75a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -410,8 +410,6 @@ &mdss_dp3 { compatible = "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; - data-lanes = <0 1 2 3>; - status = "okay"; aux-bus { @@ -431,6 +429,9 @@ ports { port@1 { reg = <1>; mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&edp_panel_in>; }; }; From 5927bc586a3f2a81abcf8134fda5f7639abeeefd Mon Sep 17 00:00:00 2001 From: Volodymyr Babchuk Date: Fri, 12 Apr 2024 19:03:26 +0000 Subject: [PATCH 070/110] arm64: dts: qcom: sa8155p-adp: lower min volt for L13C regulator Voltage regulator L13C is used by SD card IO interface. In order to support UHS modes, IO interface voltage needs to be set to 1.8V. This patch extends minimum voltage range of L13C regulator to allow this. Signed-off-by: Volodymyr Babchuk Fixes: 0deb2624e2d0 ("arm64: dts: qcom: sa8155p-adp: Add support for uSD card") Suggested-by: Stephan Gerhold Link: https://lore.kernel.org/r/20240412190310.1647893-2-volodymyr_babchuk@epam.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 5e4287f8c8cd..4f805c47fbfd 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -283,7 +283,7 @@ vreg_l12c_1p808: ldo12 { vreg_l13c_2p96: ldo13 { regulator-name = "vreg_l13c_2p96"; - regulator-min-microvolt = <2504000>; + regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2960000>; regulator-initial-mode = ; }; From 776c5f3c9c9a28f5eea0f8fc2a49e83bb87fe7d2 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Fri, 12 Apr 2024 18:02:37 +0530 Subject: [PATCH 071/110] arm64: dts: qcom: qcm6490-idp: Name the regulators Without explicitly specifying names for the regulators they are named based on the DeviceTree node name. This results in multiple regulators with the same name, making it impossible to reason debug prints and regulator_summary. Signed-off-by: Umang Chheda Link: https://lore.kernel.org/r/20240412123237.2633000-1-quic_uchheda@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index f8f8a43f638d..ac6d741868ca 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -195,129 +195,151 @@ regulators-0 { vdd-l14-l16-supply = <&vreg_s8b_1p272>; vreg_s1b_1p872: smps1 { + regulator-name = "vreg_s1b_1p872"; regulator-min-microvolt = <1840000>; regulator-max-microvolt = <2040000>; }; vreg_s2b_0p876: smps2 { + regulator-name = "vreg_s2b_0p876"; regulator-min-microvolt = <570070>; regulator-max-microvolt = <1050000>; }; vreg_s7b_0p972: smps7 { + regulator-name = "vreg_s7b_0p972"; regulator-min-microvolt = <535000>; regulator-max-microvolt = <1120000>; }; vreg_s8b_1p272: smps8 { + regulator-name = "vreg_s8b_1p272"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1500000>; regulator-initial-mode = ; }; vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; regulator-min-microvolt = <825000>; regulator-max-microvolt = <925000>; regulator-initial-mode = ; }; vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l3b_0p504: ldo3 { + regulator-name = "vreg_l3b_0p504"; regulator-min-microvolt = <312000>; regulator-max-microvolt = <910000>; regulator-initial-mode = ; }; vreg_l4b_0p752: ldo4 { + regulator-name = "vreg_l4b_0p752"; regulator-min-microvolt = <752000>; regulator-max-microvolt = <820000>; regulator-initial-mode = ; }; reg_l5b_0p752: ldo5 { + regulator-name = "reg_l5b_0p752"; regulator-min-microvolt = <552000>; regulator-max-microvolt = <832000>; regulator-initial-mode = ; }; vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; regulator-min-microvolt = <1140000>; regulator-max-microvolt = <1260000>; regulator-initial-mode = ; }; vreg_l7b_2p952: ldo7 { + regulator-name = "vreg_l7b_2p952"; regulator-min-microvolt = <2400000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; regulator-min-microvolt = <870000>; regulator-max-microvolt = <970000>; regulator-initial-mode = ; }; vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = ; }; vreg_l11b_1p504: ldo11 { + regulator-name = "vreg_l11b_1p504"; regulator-min-microvolt = <1504000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l12b_0p751: ldo12 { + regulator-name = "vreg_l12b_0p751"; regulator-min-microvolt = <751000>; regulator-max-microvolt = <824000>; regulator-initial-mode = ; }; vreg_l13b_0p53: ldo13 { + regulator-name = "vreg_l13b_0p53"; regulator-min-microvolt = <530000>; regulator-max-microvolt = <824000>; regulator-initial-mode = ; }; vreg_l14b_1p08: ldo14 { + regulator-name = "vreg_l14b_1p08"; regulator-min-microvolt = <1080000>; regulator-max-microvolt = <1304000>; regulator-initial-mode = ; }; vreg_l15b_0p765: ldo15 { + regulator-name = "vreg_l15b_0p765"; regulator-min-microvolt = <765000>; regulator-max-microvolt = <1020000>; regulator-initial-mode = ; }; vreg_l16b_1p1: ldo16 { + regulator-name = "vreg_l16b_1p1"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1300000>; regulator-initial-mode = ; }; vreg_l17b_1p7: ldo17 { + regulator-name = "vreg_l17b_1p7"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <1900000>; regulator-initial-mode = ; }; vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; @@ -349,109 +371,128 @@ regulators-1 { vdd-bob-supply = <&vph_pwr>; vreg_s1c_2p19: smps1 { + regulator-name = "vreg_s1c_2p19"; regulator-min-microvolt = <2190000>; regulator-max-microvolt = <2210000>; }; vreg_s2c_0p752: smps2 { + regulator-name = "vreg_s2c_0p752"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <800000>; }; vreg_s5c_0p752: smps5 { + regulator-name = "vreg_s5c_0p752"; regulator-min-microvolt = <465000>; regulator-max-microvolt = <1050000>; }; vreg_s7c_0p752: smps7 { + regulator-name = "vreg_s7c_0p752"; regulator-min-microvolt = <465000>; regulator-max-microvolt = <800000>; }; vreg_s9c_1p084: smps9 { + regulator-name = "vreg_s9c_1p084"; regulator-min-microvolt = <1010000>; regulator-max-microvolt = <1170000>; }; vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = ; }; vreg_l2c_1p62: ldo2 { + regulator-name = "vreg_l2c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <1980000>; regulator-initial-mode = ; }; vreg_l3c_2p8: ldo3 { + regulator-name = "vreg_l3c_2p8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3540000>; regulator-initial-mode = ; }; vreg_l4c_1p62: ldo4 { + regulator-name = "vreg_l4c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = ; }; vreg_l5c_1p62: ldo5 { + regulator-name = "vreg_l5c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3300000>; regulator-initial-mode = ; }; vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l8c_1p62: ldo8 { + regulator-name = "vreg_l8c_1p62"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <35440000>; regulator-initial-mode = ; }; vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; regulator-min-microvolt = <720000>; regulator-max-microvolt = <1050000>; regulator-initial-mode = ; }; vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_l12c_1p65: ldo12 { + regulator-name = "vreg_l12c_1p65"; regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2000000>; regulator-initial-mode = ; }; vreg_l13c_2p7: ldo13 { + regulator-name = "vreg_l13c_2p7"; regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3544000>; regulator-initial-mode = ; }; vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3960000>; }; From e788ef2bdac7fdbd61b626f65fdf7528a1c6fd3b Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 11 Apr 2024 09:06:11 +0200 Subject: [PATCH 072/110] arm64: dts: qcom: qcm6490-fairphone-fp5: Add USB-C orientation GPIO Define the USB-C orientation GPIOs so that the USB-C ports orientation is known without having to resort to the altmode notifications. On PCB level this is the signal from PM7250B (pin CC_OUT) which is called USB_PHY_PS. Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20240411-fp5-usb-c-gpio-v1-1-78f11deb940a@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 4ff9fc24e50e..f3432701945f 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -77,6 +77,8 @@ pmic-glink { #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + connector@0 { compatible = "usb-c-connector"; reg = <0>; From 254c101efde79ecf1264ba49be9cb9366542f150 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 9 Apr 2024 17:28:11 +0300 Subject: [PATCH 073/110] dt-bindings: soc: qcom: pmic-glink: allow orientation-gpios The orientation GPIOs are not limited to sm8450/sm8550/x1e8000 platforms. Allow corresponding property to be used on all Qualcom platforms. Fixes: 65682407f8f4 ("dt-bindings: soc: qcom: qcom,pmic-glink: add a gpio used to determine the Type-C port plug orientation") Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-1-658efd993987@linaro.org Signed-off-by: Bjorn Andersson --- .../bindings/soc/qcom/qcom,pmic-glink.yaml | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index 4310bae6c58e..4512390f90f0 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -58,20 +58,6 @@ patternProperties: required: - compatible -allOf: - - if: - not: - properties: - compatible: - contains: - enum: - - qcom,sm8450-pmic-glink - - qcom,sm8550-pmic-glink - - qcom,x1e80100-pmic-glink - then: - properties: - orientation-gpios: false - additionalProperties: false examples: From defac2c098965534e36e257cf80712c54207d99b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 9 Apr 2024 17:28:12 +0300 Subject: [PATCH 074/110] arm64: dts: qcom: sm8350-hdk: add USB-C orientation GPIO Define the USB-C orientation GPIO so that the USB-C port orientation is known without having to resort to the altmode notifications. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-2-658efd993987@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index b43d264ed42b..4c25ab2f5670 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -42,6 +42,7 @@ pmic-glink { compatible = "qcom,sm8350-pmic-glink", "qcom,pmic-glink"; #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; connector@0 { compatible = "usb-c-connector"; From 70b47e7b764ce0c31ed81fdb483738e3d9135e22 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 9 Apr 2024 17:28:13 +0300 Subject: [PATCH 075/110] arm64: dts: qcom: sm8450-hdk: add USB-C orientation GPIO Define the USB-C orientation GPIO so that the USB-C port orientation is known without having to resort to the altmode notifications. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-3-658efd993987@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 0786cff07b89..3be46b56c723 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -95,6 +95,7 @@ pmic-glink { compatible = "qcom,sm8450-pmic-glink", "qcom,pmic-glink"; #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; connector@0 { compatible = "usb-c-connector"; From e34d83d968165841250cc4e780921f4bb33247d9 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 9 Apr 2024 17:28:14 +0300 Subject: [PATCH 076/110] arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: add USB-C orientation GPIOs Define the USB-C orientation GPIOs so that the USB-C ports orientation is known without having to resort to the altmode notifications. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-4-658efd993987@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 15ae94c1602d..2806aa8ec497 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -100,6 +100,8 @@ pmic-glink { #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 166 GPIO_ACTIVE_HIGH>, + <&tlmm 49 GPIO_ACTIVE_HIGH>; connector@0 { compatible = "usb-c-connector"; From d2dbb1047e05d68b4f031fd50717cf3d2016268f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 9 Apr 2024 17:28:15 +0300 Subject: [PATCH 077/110] arm64: dts: qcom: sc8180x-lenovo-flex-5g: add USB-C orientation GPIOs Define the USB-C orientation GPIOs so that the USB-C ports orientation is known without having to resort to the altmode notifications. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-5-658efd993987@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 6f2e1c732ed3..6af99116c715 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -51,6 +51,8 @@ pmic-glink { #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>, + <&tlmm 58 GPIO_ACTIVE_HIGH>; connector@0 { compatible = "usb-c-connector"; From 99a1c9eedf6098826c0f9dcbda2c23e5dad20244 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Wed, 17 Apr 2024 17:39:27 +0530 Subject: [PATCH 078/110] arm64: dts: qcom: qcm6490-idp: Enable various remoteprocs Enable the ADSP, CDSP, MPSS and WPSS that are found on the SoC. Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20240417120928.32344-2-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index ac6d741868ca..47ca2d000341 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -621,6 +621,26 @@ &qupv3_id_0 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/qcm6490/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcm6490/cdsp.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/qcm6490/modem.mbn"; + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/qcm6490/wpss.mbn"; + status = "okay"; +}; + &sdhc_1 { non-removable; no-sd; From ac6d35b9b74c113753bd266e01d6b853618a1e37 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Wed, 17 Apr 2024 17:39:28 +0530 Subject: [PATCH 079/110] arm64: dts: qcom: qcs6490-rb3gen2: Enable various remoteprocs Enable the ADSP, CDSP and WPSS that are found on qcs6490-rb3gen2. Signed-off-by: Komal Bajaj Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240417120928.32344-3-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index c98c41f8f3b1..a085ff5b5fb2 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -17,7 +17,6 @@ #include "pmk8350.dtsi" /delete-node/ &ipa_fw_mem; -/delete-node/ &remoteproc_mpss; /delete-node/ &rmtfs_mem; /delete-node/ &adsp_mem; /delete-node/ &cdsp_mem; @@ -617,6 +616,16 @@ &remoteproc_cdsp { status = "okay"; }; +&remoteproc_mpss { + firmware-name = "qcom/qcs6490/modem.mdt"; + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/qcs6490/wpss.mbn"; + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ From 62f87a3cac4e70fa916914a359d3f045a5ad8b9b Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 29 Mar 2024 08:45:56 +0100 Subject: [PATCH 080/110] arm64: dts: qcom: sm6350: Add DisplayPort controller Add the node for the DisplayPort controller found on the SM6350 SoC. Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240329-sm6350-dp-v2-3-e46dceb32ef5@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 88 ++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 4864bd33e448..ad704f4e147c 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2064,6 +2064,14 @@ dpu_intf1_out: endpoint { remote-endpoint = <&mdss_dsi0_in>; }; }; + + port@2 { + reg = <2>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -2101,6 +2109,86 @@ opp-560000000 { }; }; + mdss_dp: displayport-controller@ae90000 { + compatible = "qcom,sm6350-dp", "qcom,sm8350-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SM6350_CX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp_out: endpoint { + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; From 6754fecd3bdf82cbd6eedefeb0cdb7e86aac2208 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 25 Mar 2024 11:29:24 +0100 Subject: [PATCH 081/110] arm64: dts: qcom: sdx75: add unit address to soc node Soc node has ranges, thus it must have an unit address. This fixes W=1 dtc warning: sdx75.dtsi:399.11-736.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240325102924.26820-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 7dbdf8ca6de6..f58da999a72d 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -411,7 +411,7 @@ smem: qcom,smem { hwlocks = <&tcsr_mutex 3>; }; - soc: soc { + soc: soc@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; From 6aeeb9456943ce166211231f72e8723731ad116b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 25 Mar 2024 09:34:33 +0100 Subject: [PATCH 082/110] arm64: dts: qcom: sm8650: remove useless enablement of mdss_mdp The MDP/DPU device is not disabled by default, so there is not point in enabling it in the board DTS file. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20240325-topic-sm8x50-upstream-leave-mdss-enabled-by-default-v1-1-f1b380132075@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 4450273f9667..d04ceaa73c2b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -641,10 +641,6 @@ &mdss_dsi0_phy { status = "okay"; }; -&mdss_mdp { - status = "okay"; -}; - &pcie_1_phy_aux_clk { clock-frequency = <1000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index b07cac2e5bc8..e0e4587f08c4 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -827,10 +827,6 @@ &mdss_dp0_out { remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; -&mdss_mdp { - status = "okay"; -}; - &pcie_1_phy_aux_clk { clock-frequency = <1000>; }; From 0a8ab4a834507fd5432168ddda7fd3f9eab239f0 Mon Sep 17 00:00:00 2001 From: Jianhua Lu Date: Sat, 23 Mar 2024 18:04:43 +0800 Subject: [PATCH 083/110] arm64: dts: qcom: sm8250-xiaomi-elish: set pm8150b_vbus regulator-min-microamp and regulator-max-microamp Fix the dtb check warnings: sm8250-xiaomi-elish-boe.dtb: usb-vbus-regulator@1100: 'regulator-min-microamp' is a required property sm8250-xiaomi-elish-boe.dtb: usb-vbus-regulator@1100: 'regulator-max-microamp' is a required property Fixes: 69652787279d ("arm64: dts: qcom: sm8250-xiaomi-elish: Add pm8150b type-c node and enable usb otg") Signed-off-by: Jianhua Lu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240323100443.2478-1-lujianhua000@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 2042020eb0dd..41f117474872 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -668,6 +668,8 @@ pm8150b_role_switch_in: endpoint { }; &pm8150b_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <3000000>; status = "okay"; }; From 7c4b3191b3cdb01f69bb5c1323fe67e018e7b9f9 Mon Sep 17 00:00:00 2001 From: Raymond Hackley Date: Thu, 15 Feb 2024 12:26:17 +0000 Subject: [PATCH 084/110] arm64: dts: qcom: msm8916/39-samsung-a2015: Add connector for MUIC Add subnode usb_con: extcon for SM5502 / SM5504 MUIC, which will be used for RT5033 charger. Signed-off-by: Raymond Hackley Link: https://lore.kernel.org/r/20240215122605.3817-1-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 6 ++++++ arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi | 6 ++++++ arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 2937495940ea..4bbbee80b5e4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -128,6 +128,12 @@ muic: extcon@25 { pinctrl-names = "default"; pinctrl-0 = <&muic_int_default>; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi index 3c49dac92d2d..c50f81a68897 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi @@ -23,6 +23,12 @@ muic: extcon@14 { pinctrl-names = "default"; pinctrl-0 = <&muic_int_default>; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts index aa6c39482a2f..0c599e71a464 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts @@ -286,6 +286,12 @@ muic: extcon@25 { pinctrl-0 = <&muic_int_default>; pinctrl-names = "default"; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; }; }; From 11525960fcf40fcb772b62dd5117c59fdc27eb57 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Wed, 6 Mar 2024 20:27:10 +0300 Subject: [PATCH 085/110] arm64: dts: qcom: pm6150l: add Light Pulse Generator device node Add device node defining LPG/PWM block on PM6150L PMIC chip. Signed-off-by: Danila Tikhonov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240306172710.59780-3-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6150l.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index d13a1ab7c20b..0fce45276e5c 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -118,6 +118,16 @@ pm6150l_flash: led-controller@d300 { status = "disabled"; }; + pm6150l_lpg: pwm { + compatible = "qcom,pm6150l-lpg", "qcom,pm8150l-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + pm6150l_wled: leds@d800 { compatible = "qcom,pm6150l-wled"; reg = <0xd800>, <0xd900>; From db33633b05c0b57aef197f072826127f65f59ee9 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 18 Mar 2024 11:09:45 +0100 Subject: [PATCH 086/110] arm64: dts: qcom: sm8650: add GPU nodes Add GPU nodes for the SM8650 platform. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Acked-by: Jun Nie Link: https://lore.kernel.org/r/20240318-topic-sm8650-gpu-v4-1-206eb0d31694@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 181 +++++++++++++++++++++++++++ 1 file changed, 181 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index fc057ea41d56..3d69e13ce87b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2591,6 +2591,143 @@ tcsr: clock-controller@1fc0000 { #reset-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-43051401", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&gpu_micro_code_mem>; + }; + + /* Speedbin needs more work on A740+, keep only lower freqs */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-231000000 { + opp-hz = /bits/ 64 <231000000>; + opp-level = ; + }; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + opp-level = ; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + opp-level = ; + }; + + opp-422000000 { + opp-hz = /bits/ 64 <422000000>; + opp-level = ; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + + opp-578000000 { + opp-hz = /bits/ 64 <578000000>; + opp-level = ; + }; + + opp-629000000 { + opp-hz = /bits/ 64 <629000000>; + opp-level = ; + }; + + opp-680000000 { + opp-hz = /bits/ 64 <680000000>; + opp-level = ; + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-level = ; + }; + + opp-770000000 { + opp-hz = /bits/ 64 <770000000>; + opp-level = ; + }; + + opp-834000000 { + opp-hz = /bits/ 64 <834000000>; + opp-level = ; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x35000>, + <0x0 0x03d50000 0x0 0x10000>, + <0x0 0x0b280000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-260000000 { + opp-hz = /bits/ 64 <260000000>; + opp-level = ; + }; + + opp-625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sm8650-gpucc"; reg = <0 0x03d90000 0 0xa000>; @@ -2604,6 +2741,50 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8650-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + ipa: ipa@3f40000 { compatible = "qcom,sm8650-ipa", "qcom,sm8550-ipa"; From b8cf87ca7827388ed8d817fadec7ea65aef2a172 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 18 Mar 2024 11:09:46 +0100 Subject: [PATCH 087/110] arm64: dts: qcom: sm8650-qrd: enable GPU Add path of the GPU firmware for the SM8650-QRD board Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Reviewed-by: Jun Nie Link: https://lore.kernel.org/r/20240318-topic-sm8650-gpu-v4-2-206eb0d31694@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index e0e4587f08c4..4e94f7fe4d2d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -766,6 +766,14 @@ &ipa { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8650/gen70900_zap.mbn"; + }; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio21"; From dae8cdb0a9e18f0cc7bda75e42d0da750e05ca77 Mon Sep 17 00:00:00 2001 From: Ling Xu Date: Tue, 19 Mar 2024 08:58:16 +0530 Subject: [PATCH 088/110] arm64: dts: qcom: sm8650: Add three missing fastrpc-compute-cb nodes Add three missing cDSP fastrpc compute-cb nodes for the SM8650 SoC. Signed-off-by: Ling Xu Link: https://lore.kernel.org/r/20240319032816.27070-1-quic_lxu5@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 32 ++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 3d69e13ce87b..89d6424a2b05 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5271,6 +5271,38 @@ compute-cb@8 { <&apps_smmu 0x19c8 0x0>; dma-coherent; }; + + /* note: secure cb9 in downstream */ + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + + iommus = <&apps_smmu 0x196c 0x0>, + <&apps_smmu 0x0c0c 0x20>, + <&apps_smmu 0x19cc 0x0>; + dma-coherent; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + + iommus = <&apps_smmu 0x196d 0x0>, + <&apps_smmu 0x0c0d 0x20>, + <&apps_smmu 0x19cd 0x0>; + dma-coherent; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <14>; + + iommus = <&apps_smmu 0x196e 0x0>, + <&apps_smmu 0x0c0e 0x20>, + <&apps_smmu 0x19ce 0x0>; + dma-coherent; + }; }; }; }; From 365e19c466a57ff17093cf6e9f8ad362dd122602 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 19 Mar 2024 16:23:33 +0100 Subject: [PATCH 089/110] arm64: dts: qcom: sc8280xp: Fill in EAS properties Replace the bogus capacity-dmips-mhz values and add the measured dynamic-power-coefficient values. The power numbers were measured by matters much more precise than the laggy and cache-y pmic_glink battery data, though the reported values were only accurate to 10mA. But that shouldn't be an issue, especially for the fat and power-hungry X1Cs and given that *each SoC unit* has somewhat different frequency-voltage maps. X1C cluster: 940 kHz, 596 mV, 434 mW, 663 Cx 1056 kHz, 612 mV, 463 mW, 565 Cx 1171 kHz, 628 mV, 502 mW, 574 Cx 1286 kHz, 644 mV, 534 mW, 540 Cx 1401 kHz, 660 mV, 580 mW, 550 Cx 1516 kHz, 688 mV, 630 mW, 529 Cx 1632 kHz, 712 mV, 690 mW, 533 Cx 1747 kHz, 728 mV, 722 mW, 503 Cx 1862 kHz, 752 mV, 787 mW, 504 Cx 1977 kHz, 776 mV, 855 mW, 503 Cx 2073 kHz, 792 mV, 913 mW, 504 Cx 2169 kHz, 812 mV, 989 mW, 514 Cx 2284 kHz, 856 mV, 1250 mW, 611 Cx 2400 kHz, 900 mV, 1441 mW, 626 Cx 2496 kHz, 932 mV, 1600 mW, 636 Cx 2592 kHz, 964 mV, 1790 mW, 653 Cx 2688 kHz, 1000 mV, 2020 mW, 673 Cx 2803 kHz, 1040 mV, 2292 mW, 687 Cx 2899 kHz, 1076 mV, 2572 mW, 706 Cx 2995 kHz, 1108 mV, 2850 mW, 721 Cx A78C cluster: 403 kHz, 576 mV, 180 mW, 584 Cx 499 kHz, 576 mV, 200 mW, 605 Cx 595 kHz, 576 mV, 220 mW, 612 Cx 691 kHz, 576 mV, 230 mW, 541 Cx 806 kHz, 600 mV, 250 mW, 471 Cx 902 kHz, 620 mV, 270 mW, 444 Cx 1017 kHz, 640 mV, 290 mW, 409 Cx 1113 kHz, 652 mV, 310 mW, 401 Cx 1209 kHz, 668 mV, 320 mW, 363 Cx 1324 kHz, 700 mV, 490 mW, 600 Cx 1440 kHz, 724 mV, 523 mW, 554 Cx 1555 kHz, 800 mV, 660 mW, 558 Cx 1670 kHz, 800 mV, 780 mW, 639 Cx 1785 kHz, 804 mV, 910 mW, 711 Cx 1881 kHz, 824 mV, 941 mW, 663 Cx 1996 kHz, 856 mV, 980 mW, 601 Cx 2112 kHz, 880 mV, 1020 mW, 559 Cx 2227 kHz, 908 mV, 1090 mW, 535 Cx 2342 kHz, 932 mV, 1230 mW, 552 Cx 2438 kHz, 956 mV, 1351 mW, 559 Cx Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240319-topic-8280_eas-v1-1-c605b4ea063d@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 75fa7ac5b60a..4c77f69a24a7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -50,7 +50,8 @@ CPU0: cpu@0 { reg = <0x0 0x0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; @@ -77,7 +78,8 @@ CPU1: cpu@100 { reg = <0x0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_100>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; @@ -99,7 +101,8 @@ CPU2: cpu@200 { reg = <0x0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_200>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; @@ -121,7 +124,8 @@ CPU3: cpu@300 { reg = <0x0 0x300>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_300>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; @@ -144,6 +148,7 @@ CPU4: cpu@400 { clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_400>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; @@ -166,6 +171,7 @@ CPU5: cpu@500 { clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_500>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; @@ -188,6 +194,7 @@ CPU6: cpu@600 { clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_600>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; @@ -210,6 +217,7 @@ CPU7: cpu@700 { clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_700>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; From 17a188d927f772663f8929bd5f2a990004af5917 Mon Sep 17 00:00:00 2001 From: Udipto Goswami Date: Thu, 21 Mar 2024 11:58:34 +0530 Subject: [PATCH 090/110] arm64: dts: qcom: sm8450: Update SNPS Phy parameters for QRD platform Update SNPS Phy tuning parameters for sm8450 QRD platform to fix electrical compliance failures. Signed-off-by: Udipto Goswami Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321062834.21510-1-quic_ugoswami@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index c7d05945aa51..7b62ead68e77 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -467,6 +467,14 @@ &usb_1_hsphy { vdda-pll-supply = <&vreg_l5b_0p88>; vdda18-supply = <&vreg_l1c_1p8>; vdda33-supply = <&vreg_l2b_3p07>; + qcom,squelch-detector-bp = <(-2090)>; + qcom,hs-disconnect-bp = <1743>; + qcom,pre-emphasis-amplitude-bp = <40000>; + qcom,pre-emphasis-duration-bp = <20000>; + qcom,hs-amplitude-bp = <2000>; + qcom,hs-output-impedance-micro-ohms = <2600000>; + qcom,hs-crossover-voltage-microvolt = <(-31000)>; + qcom,hs-rise-fall-time-bp = <(-4100)>; }; &usb_1_qmpphy { From d73ed58d7f2793df161d0afb66afab3d1b862945 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Wed, 20 Mar 2024 12:25:11 +0000 Subject: [PATCH 091/110] arm64: dts: qcom: sdm845-db845c: make pcie0_3p3v_dual always-on This regulator is responsible not just for the PCIe 3.3v rail, but also for 5v VBUS on the left USB port. There is currently no way to correctly model this dependency on the USB controller, as a result when the PCIe driver is not available (for example when in the initramfs) USB is non-functional. Until support is added for modelling this property (likely by referencing it as a supply under a usb-connector node), let's just make it always on. We don't target any power constrained usecases and this regulator is required for USB to function correctly. Fixes: 3f72e2d3e682 ("arm64: dts: qcom: Add Dragonboard 845c") Suggested-by: Bjorn Andersson Signed-off-by: Caleb Connolly Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240320122515.3243711-1-caleb.connolly@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 1f517328199b..9a6d3d0c0ee4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -195,6 +195,12 @@ pcie0_3p3v_dual: vldo-3v3-regulator { gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>; enable-active-high; + /* + * FIXME: this regulator is responsible for VBUS on the left USB + * port. Keep it always on until we can correctly model this + * relationship. + */ + regulator-always-on; pinctrl-names = "default"; pinctrl-0 = <&pcie0_pwren_state>; From 83d2a0a1e2b9fe1032630e0e560dee6ddd89d942 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:21 +0530 Subject: [PATCH 092/110] arm64: dts: qcom: sm8250: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-1-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 39bd8f0eba1e..fe5485256b22 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2203,6 +2203,16 @@ pcie0: pcie@1c00000 { dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2318,6 +2328,16 @@ pcie1: pcie@1c08000 { dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { @@ -2433,6 +2453,16 @@ pcie2: pcie@1c10000 { dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2_phy: phy@1c16000 { From b8347ba382ef334aeff256892229c0d6f818fd53 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:22 +0530 Subject: [PATCH 093/110] arm64: dts: qcom: sdm845: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-2-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2f20be99ee7e..10de2bd46ffc 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2375,6 +2375,16 @@ pcie0: pcie@1c00000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2479,6 +2489,16 @@ pcie1: pcie@1c08000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0a000 { From 8e0a95add7e3f3838d5b494ce645c48759ba4168 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:23 +0530 Subject: [PATCH 094/110] arm64: dts: qcom: sm8150: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-3-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a35c0852b5a1..ff22e4346660 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1901,6 +1901,16 @@ pcie0: pcie@1c00000 { pinctrl-0 = <&pcie0_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2011,6 +2021,16 @@ pcie1: pcie@1c08000 { pinctrl-0 = <&pcie1_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { From 3b743d532eac3cd1ab8fb21e8bf0390715237d8b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:24 +0530 Subject: [PATCH 095/110] arm64: dts: qcom: sm8350: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-4-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a878f5ac5bb5..f7c4700f00c3 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1573,6 +1573,16 @@ pcie0: pcie@1c00000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1670,6 +1680,16 @@ pcie1: pcie@1c08000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { From 4261fd53582df00dc7d3a384a552c35d76ab0ace Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:25 +0530 Subject: [PATCH 096/110] arm64: dts: qcom: sm8450: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Reviewed-by: Neil Armstrong Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-5-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 92b052f7b20e..7f32035aab7b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1850,6 +1850,16 @@ pcie0: pcie@1c00000 { pinctrl-0 = <&pcie0_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1971,6 +1981,16 @@ pcie1: pcie@1c08000 { pinctrl-0 = <&pcie1_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { From cc2ad77882fb9ff54d9f626df73057558dcd8322 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:26 +0530 Subject: [PATCH 097/110] arm64: dts: qcom: sm8550: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Reviewed-by: Neil Armstrong Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-6-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 5adb9b178b05..171fdb213cd9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1774,6 +1774,16 @@ pcie0: pcie@1c00000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1887,6 +1897,16 @@ pcie1: pcie@1c08000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { From cf3e010d7f4c20d3a82fb07feb937fd771cb1b53 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:27 +0530 Subject: [PATCH 098/110] arm64: dts: qcom: sm8650: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Reviewed-by: Neil Armstrong Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-7-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 89d6424a2b05..434ad2f12332 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2294,6 +2294,16 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2422,6 +2432,16 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { From 3c3abb944d3ecce10738c73c94b300974da7b81b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:28 +0530 Subject: [PATCH 099/110] arm64: dts: qcom: sa8775p: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-8-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 231cea1f0fa8..31de73594839 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3677,6 +3677,16 @@ pcie0: pcie@1c00000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c04000 { @@ -3777,6 +3787,16 @@ pcie1: pcie@1c10000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c14000 { From e6bbf39055e347e486cbb0820f2a50a27dbf5a08 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:29 +0530 Subject: [PATCH 100/110] arm64: dts: qcom: sc8280xp: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. While at it, let's remove the bridge properties from board dts as they are now redundant. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-9-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 20 +++----- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 50 +++++++++++++++++++ 2 files changed, 56 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 2806aa8ec497..f325066e24d8 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -733,22 +733,14 @@ &pcie4 { pinctrl-0 = <&pcie4_default>; status = "okay"; +}; - pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; - bus-range = <0x01 0xff>; - - wifi@0 { - compatible = "pci17cb,1103"; - reg = <0x10000 0x0 0x0 0x0 0x0>; - - qcom,ath11k-calibration-variant = "LE_X13S"; - }; + qcom,ath11k-calibration-variant = "LE_X13S"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 4c77f69a24a7..0403811264d8 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1803,6 +1803,16 @@ pcie4: pcie@1c00000 { phy-names = "pciephy"; status = "disabled"; + + pcie4_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie4_phy: phy@1c06000 { @@ -1904,6 +1914,16 @@ pcie3b: pcie@1c08000 { phy-names = "pciephy"; status = "disabled"; + + pcie3b_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3b_phy: phy@1c0e000 { @@ -2005,6 +2025,16 @@ pcie3a: pcie@1c10000 { phy-names = "pciephy"; status = "disabled"; + + pcie3a_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3a_phy: phy@1c14000 { @@ -2109,6 +2139,16 @@ pcie2b: pcie@1c18000 { phy-names = "pciephy"; status = "disabled"; + + pcie2b_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2b_phy: phy@1c1e000 { @@ -2210,6 +2250,16 @@ pcie2a: pcie@1c20000 { phy-names = "pciephy"; status = "disabled"; + + pcie2a_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2a_phy: phy@1c24000 { From b328bf2595db3bdba87df52ca1a9db431ee99c34 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:30 +0530 Subject: [PATCH 101/110] arm64: dts: qcom: msm8998: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-10-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 4dfe2d09ac28..d795b2bbe133 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -972,6 +972,16 @@ pcie0: pcie@1c00000 { power-domains = <&gcc PCIE_0_GDSC>; iommu-map = <0x100 &anoc1_smmu 0x1480 1>; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie_phy: phy@1c06000 { From df307c906c48d1c8c6ffb9022907bfb6cb041da6 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:31 +0530 Subject: [PATCH 102/110] arm64: dts: qcom: sc7280: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-11-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index bd9b1898d7a7..cea294a4ecfb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2273,6 +2273,16 @@ pcie1: pcie@1c08000 { <0x100 &apps_smmu 0x1c81 0x1>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { From ed2f87cf51b4ffab1585553b798773c9131efa6e Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:32 +0530 Subject: [PATCH 103/110] arm64: dts: qcom: qcs404: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-12-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a05d0234f7fc..ac451f378056 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1516,6 +1516,16 @@ pcie: pcie@10000000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; From a92af45c40f06b651f0773bf7ffb3d77c7a467f1 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:33 +0530 Subject: [PATCH 104/110] arm64: dts: qcom: sc8180x: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-13-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 40 +++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 019104bd70fb..6d5878f3b26d 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1777,6 +1777,16 @@ pcie0: pcie@1c00000 { dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1888,6 +1898,16 @@ pcie3: pcie@1c08000 { dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3_phy: phy@1c0c000 { @@ -2000,6 +2020,16 @@ pcie1: pcie@1c10000 { dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c16000 { @@ -2112,6 +2142,16 @@ pcie2: pcie@1c18000 { dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2_phy: phy@1c1c000 { From 71756c44f178d91bf021b51e72e111f96c715d14 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:34 +0530 Subject: [PATCH 105/110] arm64: dts: qcom: msm8996: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-14-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 1601e46549e7..8d2cb6f41095 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1929,6 +1929,16 @@ pcie0: pcie@600000 { "cfg", "bus_master", "bus_slave"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1: pcie@608000 { @@ -1982,6 +1992,16 @@ pcie1: pcie@608000 { "cfg", "bus_master", "bus_slave"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2: pcie@610000 { @@ -2032,6 +2052,16 @@ pcie2: pcie@610000 { "cfg", "bus_master", "bus_slave"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; From ed3893f6f9b800ca774f63810c5f8838bc7cee78 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:35 +0530 Subject: [PATCH 106/110] arm64: dts: qcom: ipq8074: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-15-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index bed405559866..5d42de829e75 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -883,6 +883,16 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ "ahb", "axi_m_sticky"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0: pcie@20000000 { @@ -948,6 +958,16 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ "axi_m_sticky", "axi_s_sticky"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; From 52358c64937e982d3cdcf64be58f08f30d8e518c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:36 +0530 Subject: [PATCH 107/110] arm64: dts: qcom: ipq6018: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-16-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 4e29adea570a..17ab6c475958 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -907,6 +907,16 @@ pcie0: pcie@20000000 { "axi_s_sticky"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; From 57ce4b27a12c827a24aaa18aa444bcb8733cb053 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 6 Mar 2024 10:16:47 +0200 Subject: [PATCH 108/110] arm64: dts: qcom: qrb2210-rb1: add firmware-name qualifier to WiFi node Add firmware-name property to the WiFi device tree node to specify board-specific lookup directory. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240306-wcn3990-firmware-path-v2-3-f89e98e71a57@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index fca341300521..bb5191422660 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -602,6 +602,7 @@ &wifi { vdd-1.3-rfa-supply = <&pm4125_l10>; vdd-3.3-ch0-supply = <&pm4125_l22>; qcom,ath10k-calibration-variant = "Thundercomm_RB1"; + firmware-name = "qcm2290"; status = "okay"; }; From 673b174b5b2ca2fb99fe52bf7bad3cc348432170 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 6 Mar 2024 10:16:48 +0200 Subject: [PATCH 109/110] arm64: dts: qcom: qrb4210-rb1: add firmware-name qualifier to WiFi node Add firmware-name property to the WiFi device tree node to specify board-specific lookup directory. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20240306-wcn3990-firmware-path-v2-4-f89e98e71a57@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 696d6d43c56b..2c39bb1b97db 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -678,6 +678,7 @@ &wifi { vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l23a_3p3>; qcom,ath10k-calibration-variant = "Thundercomm_RB2"; + firmware-name = "qrb4210"; status = "okay"; }; From 873d845a357a4d89700cb1bb5b3da68890756f50 Mon Sep 17 00:00:00 2001 From: Rong Zhang Date: Tue, 13 Feb 2024 18:58:38 +0800 Subject: [PATCH 110/110] dt-bindings: arm: qcom: Add Samsung Galaxy S5 China (kltechn) Document Samsung Galaxy S5 China (kltechn) as a klte variant based on msm8974pro. Also including "samsung,klte" in the compatible chain as kltechn works fine with the klte DTB except for LEDs and WiFi missing. Signed-off-by: Rong Zhang Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240213110137.122737-4-i@rong.moe Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index bdc4a8d5388c..6279143d0619 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -188,6 +188,13 @@ properties: - const: qcom,msm8974pro - const: qcom,msm8974 + - items: + - enum: + - samsung,kltechn + - const: samsung,klte + - const: qcom,msm8974pro + - const: qcom,msm8974 + - items: - enum: - acer,a1-724