From 0fc2b7af8cd5918c0101dfb178b5a3a4b021a50b Mon Sep 17 00:00:00 2001 From: Alexander Bersenev Date: Mon, 9 Jun 2014 00:08:11 +0600 Subject: [PATCH 01/22] ARM: sunxi: Add pins for IR controller on A20 to dtsi This patch adds pins for two IR controllers on A20 Signed-off-by: Alexander Bersenev Signed-off-by: Alexsey Shestacov Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 01e94664232a..656d7d36a162 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -738,6 +738,20 @@ mmc3_pins_a: mmc3@0 { allwinner,drive = <2>; allwinner,pull = <0>; }; + + ir0_pins_a: ir0@0 { + allwinner,pins = "PB3","PB4"; + allwinner,function = "ir0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + ir1_pins_a: ir1@0 { + allwinner,pins = "PB22","PB23"; + allwinner,function = "ir1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { From 0256452ecf89139d2a33b03c8470c8b47d322da2 Mon Sep 17 00:00:00 2001 From: Alexander Bersenev Date: Mon, 9 Jun 2014 00:08:13 +0600 Subject: [PATCH 02/22] ARM: sunxi: Enable IR controller on cubieboard 2 and cubietruck in dts This patch enables two IR devices in dts: - One IR device physically found on Cubieboard 2 - One IR device physically found on Cubietruck Signed-off-by: Alexander Bersenev Signed-off-by: Alexsey Shestacov Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 6 ++++++ arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index a5ad945197e8..a70f0b4aa4ed 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -66,6 +66,12 @@ led_pins_cubieboard2: led_pins@0 { }; }; + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index b87fea901489..96639d59e22c 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -100,6 +100,12 @@ pwm: pwm@01c20e00 { status = "okay"; }; + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; From c1a0ee3d5322d488c539e20d40db88b181628670 Mon Sep 17 00:00:00 2001 From: Alexander Bersenev Date: Sat, 21 Jun 2014 17:04:05 +0600 Subject: [PATCH 03/22] ARM: sunxi: Add IR controllers on A20 to dtsi This patch adds records for two IR controllers on A20 Signed-off-by: Alexander Bersenev Signed-off-by: Alexsey Shestacov Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 656d7d36a162..17823759bdc9 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -785,6 +785,24 @@ pwm: pwm@01c20e00 { status = "disabled"; }; + ir0: ir@01c21800 { + compatible = "allwinner,sun7i-a20-ir"; + clocks = <&apb0_gates 6>, <&ir0_clk>; + clock-names = "apb", "ir"; + interrupts = <0 5 4>; + reg = <0x01c21800 0x40>; + status = "disabled"; + }; + + ir1: ir@01c21c00 { + compatible = "allwinner,sun7i-a20-ir"; + clocks = <&apb0_gates 7>, <&ir1_clk>; + clock-names = "apb", "ir"; + interrupts = <0 6 4>; + reg = <0x01c21c00 0x40>; + status = "disabled"; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun7i-a20-sid"; reg = <0x01c23800 0x200>; From fd6c10fb1012c773820c5a308a7ab01879628c69 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 20 Jun 2014 22:52:52 +0800 Subject: [PATCH 04/22] ARM: sunxi: Add Allwinner A23 dtsi The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores and a Mali-400MP2 GPU. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23.dtsi | 160 +++++++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-a23.dtsi diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi new file mode 100644 index 000000000000..ac5f69afb595 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -0,0 +1,160 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &r_uart; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + }; + + memory { + reg = <0x40000000 0x40000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + timer@01c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = <0 18 4>, + <0 19 4>; + clocks = <&osc24M>; + }; + + wdt0: watchdog@01c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = <0 25 4>; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <0 0 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <0 1 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <0 2 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <0 3 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart4: serial@01c29000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c29000 0x400>; + interrupts = <0 4 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <1 9 0xf04>; + }; + + r_uart: serial@01f02800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01f02800 0x400>; + interrupts = <0 38 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + }; +}; From 4c3d4a361b7e6a24303e65f443285afd91371694 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 20 Jun 2014 22:52:53 +0800 Subject: [PATCH 05/22] ARM: sun8i: dt: Add Ippo-q8h v5 support The Ippo-q8h is a tablet circuit board commonly found in cheap Android tablets with A23 SoCs. There are at least 2 versions of the board, with different peripherals, such as WiFi chips. Common features among these tablets include 512 MB DRAM, NAND, MMC, LCD, capacitive touchscreen, accelerometer, 1 or 2 camera sensors, USB OTG, microphone and speaker. v5 of these board designs has a ESP8089 WiFi chip (not supported) connected to mmc1. This patch adds very basic support. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 2 ++ arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 30 +++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5986ff63b901..774a14b91151 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -380,6 +380,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-cubietruck.dtb \ sun7i-a20-i12-tvbox.dtb \ sun7i-a20-olinuxino-micro.dtb +dtb-$(CONFIG_MACH_SUN8I) += \ + sun8i-a23-ippo-q8h-v5.dtb dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-iris-512.dtb \ tegra20-medcom-wide.dtb \ diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts new file mode 100644 index 000000000000..34002e3eba9d --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts @@ -0,0 +1,30 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun8i-a23.dtsi" + +/ { + model = "Ippo Q8H Dual Core Tablet (v5)"; + compatible = "ippo,q8h-v5", "allwinner,sun8i-a23"; + + chosen { + bootargs = "earlyprintk console=ttyS0,115200"; + }; + + soc@01c00000 { + r_uart: serial@01f02800 { + status = "okay"; + }; + }; +}; From 7d4ff96dd390cbcf6053398bd33b194f87ef60ba Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 30 Jun 2014 23:57:51 +0200 Subject: [PATCH 06/22] ARM: dts: sunxi: Add #interrupt-cells to pinctrl nodes The pinctrl device is also an interrupt controller for external interrupts. Add the missing #interrupt-cells property. Also remove the unused #address-cells property. Signed-off-by: Chen-Yu Tsai [hdegoede@redhat.com: make the same change for sun4i, sun5i and sun6i] Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 2 +- arch/arm/boot/dts/sun5i-a10s.dtsi | 2 +- arch/arm/boot/dts/sun5i-a13.dtsi | 2 +- arch/arm/boot/dts/sun6i-a31.dtsi | 4 ++-- arch/arm/boot/dts/sun7i-a20.dtsi | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index d96e179490ce..37a6fb8013cc 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -509,7 +509,7 @@ pio: pinctrl@01c20800 { clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #address-cells = <1>; + #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <3>; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index b64f705d9008..24b0ad3a7c07 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -422,7 +422,7 @@ pio: pinctrl@01c20800 { clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #address-cells = <1>; + #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <3>; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index 3b2a94c40f6e..bf86e65dd167 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -395,7 +395,7 @@ pio: pinctrl@01c20800 { clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #address-cells = <1>; + #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <3>; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index a9dfa12eb735..baf8eff57610 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -429,7 +429,7 @@ pio: pinctrl@01c20800 { clocks = <&apb1_gates 5>; gpio-controller; interrupt-controller; - #address-cells = <1>; + #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <3>; @@ -756,7 +756,7 @@ r_pio: pinctrl@01f02c00 { resets = <&apb0_rst 0>; gpio-controller; interrupt-controller; - #address-cells = <1>; + #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <3>; }; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 17823759bdc9..edf16b512f43 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -586,7 +586,7 @@ pio: pinctrl@01c20800 { clocks = <&apb0_gates 5>; gpio-controller; interrupt-controller; - #address-cells = <1>; + #interrupt-cells = <2>; #size-cells = <0>; #gpio-cells = <3>; From e288f1bac490791e7564474b89b7c48ee537b6a7 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 30 Jun 2014 23:57:52 +0200 Subject: [PATCH 07/22] ARM: dts: sun4i: Add AXP209 support to various boards At a node for the axp209, and where necessary the i2c controller to the dts for various boards. Note the axp209 regulators are omitted as we don't have any use for them yet, and on some boards were not sure how exactly they are wired up. Adding support for just the axp209 without the regulators is still useful, as it will give us power-button and poweroff support. Signed-off-by: Carlo Caione [hdegoede@redhat.com: Drop the regulator bits for now] Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-a1000.dts | 9 ++++++++ arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 9 ++++++++ arch/arm/boot/dts/sun4i-a10-hackberry.dts | 15 +++++++++++++ arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 21 +++++++++++++------ arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 15 +++++++++++++ .../arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 15 +++++++++++++ arch/arm/boot/dts/sun4i-a10-pcduino.dts | 9 ++++++++ 7 files changed, 87 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index 0b97c071dd56..55d951070bff 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -98,6 +98,15 @@ i2c0: i2c@01c2ac00 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index c200eacc66e8..539b693f69dd 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -90,6 +90,15 @@ i2c0: i2c@01c2ac00 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; }; i2c1: i2c@01c2b000 { diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index 547fadcb984b..21df4e3f7ba3 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -92,6 +92,21 @@ uart0: serial@01c28000 { pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; }; reg_emac_3v3: emac-3v3 { diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index f13723e18b86..6b0c37812ade 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts @@ -40,12 +40,6 @@ uart0: serial@01c28000 { status = "okay"; }; - i2c0: i2c@01c2ac00 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - }; - usbphy: phy@01c13400 { usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; @@ -67,6 +61,21 @@ ehci1: usb@01c1c000 { ohci1: usb@01c1c400 { status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; }; reg_usb1_vbus: usb1-vbus { diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index c01cea50cf0c..387770db995f 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -57,6 +57,21 @@ uart0: serial@01c28000 { pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; }; reg_usb1_vbus: usb1-vbus { diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index d46a7dbecef5..d046d568f5a1 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -91,6 +91,21 @@ uart0: serial@01c28000 { pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; }; leds { diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index fb03bccb78d2..6675bcd7860e 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -76,6 +76,15 @@ i2c0: i2c@01c2ac00 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; From ec0c933d972ba69f06251f7d215723f61535fc16 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 30 Jun 2014 23:57:53 +0200 Subject: [PATCH 08/22] ARM: dts: sun7i: Add AXP209 support to various boards At a node for the axp209, and where necessary the i2c controller to the dts for various boards. Note the axp209 regulators are omitted as we don't have any use for them yet, and on some boards were not sure how exactly they are wired up. Adding support for just the axp209 without the regulators is still useful, as it will give us power-button and poweroff support. Signed-off-by: Carlo Caione [hdegoede@redhat.com: Drop the regulator bits for now] Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 10 ++++++++++ arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 10 ++++++++++ arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 16 ++++++++++++++++ arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 10 ++++++++++ 4 files changed, 46 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts index a70f0b4aa4ed..53680983461a 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts @@ -82,6 +82,16 @@ i2c0: i2c@01c2ac00 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + }; }; i2c1: i2c@01c2b000 { diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 96639d59e22c..a6c1a3c717bc 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -116,6 +116,16 @@ i2c0: i2c@01c2ac00 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + }; }; i2c1: i2c@01c2b000 { diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index b77308e90199..cba1567d5151 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -100,6 +100,22 @@ uart0: serial@01c28000 { status = "okay"; }; + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + gmac: ethernet@01c50000 { pinctrl-names = "default"; pinctrl-0 = <&gmac_pins_mii_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts index b759630bc9a9..9d669cdf031d 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts @@ -122,6 +122,16 @@ i2c0: i2c@01c2ac00 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + }; }; i2c1: i2c@01c2b000 { From 1715a389949a4a3f03192268dfb3ac5710f2dd3c Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 30 Jun 2014 23:57:54 +0200 Subject: [PATCH 09/22] ARM: dts: sun7i: Rename sun7i-a20-ir to sun4i-a10-ir The sun7i block is the same as the one in the sun4i, rename the compatible to reflect this. Signed-off-by: Hans de Goede -- I've already included the matching change to sunxi-cir.c in my pull-req to Mauro. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index edf16b512f43..4011628c7381 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -786,7 +786,7 @@ pwm: pwm@01c20e00 { }; ir0: ir@01c21800 { - compatible = "allwinner,sun7i-a20-ir"; + compatible = "allwinner,sun4i-a10-ir"; clocks = <&apb0_gates 6>, <&ir0_clk>; clock-names = "apb", "ir"; interrupts = <0 5 4>; @@ -795,7 +795,7 @@ ir0: ir@01c21800 { }; ir1: ir@01c21c00 { - compatible = "allwinner,sun7i-a20-ir"; + compatible = "allwinner,sun4i-a10-ir"; clocks = <&apb0_gates 7>, <&ir1_clk>; clock-names = "apb", "ir"; interrupts = <0 6 4>; From abe36869a5dd5ac03a54eee3ad117bbe78efe792 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 30 Jun 2014 23:57:55 +0200 Subject: [PATCH 10/22] ARM: dts: sun7i: Add ir receiver support to a20-i12-tvbox Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index cba1567d5151..6a67712d417a 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -94,6 +94,12 @@ led_pins_i12_tvbox: led_pins@0 { }; }; + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; From 04089927981f295b42cd695485383b2d11283d59 Mon Sep 17 00:00:00 2001 From: Zoltan HERPAI Date: Mon, 30 Jun 2014 23:57:56 +0200 Subject: [PATCH 11/22] ARM: dts: sun7i: Add board support for LinkSprite pcDuino V3 The LinkSprite pcDuino V3 is an A20 based development board featuring arduino compatible io headers, 1G RAM, 4G nand, sata, rtl8188cus usb wifi and 100 Mbit ethernet using an ip101a phy: http://www.pcduino.com/pcduino-v3/ Signed-off-by: Zoltan HERPAI [hdegoede@redhat.com: Various cleanups, correct led pins] [hdegoede@redhat.com: Add axp209, ir and gpio-keys nodes] Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 173 +++++++++++++++++++++++ 2 files changed, 175 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun7i-a20-pcduino3.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 774a14b91151..796fea874183 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -379,7 +379,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-cubieboard2.dtb \ sun7i-a20-cubietruck.dtb \ sun7i-a20-i12-tvbox.dtb \ - sun7i-a20-olinuxino-micro.dtb + sun7i-a20-olinuxino-micro.dtb \ + sun7i-a20-pcduino3.dtb dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a23-ippo-q8h-v5.dtb dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts new file mode 100644 index 000000000000..046dfc0d45d8 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -0,0 +1,173 @@ +/* + * Copyright 2014 Zoltan HERPAI + * Zoltan HERPAI + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" +#include +#include + +/ { + model = "LinkSprite pcDuino3"; + compatible = "linksprite,pcduino3", "allwinner,sun7i-a20"; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + + pinctrl@01c20800 { + ahci_pwr_pin_a: ahci_pwr_pin@0 { + allwinner,pins = "PH2"; + }; + + led_pins_pcduino3: led_pins@0 { + allwinner,pins = "PH15", "PH16"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + key_pins_pcduino3: key_pins@0 { + allwinner,pins = "PH17", "PH18", "PH19"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + gmac: ethernet@01c50000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_pcduino3>; + + tx { + label = "pcduino3:green:tx"; + gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; + }; + + rx { + label = "pcduino3:green:rx"; + gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins_pcduino3>; + #address-cells = <1>; + #size-cells = <0>; + button@0 { + label = "Key Back"; + linux,code = ; + gpios = <&pio 7 17 GPIO_ACTIVE_LOW>; + }; + button@1 { + label = "Key Home"; + linux,code = ; + gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; + }; + button@2 { + label = "Key Menu"; + linux,code = ; + gpios = <&pio 7 19 GPIO_ACTIVE_LOW>; + }; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; + + reg_ahci_5v: ahci-5v { + gpio = <&pio 7 2 0>; + status = "okay"; + }; +}; From 97cb8f1ed91fd1d4993cd18168b600a8294a7c6f Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 30 Jun 2014 23:57:57 +0200 Subject: [PATCH 12/22] ARM: dts: sun4i: Add new ba10-tvbox board The ba10 tvbox is an A10 based android tvbox, with 512M RAM, 8G nand flash, rtl8188ctv usb wifi 1 USB-A receptacle hooked up to an EHCI/OHCI controller, 1 USB-A receptacle hooked up to the OTG and 100Mbit ethernet using a rtl8201 phy. The PCB is labelled ba10 hence I've named the board ba10-tvbox. It is used in noname allwinner A10 tv-boxes. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts | 110 +++++++++++++++++++++ 2 files changed, 111 insertions(+) create mode 100644 arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 796fea874183..c3ee9fba892b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -360,6 +360,7 @@ dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \ stih416-b2020-revE.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ + sun4i-a10-ba10-tvbox.dtb \ sun4i-a10-cubieboard.dtb \ sun4i-a10-mini-xplus.dtb \ sun4i-a10-hackberry.dtb \ diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts new file mode 100644 index 000000000000..1763cc7ec023 --- /dev/null +++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts @@ -0,0 +1,110 @@ +/* + * Copyright 2014 Hans de Goede + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun4i-a10.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "BA10 tvbox"; + compatible = "allwinner,ba10-tvbox", "allwinner,sun4i-a10"; + + soc@01c00000 { + emac: ethernet@01c0b000 { + pinctrl-names = "default"; + pinctrl-0 = <&emac_pins_a>; + phy = <&phy1>; + status = "okay"; + }; + + mdio@01c0b080 { + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + + pinctrl@01c20800 { + usb2_vbus_pin_a: usb2_vbus_pin@0 { + allwinner,pins = "PH12"; + }; + }; + + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + gpio = <&pio 7 12 0>; + status = "okay"; + }; +}; From a4e1099a46a3ec76ae3a2a219a5931fe7fb2674d Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 30 Jun 2014 23:57:58 +0200 Subject: [PATCH 13/22] ARM: dts: sun4i: Add ir controller nodes and pinmux Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 37a6fb8013cc..459cb6377764 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -593,6 +593,20 @@ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { allwinner,drive = <0>; allwinner,pull = <1>; }; + + ir0_pins_a: ir0@0 { + allwinner,pins = "PB3","PB4"; + allwinner,function = "ir0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + ir1_pins_a: ir1@0 { + allwinner,pins = "PB22","PB23"; + allwinner,function = "ir1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; timer@01c20c00 { @@ -621,6 +635,24 @@ pwm: pwm@01c20e00 { status = "disabled"; }; + ir0: ir@01c21800 { + compatible = "allwinner,sun4i-a10-ir"; + clocks = <&apb0_gates 6>, <&ir0_clk>; + clock-names = "apb", "ir"; + interrupts = <5>; + reg = <0x01c21800 0x40>; + status = "disabled"; + }; + + ir1: ir@01c21c00 { + compatible = "allwinner,sun4i-a10-ir"; + clocks = <&apb0_gates 7>, <&ir1_clk>; + clock-names = "apb", "ir"; + interrupts = <6>; + reg = <0x01c21c00 0x40>; + status = "disabled"; + }; + sid: eeprom@01c23800 { compatible = "allwinner,sun4i-a10-sid"; reg = <0x01c23800 0x10>; From 4a5c586127253bdfa4d8b5bc72be1a9ad6ba5585 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 30 Jun 2014 23:57:59 +0200 Subject: [PATCH 14/22] ARM: dts: sun4i: Add ir node to various boards Tested on a cubieboard and the mini-x. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-a1000.dts | 6 ++++++ arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 6 ++++++ arch/arm/boot/dts/sun4i-a10-hackberry.dts | 6 ++++++ arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 13 +++++++++++++ 4 files changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index 55d951070bff..9e99ade35e37 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -88,6 +88,12 @@ led_pins_a1000: led_pins@0 { }; }; + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 539b693f69dd..3ce56bfbc0b5 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -80,6 +80,12 @@ led_pins_cubieboard: led_pins@0 { }; }; + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index 21df4e3f7ba3..891ea446abae 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -87,6 +87,12 @@ usb2_vbus_pin_hackberry: usb2_vbus_pin@0 { }; }; + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index 387770db995f..b9ecce60f2e7 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -52,6 +52,19 @@ ohci1: usb@01c1c400 { status = "okay"; }; + pinctrl@01c20800 { + ir0_pins_a: ir0@0 { + /* The ir receiver is not always populated */ + allwinner,pull = <1>; + }; + }; + + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + uart0: serial@01c28000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; From 8e9842406c1889782613f31a81a579ba14ef9e0f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 26 Jun 2014 23:55:44 +0800 Subject: [PATCH 15/22] ARM: sun8i: Add basic clock nodes to the DTSI Now that we have support for sun8i specific clocks in the driver, add the corresponding clock nodes to the DTSI. Also update the existing peripherals with the correct clocks. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23.dtsi | 125 +++++++++++++++++++++++++++++-- 1 file changed, 120 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index ac5f69afb595..79c40834bc0a 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -64,6 +64,121 @@ osc32k: osc32k_clk { clock-frequency = <32768>; clock-output-names = "osc32k"; }; + + pll1: clk@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll1"; + }; + + /* dummy clock until actually implemented */ + pll6: pll6_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <600000000>; + clock-output-names = "pll6"; + }; + + cpu: cpu_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-cpu-clk"; + reg = <0x01c20050 0x4>; + + /* + * PLL1 is listed twice here. + * While it looks suspicious, it's actually documented + * that way both in the datasheet and in the code from + * Allwinner. + */ + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; + clock-output-names = "cpu"; + }; + + axi: axi_clk@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun8i-a23-axi-clk"; + reg = <0x01c20050 0x4>; + clocks = <&cpu>; + clock-output-names = "axi"; + }; + + ahb1_mux: ahb1_mux_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; + clock-output-names = "ahb1_mux"; + }; + + ahb1: ahb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-ahb-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb1_mux>; + clock-output-names = "ahb1"; + }; + + apb1: apb1_clk@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb0-clk"; + reg = <0x01c20054 0x4>; + clocks = <&ahb1>; + clock-output-names = "apb1"; + }; + + ahb1_gates: clk@01c20060 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; + reg = <0x01c20060 0x8>; + clocks = <&ahb1>; + clock-output-names = "ahb1_mipidsi", "ahb1_dma", + "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2", + "ahb1_nand", "ahb1_sdram", + "ahb1_hstimer", "ahb1_spi0", + "ahb1_spi1", "ahb1_otg", "ahb1_ehci", + "ahb1_ohci", "ahb1_ve", "ahb1_lcd", + "ahb1_csi", "ahb1_be", "ahb1_fe", + "ahb1_gpu", "ahb1_spinlock", + "ahb1_drc"; + }; + + apb1_gates: clk@01c20068 { + #clock-cells = <1>; + compatible = "allwinner,sun8i-a23-apb1-gates-clk"; + reg = <0x01c20068 0x4>; + clocks = <&apb1>; + clock-output-names = "apb1_codec", "apb1_pio", + "apb1_daudio0", "apb1_daudio1"; + }; + + apb2_mux: apb2_mux_clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-apb1-mux-clk"; + reg = <0x01c20058 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; + clock-output-names = "apb2_mux"; + }; + + apb2: apb2_clk@01c20058 { + #clock-cells = <0>; + compatible = "allwinner,sun6i-a31-apb2-div-clk"; + reg = <0x01c20058 0x4>; + clocks = <&apb2_mux>; + clock-output-names = "apb2"; + }; + + apb2_gates: clk@01c2006c { + #clock-cells = <1>; + compatible = "allwinner,sun8i-a23-apb2-gates-clk"; + reg = <0x01c2006c 0x4>; + clocks = <&apb2>; + clock-output-names = "apb2_i2c0", "apb2_i2c1", + "apb2_i2c2", "apb2_uart0", + "apb2_uart1", "apb2_uart2", + "apb2_uart3", "apb2_uart4"; + }; }; soc@01c00000 { @@ -92,7 +207,7 @@ uart0: serial@01c28000 { interrupts = <0 0 4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb2_gates 16>; status = "disabled"; }; @@ -102,7 +217,7 @@ uart1: serial@01c28400 { interrupts = <0 1 4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb2_gates 17>; status = "disabled"; }; @@ -112,7 +227,7 @@ uart2: serial@01c28800 { interrupts = <0 2 4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb2_gates 18>; status = "disabled"; }; @@ -122,7 +237,7 @@ uart3: serial@01c28c00 { interrupts = <0 3 4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb2_gates 19>; status = "disabled"; }; @@ -132,7 +247,7 @@ uart4: serial@01c29000 { interrupts = <0 4 4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb2_gates 20>; status = "disabled"; }; From c571111ac1d6e99a4ad49ae105325704e3381ccc Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 3 Jul 2014 22:55:49 +0800 Subject: [PATCH 16/22] ARM: sun8i: Add reset controller nodes to the DTSI The A23 has the same MMIO reset controllers matching the clocks gates, just like in the A31. This patch adds the reset controller nodes and the reset control phandles for the peripherals needing them to the DTSI. Unlike the sun6i DTSI, this patch uses sun6i-a31-clock-reset for ahb1_rst. sun6i-a31-ahb-reset is for early init, and requires some additions to the machine code. It is used to support the hstimer. However the hstimer on sun8i only has 1 timer, which is somewhat useless. Support for it will probably not be added. Hence the decision to use sun6i-a31-clock-reset here to avoid the changes to sun8i machine code. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 79c40834bc0a..886776d09c06 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -187,6 +187,24 @@ soc@01c00000 { #size-cells = <1>; ranges; + ahb1_rst: reset@01c202c0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202c0 0xc>; + }; + + apb1_rst: reset@01c202d0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d0 0x4>; + }; + + apb2_rst: reset@01c202d8 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x01c202d8 0x4>; + }; + timer@01c20c00 { compatible = "allwinner,sun4i-a10-timer"; reg = <0x01c20c00 0xa0>; @@ -208,6 +226,7 @@ uart0: serial@01c28000 { reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 16>; + resets = <&apb2_rst 16>; status = "disabled"; }; @@ -218,6 +237,7 @@ uart1: serial@01c28400 { reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 17>; + resets = <&apb2_rst 17>; status = "disabled"; }; @@ -228,6 +248,7 @@ uart2: serial@01c28800 { reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 18>; + resets = <&apb2_rst 18>; status = "disabled"; }; @@ -238,6 +259,7 @@ uart3: serial@01c28c00 { reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 19>; + resets = <&apb2_rst 19>; status = "disabled"; }; @@ -248,6 +270,7 @@ uart4: serial@01c29000 { reg-shift = <2>; reg-io-width = <4>; clocks = <&apb2_gates 20>; + resets = <&apb2_rst 20>; status = "disabled"; }; From df02dd828c4ef2311c7c271f2c95384fc555961b Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 9 Jul 2014 15:54:39 +0800 Subject: [PATCH 17/22] ARM: sun8i: Add PRCM clock and reset controller nodes to the DTSI With sun8i PRCM support available, we can add the PRCM clock and reset controller nodes to the DTSI. Also update R_UART's clock phandle and add it's reset control phandle. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23.dtsi | 47 +++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 886776d09c06..54ac0787216a 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -285,13 +285,58 @@ gic: interrupt-controller@01c81000 { interrupts = <1 9 0xf04>; }; + prcm@01f01400 { + compatible = "allwinner,sun8i-a23-prcm"; + reg = <0x01f01400 0x200>; + + ar100: ar100_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "ar100"; + }; + + ahb0: ahb0_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&ar100>; + clock-output-names = "ahb0"; + }; + + apb0: apb0_clk { + compatible = "allwinner,sun8i-a23-apb0-clk"; + #clock-cells = <0>; + clocks = <&ahb0>; + clock-output-names = "apb0"; + }; + + apb0_gates: apb0_gates_clk { + compatible = "allwinner,sun8i-a23-apb0-gates-clk"; + #clock-cells = <1>; + clocks = <&apb0>; + clock-output-names = "apb0_pio", "apb0_timer", + "apb0_rsb", "apb0_uart", + "apb0_i2c"; + }; + + apb0_rst: apb0_rst { + compatible = "allwinner,sun6i-a31-clock-reset"; + #reset-cells = <1>; + }; + }; + r_uart: serial@01f02800 { compatible = "snps,dw-apb-uart"; reg = <0x01f02800 0x400>; interrupts = <0 38 4>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&osc24M>; + clocks = <&apb0_gates 4>; + resets = <&apb0_rst 4>; status = "disabled"; }; }; From ee39a3e308a418a3ff8a911335ae56fc321e3dfc Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 16 Jul 2014 01:15:43 +0800 Subject: [PATCH 18/22] ARM: dts: sun6i: Add pin muxing options for GMAC The A31 SoC has a GMAC gigabit ethernet controller supporting MII, GMII, RGMII modes. Add pin muxing options for these modes. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 42 ++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index baf8eff57610..47e143aa82fe 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -467,6 +467,48 @@ mmc0_pins_a: mmc0@0 { allwinner,drive = <2>; allwinner,pull = <0>; }; + + gmac_pins_mii_a: gmac_mii@0 { + allwinner,pins = "PA0", "PA1", "PA2", "PA3", + "PA8", "PA9", "PA11", + "PA12", "PA13", "PA14", "PA19", + "PA20", "PA21", "PA22", "PA23", + "PA24", "PA26", "PA27"; + allwinner,function = "gmac"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + gmac_pins_gmii_a: gmac_gmii@0 { + allwinner,pins = "PA0", "PA1", "PA2", "PA3", + "PA4", "PA5", "PA6", "PA7", + "PA8", "PA9", "PA10", "PA11", + "PA12", "PA13", "PA14", "PA15", + "PA16", "PA17", "PA18", "PA19", + "PA20", "PA21", "PA22", "PA23", + "PA24", "PA25", "PA26", "PA27"; + allwinner,function = "gmac"; + /* + * data lines in GMII mode run at 125MHz and + * might need a higher signal drive strength + */ + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + gmac_pins_rgmii_a: gmac_rgmii@0 { + allwinner,pins = "PA0", "PA1", "PA2", "PA3", + "PA9", "PA10", "PA11", + "PA12", "PA13", "PA14", "PA19", + "PA20", "PA25", "PA26", "PA27"; + allwinner,function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + allwinner,drive = <3>; + allwinner,pull = <0>; + }; }; ahb1_rst: reset@01c202c0 { From ed29861ae87953e0d559baaf9d225e8f8a8ff19a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 16 Jul 2014 01:15:44 +0800 Subject: [PATCH 19/22] ARM: dts: sun6i: Add GMAC clock node to the A31 dtsi The GMAC uses 1 of 2 sources for its transmit clock, depending on the PHY interface mode. Add both sources as dummy clocks, and as parents to the GMAC clock node. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 47e143aa82fe..b78a5aa4bccc 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -281,6 +281,34 @@ usb_clk: clk@01c200cc { "usb_ohci0", "usb_ohci1", "usb_ohci2"; }; + + /* + * The following two are dummy clocks, placeholders used in the gmac_tx + * clock. The gmac driver will choose one parent depending on the PHY + * interface mode, using clk_set_rate auto-reparenting. + * The actual TX clock rate is not controlled by the gmac_tx clock. + */ + mii_phy_tx_clk: clk@1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "mii_phy_tx"; + }; + + gmac_int_tx_clk: clk@2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_int_tx"; + }; + + gmac_tx_clk: clk@01c200d0 { + #clock-cells = <0>; + compatible = "allwinner,sun7i-a20-gmac-clk"; + reg = <0x01c200d0 0x4>; + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; + clock-output-names = "gmac_tx"; + }; }; soc@01c00000 { From 3dca65f8a67c525cbddfb1fca149435ab4ce37b0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 16 Jul 2014 01:15:45 +0800 Subject: [PATCH 20/22] ARM: dts: sun6i: Add A31 GMAC gigabit ethernet controller node The A31 has the same GMAC found on the A20 SoC, except it has an extra reset control. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index b78a5aa4bccc..578fde202cc1 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -691,6 +691,23 @@ i2c3: i2c@01c2b800 { status = "disabled"; }; + gmac: ethernet@01c30000 { + compatible = "allwinner,sun7i-a20-gmac"; + reg = <0x01c30000 0x1054>; + interrupts = <0 82 4>; + interrupt-names = "macirq"; + clocks = <&ahb1_gates 17>, <&gmac_tx_clk>; + clock-names = "stmmaceth", "allwinner_gmac_tx"; + resets = <&ahb1_rst 17>; + reset-names = "stmmaceth"; + snps,pbl = <2>; + snps,fixed-burst; + snps,force_sf_dma_mode; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + timer@01c60000 { compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; reg = <0x01c60000 0x1000>; From e5073fde6b3f6aafec867cfa9f19597f57349a5d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 16 Jul 2014 01:15:46 +0800 Subject: [PATCH 21/22] ARM: dts: sun6i: Add ethernet alias for GMAC Alias GMAC as ethernet0 so U-boot can fill in the MAC address. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 578fde202cc1..44b07e512c24 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -23,6 +23,7 @@ aliases { serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; + ethernet0 = &gmac; }; From c220aec2bb793bf5a1fb451fd3e4db87654c5ba5 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Wed, 16 Jul 2014 01:15:47 +0800 Subject: [PATCH 22/22] ARM: dts: sun6i: Add Merrii A31 Hummingbird support This adds support for the A31 Hummingbird: http://www.merrii.com/en/pla_d.asp?id=172 The Merrii A31 Hummingbird is a development board based on the Allwinner A31 SoC with multiple USB ports through a USB hub chip, a uSD slot, a 10/100/1000M ethernet port, an AP6210 WiFi/BT chip, TV-in, HDMI, VGA, audio in/out ports, and LCD/CSI headers. Signed-off-by: Maxime Ripard [wens@csie.org: enable usbphy, ehci0, ohci0 for on-board usb hub; add pcf8563 rtc node; add comments for i2c0 and mmc0 pull-ups; correct ethernet phy address to 0x01; drop uart2 (BT chip has no power) and uart3 (no device); use proper commit message] Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 119 ++++++++++++++++++++ 2 files changed, 120 insertions(+) create mode 100644 arch/arm/boot/dts/sun6i-a31-hummingbird.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c3ee9fba892b..8be3687120d2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -375,6 +375,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \ dtb-$(CONFIG_MACH_SUN6I) += \ sun6i-a31-app4-evb1.dtb \ sun6i-a31-colombus.dtb \ + sun6i-a31-hummingbird.dtb \ sun6i-a31-m9.dtb dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-cubieboard2.dtb \ diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts new file mode 100644 index 000000000000..f142065b3c1f --- /dev/null +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -0,0 +1,119 @@ +/* + * Copyright 2014 Maxime Ripard + * + * Maxime Ripard + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun6i-a31.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "Merrii A31 Hummingbird"; + compatible = "merrii,a31-hummingbird", "allwinner,sun6i-a31"; + + chosen { + bootargs = "earlyprintk console=ttyS0,115200"; + }; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 0 8 0>; /* PA8 */ + cd-inverted; + status = "okay"; + }; + + usbphy: phy@01c19400 { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; + + ehci0: usb@01c1a000 { + status = "okay"; + }; + + ohci0: usb@01c1a400 { + status = "okay"; + }; + + pio: pinctrl@01c20800 { + mmc0_pins_a: mmc0@0 { + /* external pull-ups missing for some pins */ + allwinner,pull = <1>; + }; + + mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 { + allwinner,pins = "PA8"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + + usb1_vbus_pin_a: usb1_vbus_pin@0 { + allwinner,pins = "PH24"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + /* pull-ups and devices require AXP221 DLDO3 */ + status = "failed"; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + gmac: ethernet@01c30000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + reg_usb1_vbus: usb1-vbus { + pinctrl-0 = <&usb1_vbus_pin_a>; + gpio = <&pio 7 24 0>; /* PH24 */ + status = "okay"; + }; +};