From d15d8d234248d6575b2d4efc14731d0a623f89d0 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Mon, 24 Mar 2025 20:52:11 +0800 Subject: [PATCH 1/6] ARM: dts: rockchip: Add aliases for rk3036-kylin MMC devices Add aliases for the MMC devices so that after the system starts up, they will all have fixed device numbers. Signed-off-by: Andy Yan Link: https://lore.kernel.org/r/20250324125215.160616-1-andyshrk@163.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3036-kylin.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts index 4f928c7898e9..cde552375a43 100644 --- a/arch/arm/boot/dts/rockchip/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rockchip/rk3036-kylin.dts @@ -8,6 +8,12 @@ / { model = "Rockchip RK3036 KylinBoard"; compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + chosen { stdout-path = "serial2:115200n8"; }; From 709a25f7a433d53dc9f0daf7cf5657f0671c5026 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 10 Apr 2025 10:47:31 -0500 Subject: [PATCH 2/6] ARM: dts: rockchip: Drop redundant CPU "clock-latency" The "clock-latency" property is part of the deprecated opp-v1 binding and is redundant if the opp-v2 table has equal or larger values in any "clock-latency-ns". Add any missing "clock-latency-ns" properties and remove "clock-latency". Signed-off-by: "Rob Herring (Arm)" Link: https://lore.kernel.org/r/20250410-dt-cpu-schema-v2-10-63d7dc9ddd0a@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 8 +++++++- arch/arm/boot/dts/rockchip/rk3188.dtsi | 1 - arch/arm/boot/dts/rockchip/rk322x.dtsi | 1 - arch/arm/boot/dts/rockchip/rk3288.dtsi | 5 +---- arch/arm/boot/dts/rockchip/rv1108.dtsi | 1 - 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index d4572146d135..c49099954c28 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -48,7 +48,6 @@ cpu0: cpu@f00 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf00>; - clock-latency = <40000>; clocks = <&cru ARMCLK>; resets = <&cru SRST_CORE0>; operating-points-v2 = <&cpu_opp_table>; @@ -87,31 +86,38 @@ cpu_opp_table: opp-table-0 { opp-216000000 { opp-hz = /bits/ 64 <216000000>; opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; }; opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; }; opp-696000000 { opp-hz = /bits/ 64 <696000000>; opp-microvolt = <975000 975000 1325000>; + clock-latency-ns = <40000>; }; opp-816000000 { opp-hz = /bits/ 64 <816000000>; opp-microvolt = <1075000 1075000 1325000>; opp-suspend; + clock-latency-ns = <40000>; }; opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <1200000 1200000 1325000>; + clock-latency-ns = <40000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1325000 1325000 1325000>; + clock-latency-ns = <40000>; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3188.dtsi b/arch/arm/boot/dts/rockchip/rk3188.dtsi index 44b54af0bbf9..850bd6e67895 100644 --- a/arch/arm/boot/dts/rockchip/rk3188.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3188.dtsi @@ -23,7 +23,6 @@ cpu0: cpu@0 { compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; - clock-latency = <40000>; clocks = <&cru ARMCLK>; operating-points-v2 = <&cpu0_opp_table>; resets = <&cru SRST_CORE0>; diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi index 96421355c274..cd11a018105b 100644 --- a/arch/arm/boot/dts/rockchip/rk322x.dtsi +++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi @@ -36,7 +36,6 @@ cpu0: cpu@f00 { resets = <&cru SRST_CORE0>; operating-points-v2 = <&cpu0_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; enable-method = "psci"; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi index 3f1d640afafa..42d705b544ec 100644 --- a/arch/arm/boot/dts/rockchip/rk3288.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi @@ -70,7 +70,6 @@ cpu0: cpu@500 { resets = <&cru SRST_CORE0>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -81,7 +80,6 @@ cpu1: cpu@501 { resets = <&cru SRST_CORE1>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -92,7 +90,6 @@ cpu2: cpu@502 { resets = <&cru SRST_CORE2>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -103,7 +100,6 @@ cpu3: cpu@503 { resets = <&cru SRST_CORE3>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; clocks = <&cru ARMCLK>; dynamic-power-coefficient = <370>; }; @@ -116,6 +112,7 @@ cpu_opp_table: opp-table-0 { opp-126000000 { opp-hz = /bits/ 64 <126000000>; opp-microvolt = <900000>; + clock-latency-ns = <40000>; }; opp-216000000 { opp-hz = /bits/ 64 <216000000>; diff --git a/arch/arm/boot/dts/rockchip/rv1108.dtsi b/arch/arm/boot/dts/rockchip/rv1108.dtsi index f3291f3bbc6f..42a4d72597a5 100644 --- a/arch/arm/boot/dts/rockchip/rv1108.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1108.dtsi @@ -32,7 +32,6 @@ cpu0: cpu@f00 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf00>; - clock-latency = <40000>; clocks = <&cru ARMCLK>; #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <75>; From cdc602ad064009470b1c40af51d4a8cd804eaaf9 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Tue, 22 Apr 2025 15:04:44 +0800 Subject: [PATCH 3/6] ARM: dts: rockchip: Add ref clk for hdmi The RK3036 HDMI DDC bus requires it's PHY's reference clock to be enabled first before normal DDC communication can be carried out. Signed-off-by: Andy Yan Tested-by: Heiko Stuebner #rk3036-kylin Link: https://lore.kernel.org/r/20250422070455.432666-6-andyshrk@163.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3036.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rk3036.dtsi b/arch/arm/boot/dts/rockchip/rk3036.dtsi index 63b9912be06a..2c0c0a9e4a64 100644 --- a/arch/arm/boot/dts/rockchip/rk3036.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3036.dtsi @@ -398,8 +398,8 @@ hdmi: hdmi@20034000 { compatible = "rockchip,rk3036-inno-hdmi"; reg = <0x20034000 0x4000>; interrupts = ; - clocks = <&cru PCLK_HDMI>; - clock-names = "pclk"; + clocks = <&cru PCLK_HDMI>, <&cru SCLK_LCDC>; + clock-names = "pclk", "ref"; pinctrl-names = "default"; pinctrl-0 = <&hdmi_ctl>; #sound-dai-cells = <0>; From dd6c77864aa69ba1079998c590b552e35649d51b Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Tue, 22 Apr 2025 15:04:45 +0800 Subject: [PATCH 4/6] Revert "ARM: dts: rockchip: drop grf reference from rk3036 hdmi" This reverts commit 1580ccb6ed9dc76b8ff3e2d8912e8215c8b0fa6d. The HSYNC/VSYNC polarity of rk3036 HDMI are controlled by GRF. Without the polarity configuration in GRF, it can be observed from the HDMI protocol analyzer that the H/V front/back timing output by RK3036 HDMI are currently not in line with the specifications. Signed-off-by: Andy Yan Tested-by: Heiko Stuebner #rk3036-kylin Link: https://lore.kernel.org/r/20250422070455.432666-7-andyshrk@163.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3036.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rockchip/rk3036.dtsi b/arch/arm/boot/dts/rockchip/rk3036.dtsi index 2c0c0a9e4a64..f4292b586bc2 100644 --- a/arch/arm/boot/dts/rockchip/rk3036.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3036.dtsi @@ -400,6 +400,7 @@ hdmi: hdmi@20034000 { interrupts = ; clocks = <&cru PCLK_HDMI>, <&cru SCLK_LCDC>; clock-names = "pclk", "ref"; + rockchip,grf = <&grf>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_ctl>; #sound-dai-cells = <0>; From cb2a6738f33c3a9da7d1c0afa9ea5e9d78282eaa Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 3 May 2025 22:10:42 +0200 Subject: [PATCH 5/6] ARM: dts: rockchip: enable hdmi on rk3066 marsboard The marsboard does have a regular hdmi-a connector and can simply use the already existing infrastructure (rk3066-hdmi) for display output. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250503201043.990933-2-heiko@sntech.de --- .../boot/dts/rockchip/rk3066a-marsboard.dts | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts index ada7dbfc06a5..d2924aca6f2d 100644 --- a/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts @@ -19,6 +19,17 @@ memory@60000000 { reg = <0x60000000 0x40000000>; }; + hdmi_con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + vdd_log: regulator-vdd-log { compatible = "pwm-regulator"; pwms = <&pwm3 0 1000>; @@ -58,6 +69,24 @@ &cpu1 { cpu-supply = <&vdd_arm>; }; +&hdmi { + status = "okay"; +}; + +&hdmi_in_vop1 { + status = "disabled"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; @@ -216,6 +245,10 @@ &usb_otg { status = "okay"; }; +&vop0 { + status = "okay"; +}; + &wdt { status = "okay"; }; From c895c32bf1ce90839fc525c5d23cbf867ebe519a Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 3 May 2025 22:10:43 +0200 Subject: [PATCH 6/6] ARM: dts: rockchip: enable Mali gpu on rk3066 marsboard The rk3066 contains a Mali400 GPU, so enable it. There is no individual (or even controllable) supply for the GPU on the board. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250503201043.990933-3-heiko@sntech.de --- arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts index d2924aca6f2d..de42d1855121 100644 --- a/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-marsboard.dts @@ -69,6 +69,10 @@ &cpu1 { cpu-supply = <&vdd_arm>; }; +&gpu { + status = "okay"; +}; + &hdmi { status = "okay"; };