From 68e01988b2088ff5b8152cc7a8576e2b7930621a Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Tue, 10 Jun 2025 21:45:21 +0800 Subject: [PATCH 001/931] arm64: dts: apple: s5l8960x: Add I2C nodes Add I2C nodes for Apple A7 SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250610-i2c-no-t2-v2-2-a5a71080fba9@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/s5l8960x.dtsi | 76 +++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/apple/s5l8960x.dtsi index 5b5175d6978c..462ffdd348fc 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi @@ -89,6 +89,62 @@ serial0: serial@20a0a0000 { status = "disabled"; }; + i2c0: i2c@20a110000 { + compatible = "apple,s5l8960x-i2c", "apple,i2c"; + reg = <0x2 0x0a110000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@20a111000 { + compatible = "apple,s5l8960x-i2c", "apple,i2c"; + reg = <0x2 0x0a111000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@20a112000 { + compatible = "apple,s5l8960x-i2c", "apple,i2c"; + reg = <0x2 0x0a112000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@20a113000 { + compatible = "apple,s5l8960x-i2c", "apple,i2c"; + reg = <0x2 0x0a113000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmgr: power-management@20e000000 { compatible = "apple,s5l8960x-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; @@ -140,6 +196,26 @@ pinctrl: pinctrl@20e300000 { , , ; + + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux = , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux = , + ; + }; }; }; From 5b1ab37ccc605f20e5309f7ba45eea2aec6054d1 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Tue, 10 Jun 2025 21:45:22 +0800 Subject: [PATCH 002/931] arm64: dts: apple: t7000: Add I2C nodes Add I2C nodes for Apple A8 SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250610-i2c-no-t2-v2-3-a5a71080fba9@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t7000.dtsi | 76 ++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7000.dtsi b/arch/arm64/boot/dts/apple/t7000.dtsi index 52edc8d776a9..0342455d3444 100644 --- a/arch/arm64/boot/dts/apple/t7000.dtsi +++ b/arch/arm64/boot/dts/apple/t7000.dtsi @@ -144,6 +144,62 @@ serial6: serial@20a0d8000 { status = "disabled"; }; + i2c0: i2c@20a110000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a110000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@20a111000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a111000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@20a112000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a112000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@20a113000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a113000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmgr: power-management@20e000000 { compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; @@ -195,6 +251,26 @@ pinctrl: pinctrl@20e300000 { , , ; + + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux = , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux = , + ; + }; }; }; From a56771d333edb1d1d5631e296fb2b021a39b3940 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Tue, 10 Jun 2025 21:45:23 +0800 Subject: [PATCH 003/931] arm64: dts: apple: t7001: Add I2C nodes Add I2C nodes for Apple A8X SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250610-i2c-no-t2-v2-4-a5a71080fba9@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t7001.dtsi | 76 ++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/apple/t7001.dtsi index a2efa81305df..e1afb0542369 100644 --- a/arch/arm64/boot/dts/apple/t7001.dtsi +++ b/arch/arm64/boot/dts/apple/t7001.dtsi @@ -144,6 +144,62 @@ serial0: serial@20a0c0000 { status = "disabled"; }; + i2c0: i2c@20a110000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a110000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@20a111000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a111000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@20a112000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a112000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@20a113000 { + compatible = "apple,t7000-i2c", "apple,i2c"; + reg = <0x2 0x0a113000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmgr: power-management@20e000000 { compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; @@ -188,6 +244,26 @@ pinctrl: pinctrl@20e300000 { , , ; + + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux = , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux = , + ; + }; }; }; From 5bee6cb9d9df55125eddd63345054ff08a0d44e9 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Tue, 10 Jun 2025 21:45:24 +0800 Subject: [PATCH 004/931] arm64: dts: apple: s800-0-3: Add I2C nodes Add I2C nodes for Apple A9 SoC. There is actually an i2c3 on this SoC but the SCL and SDA lines appears to be not connected and no peripherals are expected to be connected to it, so there is no node for it. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250610-i2c-no-t2-v2-5-a5a71080fba9@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/s800-0-3.dtsi | 57 +++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s800-0-3.dtsi b/arch/arm64/boot/dts/apple/s800-0-3.dtsi index 09db4ed64054..bb38662b7d2e 100644 --- a/arch/arm64/boot/dts/apple/s800-0-3.dtsi +++ b/arch/arm64/boot/dts/apple/s800-0-3.dtsi @@ -88,6 +88,48 @@ serial0: serial@20a0c0000 { status = "disabled"; }; + i2c0: i2c@20a110000 { + compatible = "apple,s8000-i2c", "apple,i2c"; + reg = <0x2 0x0a110000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@20a111000 { + compatible = "apple,s8000-i2c", "apple,i2c"; + reg = <0x2 0x0a111000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@20a112000 { + compatible = "apple,s8000-i2c", "apple,i2c"; + reg = <0x2 0x0a112000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmgr: power-management@20e000000 { compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; @@ -131,6 +173,21 @@ pinctrl_ap: pinctrl@20f100000 { , , ; + + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux = , + ; + }; }; pinctrl_aop: pinctrl@2100f0000 { From baf703b08374b10cd4d3dbbf7410569fee2e8cb1 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Tue, 10 Jun 2025 21:45:25 +0800 Subject: [PATCH 005/931] arm64: dts: apple: s8001: Add I2C nodes Add I2C nodes for Apple A9 SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250610-i2c-no-t2-v2-6-a5a71080fba9@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/s8001.dtsi | 76 ++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/apple/s8001.dtsi index fee350765894..b5b00dca6ffa 100644 --- a/arch/arm64/boot/dts/apple/s8001.dtsi +++ b/arch/arm64/boot/dts/apple/s8001.dtsi @@ -137,6 +137,62 @@ serial0: serial@20a0c0000 { status = "disabled"; }; + i2c0: i2c@20a110000 { + compatible = "apple,s8000-i2c", "apple,i2c"; + reg = <0x2 0x0a110000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@20a111000 { + compatible = "apple,s8000-i2c", "apple,i2c"; + reg = <0x2 0x0a111000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@20a112000 { + compatible = "apple,s8000-i2c", "apple,i2c"; + reg = <0x2 0x0a112000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@20a113000 { + compatible = "apple,s8000-i2c", "apple,i2c"; + reg = <0x2 0x0a113000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmgr: power-management@20e000000 { compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; @@ -173,6 +229,26 @@ pinctrl_ap: pinctrl@20f100000 { , , ; + + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux = , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux = , + ; + }; }; pinctrl_aop: pinctrl@2100f0000 { From 9f286293541e20c904ce59ad7ea26f8b6cab126a Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Tue, 10 Jun 2025 21:45:26 +0800 Subject: [PATCH 006/931] arm64: dts: apple: t8010: Add I2C nodes Add I2C nodes for Apple A10 SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250610-i2c-no-t2-v2-7-a5a71080fba9@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8010.dtsi | 76 ++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/apple/t8010.dtsi index b961d4f65bc3..522b3896aa87 100644 --- a/arch/arm64/boot/dts/apple/t8010.dtsi +++ b/arch/arm64/boot/dts/apple/t8010.dtsi @@ -164,6 +164,62 @@ serial0: serial@20a0c0000 { status = "disabled"; }; + i2c0: i2c@20a110000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a110000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@20a111000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a111000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@20a112000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a112000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@20a113000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a113000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmgr: power-management@20e000000 { compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; @@ -207,6 +263,26 @@ pinctrl_ap: pinctrl@20f100000 { , , ; + + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux = , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux = , + ; + }; }; pinctrl_aop: pinctrl@2100f0000 { From 1d16ae50cb1bdcfe15319d946e3418dcbdcd8509 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Tue, 10 Jun 2025 21:45:27 +0800 Subject: [PATCH 007/931] arm64: dts: apple: t8011: Add I2C nodes Add I2C nodes for Apple A10X SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250610-i2c-no-t2-v2-8-a5a71080fba9@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8011.dtsi | 76 ++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8011.dtsi b/arch/arm64/boot/dts/apple/t8011.dtsi index 974f78cc77cf..039aa4d1e887 100644 --- a/arch/arm64/boot/dts/apple/t8011.dtsi +++ b/arch/arm64/boot/dts/apple/t8011.dtsi @@ -168,6 +168,62 @@ serial0: serial@20a0c0000 { status = "disabled"; }; + i2c0: i2c@20a110000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a110000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@20a111000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a111000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@20a112000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a112000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@20a113000 { + compatible = "apple,t8010-i2c", "apple,i2c"; + reg = <0x2 0x0a113000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pmgr: power-management@20e000000 { compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; #address-cells = <1>; @@ -204,6 +260,26 @@ pinctrl_ap: pinctrl@20f100000 { , , ; + + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux = , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux = , + ; + }; }; pinctrl_aop: pinctrl@2100f0000 { From e1313c2185d22c2f8db508db61d3e2c0e62193d7 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Tue, 10 Jun 2025 21:45:28 +0800 Subject: [PATCH 008/931] arm64: dts: apple: t8015: Add I2C nodes Add I2C nodes for Apple A11 SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250610-i2c-no-t2-v2-9-a5a71080fba9@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8015.dtsi | 76 ++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/apple/t8015.dtsi index 12acf8fc8bc6..e002ecee3390 100644 --- a/arch/arm64/boot/dts/apple/t8015.dtsi +++ b/arch/arm64/boot/dts/apple/t8015.dtsi @@ -265,6 +265,62 @@ cpufreq_p: performance-controller@208ea0000 { #performance-domain-cells = <0>; }; + i2c0: i2c@22e200000 { + compatible = "apple,t8015-i2c", "apple,i2c"; + reg = <0x2 0x2e200000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@22e204000 { + compatible = "apple,t8015-i2c", "apple,i2c"; + reg = <0x2 0x2e204000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@22e208000 { + compatible = "apple,t8015-i2c", "apple,i2c"; + reg = <0x2 0x2e208000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@22e20c000 { + compatible = "apple,t8015-i2c", "apple,i2c"; + reg = <0x2 0x2e20c000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + serial0: serial@22e600000 { compatible = "apple,s5l-uart"; reg = <0x2 0x2e600000 0x0 0x4000>; @@ -321,6 +377,26 @@ pinctrl_ap: pinctrl@233100000 { , , ; + + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux = , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux = , + ; + }; }; pinctrl_aop: pinctrl@2340f0000 { From 6101fe95b1ee551b7f5d03a9edd80edc7d446be9 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Tue, 10 Jun 2025 15:29:49 +0000 Subject: [PATCH 009/931] arm64: dts: apple: t8103: Add SMC node Signed-off-by: Hector Martin Reviewed-by: Linus Walleij Reviewed-by: Sven Peter Signed-off-by: Russell King (Oracle) Reviewed-by: Alyssa Rosenzweig Reviewed-by: Neal Gompa Link: https://lore.kernel.org/r/20250610-smc-6-15-v7-8-556cafd771d3@kernel.org Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8103.dtsi | 35 ++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 589ddc039799..8b7b27887968 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -896,6 +896,41 @@ wdt: watchdog@23d2b0000 { interrupts = ; }; + smc: smc@23e400000 { + compatible = "apple,t8103-smc", "apple,smc"; + reg = <0x2 0x3e400000 0x0 0x4000>, + <0x2 0x3fe00000 0x0 0x100000>; + reg-names = "smc", "sram"; + mboxes = <&smc_mbox>; + + smc_gpio: gpio { + compatible = "apple,smc-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + smc_reboot: reboot { + compatible = "apple,smc-reboot"; + nvmem-cells = <&shutdown_flag>, <&boot_stage>, + <&boot_error_count>, <&panic_count>; + nvmem-cell-names = "shutdown_flag", "boot_stage", + "boot_error_count", "panic_count"; + }; + }; + + smc_mbox: mbox@23e408000 { + compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x2 0x3e408000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + }; + pinctrl_smc: pinctrl@23e820000 { compatible = "apple,t8103-pinctrl", "apple,pinctrl"; reg = <0x2 0x3e820000 0x0 0x4000>; From 49765a617a54837910b26978bb0dc01908a673e2 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Tue, 10 Jun 2025 15:29:50 +0000 Subject: [PATCH 010/931] arm64: dts: apple: t8112: Add SMC node Signed-off-by: Hector Martin Reviewed-by: Alyssa Rosenzweig Reviewed-by: Neal Gompa Link: https://lore.kernel.org/r/20250610-smc-6-15-v7-9-556cafd771d3@kernel.org Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8112.dtsi | 35 ++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/apple/t8112.dtsi index b36b345861b6..3f79878b25af 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -899,6 +899,41 @@ rtc_offset: rtc-offset@f900 { }; }; + smc: smc@23e400000 { + compatible = "apple,t8112-smc", "apple,smc"; + reg = <0x2 0x3e400000 0x0 0x4000>, + <0x2 0x3fe00000 0x0 0x100000>; + reg-names = "smc", "sram"; + mboxes = <&smc_mbox>; + + smc_gpio: gpio { + compatible = "apple,smc-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + smc_reboot: reboot { + compatible = "apple,smc-reboot"; + nvmem-cells = <&shutdown_flag>, <&boot_stage>, + <&boot_error_count>, <&panic_count>; + nvmem-cell-names = "shutdown_flag", "boot_stage", + "boot_error_count", "panic_count"; + }; + }; + + smc_mbox: mbox@23e408000 { + compatible = "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x2 0x3e408000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + }; + pinctrl_smc: pinctrl@23e820000 { compatible = "apple,t8112-pinctrl", "apple,pinctrl"; reg = <0x2 0x3e820000 0x0 0x4000>; From 4379305ffbc2eebe3de673fc965145d441c89b8f Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Tue, 10 Jun 2025 15:29:51 +0000 Subject: [PATCH 011/931] arm64: dts: apple: t600x: Add SMC node Signed-off-by: Hector Martin Reviewed-by: Alyssa Rosenzweig Reviewed-by: Neal Gompa Link: https://lore.kernel.org/r/20250610-smc-6-15-v7-10-556cafd771d3@kernel.org Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t600x-die0.dtsi | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi index 1563b3ce1ff6..3603b276a2ab 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -24,6 +24,41 @@ aic: interrupt-controller@28e100000 { power-domains = <&ps_aic>; }; + smc: smc@290400000 { + compatible = "apple,t6000-smc", "apple,smc"; + reg = <0x2 0x90400000 0x0 0x4000>, + <0x2 0x91e00000 0x0 0x100000>; + reg-names = "smc", "sram"; + mboxes = <&smc_mbox>; + + smc_gpio: gpio { + compatible = "apple,smc-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + smc_reboot: reboot { + compatible = "apple,smc-reboot"; + nvmem-cells = <&shutdown_flag>, <&boot_stage>, + <&boot_error_count>, <&panic_count>; + nvmem-cell-names = "shutdown_flag", "boot_stage", + "boot_error_count", "panic_count"; + }; + }; + + smc_mbox: mbox@290408000 { + compatible = "apple,t6000-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x2 0x90408000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + }; + pinctrl_smc: pinctrl@290820000 { compatible = "apple,t6000-pinctrl", "apple,pinctrl"; reg = <0x2 0x90820000 0x0 0x4000>; From b20d199da7be0602013e88123e9fe1b17f22a4cb Mon Sep 17 00:00:00 2001 From: Willie Thai Date: Thu, 17 Jul 2025 09:52:10 +0000 Subject: [PATCH 012/931] ARM: dts: aspeed: nvidia: gb200nvl: Add VCC Supply Add Vcc supply to avoid probing the devices before they have power. Signed-off-by: Deepak Kodihalli Signed-off-by: Ed Tanous Signed-off-by: Willie Thai Link: https://patch.msgid.link/20250717-update-gb200nvl-dts-for-new-hardware-v3-1-f28145c55c98@nvidia.com Signed-off-by: Andrew Jeffery --- .../aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts index 41e3e9dd85f5..bd9395a19413 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts @@ -126,6 +126,17 @@ button-uid { gpio = <&sgpiom0 154 GPIO_ACTIVE_LOW>; }; }; + + standby_power_regulator: standby-power-regulator { + status = "okay"; + compatible = "regulator-fixed"; + regulator-name = "standby_power"; + gpio = <&gpio0 ASPEED_GPIO(M, 3) GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-always-on; + }; }; // Enable Primary flash on FMC for bring up activity @@ -431,6 +442,7 @@ exp4: gpio@21 { #interrupt-cells = <2>; interrupt-parent = <&gpio1>; interrupts = ; + vcc-supply = <&standby_power_regulator>; gpio-line-names = "RTC_MUX_SEL-O", "PCI_MUX_SEL-O", @@ -464,6 +476,7 @@ i2c-mux@71 { #size-cells = <0>; reg = <0x71>; i2c-mux-idle-disconnect; + vdd-supply = <&standby_power_regulator>; imux16: i2c@0 { #address-cells = <1>; @@ -528,6 +541,7 @@ i2c-mux@72 { #size-cells = <0>; reg = <0x72>; i2c-mux-idle-disconnect; + vdd-supply = <&standby_power_regulator>; imux20: i2c@0 { #address-cells = <1>; @@ -545,6 +559,7 @@ gpio@21 { reg = <0x21>; gpio-controller; #gpio-cells = <2>; + vcc-supply = <&standby_power_regulator>; gpio-line-names = "RST_CX_0_L-O", "RST_CX_1_L-O", @@ -584,6 +599,7 @@ i2c-mux@73 { #size-cells = <0>; reg = <0x73>; i2c-mux-idle-disconnect; + vdd-supply = <&standby_power_regulator>; imux24: i2c@0 { #address-cells = <1>; @@ -602,6 +618,7 @@ i2c-mux@70 { #size-cells = <0>; reg = <0x70>; i2c-mux-idle-disconnect; + vdd-supply = <&standby_power_regulator>; i2c25mux0: i2c@0 { #address-cells = <1>; @@ -648,6 +665,7 @@ i2c-mux@75 { #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; + vdd-supply = <&standby_power_regulator>; imux28: i2c@0 { #address-cells = <1>; @@ -712,6 +730,7 @@ i2c-mux@76 { #size-cells = <0>; reg = <0x76>; i2c-mux-idle-disconnect; + vdd-supply = <&standby_power_regulator>; imux32: i2c@0 { #address-cells = <1>; @@ -729,6 +748,7 @@ gpio@21 { reg = <0x21>; gpio-controller; #gpio-cells = <2>; + vcc-supply = <&standby_power_regulator>; gpio-line-names = "SEC_RST_CX_0_L-O", "SEC_RST_CX_1_L-O", @@ -768,6 +788,7 @@ i2c-mux@77 { #size-cells = <0>; reg = <0x77>; i2c-mux-idle-disconnect; + vdd-supply = <&standby_power_regulator>; imux36: i2c@0 { #address-cells = <1>; @@ -862,6 +883,7 @@ exp0: gpio@20 { #interrupt-cells = <2>; interrupt-parent = <&gpio1>; interrupts = ; + vcc-supply = <&standby_power_regulator>; gpio-line-names = "FPGA_THERM_OVERT_L-I", "FPGA_READY_BMC-I", @@ -891,6 +913,7 @@ exp1: gpio@21 { #interrupt-cells = <2>; interrupt-parent = <&gpio1>; interrupts = ; + vcc-supply = <&standby_power_regulator>; gpio-line-names = "SEC_FPGA_THERM_OVERT_L-I", "SEC_FPGA_READY_BMC-I", @@ -949,6 +972,7 @@ exp3: gpio@74 { #interrupt-cells = <2>; interrupt-parent = <&gpio1>; interrupts = ; + vcc-supply = <&standby_power_regulator>; gpio-line-names = "IOB_PRSNT_L", "IOB_DP_HPD", @@ -1014,6 +1038,7 @@ i2c-mux@77 { #size-cells = <0>; reg = <0x77>; i2c-mux-idle-disconnect; + vdd-supply = <&standby_power_regulator>; e1si2c0: i2c@0 { #address-cells = <1>; @@ -1054,6 +1079,7 @@ i2c-mux@77 { #size-cells = <0>; reg = <0x77>; i2c-mux-idle-disconnect; + vdd-supply = <&standby_power_regulator>; e1si2c4: i2c@0 { #address-cells = <1>; From 63d2e5dd62ab4002be544bbe109d7516a1377d37 Mon Sep 17 00:00:00 2001 From: Willie Thai Date: Thu, 17 Jul 2025 09:52:11 +0000 Subject: [PATCH 013/931] ARM: dts: aspeed: nvidia: gb200nvl: Enable i2c3 bus Enable i2c3 bus for telemetry fetching purpose. Signed-off-by: Deepak Kodihalli Signed-off-by: Ed Tanous Signed-off-by: Willie Thai Link: https://patch.msgid.link/20250717-update-gb200nvl-dts-for-new-hardware-v3-2-f28145c55c98@nvidia.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts index bd9395a19413..f0a18adc3287 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts @@ -422,7 +422,7 @@ &i2c2 { // I2C4 &i2c3 { - status = "disabled"; + status = "okay"; }; // I2C5 From 2193aed6024c5766375a25f84f267053819090d0 Mon Sep 17 00:00:00 2001 From: Willie Thai Date: Thu, 17 Jul 2025 09:52:12 +0000 Subject: [PATCH 014/931] ARM: dts: aspeed: nvidia: gb200nvl: Repurpose the HMC gpio pin Repurpose the HMC reset pin to FPGA reset pin. This change is according to hardware change. Signed-off-by: Deepak Kodihalli Signed-off-by: Ed Tanous Signed-off-by: Willie Thai Link: https://patch.msgid.link/20250717-update-gb200nvl-dts-for-new-hardware-v3-3-f28145c55c98@nvidia.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts index f0a18adc3287..dd2a02a6d1d4 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts @@ -1126,7 +1126,7 @@ &gpio0 { /*J0-J7*/ "", "", "", "", "", "", "", "", /*K0-K7*/ "", "", "", "", "", "", "", "", /*L0-L7*/ "", "", "", "", "", "", "", "", - /*M0-M7*/ "PCIE_EP_RST_EN-O", "BMC_FRU_WP-O", "HMC_RESET_L-O", "STBY_POWER_EN-O", + /*M0-M7*/ "PCIE_EP_RST_EN-O", "BMC_FRU_WP-O", "FPGA_RST_L-O", "STBY_POWER_EN-O", "STBY_POWER_PG-I", "PCIE_EP_RST_L-O", "", "", /*N0-N7*/ "", "", "", "", "", "", "", "", /*O0-O7*/ "", "", "", "", "", "", "", "", From 2b4e0d787dcd7fb936b0b2f2d095a5ef3754351d Mon Sep 17 00:00:00 2001 From: Willie Thai Date: Thu, 17 Jul 2025 09:52:13 +0000 Subject: [PATCH 015/931] ARM: dts: aspeed: nvidia: gb200nvl: Enable MAC0 for BMC network Upstream-Status: Inappropriate Bad devices Signed-off-by: Deepak Kodihalli Signed-off-by: Ed Tanous Signed-off-by: Willie Thai Reviewed-by: Andrew Lunn Link: https://patch.msgid.link/20250717-update-gb200nvl-dts-for-new-hardware-v3-4-f28145c55c98@nvidia.com Signed-off-by: Andrew Jeffery --- .../aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts index dd2a02a6d1d4..72dafebc080d 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts @@ -227,6 +227,30 @@ &uart_routing { status = "okay"; }; +&mdio0 { + status = "okay"; + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mdio3 { + status = "okay"; + ethphy3: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + phy-mode = "rgmii-id"; + phy-handle = <ðphy3>; + pinctrl-0 = <&pinctrl_rgmii1_default>; +}; + &mac2 { status = "okay"; phy-mode = "rmii"; From fc6c8ccfaa142bbfd981ed3afb9ed894d7980dba Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:03 -0700 Subject: [PATCH 016/931] ARM: dts: aspeed: wedge400: Fix DTB warnings Fix the deprecated spi-gpio properties in wedge400 dts. Signed-off-by: Tao Ren Link: https://patch.msgid.link/20250728055618.61616-2-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts index 5a8169bbda87..3e4d30f0884d 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts @@ -75,9 +75,9 @@ spi_gpio: spi { #size-cells = <0>; cs-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_LOW>; - gpio-sck = <&gpio ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>; num-chipselects = <1>; tpm@0 { From 78831e53bb2162809f4ed6d2463bbea947c70b24 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:04 -0700 Subject: [PATCH 017/931] ARM: dts: aspeed: fuji: Fix DTB warnings Remove redundant adm1278 properties from fuji dts. Signed-off-by: Tao Ren Link: https://patch.msgid.link/20250728055618.61616-3-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts index f23c26a3441d..840d19d6b1d4 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts @@ -248,8 +248,6 @@ imux16: i2c@0 { adm1278@10 { compatible = "adi,adm1278"; reg = <0x10>; - #address-cells = <1>; - #size-cells = <0>; shunt-resistor-micro-ohms = <1500>; }; }; @@ -577,8 +575,6 @@ imux67: i2c@3 { adm1278@10 { compatible = "adi,adm1278"; reg = <0x10>; - #address-cells = <1>; - #size-cells = <0>; shunt-resistor-micro-ohms = <250>; }; }; @@ -648,8 +644,6 @@ imux75: i2c@3 { adm1278@10 { compatible = "adi,adm1278"; reg = <0x10>; - #address-cells = <1>; - #size-cells = <0>; shunt-resistor-micro-ohms = <250>; }; }; From dc4717e34f6942628f26dc19c831a8dfecc76c31 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:05 -0700 Subject: [PATCH 018/931] ARM: dts: aspeed: Fix DTB warnings in ast2600-facebook-netbmc-common.dtsi Fix deprecated spi-gpio properties in ast2600-facebook-netbmc-common.dtsi. Signed-off-by: Tao Ren Link: https://patch.msgid.link/20250728055618.61616-4-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- .../dts/aspeed/ast2600-facebook-netbmc-common.dtsi | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi index 00e5887c926f..208cf6567ed4 100644 --- a/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi +++ b/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi @@ -31,9 +31,13 @@ spi_gpio: spi { #address-cells = <1>; #size-cells = <0>; - gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>; + /* + * chipselect pins are defined in platform .dts files + * separately. + */ + sck-gpios = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>; tpm@0 { compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; From c11f9190f9d6a08953d5346c016a29c42ddb17dd Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:06 -0700 Subject: [PATCH 019/931] ARM: dts: aspeed: Move eMMC out of ast2600-facebook-netbmc-common.dtsi Move eMMC entries from ast2600-facebook-netbmc-common.dtsi to each platform because eMMC is removed from future Meta/Facebook AST2600 Network BMC platforms. Signed-off-by: Tao Ren Link: https://patch.msgid.link/20250728055618.61616-5-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- .../boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts | 12 ++++++++++++ .../arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts | 12 ++++++++++++ .../dts/aspeed/ast2600-facebook-netbmc-common.dtsi | 12 ------------ 3 files changed, 24 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts index 74f3c67e0eff..ff1009ea1c49 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts @@ -201,3 +201,15 @@ fixed-link { full-duplex; }; }; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + status = "okay"; + + non-removable; + max-frequency = <25000000>; + bus-width = <4>; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts index 840d19d6b1d4..d0331980d082 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts @@ -1243,3 +1243,15 @@ &mac3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rgmii4_default>; }; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + status = "okay"; + + non-removable; + max-frequency = <25000000>; + bus-width = <4>; +}; diff --git a/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi index 208cf6567ed4..0ef225acddfc 100644 --- a/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi +++ b/arch/arm/boot/dts/aspeed/ast2600-facebook-netbmc-common.dtsi @@ -156,18 +156,6 @@ &vhub { status = "okay"; }; -&emmc_controller { - status = "okay"; -}; - -&emmc { - status = "okay"; - - non-removable; - max-frequency = <25000000>; - bus-width = <4>; -}; - &rtc { status = "okay"; }; From e1b5c5f54797a61073e564278e7dbefb469c1c50 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:07 -0700 Subject: [PATCH 020/931] ARM: dts: aspeed: Add facebook-bmc-flash-layout-128-data64.dtsi Add facebook-bmc-flash-layout-128-data64.dts (with 64MB datastore) to be used by Meta Network BMC platforms. Signed-off-by: Tao Ren Link: https://patch.msgid.link/20250728055618.61616-6-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- .../facebook-bmc-flash-layout-128-data64.dtsi | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout-128-data64.dtsi diff --git a/arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout-128-data64.dtsi b/arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout-128-data64.dtsi new file mode 100644 index 000000000000..efd92232cda2 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/facebook-bmc-flash-layout-128-data64.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2020 Facebook Inc. + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * u-boot partition: 896KB. + */ + u-boot@0 { + reg = <0x0 0xe0000>; + label = "u-boot"; + }; + + /* + * u-boot environment variables: 64KB. + */ + u-boot-env@e0000 { + reg = <0xe0000 0x10000>; + label = "env"; + }; + + /* + * image metadata partition (64KB), used by Facebook internal + * tools. + */ + image-meta@f0000 { + reg = <0xf0000 0x10000>; + label = "meta"; + }; + + /* + * FIT image: 63 MB. + */ + fit@100000 { + reg = <0x100000 0x3f00000>; + label = "fit"; + }; + + /* + * "data0" partition (64MB) is used by Facebook BMC platforms as + * persistent data store. + */ + data0@4000000 { + reg = <0x4000000 0x4000000>; + label = "data0"; + }; + + /* + * Although the master partition can be created by enabling + * MTD_PARTITIONED_MASTER option, below "flash0" partition is + * explicitly created to avoid breaking legacy applications. + */ + flash0@0 { + reg = <0x0 0x8000000>; + label = "flash0"; + }; +}; From 83656699ba3ab61a86b83daf4579cb5598d68c55 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:08 -0700 Subject: [PATCH 021/931] dt-bindings: arm: aspeed: add Facebook Wedge400-data64 board Document the new compatibles used on Meta/Facebook Wedge400-data64 board. Signed-off-by: Tao Ren Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250728055618.61616-7-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 456dbf7b5ec8..5a01e2f4ce20 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -46,6 +46,7 @@ properties: - facebook,yamp-bmc - facebook,yosemitev2-bmc - facebook,wedge400-bmc + - facebook,wedge400-data64-bmc - hxt,stardragon4800-rep2-bmc - ibm,mihawk-bmc - ibm,mowgli-bmc From 2baf3b61f05cedd470b460a3b6fd1bcabd02be51 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:09 -0700 Subject: [PATCH 022/931] ARM: dts: aspeed: Add Facebook Wedge400-data64 (AST2500) BMC Add wedge400-data64.dts to extend wedge400's data0 partition from 8MB to 64MB smoothly. wedge400-data64.dts is copied from wedge400.dts with below changes: - updating model/compatible strings. - updating flash0 partition. Signed-off-by: Tao Ren Link: https://patch.msgid.link/20250728055618.61616-8-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed-bmc-facebook-wedge400-data64.dts | 375 ++++++++++++++++++ 2 files changed, 376 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400-data64.dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index aba7451ab749..0c63297bf13b 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-tiogapass.dtb \ aspeed-bmc-facebook-wedge40.dtb \ aspeed-bmc-facebook-wedge100.dtb \ + aspeed-bmc-facebook-wedge400-data64.dtb \ aspeed-bmc-facebook-wedge400.dtb \ aspeed-bmc-facebook-yamp.dtb \ aspeed-bmc-facebook-yosemitev2.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400-data64.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400-data64.dts new file mode 100644 index 000000000000..1d46eaee8656 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400-data64.dts @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2019 Facebook Inc. +/dts-v1/; + +#include +#include "ast2500-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Wedge 400 BMC (64MB Datastore)"; + compatible = "facebook,wedge400-data64-bmc", "aspeed,ast2500"; + + aliases { + /* + * PCA9548 (2-0070) provides 8 channels connecting to + * SCM (System Controller Module). + */ + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + + /* + * PCA9548 (8-0070) provides 8 channels connecting to + * SMB (Switch Main Board). + */ + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + + /* + * PCA9548 (11-0076) provides 8 channels connecting to + * FCM (Fan Controller Module). + */ + i2c32 = &imux32; + i2c33 = &imux33; + i2c34 = &imux34; + i2c35 = &imux35; + i2c36 = &imux36; + i2c37 = &imux37; + i2c38 = &imux38; + i2c39 = &imux39; + + spi2 = &spi_gpio; + }; + + chosen { + stdout-path = &uart1; + }; + + ast-adc-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, + <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>; + }; + + /* + * GPIO-based SPI Master is required to access SPI TPM, because + * full-duplex SPI transactions are not supported by ASPEED SPI + * Controllers. + */ + spi_gpio: spi { + status = "okay"; + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_LOW>; + sck-gpios = <&gpio ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; +}; + +/* + * Both firmware flashes are 128MB on Wedge400 BMC. + */ +&fmc_flash0 { +#include "facebook-bmc-flash-layout-128-data64.dtsi" +}; + +&fmc_flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x8000000>; + label = "flash1"; + }; + }; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +/* + * I2C bus #0 is multi-master environment dedicated for BMC and Bridge IC + * communication. + */ +&i2c0 { + status = "okay"; + multi-master; + bus-frequency = <1000000>; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux28: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux29: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux30: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux31: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + i2c-mux@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux32: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux33: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux34: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux35: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux36: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux37: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux38: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux39: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&sdhci1 { + max-frequency = <25000000>; + /* + * DMA mode needs to be disabled to avoid conflicts with UHCI + * Controller in AST2500 SoC. + */ + sdhci-caps-mask = <0x0 0x580000>; +}; From fe0e2fbb6a7801883df3567b1e89b834c0969998 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:10 -0700 Subject: [PATCH 023/931] ARM: dts: aspeed: wedge400: Include wedge400-data64.dts Include "wedge400-data64.dts" in wedge400 dts to avoid duplicated code. Wedge400-data64 and Wedge400 are identical except the BMC flash layout. Signed-off-by: Tao Ren Link: https://patch.msgid.link/20250728055618.61616-9-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- .../aspeed/aspeed-bmc-facebook-wedge400.dts | 366 +----------------- 1 file changed, 2 insertions(+), 364 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts index 3e4d30f0884d..ef0cfc51cda4 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts @@ -1,376 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ // Copyright (c) 2019 Facebook Inc. -/dts-v1/; -#include -#include "ast2500-facebook-netbmc-common.dtsi" +#include "aspeed-bmc-facebook-wedge400-data64.dts" / { model = "Facebook Wedge 400 BMC"; compatible = "facebook,wedge400-bmc", "aspeed,ast2500"; - - aliases { - /* - * PCA9548 (2-0070) provides 8 channels connecting to - * SCM (System Controller Module). - */ - i2c16 = &imux16; - i2c17 = &imux17; - i2c18 = &imux18; - i2c19 = &imux19; - i2c20 = &imux20; - i2c21 = &imux21; - i2c22 = &imux22; - i2c23 = &imux23; - - /* - * PCA9548 (8-0070) provides 8 channels connecting to - * SMB (Switch Main Board). - */ - i2c24 = &imux24; - i2c25 = &imux25; - i2c26 = &imux26; - i2c27 = &imux27; - i2c28 = &imux28; - i2c29 = &imux29; - i2c30 = &imux30; - i2c31 = &imux31; - - /* - * PCA9548 (11-0076) provides 8 channels connecting to - * FCM (Fan Controller Module). - */ - i2c32 = &imux32; - i2c33 = &imux33; - i2c34 = &imux34; - i2c35 = &imux35; - i2c36 = &imux36; - i2c37 = &imux37; - i2c38 = &imux38; - i2c39 = &imux39; - - spi2 = &spi_gpio; - }; - - chosen { - stdout-path = &uart1; - bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; - }; - - ast-adc-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, - <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>; - }; - - /* - * GPIO-based SPI Master is required to access SPI TPM, because - * full-duplex SPI transactions are not supported by ASPEED SPI - * Controllers. - */ - spi_gpio: spi { - status = "okay"; - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - cs-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_LOW>; - sck-gpios = <&gpio ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>; - miso-gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>; - num-chipselects = <1>; - - tpm@0 { - compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; - spi-max-frequency = <33000000>; - reg = <0>; - }; - }; }; -/* - * Both firmware flashes are 128MB on Wedge400 BMC. - */ &fmc_flash0 { + /delete-node/partitions; #include "facebook-bmc-flash-layout-128.dtsi" }; - -&fmc_flash1 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - flash1@0 { - reg = <0x0 0x8000000>; - label = "flash1"; - }; - }; -}; - -&uart2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default - &pinctrl_rxd2_default>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default>; -}; - -/* - * I2C bus #0 is multi-master environment dedicated for BMC and Bridge IC - * communication. - */ -&i2c0 { - status = "okay"; - multi-master; - bus-frequency = <1000000>; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux16: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux17: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux18: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux19: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux20: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux21: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux22: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux23: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux24: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux25: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux26: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux27: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux28: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux29: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux30: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux31: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - - }; -}; - -&i2c9 { - status = "okay"; -}; - -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; - - i2c-mux@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux32: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux33: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux34: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux35: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux36: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux37: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux38: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux39: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - - }; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&uhci { - status = "okay"; -}; - -&sdhci1 { - max-frequency = <25000000>; - /* - * DMA mode needs to be disabled to avoid conflicts with UHCI - * Controller in AST2500 SoC. - */ - sdhci-caps-mask = <0x0 0x580000>; -}; From 36296b06cd50e790d1769bb1299670b5c83ba3a7 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:11 -0700 Subject: [PATCH 024/931] dt-bindings: arm: aspeed: add Facebook Fuji-data64 board Document the new compatibles used on Meta/Facebook Fuji-data64 board. Signed-off-by: Tao Ren Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250728055618.61616-10-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 5a01e2f4ce20..e06a2e75e00d 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -85,6 +85,7 @@ properties: - facebook,cloudripper-bmc - facebook,elbert-bmc - facebook,fuji-bmc + - facebook,fuji-data64-bmc - facebook,greatlakes-bmc - facebook,harma-bmc - facebook,minerva-cmc From 1bc26258369e020d27ef11d1efd7ff82b0a9192f Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:12 -0700 Subject: [PATCH 025/931] ARM: dts: aspeed: Add Facebook Fuji-data64 (AST2600) Board Introduce fuji-data64.dts to extend Meta/Facebook Fuji BMC's data0 partition without breaking the existing users. Fuji-data64.dts is copied from fuji.dts with below changes: - updating model/compatible strings. - updating FMC flash0' data0 partition to 64MB. - removing mac3. Signed-off-by: Tao Ren Link: https://patch.msgid.link/20250728055618.61616-11-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed-bmc-facebook-fuji-data64.dts | 1256 +++++++++++++++++ 2 files changed, 1257 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji-data64.dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index 0c63297bf13b..5c447533f474 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-catalina.dtb \ aspeed-bmc-facebook-cmm.dtb \ aspeed-bmc-facebook-elbert.dtb \ + aspeed-bmc-facebook-fuji-data64.dtb \ aspeed-bmc-facebook-fuji.dtb \ aspeed-bmc-facebook-galaxy100.dtb \ aspeed-bmc-facebook-greatlakes.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji-data64.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji-data64.dts new file mode 100644 index 000000000000..aa9576d8ab56 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji-data64.dts @@ -0,0 +1,1256 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2020 Facebook Inc. + +/dts-v1/; + +#include +#include "ast2600-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Fuji BMC (64MB Datastore)"; + compatible = "facebook,fuji-data64-bmc", "aspeed,ast2600"; + + aliases { + /* + * PCA9548 (2-0070) provides 8 channels connecting to + * SCM (System Controller Module). + */ + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + + /* + * PCA9548 (8-0070) provides 8 channels connecting to + * SMB (Switch Main Board). + */ + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + + /* + * PCA9548 (11-0077) provides 8 channels connecting to + * SMB (Switch Main Board). + */ + i2c40 = &imux40; + i2c41 = &imux41; + i2c42 = &imux42; + i2c43 = &imux43; + i2c44 = &imux44; + i2c45 = &imux45; + i2c46 = &imux46; + i2c47 = &imux47; + + /* + * PCA9548 (24-0071) provides 8 channels connecting to + * PDB-Left. + */ + i2c48 = &imux48; + i2c49 = &imux49; + i2c50 = &imux50; + i2c51 = &imux51; + i2c52 = &imux52; + i2c53 = &imux53; + i2c54 = &imux54; + i2c55 = &imux55; + + /* + * PCA9548 (25-0072) provides 8 channels connecting to + * PDB-Right. + */ + i2c56 = &imux56; + i2c57 = &imux57; + i2c58 = &imux58; + i2c59 = &imux59; + i2c60 = &imux60; + i2c61 = &imux61; + i2c62 = &imux62; + i2c63 = &imux63; + + /* + * PCA9548 (26-0076) provides 8 channels connecting to + * FCM1. + */ + i2c64 = &imux64; + i2c65 = &imux65; + i2c66 = &imux66; + i2c67 = &imux67; + i2c68 = &imux68; + i2c69 = &imux69; + i2c70 = &imux70; + i2c71 = &imux71; + + /* + * PCA9548 (27-0076) provides 8 channels connecting to + * FCM2. + */ + i2c72 = &imux72; + i2c73 = &imux73; + i2c74 = &imux74; + i2c75 = &imux75; + i2c76 = &imux76; + i2c77 = &imux77; + i2c78 = &imux78; + i2c79 = &imux79; + + /* + * PCA9548 (40-0076) provides 8 channels connecting to + * PIM1. + */ + i2c80 = &imux80; + i2c81 = &imux81; + i2c82 = &imux82; + i2c83 = &imux83; + i2c84 = &imux84; + i2c85 = &imux85; + i2c86 = &imux86; + i2c87 = &imux87; + + /* + * PCA9548 (41-0076) provides 8 channels connecting to + * PIM2. + */ + i2c88 = &imux88; + i2c89 = &imux89; + i2c90 = &imux90; + i2c91 = &imux91; + i2c92 = &imux92; + i2c93 = &imux93; + i2c94 = &imux94; + i2c95 = &imux95; + + /* + * PCA9548 (42-0076) provides 8 channels connecting to + * PIM3. + */ + i2c96 = &imux96; + i2c97 = &imux97; + i2c98 = &imux98; + i2c99 = &imux99; + i2c100 = &imux100; + i2c101 = &imux101; + i2c102 = &imux102; + i2c103 = &imux103; + + /* + * PCA9548 (43-0076) provides 8 channels connecting to + * PIM4. + */ + i2c104 = &imux104; + i2c105 = &imux105; + i2c106 = &imux106; + i2c107 = &imux107; + i2c108 = &imux108; + i2c109 = &imux109; + i2c110 = &imux110; + i2c111 = &imux111; + + /* + * PCA9548 (44-0076) provides 8 channels connecting to + * PIM5. + */ + i2c112 = &imux112; + i2c113 = &imux113; + i2c114 = &imux114; + i2c115 = &imux115; + i2c116 = &imux116; + i2c117 = &imux117; + i2c118 = &imux118; + i2c119 = &imux119; + + /* + * PCA9548 (45-0076) provides 8 channels connecting to + * PIM6. + */ + i2c120 = &imux120; + i2c121 = &imux121; + i2c122 = &imux122; + i2c123 = &imux123; + i2c124 = &imux124; + i2c125 = &imux125; + i2c126 = &imux126; + i2c127 = &imux127; + + /* + * PCA9548 (46-0076) provides 8 channels connecting to + * PIM7. + */ + i2c128 = &imux128; + i2c129 = &imux129; + i2c130 = &imux130; + i2c131 = &imux131; + i2c132 = &imux132; + i2c133 = &imux133; + i2c134 = &imux134; + i2c135 = &imux135; + + /* + * PCA9548 (47-0076) provides 8 channels connecting to + * PIM8. + */ + i2c136 = &imux136; + i2c137 = &imux137; + i2c138 = &imux138; + i2c139 = &imux139; + i2c140 = &imux140; + i2c141 = &imux141; + i2c142 = &imux142; + i2c143 = &imux143; + }; + + spi_gpio: spi { + num-chipselects = <3>; + cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>, + <0>, /* device reg=<1> does not exist */ + <&gpio0 ASPEED_GPIO(X, 2) GPIO_ACTIVE_HIGH>; + + eeprom@2 { + compatible = "atmel,at93c46d"; + spi-max-frequency = <250000>; + data-size = <16>; + spi-cs-high; + reg = <2>; + }; + }; +}; + +&fmc { + flash@0 { + /delete-node/partitions; +#include "facebook-bmc-flash-layout-128-data64.dtsi" + }; +}; + +&i2c0 { + multi-master; + bus-frequency = <1000000>; +}; + +&i2c2 { + /* + * PCA9548 (2-0070) provides 8 channels connecting to SCM (System + * Controller Module). + */ + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + adm1278@10 { + compatible = "adi,adm1278"; + reg = <0x10>; + shunt-resistor-micro-ohms = <1500>; + }; + }; + + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c8 { + /* + * PCA9548 (8-0070) provides 8 channels connecting to SMB (Switch + * Main Board). + */ + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + imux48: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux49: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux50: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + lp5012@14 { + compatible = "ti,lp5012"; + reg = <0x14>; + #address-cells = <1>; + #size-cells = <0>; + + multi-led@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + color = ; + function = LED_FUNCTION_ACTIVITY; + label = "sys"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + + multi-led@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + color = ; + function = LED_FUNCTION_ACTIVITY; + label = "fan"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + + multi-led@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + color = ; + function = LED_FUNCTION_ACTIVITY; + label = "psu"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + + multi-led@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + color = ; + function = LED_FUNCTION_ACTIVITY; + label = "smb"; + + led@0 { + reg = <0>; + color = ; + }; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; + }; + }; + + imux51: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux52: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux53: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux54: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux55: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + i2c-mux@72 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72>; + i2c-mux-idle-disconnect; + + imux56: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux57: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux58: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux59: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux60: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux61: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux62: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux63: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + i2c-mux@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux64: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux65: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux66: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux67: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + adm1278@10 { + compatible = "adi,adm1278"; + reg = <0x10>; + shunt-resistor-micro-ohms = <250>; + }; + }; + + imux68: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux69: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux70: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux71: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + i2c-mux@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux72: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux73: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux74: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux75: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + adm1278@10 { + compatible = "adi,adm1278"; + reg = <0x10>; + shunt-resistor-micro-ohms = <250>; + }; + }; + + imux76: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux77: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux78: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux79: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux28: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux29: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux30: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux31: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + }; +}; + +&i2c11 { + status = "okay"; + + /* + * PCA9548 (11-0077) provides 8 channels connecting to SMB (Switch + * Main Board). + */ + i2c-mux@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + imux40: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + i2c-mux@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux80: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux81: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux82: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux83: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux84: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux85: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux86: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux87: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux41: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + i2c-mux@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux88: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux89: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux90: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux91: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux92: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux93: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux94: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux95: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux42: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + i2c-mux@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux96: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux97: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux98: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux99: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux100: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux101: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux102: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux103: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux43: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + i2c-mux@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux104: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux105: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux106: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux107: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux108: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux109: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux110: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux111: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux44: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + i2c-mux@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux112: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux113: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux114: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux115: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux116: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux117: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux118: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux119: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux45: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + i2c-mux@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux120: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux121: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux122: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux123: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux124: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux125: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux126: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux127: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux46: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + i2c-mux@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux128: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux129: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux130: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux131: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux132: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux133: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux134: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux135: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + imux47: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + i2c-mux@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux136: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux137: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux138: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux139: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux140: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux141: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux142: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux143: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + }; + + }; +}; + +&ehci1 { + status = "okay"; +}; + +&mdio1 { + status = "okay"; + + ethphy3: ethernet-phy@13 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0d>; + }; +}; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + status = "okay"; + + non-removable; + max-frequency = <25000000>; + bus-width = <4>; +}; From b0f294fdfc3e472839a9bc0dc91f2322e27e38ef Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:13 -0700 Subject: [PATCH 026/931] ARM: dts: aspeed: facebook-fuji: Include facebook-fuji-data64.dts Include "facebook-fuji-data64.dts" in facebook-fuji dts to avoid duplicated code. Fuji-data64 and Fuji are identical except the BMC flash layout. Signed-off-by: Tao Ren Link: https://patch.msgid.link/20250728055618.61616-12-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- .../dts/aspeed/aspeed-bmc-facebook-fuji.dts | 1253 +---------------- 1 file changed, 6 insertions(+), 1247 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts index d0331980d082..5dc2a165e441 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts @@ -1,1257 +1,16 @@ // SPDX-License-Identifier: GPL-2.0+ // Copyright (c) 2020 Facebook Inc. -/dts-v1/; - -#include -#include "ast2600-facebook-netbmc-common.dtsi" +#include "aspeed-bmc-facebook-fuji-data64.dts" / { model = "Facebook Fuji BMC"; compatible = "facebook,fuji-bmc", "aspeed,ast2600"; +}; - aliases { - /* - * PCA9548 (2-0070) provides 8 channels connecting to - * SCM (System Controller Module). - */ - i2c16 = &imux16; - i2c17 = &imux17; - i2c18 = &imux18; - i2c19 = &imux19; - i2c20 = &imux20; - i2c21 = &imux21; - i2c22 = &imux22; - i2c23 = &imux23; - - /* - * PCA9548 (8-0070) provides 8 channels connecting to - * SMB (Switch Main Board). - */ - i2c24 = &imux24; - i2c25 = &imux25; - i2c26 = &imux26; - i2c27 = &imux27; - i2c28 = &imux28; - i2c29 = &imux29; - i2c30 = &imux30; - i2c31 = &imux31; - - /* - * PCA9548 (11-0077) provides 8 channels connecting to - * SMB (Switch Main Board). - */ - i2c40 = &imux40; - i2c41 = &imux41; - i2c42 = &imux42; - i2c43 = &imux43; - i2c44 = &imux44; - i2c45 = &imux45; - i2c46 = &imux46; - i2c47 = &imux47; - - /* - * PCA9548 (24-0071) provides 8 channels connecting to - * PDB-Left. - */ - i2c48 = &imux48; - i2c49 = &imux49; - i2c50 = &imux50; - i2c51 = &imux51; - i2c52 = &imux52; - i2c53 = &imux53; - i2c54 = &imux54; - i2c55 = &imux55; - - /* - * PCA9548 (25-0072) provides 8 channels connecting to - * PDB-Right. - */ - i2c56 = &imux56; - i2c57 = &imux57; - i2c58 = &imux58; - i2c59 = &imux59; - i2c60 = &imux60; - i2c61 = &imux61; - i2c62 = &imux62; - i2c63 = &imux63; - - /* - * PCA9548 (26-0076) provides 8 channels connecting to - * FCM1. - */ - i2c64 = &imux64; - i2c65 = &imux65; - i2c66 = &imux66; - i2c67 = &imux67; - i2c68 = &imux68; - i2c69 = &imux69; - i2c70 = &imux70; - i2c71 = &imux71; - - /* - * PCA9548 (27-0076) provides 8 channels connecting to - * FCM2. - */ - i2c72 = &imux72; - i2c73 = &imux73; - i2c74 = &imux74; - i2c75 = &imux75; - i2c76 = &imux76; - i2c77 = &imux77; - i2c78 = &imux78; - i2c79 = &imux79; - - /* - * PCA9548 (40-0076) provides 8 channels connecting to - * PIM1. - */ - i2c80 = &imux80; - i2c81 = &imux81; - i2c82 = &imux82; - i2c83 = &imux83; - i2c84 = &imux84; - i2c85 = &imux85; - i2c86 = &imux86; - i2c87 = &imux87; - - /* - * PCA9548 (41-0076) provides 8 channels connecting to - * PIM2. - */ - i2c88 = &imux88; - i2c89 = &imux89; - i2c90 = &imux90; - i2c91 = &imux91; - i2c92 = &imux92; - i2c93 = &imux93; - i2c94 = &imux94; - i2c95 = &imux95; - - /* - * PCA9548 (42-0076) provides 8 channels connecting to - * PIM3. - */ - i2c96 = &imux96; - i2c97 = &imux97; - i2c98 = &imux98; - i2c99 = &imux99; - i2c100 = &imux100; - i2c101 = &imux101; - i2c102 = &imux102; - i2c103 = &imux103; - - /* - * PCA9548 (43-0076) provides 8 channels connecting to - * PIM4. - */ - i2c104 = &imux104; - i2c105 = &imux105; - i2c106 = &imux106; - i2c107 = &imux107; - i2c108 = &imux108; - i2c109 = &imux109; - i2c110 = &imux110; - i2c111 = &imux111; - - /* - * PCA9548 (44-0076) provides 8 channels connecting to - * PIM5. - */ - i2c112 = &imux112; - i2c113 = &imux113; - i2c114 = &imux114; - i2c115 = &imux115; - i2c116 = &imux116; - i2c117 = &imux117; - i2c118 = &imux118; - i2c119 = &imux119; - - /* - * PCA9548 (45-0076) provides 8 channels connecting to - * PIM6. - */ - i2c120 = &imux120; - i2c121 = &imux121; - i2c122 = &imux122; - i2c123 = &imux123; - i2c124 = &imux124; - i2c125 = &imux125; - i2c126 = &imux126; - i2c127 = &imux127; - - /* - * PCA9548 (46-0076) provides 8 channels connecting to - * PIM7. - */ - i2c128 = &imux128; - i2c129 = &imux129; - i2c130 = &imux130; - i2c131 = &imux131; - i2c132 = &imux132; - i2c133 = &imux133; - i2c134 = &imux134; - i2c135 = &imux135; - - /* - * PCA9548 (47-0076) provides 8 channels connecting to - * PIM8. - */ - i2c136 = &imux136; - i2c137 = &imux137; - i2c138 = &imux138; - i2c139 = &imux139; - i2c140 = &imux140; - i2c141 = &imux141; - i2c142 = &imux142; - i2c143 = &imux143; - }; - - spi_gpio: spi { - num-chipselects = <3>; - cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>, - <0>, /* device reg=<1> does not exist */ - <&gpio0 ASPEED_GPIO(X, 2) GPIO_ACTIVE_HIGH>; - - eeprom@2 { - compatible = "atmel,at93c46d"; - spi-max-frequency = <250000>; - data-size = <16>; - spi-cs-high; - reg = <2>; - }; +&fmc { + flash@0 { + /delete-node/partitions; +#include "facebook-bmc-flash-layout-128.dtsi" }; }; - -&i2c0 { - multi-master; - bus-frequency = <1000000>; -}; - -&i2c2 { - /* - * PCA9548 (2-0070) provides 8 channels connecting to SCM (System - * Controller Module). - */ - i2c-mux@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux16: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - adm1278@10 { - compatible = "adi,adm1278"; - reg = <0x10>; - shunt-resistor-micro-ohms = <1500>; - }; - }; - - imux17: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux18: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux19: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux20: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux21: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux22: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux23: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&i2c8 { - /* - * PCA9548 (8-0070) provides 8 channels connecting to SMB (Switch - * Main Board). - */ - i2c-mux@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - i2c-mux-idle-disconnect; - - imux24: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - i2c-mux@71 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - i2c-mux-idle-disconnect; - - imux48: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux49: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux50: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - lp5012@14 { - compatible = "ti,lp5012"; - reg = <0x14>; - #address-cells = <1>; - #size-cells = <0>; - - multi-led@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - color = ; - function = LED_FUNCTION_ACTIVITY; - label = "sys"; - - led@0 { - reg = <0>; - color = ; - }; - - led@1 { - reg = <1>; - color = ; - }; - - led@2 { - reg = <2>; - color = ; - }; - }; - - multi-led@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - color = ; - function = LED_FUNCTION_ACTIVITY; - label = "fan"; - - led@0 { - reg = <0>; - color = ; - }; - - led@1 { - reg = <1>; - color = ; - }; - - led@2 { - reg = <2>; - color = ; - }; - }; - - multi-led@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - color = ; - function = LED_FUNCTION_ACTIVITY; - label = "psu"; - - led@0 { - reg = <0>; - color = ; - }; - - led@1 { - reg = <1>; - color = ; - }; - - led@2 { - reg = <2>; - color = ; - }; - }; - - multi-led@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - color = ; - function = LED_FUNCTION_ACTIVITY; - label = "smb"; - - led@0 { - reg = <0>; - color = ; - }; - - led@1 { - reg = <1>; - color = ; - }; - - led@2 { - reg = <2>; - color = ; - }; - }; - }; - }; - - imux51: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux52: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux53: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux54: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux55: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux25: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - i2c-mux@72 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x72>; - i2c-mux-idle-disconnect; - - imux56: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux57: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux58: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux59: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux60: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux61: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux62: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux63: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux26: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - i2c-mux@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux64: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux65: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux66: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux67: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - adm1278@10 { - compatible = "adi,adm1278"; - reg = <0x10>; - shunt-resistor-micro-ohms = <250>; - }; - }; - - imux68: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux69: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux70: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux71: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux27: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - i2c-mux@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux72: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux73: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux74: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux75: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - adm1278@10 { - compatible = "adi,adm1278"; - reg = <0x10>; - shunt-resistor-micro-ohms = <250>; - }; - }; - - imux76: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux77: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux78: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux79: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux28: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux29: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux30: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux31: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - - }; -}; - -&i2c11 { - status = "okay"; - - /* - * PCA9548 (11-0077) provides 8 channels connecting to SMB (Switch - * Main Board). - */ - i2c-mux@77 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x77>; - i2c-mux-idle-disconnect; - - imux40: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - i2c-mux@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux80: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux81: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux82: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux83: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux84: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux85: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux86: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux87: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux41: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - i2c-mux@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux88: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux89: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux90: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux91: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux92: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux93: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux94: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux95: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux42: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - i2c-mux@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux96: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux97: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux98: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux99: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux100: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux101: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux102: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux103: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux43: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - i2c-mux@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux104: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux105: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux106: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux107: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux108: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux109: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux110: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux111: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux44: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - - i2c-mux@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux112: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux113: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux114: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux115: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux116: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux117: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux118: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux119: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux45: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - - i2c-mux@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux120: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux121: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux122: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux123: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux124: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux125: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux126: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux127: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux46: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - - i2c-mux@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux128: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux129: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux130: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux131: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux132: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux133: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux134: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux135: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - imux47: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - - i2c-mux@76 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x76>; - i2c-mux-idle-disconnect; - - imux136: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - imux137: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - imux138: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - imux139: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - imux140: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - imux141: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - imux142: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - imux143: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - - }; - - }; -}; - -&ehci1 { - status = "okay"; -}; - -&mdio1 { - status = "okay"; - - ethphy3: ethernet-phy@13 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x0d>; - }; -}; - -&mac3 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <ðphy3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii4_default>; -}; - -&emmc_controller { - status = "okay"; -}; - -&emmc { - status = "okay"; - - non-removable; - max-frequency = <25000000>; - bus-width = <4>; -}; From 0ae11080995f30cfb8362d5680e361da04fa6f79 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:14 -0700 Subject: [PATCH 027/931] dt-bindings: arm: aspeed: add Facebook Darwin board Document the new compatibles used on Meta/Facebook Darwin board. Signed-off-by: Tao Ren Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250728055618.61616-13-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index e06a2e75e00d..b3c9d3310d57 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -83,6 +83,7 @@ properties: - facebook,bletchley-bmc - facebook,catalina-bmc - facebook,cloudripper-bmc + - facebook,darwin-bmc - facebook,elbert-bmc - facebook,fuji-bmc - facebook,fuji-data64-bmc From 88950abacd5b9b8215125609dcf9449d8031417a Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Sun, 27 Jul 2025 22:56:15 -0700 Subject: [PATCH 028/931] ARM: dts: aspeed: Add Facebook Darwin (AST2600) BMC Add initial device tree for the Meta (Facebook) Darwin AST2600 BMC. Darwin is Meta's rack switch platform with an AST2600 BMC integrated for health monitoring purpose. Signed-off-by: Tao Ren Link: https://patch.msgid.link/20250728055618.61616-14-rentao.bupt@gmail.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../dts/aspeed/aspeed-bmc-facebook-darwin.dts | 72 +++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-darwin.dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index 5c447533f474..8062c685f7e8 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -20,6 +20,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-bletchley.dtb \ aspeed-bmc-facebook-catalina.dtb \ aspeed-bmc-facebook-cmm.dtb \ + aspeed-bmc-facebook-darwin.dtb \ aspeed-bmc-facebook-elbert.dtb \ aspeed-bmc-facebook-fuji-data64.dtb \ aspeed-bmc-facebook-fuji.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-darwin.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-darwin.dts new file mode 100644 index 000000000000..58c107a1b6cf --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-darwin.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2021 Facebook Inc. + +/dts-v1/; + +#include "ast2600-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Darwin BMC"; + compatible = "facebook,darwin-bmc", "aspeed,ast2600"; + + aliases { + serial0 = &uart5; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = &uart5; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; + }; + + spi_gpio: spi { + num-chipselects = <1>; + cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>; + }; +}; + +&i2c0 { + eeprom@50 { + compatible = "atmel,24c512"; + reg = <0x50>; + }; +}; + +&adc0 { + status = "okay"; + + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + status = "okay"; + + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + status = "okay"; + + non-removable; + max-frequency = <25000000>; + bus-width = <4>; +}; From 3ca621af06072aeffbaf845a407e5ff6e22c79b4 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 31 Jul 2025 17:12:18 -0500 Subject: [PATCH 029/931] ARM: dts: aspeed: Drop "no-gpio-delays" The "no-gpios-delays" property only applies to the "fsi-master-gpio" binding and not the "aspeed,ast2[45]00-cf-fsi-master" binding. It doesn't really make sense either as the timing is controlled by the offloaded firmware. Signed-off-by: Rob Herring (Arm) Acked-by: Eddie James Link: https://patch.msgid.link/20250731-dt-fsi-cleanups-v1-1-e7b695a29fc3@kernel.org Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts | 1 - arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts | 1 - arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts | 1 - 3 files changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts index 78a5656ef75d..f42254ba6aeb 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts @@ -57,7 +57,6 @@ fsi: gpio-fsi { compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; #address-cells = <2>; #size-cells = <0>; - no-gpio-delays; memory-region = <&coldfire_memory>; aspeed,sram = <&sram>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts index 1a7c61750d0d..0a67790f5ad0 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts @@ -80,7 +80,6 @@ fsi: gpio-fsi { compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; #address-cells = <2>; #size-cells = <0>; - no-gpio-delays; memory-region = <&coldfire_memory>; aspeed,sram = <&sram>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts index e6b383f6e977..96b2930017c5 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts @@ -71,7 +71,6 @@ fsi: gpio-fsi { compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; #address-cells = <2>; #size-cells = <0>; - no-gpio-delays; memory-region = <&coldfire_memory>; aspeed,sram = <&sram>; From b1ccd095b8ac4c843cf6bf15d9f6aadd8ae1195d Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 31 Jul 2025 17:12:19 -0500 Subject: [PATCH 030/931] ARM: dts: aspeed: Drop "fsi-master" compatibles The "fsi-master" compatible has been used inconsistently on FSI masters. It doesn't have any real use or meaning, so it's easier to drop it everywhere than add it where missing. It is also not documented by any schemas (only .txt bindings). Signed-off-by: Rob Herring (Arm) Acked-by: Eddie James Link: https://patch.msgid.link/20250731-dt-fsi-cleanups-v1-2-e7b695a29fc3@kernel.org [arj: Drop hunk affecting removed swift platform] Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts | 2 +- arch/arm/boot/dts/aspeed/aspeed-bmc-opp-lanyang.dts | 2 +- arch/arm/boot/dts/aspeed/aspeed-bmc-opp-mowgli.dts | 2 +- arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts | 2 +- arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts | 2 +- arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts | 2 +- arch/arm/boot/dts/aspeed/aspeed-bmc-opp-witherspoon.dts | 2 +- arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts | 2 +- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 4 ++-- 9 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts index f42254ba6aeb..79c6919b3570 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts @@ -54,7 +54,7 @@ video_engine_memory: jpegbuffer { }; fsi: gpio-fsi { - compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; + compatible = "aspeed,ast2500-cf-fsi-master"; #address-cells = <2>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-lanyang.dts index 65b2208f5a90..9f2ad551255d 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-lanyang.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-lanyang.dts @@ -63,7 +63,7 @@ sys_err { }; fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; + compatible = "fsi-master-gpio"; #address-cells = <2>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-mowgli.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-mowgli.dts index 31ff19ef87a0..6c8b966ffccc 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-mowgli.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-mowgli.dts @@ -165,7 +165,7 @@ fan4 { }; fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; + compatible = "fsi-master-gpio"; #address-cells = <2>; #size-cells = <0>; no-gpio-delays; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts index 0a67790f5ad0..ce6d30ddf07c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-nicole.dts @@ -77,7 +77,7 @@ attention { }; fsi: gpio-fsi { - compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; + compatible = "aspeed,ast2500-cf-fsi-master"; #address-cells = <2>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts index 123da82c04d5..a1d3e046d4a2 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts @@ -55,7 +55,7 @@ identify { }; fsi: gpio-fsi { - compatible = "aspeed,ast2400-cf-fsi-master", "fsi-master"; + compatible = "aspeed,ast2400-cf-fsi-master"; #address-cells = <2>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts index 96b2930017c5..a0263d969e51 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-romulus.dts @@ -68,7 +68,7 @@ power { }; fsi: gpio-fsi { - compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; + compatible = "aspeed,ast2500-cf-fsi-master"; #address-cells = <2>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-witherspoon.dts index 8b1e82c8cdfe..89907b628b65 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-witherspoon.dts @@ -173,7 +173,7 @@ power-button { }; fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; + compatible = "fsi-master-gpio"; #address-cells = <2>; #size-cells = <0>; no-gpio-delays; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts index 6ac7b0aa6e54..627c91f178e6 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts @@ -96,7 +96,7 @@ hdd_fault { }; fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; + compatible = "fsi-master-gpio"; #address-cells = <2>; #size-cells = <0>; no-gpio-delays; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 8ed715bd53aa..acdb6ae74b27 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -847,7 +847,7 @@ i2c: bus@1e78a000 { fsim0: fsi@1e79b000 { #interrupt-cells = <1>; - compatible = "aspeed,ast2600-fsi-master", "fsi-master"; + compatible = "aspeed,ast2600-fsi-master"; reg = <0x1e79b000 0x94>; interrupts = ; pinctrl-names = "default"; @@ -859,7 +859,7 @@ fsim0: fsi@1e79b000 { fsim1: fsi@1e79b100 { #interrupt-cells = <1>; - compatible = "aspeed,ast2600-fsi-master", "fsi-master"; + compatible = "aspeed,ast2600-fsi-master"; reg = <0x1e79b100 0x94>; interrupts = ; pinctrl-names = "default"; From 608e2990e67c0e367cc87a86301f2e57b9fffc7e Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 31 Jul 2025 17:12:20 -0500 Subject: [PATCH 031/931] ARM: dts: aspeed: Add missing "ibm,spi-fsi" compatibles The "ibm,spi-fsi" compatible is missing or incorrect in various nodes. The incorrect cases used the "ibm,fsi2spi" compatible by mistake which is the parent node of the actual SPI controller nodes. Signed-off-by: Rob Herring (Arm) Acked-by: Eddie James Link: https://patch.msgid.link/20250731-dt-fsi-cleanups-v1-3-e7b695a29fc3@kernel.org Signed-off-by: Andrew Jeffery --- .../dts/aspeed/aspeed-bmc-ibm-everest.dts | 24 ++++++++++++------- .../arm/boot/dts/aspeed/ibm-power10-dual.dtsi | 12 ++++++---- .../arm/boot/dts/aspeed/ibm-power10-quad.dtsi | 12 ++++++---- 3 files changed, 32 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts index 4d9e2cd11f44..9f144f527f03 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts @@ -2808,6 +2808,7 @@ fsi2spi@1c00 { #size-cells = <0>; cfam4_spi0: spi@0 { + compatible = "ibm,spi-fsi"; reg = <0x0>; #address-cells = <1>; #size-cells = <0>; @@ -2824,6 +2825,7 @@ eeprom@0 { }; cfam4_spi1: spi@20 { + compatible = "ibm,spi-fsi"; reg = <0x20>; #address-cells = <1>; #size-cells = <0>; @@ -2840,8 +2842,8 @@ eeprom@0 { }; cfam4_spi2: spi@40 { + compatible = "ibm,spi-fsi"; reg = <0x40>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -2857,8 +2859,8 @@ eeprom@0 { }; cfam4_spi3: spi@60 { + compatible = "ibm,spi-fsi"; reg = <0x60>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -3181,6 +3183,7 @@ fsi2spi@1c00 { #size-cells = <0>; cfam5_spi0: spi@0 { + compatible = "ibm,spi-fsi"; reg = <0x0>; #address-cells = <1>; #size-cells = <0>; @@ -3197,6 +3200,7 @@ eeprom@0 { }; cfam5_spi1: spi@20 { + compatible = "ibm,spi-fsi"; reg = <0x20>; #address-cells = <1>; #size-cells = <0>; @@ -3213,8 +3217,8 @@ eeprom@0 { }; cfam5_spi2: spi@40 { + compatible = "ibm,spi-fsi"; reg = <0x40>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -3230,8 +3234,8 @@ eeprom@0 { }; cfam5_spi3: spi@60 { + compatible = "ibm,spi-fsi"; reg = <0x60>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -3554,6 +3558,7 @@ fsi2spi@1c00 { #size-cells = <0>; cfam6_spi0: spi@0 { + compatible = "ibm,spi-fsi"; reg = <0x0>; #address-cells = <1>; #size-cells = <0>; @@ -3570,6 +3575,7 @@ eeprom@0 { }; cfam6_spi1: spi@20 { + compatible = "ibm,spi-fsi"; reg = <0x20>; #address-cells = <1>; #size-cells = <0>; @@ -3586,8 +3592,8 @@ eeprom@0 { }; cfam6_spi2: spi@40 { + compatible = "ibm,spi-fsi"; reg = <0x40>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -3603,8 +3609,8 @@ eeprom@0 { }; cfam6_spi3: spi@60 { + compatible = "ibm,spi-fsi"; reg = <0x60>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -3927,6 +3933,7 @@ fsi2spi@1c00 { #size-cells = <0>; cfam7_spi0: spi@0 { + compatible = "ibm,spi-fsi"; reg = <0x0>; #address-cells = <1>; #size-cells = <0>; @@ -3943,6 +3950,7 @@ eeprom@0 { }; cfam7_spi1: spi@20 { + compatible = "ibm,spi-fsi"; reg = <0x20>; #address-cells = <1>; #size-cells = <0>; @@ -3959,8 +3967,8 @@ eeprom@0 { }; cfam7_spi2: spi@40 { + compatible = "ibm,spi-fsi"; reg = <0x40>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -3976,8 +3984,8 @@ eeprom@0 { }; cfam7_spi3: spi@60 { + compatible = "ibm,spi-fsi"; reg = <0x60>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi b/arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi index 07ce3b2bc62a..06fac236773f 100644 --- a/arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi +++ b/arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi @@ -82,6 +82,7 @@ fsi2spi@1c00 { #size-cells = <0>; cfam0_spi0: spi@0 { + compatible = "ibm,spi-fsi"; reg = <0x0>; #address-cells = <1>; #size-cells = <0>; @@ -98,6 +99,7 @@ eeprom@0 { }; cfam0_spi1: spi@20 { + compatible = "ibm,spi-fsi"; reg = <0x20>; #address-cells = <1>; #size-cells = <0>; @@ -114,8 +116,8 @@ eeprom@0 { }; cfam0_spi2: spi@40 { + compatible = "ibm,spi-fsi"; reg = <0x40>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -131,8 +133,8 @@ eeprom@0 { }; cfam0_spi3: spi@60 { + compatible = "ibm,spi-fsi"; reg = <0x60>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -249,6 +251,7 @@ fsi2spi@1c00 { #size-cells = <0>; cfam1_spi0: spi@0 { + compatible = "ibm,spi-fsi"; reg = <0x0>; #address-cells = <1>; #size-cells = <0>; @@ -265,6 +268,7 @@ eeprom@0 { }; cfam1_spi1: spi@20 { + compatible = "ibm,spi-fsi"; reg = <0x20>; #address-cells = <1>; #size-cells = <0>; @@ -281,8 +285,8 @@ eeprom@0 { }; cfam1_spi2: spi@40 { + compatible = "ibm,spi-fsi"; reg = <0x40>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -298,8 +302,8 @@ eeprom@0 { }; cfam1_spi3: spi@60 { + compatible = "ibm,spi-fsi"; reg = <0x60>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi b/arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi index 57494c744b5d..9501f66d0030 100644 --- a/arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi +++ b/arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi @@ -733,6 +733,7 @@ fsi2spi@1c00 { #size-cells = <0>; cfam2_spi0: spi@0 { + compatible = "ibm,spi-fsi"; reg = <0x0>; #address-cells = <1>; #size-cells = <0>; @@ -749,6 +750,7 @@ eeprom@0 { }; cfam2_spi1: spi@20 { + compatible = "ibm,spi-fsi"; reg = <0x20>; #address-cells = <1>; #size-cells = <0>; @@ -765,8 +767,8 @@ eeprom@0 { }; cfam2_spi2: spi@40 { + compatible = "ibm,spi-fsi"; reg = <0x40>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -782,8 +784,8 @@ eeprom@0 { }; cfam2_spi3: spi@60 { + compatible = "ibm,spi-fsi"; reg = <0x60>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -1106,6 +1108,7 @@ fsi2spi@1c00 { #size-cells = <0>; cfam3_spi0: spi@0 { + compatible = "ibm,spi-fsi"; reg = <0x0>; #address-cells = <1>; #size-cells = <0>; @@ -1122,6 +1125,7 @@ eeprom@0 { }; cfam3_spi1: spi@20 { + compatible = "ibm,spi-fsi"; reg = <0x20>; #address-cells = <1>; #size-cells = <0>; @@ -1138,8 +1142,8 @@ eeprom@0 { }; cfam3_spi2: spi@40 { + compatible = "ibm,spi-fsi"; reg = <0x40>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -1155,8 +1159,8 @@ eeprom@0 { }; cfam3_spi3: spi@60 { + compatible = "ibm,spi-fsi"; reg = <0x60>; - compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; From 5bf96232edfaa83984d7637f83dae75a9a9670eb Mon Sep 17 00:00:00 2001 From: Tan Siewert Date: Sun, 3 Aug 2025 17:19:37 +0200 Subject: [PATCH 032/931] ARM: dts: aspeed: e3c246d4i: convert NVMEM content to layout syntax The used bindings syntax has been deprecated and doesn't work properly anymore. Use the newer (and non-deprecated) fixed-layout approach. See commit bd912c991d2e ("dt-bindings: nvmem: layouts: add fixed-layout") for details. Signed-off-by: Tan Siewert Reviewed-by: Zev Weiss Link: https://patch.msgid.link/20250803151949.68618-1-tan@siewert.io Signed-off-by: Andrew Jeffery --- .../boot/dts/aspeed/aspeed-bmc-asrock-e3c246d4i.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c246d4i.dts index 93190f4e696c..3ebd80db06f9 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c246d4i.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c246d4i.dts @@ -106,11 +106,15 @@ eeprom@57 { compatible = "st,24c128", "atmel,24c128"; reg = <0x57>; pagesize = <16>; - #address-cells = <1>; - #size-cells = <1>; - eth0_macaddress: macaddress@3f80 { - reg = <0x3f80 6>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eth0_macaddress: macaddress@3f80 { + reg = <0x3f80 6>; + }; }; }; }; From 2660d172a346a5f6fabc8b4e07fb57751d0b2fd7 Mon Sep 17 00:00:00 2001 From: Tan Siewert Date: Sun, 3 Aug 2025 17:19:38 +0200 Subject: [PATCH 033/931] ARM: dts: aspeed: e3c256d4i: convert NVMEM content to layout syntax The used bindings syntax has been deprecated and doesn't work properly anymore. Use the newer (and non-deprecated) fixed-layout approach. See commit bd912c991d2e ("dt-bindings: nvmem: layouts: add fixed-layout") for details. Signed-off-by: Tan Siewert Reviewed-by: Zev Weiss Link: https://patch.msgid.link/20250803151949.68618-2-tan@siewert.io Signed-off-by: Andrew Jeffery --- .../boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts index 9d00ce9475f2..8c57a071f488 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-e3c256d4i.dts @@ -191,11 +191,15 @@ eeprom@57 { compatible = "st,24c128", "atmel,24c128"; reg = <0x57>; pagesize = <16>; - #address-cells = <1>; - #size-cells = <1>; - eth0_macaddress: macaddress@3f80 { - reg = <0x3f80 6>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eth0_macaddress: macaddress@3f80 { + reg = <0x3f80 6>; + }; }; }; }; From 1f5ab37b75afbfad686c56c010b2ba93a096ca87 Mon Sep 17 00:00:00 2001 From: Tan Siewert Date: Sun, 3 Aug 2025 17:19:39 +0200 Subject: [PATCH 034/931] ARM: dts: aspeed: romed8hm3: convert NVMEM content to layout syntax The used bindings syntax has been deprecated and doesn't work properly anymore. Use the newer (and non-deprecated) fixed-layout approach. See commit bd912c991d2e ("dt-bindings: nvmem: layouts: add fixed-layout") for details. Signed-off-by: Tan Siewert Reviewed-by: Zev Weiss Link: https://patch.msgid.link/20250803151949.68618-3-tan@siewert.io Signed-off-by: Andrew Jeffery --- .../boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts index 6dd221644dc6..e306655ce4a3 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-romed8hm3.dts @@ -134,11 +134,15 @@ eeprom@50 { compatible = "st,24c128", "atmel,24c128"; reg = <0x50>; pagesize = <16>; - #address-cells = <1>; - #size-cells = <1>; - eth0_macaddress: macaddress@3f80 { - reg = <0x3f80 6>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eth0_macaddress: macaddress@3f80 { + reg = <0x3f80 6>; + }; }; }; }; From b785b5d88cc27a521ea22b3afd85804c4c321d4a Mon Sep 17 00:00:00 2001 From: Tan Siewert Date: Sun, 3 Aug 2025 17:19:40 +0200 Subject: [PATCH 035/931] ARM: dts: aspeed: x570d4u: convert NVMEM content to layout syntax The used bindings syntax has been deprecated and doesn't work properly anymore. Use the newer (and non-deprecated) fixed-layout approach. See commit bd912c991d2e ("dt-bindings: nvmem: layouts: add fixed-layout") for details. Signed-off-by: Tan Siewert Reviewed-by: Zev Weiss Link: https://patch.msgid.link/20250803151949.68618-4-tan@siewert.io Signed-off-by: Andrew Jeffery --- .../dts/aspeed/aspeed-bmc-asrock-x570d4u.dts | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x570d4u.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x570d4u.dts index 0943e0bf1305..e61a6cb43438 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x570d4u.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-x570d4u.dts @@ -232,15 +232,19 @@ eeprom@57 { compatible = "st,24c128", "atmel,24c128"; reg = <0x57>; pagesize = <16>; - #address-cells = <1>; - #size-cells = <1>; - eth0_macaddress: macaddress@3f80 { - reg = <0x3f80 6>; - }; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - eth1_macaddress: macaddress@3f88 { - reg = <0x3f88 6>; + eth0_macaddress: macaddress@3f80 { + reg = <0x3f80 6>; + }; + + eth1_macaddress: macaddress@3f88 { + reg = <0x3f88 6>; + }; }; }; }; From 7686b441c0ad921211b0a69977bad746d18e4b33 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Jul 2025 16:23:02 +0200 Subject: [PATCH 036/931] ARM: dts: nuvoton: Use generic "ethernet" as node name Common name for Ethernet controllers is "ethernet", not "eth", also recommended by Devicetree specification in "Generic Names Recommendation". Verified lack of impact using dtx_diff. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250717142301.92548-2-krzysztof.kozlowski@linaro.org Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi | 2 +- arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi index 791090f54d8b..98c35771534e 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi @@ -134,7 +134,7 @@ mc: memory-controller@f0824000 { status = "disabled"; }; - gmac0: eth@f0802000 { + gmac0: ethernet@f0802000 { device_type = "network"; compatible = "snps,dwmac"; reg = <0xf0802000 0x2000>; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi index f42ad259636c..65fe3a180bb1 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750.dtsi @@ -44,7 +44,7 @@ timer@3fe600 { }; ahb { - gmac1: eth@f0804000 { + gmac1: ethernet@f0804000 { device_type = "network"; compatible = "snps,dwmac"; reg = <0xf0804000 0x2000>; From 91f8329e67b482faa1646609f457ea0f74b93a53 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Sun, 6 Jul 2025 18:35:51 +0300 Subject: [PATCH 037/931] arm64: dts: nuvoton: npcm845: Add pinctrl groups Add 64 missing pinctrl groups to the NPCM845 device tree source file to support additional pinmux configurations defined in the npcm845-pinctrl driver. This enhances the pinmux configuration for the NPCM845 SoC, enabling further hardware pin functionalities. Signed-off-by: Tomer Maimon Link: https://patch.msgid.link/20250706153551.2180052-1-tmaimon77@gmail.com Signed-off-by: Andrew Jeffery --- .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 649 ++++++++++++++++++ 1 file changed, 649 insertions(+) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index acd3137d2464..5be132f3fd07 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -235,5 +235,654 @@ gpio7: gpio@f0017000 { interrupts = ; gpio-ranges = <&pinctrl 0 224 32>; }; + + iox1_pins: iox1-mux { + groups = "iox1"; + function = "iox1"; + }; + iox2_pins: iox2-mux { + groups = "iox2"; + function = "iox2"; + }; + smb1d_pins: smb1d-mux { + groups = "smb1d"; + function = "smb1d"; + }; + smb2d_pins: smb2d-mux { + groups = "smb2d"; + function = "smb2d"; + }; + lkgpo1_pins: lkgpo1-mux { + groups = "lkgpo1"; + function = "lkgpo1"; + }; + lkgpo2_pins: lkgpo2-mux { + groups = "lkgpo2"; + function = "lkgpo2"; + }; + ioxh_pins: ioxh-mux { + groups = "ioxh"; + function = "ioxh"; + }; + gspi_pins: gspi-mux { + groups = "gspi"; + function = "gspi"; + }; + smb5b_pins: smb5b-mux { + groups = "smb5b"; + function = "smb5b"; + }; + smb5c_pins: smb5c-mux { + groups = "smb5c"; + function = "smb5c"; + }; + lkgpo0_pins: lkgpo0-mux { + groups = "lkgpo0"; + function = "lkgpo0"; + }; + pspi_pins: pspi-mux { + groups = "pspi"; + function = "pspi"; + }; + jm1_pins: jm1-mux { + groups = "jm1"; + function = "jm1"; + }; + jm2_pins: jm2-mux { + groups = "jm2"; + function = "jm2"; + }; + smb4b_pins: smb4b-mux { + groups = "smb4b"; + function = "smb4b"; + }; + smb4c_pins: smb4c-mux { + groups = "smb4c"; + function = "smb4c"; + }; + smb15_pins: smb15-mux { + groups = "smb15"; + function = "smb15"; + }; + smb16_pins: smb16-mux { + groups = "smb16"; + function = "smb16"; + }; + smb17_pins: smb17-mux { + groups = "smb17"; + function = "smb17"; + }; + smb18_pins: smb18-mux { + groups = "smb18"; + function = "smb18"; + }; + smb19_pins: smb19-mux { + groups = "smb19"; + function = "smb19"; + }; + smb20_pins: smb20-mux { + groups = "smb20"; + function = "smb20"; + }; + smb21_pins: smb21-mux { + groups = "smb21"; + function = "smb21"; + }; + smb22_pins: smb22-mux { + groups = "smb22"; + function = "smb22"; + }; + smb23_pins: smb23-mux { + groups = "smb23"; + function = "smb23"; + }; + smb23b_pins: smb23b-mux { + groups = "smb23b"; + function = "smb23b"; + }; + smb4d_pins: smb4d-mux { + groups = "smb4d"; + function = "smb4d"; + }; + smb14_pins: smb14-mux { + groups = "smb14"; + function = "smb14"; + }; + smb5_pins: smb5-mux { + groups = "smb5"; + function = "smb5"; + }; + smb4_pins: smb4-mux { + groups = "smb4"; + function = "smb4"; + }; + smb3_pins: smb3-mux { + groups = "smb3"; + function = "smb3"; + }; + spi0cs1_pins: spi0cs1-mux { + groups = "spi0cs1"; + function = "spi0cs1"; + }; + spi1cs0_pins: spi1cs0-mux { + groups = "spi1cs0"; + function = "spi1cs0"; + }; + spi1cs1_pins: spi1cs1-mux { + groups = "spi1cs1"; + function = "spi1cs1"; + }; + spi1cs2_pins: spi1cs2-mux { + groups = "spi1cs2"; + function = "spi1cs2"; + }; + spi1cs3_pins: spi1cs3-mux { + groups = "spi1cs3"; + function = "spi1cs3"; + }; + smb3c_pins: smb3c-mux { + groups = "smb3c"; + function = "smb3c"; + }; + smb3b_pins: smb3b-mux { + groups = "smb3b"; + function = "smb3b"; + }; + bmcuart0a_pins: bmcuart0a-mux { + groups = "bmcuart0a"; + function = "bmcuart0a"; + }; + uart1_pins: uart1-mux { + groups = "uart1"; + function = "uart1"; + }; + jtag2_pins: jtag2-mux { + groups = "jtag2"; + function = "jtag2"; + }; + bmcuart1_pins: bmcuart1-mux { + groups = "bmcuart1"; + function = "bmcuart1"; + }; + uart2_pins: uart2-mux { + groups = "uart2"; + function = "uart2"; + }; + bmcuart0b_pins: bmcuart0b-mux { + groups = "bmcuart0b"; + function = "bmcuart0b"; + }; + r1err_pins: r1err-mux { + groups = "r1err"; + function = "r1err"; + }; + r1md_pins: r1md-mux { + groups = "r1md"; + function = "r1md"; + }; + r1oen_pins: r1oen-mux { + groups = "r1oen"; + function = "r1oen"; + }; + r2oen_pins: r2oen-mux { + groups = "r2oen"; + function = "r2oen"; + }; + rmii3_pins: rmii3-mux { + groups = "rmii3"; + function = "rmii3"; + }; + r3oen_pins: r3oen-mux { + groups = "r3oen"; + function = "r3oen"; + }; + smb3d_pins: smb3d-mux { + groups = "smb3d"; + function = "smb3d"; + }; + fanin0_pins: fanin0-mux { + groups = "fanin0"; + function = "fanin0"; + }; + fanin1_pins: fanin1-mux { + groups = "fanin1"; + function = "fanin1"; + }; + fanin2_pins: fanin2-mux { + groups = "fanin2"; + function = "fanin2"; + }; + fanin3_pins: fanin3-mux { + groups = "fanin3"; + function = "fanin3"; + }; + fanin4_pins: fanin4-mux { + groups = "fanin4"; + function = "fanin4"; + }; + fanin5_pins: fanin5-mux { + groups = "fanin5"; + function = "fanin5"; + }; + fanin6_pins: fanin6-mux { + groups = "fanin6"; + function = "fanin6"; + }; + fanin7_pins: fanin7-mux { + groups = "fanin7"; + function = "fanin7"; + }; + fanin8_pins: fanin8-mux { + groups = "fanin8"; + function = "fanin8"; + }; + fanin9_pins: fanin9-mux { + groups = "fanin9"; + function = "fanin9"; + }; + fanin10_pins: fanin10-mux { + groups = "fanin10"; + function = "fanin10"; + }; + fanin11_pins: fanin11-mux { + groups = "fanin11"; + function = "fanin11"; + }; + fanin12_pins: fanin12-mux { + groups = "fanin12"; + function = "fanin12"; + }; + fanin13_pins: fanin13-mux { + groups = "fanin13"; + function = "fanin13"; + }; + fanin14_pins: fanin14-mux { + groups = "fanin14"; + function = "fanin14"; + }; + fanin15_pins: fanin15-mux { + groups = "fanin15"; + function = "fanin15"; + }; + pwm0_pins: pwm0-mux { + groups = "pwm0"; + function = "pwm0"; + }; + pwm1_pins: pwm1-mux { + groups = "pwm1"; + function = "pwm1"; + }; + pwm2_pins: pwm2-mux { + groups = "pwm2"; + function = "pwm2"; + }; + pwm3_pins: pwm3-mux { + groups = "pwm3"; + function = "pwm3"; + }; + r2_pins: r2-mux { + groups = "r2"; + function = "r2"; + }; + r2err_pins: r2err-mux { + groups = "r2err"; + function = "r2err"; + }; + r2md_pins: r2md-mux { + groups = "r2md"; + function = "r2md"; + }; + r3rxer_pins: r3rxer-mux { + groups = "r3rxer"; + function = "r3rxer"; + }; + ga20kbc_pins: ga20kbc-mux { + groups = "ga20kbc"; + function = "ga20kbc"; + }; + smb5d_pins: smb5d-mux { + groups = "smb5d"; + function = "smb5d"; + }; + lpc_pins: lpc-mux { + groups = "lpc"; + function = "lpc"; + }; + espi_pins: espi-mux { + groups = "espi"; + function = "espi"; + }; + sg1mdio_pins: sg1mdio-mux { + groups = "sg1mdio"; + function = "sg1mdio"; + }; + rg2_pins: rg2-mux { + groups = "rg2"; + function = "rg2"; + }; + ddr_pins: ddr-mux { + groups = "ddr"; + function = "ddr"; + }; + i3c0_pins: i3c0-mux { + groups = "i3c0"; + function = "i3c0"; + }; + i3c1_pins: i3c1-mux { + groups = "i3c1"; + function = "i3c1"; + }; + i3c2_pins: i3c2-mux { + groups = "i3c2"; + function = "i3c2"; + }; + i3c3_pins: i3c3-mux { + groups = "i3c3"; + function = "i3c3"; + }; + i3c4_pins: i3c4-mux { + groups = "i3c4"; + function = "i3c4"; + }; + i3c5_pins: i3c5-mux { + groups = "i3c5"; + function = "i3c5"; + }; + smb0_pins: smb0-mux { + groups = "smb0"; + function = "smb0"; + }; + smb1_pins: smb1-mux { + groups = "smb1"; + function = "smb1"; + }; + smb2_pins: smb2-mux { + groups = "smb2"; + function = "smb2"; + }; + smb2c_pins: smb2c-mux { + groups = "smb2c"; + function = "smb2c"; + }; + smb2b_pins: smb2b-mux { + groups = "smb2b"; + function = "smb2b"; + }; + smb1c_pins: smb1c-mux { + groups = "smb1c"; + function = "smb1c"; + }; + smb1b_pins: smb1b-mux { + groups = "smb1b"; + function = "smb1b"; + }; + smb8_pins: smb8-mux { + groups = "smb8"; + function = "smb8"; + }; + smb9_pins: smb9-mux { + groups = "smb9"; + function = "smb9"; + }; + smb10_pins: smb10-mux { + groups = "smb10"; + function = "smb10"; + }; + smb11_pins: smb11-mux { + groups = "smb11"; + function = "smb11"; + }; + sd1_pins: sd1-mux { + groups = "sd1"; + function = "sd1"; + }; + sd1pwr_pins: sd1pwr-mux { + groups = "sd1pwr"; + function = "sd1pwr"; + }; + pwm4_pins: pwm4-mux { + groups = "pwm4"; + function = "pwm4"; + }; + pwm5_pins: pwm5-mux { + groups = "pwm5"; + function = "pwm5"; + }; + pwm6_pins: pwm6-mux { + groups = "pwm6"; + function = "pwm6"; + }; + pwm7_pins: pwm7-mux { + groups = "pwm7"; + function = "pwm7"; + }; + pwm8_pins: pwm8-mux { + groups = "pwm8"; + function = "pwm8"; + }; + pwm9_pins: pwm9-mux { + groups = "pwm9"; + function = "pwm9"; + }; + pwm10_pins: pwm10-mux { + groups = "pwm10"; + function = "pwm10"; + }; + pwm11_pins: pwm11-mux { + groups = "pwm11"; + function = "pwm11"; + }; + mmc8_pins: mmc8-mux { + groups = "mmc8"; + function = "mmc8"; + }; + mmc_pins: mmc-mux { + groups = "mmc"; + function = "mmc"; + }; + mmcwp_pins: mmcwp-mux { + groups = "mmcwp"; + function = "mmcwp"; + }; + mmccd_pins: mmccd-mux { + groups = "mmccd"; + function = "mmccd"; + }; + mmcrst_pins: mmcrst-mux { + groups = "mmcrst"; + function = "mmcrst"; + }; + clkout_pins: clkout-mux { + groups = "clkout"; + function = "clkout"; + }; + serirq_pins: serirq-mux { + groups = "serirq"; + function = "serirq"; + }; + scipme_pins: scipme-mux { + groups = "scipme"; + function = "scipme"; + }; + smb6_pins: smb6-mux { + groups = "smb6"; + function = "smb6"; + }; + smb6b_pins: smb6b-mux { + groups = "smb6b"; + function = "smb6b"; + }; + smb6c_pins: smb6c-mux { + groups = "smb6c"; + function = "smb6c"; + }; + smb6d_pins: smb6d-mux { + groups = "smb6d"; + function = "smb6d"; + }; + smb7_pins: smb7-mux { + groups = "smb7"; + function = "smb7"; + }; + smb7b_pins: smb7b-mux { + groups = "smb7b"; + function = "smb7b"; + }; + smb7c_pins: smb7c-mux { + groups = "smb7c"; + function = "smb7c"; + }; + smb7d_pins: smb7d-mux { + groups = "smb7d"; + function = "smb7d"; + }; + spi1_pins: spi1-mux { + groups = "spi1"; + function = "spi1"; + }; + faninx_pins: faninx-mux { + groups = "faninx"; + function = "faninx"; + }; + r1_pins: r1-mux { + groups = "r1"; + function = "r1"; + }; + spi3_pins: spi3-mux { + groups = "spi3"; + function = "spi3"; + }; + spi3cs1_pins: spi3cs1-mux { + groups = "spi3cs1"; + function = "spi3cs1"; + }; + spi3quad_pins: spi3quad-mux { + groups = "spi3quad"; + function = "spi3quad"; + }; + spi3cs2_pins: spi3cs2-mux { + groups = "spi3cs2"; + function = "spi3cs2"; + }; + spi3cs3_pins: spi3cs3-mux { + groups = "spi3cs3"; + function = "spi3cs3"; + }; + nprd_smi_pins: nprd-smi-mux { + groups = "nprd_smi"; + function = "nprd_smi"; + }; + smi_pins: smi-mux { + groups = "smi"; + function = "smi"; + }; + smb0b_pins: smb0b-mux { + groups = "smb0b"; + function = "smb0b"; + }; + smb0c_pins: smb0c-mux { + groups = "smb0c"; + function = "smb0c"; + }; + smb0den_pins: smb0den-mux { + groups = "smb0den"; + function = "smb0den"; + }; + smb0d_pins: smb0d-mux { + groups = "smb0d"; + function = "smb0d"; + }; + ddc_pins: ddc-mux { + groups = "ddc"; + function = "ddc"; + }; + rg2mdio_pins: rg2mdio-mux { + groups = "rg2mdio"; + function = "rg2mdio"; + }; + wdog1_pins: wdog1-mux { + groups = "wdog1"; + function = "wdog1"; + }; + wdog2_pins: wdog2-mux { + groups = "wdog2"; + function = "wdog2"; + }; + smb12_pins: smb12-mux { + groups = "smb12"; + function = "smb12"; + }; + smb13_pins: smb13-mux { + groups = "smb13"; + function = "smb13"; + }; + spix_pins: spix-mux { + groups = "spix"; + function = "spix"; + }; + spixcs1_pins: spixcs1-mux { + groups = "spixcs1"; + function = "spixcs1"; + }; + clkreq_pins: clkreq-mux { + groups = "clkreq"; + function = "clkreq"; + }; + hgpio0_pins: hgpio0-mux { + groups = "hgpio0"; + function = "hgpio0"; + }; + hgpio1_pins: hgpio1-mux { + groups = "hgpio1"; + function = "hgpio1"; + }; + hgpio2_pins: hgpio2-mux { + groups = "hgpio2"; + function = "hgpio2"; + }; + hgpio3_pins: hgpio3-mux { + groups = "hgpio3"; + function = "hgpio3"; + }; + hgpio4_pins: hgpio4-mux { + groups = "hgpio4"; + function = "hgpio4"; + }; + hgpio5_pins: hgpio5-mux { + groups = "hgpio5"; + function = "hgpio5"; + }; + hgpio6_pins: hgpio6-mux { + groups = "hgpio6"; + function = "hgpio6"; + }; + hgpio7_pins: hgpio7-mux { + groups = "hgpio7"; + function = "hgpio7"; + }; + bu4_pins: bu4-mux { + groups = "bu4"; + function = "bu4"; + }; + bu4b_pins: bu4b-mux { + groups = "bu4b"; + function = "bu4b"; + }; + bu5_pins: bu5-mux { + groups = "bu5"; + function = "bu5"; + }; + bu5b_pins: bu5b-mux { + groups = "bu5b"; + function = "bu5b"; + }; + bu6_pins: bu6-mux { + groups = "bu6"; + function = "bu6"; + }; + gpo187_pins: gpo187-mux { + groups = "gpo187"; + function = "gpo187"; + }; }; }; From 2e6028f8faf07e896ea4c2603adb4b06e8cb92fa Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Sun, 6 Jul 2025 16:42:06 +0300 Subject: [PATCH 038/931] arm64: dts: nuvoton: combine NPCM845 reset and clk nodes Combine the NPCM845 reset and clock controller nodes into a single node with compatible "nuvoton,npcm845-reset" in nuvoton-common-npcm8xx.dtsi, using the auxiliary device framework to provide clock functionality. Update the register range to 0xC4 to cover the shared reset and clock registers at 0xf0801000. Remove the separate nuvoton,npcm845-clk node, as the reset driver now handles clocks via an auxiliary device. Signed-off-by: Tomer Maimon Link: https://patch.msgid.link/20250706134207.2168184-2-tmaimon77@gmail.com Signed-off-by: Andrew Jeffery --- .../boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index 5be132f3fd07..400d5c5b71ac 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -42,17 +42,12 @@ ahb { interrupt-parent = <&gic>; ranges; - rstc: reset-controller@f0801000 { + clk: rstc: reset-controller@f0801000 { compatible = "nuvoton,npcm845-reset"; - reg = <0x0 0xf0801000 0x0 0x78>; - #reset-cells = <2>; + reg = <0x0 0xf0801000 0x0 0xC4>; nuvoton,sysgcr = <&gcr>; - }; - - clk: clock-controller@f0801000 { - compatible = "nuvoton,npcm845-clk"; + #reset-cells = <2>; #clock-cells = <1>; - reg = <0x0 0xf0801000 0x0 0x1000>; }; apb { From 13587befb34ffa5d605196494c243420e045f28e Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Sun, 6 Jul 2025 16:42:07 +0300 Subject: [PATCH 039/931] arm64: dts: nuvoton: add refclk and update peripheral clocks for NPCM845 Add a 25 MHz fixed-clock node (refclk) in the NPCM845-EVB board device tree to represent the external reference clock used by the NPCM845 reset and clock controller. Update peripherals (timer0, watchdog0-2) in the NPCM845 device tree to reference this refclk directly instead of the previous clock controller output (NPCM8XX_CLK_REFCLK). Depends-on: arm64: dts: nuvoton: Combine NPCM845 reset and clk nodes Signed-off-by: Tomer Maimon Link: https://patch.msgid.link/20250706134207.2168184-3-tmaimon77@gmail.com Signed-off-by: Andrew Jeffery --- arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 9 +++++---- arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 6 ++++++ 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index 400d5c5b71ac..24133528b8e9 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -47,6 +47,7 @@ clk: rstc: reset-controller@f0801000 { reg = <0x0 0xf0801000 0x0 0xC4>; nuvoton,sysgcr = <&gcr>; #reset-cells = <2>; + clocks = <&refclk>; #clock-cells = <1>; }; @@ -71,7 +72,7 @@ timer0: timer@8000 { compatible = "nuvoton,npcm845-timer"; interrupts = ; reg = <0x8000 0x1C>; - clocks = <&clk NPCM8XX_CLK_REFCLK>; + clocks = <&refclk>; clock-names = "refclk"; }; @@ -143,7 +144,7 @@ watchdog0: watchdog@801c { interrupts = ; reg = <0x801c 0x4>; status = "disabled"; - clocks = <&clk NPCM8XX_CLK_REFCLK>; + clocks = <&refclk>; syscon = <&gcr>; }; @@ -152,7 +153,7 @@ watchdog1: watchdog@901c { interrupts = ; reg = <0x901c 0x4>; status = "disabled"; - clocks = <&clk NPCM8XX_CLK_REFCLK>; + clocks = <&refclk>; syscon = <&gcr>; }; @@ -161,7 +162,7 @@ watchdog2: watchdog@a01c { interrupts = ; reg = <0xa01c 0x4>; status = "disabled"; - clocks = <&clk NPCM8XX_CLK_REFCLK>; + clocks = <&refclk>; syscon = <&gcr>; }; }; diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts index eeceb5b292a8..2638ee1c3846 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts @@ -19,6 +19,12 @@ chosen { memory@0 { reg = <0x0 0x0 0x0 0x40000000>; }; + + refclk: refclk-25mhz { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + #clock-cells = <0>; + }; }; &serial0 { From 3ede313b5ec41bf1064fc35a168618eaee0d8e98 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 18 Jul 2025 18:25:38 +0300 Subject: [PATCH 040/931] arm64: dts: qcom: sa8775p: fix RPMh power domain indices On SA8775P power domains device doesn't use unufied (RPMHPD_foo) ABI, but it uses SoC-specific indices (SA8775P_foo). Consequently, all DSP on that platform are referencing random PDs instead of the expected ones. Correct indices used for that platform. Fixes: df54dcb34ff2 ("arm64: dts: qcom: sa8775p: add ADSP, CDSP and GPDSP nodes") Reviewed-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20250718-fix-rpmhpd-abi-v2-1-0059edb9ddb3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index fed34717460f..f3bd8c9ad2ee 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -17,7 +17,6 @@ #include #include #include -#include #include #include @@ -6055,8 +6054,8 @@ remoteproc_gpdsp0: remoteproc@20c00000 { clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd RPMHPD_CX>, - <&rpmhpd RPMHPD_MXC>; + power-domains = <&rpmhpd SA8775P_CX>, + <&rpmhpd SA8775P_MXC>; power-domain-names = "cx", "mxc"; interconnects = <&gpdsp_anoc MASTER_DSP0 0 @@ -6098,8 +6097,8 @@ remoteproc_gpdsp1: remoteproc@21c00000 { clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd RPMHPD_CX>, - <&rpmhpd RPMHPD_MXC>; + power-domains = <&rpmhpd SA8775P_CX>, + <&rpmhpd SA8775P_MXC>; power-domain-names = "cx", "mxc"; interconnects = <&gpdsp_anoc MASTER_DSP1 0 @@ -6239,9 +6238,9 @@ remoteproc_cdsp0: remoteproc@26300000 { clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd RPMHPD_CX>, - <&rpmhpd RPMHPD_MXC>, - <&rpmhpd RPMHPD_NSP0>; + power-domains = <&rpmhpd SA8775P_CX>, + <&rpmhpd SA8775P_MXC>, + <&rpmhpd SA8775P_NSP0>; power-domain-names = "cx", "mxc", "nsp"; interconnects = <&nspa_noc MASTER_CDSP_PROC 0 @@ -6371,9 +6370,9 @@ remoteproc_cdsp1: remoteproc@2a300000 { clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd RPMHPD_CX>, - <&rpmhpd RPMHPD_MXC>, - <&rpmhpd RPMHPD_NSP1>; + power-domains = <&rpmhpd SA8775P_CX>, + <&rpmhpd SA8775P_MXC>, + <&rpmhpd SA8775P_NSP1>; power-domain-names = "cx", "mxc", "nsp"; interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 @@ -6527,8 +6526,8 @@ remoteproc_adsp: remoteproc@30000000 { clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd RPMHPD_LCX>, - <&rpmhpd RPMHPD_LMX>; + power-domains = <&rpmhpd SA8775P_LCX>, + <&rpmhpd SA8775P_LMX>; power-domain-names = "lcx", "lmx"; interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; From 1d517444b21e49bb049dc1ca9df0281ba5203c86 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 18 Jul 2025 18:25:39 +0300 Subject: [PATCH 041/931] arm64: dts: qcom: sm8150: use correct PD for DisplayPort controller Commit 5dd110c90a50 ("arm64: dts: qcom: sm8150: add DisplayPort controller") specified SM8250_MMCX (= 6) for the DisplayPort power domain, however on SM8150 this indices maps to SM8150_MX_AO (= 6). Use correct indice instead (SM8150_MMCX = 9). Fixes: 5dd110c90a50 ("arm64: dts: qcom: sm8150: add DisplayPort controller") Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20250718-fix-rpmhpd-abi-v2-2-0059edb9ddb3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index abf12e10d33f..4b347ee32441 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3908,7 +3908,7 @@ mdss_dp: displayport-controller@ae90000 { #sound-dai-cells = <0>; operating-points-v2 = <&dp_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd SM8150_MMCX>; status = "disabled"; From c48aa92720dc1b883982b1b7e110429d2e316c22 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 18 Jul 2025 18:25:40 +0300 Subject: [PATCH 042/931] arm64: dts: qcom: sm8250: stop using SoC-specific genpd indices The SM8250 has switched to RPMHPD_* indices for RPMh power domains, however commit 86a9264b6c56 ("arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPs") brought some more old-style indices. Convert all of them to use common RPMh PD indices. Fixes: 86a9264b6c56 ("arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPs") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250718-fix-rpmhpd-abi-v2-3-0059edb9ddb3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 42 ++++++++++++++-------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index b30aea8b0540..2b3442a74a5a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1030,7 +1030,7 @@ i2c14: i2c@880000 { dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, <&gpi_dma2 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1075,7 +1075,7 @@ i2c15: i2c@884000 { dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, <&gpi_dma2 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1120,7 +1120,7 @@ i2c16: i2c@888000 { dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, <&gpi_dma2 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1165,7 +1165,7 @@ i2c17: i2c@88c000 { dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, <&gpi_dma2 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1227,7 +1227,7 @@ i2c18: i2c@890000 { dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, <&gpi_dma2 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1289,7 +1289,7 @@ i2c19: i2c@894000 { dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, <&gpi_dma2 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1370,7 +1370,7 @@ i2c0: i2c@980000 { dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, <&gpi_dma0 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1415,7 +1415,7 @@ i2c1: i2c@984000 { dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1460,7 +1460,7 @@ i2c2: i2c@988000 { dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1522,7 +1522,7 @@ i2c3: i2c@98c000 { dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1567,7 +1567,7 @@ i2c4: i2c@990000 { dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, <&gpi_dma0 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1612,7 +1612,7 @@ i2c5: i2c@994000 { dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, <&gpi_dma0 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1657,7 +1657,7 @@ i2c6: i2c@998000 { dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, <&gpi_dma0 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1719,7 +1719,7 @@ i2c7: i2c@99c000 { dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, <&gpi_dma0 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1797,7 +1797,7 @@ i2c8: i2c@a80000 { dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1842,7 +1842,7 @@ i2c9: i2c@a84000 { dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1887,7 +1887,7 @@ i2c10: i2c@a88000 { dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1932,7 +1932,7 @@ i2c11: i2c@a8c000 { dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -1977,7 +1977,7 @@ i2c12: i2c@a90000 { dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -2039,7 +2039,7 @@ i2c13: i2c@a94000 { dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; @@ -4797,7 +4797,7 @@ mdss_dp: displayport-controller@ae90000 { #sound-dai-cells = <0>; operating-points-v2 = <&dp_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; status = "disabled"; From 633ffe23173d947e4075ecf419889a59e6851ea9 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 18 Jul 2025 18:25:41 +0300 Subject: [PATCH 043/931] arm64: dts: qcom: sm8550: stop using SoC-specific genpd indices The SM8550 has switched to RPMHPD_* indices for RPMh power domains, however commit e271b59e39a6 ("arm64: dts: qcom: sm8550: Add camera clock controller") brought some more old-style indices. Convert all of them to use common RPMh PD indices. Fixes: e271b59e39a6 ("arm64: dts: qcom: sm8550: Add camera clock controller") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250718-fix-rpmhpd-abi-v2-4-0059edb9ddb3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 45713d46f3c5..a4ca06679c2f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3623,7 +3623,7 @@ camcc: clock-controller@ade0000 { <&bi_tcxo_div2>, <&bi_tcxo_ao_div2>, <&sleep_clk>; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; From c7724332e0ac88168723f4140cef4c8ba92f87e0 Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Sun, 3 Aug 2025 16:31:05 +0530 Subject: [PATCH 044/931] arm64: dts: qcom: Rename sa8775p SoC to "lemans" SA8775P, QCS9100 and QCS9075 are all variants of the same die, collectively referred to as lemans. Most notably, the last of them has the SAIL (Safety Island) fused off, but remains identical otherwise. In an effort to streamline the codebase, rename the SoC DTSI, moving away from less meaningful numerical model identifiers. Reviewed-by: Konrad Dybcio Nacked-by: Krzysztof Kozlowski Signed-off-by: Wasim Nazir Link: https://lore.kernel.org/r/20250803110113.401927-2-wasim.nazir@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/{sa8775p.dtsi => lemans.dtsi} | 0 arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm64/boot/dts/qcom/{sa8775p.dtsi => lemans.dtsi} (100%) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi similarity index 100% rename from arch/arm64/boot/dts/qcom/sa8775p.dtsi rename to arch/arm64/boot/dts/qcom/lemans.dtsi diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi index 63b3031cfcc1..bcd284c0f939 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -8,7 +8,7 @@ #include #include -#include "sa8775p.dtsi" +#include "lemans.dtsi" #include "sa8775p-pmics.dtsi" / { From 24dc241bddcde97f4099b5b8ebb3b211d5e7122c Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Sun, 3 Aug 2025 16:31:06 +0530 Subject: [PATCH 045/931] arm64: dts: qcom: lemans: Update memory-map for IoT platforms The "automotive" memory map is the special case for the Lemans configuration described by this dtsi, move it aside and use the IoT memory map as the baseline. Introduce "lemans-auto" as a derivative of "lemans" that retains the old automotive memory map to support legacy use cases. As part of the IoT memory map updates: - Introduce new carveouts for gunyah_md and pil_dtb. Adjust the size and base address of the PIL carveout to accommodate these changes. - Increase the size of the video/camera PIL carveout without affecting existing functionality. - Reduce the size of the trusted apps carveout to meet IoT-specific requirements. - Remove audio_mdf_mem, tz_ffi_mem, and their corresponding SCM references, as they are not required for IoT platforms. Co-developed-by: Pratyush Brahma Signed-off-by: Pratyush Brahma Co-developed-by: Prakash Gupta Signed-off-by: Prakash Gupta Nacked-by: Krzysztof Kozlowski Signed-off-by: Wasim Nazir Link: https://lore.kernel.org/r/20250803110113.401927-3-wasim.nazir@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-auto.dtsi | 104 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/lemans.dtsi | 77 ++++++++------- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 2 +- 3 files changed, 150 insertions(+), 33 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/lemans-auto.dtsi diff --git a/arch/arm64/boot/dts/qcom/lemans-auto.dtsi b/arch/arm64/boot/dts/qcom/lemans-auto.dtsi new file mode 100644 index 000000000000..8db958d60fd1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-auto.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include "lemans.dtsi" + +/delete-node/ &pil_camera_mem; +/delete-node/ &pil_adsp_mem; +/delete-node/ &q6_adsp_dtb_mem; +/delete-node/ &q6_gdsp0_dtb_mem; +/delete-node/ &pil_gdsp0_mem; +/delete-node/ &pil_gdsp1_mem; +/delete-node/ &q6_gdsp1_dtb_mem; +/delete-node/ &q6_cdsp0_dtb_mem; +/delete-node/ &pil_cdsp0_mem; +/delete-node/ &pil_gpu_mem; +/delete-node/ &pil_cdsp1_mem; +/delete-node/ &q6_cdsp1_dtb_mem; +/delete-node/ &pil_cvp_mem; +/delete-node/ &pil_video_mem; +/delete-node/ &gunyah_md_mem; + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz_ffi_mem: tz-ffi@91c00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x91c00000 0x0 0x1400000>; + no-map; + }; + + pil_camera_mem: pil-camera@95200000 { + reg = <0x0 0x95200000 0x0 0x500000>; + no-map; + }; + + pil_adsp_mem: pil-adsp@95c00000 { + reg = <0x0 0x95c00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp0_mem: pil-gdsp0@97b00000 { + reg = <0x0 0x97b00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp1_mem: pil-gdsp1@99900000 { + reg = <0x0 0x99900000 0x0 0x1e00000>; + no-map; + }; + + pil_cdsp0_mem: pil-cdsp0@9b800000 { + reg = <0x0 0x9b800000 0x0 0x1e00000>; + no-map; + }; + + pil_gpu_mem: pil-gpu@9d600000 { + reg = <0x0 0x9d600000 0x0 0x2000>; + no-map; + }; + + pil_cdsp1_mem: pil-cdsp1@9d700000 { + reg = <0x0 0x9d700000 0x0 0x1e00000>; + no-map; + }; + + pil_cvp_mem: pil-cvp@9f500000 { + reg = <0x0 0x9f500000 0x0 0x700000>; + no-map; + }; + + pil_video_mem: pil-video@9fc00000 { + reg = <0x0 0x9fc00000 0x0 0x700000>; + no-map; + }; + + audio_mdf_mem: audio-mdf-region@ae000000 { + reg = <0x0 0xae000000 0x0 0x1000000>; + no-map; + }; + + hyptz_reserved_mem: hyptz-reserved@beb00000 { + reg = <0x0 0xbeb00000 0x0 0x11500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@d1900000 { + reg = <0x0 0xd1900000 0x0 0x3800000>; + no-map; + }; + }; + + firmware { + scm { + memory-region = <&tz_ffi_mem>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index f3bd8c9ad2ee..0a9c92aa7234 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -513,7 +513,6 @@ firmware { scm { compatible = "qcom,scm-sa8775p", "qcom,scm"; qcom,dload-mode = <&tcsr 0x13000>; - memory-region = <&tz_ffi_mem>; }; }; @@ -772,6 +771,11 @@ sail_ota_mem: sail-ss@90e00000 { no-map; }; + gunyah_md_mem: gunyah-md@91a80000 { + reg = <0x0 0x91a80000 0x0 0x80000>; + no-map; + }; + aoss_backup_mem: aoss-backup@91b00000 { reg = <0x0 0x91b00000 0x0 0x40000>; no-map; @@ -797,12 +801,6 @@ cdt_data_backup_mem: cdt-data-backup@91ba0000 { no-map; }; - tz_ffi_mem: tz-ffi@91c00000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x91c00000 0x0 0x1400000>; - no-map; - }; - lpass_machine_learning_mem: lpass-machine-learning@93b00000 { reg = <0x0 0x93b00000 0x0 0xf00000>; no-map; @@ -814,52 +812,72 @@ adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { }; pil_camera_mem: pil-camera@95200000 { - reg = <0x0 0x95200000 0x0 0x500000>; + reg = <0x0 0x95200000 0x0 0x700000>; no-map; }; - pil_adsp_mem: pil-adsp@95c00000 { - reg = <0x0 0x95c00000 0x0 0x1e00000>; + pil_adsp_mem: pil-adsp@95900000 { + reg = <0x0 0x95900000 0x0 0x1e00000>; no-map; }; - pil_gdsp0_mem: pil-gdsp0@97b00000 { - reg = <0x0 0x97b00000 0x0 0x1e00000>; + q6_adsp_dtb_mem: q6-adsp-dtb@97700000 { + reg = <0x0 0x97700000 0x0 0x80000>; no-map; }; - pil_gdsp1_mem: pil-gdsp1@99900000 { - reg = <0x0 0x99900000 0x0 0x1e00000>; + q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 { + reg = <0x0 0x97780000 0x0 0x80000>; no-map; }; - pil_cdsp0_mem: pil-cdsp0@9b800000 { - reg = <0x0 0x9b800000 0x0 0x1e00000>; + pil_gdsp0_mem: pil-gdsp0@97800000 { + reg = <0x0 0x97800000 0x0 0x1e00000>; no-map; }; - pil_gpu_mem: pil-gpu@9d600000 { - reg = <0x0 0x9d600000 0x0 0x2000>; + pil_gdsp1_mem: pil-gdsp1@99600000 { + reg = <0x0 0x99600000 0x0 0x1e00000>; no-map; }; - pil_cdsp1_mem: pil-cdsp1@9d700000 { - reg = <0x0 0x9d700000 0x0 0x1e00000>; + q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 { + reg = <0x0 0x9b400000 0x0 0x80000>; no-map; }; - pil_cvp_mem: pil-cvp@9f500000 { - reg = <0x0 0x9f500000 0x0 0x700000>; + q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 { + reg = <0x0 0x9b480000 0x0 0x80000>; no-map; }; - pil_video_mem: pil-video@9fc00000 { - reg = <0x0 0x9fc00000 0x0 0x700000>; + pil_cdsp0_mem: pil-cdsp0@9b500000 { + reg = <0x0 0x9b500000 0x0 0x1e00000>; no-map; }; - audio_mdf_mem: audio-mdf-region@ae000000 { - reg = <0x0 0xae000000 0x0 0x1000000>; + pil_gpu_mem: pil-gpu@9d300000 { + reg = <0x0 0x9d300000 0x0 0x2000>; + no-map; + }; + + q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 { + reg = <0x0 0x9d380000 0x0 0x80000>; + no-map; + }; + + pil_cdsp1_mem: pil-cdsp1@9d400000 { + reg = <0x0 0x9d400000 0x0 0x1e00000>; + no-map; + }; + + pil_cvp_mem: pil-cvp@9f200000 { + reg = <0x0 0x9f200000 0x0 0x700000>; + no-map; + }; + + pil_video_mem: pil-video@9f900000 { + reg = <0x0 0x9f900000 0x0 0x1000000>; no-map; }; @@ -868,11 +886,6 @@ firmware_mem: firmware-region@b0000000 { no-map; }; - hyptz_reserved_mem: hyptz-reserved@beb00000 { - reg = <0x0 0xbeb00000 0x0 0x11500000>; - no-map; - }; - scmi_mem: scmi-region@d0000000 { reg = <0x0 0xd0000000 0x0 0x40000>; no-map; @@ -914,7 +927,7 @@ deepsleep_backup_mem: deepsleep-backup@d1800000 { }; trusted_apps_mem: trusted-apps@d1900000 { - reg = <0x0 0xd1900000 0x0 0x3800000>; + reg = <0x0 0xd1900000 0x0 0x1c00000>; no-map; }; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi index bcd284c0f939..a9ec6ded412e 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -8,7 +8,7 @@ #include #include -#include "lemans.dtsi" +#include "lemans-auto.dtsi" #include "sa8775p-pmics.dtsi" / { From 4c0c97b95a9b05e3886c3453492a465507d5c09b Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Sun, 3 Aug 2025 16:31:07 +0530 Subject: [PATCH 046/931] arm64: dts: qcom: lemans: Separate out ethernet card for ride & ride-r3 Ride & Ride-r3 in lemans/lemans-auto uses different ethernet cards with different phy capabilities. Separate out the ethernet card information from main board so that it can be reused for all the variants of ride & ride-r3 platforms in lemans/lemans-auto. Lemans/lemans-auto Ride uses 1G phy while Lemans/lemans-auto Ride-r3 uses 2.5G phy. Introduce ethernet cards with 1G & 2.5G phy capabilities respectively: *-88ea1512.dtsi is for 2x 1G - SGMII (Marvell 88EA1512-B2) phy *-aqr115c.dtsi is for 2x 2.5G - HSGMII (Marvell AQR115c) phy Nacked-by: Krzysztof Kozlowski Signed-off-by: Wasim Nazir Link: https://lore.kernel.org/r/20250803110113.401927-4-wasim.nazir@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../qcom/lemans-ride-ethernet-88ea1512.dtsi | 205 ++++++++++++++++++ .../qcom/lemans-ride-ethernet-aqr115c.dtsi | 205 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts | 35 +-- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 35 +-- arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi | 163 -------------- 5 files changed, 412 insertions(+), 231 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi create mode 100644 arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi new file mode 100644 index 000000000000..9d6bbe1447a4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-88ea1512.dtsi @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/* + * Ethernet card for Lemans based Ride boards. + * It supports 2x 1G - SGMII (Marvell 88EA1512-B2) phy for Main domain + */ + +#include +#include + +/ { + aliases { + ethernet0 = ðernet0; + ethernet1 = ðernet1; + }; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio8"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio9"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; +}; + +ðernet0 { + phy-handle = <&sgmii_phy0>; + phy-mode = "sgmii"; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,ps-speed = <1000>; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy0: phy@8 { + compatible = "ethernet-phy-id0141.0dd4"; + reg = <0x8>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + + sgmii_phy1: phy@a { + compatible = "ethernet-phy-id0141.0dd4"; + reg = <0xa>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +ðernet1 { + phy-handle = <&sgmii_phy1>; + phy-mode = "sgmii"; + + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + snps,ps-speed = <1000>; + + status = "okay"; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi new file mode 100644 index 000000000000..2d2d9ee5f0d9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-ride-ethernet-aqr115c.dtsi @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/* + * Ethernet card for Lemans based Ride r3 boards. + * It supports 2x 2.5G - HSGMII (Marvell hsgmii) phy for Main domain + */ + +#include +#include + +/ { + aliases { + ethernet0 = ðernet0; + ethernet1 = ðernet1; + }; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio8"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio9"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; +}; + +ðernet0 { + phy-handle = <&hsgmii_phy0>; + phy-mode = "2500base-x"; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,ps-speed = <1000>; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + hsgmii_phy0: phy@8 { + compatible = "ethernet-phy-id31c3.1c33"; + reg = <0x8>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + + hsgmii_phy1: phy@0 { + compatible = "ethernet-phy-id31c3.1c33"; + reg = <0x0>; + device_type = "ethernet-phy"; + interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +ðernet1 { + phy-handle = <&hsgmii_phy1>; + phy-mode = "2500base-x"; + + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + snps,ps-speed = <1000>; + + status = "okay"; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts index ae065ae92478..a7f377dc4733 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts @@ -6,42 +6,9 @@ /dts-v1/; #include "sa8775p-ride.dtsi" +#include "lemans-ride-ethernet-aqr115c.dtsi" / { model = "Qualcomm SA8775P Ride Rev3"; compatible = "qcom,sa8775p-ride-r3", "qcom,sa8775p"; }; - -ðernet0 { - phy-mode = "2500base-x"; -}; - -ðernet1 { - phy-mode = "2500base-x"; -}; - -&mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - sgmii_phy0: phy@8 { - compatible = "ethernet-phy-id31c3.1c33"; - reg = <0x8>; - device_type = "ethernet-phy"; - interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; - reset-assert-us = <11000>; - reset-deassert-us = <70000>; - }; - - sgmii_phy1: phy@0 { - compatible = "ethernet-phy-id31c3.1c33"; - reg = <0x0>; - device_type = "ethernet-phy"; - interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <11000>; - reset-deassert-us = <70000>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 2e87fd760dbd..b765794f7e54 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -6,42 +6,9 @@ /dts-v1/; #include "sa8775p-ride.dtsi" +#include "lemans-ride-ethernet-88ea1512.dtsi" / { model = "Qualcomm SA8775P Ride"; compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; }; - -ðernet0 { - phy-mode = "sgmii"; -}; - -ðernet1 { - phy-mode = "sgmii"; -}; - -&mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - sgmii_phy0: phy@8 { - compatible = "ethernet-phy-id0141.0dd4"; - reg = <0x8>; - device_type = "ethernet-phy"; - interrupts-extended = <&tlmm 7 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; - reset-assert-us = <11000>; - reset-deassert-us = <70000>; - }; - - sgmii_phy1: phy@a { - compatible = "ethernet-phy-id0141.0dd4"; - reg = <0xa>; - device_type = "ethernet-phy"; - interrupts-extended = <&tlmm 26 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; - reset-assert-us = <11000>; - reset-deassert-us = <70000>; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi index a9ec6ded412e..f512363f6222 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi @@ -13,8 +13,6 @@ / { aliases { - ethernet0 = ðernet0; - ethernet1 = ðernet1; i2c11 = &i2c11; i2c18 = &i2c18; serial0 = &uart10; @@ -443,151 +441,6 @@ vreg_l8e: ldo8 { }; }; -ðernet0 { - phy-handle = <&sgmii_phy0>; - - pinctrl-0 = <ðernet0_default>; - pinctrl-names = "default"; - - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - snps,ps-speed = <1000>; - - status = "okay"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xc>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <4>; - - queue0 { - snps,dcb-algorithm; - }; - - queue1 { - snps,dcb-algorithm; - }; - - queue2 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - - queue3 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - }; -}; - -ðernet1 { - phy-handle = <&sgmii_phy1>; - - snps,mtl-rx-config = <&mtl_rx_setup1>; - snps,mtl-tx-config = <&mtl_tx_setup1>; - snps,ps-speed = <1000>; - - status = "okay"; - - mtl_rx_setup1: rx-queues-config { - snps,rx-queues-to-use = <4>; - snps,rx-sched-sp; - - queue0 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x0>; - snps,route-up; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xc>; - }; - }; - - mtl_tx_setup1: tx-queues-config { - snps,tx-queues-to-use = <4>; - - queue0 { - snps,dcb-algorithm; - }; - - queue1 { - snps,dcb-algorithm; - }; - - queue2 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - - queue3 { - snps,avb-algorithm; - snps,send_slope = <0x1000>; - snps,idle_slope = <0x1000>; - snps,high_credit = <0x3e800>; - snps,low_credit = <0xffc18000>; - }; - }; -}; - &i2c11 { clock-frequency = <400000>; status = "okay"; @@ -960,22 +813,6 @@ dp1_hot_plug_det: dp1-hot-plug-det-state { bias-disable; }; - ethernet0_default: ethernet0-default-state { - ethernet0_mdc: ethernet0-mdc-pins { - pins = "gpio8"; - function = "emac0_mdc"; - drive-strength = <16>; - bias-pull-up; - }; - - ethernet0_mdio: ethernet0-mdio-pins { - pins = "gpio9"; - function = "emac0_mdio"; - drive-strength = <16>; - bias-pull-up; - }; - }; - io_expander_intr_active: io-expander-intr-active-state { pins = "gpio98"; function = "gpio"; From 76326da895b889f7f0b20e5ba5cc47b836521f44 Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Sun, 3 Aug 2025 16:31:08 +0530 Subject: [PATCH 047/931] arm64: dts: qcom: lemans: Refactor ride/ride-r3 boards based on daughter cards Ride/Ride-r3 boards used with lemans and derivatives: - Are composed of multiple daughter cards (SoC-card, display, camera, ethernet, pcie, sensor, front & backplane, WLAN & BT). - Across lemans & its derivatives, SoM is changing. - Across Ride & Ride-r3 board, ethernet card is changing. Excluding the differences all other cards i.e SoC-card, display, camera, PCIe, sensor, front & backplane are same across Ride/Ride-r3 boards used with lemans and derivatives. Describe all the common cards in lemans-ride-common so that it can be reused for all the variants of ride & ride-r3 platforms in lemans and derivatives. Nacked-by: Krzysztof Kozlowski Signed-off-by: Wasim Nazir Link: https://lore.kernel.org/r/20250803110113.401927-5-wasim.nazir@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/{sa8775p-ride.dtsi => lemans-ride-common.dtsi} | 5 ----- arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts | 5 ++++- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 5 ++++- 3 files changed, 8 insertions(+), 7 deletions(-) rename arch/arm64/boot/dts/qcom/{sa8775p-ride.dtsi => lemans-ride-common.dtsi} (99%) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi similarity index 99% rename from arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi rename to arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index f512363f6222..25e756c14160 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -3,14 +3,9 @@ * Copyright (c) 2023, Linaro Limited */ -/dts-v1/; - #include #include -#include "lemans-auto.dtsi" -#include "sa8775p-pmics.dtsi" - / { aliases { i2c11 = &i2c11; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts index a7f377dc4733..3e19ff5e061f 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts @@ -5,7 +5,10 @@ /dts-v1/; -#include "sa8775p-ride.dtsi" +#include "lemans-auto.dtsi" + +#include "sa8775p-pmics.dtsi" +#include "lemans-ride-common.dtsi" #include "lemans-ride-ethernet-aqr115c.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index b765794f7e54..68a99582b538 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -5,7 +5,10 @@ /dts-v1/; -#include "sa8775p-ride.dtsi" +#include "lemans-auto.dtsi" + +#include "sa8775p-pmics.dtsi" +#include "lemans-ride-common.dtsi" #include "lemans-ride-ethernet-88ea1512.dtsi" / { From d39e1d737bdb0242e1d70345bb1ecfc8382289ce Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Sun, 3 Aug 2025 16:31:09 +0530 Subject: [PATCH 048/931] arm64: dts: qcom: lemans: Rename sa8775p-pmics.dtsi to lemans-pmics.dtsi The existing PMIC DTSI file is named sa8775p-pmics.dtsi, which does not align with the updated naming convention for Lemans platform components. This inconsistency can lead to confusion and misalignment with other platform-specific files. Rename the file to lemans-pmics.dtsi to reflect the platform naming convention and improve clarity. Signed-off-by: Wasim Nazir Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250803110113.401927-6-wasim.nazir@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/{sa8775p-pmics.dtsi => lemans-pmics.dtsi} | 0 arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts | 2 +- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 2 +- 3 files changed, 2 insertions(+), 2 deletions(-) rename arch/arm64/boot/dts/qcom/{sa8775p-pmics.dtsi => lemans-pmics.dtsi} (100%) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi similarity index 100% rename from arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi rename to arch/arm64/boot/dts/qcom/lemans-pmics.dtsi diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts index 3e19ff5e061f..b25f0b2c9410 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts @@ -7,7 +7,7 @@ #include "lemans-auto.dtsi" -#include "sa8775p-pmics.dtsi" +#include "lemans-pmics.dtsi" #include "lemans-ride-common.dtsi" #include "lemans-ride-ethernet-aqr115c.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 68a99582b538..2d9028cd60be 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -7,7 +7,7 @@ #include "lemans-auto.dtsi" -#include "sa8775p-pmics.dtsi" +#include "lemans-pmics.dtsi" #include "lemans-ride-common.dtsi" #include "lemans-ride-ethernet-88ea1512.dtsi" From b4feac9e034fe1a609619cb7feb55217fd5d6583 Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Sun, 3 Aug 2025 16:31:10 +0530 Subject: [PATCH 049/931] arm64: dts: qcom: lemans: Fix dts inclusion for IoT boards and update memory map IoT boards currently inherit the automotive memory map, which is not suitable for their configuration. This leads to incorrect memory layout and inclusion of unnecessary carveouts. Use lemans.dtsi as the base for IoT boards to apply the correct memory map. Include additional DTSI files as needed to complete the board configuration. Update 'model' string to represent these boards as 'lemans'. Signed-off-by: Wasim Nazir Link: https://lore.kernel.org/r/20250803110113.401927-7-wasim.nazir@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts | 9 +++++++-- arch/arm64/boot/dts/qcom/qcs9100-ride.dts | 9 +++++++-- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts b/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts index 759d1ec694b2..7fc2de0d3d5e 100644 --- a/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts +++ b/arch/arm64/boot/dts/qcom/qcs9100-ride-r3.dts @@ -4,8 +4,13 @@ */ /dts-v1/; -#include "sa8775p-ride-r3.dts" +#include "lemans.dtsi" +#include "lemans-pmics.dtsi" + +#include "lemans-ride-common.dtsi" +#include "lemans-ride-ethernet-aqr115c.dtsi" + / { - model = "Qualcomm QCS9100 Ride Rev3"; + model = "Qualcomm Technologies, Inc. Lemans Ride Rev3"; compatible = "qcom,qcs9100-ride-r3", "qcom,qcs9100", "qcom,sa8775p"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs9100-ride.dts b/arch/arm64/boot/dts/qcom/qcs9100-ride.dts index 979462dfec30..b0c5fdde56ae 100644 --- a/arch/arm64/boot/dts/qcom/qcs9100-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs9100-ride.dts @@ -4,8 +4,13 @@ */ /dts-v1/; -#include "sa8775p-ride.dts" +#include "lemans.dtsi" +#include "lemans-pmics.dtsi" + +#include "lemans-ride-common.dtsi" +#include "lemans-ride-ethernet-88ea1512.dtsi" + / { - model = "Qualcomm QCS9100 Ride"; + model = "Qualcomm Technologies, Inc. Lemans Ride"; compatible = "qcom,qcs9100-ride", "qcom,qcs9100", "qcom,sa8775p"; }; From e9d84a1f8bfe85b6c406c4a088e537d4a5f83a87 Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Sun, 3 Aug 2025 16:31:11 +0530 Subject: [PATCH 050/931] dt-bindings: arm: qcom: lemans: Add bindings for Lemans Evaluation Kit (EVK) Introduce new bindings for the Lemans EVK, an IoT board without safety features. Signed-off-by: Wasim Nazir Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250803110113.401927-8-wasim.nazir@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index ae43b3556580..bf5f3beb320b 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -969,6 +969,7 @@ properties: - items: - enum: + - qcom,lemans-evk - qcom,qcs9100-ride - qcom,qcs9100-ride-r3 - const: qcom,qcs9100 From 99ea5a0d6bc820b15727cea006561ede7339bb79 Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Sun, 3 Aug 2025 16:31:12 +0530 Subject: [PATCH 051/931] arm64: dts: qcom: Add lemans evaluation kit (EVK) initial board support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lemans EVK is an IoT board without safety monitoring feature of Safety Island(SAIL) subsystem. Lemans EVK is single board supporting these peripherals: - Storage: 2 × 128 GB UFS, micro-SD card, EEPROMs for MACs, eMMC on mezzanine card - Audio/Video, Camera & Display ports - Connectivity: RJ45 2.5GbE, WLAN/Bluetooth, CAN/CAN-FD - Sensors: IMU - PCIe ports - USB & UART ports On top of lemans EVK board additional mezzanine boards can be stacked in future. Implement basic features like uart/ufs to enable 'boot to shell'. Co-developed-by: Rakesh Kota Signed-off-by: Rakesh Kota Co-developed-by: Sayali Lokhande Signed-off-by: Sayali Lokhande Reviewed-by: Konrad Dybcio Signed-off-by: Wasim Nazir Link: https://lore.kernel.org/r/20250803110113.401927-9-wasim.nazir@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/lemans-evk.dts | 291 ++++++++++++++++++++++++ 2 files changed, 292 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/lemans-evk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4bfa926b6a08..dcc0f6382f51 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts new file mode 100644 index 000000000000..669ac52f4cf6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include +#include + +#include "lemans.dtsi" +#include "lemans-pmics.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lemans EVK"; + compatible = "qcom,lemans-evk", "qcom,qcs9100", "qcom,sa8775p"; + + aliases { + serial0 = &uart10; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s4a: smps4 { + regulator-name = "vreg_s4a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1816000>; + regulator-initial-mode = ; + }; + + vreg_s5a: smps5 { + regulator-name = "vreg_s5a"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1996000>; + regulator-initial-mode = ; + }; + + vreg_s9a: smps9 { + regulator-name = "vreg_s9a"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5c: ldo5 { + regulator-name = "vreg_l5c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2700000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "e"; + + vreg_s4e: smps4 { + regulator-name = "vreg_s4e"; + regulator-min-microvolt = <970000>; + regulator-max-microvolt = <1520000>; + regulator-initial-mode = ; + }; + + vreg_s7e: smps7 { + regulator-name = "vreg_s7e"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + regulator-initial-mode = ; + }; + + vreg_s9e: smps9 { + regulator-name = "vreg_s9e"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = ; + }; + + vreg_l6e: ldo6 { + regulator-name = "vreg_l6e"; + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8e: ldo8 { + regulator-name = "vreg_l8e"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32768>; +}; + +&uart10 { + compatible = "qcom,geni-debug-uart"; + pinctrl-0 = <&qup_uart10_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l8a>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l4c>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; From 91ec67fa33250059a0c52bbf3148302f364a6e99 Mon Sep 17 00:00:00 2001 From: Anton Kirilov Date: Thu, 7 Aug 2025 18:00:11 +0100 Subject: [PATCH 052/931] arm64: dts: rockchip: Enable HDMI audio output for NanoPi R6C/R6S Enable HDMI audio output for FriendlyElec NanoPi R6C/R6S boards. Signed-off-by: Anton Kirilov Link: https://lore.kernel.org/r/20250807170012.88178-1-anton.kirilov@arm.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi index fbf062ec3bf1..2e9d5143476d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi @@ -251,6 +251,10 @@ hdmi0_out_con: endpoint { }; }; +&hdmi0_sound { + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -335,6 +339,10 @@ hym8563: rtc@51 { }; }; +&i2s5_8ch { + status = "okay"; +}; + &mdio1 { rgmii_phy1: ethernet-phy@1 { compatible = "ethernet-phy-id001c.c916"; From 6f36b1fdb80dd1fdd24742af4ca435f76f73dfe9 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sun, 10 Aug 2025 18:00:20 +0800 Subject: [PATCH 053/931] arm64: dts: rockchip: set LAN LEDs to default-off on Radxa E52C The NICs have default-trigger of "netdev" in order to show up as LAN/WAN connected, so their default-state should be set to "off". Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20250810100020.445053-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts b/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts index e04f21d8c831..63e5dfb77ab1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts @@ -71,7 +71,7 @@ leds-1 { led-1 { color = ; - default-state = "on"; + default-state = "off"; function = LED_FUNCTION_LAN; linux,default-trigger = "netdev"; pwms = <&pwm14 0 1000000 PWM_POLARITY_INVERTED>; @@ -80,7 +80,7 @@ led-1 { led-2 { color = ; - default-state = "on"; + default-state = "off"; function = LED_FUNCTION_WAN; linux,default-trigger = "netdev"; pwms = <&pwm11 0 1000000 PWM_POLARITY_INVERTED>; From 6294d0590d5f65725e505b89978895bd04b55650 Mon Sep 17 00:00:00 2001 From: Chaoyi Chen Date: Thu, 31 Jul 2025 14:24:15 +0800 Subject: [PATCH 054/931] arm64: dts: rockchip: Enable eMMC on rk3576-evb1-v10 Some rk3576-evb1 boards use eMMC instead of UFS. Enable eMMC for it. Signed-off-by: Chaoyi Chen Link: https://lore.kernel.org/r/20250731062415.212-1-kernel@airkyi.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index 56527c56830e..a60dee0de9f9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -723,6 +723,18 @@ usbc0_int: usbc0-int { }; }; +&sdhci { + bus-width = <8>; + full-pwr-cycle-in-suspend; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; From 15e8ba9d8b14ae6de415186622379f5f4dcfd141 Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Tue, 10 Jun 2025 14:32:42 +0200 Subject: [PATCH 055/931] arm64: dts: rockchip: Add thermal nodes to RK3576 Add the TSADC node to the RK3576. Additionally, add everything the TSADC needs to function, i.e. thermal zones, their trip points and maps, as well as adjust the CPU cooling-cells property. The polling-delay properties are set to 0 as we do have interrupts for this TSADC on this particular SoC, though the polling-delay-passive properties are set to 100 for the thermal zones that have a passive cooling device, as otherwise the thermal throttling behaviour never unthrottles. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-6-b6e9efbf1015@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 164 ++++++++++++++++++++++- 1 file changed, 162 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index c3cdae8a5494..2ec752b12b41 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { compatible = "rockchip,rk3576"; @@ -113,9 +114,9 @@ cpu_l0: cpu@0 { capacity-dmips-mhz = <485>; clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; - #cooling-cells = <2>; dynamic-power-coefficient = <120>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_l1: cpu@1 { @@ -127,6 +128,7 @@ cpu_l1: cpu@1 { clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_l2: cpu@2 { @@ -138,6 +140,7 @@ cpu_l2: cpu@2 { clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_l3: cpu@3 { @@ -149,6 +152,7 @@ cpu_l3: cpu@3 { clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b0: cpu@100 { @@ -159,9 +163,9 @@ cpu_b0: cpu@100 { capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; - #cooling-cells = <2>; dynamic-power-coefficient = <320>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b1: cpu@101 { @@ -173,6 +177,7 @@ cpu_b1: cpu@101 { clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b2: cpu@102 { @@ -184,6 +189,7 @@ cpu_b2: cpu@102 { clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; cpu_b3: cpu@103 { @@ -195,6 +201,7 @@ cpu_b3: cpu@103 { clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; }; idle-states { @@ -520,6 +527,143 @@ psci { method = "smc"; }; + thermal_zones: thermal-zones { + /* sensor near the center of the SoC */ + package_thermal: package-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 0>; + + trips { + package_crit: package-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + /* sensor for cluster1 (big Cortex-A72 cores) */ + bigcore_thermal: bigcore-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 1>; + + trips { + bigcore_alert: bigcore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + bigcore_crit: bigcore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&bigcore_alert>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor for cluster0 (little Cortex-A53 cores) */ + littlecore_thermal: littlecore-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 2>; + + trips { + littlecore_alert: littlecore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + littlecore_crit: littlecore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&littlecore_alert>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 3>; + + trips { + gpu_alert: gpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + npu_thermal: npu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 4>; + + trips { + npu_crit: npu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr_thermal: ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 5>; + + trips { + ddr_crit: ddr-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -2303,6 +2447,22 @@ saradc: adc@2ae00000 { status = "disabled"; }; + tsadc: tsadc@2ae70000 { + compatible = "rockchip,rk3576-tsadc"; + reg = <0x0 0x2ae70000 0x0 0x400>; + interrupts = ; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>; + assigned-clock-rates = <2000000>; + resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; + reset-names = "tsadc-apb", "tsadc"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + }; + i2c9: i2c@2ae80000 { compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0x2ae80000 0x0 0x1000>; From a4053badacf3699023527392c947314b074f5e0e Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Tue, 10 Jun 2025 14:32:43 +0200 Subject: [PATCH 056/931] arm64: dts: rockchip: Add thermal trim OTP and tsadc nodes Thanks to Heiko's work getting OTP working on the RK3576, we can specify the thermal sensor trim values which are stored there now, and with my driver addition to rockchip_thermal, we can make use of these. Add them to the devicetree for the SoC. Signed-off-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-7-b6e9efbf1015@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 57 ++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 2ec752b12b41..f28c5a3e4f4c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1937,6 +1937,30 @@ gpu_leakage: gpu-leakage@21 { log_leakage: log-leakage@22 { reg = <0x22 0x1>; }; + bigcore_tsadc_trim: bigcore-tsadc-trim@24 { + reg = <0x24 0x2>; + bits = <0 10>; + }; + litcore_tsadc_trim: litcore-tsadc-trim@26 { + reg = <0x26 0x2>; + bits = <0 10>; + }; + ddr_tsadc_trim: ddr-tsadc-trim@28 { + reg = <0x28 0x2>; + bits = <0 10>; + }; + npu_tsadc_trim: npu-tsadc-trim@2a { + reg = <0x2a 0x2>; + bits = <0 10>; + }; + gpu_tsadc_trim: gpu-tsadc-trim@2c { + reg = <0x2c 0x2>; + bits = <0 10>; + }; + soc_tsadc_trim: soc-tsadc-trim@64 { + reg = <0x64 0x2>; + bits = <0 10>; + }; }; sai0: sai@2a600000 { @@ -2461,6 +2485,39 @@ tsadc: tsadc@2ae70000 { rockchip,hw-tshut-temp = <120000>; rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + #address-cells = <1>; + #size-cells = <0>; + + sensor@0 { + reg = <0>; + nvmem-cells = <&soc_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@1 { + reg = <1>; + nvmem-cells = <&bigcore_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@2 { + reg = <2>; + nvmem-cells = <&litcore_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@3 { + reg = <3>; + nvmem-cells = <&ddr_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@4 { + reg = <4>; + nvmem-cells = <&npu_tsadc_trim>; + nvmem-cell-names = "trim"; + }; + sensor@5 { + reg = <5>; + nvmem-cells = <&gpu_tsadc_trim>; + nvmem-cell-names = "trim"; + }; }; i2c9: i2c@2ae80000 { From 6d64bceb97a1c93b3cc2131f7e023ef2f9cf33f2 Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Mon, 21 Jul 2025 11:17:34 +0200 Subject: [PATCH 057/931] arm64: dts: rockchip: add pd_npu label for RK3588 power domains The NPU of the RK3588 has an external supply. This supply also affects the power domain of the NPU, not just the NPU device nodes themselves. Since correctly modelled boards will want the power domain to be aware of the regulator so that it doesn't always have to be on, add a label to the NPU power domain node so board files can reference it. Signed-off-by: Nicolas Frattaroli Tested-by: Heiko Stuebner Signed-off-by: Tomeu Vizoso Link: https://lore.kernel.org/r/20250721-6-10-rocket-v9-7-77ebd484941e@tomeuvizoso.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 70f03e68ba55..1eddc69fd9c9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -841,7 +841,7 @@ power: power-controller { status = "okay"; /* These power domains are grouped by VD_NPU */ - power-domain@RK3588_PD_NPU { + pd_npu: power-domain@RK3588_PD_NPU { reg = ; #power-domain-cells = <0>; #address-cells = <1>; From a31dfc060a747f08705ace36d8de006bc13318fa Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Mon, 21 Jul 2025 11:17:35 +0200 Subject: [PATCH 058/931] arm64: dts: rockchip: Add nodes for NPU and its MMU to rk3588-base See Chapter 36 "RKNN" from the RK3588 TRM (Part 1). The IP is divided in three cores, programmed independently. The first core though is special, being able to delegate work to the other cores. The IOMMU of the first core is also special in that it has two subunits (read/write?) that need to be programmed in sync. v2: - Have one device for each NPU core (Sebastian Reichel) - Have one device for each IOMMU (Sebastian Reichel) - Correctly sort nodes (Diederik de Haas) - Add rockchip,iommu compatible to IOMMU nodes (Sebastian Reichel) v3: - Adapt to a split of the register block in the DT bindings (Nicolas Frattaroli) v4: - Adapt to changes in bindings v6: - pclk and npu clocks are needed by all clocks (Rob Herring) v8: - Remove notion of top core (Robin Murphy) Tested-by: Heiko Stuebner Signed-off-by: Tomeu Vizoso Link: https://lore.kernel.org/r/20250721-6-10-rocket-v9-8-77ebd484941e@tomeuvizoso.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 1eddc69fd9c9..a18aa1e6c3f1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1140,6 +1140,97 @@ power-domain@RK3588_PD_SDMMC { }; }; + rknn_core_0: npu@fdab0000 { + compatible = "rockchip,rk3588-rknn-core"; + reg = <0x0 0xfdab0000 0x0 0x1000>, + <0x0 0xfdab1000 0x0 0x1000>, + <0x0 0xfdab3000 0x0 0x1000>; + reg-names = "pc", "cna", "core"; + interrupts = ; + clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; + clock-names = "aclk", "hclk", "npu", "pclk"; + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; + assigned-clock-rates = <200000000>; + resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RK3588_PD_NPUTOP>; + iommus = <&rknn_mmu_0>; + status = "disabled"; + }; + + rknn_mmu_0: iommu@fdab9000 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdab9000 0x0 0x100>, + <0x0 0xfdaba000 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_NPUTOP>; + status = "disabled"; + }; + + rknn_core_1: npu@fdac0000 { + compatible = "rockchip,rk3588-rknn-core"; + reg = <0x0 0xfdac0000 0x0 0x1000>, + <0x0 0xfdac1000 0x0 0x1000>, + <0x0 0xfdac3000 0x0 0x1000>; + reg-names = "pc", "cna", "core"; + interrupts = ; + clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; + clock-names = "aclk", "hclk", "npu", "pclk"; + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; + assigned-clock-rates = <200000000>; + resets = <&cru SRST_A_RKNN1>, <&cru SRST_H_RKNN1>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RK3588_PD_NPU1>; + iommus = <&rknn_mmu_1>; + status = "disabled"; + }; + + rknn_mmu_1: iommu@fdac9000 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdaca000 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_NPU1>; + status = "disabled"; + }; + + rknn_core_2: npu@fdad0000 { + compatible = "rockchip,rk3588-rknn-core"; + reg = <0x0 0xfdad0000 0x0 0x1000>, + <0x0 0xfdad1000 0x0 0x1000>, + <0x0 0xfdad3000 0x0 0x1000>; + reg-names = "pc", "cna", "core"; + interrupts = ; + clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; + clock-names = "aclk", "hclk", "npu", "pclk"; + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; + assigned-clock-rates = <200000000>; + resets = <&cru SRST_A_RKNN2>, <&cru SRST_H_RKNN2>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RK3588_PD_NPU2>; + iommus = <&rknn_mmu_2>; + status = "disabled"; + }; + + rknn_mmu_2: iommu@fdad9000 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdada000 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_NPU2>; + status = "disabled"; + }; + vpu121: video-codec@fdb50000 { compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu"; reg = <0x0 0xfdb50000 0x0 0x800>; From 640366d644b1e282771a09c72be37162b6eda438 Mon Sep 17 00:00:00 2001 From: Tomeu Vizoso Date: Mon, 21 Jul 2025 11:17:36 +0200 Subject: [PATCH 059/931] arm64: dts: rockchip: Enable the NPU on quartzpro64 Enable the nodes added in a previous commit to the rk3588s device tree. v2: - Split nodes (Sebastian Reichel) - Sort nodes (Sebastian Reichel) - Add board regulators (Sebastian Reichel) v8: - Remove notion of top core (Robin Murphy) Tested-by: Heiko Stuebner Signed-off-by: Tomeu Vizoso Link: https://lore.kernel.org/r/20250721-6-10-rocket-v9-9-77ebd484941e@tomeuvizoso.net Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-quartzpro64.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts index 78aaa6635b5d..b2336c36da01 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts @@ -415,6 +415,36 @@ &pcie3x4 { status = "okay"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8_s0>; status = "okay"; From 3af6a83fc85033e44ce5cd0e1de54dc20b7e15af Mon Sep 17 00:00:00 2001 From: Nicolas Frattaroli Date: Mon, 21 Jul 2025 11:17:37 +0200 Subject: [PATCH 060/931] arm64: dts: rockchip: enable NPU on ROCK 5B The NPU on the ROCK5B uses the same regulator for both the sram-supply and the npu's supply. Add this regulator, and enable all the NPU bits. Also add the regulator as a domain-supply to the pd_npu power domain. v8: - Remove notion of top core (Robin Murphy) Signed-off-by: Nicolas Frattaroli Tested-by: Heiko Stuebner Signed-off-by: Tomeu Vizoso Link: https://lore.kernel.org/r/20250721-6-10-rocket-v9-10-77ebd484941e@tomeuvizoso.net Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi index 973d39a7e0e0..612808d2b4c5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi @@ -268,6 +268,29 @@ regulator-state-mem { }; }; +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <500>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + &i2c6 { status = "okay"; @@ -392,6 +415,10 @@ &pd_gpu { domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -424,6 +451,36 @@ &pwm1 { status = "okay"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; From 1bce3444df79910512587a1f18022c396e9430b5 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 20 Jun 2025 22:17:15 +0200 Subject: [PATCH 061/931] arm64: dts: rockchip: convert rk3528 power-domains to dt-binding constants Now that the binding head has been merged, convert the power-domain ids back to these constants for easier handling. Reviewed-by: Jonas Karlman Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250620201715.1572609-1-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 001a555c83b7..54fa8089c4d3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include / { @@ -480,8 +481,8 @@ power: power-controller { #size-cells = <0>; /* These power domains are grouped by VD_GPU */ - power-domain@4 { - reg = <4>; + power-domain@RK3528_PD_GPU { + reg = ; clocks = <&cru ACLK_GPU_MALI>, <&cru PCLK_GPU_ROOT>; pm_qos = <&qos_gpu_m0>, @@ -490,20 +491,20 @@ power-domain@4 { }; /* These power domains are grouped by VD_LOGIC */ - power-domain@5 { - reg = <5>; + power-domain@RK3528_PD_RKVDEC { + reg = ; pm_qos = <&qos_rkvdec>; #power-domain-cells = <0>; status = "disabled"; }; - power-domain@6 { - reg = <6>; + power-domain@RK3528_PD_RKVENC { + reg = ; pm_qos = <&qos_rkvenc>; #power-domain-cells = <0>; status = "disabled"; }; - power-domain@7 { - reg = <7>; + power-domain@RK3528_PD_VO { + reg = ; pm_qos = <&qos_gmac0>, <&qos_hdcp>, <&qos_jpegdec>, @@ -516,8 +517,8 @@ power-domain@7 { #power-domain-cells = <0>; status = "disabled"; }; - power-domain@8 { - reg = <8>; + power-domain@RK3528_PD_VPU { + reg = ; pm_qos = <&qos_emmc>, <&qos_fspi>, <&qos_gmac1>, @@ -556,7 +557,7 @@ gpu: gpu@ff700000 { "pp1", "ppmmu1"; operating-points-v2 = <&gpu_opp_table>; - power-domains = <&power 4>; + power-domains = <&power RK3528_PD_GPU>; resets = <&cru SRST_A_GPU>; status = "disabled"; }; From d17b34744f5e4299109801c0a151e5dd31d76936 Mon Sep 17 00:00:00 2001 From: Thierry Bultel Date: Tue, 17 Jun 2025 17:28:09 +0100 Subject: [PATCH 062/931] arm64: dts: renesas: Add initial support for the Renesas RZ/T2H SoC Add the initial dtsi for the RZ/T2H SoC: - GIC - ARMv8-timer - CPG clock - SCI0 UART also add arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi, that keeps all 4 CPUs enabled, for consistency with later support of -m24 and -m04 SoC revisions, that only have 2 and 1 Cortex-A55, respectively, and that will use /delete-node/ to disable the missing CPUs. Signed-off-by: Thierry Bultel Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250617162810.154332-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 124 ++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi | 13 ++ 2 files changed, 137 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi new file mode 100644 index 000000000000..42c3b86196d6 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/T2H SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a09g077"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a55"; + reg = <0x200>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a55"; + reg = <0x300>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x100000>; + cache-level = <3>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sci0: serial@80005000 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x80005000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + cpg: clock-controller@80280000 { + compatible = "renesas,r9a09g077-cpg-mssr"; + reg = <0 0x80280000 0 0x1000>, + <0 0x81280000 0 0x9000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + gic: interrupt-controller@83000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x83000000 0 0x40000>, + <0x0 0x83040000 0 0x160000>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi new file mode 100644 index 000000000000..6f4a11b39d12 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/T2H 4-core SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a09g077.dtsi" + +/ { + compatible = "renesas,r9a09g077m44", "renesas,r9a09g077"; +}; From a38f991fa19cb0d9375a95e04ccc93e7aaed4d34 Mon Sep 17 00:00:00 2001 From: Thierry Bultel Date: Tue, 17 Jun 2025 17:28:10 +0100 Subject: [PATCH 063/931] arm64: dts: renesas: Add initial support for the Renesas RZ/T2H eval board Add the initial device tree for the RZ/T2H evaluation board. Signed-off-by: Thierry Bultel Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250617162810.154332-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 ++ .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 31 +++++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 6093d5f6e548..89acad605c2d 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -180,5 +180,7 @@ r9a09g057h44-rzv2h-evk-cn15-sd-dtbs := r9a09g057h44-rzv2h-evk.dtb rzv2-evk-cn15- dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk-cn15-sd.dtb dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb +dtb-$(CONFIG_ARCH_R9A09G077) += r9a09g077m44-rzt2h-evk.dtb + dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts new file mode 100644 index 000000000000..752d4c9f2cae --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/T2H EVK board + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a09g077m44.dtsi" + +/ { + model = "Renesas RZ/T2H EVK Board based on r9a09g077m44"; + compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077"; + + aliases { + serial0 = &sci0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&extal_clk { + clock-frequency = <25000000>; +}; + +&sci0 { + status = "okay"; +}; From 4b3d31f0b81fefae5874467081496467af0f05a7 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 17 Jun 2025 18:19:54 +0100 Subject: [PATCH 064/931] arm64: dts: renesas: Add initial SoC DTSI for the RZ/N2H SoC Add the initial SoC DTSI for the Renesas RZ/N2H ("R9A09G087") SoC, below is the list of blocks added: - EXT CLKs - 4x CA55 - SCIF - CPG - GIC - ARMv8 Timer Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250617171957.162145-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 124 +++++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi new file mode 100644 index 000000000000..e57a91adcb68 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/N2H SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a09g087"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a55"; + reg = <0x200>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a55"; + reg = <0x300>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x100000>; + cache-level = <3>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sci0: serial@80005000 { + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; + reg = <0 0x80005000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + cpg: clock-controller@80280000 { + compatible = "renesas,r9a09g087-cpg-mssr"; + reg = <0 0x80280000 0 0x1000>, + <0 0x81280000 0 0x9000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + gic: interrupt-controller@83000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x83000000 0 0x40000>, + <0x0 0x83040000 0 0x160000>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; From 8989230e80113e2bd2f322fba6922f9a3252e9c0 Mon Sep 17 00:00:00 2001 From: Paul Barker Date: Tue, 17 Jun 2025 18:19:55 +0100 Subject: [PATCH 065/931] arm64: dts: renesas: Refactor RZ/T2H EVK device tree The RZ/T2H EVK and RZ/N2H EVK are very similar boards. As there is so much overlap between these parts, common device tree entries are moved to the new file rzt2h-n2h-evk-common.dtsi. Signed-off-by: Paul Barker Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250617171957.162145-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 17 +------------ .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 24 +++++++++++++++++++ 2 files changed, 25 insertions(+), 16 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 752d4c9f2cae..486584fefead 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -8,24 +8,9 @@ /dts-v1/; #include "r9a09g077m44.dtsi" +#include "rzt2h-n2h-evk-common.dtsi" / { model = "Renesas RZ/T2H EVK Board based on r9a09g077m44"; compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077"; - - aliases { - serial0 = &sci0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&extal_clk { - clock-frequency = <25000000>; -}; - -&sci0 { - status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi new file mode 100644 index 000000000000..5f17996bcd6b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Common Device Tree Source for the RZ/T2H and RZ/N2H EVK boards. + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/ { + aliases { + serial0 = &sci0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&extal_clk { + clock-frequency = <25000000>; +}; + +&sci0 { + status = "okay"; +}; From bddf6ae4f51755b31ad85906331f4bd4ded7632c Mon Sep 17 00:00:00 2001 From: Paul Barker Date: Tue, 17 Jun 2025 18:19:56 +0100 Subject: [PATCH 066/931] arm64: dts: renesas: Add DTSI for R9A09G087M44 variant of RZ/N2H Add the device tree source include file for the R9A09G087M44 variant of the Renesas RZ/N2H SoC, which features a 4-core configuration. Signed-off-by: Paul Barker Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250617171957.162145-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi new file mode 100644 index 000000000000..ef0343b53309 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/N2H 4-core SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a09g087.dtsi" + +/ { + compatible = "renesas,r9a09g087m44", "renesas,r9a09g087"; +}; From 8d0b6ca38f942292d9c1ae557150c58eaae63052 Mon Sep 17 00:00:00 2001 From: Paul Barker Date: Tue, 17 Jun 2025 18:19:57 +0100 Subject: [PATCH 067/931] arm64: dts: renesas: Add initial support for the RZ/N2H EVK Add an initial device tree file for the Renesas RZ/N2H Evaluation Board (EVK). Signed-off-by: Paul Barker Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250617171957.162145-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 ++ .../boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 89acad605c2d..d8c923762466 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -182,5 +182,7 @@ dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb dtb-$(CONFIG_ARCH_R9A09G077) += r9a09g077m44-rzt2h-evk.dtb +dtb-$(CONFIG_ARCH_R9A09G087) += r9a09g087m44-rzn2h-evk.dtb + dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts new file mode 100644 index 000000000000..d6ba14a26f03 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/N2H EVK board + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a09g087m44.dtsi" +#include "rzt2h-n2h-evk-common.dtsi" + +/ { + model = "Renesas RZ/N2H EVK Board based on r9a09g087m44"; + compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087"; +}; From c494de2e00fb06d5b62708a91d7dda701abc52f4 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Tue, 24 Jun 2025 20:23:04 +0100 Subject: [PATCH 068/931] arm64: dts: renesas: r9a09g057: Add RSPI nodes Add nodes for the RSPI IPs found in the Renesas RZ/V2H(P) SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250624192304.338979-7-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 044f2a22f161..6d0c6449b9ff 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -607,6 +607,69 @@ scif: serial@11c01400 { status = "disabled"; }; + rspi0: spi@12800000 { + compatible = "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800000 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x54>, + <&cpg CPG_MOD 0x55>, + <&cpg CPG_MOD 0x56>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7b>, <&cpg 0x7c>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi1: spi@12800400 { + compatible = "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800400 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x57>, + <&cpg CPG_MOD 0x58>, + <&cpg CPG_MOD 0x59>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7d>, <&cpg 0x7e>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi2: spi@12800800 { + compatible = "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800800 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x5a>, + <&cpg CPG_MOD 0x5b>, + <&cpg CPG_MOD 0x5c>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7f>, <&cpg 0x80>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; From 33450878adfc9d6bfd9cd2da2135b7fd33f2a4fe Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 11 Aug 2025 14:25:17 +0200 Subject: [PATCH 069/931] arm64: dts: qcom: sm8550: Flatten the USB nodes Transition the USB controllers found in the SM8550 SoC to the newly introduced, flattened representation of the Qualcomm USB block. The reg and interrupts properties from the usb child node are merged with their counterpart in the outer node, remaining properties and child nodes are simply moved. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250811-topic-sm8x50-usb-flatten-v2-1-0bbb3ac292e4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 84 ++++++++++++++-------------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index a4ca06679c2f..38d139d1dd4a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -4084,12 +4084,11 @@ usb_dp_qmpphy_dp_in: endpoint { }; }; - usb_1: usb@a6f8800 { - compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; - reg = <0x0 0x0a6f8800 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_1: usb@a600000 { + compatible = "qcom,sm8550-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -4108,12 +4107,14 @@ usb_1: usb@a6f8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", @@ -4130,47 +4131,46 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "usb-ddr", "apps-usb"; + iommus = <&apps_smmu 0x40 0x0>; + + phys = <&usb_1_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + + dma-coherent; + + usb-role-switch; + status = "disabled"; - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0x0 0x0a600000 0x0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x40 0x0>; - phys = <&usb_1_hsphy>, - <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", "usb3-phy"; - snps,hird-threshold = /bits/ 8 <0x0>; - snps,usb2-gadget-lpm-disable; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,is-utmi-l1-suspend; - snps,usb3_lpm_capable; - snps,usb2-lpm-disable; - snps,has-lpm-erratum; - tx-fifo-resize; - dma-coherent; - usb-role-switch; + ports { + #address-cells = <1>; + #size-cells = <0>; - ports { - #address-cells = <1>; - #size-cells = <0>; + port@0 { + reg = <0>; - port@0 { - reg = <0>; - - usb_1_dwc3_hs: endpoint { - }; + usb_1_dwc3_hs: endpoint { }; + }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - usb_1_dwc3_ss: endpoint { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; - }; + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; }; }; From 77e1f16b930221b427ec24c634703388a64175af Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 11 Aug 2025 14:25:18 +0200 Subject: [PATCH 070/931] arm64: dts: qcom: sm8650: Flatten the USB nodes Transition the USB controllers found in the SM8650 SoC to the newly introduced, flattened representation of the Qualcomm USB block. The reg and interrupts properties from the usb child node are merged with their counterpart in the outer node, remaining properties and child nodes are simply moved. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250811-topic-sm8x50-usb-flatten-v2-2-0bbb3ac292e4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 6 +- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 6 +- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 6 +- arch/arm64/boot/dts/qcom/sm8650.dtsi | 88 ++++++++++++------------- 4 files changed, 47 insertions(+), 59 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 259649d7dcd7..a00da76a6062 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -1310,12 +1310,10 @@ &ufs_mem_phy { */ &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 8a957adbfb38..c67bbace2743 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -857,12 +857,10 @@ &ufs_mem_phy { */ &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 7552d5d3fb40..081b7e40f574 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -1293,12 +1293,10 @@ &ufs_mem_phy { */ &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index e14d3d778b71..bcafd9cf3eae 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5651,16 +5651,18 @@ usb_dp_qmpphy_dp_in: endpoint { }; }; - usb_1: usb@a6f8800 { - compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; + usb_1: usb@a600000 { + compatible = "qcom,sm8650-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a600000 0 0xfc100>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 14 IRQ_TYPE_EDGE_RISING>, <&pdc 15 IRQ_TYPE_EDGE_RISING>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", @@ -5685,6 +5687,11 @@ usb_1: usb@a6f8800 { resets = <&gcc GCC_USB30_PRIM_BCR>; + phys = <&usb_1_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -5692,59 +5699,46 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "usb-ddr", "apps-usb"; + iommus = <&apps_smmu 0x40 0>; + power-domains = <&gcc USB30_PRIM_GDSC>; required-opps = <&rpmhpd_opp_nom>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + + dma-coherent; + + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; + ports { + #address-cells = <1>; + #size-cells = <0>; - interrupts = ; + port@0 { + reg = <0>; - iommus = <&apps_smmu 0x40 0>; - - phys = <&usb_1_hsphy>, - <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", - "usb3-phy"; - - snps,hird-threshold = /bits/ 8 <0x0>; - snps,usb2-gadget-lpm-disable; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,is-utmi-l1-suspend; - snps,usb3_lpm_capable; - snps,usb2-lpm-disable; - snps,has-lpm-erratum; - tx-fifo-resize; - - dma-coherent; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_1_dwc3_hs: endpoint { - }; + usb_1_dwc3_hs: endpoint { }; + }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - usb_1_dwc3_ss: endpoint { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; - }; + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; }; }; From c17ccefb611fdb346eef9be6bfbd0bfd04afa204 Mon Sep 17 00:00:00 2001 From: Sricharan Ramabadhran Date: Mon, 11 Aug 2025 14:39:51 +0530 Subject: [PATCH 071/931] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller The CPU core in ipq5424 is clocked by a huayra PLL with RCG support. The RCG and PLL have a separate register space from the GCC. Also the L3 cache has a separate pll and needs to be scaled along with the CPU. Co-developed-by: Md Sadre Alam Signed-off-by: Md Sadre Alam Signed-off-by: Sricharan Ramabadhran [ Added interconnect related changes ] Reviewed-by: Krzysztof Kozlowski Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/20250811090954.2854440-2-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,ipq5424-apss-clk.yaml | 55 +++++++++++++++++++ include/dt-bindings/clock/qcom,apss-ipq.h | 6 ++ .../dt-bindings/interconnect/qcom,ipq5424.h | 3 + 3 files changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml new file mode 100644 index 000000000000..def739fa0a8c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm APSS IPQ5424 Clock Controller + +maintainers: + - Varadarajan Narayanan + +description: + The CPU core in ipq5424 is clocked by a huayra PLL with RCG support. + The RCG and PLL have a separate register space from the GCC. + +properties: + compatible: + enum: + - qcom,ipq5424-apss-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference to the XO clock. + - description: Reference to the GPLL0 clock. + + '#clock-cells': + const: 1 + + '#interconnect-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + #include + + apss_clk: clock-controller@fa80000 { + compatible = "qcom,ipq5424-apss-clk"; + reg = <0x0fa80000 0x20000>; + clocks = <&xo_board>, + <&gcc GPLL0>; + #clock-cells = <1>; + #interconnect-cells = <1>; + }; diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h index 77b6e05492e2..0bb41e5efdef 100644 --- a/include/dt-bindings/clock/qcom,apss-ipq.h +++ b/include/dt-bindings/clock/qcom,apss-ipq.h @@ -8,5 +8,11 @@ #define APCS_ALIAS0_CLK_SRC 0 #define APCS_ALIAS0_CORE_CLK 1 +#define APSS_PLL_EARLY 2 +#define APSS_SILVER_CLK_SRC 3 +#define APSS_SILVER_CORE_CLK 4 +#define L3_PLL 5 +#define L3_CLK_SRC 6 +#define L3_CORE_CLK 7 #endif diff --git a/include/dt-bindings/interconnect/qcom,ipq5424.h b/include/dt-bindings/interconnect/qcom,ipq5424.h index a770356112ee..afd7e0683a24 100644 --- a/include/dt-bindings/interconnect/qcom,ipq5424.h +++ b/include/dt-bindings/interconnect/qcom,ipq5424.h @@ -21,4 +21,7 @@ #define MASTER_CNOC_USB 16 #define SLAVE_CNOC_USB 17 +#define MASTER_CPU 0 +#define SLAVE_L3 1 + #endif /* INTERCONNECT_QCOM_IPQ5424_H */ From b261da9e9ed8d7bfae7f34940a338750900e9b09 Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Sun, 22 Jun 2025 18:26:38 +0000 Subject: [PATCH 072/931] ARM: dts: qcom: msm8960: add sdcc3 pinctrl states Adds sdcc3-default-state and sdcc3-sleep-state pinctrl states for MSM8960. These are required for devices like Sony Xperia SP to ensure micro SD card functionality, though they are a no-op on the Samsung Galaxy Express. Tested-by: Rudraksha Gupta Signed-off-by: Antony Kurniawan Soemardi Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250623-msm8960-sdcard-v2-1-340a5e8f7df0@smankusors.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8960-pins.dtsi | 40 +++++++++++++++++++ .../qcom/qcom-msm8960-samsung-expressatt.dts | 5 +++ 2 files changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-pins.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960-pins.dtsi index 4fa982771288..f18753e9f5ef 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-pins.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-pins.dtsi @@ -18,4 +18,44 @@ i2c3-pins { bias-bus-hold; }; }; + + sdcc3_default_state: sdcc3-default-state { + clk-pins { + pins = "sdc3_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "sdc3_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "sdc3_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + sdcc3_sleep_state: sdcc3-sleep-state { + clk-pins { + pins = "sdc3_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc3_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc3_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts index af6cc6393d74..49d117ea033a 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts @@ -71,6 +71,11 @@ &sdcc1 { &sdcc3 { vmmc-supply = <&pm8921_l6>; vqmmc-supply = <&pm8921_l7>; + + pinctrl-0 = <&sdcc3_default_state>; + pinctrl-1 = <&sdcc3_sleep_state>; + pinctrl-names = "default", "sleep"; + status = "okay"; }; From 12bf7cfb5ad4e278ac555f209f2b18d81fb4783f Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Sun, 22 Jun 2025 18:26:41 +0000 Subject: [PATCH 073/931] ARM: dts: qcom: msm8960: add gsbi8 and its serial configuration The LTE variant of the MSM8960 SoC has a gsbi8 node used for the serial console. That's if the downstream kernel is to be believed, as Xperia SP has a serial console on gsbi8 even on the non-LTE variant. Signed-off-by: Antony Kurniawan Soemardi Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250623-msm8960-sdcard-v2-2-340a5e8f7df0@smankusors.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 28 ++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 203f0b69b353..cf0b1da230f1 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -333,6 +333,34 @@ gsbi5_serial: serial@16440000 { }; }; + gsbi8: gsbi@1a000000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <8>; + reg = <0x1a000000 0x100>; + clocks = <&gcc GSBI8_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + + status = "disabled"; + + gsbi8_serial: serial@1a040000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x1a040000 0x1000>, + <0x1a000000 0x1000>; + interrupts = ; + clocks = <&gcc GSBI8_UART_CLK>, + <&gcc GSBI8_H_CLK>; + clock-names = "core", + "iface"; + + status = "disabled"; + }; + }; + ssbi: ssbi@500000 { compatible = "qcom,ssbi"; reg = <0x500000 0x1000>; From 45f5d1dc6ff3b2b80e92071b507bee77c86f6ad6 Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Sun, 22 Jun 2025 18:26:44 +0000 Subject: [PATCH 074/931] ARM: dts: qcom: msm8960: disable gsbi1 and gsbi5 nodes in msm8960 dtsi Not all devices use gsbi1 and gsbi5, so these nodes should be disabled in the SoC dtsi, following the existing pattern used for gsbi3. The upstream samsung-expressatt and msm8960-cdp devices already have status "okay" for these nodes, so this change should not break existing functionality. This eliminates the following error messages when gsbi nodes are not configured in the board's device tree: [ 1.109723] gsbi 16000000.gsbi: missing mode configuration [ 1.109797] gsbi 16000000.gsbi: probe with driver gsbi failed with error -22 (Note: Xperia SP doesn't use gsbi5) Signed-off-by: Antony Kurniawan Soemardi Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250623-msm8960-sdcard-v2-3-340a5e8f7df0@smankusors.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index cf0b1da230f1..6e272d5345a8 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -322,6 +322,8 @@ gsbi5: gsbi@16400000 { syscon-tcsr = <&tcsr>; + status = "disabled"; + gsbi5_serial: serial@16440000 { compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16440000 0x1000>, @@ -445,6 +447,8 @@ gsbi1: gsbi@16000000 { #size-cells = <1>; ranges; + status = "disabled"; + gsbi1_spi: spi@16080000 { compatible = "qcom,spi-qup-v1.1.1"; #address-cells = <1>; From 450a80623e3b8bb5dae59e0d56046fc3d0a88f3b Mon Sep 17 00:00:00 2001 From: Sricharan Ramabadhran Date: Thu, 12 Jun 2025 10:46:14 +0400 Subject: [PATCH 075/931] arm64: dts: qcom: ipq5018: Add tsens node IPQ5018 has tsens V1.0 IP with 5 sensors, though 4 are in use. There is no RPM, so tsens has to be manually enabled. Adding the tsens and nvmem nodes and adding 4 thermal sensors (zones). The critical trip temperature is set to 120'C with an action to reboot. In addition, adding a cooling device to the CPU thermal zone which uses CPU frequency scaling. Reviewed-by: Dmitry Baryshkov Signed-off-by: Sricharan Ramabadhran Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio [bjorn: Added tsens-v1 fallback compatible, per binding] Link: https://lore.kernel.org/r/20250612-ipq5018-tsens-v13-2-a210f3683240@outlook.com --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 178 ++++++++++++++++++++++++++ 1 file changed, 178 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 130360014c5e..baf583c75e76 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -39,6 +40,7 @@ cpu0: cpu@0 { next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -49,6 +51,7 @@ cpu1: cpu@1 { next-level-cache = <&l2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; l2_0: l2-cache { @@ -182,6 +185,117 @@ pcie0_phy: phy@86000 { status = "disabled"; }; + qfprom: qfprom@a0000 { + compatible = "qcom,ipq5018-qfprom", "qcom,qfprom"; + reg = <0x000a0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + tsens_mode: mode@249 { + reg = <0x249 0x1>; + bits = <0 3>; + }; + + tsens_base1: base1@249 { + reg = <0x249 0x2>; + bits = <3 8>; + }; + + tsens_base2: base2@24a { + reg = <0x24a 0x2>; + bits = <3 8>; + }; + + tsens_s0_p1: s0-p1@24b { + reg = <0x24b 0x2>; + bits = <2 6>; + }; + + tsens_s0_p2: s0-p2@24c { + reg = <0x24c 0x1>; + bits = <1 6>; + }; + + tsens_s1_p1: s1-p1@24c { + reg = <0x24c 0x2>; + bits = <7 6>; + }; + + tsens_s1_p2: s1-p2@24d { + reg = <0x24d 0x2>; + bits = <5 6>; + }; + + tsens_s2_p1: s2-p1@24e { + reg = <0x24e 0x2>; + bits = <3 6>; + }; + + tsens_s2_p2: s2-p2@24f { + reg = <0x24f 0x1>; + bits = <1 6>; + }; + + tsens_s3_p1: s3-p1@24f { + reg = <0x24f 0x2>; + bits = <7 6>; + }; + + tsens_s3_p2: s3-p2@250 { + reg = <0x250 0x2>; + bits = <5 6>; + }; + + tsens_s4_p1: s4-p1@251 { + reg = <0x251 0x2>; + bits = <3 6>; + }; + + tsens_s4_p2: s4-p2@254 { + reg = <0x254 0x1>; + bits = <0 6>; + }; + }; + + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, + <0x004a8000 0x1000>; + + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, + <&tsens_base2>, + <&tsens_s0_p1>, + <&tsens_s0_p2>, + <&tsens_s1_p1>, + <&tsens_s1_p2>, + <&tsens_s2_p1>, + <&tsens_s2_p2>, + <&tsens_s3_p1>, + <&tsens_s3_p2>, + <&tsens_s4_p1>, + <&tsens_s4_p2>; + + nvmem-cell-names = "mode", + "base1", + "base2", + "s0_p1", + "s0_p2", + "s1_p1", + "s1_p2", + "s2_p1", + "s2_p2", + "s3_p1", + "s3_p2", + "s4_p1", + "s4_p2"; + + interrupts = ; + interrupt-names = "uplow"; + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>; @@ -631,6 +745,70 @@ pcie@0 { }; }; + thermal-zones { + cpu-thermal { + thermal-sensors = <&tsens 2>; + + trips { + cpu-critical { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + + cpu_alert: cpu-passive { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gephy-thermal { + thermal-sensors = <&tsens 4>; + + trips { + gephy-critical { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + top-glue-thermal { + thermal-sensors = <&tsens 3>; + + trips { + top-glue-critical { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ubi32-thermal { + thermal-sensors = <&tsens 1>; + + trips { + ubi32-critical { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From e08d75e4834cb9a6224bfa090fce0e6259113d7a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 21 Jun 2025 21:20:02 +0300 Subject: [PATCH 076/931] arm64: dts: qcom: sdm845: rename DisplayPort labels Rename DP labels to have mdss_ prefix, so that corresponding device nodes are grouped together. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250621-sdm845-dp-rename-v1-1-6f7f13443b43@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index c0f466d96630..2311ebd515d7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4089,7 +4089,7 @@ port@2 { reg = <2>; usb_1_qmpphy_dp_in: endpoint { - remote-endpoint = <&dp_out>; + remote-endpoint = <&mdss_dp_out>; }; }; }; @@ -4603,7 +4603,7 @@ ports { port@0 { reg = <0>; dpu_intf0_out: endpoint { - remote-endpoint = <&dp_in>; + remote-endpoint = <&mdss_dp_in>; }; }; @@ -4682,14 +4682,14 @@ ports { #size-cells = <0>; port@0 { reg = <0>; - dp_in: endpoint { + mdss_dp_in: endpoint { remote-endpoint = <&dpu_intf0_out>; }; }; port@1 { reg = <1>; - dp_out: endpoint { + mdss_dp_out: endpoint { remote-endpoint = <&usb_1_qmpphy_dp_in>; }; }; From 5bde57b9cd3c769f5f4c85c021c37e2d151ca228 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 18 Jun 2025 20:49:51 +0300 Subject: [PATCH 077/931] arm64: dts: qcom: sar2130p: use TAG_ALWAYS for MDSS's mdp0-mem path Switch the main memory interconnect of the MDSS device to use QCOM_ICC_TAG_ALWAYS instead of _ACTIVE_ONLY. Fixes: 541d0b2f4dcd ("arm64: dts: qcom: sar2130p: add display nodes") Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250618-sar2130p-fix-mdss-v1-1-78c2fb9e9fba@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index e400ea4cdee8..6d7d4f05d502 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -2036,8 +2036,8 @@ mdss: display-subsystem@ae00000 { power-domains = <&dispcc MDSS_GDSC>; - interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ACTIVE_ONLY - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "mdp0-mem", "cpu-cfg"; From b1f622224b8e5da3d08dac33ad76b0672c21eded Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 18 Jun 2025 20:49:52 +0300 Subject: [PATCH 078/931] arm64: dts: qcom: sar2130p: correct VBIF region size for MDSS Correct the VBIF region size for the display device on the SAR1230P platform. Fixes: 541d0b2f4dcd ("arm64: dts: qcom: sar2130p: add display nodes") Reported-by: Konrad Dybcio Closes: https://lore.kernel.org/all/c14dfd37-7d12-40c3-8281-fd0a7410813e@oss.qualcomm.com/ Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250618-sar2130p-fix-mdss-v1-2-78c2fb9e9fba@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index 6d7d4f05d502..d9948360cc01 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -2053,7 +2053,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, mdss_mdp: display-controller@ae01000 { compatible = "qcom,sar2130p-dpu"; reg = <0x0 0x0ae01000 0x0 0x8f000>, - <0x0 0x0aeb0000 0x0 0x2008>; + <0x0 0x0aeb0000 0x0 0x3000>; reg-names = "mdp", "vbif"; From e2a01c3b1033ae39c2153ab5e84ae7167016826c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 18 Jun 2025 20:49:53 +0300 Subject: [PATCH 079/931] arm64: dts: qcom: sar2130p: use defines for DSI PHY clocks Use defined IDs to reference DSI PHY clocks instead of using raw numbers. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250618-sar2130p-fix-mdss-v1-3-78c2fb9e9fba@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index d9948360cc01..38f7869616ff 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2024, Linaro Limited */ +#include #include #include #include @@ -2237,8 +2238,8 @@ mdss_dsi0: dsi@ae94000 { assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&mdss_dsi_opp_table>; @@ -2333,8 +2334,8 @@ mdss_dsi1: dsi@ae96000 { assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>; + assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&mdss_dsi_opp_table>; @@ -2392,10 +2393,10 @@ dispcc: clock-controller@af00000 { <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GCC_DISP_AHB_CLK>, <&sleep_clk>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <0>, /* dp1 */ From c02716951e665181aecf59c663622689a576bccb Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 8 Jun 2025 19:16:05 +0300 Subject: [PATCH 080/931] arm64: dts: qcom: sdm850-lenovo-yoga-c630: add routing for second USB connector On Lenovo Yoga C630 second (left) Type-C port is not connected to the SoC directly. Instead it has a USB hub, which also powers on the onboard USB camera. Describe these signal lines properly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250608-c630-ports-v1-1-e4951db96efa@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 104 +++++++++++++++++- 1 file changed, 102 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 8ef6db3be6e3..480192c86fb7 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -421,9 +421,46 @@ connector@1 { data-role = "host"; /* - * connected to the onboard USB hub, orientation is - * handled by the controller + * connected to the onboard USB hub, each pair of lanes + * (and D+/D- pair) is connected to a separate port on + * the hub. */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + ucsi1_hs_in_1: endpoint@1 { + reg = <1>; + remote-endpoint = <&usb_hub_2_1>; + }; + + ucsi1_hs_in_2: endpoint@2 { + reg = <2>; + remote-endpoint = <&usb_hub_2_2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ucsi1_ss_in_1: endpoint@1 { + reg = <1>; + remote-endpoint = <&usb_hub_3_1>; + }; + + ucsi1_ss_in_2: endpoint@2 { + reg = <2>; + remote-endpoint = <&usb_hub_3_2>; + }; + }; + }; }; }; }; @@ -842,6 +879,69 @@ &usb_2 { &usb_2_dwc3 { dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + + usb_hub_2_x: hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + peer-hub = <&usb_hub_3_x>; + #address-cells = <1>; + #size-cells = <0>; + + camera@3 { + compatible = "usb4f2,b61e"; + reg = <3>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_hub_2_1: endpoint { + remote-endpoint = <&ucsi1_hs_in_1>; + }; + }; + + port@2 { + reg = <2>; + + usb_hub_2_2: endpoint { + remote-endpoint = <&ucsi1_hs_in_2>; + }; + }; + }; + }; + + usb_hub_3_x: hub@2 { + compatible = "usb5e3,620"; + reg = <2>; + peer-hub = <&usb_hub_2_x>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_hub_3_1: endpoint { + remote-endpoint = <&ucsi1_ss_in_1>; + }; + }; + + port@2 { + reg = <2>; + + usb_hub_3_2: endpoint { + remote-endpoint = <&ucsi1_ss_in_2>; + }; + }; + }; + }; }; &usb_2_hsphy { From 0403e42f2fbb43fe38d645fb399727327e1002c6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 2 Jun 2025 10:23:35 +0300 Subject: [PATCH 081/931] arm64: dts: qcom: sa8775p: rename bus clock to follow the bindings DT bindings for the DPU SA8775P declare the first clock to be "nrt_bus", not just "bus". Fix the DT file accordingly. Fixes: 2f39d2d46c73 ("arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250602-sa8775p-fix-dts-v1-1-f9f6271b33a3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 0a9c92aa7234..322abd0294be 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4417,7 +4417,7 @@ mdss0_mdp: display-controller@ae01000 { <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", + clock-names = "nrt_bus", "iface", "lut", "core", From 3e0252ea5d91ac21c6b606f71f42733b526646df Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 4 Jun 2025 16:40:28 +0300 Subject: [PATCH 082/931] dt-bindings: arm: qcom: add qcom,sm6150 fallback compatible to QCS615 QCS615 SoC is based on the earlier mobile chip SM6150. Add corresponding compatible string to follow established practice for IoT chips. Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250604-qcs615-sm6150-v1-1-2f01fd46c365@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index bf5f3beb320b..1b705079c1ae 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -87,6 +87,7 @@ description: | sm6115 sm6115p sm6125 + sm6150 sm6350 sm6375 sm7125 @@ -949,6 +950,7 @@ properties: - enum: - qcom,qcs615-ride - const: qcom,qcs615 + - const: qcom,sm6150 - items: - enum: From 9af4e5351229a4364030c6102babc6af831fbb84 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 4 Jun 2025 16:40:29 +0300 Subject: [PATCH 083/931] arm64: dts: qcom: rename qcs615.dtsi to sm6150.dtsi The established practice is to have the base DTSI file named after the base SoC name (see examples of qrb5165-rb5.dts vs sm8250.dtsi, qrb2210-rb1.dts vs qcm2290.dtsi, qrb4210-rb2.dts vs sm4250.dtsi vs sm6115.dtsi). Rename the SoC dtsi file accordingly and add "qcom,sm6150" as a fallback compat string. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250604-qcs615-sm6150-v1-2-2f01fd46c365@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 4 ++-- arch/arm64/boot/dts/qcom/{qcs615.dtsi => sm6150.dtsi} | 0 2 files changed, 2 insertions(+), 2 deletions(-) rename arch/arm64/boot/dts/qcom/{qcs615.dtsi => sm6150.dtsi} (100%) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index a6652e4817d1..fdad6388f6f7 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -7,11 +7,11 @@ #include #include #include -#include "qcs615.dtsi" +#include "sm6150.dtsi" #include "pm8150.dtsi" / { model = "Qualcomm Technologies, Inc. QCS615 Ride"; - compatible = "qcom,qcs615-ride", "qcom,qcs615"; + compatible = "qcom,qcs615-ride", "qcom,qcs615", "qcom,sm6150"; chassis-type = "embedded"; aliases { diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi similarity index 100% rename from arch/arm64/boot/dts/qcom/qcs615.dtsi rename to arch/arm64/boot/dts/qcom/sm6150.dtsi From 8ff47ada5e95577fdb8a1da903d37c75636808e6 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 14 Jun 2025 21:05:19 +0200 Subject: [PATCH 084/931] arm64: dts: qcom: msm8916: Drop venus-enc/decoder node Commit 687bfbba5a1c ("media: venus: Add support for static video encoder/decoder declarations") invalidates these empty nodes. Get rid of them. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250614-topic-encdec-v1-1-f974c3e9cb43@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index de9fdc0dfc5f..b50c7e6e0bfc 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1834,14 +1834,6 @@ venus: video-codec@1d00000 { iommus = <&apps_iommu 5>; memory-region = <&venus_mem>; status = "disabled"; - - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; }; apps_iommu: iommu@1ef0000 { From 1f67c23f98bd64d4034898af5a149304a09080be Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 14 Jun 2025 21:05:20 +0200 Subject: [PATCH 085/931] arm64: dts: qcom: sc7180: Drop venus-enc/decoder node Commit 687bfbba5a1c ("media: venus: Add support for static video encoder/decoder declarations") invalidates these empty nodes. Get rid of them. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250614-topic-encdec-v1-2-f974c3e9cb43@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 3afb69921be3..8f827f1d8515 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3095,14 +3095,6 @@ venus: video-codec@aa00000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; interconnect-names = "video-mem", "cpu-cfg"; - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; - venus_opp_table: opp-table { compatible = "operating-points-v2"; From dce1122f076c7f4acc809cd2c9b7e3ed3fe19a4c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 14 Jun 2025 21:05:21 +0200 Subject: [PATCH 086/931] arm64: dts: qcom: sdm845: Drop venus-enc/decoder node Commit 687bfbba5a1c ("media: venus: Add support for static video encoder/decoder declarations") invalidates these empty nodes. Get rid of them. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250614-topic-encdec-v1-3-f974c3e9cb43@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2311ebd515d7..828b55cb6baf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4286,14 +4286,6 @@ venus: video-codec@aa00000 { status = "disabled"; - video-core0 { - compatible = "venus-decoder"; - }; - - video-core1 { - compatible = "venus-encoder"; - }; - venus_opp_table: opp-table { compatible = "operating-points-v2"; From 71ef5e99e925fc4e3f8bfd071a546c4dd6b45825 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 14 Jun 2025 21:05:22 +0200 Subject: [PATCH 087/931] arm64: dts: qcom: sm8250: Drop venus-enc/decoder node Commit 687bfbba5a1c ("media: venus: Add support for static video encoder/decoder declarations") invalidates these empty nodes. Get rid of them. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250614-topic-encdec-v1-4-f974c3e9cb43@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 2b3442a74a5a..244339cfbed5 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4338,14 +4338,6 @@ venus: video-codec@aa00000 { status = "disabled"; - video-decoder { - compatible = "venus-decoder"; - }; - - video-encoder { - compatible = "venus-encoder"; - }; - venus_opp_table: opp-table { compatible = "operating-points-v2"; From 1aa0b4e364361ccaf047a34308527ccf7441feef Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Mon, 23 Jun 2025 19:42:09 +0530 Subject: [PATCH 088/931] arm64: dts: qcom: x1p42100: Add GPU support X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller version of Adreno X1-85 GPU. Describe this new GPU and also add the secure gpu firmware path that should used for X1P42100 CRD. Tested-by: Jens Glathe Reviewed-by: Konrad Dybcio Tested-by: Aleksandrs Vinarskis # x1-26-100 Signed-off-by: Akhil P Oommen Link: https://lore.kernel.org/r/20250623-x1p-adreno-v4-4-d2575c839cbb@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 7 ++ arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 4 + arch/arm64/boot/dts/qcom/x1p42100.dtsi | 120 +++++++++++++++++++++- 3 files changed, 129 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index a9a7bb676c6f..5e9a8fa3cf96 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -8251,6 +8251,13 @@ sbsa_watchdog: watchdog@1c840000 { interrupts = ; }; + qfprom: efuse@221c8000 { + compatible = "qcom,x1e80100-qfprom", "qcom,qfprom"; + reg = <0 0x221c8000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + pmu@24091000 { compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0 0x24091000 0 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts index cf07860a63e9..cf999c2cf8d4 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts @@ -15,3 +15,7 @@ / { model = "Qualcomm Technologies, Inc. X1P42100 CRD"; compatible = "qcom,x1p42100-crd", "qcom,x1p42100"; }; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/gen71500_zap.mbn"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi index 9af9e707f982..b7326be4d064 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi @@ -17,6 +17,7 @@ /delete-node/ &cpu_pd9; /delete-node/ &cpu_pd10; /delete-node/ &cpu_pd11; +/delete-node/ &gpu_opp_table; /delete-node/ &pcie3_phy; /delete-node/ &thermal_zones; @@ -24,9 +25,117 @@ &gcc { compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc"; }; -/* The GPU is physically different and will be brought up later */ +&gmu { + compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu"; +}; + &gpu { - /delete-property/ compatible; + compatible = "qcom,adreno-43030c00", "qcom,adreno"; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2-adreno", "operating-points-v2"; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0xa8295ffd>; + opp-supported-hw = <0x3>; + }; + + opp-1250000000 { + opp-hz = /bits/ 64 <1250000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0x882a5ffd>; + opp-supported-hw = <0x7>; + }; + + opp-1107000000 { + opp-hz = /bits/ 64 <1107000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0x882a5ffd>; + opp-supported-hw = <0xf>; + }; + + opp-1014000000 { + opp-hz = /bits/ 64 <1014000000>; + opp-level = ; + opp-peak-kBps = <14398438>; + qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0xf>; + }; + + opp-940000000 { + opp-hz = /bits/ 64 <940000000>; + opp-level = ; + opp-peak-kBps = <14398438>; + qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0xf>; + }; + + opp-825000000 { + opp-hz = /bits/ 64 <825000000>; + opp-level = ; + opp-peak-kBps = <12449219>; + qcom,opp-acd-level = <0x882b5ffd>; + opp-supported-hw = <0xf>; + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-level = ; + opp-peak-kBps = <10687500>; + qcom,opp-acd-level = <0xa82c5ffd>; + opp-supported-hw = <0xf>; + }; + + opp-666000000-0 { + opp-hz = /bits/ 64 <666000000>; + opp-level = ; + opp-peak-kBps = <8171875>; + qcom,opp-acd-level = <0xa82d5ffd>; + opp-supported-hw = <0xf>; + }; + + /* Only applicable for SKUs which has 666Mhz as Fmax */ + opp-666000000-1 { + opp-hz = /bits/ 64 <666000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0xa82d5ffd>; + opp-supported-hw = <0x10>; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = ; + opp-peak-kBps = <6074219>; + qcom,opp-acd-level = <0x882e5ffd>; + opp-supported-hw = <0x1f>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + opp-level = ; + opp-peak-kBps = <3000000>; + qcom,opp-acd-level = <0xc82f5ffd>; + opp-supported-hw = <0x1f>; + }; + + opp-280000000 { + opp-hz = /bits/ 64 <280000000>; + opp-level = ; + opp-peak-kBps = <2136719>; + qcom,opp-acd-level = <0xc82f5ffd>; + opp-supported-hw = <0x1f>; + }; + }; + }; &gpucc { @@ -42,6 +151,13 @@ &pcie6a_phy { compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; }; +&qfprom { + gpu_speed_bin: gpu-speed-bin@119 { + reg = <0x119 0x2>; + bits = <7 9>; + }; +}; + &soc { /* The PCIe3 PHY on X1P42100 uses a different IP block */ pcie3_phy: phy@1bd4000 { From ebf6fc452ad61f79d801f68f8298c7d00796c580 Mon Sep 17 00:00:00 2001 From: Jens Glathe Date: Tue, 24 Jun 2025 08:46:00 +0200 Subject: [PATCH 089/931] arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: add Bluetooth support To enable Bluetooth pwrseq appears to be required for the WCN7850. Add the nodes from QCP, add the TODO hint for vreg_wcn_0p95 and vreg_wcn_1p9 Add uart14 for the BT interface. Tested-by: Anthony Ruhier Signed-off-by: Jens Glathe Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250624-slim7x-bt-v3-1-7ada18058419@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson --- .../dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index dad0f11e8e85..d02f8d4f7baf 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -18,6 +18,7 @@ / { aliases { serial0 = &uart21; + serial1 = &uart14; }; chosen { @@ -404,6 +405,107 @@ vph_pwr: regulator-vph-pwr { regulator-always-on; regulator-boot-on; }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the CRD mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -1045,6 +1147,16 @@ &pcie4_port0 { wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; }; }; @@ -1403,6 +1515,37 @@ usb2_pwr_3p3_reg_en: usb2-pwr-3p3-reg-en-state { drive-strength = <2>; bias-disable; }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; }; &uart21 { From 6a5e9b9738a32229e2673d4eccfcbfe2ef3a1ab4 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Mon, 30 Jun 2025 12:13:38 +0530 Subject: [PATCH 090/931] arm64: dts: qcom: qcs615: add missing dt property in QUP SEs Add the missing required-opps and operating-points-v2 properties to several I2C, SPI, and UART nodes in the QUP SEs. Fixes: f6746dc9e379 ("arm64: dts: qcom: qcs615: Add QUPv3 configuration") Cc: stable@vger.kernel.org Signed-off-by: Viken Dadhaniya Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250630064338.2487409-1-viken.dadhaniya@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi index bfbb21035492..e033b53f0f0f 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -631,6 +631,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -654,6 +655,7 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", @@ -681,6 +683,7 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", @@ -703,6 +706,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, <&gpi_dma0 1 2 QCOM_GPI_SPI>; dma-names = "tx", @@ -728,6 +732,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "qup-core", "qup-config"; power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -751,6 +756,7 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, "qup-config", "qup-memory"; power-domains = <&rpmhpd RPMHPD_CX>; + required-opps = <&rpmhpd_opp_low_svs>; dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", From bbc5a9b5d9d91e9159be95856363979829ec0b80 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 1 May 2025 08:48:50 +0200 Subject: [PATCH 091/931] arm64: dts: qcom: sm6350: Add q6usbdai node Add a node for q6usb which handles USB audio offloading, allowing to play audio via a USB-C headset with lower power consumption and enabling some other features. We also need to set num-hc-interrupters for the dwc3 for the q6usb to be able to use its sideband interrupter. Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250501-fp4-usb-audio-offload-v2-4-30f4596281cd@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index ff1eb2c53e7b..c7230cdcf714 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1351,6 +1351,13 @@ q6afecc: clock-controller { compatible = "qcom,q6afe-clocks"; #clock-cells = <2>; }; + + q6usbdai: usbd { + compatible = "qcom,q6usb"; + iommus = <&apps_smmu 0x100f 0x0>; + #sound-dai-cells = <1>; + qcom,usb-audio-intr-idx = /bits/ 16 <2>; + }; }; q6asm: service@7 { @@ -1979,6 +1986,7 @@ usb_1_dwc3: usb@a600000 { reg = <0x0 0x0a600000 0x0 0xcd00>; interrupts = ; iommus = <&apps_smmu 0x540 0x0>; + num-hc-interrupters = /bits/ 16 <3>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,has-lpm-erratum; From 5ce2aa520d3f87e54338a3874a76139ad6341bc2 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 1 May 2025 08:48:51 +0200 Subject: [PATCH 092/931] arm64: dts: qcom: sm7225-fairphone-fp4: Enable USB audio offload support Enable USB audio offloading which allows to play audio via a USB-C headset with lower power consumption and enabling some other features. This can be used like the following: $ amixer -c0 cset name='USB_RX Audio Mixer MultiMedia1' On $ aplay --device=plughw:0,0 test.wav Compared to regular playback to the USB sound card no xhci-hcd interrupts appear during playback, instead the ADSP will be handling the USB transfers. Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250501-fp4-usb-audio-offload-v2-5-30f4596281cd@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 3 ++ .../boot/dts/qcom/sm7225-fairphone-fp4.dts | 36 +++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index c7230cdcf714..2d891a5640de 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2970,6 +2970,9 @@ wifi: wifi@18800000 { }; }; + sound: sound { + }; + thermal-zones { aoss0-thermal { thermal-sensors = <&tsens0 0>; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 52b16a4fdc43..4afbab570ca1 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -19,6 +19,7 @@ #include #include #include +#include #include #include "sm7225.dtsi" #include "pm6150l.dtsi" @@ -938,6 +939,12 @@ channel@644 { }; }; +&q6asmdai { + dai@0 { + reg = ; + }; +}; + &qup_uart1_cts { /* * Configure a bias-bus-hold on CTS to lower power @@ -1006,6 +1013,35 @@ &sdhc_2 { status = "okay"; }; +&sound { + compatible = "fairphone,fp4-sndcard"; + model = "Fairphone 4"; + + mm1-dai-link { + link-name = "MultiMedia1"; + + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + usb-dai-link { + link-name = "USB Playback"; + + codec { + sound-dai = <&q6usbdai USB_RX>; + }; + + cpu { + sound-dai = <&q6afedai USB_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; +}; + &tlmm { gpio-reserved-ranges = <13 4>, <56 2>; From 682c9d0e788b2e35ece1cbae5448bec1dadaf9af Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Tue, 10 Jun 2025 18:35:20 +0800 Subject: [PATCH 093/931] arm64: dts: qcom: ipq5424: Add CMN PLL node Add CMN PLL node for enabling output clocks to the networking hardware blocks on IPQ5424 devices. The reference clock of CMN PLL is routed from XO to the CMN PLL through the internal WiFi block. .XO (48 MHZ or 96 MHZ or 192 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL. Reviewed-by: Konrad Dybcio Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-3-ceada8165645@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 17 +++++++++++++- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 26 ++++++++++++++++++++- 2 files changed, 41 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index 1f89530cb035..5ca578904f85 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -2,7 +2,7 @@ /* * IPQ5424 RDP466 board device tree source * - * Copyright (c) 2024 The Linux Foundation. All rights reserved. + * Copyright (c) 2024-2025 The Linux Foundation. All rights reserved. */ /dts-v1/; @@ -253,6 +253,21 @@ &usb3 { status = "okay"; }; +/* + * The bootstrap pins for the board select the XO clock frequency that + * supports 48 MHZ, 96 MHZ or 192 MHZ. This setting automatically + * enables the right dividers, to ensure the reference clock output + * from WiFi to the CMN PLL is 48 MHZ. + */ +&ref_48mhz_clk { + clock-div = <1>; + clock-mult = <1>; +}; + &xo_board { clock-frequency = <24000000>; }; + +&xo_clk { + clock-frequency = <48000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 66bd2261eb25..13c641fced8f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -3,10 +3,11 @@ * IPQ5424 device tree source * * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include +#include #include #include #include @@ -18,6 +19,12 @@ / { interrupt-parent = <&intc>; clocks { + ref_48mhz_clk: ref-48mhz-clk { + compatible = "fixed-factor-clock"; + clocks = <&xo_clk>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -27,6 +34,11 @@ xo_board: xo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; + + xo_clk: xo-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; }; cpus: cpus { @@ -210,6 +222,18 @@ pcie1_phy: phy@8c000 { status = "disabled"; }; + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq5424-cmn-pll"; + reg = <0 0x0009b000 0 0x800>; + clocks = <&ref_48mhz_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", "ahb", "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll IPQ5424_CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <12000000000>; + }; + efuse@a4000 { compatible = "qcom,ipq5424-qfprom", "qcom,qfprom"; reg = <0 0x000a4000 0 0x741>; From e5612530e325897da9a70dc78828d6ff2138ae32 Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Tue, 10 Jun 2025 18:35:21 +0800 Subject: [PATCH 094/931] arm64: dts: qcom: Update IPQ5424 xo_board to use fixed factor clock xo_board is fixed to 24 MHZ, which is routed from WiFi output clock 48 MHZ (also being the reference clock of CMN PLL) divided 2 by analog block routing channel. Reviewed-by: Konrad Dybcio Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-4-ceada8165645@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 7 ++++++- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index 5ca578904f85..117f1785e8b8 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -264,8 +264,13 @@ &ref_48mhz_clk { clock-mult = <1>; }; +/* + * The frequency of xo_board is fixed to 24 MHZ, which is routed + * from WiFi output clock 48 MHZ divided by 2. + */ &xo_board { - clock-frequency = <24000000>; + clock-div = <2>; + clock-mult = <1>; }; &xo_clk { diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 13c641fced8f..2eea8a078595 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -31,7 +31,8 @@ sleep_clk: sleep-clk { }; xo_board: xo-board-clk { - compatible = "fixed-clock"; + compatible = "fixed-factor-clock"; + clocks = <&ref_48mhz_clk>; #clock-cells = <0>; }; From 1e2261a669a9596ba435c6fe524e026bac0f0e2f Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Mon, 30 Jun 2025 16:35:01 +0400 Subject: [PATCH 095/931] arm64: dts: qcom: ipq5018: Add MDIO buses IPQ5018 contains two mdio buses of which one bus is used to control the SoC's internal GE PHY, while the other bus is connected to external PHYs or switches. There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's simply add the mdio nodes for them. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-2-01be06378c15@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index baf583c75e76..6e93495ce14c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -185,6 +185,30 @@ pcie0_phy: phy@86000 { status = "disabled"; }; + mdio0: mdio@88000 { + compatible = "qcom,ipq5018-mdio"; + reg = <0x00088000 0x64>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&gcc GCC_MDIO0_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + + status = "disabled"; + }; + + mdio1: mdio@90000 { + compatible = "qcom,ipq5018-mdio"; + reg = <0x00090000 0x64>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&gcc GCC_MDIO1_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + + status = "disabled"; + }; + qfprom: qfprom@a0000 { compatible = "qcom,ipq5018-qfprom", "qcom,qfprom"; reg = <0x000a0000 0x1000>; From f5f2b835e316df29b89e28ed7e467df473932e8d Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Mon, 30 Jun 2025 16:35:02 +0400 Subject: [PATCH 096/931] arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus The IPQ5018 SoC contains an internal GE PHY, always at phy address 7. As such, let's add the GE PHY node to the SoC dtsi. The LDO controller found in the SoC must be enabled to provide constant low voltages to the PHY. The mdio-ipq4019 driver already has support for this, so adding the appropriate TCSR register offset. In addition, the GE PHY outputs both the RX and TX clocks to the GCC which gate controls them and routes them back to the PHY itself. So let's create two DT fixed clocks and register them in the GCC node. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-3-01be06378c15@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 6e93495ce14c..9ce73682e4ae 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -17,6 +17,18 @@ / { #size-cells = <2>; clocks { + gephy_rx_clk: gephy-rx-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + #clock-cells = <0>; + }; + + gephy_tx_clk: gephy-tx-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -187,7 +199,8 @@ pcie0_phy: phy@86000 { mdio0: mdio@88000 { compatible = "qcom,ipq5018-mdio"; - reg = <0x00088000 0x64>; + reg = <0x00088000 0x64>, + <0x019475c4 0x4>; #address-cells = <1>; #size-cells = <0>; @@ -195,6 +208,13 @@ mdio0: mdio@88000 { clock-names = "gcc_mdio_ahb_clk"; status = "disabled"; + + ge_phy: ethernet-phy@7 { + compatible = "ethernet-phy-id004d.d0c0"; + reg = <7>; + + resets = <&gcc GCC_GEPHY_MISC_ARES>; + }; }; mdio1: mdio@90000 { @@ -346,8 +366,8 @@ gcc: clock-controller@1800000 { <&pcie0_phy>, <&pcie1_phy>, <0>, - <0>, - <0>, + <&gephy_rx_clk>, + <&gephy_tx_clk>, <0>, <0>; #clock-cells = <1>; From 718cc7542a000e2911c8d18878ba2eac5f29e744 Mon Sep 17 00:00:00 2001 From: Krishna chaitanya chundru Date: Fri, 25 Jul 2025 19:23:45 +0800 Subject: [PATCH 097/931] arm64: dts: qcom: qcs615: enable pcie Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence. Add PCIe lane equalization preset properties for 8 GT/s. Signed-off-by: Krishna chaitanya chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/r/20250725112346.614316-2-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 138 +++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi index e033b53f0f0f..6fa4614c13ae 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -1072,6 +1072,144 @@ mmss_noc: interconnect@1740000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + pcie: pcie@1c08000 { + device_type = "pci"; + compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150"; + reg = <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c0b000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <0>; + num-lanes = <1>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &apps_smmu 0x400 0x1>, + <0x100 &apps_smmu 0x401 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie_phy>; + phy-names = "pciephy"; + + max-link-speed = <2>; + + operating-points-v2 = <&pcie_opp_table>; + + status = "disabled"; + + pcie_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + }; + }; + + pcie_phy: phy@1c0e000 { + compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy"; + reg = <0x0 0x01c0e000 0x0 0x1000>; + + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>, From 414be2b5a79de8694db1e26a3ea63a2aee5957ad Mon Sep 17 00:00:00 2001 From: Krishna chaitanya chundru Date: Fri, 25 Jul 2025 19:23:46 +0800 Subject: [PATCH 098/931] arm64: dts: qcom: qcs615-ride: Enable PCIe interface Add platform configurations in devicetree for PCIe, board related gpios, PMIC regulators, etc. Reviewed-by: Konrad Dybcio Signed-off-by: Krishna chaitanya chundru Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/r/20250725112346.614316-3-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 42 ++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index fdad6388f6f7..2dd26267ba2e 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -217,6 +217,23 @@ &gcc { <&sleep_clk>; }; +&pcie { + perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + + status = "okay"; +}; + &pm8150_gpios { usb2_en: usb2-en-state { pins = "gpio10"; @@ -256,6 +273,31 @@ &rpmhcc { clocks = <&xo_board_clk>; }; +&tlmm { + pcie_default_state: pcie-default-state { + clkreq-pins { + pins = "gpio90"; + function = "pcie_clk_req"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio101"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-pins { + pins = "gpio100"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + &sdhc_1 { pinctrl-0 = <&sdc1_state_on>; pinctrl-1 = <&sdc1_state_off>; From e13555a3e17b572609901c0f1992f03243a45121 Mon Sep 17 00:00:00 2001 From: "Yu Zhang(Yuriy)" Date: Sun, 27 Jul 2025 18:22:36 +0800 Subject: [PATCH 099/931] arm64: dts: qcom: qcs615: add a PCIe port for WLAN Add an original PCIe port for WLAN. This port will be referenced and supplemented by specific WLAN devices. Signed-off-by: Yu Zhang (Yuriy) Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250727-615-v7-1-2adb6233bbb9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi index 6fa4614c13ae..591fcb740259 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -1179,6 +1179,15 @@ opp-5000000 { opp-peak-kBps = <500000 1>; }; }; + + pcie_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + bus-range = <0x01 0xff>; + }; }; pcie_phy: phy@1c0e000 { From b5634bf97913756c208bb29f6061ee39154458cf Mon Sep 17 00:00:00 2001 From: "Yu Zhang(Yuriy)" Date: Sun, 27 Jul 2025 18:22:37 +0800 Subject: [PATCH 100/931] arm64: dts: qcom: qcs615-ride: Enable WiFi/BT nodes Enable WiFi/BT on qcs615-ride by adding a node for the PMU module of the WCN6855 and assigning its LDO power outputs to the existing WiFi/BT module. Signed-off-by: Yu Zhang (Yuriy) Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250727-615-v7-2-2adb6233bbb9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 135 +++++++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 2dd26267ba2e..36978fdfe3dd 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -18,6 +18,7 @@ aliases { mmc0 = &sdhc_1; mmc1 = &sdhc_2; serial0 = &uart0; + serial1 = &uart7; }; chosen { @@ -38,6 +39,22 @@ xo_board_clk: xo-board-clk { }; }; + vreg_conn_1p8: regulator-conn-1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_1p8"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm8150_gpios 1 GPIO_ACTIVE_HIGH>; + }; + + vreg_conn_pa: regulator-conn-pa { + compatible = "regulator-fixed"; + regulator-name = "vreg_conn_pa"; + startup-delay-us = <4000>; + enable-active-high; + gpio = <&pm8150_gpios 6 GPIO_ACTIVE_HIGH>; + }; + regulator-usb2-vbus { compatible = "regulator-fixed"; regulator-name = "USB2_VBUS"; @@ -47,6 +64,69 @@ regulator-usb2-vbus { enable-active-high; regulator-always-on; }; + + wcn6855-pmu { + compatible = "qcom,wcn6855-pmu"; + + pinctrl-0 = <&bt_en_state>, <&wlan_en_state>; + pinctrl-names = "default"; + + bt-enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&vreg_conn_pa>; + vddaon-supply = <&vreg_s5a>; + vddpmu-supply = <&vreg_conn_1p8>; + vddpmumx-supply = <&vreg_conn_1p8>; + vddpmucx-supply = <&vreg_conn_pa>; + vddrfa0p95-supply = <&vreg_s5a>; + vddrfa1p3-supply = <&vreg_s6a>; + vddrfa1p9-supply = <&vreg_l15a>; + vddpcie1p3-supply = <&vreg_s6a>; + vddpcie1p9-supply = <&vreg_l15a>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -234,6 +314,25 @@ &pcie_phy { status = "okay"; }; +&pcie_port0 { + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + qcom,calibration-variant = "QC_QCS615_Ride"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pm8150_gpios { usb2_en: usb2-en-state { pins = "gpio10"; @@ -257,6 +356,10 @@ &qupv3_id_0 { status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/qcs615/adsp.mbn"; @@ -274,6 +377,13 @@ &rpmhcc { }; &tlmm { + bt_en_state: bt-en-state { + pins = "gpio85"; + function = "gpio"; + bias-pull-down; + output-low; + }; + pcie_default_state: pcie-default-state { clkreq-pins { pins = "gpio90"; @@ -296,6 +406,13 @@ wake-pins { bias-pull-up; }; }; + + wlan_en_state: wlan-en-state { + pins = "gpio98"; + function = "gpio"; + bias-pull-down; + output-low; + }; }; &sdhc_1 { @@ -336,6 +453,24 @@ &uart0 { status = "okay"; }; +&uart7 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn6855-bt"; + firmware-name = "QCA6698/hpnv21", "QCA6698/hpbtfw21.tlv"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + }; +}; + &usb_1_hsphy { vdd-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l12a>; From 35e0b432d5ca73b7498398d7eb369c5665cc3ab1 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 25 Jun 2025 11:11:25 +0200 Subject: [PATCH 101/931] arm64: dts: qcom: pmk8550: Correct gpio node name The reg for the GPIOs is 0xb800 and not 0x8800, so fix this copy-paste mistake. Fixes: e9c0a4e48489 ("arm64: dts: qcom: Add PMK8550 pmic dtsi") Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250625-pmk8550-gpio-name-v1-1-58402849f365@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmk8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qcom/pmk8550.dtsi index c7ac9b2eaacf..583f61fc16ad 100644 --- a/arch/arm64/boot/dts/qcom/pmk8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi @@ -64,7 +64,7 @@ reboot_reason: reboot-reason@48 { }; }; - pmk8550_gpios: gpio@8800 { + pmk8550_gpios: gpio@b800 { compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio"; reg = <0xb800>; gpio-controller; From b2659ddbc2999e8b56edbcd12251b3e469bd0bca Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 11 Aug 2025 17:06:48 +0200 Subject: [PATCH 102/931] arm64: dts: qcom: qrb2210-rb1: fix GPIO lookup flags for i2c SDA and SCL The I2C GPIO bus driver enforces the SDA and SCL pins as open-drain outputs but the lookup flags in the DTS don't reflect that triggering warnings from GPIO core. Add the appropriate flags. Tested-by: Alexey Klimov Reported-by: Alexey Klimov Reviewed-by: Konrad Dybcio Signed-off-by: Bartosz Golaszewski Link: https://lore.kernel.org/r/20250811-qcom-gpio-lookup-open-drain-v1-1-b5496f80e047@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index b2e0fc5501c1..277b33100ac0 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include #include "qcm2290.dtsi" #include "pm4125.dtsi" @@ -63,8 +64,8 @@ hdmi_con: endpoint { i2c2_gpio: i2c { compatible = "i2c-gpio"; - sda-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; - scl-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + sda-gpios = <&tlmm 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; From f07f492773b70efe01f9966703fef658b428f17b Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 11 Aug 2025 17:06:49 +0200 Subject: [PATCH 103/931] arm64: dts: qcom: qrb4210-rb2: fix GPIO lookup flags for i2c SDA and SCL The I2C GPIO bus driver enforces the SDA and SCL pins as open-drain outputs but the lookup flags in the DTS don't reflect that triggering warnings from GPIO core. Add the appropriate flags. Reported-by: Alexey Klimov Reviewed-by: Konrad Dybcio Signed-off-by: Bartosz Golaszewski Link: https://lore.kernel.org/r/20250811-qcom-gpio-lookup-open-drain-v1-2-b5496f80e047@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index a37860175d27..bdf2d66e40c6 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include #include #include @@ -65,8 +66,8 @@ hdmi_con: endpoint { i2c2_gpio: i2c { compatible = "i2c-gpio"; - sda-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; - scl-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + sda-gpios = <&tlmm 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; From 25197809e78c5ff521353acce00406cc2b4bbc16 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 11 Aug 2025 17:06:50 +0200 Subject: [PATCH 104/931] arm64: dts: qcom: sdm845-samsung-starqltechn: fix GPIO lookup flags for i2c SDA and SCL The I2C GPIO bus driver enforces the SDA and SCL pins as open-drain outputs but the lookup flags in the DTS don't reflect that triggering warnings from GPIO core. Add the appropriate flags. Reviewed-by: Konrad Dybcio Signed-off-by: Bartosz Golaszewski Link: https://lore.kernel.org/r/20250811-qcom-gpio-lookup-open-drain-v1-3-b5496f80e047@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index d686531bf4ea..9076d8eb4d50 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -145,8 +145,8 @@ rmtfs_mem: rmtfs-mem@fde00000 { i2c21 { compatible = "i2c-gpio"; - sda-gpios = <&tlmm 127 GPIO_ACTIVE_HIGH>; - scl-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>; + sda-gpios = <&tlmm 127 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 128 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; pinctrl-0 = <&i2c21_sda_state &i2c21_scl_state>; pinctrl-names = "default"; From 8d2a8e8dc448f218b36b3b9f3790c9c0dfaa2b74 Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Thu, 1 May 2025 13:20:52 +0400 Subject: [PATCH 105/931] arm64: dts: qcom: ipq5018: Add SPI nand support Add QPIC SPI NAND support for IPQ5018 SoC. Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250501-ipq5018-spi-qpic-snand-v1-2-31e01fbb606f@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 38 +++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 9ce73682e4ae..e223b087b28b 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -436,6 +436,44 @@ blsp1_spi1: spi@78b5000 { status = "disabled"; }; + qpic_bam: dma-controller@7984000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x07984000 0x1c000>; + + interrupts = ; + + clocks = <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "bam_clk"; + + #dma-cells = <1>; + qcom,ee = <0>; + + status = "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible = "qcom,ipq5018-snand", "qcom,ipq9574-snand"; + reg = <0x079b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", + "aon", + "iom"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", + "rx", + "cmd"; + + status = "disabled"; + }; + usb: usb@8af8800 { compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; reg = <0x08af8800 0x400>; From 1a67f85c690658a35cac41c070df33e3e5a72868 Mon Sep 17 00:00:00 2001 From: Val Packett Date: Sun, 25 May 2025 06:53:33 -0300 Subject: [PATCH 106/931] dt-bindings: arm: qcom: Add Dell Latitude 7455 Document the X1E80100-based Dell Latitude 7455 laptop. Signed-off-by: Val Packett Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250525095341.12462-3-val@packett.cool Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1b705079c1ae..c8a71a33d358 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1149,6 +1149,7 @@ properties: - enum: - asus,vivobook-s15 - asus,zenbook-a14-ux3407ra + - dell,latitude-7455 - dell,xps13-9345 - hp,elitebook-ultra-g1q - hp,omnibook-x14 From 8def31f8c1e1f3d28e4ee3dcf6818a74c9a9a2f7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 27 Jul 2025 21:36:53 +0200 Subject: [PATCH 107/931] arm64: dts: qcom: sm8650: Sort nodes by unit address Qualcomm DTS uses sorting of MMIO nodes by the unit address, so move few nodes in SM8650 DTSI to fix that. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250727193652.4029-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 402 +++++++++++++-------------- 1 file changed, 201 insertions(+), 201 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index bcafd9cf3eae..34ec162db53d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3490,6 +3490,11 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, }; }; + rng: rng@10c3000 { + compatible = "qcom,sm8650-trng", "qcom,trng"; + reg = <0 0x010c3000 0 0x1000>; + }; + cnoc_main: interconnect@1500000 { compatible = "qcom,sm8650-cnoc-main"; reg = <0 0x01500000 0 0x14080>; @@ -3561,11 +3566,6 @@ mmss_noc: interconnect@1780000 { #interconnect-cells = <2>; }; - rng: rng@10c3000 { - compatible = "qcom,sm8650-trng", "qcom,trng"; - reg = <0 0x010c3000 0 0x1000>; - }; - pcie0: pcie@1c00000 { device_type = "pci"; compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; @@ -3926,38 +3926,6 @@ pcie1_phy: phy@1c0e000 { status = "disabled"; }; - cryptobam: dma-controller@1dc4000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0 0x01dc4000 0 0x28000>; - - interrupts = ; - - #dma-cells = <1>; - - iommus = <&apps_smmu 0x480 0>, - <&apps_smmu 0x481 0>; - - qcom,ee = <0>; - qcom,num-ees = <4>; - num-channels = <20>; - qcom,controlled-remotely; - }; - - crypto: crypto@1dfa000 { - compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; - reg = <0 0x01dfa000 0 0x6000>; - - interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "memory"; - - dmas = <&cryptobam 4>, <&cryptobam 5>; - dma-names = "rx", "tx"; - - iommus = <&apps_smmu 0x480 0>, - <&apps_smmu 0x481 0>; - }; - ufs_mem_phy: phy@1d80000 { compatible = "qcom,sm8650-qmp-ufs-phy"; reg = <0 0x01d80000 0 0x2000>; @@ -4079,6 +4047,38 @@ ice: crypto@1d88000 { clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x28000>; + + interrupts = ; + + #dma-cells = <1>; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + + qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>; @@ -4962,6 +4962,170 @@ opp-202000000 { }; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8650-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x088e3000 0 0x154>; + + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,sm8650-qmp-usb3-dp-phy"; + reg = <0 0x088e8000 0 0x3000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + power-domains = <&gcc USB3_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + }; + }; + + usb_1: usb@a600000 { + compatible = "qcom,sm8650-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a600000 0 0xfc100>; + + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&tcsr TCSR_USB3_CLKREF_EN>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + phys = <&usb_1_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", + "apps-usb"; + + iommus = <&apps_smmu 0x40 0>; + + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + + dma-coherent; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; + }; + }; + }; + }; + iris: video-codec@aa00000 { compatible = "qcom,sm8650-iris"; reg = <0 0x0aa00000 0 0xf0000>; @@ -5580,170 +5744,6 @@ dispcc: clock-controller@af00000 { #power-domain-cells = <1>; }; - usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sm8650-snps-eusb2-phy", - "qcom,sm8550-snps-eusb2-phy"; - reg = <0 0x088e3000 0 0x154>; - - clocks = <&tcsr TCSR_USB2_CLKREF_EN>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - - #phy-cells = <0>; - - status = "disabled"; - }; - - usb_dp_qmpphy: phy@88e8000 { - compatible = "qcom,sm8650-qmp-usb3-dp-phy"; - reg = <0 0x088e8000 0 0x3000>; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "aux", - "ref", - "com_aux", - "usb3_pipe"; - - resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; - reset-names = "phy", - "common"; - - power-domains = <&gcc USB3_PHY_GDSC>; - - #clock-cells = <1>; - #phy-cells = <1>; - - orientation-switch; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_dp_qmpphy_out: endpoint { - }; - }; - - port@1 { - reg = <1>; - - usb_dp_qmpphy_usb_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; - }; - }; - - port@2 { - reg = <2>; - - usb_dp_qmpphy_dp_in: endpoint { - remote-endpoint = <&mdss_dp0_out>; - }; - }; - }; - }; - - usb_1: usb@a600000 { - compatible = "qcom,sm8650-dwc3", "qcom,snps-dwc3"; - reg = <0 0x0a600000 0 0xfc100>; - - interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, - <&pdc 14 IRQ_TYPE_EDGE_RISING>, - <&pdc 15 IRQ_TYPE_EDGE_RISING>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "dwc_usb3", - "pwr_event", - "hs_phy_irq", - "dp_hs_phy_irq", - "dm_hs_phy_irq", - "ss_phy_irq"; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&tcsr TCSR_USB3_CLKREF_EN>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi", - "xo"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - phys = <&usb_1_hsphy>, - <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", - "usb3-phy"; - - interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; - interconnect-names = "usb-ddr", - "apps-usb"; - - iommus = <&apps_smmu 0x40 0>; - - power-domains = <&gcc USB30_PRIM_GDSC>; - required-opps = <&rpmhpd_opp_nom>; - - snps,hird-threshold = /bits/ 8 <0x0>; - snps,usb2-gadget-lpm-disable; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,is-utmi-l1-suspend; - snps,usb3_lpm_capable; - snps,usb2-lpm-disable; - snps,has-lpm-erratum; - tx-fifo-resize; - - dma-coherent; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_1_dwc3_hs: endpoint { - }; - }; - - port@1 { - reg = <1>; - - usb_1_dwc3_ss: endpoint { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; - }; - }; - }; - }; - pdc: interrupt-controller@b220000 { compatible = "qcom,sm8650-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; From cb69daf085b5974fef2df9789f8c1b35e78e7913 Mon Sep 17 00:00:00 2001 From: Nick Hu Date: Fri, 1 Aug 2025 15:01:12 +0800 Subject: [PATCH 108/931] dt-bindings: riscv: Add SiFive vendor extensions description Add description for SiFive vendor extensions "xsfcflushdlone", "xsfpgflushdlone" and "xsfcease". This is used in the SBI implementation [1]. Link: https://lore.kernel.org/opensbi/20250708074940.10904-1-nick.hu@sifive.com/ [1] Signed-off-by: Nick Hu Acked-by: Conor Dooley Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index ede6a58ccf53..5638297759df 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -663,6 +663,24 @@ properties: https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf # SiFive + - const: xsfcease + description: + SiFive CEASE Instruction Extensions Specification. + See more details in + https://www.sifive.com/document-file/freedom-u740-c000-manual + + - const: xsfcflushdlone + description: + SiFive L1D Cache Flush Instruction Extensions Specification. + See more details in + https://www.sifive.com/document-file/freedom-u740-c000-manual + + - const: xsfpgflushdlone + description: + SiFive PGFLUSH Instruction Extensions for the power management. The + CPU will flush the L1D and enter the cease state after executing + the instruction. + - const: xsfvqmaccdod description: SiFive Int8 Matrix Multiplication Extensions Specification. From f93e5882134a314760d47536d93b57fbd32d0da1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 24 Jul 2025 15:24:37 +0200 Subject: [PATCH 109/931] dt-bindings: arm: qcom: Drop redundant free-form SoC list The schema and Devicetree specification defines how list of top-level compatibles should be created, thus first paragraph explaining this is completely redundant. The list of SoCs is redundant as well, because the schema lists them. On the other hand, Linux kernel should not be place to store marketing names of some company products, so such list is irrelevant here. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250724132436.77160-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/arm/qcom.yaml | 95 ------------------- 1 file changed, 95 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c8a71a33d358..1df00d9e6de0 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -10,101 +10,6 @@ maintainers: - Bjorn Andersson description: | - For devices using the Qualcomm SoC the "compatible" properties consists of - one or several "manufacturer,model" strings, describing the device itself, - followed by one or several "qcom," strings, describing the SoC used in - the device. - - The 'SoC' element must be one of the following strings: - - apq8016 - apq8026 - apq8064 - apq8074 - apq8084 - apq8094 - apq8096 - ipq4018 - ipq4019 - ipq5018 - ipq5332 - ipq5424 - ipq6018 - ipq8064 - ipq8074 - ipq9574 - mdm9615 - msm8226 - msm8660 - msm8916 - msm8917 - msm8926 - msm8929 - msm8939 - msm8953 - msm8956 - msm8960 - msm8974 - msm8974pro - msm8976 - msm8992 - msm8994 - msm8996 - msm8996pro - msm8998 - qcs404 - qcs615 - qcs8300 - qcs8550 - qcm2290 - qcm6490 - qcs9100 - qdu1000 - qrb2210 - qrb4210 - qru1000 - sa8155p - sa8540p - sa8775p - sar2130p - sc7180 - sc7280 - sc8180x - sc8280xp - sda660 - sdm450 - sdm630 - sdm632 - sdm636 - sdm660 - sdm670 - sdm845 - sdx55 - sdx65 - sdx75 - sm4250 - sm4450 - sm6115 - sm6115p - sm6125 - sm6150 - sm6350 - sm6375 - sm7125 - sm7150 - sm7225 - sm7325 - sm8150 - sm8250 - sm8350 - sm8450 - sm8550 - sm8650 - sm8750 - x1e78100 - x1e80100 - x1p42100 - There are many devices in the list below that run the standard ChromeOS bootloader setup and use the open source depthcharge bootloader to boot the OS. These devices use the bootflow explained at From 6facfaff0fe3b4d5903bed6164eb5e60ee6cdb8f Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Tue, 22 Jul 2025 17:11:50 +0800 Subject: [PATCH 110/931] arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3 Add pcie3_port node to represent the PCIe bridge of PCIe3 so that PCI slot voltage rails can be described under this node in the board's dts. Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250722091151.1423332-3-quic_wenbyao@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 5e9a8fa3cf96..c9fea040223b 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3306,6 +3306,17 @@ opp-128000000 { opp-peak-kBps = <15753000 1>; }; }; + + pcie3_port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3_phy: phy@1be0000 { From df758a868dbc90cae98044d52a9d753575f50cfa Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Tue, 22 Jul 2025 17:11:51 +0800 Subject: [PATCH 111/931] arm64: dts: qcom: x1e80100-qcp: enable pcie3 x8 slot for X1E80100-QCP Add perst, wake and clkreq sideband signals and required regulators in PCIe3 controller and PHY device tree node. Describe the voltage rails of the x8 PCI slots for PCIe3 port. Signed-off-by: Qiang Yu Signed-off-by: Wenbin Yao Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250722091151.1423332-4-quic_wenbyao@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 118 ++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 4dfba835af6a..71c44e37a44b 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -318,6 +318,48 @@ vreg_wcn_3p3: regulator-wcn-3p3 { regulator-boot-on; }; + vreg_pcie_12v: regulator-pcie-12v { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + + gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pcie_x8_12v>; + pinctrl-names = "default"; + }; + + vreg_pcie_3v3_aux: regulator-pcie-3v3-aux { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_3P3_AUX"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pm_sde7_aux_3p3_en>; + pinctrl-names = "default"; + }; + + vreg_pcie_3v3: regulator-pcie-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pm_sde7_main_3p3_en>; + pinctrl-names = "default"; +}; + usb-1-ss0-sbu-mux { compatible = "onnn,fsusb42", "gpio-sbu-mux"; @@ -908,6 +950,59 @@ &mdss_dp3_phy { status = "okay"; }; +&pm8550ve_8_gpios { + pcie_x8_12v: pcie-12v-default-state { + pins = "gpio8"; + function = "normal"; + output-enable; + output-high; + bias-pull-down; + power-source = <0>; + }; +}; + +&pmc8380_3_gpios { + pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { + pins = "gpio8"; + function = "normal"; + output-enable; + output-high; + bias-pull-down; + power-source = <0>; + }; + + pm_sde7_main_3p3_en: pcie-main-3p3-default-state { + pins = "gpio6"; + function = "normal"; + output-enable; + output-high; + bias-pull-down; + power-source = <0>; + }; +}; + +&pcie3 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_default>; + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie3_port { + vpcie12v-supply = <&vreg_pcie_12v>; + vpcie3v3-supply = <&vreg_pcie_3v3>; + vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>; +}; + &pcie4 { perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; @@ -1119,6 +1214,29 @@ nvme_reg_en: nvme-reg-en-state { bias-disable; }; + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio144"; + function = "pcie3_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; From bebacd802b51fae87e04a0f2b6eeb66ac259c14e Mon Sep 17 00:00:00 2001 From: Raviteja Laggyshetty Date: Tue, 22 Jul 2025 05:50:39 +0000 Subject: [PATCH 112/931] arm64: dts: qcom: qcs8300: Add EPSS l3 interconnect provider node and CPUCP OPP tables to scale DDR/L3 Add Epoch Subsystem (EPSS) L3 interconnect provider node and OPP tables required to scale DDR and L3 per freq-domain on QCS8300 platform. As QCS8300 and SA8775P SoCs have same EPSS hardware, added SA8775P compatible as fallback for QCS8300 EPSS device node. Reviewed-by: Konrad Dybcio Co-developed-by: Imran Shaik Signed-off-by: Imran Shaik Signed-off-by: Raviteja Laggyshetty Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250722055039.135140-2-raviteja.laggyshetty@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 301 ++++++++++++++++++++++++++ 1 file changed, 301 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 7ada029c32c1..7d38ddd2cc9e 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -53,6 +54,11 @@ cpu0: cpu@0 { capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <472>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_0: l2-cache { compatible = "cache"; @@ -73,6 +79,11 @@ cpu1: cpu@100 { capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <472>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_1: l2-cache { compatible = "cache"; @@ -93,6 +104,11 @@ cpu2: cpu@200 { capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <507>; qcom,freq-domain = <&cpufreq_hw 2>; + operating-points-v2 = <&cpu2_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_2: l2-cache { compatible = "cache"; @@ -113,6 +129,11 @@ cpu3: cpu@300 { capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <507>; qcom,freq-domain = <&cpufreq_hw 2>; + operating-points-v2 = <&cpu2_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; l2_3: l2-cache { compatible = "cache"; @@ -133,6 +154,11 @@ cpu4: cpu@10000 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_4: l2-cache { compatible = "cache"; @@ -153,6 +179,11 @@ cpu5: cpu@10100 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_5: l2-cache { compatible = "cache"; @@ -173,6 +204,11 @@ cpu6: cpu@10200 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_6: l2-cache { compatible = "cache"; @@ -193,6 +229,11 @@ cpu7: cpu@10300 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; l2_7: l2-cache { compatible = "cache"; @@ -323,6 +364,248 @@ system_sleep: domain-sleep { }; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(681600 * 4) (921600 * 32)>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; + }; + + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; + }; + + opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; + }; + + opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; + }; + + opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; + opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; + }; + + opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; + }; + + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; + }; + + opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; + }; + + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; + }; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; + }; + + opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; + }; + + opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; + }; + + opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; + }; + + }; + + cpu2_opp_table: opp-table-cpu2 { + compatible = "operating-points-v2"; + opp-shared; + + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <(681600 * 4) (921600 * 32)>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; + }; + + opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; + }; + + opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; + }; + + opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; + opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; + }; + + opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; + }; + + opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; + }; + + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; + }; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; + }; + + opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; + }; + + opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; + }; + + opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; + }; + + opp-2284800000 { + opp-hz = /bits/ 64 <2284800000>; + opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; + }; + + opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; + }; + + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible = "operating-points-v2"; + opp-shared; + + opp-844800000 { + opp-hz = /bits/ 64 <844800000>; + opp-peak-kBps = <(681600 * 4) (921600 * 32)>; + }; + + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; + }; + + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; + }; + + opp-1305600000 { + opp-hz = /bits/ 64 <1305600000>; + opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; + }; + + opp-1382400000 { + opp-hz = /bits/ 64 <1382400000>; + opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; + }; + + opp-1459200000 { + opp-hz = /bits/ 64 <1459200000>; + opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; + }; + + opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; + }; + + opp-1728000000 { + opp-hz = /bits/ 64 <1728000000>; + opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; + }; + + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; + }; + + opp-1881600000 { + opp-hz = /bits/ 64 <1881600000>; + opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; + }; + + opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; + }; + }; + dummy_eud: dummy-sink { compatible = "arm,coresight-dummy-sink"; @@ -5433,6 +5716,15 @@ rpmhpd_opp_turbo_l1: opp-9 { }; }; + epss_l3_cl0: interconnect@18590000 { + compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", + "qcom,epss-l3"; + reg = <0x0 0x18590000 0x0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0x0 0x18591000 0x0 0x1000>, @@ -5455,6 +5747,15 @@ cpufreq_hw: cpufreq@18591000 { #freq-domain-cells = <1>; }; + epss_l3_cl1: interconnect@18592000 { + compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", + "qcom,epss-l3"; + reg = <0x0 0x18592000 0x0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + remoteproc_gpdsp: remoteproc@20c00000 { compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas"; reg = <0x0 0x20c00000 0x0 0x10000>; From bf258fdaa2bcbafa04bf1ad646e8ed42e13033cb Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Mon, 21 Jul 2025 10:30:46 +0400 Subject: [PATCH 113/931] arm64: dts: qcom: ipq5018: add PRNG node PRNG inside of IPQ5018 is already supported, so let's add the node for it. Signed-off-by: George Moussalem Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250721-ipq5018-prng-v1-1-474310e0575d@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index e223b087b28b..7363bb6dcd68 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -301,6 +301,14 @@ tsens_s4_p2: s4-p2@254 { }; }; + prng: rng@e3000 { + compatible = "qcom,prng-ee"; + reg = <0x000e3000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + status = "disabled"; + }; + tsens: thermal-sensor@4a9000 { compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1"; reg = <0x004a9000 0x1000>, From ed5789ba7c2ce548f01ebbdbd7488dd9cccc4513 Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Mon, 21 Jul 2025 10:23:15 +0400 Subject: [PATCH 114/931] arm64: dts: qcom: ipq5018: Add crypto nodes IPQ5018 uses Qualcomm QCE crypto engine v5.1 which is already supported. So let's add the dts nodes for its DMA v1.7.4 and QCE itself. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250721-ipq5018-crypto-v3-1-b9cd9b0ef147@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 7363bb6dcd68..08bea072cf11 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -348,6 +348,36 @@ tsens: thermal-sensor@4a9000 { #thermal-sensor-cells = <1>; }; + cryptobam: dma-controller@704000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x00704000 0x20000>; + interrupts = ; + + clocks = <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "bam_clk"; + + #dma-cells = <1>; + qcom,ee = <1>; + qcom,controlled-remotely; + }; + + crypto: crypto@73a000 { + compatible = "qcom,crypto-v5.1"; + reg = <0x0073a000 0x6000>; + + clocks = <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>; + clock-names = "iface", + "bus", + "core"; + + dmas = <&cryptobam 2>, + <&cryptobam 3>; + dma-names = "rx", + "tx"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5018-tlmm"; reg = <0x01000000 0x300000>; From c006b249c54441dd8a3a493c7c87158f441f8178 Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Mon, 21 Jul 2025 10:04:35 +0400 Subject: [PATCH 115/931] arm64: dts: ipq5018: Add CMN PLL node Add CMN PLL node for enabling output clocks to the networking hardware blocks on IPQ5018 devices. The reference clock of CMN PLL is routed from XO to the CMN PLL through the internal WiFi block. .XO (48 MHZ) --> WiFi (multiplier/divider)--> 96 MHZ to CMN PLL. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20250721-ipq5018-cmn-pll-v5-1-4cbf3479af65@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 33 +++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 08bea072cf11..fc1054301c03 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -2,12 +2,13 @@ /* * IPQ5018 SoC device tree source * - * Copyright (c) 2023 The Linux Foundation. All rights reserved. + * Copyright (c) 2023-2025 The Linux Foundation. All rights reserved. */ #include -#include #include +#include +#include #include #include @@ -29,6 +30,14 @@ gephy_tx_clk: gephy-tx-clk { #clock-cells = <0>; }; + ref_96mhz_clk: ref-96mhz-clk { + compatible = "fixed-factor-clock"; + clocks = <&xo_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -38,6 +47,12 @@ xo_board_clk: xo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; + + xo_clk: xo-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; }; cpus { @@ -229,6 +244,20 @@ mdio1: mdio@90000 { status = "disabled"; }; + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq5018-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&ref_96mhz_clk>, + <&gcc GCC_CMN_BLK_AHB_CLK>, + <&gcc GCC_CMN_BLK_SYS_CLK>; + clock-names = "ref", + "ahb", + "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <9600000000>; + }; + qfprom: qfprom@a0000 { compatible = "qcom,ipq5018-qfprom", "qcom,qfprom"; reg = <0x000a0000 0x1000>; From 5ca3d42384a66bcb66f91d75da16ec9e9f053aab Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Mon, 21 Jul 2025 10:04:36 +0400 Subject: [PATCH 116/931] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4 to the analog block routing channel. Update the xo_board_clk nodes in the board DTS files to use clock-div/clock-mult accordingly. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20250721-ipq5018-cmn-pll-v5-2-4cbf3479af65@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 3 ++- arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts | 3 ++- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts index 43def95e9275..df3cbb7c79c4 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -120,5 +120,6 @@ &usbphy0 { }; &xo_board_clk { - clock-frequency = <24000000>; + clock-div = <4>; + clock-mult = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts index 5bb021cb29cd..7a25af57749c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts @@ -124,5 +124,6 @@ uart_pins: uart-pins-state { }; &xo_board_clk { - clock-frequency = <24000000>; + clock-div = <4>; + clock-mult = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index fc1054301c03..4ddb56d63f8f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -44,7 +44,8 @@ sleep_clk: sleep-clk { }; xo_board_clk: xo-board-clk { - compatible = "fixed-clock"; + compatible = "fixed-factor-clock"; + clocks = <&ref_96mhz_clk>; #clock-cells = <0>; }; From 84f3849d0526b22589dd5b4a5634ed4235a6ccf9 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 17 Jul 2025 16:10:57 +0530 Subject: [PATCH 117/931] arm64: dts: qcom: qcs6490-rb3gen2: Add missing clkreq pinctrl property Add the missing clkreq pinctrl entry to the PCIe1 node. This ensures proper configuration of the CLKREQ# signal, which is needed for proper functioning of PCIe ASPM. Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250717-clkreq-v1-1-5a82c7e8e891@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 5fbcd48f2e2d..8f15be633946 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -811,7 +811,7 @@ &mdss_edp_phy { &pcie1 { perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>; + pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, From fba47ba8c8a8ffa9d8ad1836396837a998bb5153 Mon Sep 17 00:00:00 2001 From: Ziyue Zhang Date: Thu, 17 Jul 2025 15:27:46 +0800 Subject: [PATCH 118/931] arm64: dts: qcom: qcs615: Set LDO12A regulator to HPM to avoid boot hang MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On certain platforms (e.g., QCS615), consumers of LDO12A—such as PCIe, UFS, and eMMC—may draw more than 10mA of current during boot. This can exceed the regulator's limit in Low Power Mode (LPM), triggering current limit protection and causing the system to hang. To address this, there are two possible approaches: a) Set the regulator's initial mode to High Performance Mode (HPM) in the device tree. b) Keep the default LPM setting and have each consumer driver explicitly set its current load. Since some regulators are shared among multiple consumers, and setting the current must be coordinated across all of them, we will initially adopt option a by setting the regulator to HPM. We can later migrate to option b when the timing is appropriate and all consumer drivers are ready. Signed-off-by: Ziyue Zhang Signed-off-by: Tingguo Cheng Link: https://lore.kernel.org/r/20250717072746.987298-1-quic_ziyuzhan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 36978fdfe3dd..59582d3dc4c4 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -246,10 +246,7 @@ vreg_l12a: ldo12 { regulator-name = "vreg_l12a"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1890000>; - regulator-initial-mode = ; - regulator-allow-set-load; - regulator-allowed-modes = ; + regulator-initial-mode = ; }; vreg_l13a: ldo13 { From 474aa14da0e160f2f3fb002b64b8363ae91f9590 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 16 Jul 2025 18:24:13 +0200 Subject: [PATCH 119/931] dt-bindings: arm: qcom-soc: Document new Milos and Glymur SoCs Extend the schema enforcing correct SoC-block naming to cover Milos (compatibles already accepted by some maintainers for next release) and Glymur (posted on mailing lists [1]) SoCs. Link: https://lore.kernel.org/linux-devicetree/20250716152017.4070029-1-pankaj.patil@oss.qualcomm.com/ [1] Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250716162412.27471-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom-soc.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml index a77d68dcad4e..27261039d56f 100644 --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml @@ -23,7 +23,9 @@ description: | select: properties: compatible: - pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + oneOf: + - pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - pattern: "^qcom,.*(glymur|milos).*$" required: - compatible @@ -34,6 +36,7 @@ properties: - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$" - pattern: "^qcom,sar[0-9]+[a-z]?-.*$" - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$" + - pattern: "^qcom,(glymur|milos)-.*$" # Legacy namings - variations of existing patterns/compatibles are OK, # but do not add completely new entries to these: From 92d05aceadbd799b416ad08bf2f741a096bf3e56 Mon Sep 17 00:00:00 2001 From: Arseniy Velikanov Date: Wed, 16 Jul 2025 18:10:39 +0400 Subject: [PATCH 120/931] arm64: dts: qcom: sm8250-xiaomi-pipa: Drop nonexistent pm8009 pmic PM8009 was erroneously added since this device doesn't actually have it. It triggers a big critical error at boot, so we're drop it. Fixes: 264beb3cbd0d ("arm64: dts: qcom: sm8250-xiaomi-pipa: Add initial device tree") Reviewed-by: Luka Panio Signed-off-by: Arseniy Velikanov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250716141041.24507-1-me@adomerle.pw Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sm8250-xiaomi-pipa.dts | 58 ------------------- 1 file changed, 58 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts index 668078ea4f04..a4c8b778ae46 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts @@ -12,7 +12,6 @@ #include "pm8150.dtsi" #include "pm8150b.dtsi" #include "pm8150l.dtsi" -#include "pm8009.dtsi" /* * Delete following upstream (sm8250.dtsi) reserved @@ -406,63 +405,6 @@ vreg_l11c_3p0: ldo11 { regulator-initial-mode = ; }; }; - - regulators-2 { - compatible = "qcom,pm8009-rpmh-regulators"; - qcom,pmic-id = "f"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vreg_bob>; - vdd-l2-supply = <&vreg_s8c_1p35>; - vdd-l5-l6-supply = <&vreg_bob>; - vdd-l7-supply = <&vreg_s4a_1p8>; - - vreg_s1f_1p2: smps1 { - regulator-name = "vreg_s1f_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - regulator-initial-mode = ; - }; - - vreg_s2f_0p5: smps2 { - regulator-name = "vreg_s2f_0p5"; - regulator-min-microvolt = <512000>; - regulator-max-microvolt = <1100000>; - regulator-initial-mode = ; - }; - - /* L1 is unused. */ - - vreg_l2f_1p3: ldo2 { - regulator-name = "vreg_l2f_1p3"; - regulator-min-microvolt = <1056000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - /* L3 & L4 are unused. */ - - vreg_l5f_2p8: ldo5 { - regulator-name = "vreg_l5f_2p85"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = ; - }; - - vreg_l6f_2p8: ldo6 { - regulator-name = "vreg_l6f_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = ; - }; - - vreg_l7f_1p8: ldo7 { - regulator-name = "vreg_l7f_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; }; &cdsp { From 56197c8737b88d300cda97cd71b64b8a93cf6f70 Mon Sep 17 00:00:00 2001 From: Arseniy Velikanov Date: Wed, 16 Jul 2025 18:10:40 +0400 Subject: [PATCH 121/931] arm64: dts: qcom: sm8250-xiaomi-pipa: Drop unused bq27z561 It looks like the fuel gauge is not connected to the battery, it reports nonsense info. Downstream kernel uses pmic fg. Reviewed-by: Luka Panio Signed-off-by: Arseniy Velikanov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250716141041.24507-2-me@adomerle.pw Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sm8250-xiaomi-pipa.dts | 22 ------------------- 1 file changed, 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts index a4c8b778ae46..c2d0f0254776 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts @@ -437,17 +437,6 @@ zap-shader { }; }; -&i2c0 { - clock-frequency = <400000>; - status = "okay"; - - fuel-gauge@55 { - compatible = "ti,bq27z561"; - reg = <0x55>; - monitored-battery = <&battery_r>; - }; -}; - &i2c11 { clock-frequency = <400000>; status = "okay"; @@ -465,17 +454,6 @@ backlight: backlight@11 { }; }; -&i2c13 { - clock-frequency = <400000>; - status = "okay"; - - fuel-gauge@55 { - compatible = "ti,bq27z561"; - reg = <0x55>; - monitored-battery = <&battery_l>; - }; -}; - &pcie0 { status = "okay"; }; From e2ec684f82536d62e0d60663ed3689455a9b0b9f Mon Sep 17 00:00:00 2001 From: Arseniy Velikanov Date: Wed, 16 Jul 2025 18:10:41 +0400 Subject: [PATCH 122/931] arm64: dts: sm8250-xiaomi-pipa: Update battery info Added max design microvolt. Merged battery info into one node, since pmic fuel-gauge uses mixed info about dual-cell battery. Reviewed-by: Luka Panio Signed-off-by: Arseniy Velikanov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250716141041.24507-3-me@adomerle.pw Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts index c2d0f0254776..4ad24974c09f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts @@ -49,18 +49,12 @@ framebuffer: framebuffer@9c000000 { }; }; - battery_l: battery-l { + battery: battery { compatible = "simple-battery"; - voltage-min-design-microvolt = <3870000>; - energy-full-design-microwatt-hours = <16700000>; - charge-full-design-microamp-hours = <4420000>; - }; - - battery_r: battery-r { - compatible = "simple-battery"; - voltage-min-design-microvolt = <3870000>; - energy-full-design-microwatt-hours = <16700000>; - charge-full-design-microamp-hours = <4420000>; + charge-full-design-microamp-hours = <8840000>; + energy-full-design-microwatt-hours = <34300000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4370000>; }; bl_vddpos_5p5: bl-vddpos-regulator { From bc6776fab8455762089274d469a67d104e3b96ae Mon Sep 17 00:00:00 2001 From: Shivnandan Kumar Date: Wed, 16 Jul 2025 14:25:47 +0200 Subject: [PATCH 123/931] arm64: dts: qcom: sm8750: Add BWMONs Add the CPU BWMONs for SM8750 SoCs. Notably, the one related to cluster0 requires that it's mapped with the nE memory attribute. This is specific to a single instance, on this platform only and should not be mimicked elsewhere. Signed-off-by: Shivnandan Kumar [konrad: add nonposted-mmio where necessary, re-sort nodes] Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250716-8750_cpubwmon-v4-2-12212098e90f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 76 ++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 4643705021c6..79ca262f5811 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3617,6 +3617,82 @@ frame@1680d000 { }; }; + /* cluster0 */ + pmu@240b3400 { + compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x240b3400 0x0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + nonposted-mmio; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <800000>; + }; + + opp-1 { + opp-peak-kBps = <2188000>; + }; + + opp-2 { + opp-peak-kBps = <5414400>; + }; + + opp-3 { + opp-peak-kBps = <6220800>; + }; + + opp-4 { + opp-peak-kBps = <6835200>; + }; + + opp-5 { + opp-peak-kBps = <8371200>; + }; + + opp-6 { + opp-peak-kBps = <10944000>; + }; + + opp-7 { + opp-peak-kBps = <12748800>; + }; + + opp-8 { + opp-peak-kBps = <14745600>; + }; + + opp-9 { + opp-peak-kBps = <16896000>; + }; + + opp-10 { + opp-peak-kBps = <19046400>; + }; + }; + }; + + /* cluster1 */ + pmu@240b7400 { + compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x240b7400 0x0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + gem_noc: interconnect@24100000 { compatible = "qcom,sm8750-gem-noc"; reg = <0x0 0x24100000 0x0 0x14b080>; From 5e4ca587f56319c3c9800b9d1a97443b9c364a15 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 16 Jul 2025 12:16:07 +0200 Subject: [PATCH 124/931] arm64: dts: qcom: Remove sdm845-cheza boards Cheza was a prototype board, used mainly by the ChromeOS folks, whose former efforts on making linux-arm-msm better we greatly appreciate. There are close to zero known-working devices at this point in time (see the link below) and it was never productized. Remove it to ease maintenance burden. Link: https://lore.kernel.org/linux-arm-msm/5567e441-055d-443a-b117-ec16b53dc059@oss.qualcomm.com/ Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20250716-topic-goodnight_cheza-v2-1-6fa8d3261813@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- MAINTAINERS | 1 - arch/arm64/boot/dts/qcom/Makefile | 3 - arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts | 238 ---- arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts | 238 ---- arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts | 174 --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 1330 ------------------ 6 files changed, 1984 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts delete mode 100644 arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts delete mode 100644 arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts delete mode 100644 arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index fe168477caa4..9a06a729af0c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3109,7 +3109,6 @@ ARM/QUALCOMM CHROMEBOOK SUPPORT R: cros-qcom-dts-watchers@chromium.org F: arch/arm64/boot/dts/qcom/sc7180* F: arch/arm64/boot/dts/qcom/sc7280* -F: arch/arm64/boot/dts/qcom/sdm845-cheza* ARM/QUALCOMM MAILING LIST L: linux-arm-msm@vger.kernel.org diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index dcc0f6382f51..94a84770b080 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -232,9 +232,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm632-motorola-ocean.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts b/arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts deleted file mode 100644 index bd7c25bb8d35..000000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza-r1.dts +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza board device tree source - * - * Copyright 2018 Google LLC. - */ - -/dts-v1/; - -#include "sdm845-cheza.dtsi" - -/ { - model = "Google Cheza (rev1)"; - compatible = "google,cheza-rev1", "qcom,sdm845"; - - /* - * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children - */ - - /* - * NOTE: Technically pp3500_a is not the exact same signal as - * pp3500_a_vbob (there's a load switch between them and the EC can - * control pp3500_a via "en_pp3300_a"), but from the AP's point of - * view they are the same. - */ - pp3500_a: - pp3500_a_vbob: pp3500-a-vbob-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_bob"; - - /* - * Comes on automatically when pp5000_ldo comes on, which - * comes on automatically when ppvar_sys comes on - */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_dx_edp: pp3300-dx-edp-regulator { - /* Yes, it's really 3.5 despite the name of the signal */ - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&pp3500_a>; - }; -}; - -/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */ - -/* - * L19 and L28 technically go to 3.3V, but most boards have old AOP firmware - * that limits them to 3.0, and trying to run at 3.3V with that old firmware - * prevents the system from booting. - */ -&src_pp3000_l19a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_pp3300_l22a { - /delete-property/regulator-boot-on; - /delete-property/regulator-always-on; -}; - -&src_pp3300_l28a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_vreg_bob { - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - vin-supply = <&pp3500_a_vbob>; -}; - -/* - * NON-REGULATOR OVERRIDES - * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label - */ - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "", - "FP_RST_L", - "FCAM_EN", - "", - "EDP_BRIJ_IRQ", - "EC_IN_RW_ODL", - "", - "RCAM_MCLK", - "FCAM_MCLK", - "", - "RCAM_EN", - "CCI0_SDA", - "CCI0_SCL", - "CCI1_SDA", - "CCI1_SCL", - "FCAM_RST_L", - "", - "PEN_RST_L", - "PEN_IRQ_L", - "", - "RCAM_VSYNC", - "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "AP_PEN_1V8_SDA", - "AP_PEN_1V8_SCL", - "AP_TS_I2C_SDA", - "AP_TS_I2C_SCL", - "RCAM_RST_L", - "", - "AP_EDP_BKLTEN", - "AP_BRD_ID1", - "BOOT_CONFIG_4", - "AMP_IRQ_L", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "EN_PP3300_DX_EDP", - "SD_CD_ODL", - "BT_UART_RTS", - "BT_UART_CTS", - "BT_UART_RXD", - "BT_UART_TXD", - "AMP_I2C_SDA", - "AMP_I2C_SCL", - "AP_BRD_ID3", - "", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DOUT", - "AMP_DIN", - "AP_BRD_ID2", - "PEN_PDCT_L", - "HP_MCLK", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "", - "", - "", - "", - "BT_SLIMBUS_DATA", - "BT_SLIMBUS_CLK", - "AMP_RESET_L", - "", - "FCAM_VSYNC", - "", - "AP_SKU_ID1", - "EC_WOV_BCLK", - "EC_WOV_LRCLK", - "EC_WOV_DOUT", - "", - "", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "AP_SPI_CS0_L", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "", - "", - "AP_SPI_CLK", - "", - "RFFE6_CLK", - "RFFE6_DATA", - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_0", - "EDP_BRIJ_EN", - "", - "USB_HS_TX_EN", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "AP_SKU_ID2", - "SDM_GRFC_8", - "SDM_GRFC_9", - "AP_RST_REQ", - "HP_IRQ", - "TS_RESET_L", - "PEN_EJECT_ODL", - "HUB_RST_L", - "FP_TO_AP_IRQ", - "AP_EC_INT_L", - "", - "", - "TS_INT_L", - "AP_SUSPEND_L", - "SDM_GRFC_3", - "", - "H1_AP_INT_ODL", - "QLINK_REQ", - "QLINK_EN", - "SDM_GRFC_2", - "BOOT_CONFIG_3", - "WMSS_RESET_L", - "SDM_GRFC_0", - "SDM_GRFC_1", - "RFFE3_DATA", - "RFFE3_CLK", - "RFFE4_DATA", - "RFFE4_CLK", - "RFFE5_DATA", - "RFFE5_CLK", - "GNSS_EN", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "AP_RAM_ID1", - "AP_RAM_ID2", - "RFFE1_DATA", - "RFFE1_CLK"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts b/arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts deleted file mode 100644 index 2b7230594ecb..000000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza-r2.dts +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza board device tree source - * - * Copyright 2018 Google LLC. - */ - -/dts-v1/; - -#include "sdm845-cheza.dtsi" - -/ { - model = "Google Cheza (rev2)"; - compatible = "google,cheza-rev2", "qcom,sdm845"; - - /* - * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children - */ - - /* - * NOTE: Technically pp3500_a is not the exact same signal as - * pp3500_a_vbob (there's a load switch between them and the EC can - * control pp3500_a via "en_pp3300_a"), but from the AP's point of - * view they are the same. - */ - pp3500_a: - pp3500_a_vbob: pp3500-a-vbob-regulator { - compatible = "regulator-fixed"; - regulator-name = "vreg_bob"; - - /* - * Comes on automatically when pp5000_ldo comes on, which - * comes on automatically when ppvar_sys comes on - */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_dx_edp: pp3300-dx-edp-regulator { - /* Yes, it's really 3.5 despite the name of the signal */ - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - - vin-supply = <&pp3500_a>; - }; -}; - -/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */ - -/* - * L19 and L28 technically go to 3.3V, but most boards have old AOP firmware - * that limits them to 3.0, and trying to run at 3.3V with that old firmware - * prevents the system from booting. - */ -&src_pp3000_l19a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_pp3300_l22a { - /delete-property/regulator-boot-on; - /delete-property/regulator-always-on; -}; - -&src_pp3300_l28a { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3008000>; -}; - -&src_vreg_bob { - regulator-min-microvolt = <3500000>; - regulator-max-microvolt = <3500000>; - vin-supply = <&pp3500_a_vbob>; -}; - -/* - * NON-REGULATOR OVERRIDES - * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label - */ - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "BRIJ_SUSPEND", - "FP_RST_L", - "FCAM_EN", - "", - "EDP_BRIJ_IRQ", - "EC_IN_RW_ODL", - "", - "RCAM_MCLK", - "FCAM_MCLK", - "", - "RCAM_EN", - "CCI0_SDA", - "CCI0_SCL", - "CCI1_SDA", - "CCI1_SCL", - "FCAM_RST_L", - "FPMCU_BOOT0", - "PEN_RST_L", - "PEN_IRQ_L", - "FPMCU_SEL_OD", - "RCAM_VSYNC", - "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "AP_PEN_1V8_SDA", - "AP_PEN_1V8_SCL", - "AP_TS_I2C_SDA", - "AP_TS_I2C_SCL", - "RCAM_RST_L", - "", - "AP_EDP_BKLTEN", - "AP_BRD_ID1", - "BOOT_CONFIG_4", - "AMP_IRQ_L", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "EN_PP3300_DX_EDP", - "SD_CD_ODL", - "BT_UART_RTS", - "BT_UART_CTS", - "BT_UART_RXD", - "BT_UART_TXD", - "AMP_I2C_SDA", - "AMP_I2C_SCL", - "AP_BRD_ID3", - "", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DOUT", - "AMP_DIN", - "AP_BRD_ID2", - "PEN_PDCT_L", - "HP_MCLK", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "", - "", - "", - "", - "BT_SLIMBUS_DATA", - "BT_SLIMBUS_CLK", - "AMP_RESET_L", - "", - "FCAM_VSYNC", - "", - "AP_SKU_ID1", - "EC_WOV_BCLK", - "EC_WOV_LRCLK", - "EC_WOV_DOUT", - "", - "", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "AP_SPI_CS0_L", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "", - "", - "AP_SPI_CLK", - "", - "RFFE6_CLK", - "RFFE6_DATA", - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_0", - "EDP_BRIJ_EN", - "", - "USB_HS_TX_EN", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "AP_SKU_ID2", - "SDM_GRFC_8", - "SDM_GRFC_9", - "AP_RST_REQ", - "HP_IRQ", - "TS_RESET_L", - "PEN_EJECT_ODL", - "HUB_RST_L", - "FP_TO_AP_IRQ", - "AP_EC_INT_L", - "", - "", - "TS_INT_L", - "AP_SUSPEND_L", - "SDM_GRFC_3", - "", - "H1_AP_INT_ODL", - "QLINK_REQ", - "QLINK_EN", - "SDM_GRFC_2", - "BOOT_CONFIG_3", - "WMSS_RESET_L", - "SDM_GRFC_0", - "SDM_GRFC_1", - "RFFE3_DATA", - "RFFE3_CLK", - "RFFE4_DATA", - "RFFE4_CLK", - "RFFE5_DATA", - "RFFE5_CLK", - "GNSS_EN", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "AP_RAM_ID1", - "AP_RAM_ID2", - "RFFE1_DATA", - "RFFE1_CLK"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts b/arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts deleted file mode 100644 index 1ba67be08f81..000000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dts +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza board device tree source - * - * Copyright 2018 Google LLC. - */ - -/dts-v1/; - -#include "sdm845-cheza.dtsi" - -/ { - model = "Google Cheza (rev3+)"; - compatible = "google,cheza", "qcom,sdm845"; -}; - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "BRIJ_SUSPEND", - "FP_RST_L", - "FCAM_EN", - "", - "EDP_BRIJ_IRQ", - "EC_IN_RW_ODL", - "", - "RCAM_MCLK", - "FCAM_MCLK", - "", - "RCAM_EN", - "CCI0_SDA", - "CCI0_SCL", - "CCI1_SDA", - "CCI1_SCL", - "FCAM_RST_L", - "FPMCU_BOOT0", - "PEN_RST_L", - "PEN_IRQ_L", - "FPMCU_SEL_OD", - "RCAM_VSYNC", - "ESIM_MISO", - "ESIM_MOSI", - "ESIM_CLK", - "ESIM_CS_L", - "AP_PEN_1V8_SDA", - "AP_PEN_1V8_SCL", - "AP_TS_I2C_SDA", - "AP_TS_I2C_SCL", - "RCAM_RST_L", - "", - "AP_EDP_BKLTEN", - "AP_BRD_ID0", - "BOOT_CONFIG_4", - "AMP_IRQ_L", - "EDP_BRIJ_I2C_SDA", - "EDP_BRIJ_I2C_SCL", - "EN_PP3300_DX_EDP", - "SD_CD_ODL", - "BT_UART_RTS", - "BT_UART_CTS", - "BT_UART_RXD", - "BT_UART_TXD", - "AMP_I2C_SDA", - "AMP_I2C_SCL", - "AP_BRD_ID2", - "", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DOUT", - "AMP_DIN", - "AP_BRD_ID1", - "PEN_PDCT_L", - "HP_MCLK", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "", - "", - "", - "", - "BT_SLIMBUS_DATA", - "BT_SLIMBUS_CLK", - "AMP_RESET_L", - "", - "FCAM_VSYNC", - "", - "AP_SKU_ID0", - "EC_WOV_BCLK", - "EC_WOV_LRCLK", - "EC_WOV_DOUT", - "", - "", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "", - "AP_SPI_CS0_L", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "", - "", - "AP_SPI_CLK", - "", - "RFFE6_CLK", - "RFFE6_DATA", - "BOOT_CONFIG_1", - "BOOT_CONFIG_2", - "BOOT_CONFIG_0", - "EDP_BRIJ_EN", - "", - "USB_HS_TX_EN", - "UIM2_DATA", - "UIM2_CLK", - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "AP_SKU_ID1", - "SDM_GRFC_8", - "SDM_GRFC_9", - "AP_RST_REQ", - "HP_IRQ", - "TS_RESET_L", - "PEN_EJECT_ODL", - "HUB_RST_L", - "FP_TO_AP_IRQ", - "AP_EC_INT_L", - "", - "", - "TS_INT_L", - "AP_SUSPEND_L", - "SDM_GRFC_3", - /* - * AP_FLASH_WP_L is crossystem ABI. Rev3 schematics - * call it BIOS_FLASH_WP_R_L. - */ - "AP_FLASH_WP_L", - "H1_AP_INT_ODL", - "QLINK_REQ", - "QLINK_EN", - "SDM_GRFC_2", - "BOOT_CONFIG_3", - "WMSS_RESET_L", - "SDM_GRFC_0", - "SDM_GRFC_1", - "RFFE3_DATA", - "RFFE3_CLK", - "RFFE4_DATA", - "RFFE4_CLK", - "RFFE5_DATA", - "RFFE5_CLK", - "GNSS_EN", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "AP_RAM_ID0", - "AP_RAM_ID1", - "RFFE1_DATA", - "RFFE1_CLK"; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi deleted file mode 100644 index b7e514f81f92..000000000000 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ /dev/null @@ -1,1330 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Cheza device tree source (common between revisions) - * - * Copyright 2018 Google LLC. - */ - -#include -#include -#include "sdm845.dtsi" - -/* PMICs depend on spmi_bus label and so must come after SoC */ -#include "pm8005.dtsi" -#include "pm8998.dtsi" - -/ { - aliases { - bluetooth0 = &bluetooth; - serial1 = &uart6; - serial0 = &uart9; - wifi0 = &wifi; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&cros_ec_pwm 0>; - enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; - power-supply = <&ppvar_sys>; - pinctrl-names = "default"; - pinctrl-0 = <&ap_edp_bklten>; - }; - - /* FIXED REGULATORS - parents above children */ - - /* This is the top level supply and variable voltage */ - ppvar_sys: ppvar-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "ppvar_sys"; - regulator-always-on; - regulator-boot-on; - }; - - /* This divides ppvar_sys by 2, so voltage is variable */ - src_vph_pwr: src-vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "src_vph_pwr"; - - /* EC turns on with switchcap_on_l; always on for AP */ - regulator-always-on; - regulator-boot-on; - - vin-supply = <&ppvar_sys>; - }; - - pp5000_a: pp5000-a-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp5000_a"; - - /* EC turns on with en_pp5000_a; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&ppvar_sys>; - }; - - src_vreg_bob: src-vreg-bob-regulator { - compatible = "regulator-fixed"; - regulator-name = "src_vreg_bob"; - - /* EC turns on with vbob_en; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_dx_edp: pp3300-dx-edp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_dx_edp"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_dx_edp>; - }; - - /* - * Apparently RPMh does not provide support for PM8998 S4 because it - * is always-on; model it as a fixed regulator. - */ - src_pp1800_s4a: pm8998-smps4 { - compatible = "regulator-fixed"; - regulator-name = "src_pp1800_s4a"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-always-on; - regulator-boot-on; - - vin-supply = <&src_vph_pwr>; - }; - - /* BOARD-SPECIFIC TOP LEVEL NODES */ - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pen_eject_odl>; - - switch-pen-insert { - label = "Pen Insert"; - /* Insert = low, eject = high */ - gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-source; - }; - }; - - panel: panel { - compatible = "innolux,p120zdg-bf1"; - power-supply = <&pp3300_dx_edp>; - backlight = <&backlight>; - no-hpd; - - panel_in: port { - panel_in_edp: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; -}; - -&cpufreq_hw { - /delete-property/ interrupts-extended; /* reference to lmh_cluster[01] */ -}; - -&psci { - /delete-node/ power-domain-cpu0; - /delete-node/ power-domain-cpu1; - /delete-node/ power-domain-cpu2; - /delete-node/ power-domain-cpu3; - /delete-node/ power-domain-cpu4; - /delete-node/ power-domain-cpu5; - /delete-node/ power-domain-cpu6; - /delete-node/ power-domain-cpu7; - /delete-node/ power-domain-cluster; -}; - -&cpus { - /delete-node/ domain-idle-states; -}; - -&cpu_idle_states { - little_cpu_sleep_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "little-power-down"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <350>; - exit-latency-us = <461>; - min-residency-us = <1890>; - local-timer-stop; - }; - - little_cpu_sleep_1: cpu-sleep-0-1 { - compatible = "arm,idle-state"; - idle-state-name = "little-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <360>; - exit-latency-us = <531>; - min-residency-us = <3934>; - local-timer-stop; - }; - - big_cpu_sleep_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "big-power-down"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <264>; - exit-latency-us = <621>; - min-residency-us = <952>; - local-timer-stop; - }; - - big_cpu_sleep_1: cpu-sleep-1-1 { - compatible = "arm,idle-state"; - idle-state-name = "big-rail-power-down"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <702>; - exit-latency-us = <1061>; - min-residency-us = <4488>; - local-timer-stop; - }; - - cluster_sleep_0: cluster-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "cluster-power-down"; - arm,psci-suspend-param = <0x400000F4>; - entry-latency-us = <3263>; - exit-latency-us = <6562>; - min-residency-us = <9987>; - local-timer-stop; - }; -}; - -&cpu0 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&little_cpu_sleep_0 - &little_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu1 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&little_cpu_sleep_0 - &little_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu2 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&little_cpu_sleep_0 - &little_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu3 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&little_cpu_sleep_0 - &little_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu4 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&big_cpu_sleep_0 - &big_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu5 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&big_cpu_sleep_0 - &big_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu6 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&big_cpu_sleep_0 - &big_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&cpu7 { - /delete-property/ power-domains; - /delete-property/ power-domain-names; - cpu-idle-states = <&big_cpu_sleep_0 - &big_cpu_sleep_1 - &cluster_sleep_0>; -}; - -&lmh_cluster0 { - status = "disabled"; -}; - -&lmh_cluster1 { - status = "disabled"; -}; - -/* - * Reserved memory changes - * - * Putting this all together (out of order with the rest of the file) to keep - * all modifications to the memory map (from sdm845.dtsi) in one place. - */ - -/* - * Our mpss_region is 8MB bigger than the default one and that conflicts - * with venus_mem and cdsp_mem. - * - * For venus_mem we'll delete and re-create at a different address. - * - * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but - * that also means we need to delete cdsp_pas. - */ -/delete-node/ &venus_mem; -/delete-node/ &cdsp_mem; -/delete-node/ &cdsp_pas; -/delete-node/ &gpu_mem; - -/* Increase the size from 120 MB to 128 MB */ -&mpss_region { - reg = <0 0x8e000000 0 0x8000000>; -}; - -/* Increase the size from 2MB to 8MB */ -&rmtfs_mem { - reg = <0 0x88f00000 0 0x800000>; -}; - -/ { - reserved-memory { - venus_mem: memory@96000000 { - reg = <0 0x96000000 0 0x500000>; - no-map; - }; - }; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; - pinctrl-1 = <&qspi_sleep>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - /* - * In theory chip supports up to 104 MHz and controller up - * to 80 MHz, but above 25 MHz wasn't reliable so we'll use - * that for now. b:117440651 - */ - spi-max-frequency = <25000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; -}; - - -&apps_rsc { - /delete-property/ power-domains; - - regulators-0 { - compatible = "qcom,pm8998-rpmh-regulators"; - qcom,pmic-id = "a"; - - vdd-s1-supply = <&src_vph_pwr>; - vdd-s2-supply = <&src_vph_pwr>; - vdd-s3-supply = <&src_vph_pwr>; - vdd-s4-supply = <&src_vph_pwr>; - vdd-s5-supply = <&src_vph_pwr>; - vdd-s6-supply = <&src_vph_pwr>; - vdd-s7-supply = <&src_vph_pwr>; - vdd-s8-supply = <&src_vph_pwr>; - vdd-s9-supply = <&src_vph_pwr>; - vdd-s10-supply = <&src_vph_pwr>; - vdd-s11-supply = <&src_vph_pwr>; - vdd-s12-supply = <&src_vph_pwr>; - vdd-s13-supply = <&src_vph_pwr>; - vdd-l1-l27-supply = <&src_pp1025_s7a>; - vdd-l2-l8-l17-supply = <&src_pp1350_s3a>; - vdd-l3-l11-supply = <&src_pp1025_s7a>; - vdd-l4-l5-supply = <&src_pp1025_s7a>; - vdd-l6-supply = <&src_vph_pwr>; - vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>; - vdd-l9-supply = <&src_pp2040_s5a>; - vdd-l10-l23-l25-supply = <&src_vreg_bob>; - vdd-l13-l19-l21-supply = <&src_vreg_bob>; - vdd-l16-l28-supply = <&src_vreg_bob>; - vdd-l18-l22-supply = <&src_vreg_bob>; - vdd-l20-l24-supply = <&src_vreg_bob>; - vdd-l26-supply = <&src_pp1350_s3a>; - vin-lvs-1-2-supply = <&src_pp1800_s4a>; - - src_pp1125_s2a: smps2 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - src_pp1350_s3a: smps3 { - regulator-min-microvolt = <1352000>; - regulator-max-microvolt = <1352000>; - }; - - src_pp2040_s5a: smps5 { - regulator-min-microvolt = <1904000>; - regulator-max-microvolt = <2040000>; - }; - - src_pp1025_s7a: smps7 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1028000>; - }; - - vdd_qusb_hs0: - vdda_hp_pcie_core: - vdda_mipi_csi0_0p9: - vdda_mipi_csi1_0p9: - vdda_mipi_csi2_0p9: - vdda_mipi_dsi0_pll: - vdda_mipi_dsi1_pll: - vdda_qlink_lv: - vdda_qlink_lv_ck: - vdda_qrefs_0p875: - vdda_pcie_core: - vdda_pll_cc_ebi01: - vdda_pll_cc_ebi23: - vdda_sp_sensor: - vdda_ufs1_core: - vdda_ufs2_core: - vdda_usb1_ss_core: - vdda_usb2_ss_core: - src_pp875_l1a: ldo1 { - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; - regulator-initial-mode = ; - }; - - vddpx_10: - src_pp1200_l2a: ldo2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - - /* TODO: why??? */ - regulator-always-on; - }; - - pp1000_l3a_sdr845: ldo3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-initial-mode = ; - }; - - vdd_wcss_cx: - vdd_wcss_mx: - vdda_wcss_pll: - src_pp800_l5a: ldo5 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-initial-mode = ; - }; - - vddpx_13: - src_pp1800_l6a: ldo6 { - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <1856000>; - regulator-initial-mode = ; - }; - - pp1800_l7a_wcn3990: ldo7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - src_pp1200_l8a: ldo8 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1248000>; - regulator-initial-mode = ; - }; - - pp1800_dx_pen: - src_pp1800_l9a: ldo9 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - src_pp1800_l10a: ldo10 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - pp1000_l11a_sdr845: ldo11 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1048000>; - regulator-initial-mode = ; - }; - - vdd_qfprom: - vdd_qfprom_sp: - vdda_apc1_cs_1p8: - vdda_gfx_cs_1p8: - vdda_qrefs_1p8: - vdda_qusb_hs0_1p8: - vddpx_11: - src_pp1800_l12a: ldo12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vddpx_2: - src_pp2950_l13a: ldo13 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - src_pp1800_l14a: ldo14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - src_pp1800_l15a: ldo15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - pp2700_l16a: ldo16 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2704000>; - regulator-initial-mode = ; - }; - - src_pp1300_l17a: ldo17 { - regulator-min-microvolt = <1304000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - pp2700_l18a: ldo18 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - /* - * NOTE: this rail should have been called - * src_pp3300_l19a in the schematic - */ - src_pp3000_l19a: ldo19 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - - regulator-initial-mode = ; - }; - - src_pp2950_l20a: ldo20 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - src_pp2950_l21a: ldo21 { - regulator-min-microvolt = <2704000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - pp3300_hub: - src_pp3300_l22a: ldo22 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - /* - * HACK: Should add a usb hub node and driver - * to turn this on and off at suspend/resume time - */ - regulator-boot-on; - regulator-always-on; - }; - - pp3300_l23a_ch1_wcn3990: ldo23 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3312000>; - regulator-initial-mode = ; - }; - - vdda_qusb_hs0_3p1: - src_pp3075_l24a: ldo24 { - regulator-min-microvolt = <3088000>; - regulator-max-microvolt = <3088000>; - regulator-initial-mode = ; - }; - - pp3300_l25a_ch0_wcn3990: ldo25 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - pp1200_hub: - vdda_hp_pcie_1p2: - vdda_hv_ebi0: - vdda_hv_ebi1: - vdda_hv_ebi2: - vdda_hv_ebi3: - vdda_mipi_csi_1p25: - vdda_mipi_dsi0_1p2: - vdda_mipi_dsi1_1p2: - vdda_pcie_1p2: - vdda_ufs1_1p2: - vdda_ufs2_1p2: - vdda_usb1_ss_1p2: - vdda_usb2_ss_1p2: - src_pp1200_l26a: ldo26 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - pp3300_dx_pen: - src_pp3300_l28a: ldo28 { - regulator-min-microvolt = <3304000>; - regulator-max-microvolt = <3304000>; - regulator-initial-mode = ; - }; - - src_pp1800_lvs1: lvs1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - src_pp1800_lvs2: lvs2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - - regulators-1 { - compatible = "qcom,pm8005-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&src_vph_pwr>; - vdd-s2-supply = <&src_vph_pwr>; - vdd-s3-supply = <&src_vph_pwr>; - vdd-s4-supply = <&src_vph_pwr>; - - src_pp600_s3c: smps3 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <600000>; - }; - }; -}; - -edp_brij_i2c: &i2c3 { - status = "okay"; - clock-frequency = <400000>; - - sn65dsi86_bridge: bridge@2d { - compatible = "ti,sn65dsi86"; - reg = <0x2d>; - pinctrl-names = "default"; - pinctrl-0 = <&edp_brij_en &edp_brij_irq>; - - interrupt-parent = <&tlmm>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; - - vpll-supply = <&src_pp1800_s4a>; - vccio-supply = <&src_pp1800_s4a>; - vcca-supply = <&src_pp1200_l2a>; - vcc-supply = <&src_pp1200_l2a>; - - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; - clock-names = "refclk"; - - no-hpd; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sn65dsi86_in: endpoint { - remote-endpoint = <&mdss_dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - sn65dsi86_out: endpoint { - remote-endpoint = <&panel_in_edp>; - }; - }; - }; - }; -}; - -ap_pen_1v8: &i2c11 { - status = "okay"; - clock-frequency = <400000>; - - digitizer@9 { - compatible = "wacom,w9013", "hid-over-i2c"; - reg = <0x9>; - pinctrl-names = "default"; - pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; - - vdd-supply = <&pp3300_dx_pen>; - vddl-supply = <&pp1800_dx_pen>; - post-power-on-delay-ms = <100>; - - interrupt-parent = <&tlmm>; - interrupts = <24 IRQ_TYPE_LEVEL_LOW>; - - hid-descr-addr = <0x1>; - }; -}; - -amp_i2c: &i2c12 { - status = "okay"; - clock-frequency = <400000>; -}; - -ap_ts_i2c: &i2c14 { - status = "okay"; - clock-frequency = <400000>; - - touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l &ts_reset_l>; - - interrupt-parent = <&tlmm>; - interrupts = <125 IRQ_TYPE_LEVEL_LOW>; - - vcc33-supply = <&src_pp3300_l28a>; - - reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; - }; -}; - -&gpu { - status = "okay"; -}; - -&ipa { - qcom,gsi-loader = "modem"; - status = "okay"; -}; - -&lpasscc { - status = "okay"; -}; - -&mdss { - status = "okay"; -}; - -&mdss_dsi0 { - status = "okay"; - vdda-supply = <&vdda_mipi_dsi0_1p2>; - - ports { - port@1 { - endpoint { - remote-endpoint = <&sn65dsi86_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&mdss_dsi0_phy { - status = "okay"; - vdds-supply = <&vdda_mipi_dsi0_pll>; -}; - -/* - * Cheza fw does not properly program the GPU aperture to allow the - * GPU to update the SMMU pagetables for context switches. Work - * around this by dropping the "qcom,adreno-smmu" compat string. - */ -&adreno_smmu { - compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; -}; - -&mss_pil { - status = "okay"; - - iommus = <&apps_smmu 0x781 0x0>, - <&apps_smmu 0x724 0x3>; -}; - -&pm8998_pwrkey { - status = "disabled"; -}; - -&qupv3_id_0 { - status = "okay"; - iommus = <&apps_smmu 0x0 0x3>; -}; - -&qupv3_id_1 { - status = "okay"; - iommus = <&apps_smmu 0x6c0 0x3>; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>; - - vmmc-supply = <&src_pp2950_l21a>; - vqmmc-supply = <&vddpx_2>; - - cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; -}; - -&spi0 { - status = "okay"; -}; - -&spi5 { - status = "okay"; - - tpm@0 { - compatible = "google,cr50"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&h1_ap_int_odl>; - spi-max-frequency = <800000>; - interrupt-parent = <&tlmm>; - interrupts = <129 IRQ_TYPE_EDGE_RISING>; - }; -}; - -&spi10 { - status = "okay"; - - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - interrupt-parent = <&tlmm>; - interrupts = <122 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ec_ap_int_l>; - spi-max-frequency = <3000000>; - wakeup-source; - - cros_ec_pwm: pwm { - compatible = "google,cros-ec-pwm"; - #pwm-cells = <1>; - }; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -#include -#include - -&uart6 { - status = "okay"; - - pinctrl-0 = <&qup_uart6_4pin>; - - bluetooth: bluetooth { - compatible = "qcom,wcn3990-bt"; - vddio-supply = <&src_pp1800_s4a>; - vddxo-supply = <&pp1800_l7a_wcn3990>; - vddrf-supply = <&src_pp1300_l17a>; - vddch0-supply = <&pp3300_l25a_ch0_wcn3990>; - max-speed = <3200000>; - }; -}; - -&uart9 { - status = "okay"; -}; - -&ufs_mem_hc { - status = "okay"; - - reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; - - vcc-supply = <&src_pp2950_l20a>; - vcc-max-microamp = <600000>; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vdda_ufs1_core>; - vdda-pll-supply = <&vdda_ufs1_1p2>; -}; - -&usb_1 { - status = "okay"; - - /* We'll use this as USB 2.0 only */ - qcom,select-utmi-as-pipe-clk; -}; - -&usb_1_dwc3 { - /* - * The hardware design intends this port to be hooked up in peripheral - * mode, so we'll hardcode it here. Some details: - * - SDM845 expects only a single Type C connector so it has only one - * native Type C port but cheza has two Type C connectors. - * - The only source of DP is the single native Type C port. - * - On cheza we want to be able to hook DP up to _either_ of the - * two Type C connectors and want to be able to achieve 4 lanes of DP. - * - When you configure a Type C port for 4 lanes of DP you lose USB3. - * - In order to make everything work, the native Type C port is always - * configured as 4-lanes DP so it's always available. - * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then - * sent to the two Type C connectors. - * - The extra USB2 lines from the native Type C port are always - * setup as "peripheral" so that we can mux them over to one connector - * or the other if someone needs the connector configured as a gadget - * (but they only get USB2 speeds). - * - * All the hardware muxes would allow us to hook things up in different - * ways to some potential benefit for static configurations (you could - * achieve extra USB2 bandwidth by using two different ports for the - * two connectors or possibly even get USB3 peripheral mode), but in - * each case you end up forcing to disconnect/reconnect an in-use - * USB session in some cases depending on what you hotplug into the - * other connector. Thus hardcoding this as peripheral makes sense. - */ - dr_mode = "peripheral"; - - /* - * We always need the high speed pins as 4-lanes DP in case someone - * hotplugs a DP peripheral. Thus limit this port to a max of high - * speed. - */ - maximum-speed = "high-speed"; - - /* - * We don't need the usb3-phy since we run in highspeed mode always, so - * re-define these properties removing the superspeed USB PHY reference. - */ - phys = <&usb_1_hsphy>; - phy-names = "usb2-phy"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb1_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; - qcom,preemphasis-level = ; - qcom,preemphasis-width = ; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - /* We have this hooked up to a hub and we always use in host mode */ - dr_mode = "host"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdd-supply = <&vdda_usb2_ss_core>; - vdda-pll-supply = <&vdda_qusb_hs0_1p8>; - vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; - - qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; -}; - -&usb_2_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; -}; - -&wifi { - status = "okay"; - - vdd-0.8-cx-mx-supply = <&src_pp800_l5a >; - vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>; - vdd-1.3-rfa-supply = <&src_pp1300_l17a>; - vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>; -}; - -/* PINCTRL - additions to nodes defined in sdm845.dtsi */ - -&qspi_cs0 { - bias-disable; /* External pullup */ -}; - -&qspi_clk { - bias-disable; /* Rely on Cr50 internal pulldown */ -}; - -&qspi_data0 { - bias-disable; /* Rely on Cr50 internal pulldown */ -}; - -&qspi_data1 { - bias-pull-down; -}; - -&qup_i2c3_default { - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; -}; - -&qup_i2c11_default { - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; -}; - -&qup_i2c12_default { - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; -}; - -&qup_i2c14_default { - drive-strength = <2>; - - /* Has external pullup */ - bias-disable; -}; - -&qup_spi0_default { - drive-strength = <2>; - bias-disable; -}; - -&qup_spi5_default { - drive-strength = <2>; - bias-disable; -}; - -&qup_spi10_default { - drive-strength = <2>; - bias-disable; -}; - -&qup_uart9_rx { - drive-strength = <2>; - bias-pull-up; -}; - -&qup_uart9_tx { - drive-strength = <2>; - bias-disable; -}; - -/* PINCTRL - board-specific pinctrl */ -&pm8005_gpios { - gpio-line-names = "", - "", - "SLB", - ""; -}; - -&pm8998_adc { - channel@4d { - reg = ; - label = "sdm_temp"; - }; - - channel@4e { - reg = ; - label = "quiet_temp"; - }; - - channel@4f { - reg = ; - label = "lte_temp_1"; - }; - - channel@50 { - reg = ; - label = "lte_temp_2"; - }; - - channel@51 { - reg = ; - label = "charger_temp"; - }; -}; - -&pm8998_gpios { - gpio-line-names = "", - "", - "SW_CTRL", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "CFG_OPT1", - "WCSS_PWR_REQ", - "", - "CFG_OPT2", - "SLB"; -}; - -&tlmm { - /* - * pinctrl settings for pins that have no real owners. - */ - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&bios_flash_wp_r_l>, - <&ap_suspend_l_deassert>; - - pinctrl-1 = <&bios_flash_wp_r_l>, - <&ap_suspend_l_assert>; - - /* - * Hogs prevent usermode from changing the value. A GPIO can be both - * here and in the pinctrl section. - */ - ap-suspend-l-hog { - gpio-hog; - gpios = <126 GPIO_ACTIVE_LOW>; - output-low; - }; - - ap_edp_bklten: ap-edp-bklten-state { - pins = "gpio37"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - bios_flash_wp_r_l: bios-flash-wp-r-l-state { - pins = "gpio128"; - function = "gpio"; - bias-disable; - }; - - ec_ap_int_l: ec-ap-int-l-state { - pins = "gpio122"; - function = "gpio"; - bias-pull-up; - }; - - edp_brij_en: edp-brij-en-state { - pins = "gpio102"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - edp_brij_irq: edp-brij-irq-state { - pins = "gpio10"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - en_pp3300_dx_edp: en-pp3300-dx-edp-state { - pins = "gpio43"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - h1_ap_int_odl: h1-ap-int-odl-state { - pins = "gpio129"; - function = "gpio"; - bias-pull-up; - }; - - pen_eject_odl: pen-eject-odl-state { - pins = "gpio119"; - function = "gpio"; - bias-pull-up; - }; - - pen_irq_l: pen-irq-l-state { - pins = "gpio24"; - function = "gpio"; - - /* Has external pullup */ - bias-disable; - }; - - pen_pdct_l: pen-pdct-l-state { - pins = "gpio63"; - function = "gpio"; - - /* Has external pullup */ - bias-disable; - }; - - pen_rst_l: pen-rst-l-state { - pins = "gpio23"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - - /* - * The pen driver doesn't currently support - * driving this reset line. By specifying - * output-high here we're relying on the fact - * that this pin has a default pulldown at boot - * (which makes sure the pen was in reset if it - * was powered) and then we set it high here to - * take it out of reset. Better would be if the - * pen driver could control this and we could - * remove "output-high" here. - */ - output-high; - }; - - qspi_sleep: qspi-sleep-state { - pins = "gpio90", "gpio91", "gpio92", "gpio95"; - - /* - * When we're not actively transferring we want pins as GPIOs - * with output disabled so that the quad SPI IP block stops - * driving them. We rely on the normal pulls configured in - * the active state and don't redefine them here. Also note - * that we don't need the reverse (output-enable) in the - * normal mode since the "output-enable" only matters for - * GPIO function. - */ - function = "gpio"; - output-disable; - }; - - sdc2_clk: sdc2-clk-state { - pins = "sdc2_clk"; - bias-disable; - - /* - * It seems that mmc_test reports errors if drive - * strength is not 16. - */ - drive-strength = <16>; - }; - - sdc2_cmd: sdc2-cmd-state { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <16>; - }; - - sdc2_data: sdc2-data-state { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <16>; - }; - - sd_cd_odl: sd-cd-odl-state { - pins = "gpio44"; - function = "gpio"; - bias-pull-up; - }; - - ts_int_l: ts-int-l-state { - pins = "gpio125"; - function = "gpio"; - bias-pull-up; - }; - - ts_reset_l: ts-reset-l-state { - pins = "gpio118"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - }; - - ap_suspend_l_assert: ap-suspend-l-assert-state { - pins = "gpio126"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - output-low; - }; - - ap_suspend_l_deassert: ap-suspend-l-deassert-state { - pins = "gpio126"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - output-high; - }; -}; - -&venus { - status = "okay"; - - video-firmware { - iommus = <&apps_smmu 0x10b2 0x0>; - }; -}; From bae72efa3ca6674ff99668b00290376babae10f5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 16 Jul 2025 12:16:08 +0200 Subject: [PATCH 125/931] dt-bindings: arm: qcom: Remove sdm845-cheza Cheza was a prototype board, used mainly by the ChromeOS folks. Almost no working devices are known to exist, and the small amount of remaining ones are not in use anymore. Remove the compatible strings reserved for it, as, quite frankly, Cheza is no more. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20250716-topic-goodnight_cheza-v2-2-6fa8d3261813@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 3 --- 1 file changed, 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1df00d9e6de0..b5acb0d26346 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -884,9 +884,6 @@ properties: - items: - enum: - - google,cheza - - google,cheza-rev1 - - google,cheza-rev2 - lenovo,yoga-c630 - lg,judyln - lg,judyp From 43b8556e82f38cc2e7a66c9dd44d1104be4fe73c Mon Sep 17 00:00:00 2001 From: Sayali Lokhande Date: Wed, 16 Jul 2025 14:21:24 +0530 Subject: [PATCH 126/931] arm64: dts: qcom: qcs8300: Add eMMC support Add eMMC support for qcs8300 board. Signed-off-by: Sayali Lokhande Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250716085125.27169-2-quic_sayalil@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 113 ++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 7d38ddd2cc9e..3cf1d4bc7e4a 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -4120,6 +4120,69 @@ cti@6900000 { clock-names = "apb_pclk"; }; + sdhc_1: mmc@87c4000 { + compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x087c4000 0x0 0x1000>, + <0x0 0x087c5000 0x0 0x1000>; + reg-names = "hc", + "cqhci"; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + resets = <&gcc GCC_SDCC1_BCR>; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + iommus = <&apps_smmu 0x0 0x0>; + interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + qcom,dll-config = <0x000f64ee>; + qcom,ddr-config = <0x80040868>; + supports-cqe; + dma-coherent; + + status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + usb_1_hsphy: phy@8904000 { compatible = "qcom,qcs8300-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; @@ -5325,6 +5388,56 @@ qup_uart16_rx: qup-uart16-rx-state { pins = "gpio13"; function = "qup2_se0"; }; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-bus-hold; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-bus-hold; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-bus-hold; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-bus-hold; + }; + }; }; sram: sram@146d8000 { From d81448d49cb26d9255479c7c74de03a257b5c528 Mon Sep 17 00:00:00 2001 From: Sayali Lokhande Date: Wed, 16 Jul 2025 14:21:25 +0530 Subject: [PATCH 127/931] arm64: dts: qcom: qcs8300-ride: Enable SDHC1 node Enable sdhc1 support for qcs8300 ride platform. Signed-off-by: Sayali Lokhande Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250716085125.27169-3-quic_sayalil@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 8c166ead912c..9c37a0f5ba25 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -17,6 +17,7 @@ / { aliases { serial0 = &uart7; + mmc0 = &sdhc_1; }; chosen { @@ -332,6 +333,26 @@ &serdes0 { status = "okay"; }; +&sdhc_1 { + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + vmmc-supply = <&vreg_l8a>; + vqmmc-supply = <&vreg_s4a>; + + non-removable; + no-sd; + no-sdio; + + status = "okay"; +}; + &tlmm { ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { From f578e5f0b8b5f81e19e5f97a95e9cadf4e9c699d Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Tue, 15 Jul 2025 10:57:38 +0530 Subject: [PATCH 128/931] arm64: dts: qcom: sm8450-qrd: add pmic glink node Add the pmic glink node linked with the DWC3 USB controller switched to OTG mode and tagged with usb-role-switch. Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250715052739.3831549-2-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 51 ++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 8c39fbcaad80..56db5f79f59d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -28,6 +28,49 @@ chosen { stdout-path = "serial0:115200n8"; }; + pmic-glink { + compatible = "qcom,sm8450-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 91 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + }; + }; + + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -461,8 +504,8 @@ &usb_1 { status = "okay"; }; -&usb_1_dwc3 { - dr_mode = "peripheral"; +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; }; &usb_1_hsphy { @@ -487,3 +530,7 @@ &usb_1_qmpphy { vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p91>; }; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; From c5a87e3a6b3ed051466a20cb954be1c138199c56 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Tue, 15 Jul 2025 10:57:39 +0530 Subject: [PATCH 129/931] arm64: dts: qcom: sm8450: Flatten usb controller node Flatten usb controller node and update to using latest bindings and flattened driver approach. Reviewed-by: Konrad Dybcio Signed-off-by: Krishna Kurapati Link: https://lore.kernel.org/r/20250715052739.3831549-3-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 5 -- .../dts/qcom/sm8450-sony-xperia-nagara.dtsi | 5 +- arch/arm64/boot/dts/qcom/sm8450.dtsi | 57 +++++++++---------- 3 files changed, 27 insertions(+), 40 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 2ff40a120aad..0c6aa7ddf432 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -1199,11 +1199,6 @@ &usb_1 { status = "okay"; }; -&usb_1_dwc3 { - dr_mode = "otg"; - usb-role-switch; -}; - &usb_1_dwc3_hs { remote-endpoint = <&pmic_glink_hs_in>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi index cc1335a07a35..6bd315e10992 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi @@ -781,11 +781,8 @@ &uart7 { }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "peripheral"; + status = "okay"; }; &usb_1_hsphy { diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 33574ad706b9..2baef6869ed7 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5418,12 +5418,9 @@ opp-202000000 { }; usb_1: usb@a6f8800 { - compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; + compatible = "qcom,sm8450-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a600000 0 0xfc100>; status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -5442,12 +5439,14 @@ usb_1: usb@a6f8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", @@ -5461,36 +5460,32 @@ usb_1: usb@a6f8800 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; interconnect-names = "usb-ddr", "apps-usb"; - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = ; - iommus = <&apps_smmu 0x0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", "usb3-phy"; + iommus = <&apps_smmu 0x0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", "usb3-phy"; + usb-role-switch; - ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@0 { - reg = <0>; + port@0 { + reg = <0>; - usb_1_dwc3_hs: endpoint { - }; + usb_1_dwc3_hs: endpoint { }; + }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - usb_1_dwc3_ss: endpoint { - remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; - }; + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; }; }; }; From ad9abc9ba4046360f23a410f74ef78e646c08aa1 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 14 Jul 2025 13:48:15 +0200 Subject: [PATCH 130/931] arm64: dts: qcom: x1e80100-crd: Add USB multiport fingerprint reader The X1E80100 CRD has a Goodix fingerprint reader connected to the USB multiport controller on eUSB6. All other ports (including USB super-speed pins) are unused. Set it up in the device tree together with the NXP PTN3222 repeater. Signed-off-by: Stephan Gerhold Reviewed-by: Johan Hovold Tested-by: Johan Hovold Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250714-x1e80100-crd-fp-v2-1-3246eb02b679@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 64 ++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index c9f0d5052670..730b27c878fc 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1016,6 +1016,27 @@ retimer_ss0_con_sbu_out: endpoint { }; }; +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + + vdd1v8-supply = <&vreg_l4b_1p8>; + vdd3v3-supply = <&vreg_l13b_3p0>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + + #phy-cells = <0>; + }; +}; + &i2c7 { clock-frequency = <400000>; @@ -1466,6 +1487,14 @@ edp_reg_en: edp-reg-en-state { bias-disable; }; + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + hall_int_n_default: hall-int-n-state { pins = "gpio92"; function = "gpio"; @@ -1747,3 +1776,38 @@ &usb_1_ss2_dwc3_hs { &usb_1_ss2_qmpphy_out { remote-endpoint = <&retimer_ss2_ss_in>; }; + +&usb_mp { + /* Only second port is used with USB 2.0 maximum speed */ + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; From 5433560caa5e7e677a8d4310bbec08312be765b4 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 10 Jul 2025 20:47:08 +0300 Subject: [PATCH 131/931] arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Replace clock-frequency in camera sensor node The clock-frequency for camera sensors has been deprecated in favour of the assigned-clocks and assigned-clock-rates properties. Replace it in the device tree. Signed-off-by: Laurent Pinchart Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250710174808.5361-13-laurent.pinchart@ideasonboard.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso index 51f1a4883ab8..dbe1911d8e47 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c-navigation-mezzanine.dtso @@ -44,7 +44,8 @@ camera@10 { clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; clock-names = "xvclk"; - clock-frequency = <19200000>; + assigned-clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + assigned-clock-rates = <19200000>; /* * The &vreg_s4a_1p8 trace is powered on as a, From 3a99873d8b9f6c1ec027987fff7b32eab9273316 Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Sun, 22 Jun 2025 18:26:47 +0000 Subject: [PATCH 132/931] dt-bindings: arm: qcom: add Sony Xperia SP Document the Sony Xperia SP (huashan), which uses the MSM8960T SoC. The MSM8960T is a variant of the MSM8960 featuring an upgraded GPU (Adreno 320 instead of Adreno 225) and a slightly overclocked CPU (1.7GHz instead of 1.5GHz). Signed-off-by: Antony Kurniawan Soemardi Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250623-msm8960-sdcard-v2-4-340a5e8f7df0@smankusors.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index ae43b3556580..b9e8defc7ffe 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -203,6 +203,12 @@ properties: - samsung,expressatt - const: qcom,msm8960 + - items: + - enum: + - sony,huashan + - const: qcom,msm8960t + - const: qcom,msm8960 + - items: - enum: - lge,hammerhead From d2f146b3dfbcc2550b9c805b49dab53b4babf2e8 Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Sun, 22 Jun 2025 18:26:50 +0000 Subject: [PATCH 133/931] ARM: dts: qcom: add device tree for Sony Xperia SP Add initial device tree support for the Sony Xperia SP (codename: sony-huashan), a smartphone based on the Qualcomm MSM8960T SoC. There are two variants of the Xperia SP, one without LTE and one with LTE. This device tree should work for both variants, though it has only been tested on the non-LTE variant. The following are currently supported: - Serial console support via gsbi8 - GPIO keys for volume up/down buttons - PM8921 keypad with camera focus/capture keys - eMMC (sdcc1) and micro SD card (sdcc3) support - USB OTG support Other hardware features are not yet implemented. Booting notes: Booting a kernel requires using the Sony ELF boot image format, which embeds the kernel, ramdisk, RPM firmware, and cmdline. This can be created using the `mkelf` tool. For example: python2 mkelf.py -o boot.img \ kernel+dtb@0x80208000 \ ramdisk.img@0x81900000 \ RPM.bin@0x00020000,rpm \ cmdline.txt@cmdline The resulting `boot.img` can then be flashed via fastboot. A detailed guide, including an alternative method, is available at: https://wiki.postmarketos.org/wiki/Sony_Xperia_SP_(sony-huashan) Signed-off-by: Antony Kurniawan Soemardi Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250623-msm8960-sdcard-v2-5-340a5e8f7df0@smankusors.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/Makefile | 1 + .../dts/qcom/qcom-msm8960-sony-huashan.dts | 361 ++++++++++++++++++ 2 files changed, 362 insertions(+) create mode 100644 arch/arm/boot/dts/qcom/qcom-msm8960-sony-huashan.dts diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index e875b5d25e84..c7873dcef154 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8926-samsung-matisselte.dtb \ qcom-msm8960-cdp.dtb \ qcom-msm8960-samsung-expressatt.dtb \ + qcom-msm8960-sony-huashan.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ qcom-msm8974-samsung-hlte.dtb \ qcom-msm8974-sony-xperia-rhine-amami.dtb \ diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-sony-huashan.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-sony-huashan.dts new file mode 100644 index 000000000000..f2f59fc8b9b6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-sony-huashan.dts @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025, Antony Kurniawan Soemardi + */ +#include +#include +#include +#include + +#include "qcom-msm8960.dtsi" +#include "pm8921.dtsi" + +/ { + model = "Sony Xperia SP"; + compatible = "sony,huashan", "qcom,msm8960t", "qcom,msm8960"; + chassis-type = "handset"; + + aliases { + serial0 = &gsbi8_serial; + mmc0 = &sdcc1; /* SDCC1 eMMC slot */ + mmc1 = &sdcc3; /* SDCC3 SD card slot */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm8921_gpio 21 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&pm8921_gpio 20 GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + linux,code = ; + }; + }; +}; + +&gsbi8 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi8_serial { + status = "okay"; +}; + +&pm8921 { + interrupts-extended = <&msmgpio 104 IRQ_TYPE_LEVEL_LOW>; +}; + +&pm8921_gpio { + keypad_default_state: keypad-default-state { + keypad-sense-pins { + pins = "gpio1", "gpio2", "gpio3", "gpio4", "gpio5"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-pull-up; + input-enable; + power-source = ; + qcom,drive-strength = ; + qcom,pull-up-strength = ; + }; + + keypad-drive-pins { + pins = "gpio9", "gpio10"; + function = PMIC_GPIO_FUNC_FUNC1; + bias-disable; + drive-open-drain; + output-low; + power-source = ; + qcom,drive-strength = ; + }; + }; +}; + +&pm8921_keypad { + linux,keymap = < + MATRIX_KEY(1, 0, KEY_CAMERA_FOCUS) + MATRIX_KEY(1, 1, KEY_CAMERA) + >; + keypad,num-rows = <2>; + keypad,num-columns = <5>; + + pinctrl-0 = <&keypad_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&rpm { + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s4>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + vdd_ncp-supply = <&pm8921_l6>; + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l21_l23_l29-supply = <&pm8921_s8>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l26-supply = <&pm8921_s7>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + vdd_l29-supply = <&pm8921_s8>; + + /* Buck SMPS */ + pm8921_s1: s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s2: s2 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + pm8921_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <4800000>; + bias-pull-down; + }; + + pm8921_s4: s4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + qcom,force-mode = ; + }; + + pm8921_s7: s7 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + pm8921_s8: s8 { + regulator-always-on; + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + }; + + /* PMOS LDO */ + pm8921_l1: l1 { + regulator-always-on; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + bias-pull-down; + }; + + pm8921_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l3: l3 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + bias-pull-down; + }; + + pm8921_l4: l4 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l5: l5 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l6: l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l7: l7 { + regulator-always-on; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l8: l8 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l9: l9 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + bias-pull-down; + }; + + pm8921_l10: l10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l11: l11 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l12: l12 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + pm8921_l16: l16 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l17: l17 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + }; + + pm8921_l18: l18 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + bias-pull-down; + }; + + pm8921_l21: l21 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + pm8921_l22: l22 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + bias-pull-down; + }; + + pm8921_l23: l23 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + pm8921_l24: l24 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + + pm8921_l25: l25 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + bias-pull-down; + }; + + /* Low Voltage Switch */ + pm8921_lvs1: lvs1 { + bias-pull-down; + }; + + pm8921_lvs2: lvs2 { + bias-pull-down; + }; + + pm8921_lvs3: lvs3 { + bias-pull-down; + }; + + pm8921_lvs4: lvs4 { + bias-pull-down; + }; + + pm8921_lvs5: lvs5 { + bias-pull-down; + }; + + pm8921_lvs6: lvs6 { + bias-pull-down; + }; + + pm8921_lvs7: lvs7 { + bias-pull-down; + }; + + pm8921_ncp: ncp { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <1600000>; + }; + }; +}; + +&sdcc1 { + vmmc-supply = <&pm8921_l5>; + status = "okay"; +}; + +&sdcc3 { + vmmc-supply = <&pm8921_l6>; + vqmmc-supply = <&pm8921_l7>; + + pinctrl-0 = <&sdcc3_default_state>; + pinctrl-1 = <&sdcc3_sleep_state>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&usb_hs1_phy { + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; +}; + +&usb1 { + dr_mode = "otg"; + status = "okay"; +}; From 3f9e5d74d1943a9f98c814970b709098a1108845 Mon Sep 17 00:00:00 2001 From: Shinjo Park Date: Fri, 13 Jun 2025 21:42:53 +0200 Subject: [PATCH 134/931] ARM: dts: qcom: pm8921: add vibrator device node Use the same definition as pm8058.dtsi. Since vibrator is used only by some devices, disable it by default and let it be enabled explicitly. Signed-off-by: Shinjo Park Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250613194253.20080-1-peremen@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/pm8921.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom/pm8921.dtsi b/arch/arm/boot/dts/qcom/pm8921.dtsi index 058962af3005..535cb6a2543f 100644 --- a/arch/arm/boot/dts/qcom/pm8921.dtsi +++ b/arch/arm/boot/dts/qcom/pm8921.dtsi @@ -17,6 +17,12 @@ pwrkey@1c { pull-up; }; + pm8921_vibrator: vibrator@4a { + compatible = "qcom,pm8921-vib"; + reg = <0x4a>; + status = "disabled"; + }; + pm8921_mpps: mpps@50 { compatible = "qcom,pm8921-mpp", "qcom,ssbi-mpp"; From fdf913d0c44f330e83905e7f1ab738dc63b2b82c Mon Sep 17 00:00:00 2001 From: Adam Honse Date: Wed, 18 Jun 2025 23:45:44 +0200 Subject: [PATCH 135/931] ARM: dts: qcom: msm8974-samsung-hlte: Add touchkey support Add support for the touchkeys on the Samsung Galaxy Note 3 (hlte). Signed-off-by: Adam Honse Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250618-hlte-touchkey-v2-1-2cf188b57e31@lucaweiss.eu Signed-off-by: Bjorn Andersson --- .../dts/qcom/qcom-msm8974-samsung-hlte.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts index 903bb4d12513..b7a1367d3470 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts @@ -50,6 +50,34 @@ key-volume-up { }; }; + i2c-touchkey { + compatible = "i2c-gpio"; + + sda-gpios = <&tlmm 95 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 96 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&i2c_touchkey_pins>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + touchkey@20 { + compatible = "cypress,midas-touchkey"; + reg = <0x20>; + + interrupts-extended = <&pm8941_gpios 29 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&touchkey_pin>; + pinctrl-names = "default"; + + vcc-supply = <&pm8941_lvs3>; + vdd-supply = <&pm8941_l13>; + + linux,keycodes = ; + }; + }; + touch_ldo: regulator-touch { compatible = "regulator-fixed"; regulator-name = "touch-ldo"; @@ -149,6 +177,14 @@ touch_ldo_pin: touchscreen-ldo-state { power-source = ; qcom,drive-strength = ; }; + + touchkey_pin: touchkey-int-state { + pins = "gpio29"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; }; &remoteproc_adsp { @@ -332,6 +368,9 @@ pm8941_l24: l24 { regulator-min-microvolt = <3075000>; regulator-max-microvolt = <3075000>; }; + + pm8941_lvs1: lvs1 {}; + pm8941_lvs3: lvs3 {}; }; }; @@ -378,6 +417,12 @@ sdhc3_pin_a: sdhc3-pin-active-state { drive-strength = <8>; bias-disable; }; + + i2c_touchkey_pins: i2c-touchkey-state { + pins = "gpio95", "gpio96"; + function = "gpio"; + bias-pull-up; + }; }; &usb { From 60fdba1dccd81420bbe8da0d7483b4f28c7fa833 Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Mon, 30 Jun 2025 22:54:10 +0200 Subject: [PATCH 136/931] arm64: dts: qcom: x1-crd: Enable HBR3 on external DPs When no link frequencies are set, msm/dp driver defaults to HBR2 speed. Explicitly list supported frequencies including HBR3/8.1Gbps for all external DisplayPort(s). Signed-off-by: Aleksandrs Vinarskis Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250630205514.14022-2-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 730b27c878fc..35d26d14b6bd 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1150,6 +1150,7 @@ &mdss_dp0 { &mdss_dp0_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp1 { @@ -1158,6 +1159,7 @@ &mdss_dp1 { &mdss_dp1_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp2 { @@ -1166,6 +1168,7 @@ &mdss_dp2 { &mdss_dp2_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp3 { From 93109afda01593c2ddadb4ec1c42b3bdf695ee2a Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Mon, 30 Jun 2025 22:54:11 +0200 Subject: [PATCH 137/931] arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: Enable HBR3 on external DPs When no link frequencies are set, msm/dp driver defaults to HBR2 speed. Explicitly list supported frequencies including HBR3/8.1Gbps for all external DisplayPort(s). Signed-off-by: Aleksandrs Vinarskis Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250630205514.14022-3-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index ac1dddf27da3..2308d5a0e3af 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -995,6 +995,7 @@ &mdss_dp0 { &mdss_dp0_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp1 { @@ -1003,6 +1004,7 @@ &mdss_dp1 { &mdss_dp1_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_dp3 { From 8839b8e6e849e209b52bf0ae4d0770d89c036b0e Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Mon, 30 Jun 2025 18:41:59 -0400 Subject: [PATCH 138/931] arm64: dts: qcom: sdm670-google-sargo: enable charger The Pixel 3a has a rechargeable 3000 mAh battery. Describe it and enable its charging controller in PM660. Signed-off-by: Richard Acayan Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250630224158.249726-2-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/sdm670-google-sargo.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index 74b5d9c68eb6..d01422844fbf 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -33,6 +33,14 @@ / { aliases { }; + battery: battery { + compatible = "simple-battery"; + + voltage-min-design-microvolt = <3312000>; + voltage-max-design-microvolt = <4400000>; + charge-full-design-microamp-hours = <3000000>; + }; + chosen { stdout-path = "serial0:115200n8"; @@ -478,6 +486,15 @@ &mdss_mdp { status = "okay"; }; +&pm660_charger { + monitored-battery = <&battery>; + status = "okay"; +}; + +&pm660_rradc { + status = "okay"; +}; + &pm660l_flash { status = "okay"; From 285fee8c65efd7969f9376ed9798afece9a0ccc9 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 1 Aug 2025 10:21:39 +0200 Subject: [PATCH 139/931] arm64: dts: qcom: sdm845*: Use definition for msm-id For all boards it's QCOM_ID_SDM845 except Dragonboard, where it's QCOM_ID_SDA845. Except for OnePlus 6 / 6T, which is handled in following commit. Signed-off-by: David Heidelberg Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250801-sdm845-msmid-v2-1-9f44d125ee44@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 3 ++- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 3 ++- arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 3 ++- 5 files changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index b5c63fa0365d..3ec2c7864f1e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include #include #include @@ -18,7 +19,7 @@ / { model = "Thundercomm Dragonboard 845c"; compatible = "thundercomm,db845c", "qcom,sdm845"; - qcom,msm-id = <341 0x20001>; + qcom,msm-id = ; qcom,board-id = <8 0>; aliases { diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 2cf7b5e1243c..87e913343cbb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include #include #include #include @@ -17,7 +18,7 @@ / { model = "SHIFT SHIFT6mq"; compatible = "shift,axolotl", "qcom,sdm845"; - qcom,msm-id = <321 0x20001>; + qcom,msm-id = ; qcom,board-id = <11 0>; aliases { diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index a3a304e1ac87..f3f4c0900572 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021, Konrad Dybcio */ +#include #include #include #include @@ -12,7 +13,7 @@ #include "pmi8998.dtsi" / { - qcom,msm-id = <321 0x20001>; /* SDM845 v2.1 */ + qcom,msm-id = ; /* SDM845 v2.1 */ qcom,board-id = <8 0>; aliases { diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 7810b0ce7591..7480c8d7ac5b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -2,6 +2,7 @@ /dts-v1/; +#include #include #include #include @@ -32,7 +33,7 @@ / { /* required for bootloader to select correct board */ qcom,board-id = <69 0>; - qcom,msm-id = <321 0x20001>; + qcom,msm-id = ; aliases { serial1 = &uart6; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 63cf879a7a29..1c50a0563bc4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include #include #include #include @@ -38,7 +39,7 @@ / { chassis-type = "handset"; /* required for bootloader to select correct board */ - qcom,msm-id = <0x141 0x20001>; + qcom,msm-id = ; qcom,board-id = <0x2a 0x0>; aliases { From f72f3aac4a9a990701455a4759a49393cd5802d6 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Fri, 1 Aug 2025 10:21:40 +0200 Subject: [PATCH 140/931] arm64: dts: qcom: sdm845-oneplus: Deduplicate shared entries Use the definition for qcom,msm-id and put them into the common dtsi. Signed-off-by: David Heidelberg Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250801-sdm845-msmid-v2-2-9f44d125ee44@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts | 2 -- arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts | 2 -- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index b118d666e535..dcfffb271fcf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -7,6 +7,7 @@ /dts-v1/; +#include #include #include #include @@ -21,6 +22,9 @@ /delete-node/ &rmtfs_mem; / { + chassis-type = "handset"; + qcom,msm-id = ; + aliases { serial0 = &uart9; serial1 = &uart6; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index 4005e04d998a..cd5546b69d13 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -10,8 +10,6 @@ / { model = "OnePlus 6"; compatible = "oneplus,enchilada", "qcom,sdm845"; - chassis-type = "handset"; - qcom,msm-id = <0x141 0x20001>; qcom,board-id = <8 0 17819 22>; battery: battery { diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index 9471ada0d6ad..b4212626b429 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -10,8 +10,6 @@ / { model = "OnePlus 6T"; compatible = "oneplus,fajita", "qcom,sdm845"; - chassis-type = "handset"; - qcom,msm-id = <0x141 0x20001>; qcom,board-id = <8 0 18801 41>; battery: battery { From dc231840dca64793da7a80ff156fa1d99584f3ea Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Wed, 30 Jul 2025 18:52:30 +0530 Subject: [PATCH 141/931] arm64: dts: qcom: qcm2290: Add TCSR download mode address Allow configuration of download mode via qcom_scm driver via specifying download mode register address in the TCSR space. It is especially useful for a clean watchdog reset without entry into download mode. The problem remained un-noticed until now since error reporting for missing download mode configuration feature was explicitly suppressed. Signed-off-by: Sumit Garg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250730132230.247727-1-sumit.garg@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index fa24b77a31a7..5edf9ca29ca0 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -154,6 +154,7 @@ scm: scm { compatible = "qcom,scm-qcm2290", "qcom,scm"; clocks = <&rpmcc RPM_SMD_CE1_CLK>; clock-names = "core"; + qcom,dload-mode = <&tcsr_regs 0x13000>; #reset-cells = <1>; interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; From c2e07613b8d40f0ac60dd9b28c0dd15f9a298c11 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 29 Jul 2025 16:40:53 +0200 Subject: [PATCH 142/931] arm64: dts: qcom: sm8650: Add ACD levels for GPU Update GPU node to include acd level values. Signed-off-by: Neil Armstrong Reviewed-by: Akhil P Oommen Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250729-topic-sm8650-upstream-gpu-acd-level-v1-1-258090038a41@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 34ec162db53d..d6794901f06b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4127,72 +4127,84 @@ zap-shader { /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { - compatible = "operating-points-v2"; + compatible = "operating-points-v2-adreno", + "operating-points-v2"; opp-231000000 { opp-hz = /bits/ 64 <231000000>; opp-level = ; opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xc82f5ffd>; }; opp-310000000 { opp-hz = /bits/ 64 <310000000>; opp-level = ; opp-peak-kBps = <2136718>; + qcom,opp-acd-level = <0xc82c5ffd>; }; opp-366000000 { opp-hz = /bits/ 64 <366000000>; opp-level = ; opp-peak-kBps = <6074218>; + qcom,opp-acd-level = <0xc02e5ffd>; }; opp-422000000 { opp-hz = /bits/ 64 <422000000>; opp-level = ; opp-peak-kBps = <8171875>; + qcom,opp-acd-level = <0xc02d5ffd>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-level = ; opp-peak-kBps = <8171875>; + qcom,opp-acd-level = <0xc02a5ffd>; }; opp-578000000 { opp-hz = /bits/ 64 <578000000>; opp-level = ; opp-peak-kBps = <8171875>; + qcom,opp-acd-level = <0x882c5ffd>; }; opp-629000000 { opp-hz = /bits/ 64 <629000000>; opp-level = ; opp-peak-kBps = <10687500>; + qcom,opp-acd-level = <0x882a5ffd>; }; opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; opp-peak-kBps = <12449218>; + qcom,opp-acd-level = <0x882a5ffd>; }; opp-720000000 { opp-hz = /bits/ 64 <720000000>; opp-level = ; opp-peak-kBps = <12449218>; + qcom,opp-acd-level = <0x882a5ffd>; }; opp-770000000 { opp-hz = /bits/ 64 <770000000>; opp-level = ; opp-peak-kBps = <12449218>; + qcom,opp-acd-level = <0x882a5ffd>; }; opp-834000000 { opp-hz = /bits/ 64 <834000000>; opp-level = ; opp-peak-kBps = <14398437>; + qcom,opp-acd-level = <0x882a5ffd>; }; }; }; From d15cb624a60ab0119ec1b92d0a94f1cc305019e5 Mon Sep 17 00:00:00 2001 From: Ling Xu Date: Tue, 29 Jul 2025 08:42:59 +0530 Subject: [PATCH 143/931] arm64: dts: qcom: sm6150: Add ADSP and CDSP fastrpc nodes Add ADSP and CDSP fastrpc nodes for SM6150 platform. Signed-off-by: Ling Xu Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250729031259.4190916-1-quic_lxu5@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 87 ++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi index 591fcb740259..b66bc13c0b5e 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -3319,6 +3319,56 @@ glink-edge { mboxes = <&apss_shared 4>; label = "cdsp"; qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x1081 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1082 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1083 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1084 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1085 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1086 0x0>; + dma-coherent; + }; + }; }; }; @@ -3991,6 +4041,43 @@ glink_edge: glink-edge { mboxes = <&apss_shared 24>; label = "lpass"; qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1723 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1724 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1725 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1726 0x0>; + qcom,nsessions = <5>; + dma-coherent; + }; + }; }; }; }; From 1d363a6cf8a2627f31bc3609a0fa9d85dfb0d9dc Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Mon, 28 Jul 2025 11:34:26 +0200 Subject: [PATCH 144/931] arm64: dts: qcom: qcm2290: Enable HS eMMC timing modes The host controller supports HS200/HS400 and HS400 enhanced strobe mode. On RB1, this improves Linux eMMC read speed, from ~170MB/s to 300MB/s. Signed-off-by: Loic Poulain Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250728093426.1413379-1-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 5edf9ca29ca0..eb489d0a684a 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -954,6 +954,11 @@ &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, qcom,ddr-config = <0x80040868>; bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "disabled"; sdhc1_opp_table: opp-table { From 642af3f3d59003657483d60bb6b7229a43ff56e7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 28 Jul 2025 11:33:52 +0200 Subject: [PATCH 145/931] arm64: dts: qcom: sc7280-chrome-common: Remove duplicate node sc7280.dtsi already includes the very same definition (bar 'memory@' vs 'video@', which doesn't matter). Remove the duplicate to fix a lot of dtbs W=1 warning instances (unique_unit_address_if_enabled). Signed-off-by: Konrad Dybcio Acked-by: Douglas Anderson Link: https://lore.kernel.org/r/20250728-topic-chrome_dt_fixup-v1-1-1fc38a95d5ea@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi index 8b4239f13748..84c6d662b54f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -44,11 +44,6 @@ camera_mem: memory@8ad00000 { reg = <0x0 0x8ad00000 0x0 0x500000>; no-map; }; - - venus_mem: memory@8b200000 { - reg = <0x0 0x8b200000 0x0 0x500000>; - no-map; - }; }; }; From d72cb0551d113a0a42e12dcdfdad78ade2c63f50 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Mon, 28 Jul 2025 09:28:12 +0530 Subject: [PATCH 146/931] arm64: dts: qcom: sc7280: Flatten usb controller nodes Flatten usb controller nodes and update to using latest bindings and flattened driver approach. Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Tested-by: Konrad Dybcio # FP5 Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250728035812.2762957-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcm6490-fairphone-fp5.dts | 6 +- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 7 +- .../boot/dts/qcom/qcm6490-shift-otter.dts | 6 +- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 6 +- .../arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 6 +- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 6 +- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 6 +- arch/arm64/boot/dts/qcom/sc7280.dtsi | 106 ++++++++---------- .../boot/dts/qcom/sm7325-nothing-spacewar.dts | 6 +- 9 files changed, 62 insertions(+), 93 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index e115b6a52b29..f17ac3dc9b06 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -1364,12 +1364,10 @@ &ufs_mem_phy { }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 7a155ef6492e..8ed6e28b0c29 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -751,12 +751,9 @@ &ufs_mem_phy { }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - /delete-property/ usb-role-switch; dr_mode = "peripheral"; + + status = "okay"; }; &usb_1_hsphy { diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index b9a0f7ac4d9c..eb8efba1b9dd 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -910,12 +910,10 @@ &ufs_mem_phy { }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 8f15be633946..7509c27bd3f8 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1127,12 +1127,10 @@ bluetooth: bluetooth { }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "otg"; usb-role-switch; + + status = "okay"; }; &usb_1_dwc3_hs { diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 2ba4ea60cb14..5c5e4f1dd221 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -621,15 +621,13 @@ CROS_STD_MAIN_KEYMAP }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "host"; #address-cells = <1>; #size-cells = <0>; + status = "okay"; + /* 2.x hub on port 1 */ usb_hub_2_x: hub@1 { compatible = "usbbda,5411"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index b5fe7356be48..3103f94cd685 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -81,11 +81,9 @@ channel@403 { }; &usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { dr_mode = "otg"; + + status = "okay"; }; &usb_2_hsphy { diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 90e5b9ab5b84..ccd39a1baeda 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -520,11 +520,9 @@ &ufs_mem_phy { }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "host"; + + status = "okay"; }; &usb_1_hsphy { diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 64a2abd30100..0fa8d34999a3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3711,14 +3711,10 @@ usb_dp_qmpphy_dp_in: endpoint { }; }; - usb_2: usb@8cf8800 { - compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; - reg = <0 0x08cf8800 0 0x400>; + usb_2: usb@8c00000 { + compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3"; + reg = <0 0x08c00000 0 0xfc100>; status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_MASTER_CLK>, @@ -3735,11 +3731,13 @@ usb_2: usb@8cf8800 { <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; @@ -3753,24 +3751,19 @@ usb_2: usb@8cf8800 { <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; interconnect-names = "usb-ddr", "apps-usb"; - usb_2_dwc3: usb@8c00000 { - compatible = "snps,dwc3"; - reg = <0 0x08c00000 0 0xe000>; - interrupts = ; - iommus = <&apps_smmu 0xa0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - phys = <&usb_2_hsphy>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - usb-role-switch; + iommus = <&apps_smmu 0xa0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + usb-role-switch; - port { - usb2_role_switch: endpoint { - remote-endpoint = <&eud_ep>; - }; + port { + usb2_role_switch: endpoint { + remote-endpoint = <&eud_ep>; }; }; }; @@ -4252,14 +4245,10 @@ compute-cb@14 { }; }; - usb_1: usb@a6f8800 { - compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; + usb_1: usb@a600000 { + compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a600000 0 0xfc100>; status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - dma-ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -4276,12 +4265,14 @@ usb_1: usb@a6f8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", @@ -4298,37 +4289,32 @@ usb_1: usb@a6f8800 { wakeup-source; - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xe000>; - interrupts = ; - iommus = <&apps_smmu 0xe0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,parkmode-disable-ss-quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", "usb3-phy"; - maximum-speed = "super-speed"; + iommus = <&apps_smmu 0xe0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,parkmode-disable-ss-quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", "usb3-phy"; + maximum-speed = "super-speed"; - ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@0 { - reg = <0>; + port@0 { + reg = <0>; - usb_1_dwc3_hs: endpoint { - }; + usb_1_dwc3_hs: endpoint { }; + }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - usb_1_dwc3_ss: endpoint { - remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; - }; + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts index befbb40228b5..f16b47b6a74c 100644 --- a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts +++ b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts @@ -1425,16 +1425,14 @@ &ufs_mem_phy { &usb_1 { /* USB 2.0 only */ qcom,select-utmi-as-pipe-clk; - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "otg"; usb-role-switch; maximum-speed = "high-speed"; /* Remove USB3 phy */ phys = <&usb_1_hsphy>; phy-names = "usb2-phy"; + + status = "okay"; }; &usb_1_dwc3_hs { From d41fb878adf64ef5dc4b4c25419e875483f62fe2 Mon Sep 17 00:00:00 2001 From: Ziyue Zhang Date: Fri, 25 Jul 2025 18:22:30 +0800 Subject: [PATCH 147/931] arm64: dts: qcom: sa8775p: remove aux clock from pcie phy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The gcc_aux_clk is used by the PCIe Root Complex (RC) and is not required by the PHY. The correct clock for the PHY is gcc_phy_aux_clk, which this patch uses to replace the incorrect reference. The distinction between AUX_CLK and PHY_AUX_CLK is important: AUX_CLK is typically used by the controller, while PHY_AUX_CLK is required by certain PHYs—particularly Gen4 QMP PHYs—for internal operations such as clock gating and power management. Some non-Gen4 Qualcomm PHYs also use PHY_AUX_CLK, but they do not require AUX_CLK. This change ensures proper clock configuration and avoids unnecessary dependencies. Signed-off-by: Ziyue Zhang Reviewed-by: Johan Hovold Fixes: 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes") Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250725102231.3608298-3-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 322abd0294be..4ccaddb7794c 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -7719,16 +7719,18 @@ pcie0_phy: phy@1c04000 { compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; reg = <0x0 0x1c04000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, - <&gcc GCC_PCIE_0_PHY_AUX_CLK>; - - clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", - "pipediv2", "phy_aux"; + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; @@ -7885,16 +7887,18 @@ pcie1_phy: phy@1c14000 { compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; reg = <0x0 0x1c14000 0x0 0x4000>; - clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, - <&gcc GCC_PCIE_1_PHY_AUX_CLK>; - - clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", - "pipediv2", "phy_aux"; + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; From f0370265b1d7fc169956927aa62c3abc375743b5 Mon Sep 17 00:00:00 2001 From: Ziyue Zhang Date: Fri, 25 Jul 2025 18:22:31 +0800 Subject: [PATCH 148/931] arm64: dts: qcom: sa8775p: add link_down reset for pcie SA8775p supports 'link_down' reset on hardware, so add it for both pcie0 and pcie1, which can provide a better user experience. Reviewed-by: Konrad Dybcio Reviewed-by: Johan Hovold Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/r/20250725102231.3608298-4-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 4ccaddb7794c..9b7fa4c932e3 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -7647,8 +7647,11 @@ pcie0: pcie@1c00000 { iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, <0x100 &pcie_smmu 0x0001 0x1>; - resets = <&gcc GCC_PCIE_0_BCR>; - reset-names = "pci"; + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + power-domains = <&gcc PCIE_0_GDSC>; phys = <&pcie0_phy>; @@ -7815,8 +7818,11 @@ pcie1: pcie@1c10000 { iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, <0x100 &pcie_smmu 0x0081 0x1>; - resets = <&gcc GCC_PCIE_1_BCR>; - reset-names = "pci"; + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + power-domains = <&gcc PCIE_1_GDSC>; phys = <&pcie1_phy>; From 45cca0f3c8208d210751ec91edf778a18336df88 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 24 Jul 2025 15:23:39 +0300 Subject: [PATCH 149/931] arm64: dts: qcom: sc8180x: add empty mdss_edp_out endpoint Follow the example of other DP controllers and also eDP controller on SC7280 and move mdss_edp_out endpoint declaration to the SoC DTSI. This slightly reduces the boilerplate in the platform DT files and also reduces the difference between DP and eDP controllers. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250724-move-edp-endpoints-v1-1-6ca569812838@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 11 +++-------- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 11 +++-------- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 7 +++++++ 3 files changed, 13 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 21c2d25a2945..93dfb82c36da 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -457,15 +457,10 @@ auo_b140han06_in: endpoint { }; }; }; +}; - ports { - port@1 { - reg = <1>; - mdss_edp_out: endpoint { - remote-endpoint = <&auo_b140han06_in>; - }; - }; - }; +&mdss_edp_out { + remote-endpoint = <&auo_b140han06_in>; }; &pcie3 { diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index 7a4bd6955470..6808226b04e4 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -551,15 +551,10 @@ auo_b133han05_in: endpoint { }; }; }; +}; - ports { - port@1 { - reg = <1>; - mdss_edp_out: endpoint { - remote-endpoint = <&auo_b133han05_in>; - }; - }; - }; +&mdss_edp_out { + remote-endpoint = <&auo_b133han05_in>; }; &pcie1 { diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index f4f1d6a11960..836ac9455147 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3423,6 +3423,13 @@ edp_in: endpoint { remote-endpoint = <&dpu_intf5_out>; }; }; + + port@1 { + reg = <1>; + + mdss_edp_out: endpoint { + }; + }; }; edp_opp_table: opp-table { From caaba55bb751133433c1b0806f5ce6b88359f0f7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 24 Jul 2025 15:23:40 +0300 Subject: [PATCH 150/931] arm64: dts: qcom: sc8280xp: add empty mdss*_dp*_out endpoints Follow the example of other DP controllers and also eDP controller on SC7280 and move all mdss[01]_dp[0123]_out endpoints declaration to the SoC DTSI. This slightly reduces the boilerplate in the platform DT files and also reduces the difference between DP and eDP controllers. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250724-move-edp-endpoints-v1-2-6ca569812838@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 78 ++++++------------- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 11 +-- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 11 +-- .../dts/qcom/sc8280xp-microsoft-blackrock.dts | 13 +--- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 18 +++++ 5 files changed, 52 insertions(+), 79 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 2fd1dafe63ce..d5015ec4b23d 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -35,7 +35,7 @@ dp2-connector { port { dp2_connector_in: endpoint { - remote-endpoint = <&mdss1_dp0_phy_out>; + remote-endpoint = <&mdss1_dp0_out>; }; }; }; @@ -49,7 +49,7 @@ dp3-connector { port { dp3_connector_in: endpoint { - remote-endpoint = <&mdss1_dp1_phy_out>; + remote-endpoint = <&mdss1_dp1_out>; }; }; }; @@ -63,7 +63,7 @@ edp0-connector { port { edp0_connector_in: endpoint { - remote-endpoint = <&mdss0_dp2_phy_out>; + remote-endpoint = <&mdss0_dp2_out>; }; }; }; @@ -77,7 +77,7 @@ edp1-connector { port { edp1_connector_in: endpoint { - remote-endpoint = <&mdss0_dp3_phy_out>; + remote-endpoint = <&mdss0_dp3_out>; }; }; }; @@ -91,7 +91,7 @@ edp2-connector { port { edp2_connector_in: endpoint { - remote-endpoint = <&mdss1_dp2_phy_out>; + remote-endpoint = <&mdss1_dp2_out>; }; }; }; @@ -105,7 +105,7 @@ edp3-connector { port { edp3_connector_in: endpoint { - remote-endpoint = <&mdss1_dp3_phy_out>; + remote-endpoint = <&mdss1_dp3_out>; }; }; }; @@ -364,15 +364,10 @@ &mdss0_dp2 { data-lanes = <0 1 2 3>; status = "okay"; +}; - ports { - port@1 { - reg = <1>; - mdss0_dp2_phy_out: endpoint { - remote-endpoint = <&edp0_connector_in>; - }; - }; - }; +&mdss0_dp2_out { + remote-endpoint = <&edp0_connector_in>; }; &mdss0_dp2_phy { @@ -386,15 +381,10 @@ &mdss0_dp3 { data-lanes = <0 1 2 3>; status = "okay"; +}; - ports { - port@1 { - reg = <1>; - mdss0_dp3_phy_out: endpoint { - remote-endpoint = <&edp1_connector_in>; - }; - }; - }; +&mdss0_dp3_out { + remote-endpoint = <&edp1_connector_in>; }; &mdss0_dp3_phy { @@ -412,15 +402,10 @@ &mdss1_dp0 { data-lanes = <0 1 2 3>; status = "okay"; +}; - ports { - port@1 { - reg = <1>; - mdss1_dp0_phy_out: endpoint { - remote-endpoint = <&dp2_connector_in>; - }; - }; - }; +&mdss1_dp0_out { + remote-endpoint = <&dp2_connector_in>; }; &mdss1_dp0_phy { @@ -434,15 +419,10 @@ &mdss1_dp1 { data-lanes = <0 1 2 3>; status = "okay"; +}; - ports { - port@1 { - reg = <1>; - mdss1_dp1_phy_out: endpoint { - remote-endpoint = <&dp3_connector_in>; - }; - }; - }; +&mdss1_dp1_out { + remote-endpoint = <&dp3_connector_in>; }; &mdss1_dp1_phy { @@ -456,15 +436,10 @@ &mdss1_dp2 { data-lanes = <0 1 2 3>; status = "okay"; +}; - ports { - port@1 { - reg = <1>; - mdss1_dp2_phy_out: endpoint { - remote-endpoint = <&edp2_connector_in>; - }; - }; - }; +&mdss1_dp2_out { + remote-endpoint = <&edp2_connector_in>; }; &mdss1_dp2_phy { @@ -478,15 +453,10 @@ &mdss1_dp3 { data-lanes = <0 1 2 3>; status = "okay"; +}; - ports { - port@1 { - reg = <1>; - mdss1_dp3_phy_out: endpoint { - remote-endpoint = <&edp3_connector_in>; - }; - }; - }; +&mdss1_dp3_out { + remote-endpoint = <&edp3_connector_in>; }; &mdss1_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 8e2c02497c05..bcbd668f562f 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -548,15 +548,10 @@ edp_panel_in: endpoint { }; }; }; +}; - ports { - port@1 { - reg = <1>; - mdss0_dp3_out: endpoint { - remote-endpoint = <&edp_panel_in>; - }; - }; - }; +&mdss0_dp3_out { + remote-endpoint = <&edp_panel_in>; }; &mdss0_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index cefecb7a23cf..0b479e98ba38 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -761,15 +761,10 @@ edp_panel_in: endpoint { }; }; }; +}; - ports { - port@1 { - reg = <1>; - mdss0_dp3_out: endpoint { - remote-endpoint = <&edp_panel_in>; - }; - }; - }; +&mdss0_dp3_out { + remote-endpoint = <&edp_panel_in>; }; &mdss0_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index 812251324002..29efbef5ef69 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -63,7 +63,7 @@ dp3_connector: connector { port { dp1_connector_in: endpoint { - remote-endpoint = <&mdss0_dp2_phy_out>; + remote-endpoint = <&mdss0_dp2_out>; }; }; }; @@ -602,15 +602,10 @@ &mdss0_dp2 { data-lanes = <0 1 2 3>; status = "okay"; +}; - ports { - port@1 { - reg = <1>; - mdss0_dp2_phy_out: endpoint { - remote-endpoint = <&dp1_connector_in>; - }; - }; - }; +&mdss0_dp2_out { + remote-endpoint = <&dp1_connector_in>; }; &mdss0_dp2_phy { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 87555a119d94..421693208af0 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4526,6 +4526,9 @@ mdss0_dp2_in: endpoint { port@1 { reg = <1>; + + mdss0_dp2_out: endpoint { + }; }; }; @@ -4598,6 +4601,9 @@ mdss0_dp3_in: endpoint { port@1 { reg = <1>; + + mdss0_dp3_out: endpoint { + }; }; }; @@ -5701,6 +5707,9 @@ mdss1_dp0_in: endpoint { port@1 { reg = <1>; + + mdss1_dp0_out: endpoint { + }; }; }; @@ -5773,6 +5782,9 @@ mdss1_dp1_in: endpoint { port@1 { reg = <1>; + + mdss1_dp1_out: endpoint { + }; }; }; @@ -5845,6 +5857,9 @@ mdss1_dp2_in: endpoint { port@1 { reg = <1>; + + mdss1_dp2_out: endpoint { + }; }; }; @@ -5917,6 +5932,9 @@ mdss1_dp3_in: endpoint { port@1 { reg = <1>; + + mdss1_dp3_out: endpoint { + }; }; }; From 91329efd132bf58aaecb33c07a4e566d9e95ff71 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 24 Jul 2025 15:23:41 +0300 Subject: [PATCH 151/931] arm64: dts: qcom: x1e80100: add empty mdss_dp3_out endpoint Follow the example of other DP controllers and also eDP controller on SC7280 and move mdss_dp3_out endpoint declaration to the SoC DTSI. This slightly reduces the boilerplate in the platform DT files and also reduces the difference between DP and eDP controllers. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250724-move-edp-endpoints-v1-3-6ca569812838@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi | 16 +++++----------- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 15 +++++---------- .../dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 16 +++++----------- .../boot/dts/qcom/x1e80100-asus-vivobook-s15.dts | 16 +++++----------- .../boot/dts/qcom/x1e80100-dell-xps13-9345.dts | 16 +++++----------- .../boot/dts/qcom/x1e80100-hp-omnibook-x14.dts | 16 +++++----------- .../dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 16 +++++----------- .../dts/qcom/x1e80100-microsoft-romulus.dtsi | 16 +++++----------- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 15 +++++---------- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 3 +++ 10 files changed, 48 insertions(+), 97 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi index c771fd1d8029..16d045cf64c0 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi @@ -1019,19 +1019,13 @@ edp_panel_in: endpoint { }; }; }; +}; - ports { - port@1 { - reg = <1>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 35d26d14b6bd..e3d2fc342bd1 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1192,18 +1192,13 @@ edp_panel_in: endpoint { }; }; }; +}; - ports { - port@1 { - reg = <1>; - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 2308d5a0e3af..4cf61c2a34e3 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -1024,19 +1024,13 @@ edp_panel_in: endpoint { }; }; }; +}; - ports { - port@1 { - reg = <1>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index 71b2cc6c392f..62eba17cdc87 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -611,19 +611,13 @@ edp_panel_in: endpoint { }; }; }; +}; - ports { - port@1 { - reg = <1>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index fd00d1bf12e1..6b27067f0be6 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -918,19 +918,13 @@ edp_panel_in: endpoint { }; }; }; +}; - ports { - port@1 { - reg = <1>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts index 8d2a9b7f4730..f9ce2a63767c 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts @@ -1060,19 +1060,13 @@ edp_panel_in: endpoint { }; }; }; +}; - ports { - port@1 { - reg = <1>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index d02f8d4f7baf..71becfc5e6f6 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -1104,19 +1104,13 @@ edp_panel_in: endpoint { }; }; }; +}; - ports { - port@1 { - reg = <1>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 0fd8516580b2..27dd5e4e9939 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -981,19 +981,13 @@ edp_panel_in: endpoint { }; }; }; +}; - ports { - port@1 { - reg = <1>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 71c44e37a44b..9369b76c668b 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -929,18 +929,13 @@ edp_panel_in: endpoint { }; }; }; +}; - ports { - port@1 { - reg = <1>; - mdss_dp3_out: endpoint { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - remote-endpoint = <&edp_panel_in>; - }; - }; - }; + remote-endpoint = <&edp_panel_in>; }; &mdss_dp3_phy { diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index c9fea040223b..4dba9f2b64f7 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5608,6 +5608,9 @@ mdss_dp3_in: endpoint { port@1 { reg = <1>; + + mdss_dp3_out: endpoint { + }; }; }; From c361adf09dfc77c62da4c0d548a8c8d50eb9c71d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 24 Jul 2025 15:23:42 +0300 Subject: [PATCH 152/931] arm64: dts: qcom: move data-lanes to the DP-out endpoint Support for the data-lanes declaration in the DP node is deprecated. Move them to the corresponding endpoint as recommended by the current DP bindings. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250724-move-edp-endpoints-v1-4-6ca569812838@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 18 ++++++------------ .../boot/dts/qcom/sc7180-acer-aspire1.dts | 3 +-- .../boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 3 +-- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 3 +-- 4 files changed, 9 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index d5015ec4b23d..64e59299672c 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -361,12 +361,11 @@ &mdss0 { }; &mdss0_dp2 { - data-lanes = <0 1 2 3>; - status = "okay"; }; &mdss0_dp2_out { + data-lanes = <0 1 2 3>; remote-endpoint = <&edp0_connector_in>; }; @@ -378,12 +377,11 @@ &mdss0_dp2_phy { }; &mdss0_dp3 { - data-lanes = <0 1 2 3>; - status = "okay"; }; &mdss0_dp3_out { + data-lanes = <0 1 2 3>; remote-endpoint = <&edp1_connector_in>; }; @@ -399,12 +397,11 @@ &mdss1 { }; &mdss1_dp0 { - data-lanes = <0 1 2 3>; - status = "okay"; }; &mdss1_dp0_out { + data-lanes = <0 1 2 3>; remote-endpoint = <&dp2_connector_in>; }; @@ -416,12 +413,11 @@ &mdss1_dp0_phy { }; &mdss1_dp1 { - data-lanes = <0 1 2 3>; - status = "okay"; }; &mdss1_dp1_out { + data-lanes = <0 1 2 3>; remote-endpoint = <&dp3_connector_in>; }; @@ -433,12 +429,11 @@ &mdss1_dp1_phy { }; &mdss1_dp2 { - data-lanes = <0 1 2 3>; - status = "okay"; }; &mdss1_dp2_out { + data-lanes = <0 1 2 3>; remote-endpoint = <&edp2_connector_in>; }; @@ -450,12 +445,11 @@ &mdss1_dp2_phy { }; &mdss1_dp3 { - data-lanes = <0 1 2 3>; - status = "okay"; }; &mdss1_dp3_out { + data-lanes = <0 1 2 3>; remote-endpoint = <&edp3_connector_in>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts index 672ac4c3afa3..a70396f250f0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts @@ -438,8 +438,6 @@ &mdss { }; &mdss_dp { - data-lanes = <0 1>; - vdda-1p2-supply = <&vreg_l3c_1p2>; vdda-0p9-supply = <&vreg_l4a_0p8>; @@ -447,6 +445,7 @@ &mdss_dp { }; &mdss_dp_out { + data-lanes = <0 1>; remote-endpoint = <&ec_dp_in>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 93dfb82c36da..08d0784d0cbb 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -436,8 +436,6 @@ &mdss_dp1_out { }; &mdss_edp { - data-lanes = <0 1 2 3>; - pinctrl-0 = <&edp_hpd_active>; pinctrl-names = "default"; @@ -460,6 +458,7 @@ auo_b140han06_in: endpoint { }; &mdss_edp_out { + data-lanes = <0 1 2 3>; remote-endpoint = <&auo_b140han06_in>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index 6808226b04e4..93de9fe918eb 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -531,8 +531,6 @@ &mdss_dp1_out { }; &mdss_edp { - data-lanes = <0 1 2 3>; - pinctrl-names = "default"; pinctrl-0 = <&edp_hpd_active>; @@ -554,6 +552,7 @@ auo_b133han05_in: endpoint { }; &mdss_edp_out { + data-lanes = <0 1 2 3>; remote-endpoint = <&auo_b133han05_in>; }; From afde4d8ea536964b7b7fe83cc6736e28475b6135 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 24 Jul 2025 15:23:43 +0300 Subject: [PATCH 153/931] arm64: dts: qcom: sc7180-acer-aspire1: drop deprecated DP supplies DP supplies were migrated to the corresponding DP PHY. Drop them from the DP controller node. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250724-move-edp-endpoints-v1-5-6ca569812838@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts index a70396f250f0..ad342d8b7508 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts @@ -438,9 +438,6 @@ &mdss { }; &mdss_dp { - vdda-1p2-supply = <&vreg_l3c_1p2>; - vdda-0p9-supply = <&vreg_l4a_0p8>; - status = "okay"; }; From 55863887fa1c536568dba6cb10b2cefc2b0e24cc Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 1 Aug 2025 15:51:05 +0200 Subject: [PATCH 154/931] arm64: dts: qcom: sc7280: Add q6usbdai node Add a node for q6usb which handles USB audio offloading, allowing to play audio via a USB-C headset with lower power consumption and enabling some other features. We also need to set num-hc-interrupters for the dwc3 for the q6usb to be able to use its sideband interrupter. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250801-fp5-usb-audio-offload-v1-1-240fc213d3d3@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0fa8d34999a3..97bb8a42a7b6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3855,6 +3855,13 @@ q6afecc: clock-controller { compatible = "qcom,q6afe-clocks"; #clock-cells = <2>; }; + + q6usbdai: usbd { + compatible = "qcom,q6usb"; + iommus = <&apps_smmu 0x180f 0x0>; + #sound-dai-cells = <1>; + qcom,usb-audio-intr-idx = /bits/ 16 <2>; + }; }; q6asm: service@7 { @@ -4295,6 +4302,7 @@ usb_1: usb@a600000 { snps,parkmode-disable-ss-quirk; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; + num-hc-interrupters = /bits/ 16 <3>; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; maximum-speed = "super-speed"; From c183cebe69d0c02a3483d18b6953b29ff790c643 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 1 Aug 2025 15:51:06 +0200 Subject: [PATCH 155/931] arm64: dts: qcom: qcm6490-fairphone-fp5: Enable USB audio offload support Enable USB audio offloading which allows to play audio via a USB-C headset with lower power consumption and enabling some other features. This can be used like the following: $ amixer -c0 cset name='USB_RX Audio Mixer MultiMedia1' On $ aplay --device=plughw:0,0 test.wav Compared to regular playback to the USB sound card no xhci-hcd interrupts appear during playback, instead the ADSP will be handling the USB transfers. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250801-fp5-usb-audio-offload-v1-2-240fc213d3d3@fairphone.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcm6490-fairphone-fp5.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index f17ac3dc9b06..519e458e1a89 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -1176,6 +1176,22 @@ platform { sound-dai = <&q6routing>; }; }; + + usb-dai-link { + link-name = "USB Playback"; + + codec { + sound-dai = <&q6usbdai USB_RX>; + }; + + cpu { + sound-dai = <&q6afedai USB_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; }; &spi13 { From ce4d078469792d865b05f1687bca2eb24b77d84a Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 1 Aug 2025 15:40:59 +0200 Subject: [PATCH 156/931] arm64: dts: qcom: sm6350: Add rpmh-stats node The qcom_stats driver allows querying sleep stats from various remoteprocs. Add a node to enable it. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250801-sm6350-rpmh-stats-v1-1-f1fb649d1095@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 2d891a5640de..2493b9611dcb 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2487,6 +2487,11 @@ aoss_qmp: power-management@c300000 { #clock-cells = <0>; }; + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0x0 0x0c3f0000 0x0 0x400>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0 0x0c440000 0x0 0x1100>, From 1335a89bbc8ac5b0310db9457018c261816e61cc Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 7 Jul 2025 16:35:30 +0100 Subject: [PATCH 157/931] arm64: dts: renesas: r9a09g077: Add I2C controller nodes The Renesas RZ/T2H ("R9A09G077") SoC includes three I2C (RIIC) channels. Add device tree nodes for all three I2C controllers to the RZ/T2H SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250707153533.287832-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 42c3b86196d6..0583a26ecbc4 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -90,6 +90,51 @@ sci0: serial@80005000 { status = "disabled"; }; + i2c0: i2c@80088000 { + compatible = "renesas,riic-r9a09g077"; + reg = <0 0x80088000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eei", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 100>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@80088400 { + compatible = "renesas,riic-r9a09g077"; + reg = <0 0x80088400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eei", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 101>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@81008000 { + compatible = "renesas,riic-r9a09g077"; + reg = <0 0x81008000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eei", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + cpg: clock-controller@80280000 { compatible = "renesas,r9a09g077-cpg-mssr"; reg = <0 0x80280000 0 0x1000>, From 1977f7d0d180621c11af26e96be29cc4e772dcc4 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 7 Jul 2025 16:35:31 +0100 Subject: [PATCH 158/931] arm64: dts: renesas: r9a09g087: Add I2C controller nodes The Renesas RZ/N2H ("R9A09G087") SoC includes three I2C (RIIC) channels. Add device tree nodes for all three I2C controllers to the RZ/N2H SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250707153533.287832-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index e57a91adcb68..7452aca6b05b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -90,6 +90,51 @@ sci0: serial@80005000 { status = "disabled"; }; + i2c0: i2c@80088000 { + compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; + reg = <0 0x80088000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eei", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 100>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@80088400 { + compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; + reg = <0 0x80088400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eei", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 101>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@81008000 { + compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; + reg = <0 0x81008000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eei", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + cpg: clock-controller@80280000 { compatible = "renesas,r9a09g087-cpg-mssr"; reg = <0 0x80280000 0 0x1000>, From c5dbcd94fc78d67b6c0a7e55615ae2019300956f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 7 Jul 2025 16:35:32 +0100 Subject: [PATCH 159/931] arm64: dts: renesas: r9a09g077: Add SDHI nodes Add the SDHI0-SDHI1 nodes to the RZ/T2H ("R9A09G077") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250707153533.287832-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 0583a26ecbc4..b16fd9259d8d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 { interrupt-controller; interrupts = ; }; + + sdhi0: mmc@92080000 { + compatible = "renesas,sdhi-r9a09g077", + "renesas,sdhi-r9a09g057"; + reg = <0x0 0x92080000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 1212>, + <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>; + clock-names = "aclk", "clkh"; + power-domains = <&cpg>; + status = "disabled"; + + sdhi0_vqmmc: vqmmc-regulator { + regulator-name = "SDHI0-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + }; + + sdhi1: mmc@92090000 { + compatible = "renesas,sdhi-r9a09g077", + "renesas,sdhi-r9a09g057"; + reg = <0x0 0x92090000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 1213>, + <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>; + clock-names = "aclk", "clkh"; + power-domains = <&cpg>; + status = "disabled"; + + sdhi1_vqmmc: vqmmc-regulator { + regulator-name = "SDHI1-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + }; }; timer { From deab74707654cbfcd4b1e984d8f64479145b6895 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 7 Jul 2025 16:35:33 +0100 Subject: [PATCH 160/931] arm64: dts: renesas: r9a09g087: Add SDHI nodes Add the SDHI0-SDHI1 nodes to the RZ/N2H ("R9A09G087") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250707153533.287832-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index 7452aca6b05b..4da21199d22e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -155,6 +155,46 @@ gic: interrupt-controller@83000000 { interrupt-controller; interrupts = ; }; + + sdhi0: mmc@92080000 { + compatible = "renesas,sdhi-r9a09g087", + "renesas,sdhi-r9a09g057"; + reg = <0x0 0x92080000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 1212>, + <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>; + clock-names = "aclk", "clkh"; + power-domains = <&cpg>; + status = "disabled"; + + sdhi0_vqmmc: vqmmc-regulator { + regulator-name = "SDHI0-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + }; + + sdhi1: mmc@92090000 { + compatible = "renesas,sdhi-r9a09g087", + "renesas,sdhi-r9a09g057"; + reg = <0x0 0x92090000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 1213>, + <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>; + clock-names = "aclk", "clkh"; + power-domains = <&cpg>; + status = "disabled"; + + sdhi1_vqmmc: vqmmc-regulator { + regulator-name = "SDHI1-VQMMC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + status = "disabled"; + }; + }; }; timer { From 0a0e0852f3f339afdc75ff62750eae3857437231 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 31 Jul 2025 10:36:59 +0200 Subject: [PATCH 161/931] arm64: dts: renesas: r9a09g057h48-kakip: Fix misplaced article Move the article "the" before the full name of the board. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/280176885acf46d117a0ab9a02c314e2b5cf250f.1753950938.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts index d2586d278769..f6f2cb7d2d25 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for Yuridenki-Shokai the Kakip board + * Device Tree Source for the Yuridenki-Shokai Kakip board * * Copyright (C) 2024 Nobuhiro Iwamatsu */ From c44c51bc3566412075c66e0064e17c0c9cb5a638 Mon Sep 17 00:00:00 2001 From: Tommaso Merciai Date: Fri, 1 Aug 2025 10:48:23 +0200 Subject: [PATCH 162/931] arm64: dts: renesas: r9a09g047: Add DMAC nodes Add nodes for the DMAC IPs found on the Renesas RZ/G3E SoC. Signed-off-by: Tommaso Merciai Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250801084825.471011-4-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 170 +++++++++++++++++++++ 1 file changed, 170 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index e4fac7e0d764..eeccd1345f71 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -301,6 +301,176 @@ xspi: spi@11030000 { status = "disabled"; }; + dmac0: dma-controller@11400000 { + compatible = "renesas,r9a09g047-dmac", + "renesas,r9a09g057-dmac"; + reg = <0 0x11400000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x0>; + power-domains = <&cpg>; + resets = <&cpg 0x31>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 4>; + }; + + dmac1: dma-controller@14830000 { + compatible = "renesas,r9a09g047-dmac", + "renesas,r9a09g057-dmac"; + reg = <0 0x14830000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x1>; + power-domains = <&cpg>; + resets = <&cpg 0x32>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 0>; + }; + + dmac2: dma-controller@14840000 { + compatible = "renesas,r9a09g047-dmac", + "renesas,r9a09g057-dmac"; + reg = <0 0x14840000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x2>; + power-domains = <&cpg>; + resets = <&cpg 0x33>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 1>; + }; + + dmac3: dma-controller@12000000 { + compatible = "renesas,r9a09g047-dmac", + "renesas,r9a09g057-dmac"; + reg = <0 0x12000000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x3>; + power-domains = <&cpg>; + resets = <&cpg 0x34>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 2>; + }; + + dmac4: dma-controller@12010000 { + compatible = "renesas,r9a09g047-dmac", + "renesas,r9a09g057-dmac"; + reg = <0 0x12010000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x4>; + power-domains = <&cpg>; + resets = <&cpg 0x35>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 3>; + }; + scif0: serial@11c01400 { compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; reg = <0 0x11c01400 0 0x400>; From ae014fbc99c7f986ee785233e7a5336834e39af4 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 1 Aug 2025 13:19:53 +0100 Subject: [PATCH 163/931] arm64: dts: renesas: rzg2lc-smarc: Disable CAN-FD channel0 On RZ/G2LC SMARC EVK, CAN-FD channel0 is not populated, and currently we are deleting a wrong and nonexistent node. Fixing the wrong node would invoke a dtb warning message, as channel0 is a required property. Disable CAN-FD channel0 instead of deleting the node. Fixes: 46da632734a5 ("arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1") Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250801121959.267424-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 345b779e4f60..f3d7eff0d2f2 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -48,7 +48,10 @@ sound_card { #if (SW_SCIF_CAN || SW_RSPI_CAN) &canfd { pinctrl-0 = <&can1_pins>; - /delete-node/ channel@0; + + channel0 { + status = "disabled"; + }; }; #else &canfd { From 95319aaa3ffc680cab9abe6e7197299561e890de Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 6 Aug 2025 17:00:36 +0200 Subject: [PATCH 164/931] arm64: dts: renesas: sparrow-hawk: Describe generic SPI NOR support Retronix R-Car V4H Sparrow Hawk EVTA1 is populated with Spansion S25FS512S, EVTB1 is populated with Winbond W77Q51NW. Describe the SPI NOR using the generic "jedec,spi-nor" compatible, because both FLASHes can be auto-detected based on their built-in IDs. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250806150048.9364-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts index 9ba23129e65e..1f44005e1a11 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts @@ -756,7 +756,11 @@ &rpc { status = "okay"; flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; + /* + * EVTA1 is populated with Spansion S25FS512S + * EVTB1 is populated with Winbond W77Q51NW + */ + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; spi-rx-bus-width = <4>; From 256feb5be482315a91c1bd1a1808276f57ef76dd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 6 Aug 2025 17:04:27 +0200 Subject: [PATCH 165/931] ARM: dts: renesas: r7s72100: Add boot phase tags bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to describe various node usage during boot phases with DT. Add bootph-all for all nodes that are used in the bootloader on Renesas RZ/A1 SoCs. All SoCs require BSC bus, PFC pin control, and OSTM0 timer access during all stages of the boot process, those are marked using bootph-all property, and so is the SoC bus node which contains the PFC and OSTM IPs. Each board console UART is also marked as bootph-all to make it available in all stages of the boot process. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250806150448.9669-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r7s72100-genmai.dts | 4 +++- arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts | 4 +++- arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts | 3 +++ arch/arm/boot/dts/renesas/r7s72100.dtsi | 3 +++ 4 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts index c81840dfb7da..3c3756509714 100644 --- a/arch/arm/boot/dts/renesas/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/renesas/r7s72100-genmai.dts @@ -203,6 +203,7 @@ &mtu2 { }; &ostm0 { + bootph-all; status = "okay"; }; @@ -258,6 +259,7 @@ mmcif_pins: mmcif { }; scif2_pins: serial2 { + bootph-all; /* P3_0 as TxD2; P3_2 as RxD2 */ pinmux = , ; }; @@ -286,7 +288,7 @@ &rtc { &scif2 { pinctrl-names = "default"; pinctrl-0 = <&scif2_pins>; - + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts b/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts index 9d29861f23f1..23ddec217685 100644 --- a/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts +++ b/arch/arm/boot/dts/renesas/r7s72100-gr-peach.dts @@ -59,6 +59,7 @@ led1 { &pinctrl { scif2_pins: serial2 { + bootph-all; /* P6_2 as RxD2; P6_3 as TxD2 */ pinmux = , ; }; @@ -99,6 +100,7 @@ &mtu2 { }; &ostm0 { + bootph-all; status = "okay"; }; @@ -109,7 +111,7 @@ &ostm1 { &scif2 { pinctrl-names = "default"; pinctrl-0 = <&scif2_pins>; - + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts index 25c6d0c78828..91178fb9e721 100644 --- a/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/renesas/r7s72100-rskrza1.dts @@ -199,6 +199,7 @@ keyboard_pins: keyboard { /* Serial Console */ scif2_pins: serial2 { + bootph-all; pinmux = , /* TxD2 */ ; /* RxD2 */ }; @@ -264,6 +265,7 @@ &sdhi1 { }; &ostm0 { + bootph-all; status = "okay"; }; @@ -278,6 +280,7 @@ &rtc { &scif2 { pinctrl-names = "default"; pinctrl-0 = <&scif2_pins>; + bootph-all; status = "okay"; }; diff --git a/arch/arm/boot/dts/renesas/r7s72100.dtsi b/arch/arm/boot/dts/renesas/r7s72100.dtsi index 1a866dbaf5e9..a1e4e9ac8f62 100644 --- a/arch/arm/boot/dts/renesas/r7s72100.dtsi +++ b/arch/arm/boot/dts/renesas/r7s72100.dtsi @@ -41,6 +41,7 @@ bsc: bus { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x18000000>; + bootph-all; }; cpus { @@ -107,6 +108,7 @@ soc { #address-cells = <1>; #size-cells = <1>; ranges; + bootph-all; L2: cache-controller@3ffff000 { compatible = "arm,pl310-cache"; @@ -557,6 +559,7 @@ R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11 pinctrl: pinctrl@fcfe3000 { compatible = "renesas,r7s72100-ports"; + bootph-all; reg = <0xfcfe3000 0x4230>; From f8328b7549e1faff45e32ab2ecc2573b90604e76 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 11 Aug 2025 22:16:29 -0500 Subject: [PATCH 166/931] arm64: dts: qcom: sc7280: Describe the first PCIe controller and PHY Only one PCIe controller has been described so far, but the SC7280 has two controllers/phys. Describe the second one as well. Signed-off-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250811-sc7280-pcie0-v1-1-6093e5b208f9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 134 +++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 97bb8a42a7b6..e38c2fbbecd5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2200,6 +2200,135 @@ wifi: wifi@17a10040 { qcom,smem-state-names = "wlan-smp2p-out"; }; + pcie0: pcie@1c00000 { + compatible = "qcom,pcie-sc7280"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie0_phy>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc GCC_PCIE_0_GDSC>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_clkreq_n>; + dma-coherent; + + status = "disabled"; + + pcie0_port: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; + reg = <0 0x01c06000 0 0x1000>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + }; + pcie1: pcie@1c08000 { compatible = "qcom,pcie-sc7280"; reg = <0 0x01c08000 0 0x3000>, @@ -5279,6 +5408,11 @@ mi2s1_ws: mi2s1-ws-state { function = "mi2s1_ws"; }; + pcie0_clkreq_n: pcie0-clkreq-n-state { + pins = "gpio88"; + function = "pcie0_clkreqn"; + }; + pcie1_clkreq_n: pcie1-clkreq-n-state { pins = "gpio79"; function = "pcie1_clkreqn"; From 039a504cda2cb69354387aa453391ec89a9e0e49 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 11 Aug 2025 22:11:33 -0500 Subject: [PATCH 167/931] dt-bindings: clock: dispcc-sc7280: Add display resets Like other platforms the sc7280 display clock controller provides a couple of resets, add the defines to allow referring to them. Signed-off-by: Bjorn Andersson Reviewed-by: Taniya Das Link: https://lore.kernel.org/r/20250811-sc7280-mdss-reset-v1-1-83ceff1d48de@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,dispcc-sc7280.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7280.h b/include/dt-bindings/clock/qcom,dispcc-sc7280.h index a4a692c20acf..9f113f346be8 100644 --- a/include/dt-bindings/clock/qcom,dispcc-sc7280.h +++ b/include/dt-bindings/clock/qcom,dispcc-sc7280.h @@ -52,4 +52,8 @@ /* DISP_CC power domains */ #define DISP_CC_MDSS_CORE_GDSC 0 +/* DISPCC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_RSCC_BCR 1 + #endif From 9cdb77e3103a449ee54f397d29321a5d4157bcb7 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 11 Aug 2025 22:11:35 -0500 Subject: [PATCH 168/931] arm64: dts: qcom: sc7280: Add MDSS_CORE reset to mdss Like on other platforms, if the OS does not support recovering the state left by the bootloader it needs access to MDSS_CORE, so that it can clear the MDSS configuration. Until now it seems no version of the bootloaders have done so, but e.g. the Particle Tachyon ships with a bootloader that does leave the display in a state that results in a series of iommu faults. So let's provide the reset, to allow the OS to clear that state. Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250811-sc7280-mdss-reset-v1-3-83ceff1d48de@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e38c2fbbecd5..1a7679d38a42 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4847,6 +4847,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, iommus = <&apps_smmu 0x900 0x402>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + #address-cells = <2>; #size-cells = <2>; ranges; From 393d69df0fda903dc41e071fef76baf485510672 Mon Sep 17 00:00:00 2001 From: Pushpendra Singh Date: Wed, 2 Jul 2025 05:31:20 +0530 Subject: [PATCH 169/931] arm64: dts: qcom: sc7280: Add support for two additional DDR frequencies The SC7280 SoC now supports two additional frequencies. This patch add those frequencies to the BWMON OPP table and updates the frequency mapping table accordingly. These changes do not impact existing platforms, as the updated mapping only affects the highest OPP. On any given platform, this will continue to vote for the maximum available OPP. Signed-off-by: Pushpendra Singh Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250702000120.2902158-1-quic_pussin@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 1a7679d38a42..0dd6a5c91d10 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -620,12 +620,12 @@ cpu4_opp_2208mhz: opp-2208000000 { cpu4_opp_2400mhz: opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; - opp-peak-kBps = <8532000 48537600>; + opp-peak-kBps = <12787200 48537600>; }; cpu4_opp_2611mhz: opp-2611200000 { opp-hz = /bits/ 64 <2611200000>; - opp-peak-kBps = <8532000 48537600>; + opp-peak-kBps = <12787200 48537600>; }; }; @@ -685,22 +685,22 @@ cpu7_opp_2381mhz: opp-2380800000 { cpu7_opp_2400mhz: opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; - opp-peak-kBps = <8532000 48537600>; + opp-peak-kBps = <12787200 48537600>; }; cpu7_opp_2515mhz: opp-2515200000 { opp-hz = /bits/ 64 <2515200000>; - opp-peak-kBps = <8532000 48537600>; + opp-peak-kBps = <12787200 48537600>; }; cpu7_opp_2707mhz: opp-2707200000 { opp-hz = /bits/ 64 <2707200000>; - opp-peak-kBps = <8532000 48537600>; + opp-peak-kBps = <12787200 48537600>; }; cpu7_opp_3014mhz: opp-3014400000 { opp-hz = /bits/ 64 <3014400000>; - opp-peak-kBps = <8532000 48537600>; + opp-peak-kBps = <12787200 48537600>; }; }; @@ -4142,6 +4142,12 @@ opp-6 { opp-7 { opp-peak-kBps = <8532000>; }; + opp-8 { + opp-peak-kBps = <10944000>; + }; + opp-9 { + opp-peak-kBps = <12787200>; + }; }; }; From d56ddcee0101a4b948be0d388e91f5f38f14d448 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 12 Aug 2025 16:02:41 +0530 Subject: [PATCH 170/931] arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the first SE, which supports a 4-wire UART configuration suitable for applications such as HS-UART. Note that the required initialization for this SE is not handled by the bootloader. Therefore, add the SE node in the device tree but keep it reserved. Enable it once Linux gains support for configuring the SE, allowing to use in relevant RDPs. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250812-ipq5424_hsuart-v4-1-f1faa7704ea9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 18 ++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq5424.dtsi | 9 +++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index 117f1785e8b8..738618551203 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -224,6 +224,13 @@ data-pins { }; }; + uart0_pins: uart0-default-state { + pins = "gpio10", "gpio11", "gpio12", "gpio13"; + function = "uart0"; + drive-strength = <8>; + bias-pull-down; + }; + pcie2_default_state: pcie2-default-state { pins = "gpio31"; function = "gpio"; @@ -239,6 +246,17 @@ pcie3_default_state: pcie3-default-state { }; }; +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + /* + * The required initialization for this SE is not handled by the + * bootloader. Therefore, keep the device in "reserved" state until + * linux gains support for configuring the SE. + */ + status = "reserved"; +}; + &uart1 { pinctrl-0 = <&uart1_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 2eea8a078595..bd891e39f33e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -442,6 +442,15 @@ qupv3: geniqup@1ac0000 { #address-cells = <2>; #size-cells = <2>; + uart0: serial@1a80000 { + compatible = "qcom,geni-uart"; + reg = <0 0x01a80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_UART0_CLK>; + clock-names = "se"; + interrupts = ; + status = "disabled"; + }; + uart1: serial@1a84000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x01a84000 0 0x4000>; From 4ea55ecb4990aa4142ddae5f713289f4101f046f Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 11 Jun 2025 18:33:18 +0200 Subject: [PATCH 171/931] arm64: dts: qcom: sdm632-fairphone-fp3: Enable display and GPU Add the description for the display panel found on this phone. Unfortunately the LCDB module on PMI632 isn't yet supported upstream so we need to use a dummy regulator-fixed in the meantime. And with this done we can also enable the GPU and set the zap shader firmware path. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20250611-fp3-display-v4-4-ef67701e7687@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 2 +- .../boot/dts/qcom/sdm632-fairphone-fp3.dts | 62 +++++++++++++++++++ 2 files changed, 63 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 273e79fb7569..c5205d09c442 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -1147,7 +1147,7 @@ &bimc SLV_EBI RPM_ALWAYS_TAG>, status = "disabled"; - zap-shader { + gpu_zap_shader: zap-shader { memory-region = <&zap_shader_region>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 31ed26c31e6e..55a45b528bd3 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -36,6 +36,14 @@ key-volume-up { }; }; + /* Dummy regulator until PMI632 has LCDB VSP/VSN support */ + lcdb_dummy: regulator-lcdb-dummy { + compatible = "regulator-fixed"; + regulator-name = "lcdb_dummy"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -44,6 +52,14 @@ vph_pwr: vph-pwr-regulator { }; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/msm8953/fairphone/fp3/a506_zap.mbn"; +}; + &hsusb_phy { vdd-supply = <&pm8953_l3>; vdda-pll-supply = <&pm8953_l7>; @@ -87,6 +103,45 @@ &lpass { status = "okay"; }; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm8953_s3>; + status = "okay"; + + panel@0 { + compatible = "djn,98-03057-6598b-i"; + reg = <0>; + + reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; + + iovcc-supply = <&pm8953_l6>; + vsn-supply = <&lcdb_dummy>; + vsp-supply = <&lcdb_dummy>; + + pinctrl-0 = <&mdss_te_default>; + pinctrl-names = "default"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; +}; + +&mdss_dsi0_phy { + vcca-supply = <&pm8953_l3>; + status = "okay"; +}; + &mpss { firmware-name = "qcom/msm8953/fairphone/fp3/mba.mbn", "qcom/msm8953/fairphone/fp3/modem.mbn"; @@ -292,6 +347,13 @@ &tlmm { * 135-138: fingerprint reader (SPI) */ gpio-reserved-ranges = <0 4>, <135 4>; + + mdss_te_default: mdss-te-default-state { + pins = "gpio24"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; }; &uart_0 { From ebfe5797ac3e6e9fb56340b6b228d2747fdec912 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20Gon=C3=A7alves?= Date: Sun, 15 Jun 2025 20:44:37 +0000 Subject: [PATCH 172/931] dt-bindings: arm: qcom: document r0q board binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds compatible for the Samsung Galaxy S22 (SM-S901E) (r0q), based on the Snapdragon 8 Gen 1 SoC. Signed-off-by: Eric Gonçalves Link: https://lore.kernel.org/r/20250615204438.1130213-1-ghatto404@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index b5acb0d26346..fa929698229e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1002,6 +1002,7 @@ properties: - qcom,sm8450-qrd - sony,pdx223 - sony,pdx224 + - samsung,r0q - const: qcom,sm8450 - items: From 46952305d2b64e9a2498c53046a832b51c93e5a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20Gon=C3=A7alves?= Date: Sun, 15 Jun 2025 20:44:38 +0000 Subject: [PATCH 173/931] arm64: dts: qcom: sm8450: add initial device tree for Samsung Galaxy S22 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds new device support for the Samsung Galaxy S22 (SM-S901E) phone Working features: - simple-framebuffer - side buttons - storage - usb Signed-off-by: Eric Gonçalves Link: https://lore.kernel.org/r/20250615204438.1130213-2-ghatto404@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sm8450-samsung-r0q.dts | 364 ++++++++++++++++++ 1 file changed, 364 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts diff --git a/arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts b/arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts new file mode 100644 index 000000000000..e9e21c25444a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025, Eric Gonçalves + */ + +/dts-v1/; + +#include +#include +#include + +#include "sm8450.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pm8450.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" + +/delete-node/ &xbl_ramdump_mem; +/delete-node/ &xbl_sc_mem; +/delete-node/ &adsp_mem; +/delete-node/ &rmtfs_mem; +/delete-node/ &mte_mem; +/delete-node/ &trusted_apps_mem; +/delete-node/ &trusted_apps_ext_mem; + +/ { + chassis-type = "handset"; + model = "Samsung Galaxy S22 (SM-S901E)"; + compatible = "samsung,r0q", "qcom,sm8450"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + bootargs = "clk_ignore_unused pd_ignore_unused"; + linux,initrd-start = <0x00 0xb6915000>; + linux,initrd-end = <0x00 0xb7fff22c>; + stdout-path = "serial0:115200n8"; + + framebuffer: framebuffer@b8000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0xb8000000 0x0 0x2b00000>; + width = <1080>; + height = <2340>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-0 = <&vol_up_n>; + pinctrl-names = "default"; + + key-vol-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8350_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + }; + + memory { + ddr_device_type = <0x08>; + device_type = "memory"; + reg = <0x00 0x80000000 0x00 0x6a000000 0x00 0xf1c00000 0x00 0xe400000 0x08 0x00 0x00 0x3ab00000 0x08 0x40000000 0x01 0x40000000 0x08 0x3b100000 0x00 0x1e00000>; + }; + + reserved-memory { + xbl_ramdump_mem: memory@a6b80000 { + reg = <0x0 0xa7d00000 0x0 0x300000>; + no-map; + }; + + xbl_sc_mem: memory@a6e00000 { + reg = <0x0 0xa6e00000 0x0 0x40000>; + no-map; + }; + + adsp_mem: memory@9fd00000 { + reg = <0x0 0x84500000 0x0 0x3b00000>; + no-map; + }; + + rmtfs_mem: memory@fe200000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xfe200000 0x0 0x280000>; + reg-names = "rmtfs"; + qcom,client-id = <1>; + no-map; + + qcom,vmid = ; + }; + + splash_region@b8000000 { + reg = <0x0 0xb8000000 0x0 0x2b00000>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&tlmm { + gpio-reserved-ranges = <36 4>, <50 1>, <93 1>; + + dsi_default: dsi-default-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + dsi_suspend: dsi-suspend-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + + vdd-l1-l4-supply = <&vreg_s11b_0p95>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_bob>; + vdd-l6-l9-l10-supply = <&vreg_s12b_1p25>; + vdd-l8-supply = <&vreg_s2h_0p95>; + + vreg_s11b_0p95: smps11 { + regulator-name = "vreg_s11b_0p95"; + regulator-min-microvolt = <848000>; + regulator-max-microvolt = <1104000>; + }; + + vreg_s12b_1p25: smps12 { + regulator-name = "vreg_s12b_1p25"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1400000>; + }; + + vreg_l1b_0p91: ldo1 { + regulator-name = "vreg_l1b_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p07: ldo2 { + regulator-name = "vreg_l2b_3p07"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l5b_0p88: ldo5 { + regulator-name = "vreg_l5b_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p5: ldo7 { + regulator-name = "vreg_l7b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_bob>; + vdd-l2-l8-supply = <&vreg_bob>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_1p86: smps1 { + regulator-name = "vreg_s1c_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2024000>; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pm8450-rpmh-regulators"; + qcom,pmic-id = "h"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vdd-l2-supply = <&vreg_bob>; + vdd-l3-supply = <&vreg_bob>; + vdd-l4-supply = <&vreg_bob>; + + vreg_s2h_0p95: smps2 { + regulator-name = "vreg_s2h_0p95"; + regulator-min-microvolt = <848000>; + regulator-max-microvolt = <1104000>; + }; + }; + + regulators-3 { + compatible = "qcom,pmr735a-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + + vdd-l1-l2-supply = <&vreg_s2e_0p85>; + vdd-l3-supply = <&vreg_s1e_1p25>; + vdd-l4-supply = <&vreg_s1c_1p86>; + vdd-l5-l6-supply = <&vreg_s1c_1p86>; + vdd-l7-bob-supply = <&vreg_bob>; + + vreg_s1e_1p25: smps1 { + regulator-name = "vreg_s1e_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1296000>; + }; + + vreg_s2e_0p85: smps2 { + regulator-name = "vreg_s2e_0p85"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + }; +}; + +&pm8350_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + input-enable; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + linux,code = ; +}; + +&usb_1 { + qcom,select-utmi-as-pipe-clk; + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_hsphy { + status = "okay"; + vdda-pll-supply = <&vreg_l5b_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p07>; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b_2p5>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <1200000>; + vccq2-supply = <&vreg_l9b_1p2>; + vccq2-max-microamp = <1200000>; + vdd-hba-supply = <&vreg_l9b_1p2>; + + status = "okay"; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; From d6111177f6504b013d0424657e131ae9a36ab5e2 Mon Sep 17 00:00:00 2001 From: Mrinmay Sarkar Date: Tue, 17 Jun 2025 17:08:20 +0530 Subject: [PATCH 174/931] arm64: dts: qcom: sa8775p: Remove max link speed property for PCIe EP The maximum link speed was previously restricted to Gen3 due to the absence of Gen4 equalization support in the driver. As Gen4 equalization is already supported by the PCIe controller driver, remove the max-link-speed property. Signed-off-by: Mrinmay Sarkar Link: https://lore.kernel.org/r/20250617-update_phy-v5-2-2df83ed6a373@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 9b7fa4c932e3..64f5378c6a47 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -7711,7 +7711,6 @@ pcie0_ep: pcie-ep@1c00000 { power-domains = <&gcc PCIE_0_GDSC>; phys = <&pcie0_phy>; phy-names = "pciephy"; - max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <2>; linux,pci-domain = <0>; @@ -7882,7 +7881,6 @@ pcie1_ep: pcie-ep@1c10000 { power-domains = <&gcc PCIE_1_GDSC>; phys = <&pcie1_phy>; phy-names = "pciephy"; - max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ num-lanes = <4>; linux,pci-domain = <1>; From a8a5ea012471dd19ea9cb4d668c27ac678e84a3e Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 9 Jul 2025 12:08:58 +0200 Subject: [PATCH 175/931] arm64: dts: qcom: x1e80100: Add videocc Add the video clock controller for X1E80100, similar to sm8550.dtsi. It provides the needed clocks/power domains for the iris video codec. Reviewed-by: Bryan O'Donoghue Signed-off-by: Stephan Gerhold Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250709-x1e-videocc-v2-6-ad1acf5674b4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 4dba9f2b64f7..f293b13ecc0c 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -5182,6 +5183,20 @@ usb_1_ss1_dwc3_ss: endpoint { }; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,x1e80100-videocc"; + reg = <0 0x0aaf0000 0 0x10000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,x1e80100-mdss"; reg = <0 0x0ae00000 0 0x1000>; From 77abf70ee126d40dba9ada0a4ccb4c7743f6a3e6 Mon Sep 17 00:00:00 2001 From: Sricharan Ramabadhran Date: Mon, 11 Aug 2025 14:39:54 +0530 Subject: [PATCH 176/931] arm64: dts: qcom: ipq5424: Enable cpufreq Add the qfprom, cpu clocks, A53 PLL and cpu-opp-table required for CPU clock scaling. Signed-off-by: Sricharan Ramabadhran [ Added interconnect related entries, fix dt-bindings errors ] Reviewed-by: Konrad Dybcio Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/20250811090954.2854440-5-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 69 +++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index bd891e39f33e..bbb539dbdf5c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -52,6 +53,11 @@ cpu0: cpu@0 { reg = <0x0>; enable-method = "psci"; next-level-cache = <&l2_0>; + clocks = <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; + l2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -72,6 +78,10 @@ cpu1: cpu@100 { enable-method = "psci"; reg = <0x100>; next-level-cache = <&l2_100>; + clocks = <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; l2_100: l2-cache { compatible = "cache"; @@ -87,6 +97,10 @@ cpu2: cpu@200 { enable-method = "psci"; reg = <0x200>; next-level-cache = <&l2_200>; + clocks = <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; l2_200: l2-cache { compatible = "cache"; @@ -102,6 +116,10 @@ cpu3: cpu@300 { enable-method = "psci"; reg = <0x300>; next-level-cache = <&l2_300>; + clocks = <&apss_clk APSS_SILVER_CORE_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; l2_300: l2-cache { compatible = "cache"; @@ -119,6 +137,36 @@ scm { }; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2-kryo-cpu"; + opp-shared; + nvmem-cells = <&cpu_speed_bin>; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + opp-peak-kBps = <816000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + opp-peak-kBps = <984000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1000000>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + opp-peak-kBps = <1272000>; + }; + }; + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -388,6 +436,18 @@ system-cache-controller@800000 { interrupts = ; }; + qfprom@a6000 { + compatible = "qcom,ipq5424-qfprom", "qcom,qfprom"; + reg = <0x0 0x000a6000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_bin: cpu-speed-bin@234 { + reg = <0x234 0x1>; + bits = <0 8>; + }; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5424-tlmm"; reg = <0 0x01000000 0 0x300000>; @@ -739,6 +799,15 @@ frame@f42d000 { }; }; + apss_clk: clock-controller@fa80000 { + compatible = "qcom,ipq5424-apss-clk"; + reg = <0x0 0x0fa80000 0x0 0x20000>; + clocks = <&xo_board>, + <&gcc GPLL0>; + #clock-cells = <1>; + #interconnect-cells = <1>; + }; + pcie3: pcie@40000000 { compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; reg = <0x0 0x40000000 0x0 0xf1c>, From 3b745d0b3dc18cd1e6344c97d61b3b1872c57219 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Thu, 31 Jul 2025 18:45:32 -0500 Subject: [PATCH 177/931] arm64: dts: exynos: Add Ethernet node for E850-96 board The E850-96 board has a hard-wired LAN9514 chip which acts as a USB hub and Ethernet bridge. It's being discovered dynamically when the USB bus gets enumerated, but the corresponding Ethernet device tree node is still needed for the bootloader to pass the MAC address through. Add LAN9514 nodes as described in [1]. 'local-mac-address' property (in the 'ethernet' node) is used for MAC address handover from the bootloader to Linux. [1] Documentation/devicetree/bindings/net/microchip,lan95xx.yaml Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20250731234532.12903-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos850-e850-96.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts index 7d70a32e75b2..ab076d326a49 100644 --- a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts +++ b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts @@ -21,6 +21,7 @@ / { compatible = "winlink,e850-96", "samsung,exynos850"; aliases { + ethernet0 = ðernet; mmc0 = &mmc_0; serial0 = &serial_0; }; @@ -241,10 +242,24 @@ &usbdrd { }; &usbdrd_dwc3 { + #address-cells = <1>; + #size-cells = <0>; dr_mode = "otg"; usb-role-switch; role-switch-default-mode = "host"; + hub@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: ethernet@1 { + compatible = "usb424,ec00"; + reg = <1>; + }; + }; + port { usb1_drd_sw: endpoint { remote-endpoint = <&usb_dr_connector>; From ad211501fff48d0cda35dd187aa7e356a4fb5581 Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Thu, 10 Jul 2025 18:50:05 +0200 Subject: [PATCH 178/931] arm64: dts: exynos990: Enable watchdog timer Enable the two watchdog timer clusters (cl0, cl2) present on the Exynos990 SoC. Signed-off-by: Igor Belwon Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-1-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos990.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi index dd7f99f51a75..4446a1a54ba2 100644 --- a/arch/arm64/boot/dts/exynos/exynos990.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi @@ -211,6 +211,30 @@ timer@10040000 { ; }; + watchdog_cl0: watchdog@10050000 { + compatible = "samsung,exynos990-wdt"; + reg = <0x10050000 0x100>; + interrupts = ; + clocks = <&cmu_peris CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK>, + <&oscclk>; + clock-names = "watchdog", + "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <0>; + }; + + watchdog_cl2: watchdog@10060000 { + compatible = "samsung,exynos990-wdt"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&cmu_peris CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK>, + <&oscclk>; + clock-names = "watchdog", + "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <2>; + }; + gic: interrupt-controller@10101000 { compatible = "arm,gic-400"; reg = <0x10101000 0x1000>, From d3830b5b0db59d0b8e33083462e4c0dd021ed300 Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Thu, 10 Jul 2025 18:50:06 +0200 Subject: [PATCH 179/931] arm64: dts: exynos990: Add USB nodes Add USB controller and USB PHY controller nodes for use in the Exynos990 SoC. This SoC supports USB full-speed, high-speed and super-speed modes. Due to the inability to test PIPE3, USB super-speed is not enabled, and the USB PHY is only configured for UTMI+ operation for now. Signed-off-by: Igor Belwon Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-2-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos990.dtsi | 31 +++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi index 4446a1a54ba2..bd5e086ac46d 100644 --- a/arch/arm64/boot/dts/exynos/exynos990.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi @@ -278,6 +278,37 @@ cmu_hsi0: clock-controller@10a00000 { "dpgtc"; }; + usbdrd_phy: phy@10c00000 { + compatible = "samsung,exynos990-usbdrd-phy"; + reg = <0x10c00000 0x100>; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL>, + <&oscclk>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + status = "disabled"; + }; + + usbdrd: usb@10e00000 { + compatible = "samsung,exynos990-dwusb3", + "samsung,exynos850-dwusb3"; + ranges = <0x0 0x10e00000 0x10000>; + clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40>; + clock-names = "bus_early", "ref"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + usbdrd_dwc3: usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + phys = <&usbdrd_phy 0>; + phy-names = "usb2-phy"; + }; + }; + pinctrl_hsi1: pinctrl@13040000 { compatible = "samsung,exynos990-pinctrl"; reg = <0x13040000 0x1000>; From 707181264badf4f82c78c18348684cd06db31ce0 Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Thu, 10 Jul 2025 18:50:07 +0200 Subject: [PATCH 180/931] arm64: dts: exynos990-x1s-common: Enable USB The x1s family uses a shared USB configuration. Enable both the USB PHY as well as the DWC3 controller. Since we do not have any PMIC for USB implemented yet, use dummy regulators until we do. Signed-off-by: Igor Belwon Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-3-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos/exynos990-x1s-common.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi b/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi index 55fa8e9e05db..7b97220cccb7 100644 --- a/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi @@ -27,6 +27,12 @@ framebuffer0: framebuffer@f1000000 { }; }; + /* TODO: Remove this once PMIC is implemented */ + reg_dummy: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "dummy_reg"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -96,3 +102,13 @@ key_volup: key-volup-pins { samsung,pin-drv = ; }; }; + +&usbdrd { + status = "okay"; + vdd10-supply = <®_dummy>; + vdd33-supply = <®_dummy>; +}; + +&usbdrd_phy { + status = "okay"; +}; From 32532687a9ce2f1c5556e082f957200a81ba0ad7 Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Thu, 10 Jul 2025 18:50:08 +0200 Subject: [PATCH 181/931] arm64: dts: exynos990-c1s: Enable USB Enable both the USB PHY as well as the DWC3 controller nodes. Since we do not have any PMIC for USB implemented yet, use dummy regulators until we do. Signed-off-by: Igor Belwon Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-4-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos990-c1s.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos990-c1s.dts b/arch/arm64/boot/dts/exynos/exynos990-c1s.dts index 36a6f1377e92..9f0ad4f9673a 100644 --- a/arch/arm64/boot/dts/exynos/exynos990-c1s.dts +++ b/arch/arm64/boot/dts/exynos/exynos990-c1s.dts @@ -44,6 +44,12 @@ memory@80000000 { <0x8 0x80000000 0x1 0x7ec00000>; }; + /* TODO: Remove this once PMIC is implemented */ + reg_dummy: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "dummy_reg"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -113,3 +119,13 @@ key_volup: key-volup-pins { samsung,pin-drv = ; }; }; + +&usbdrd { + status = "okay"; + vdd10-supply = <®_dummy>; + vdd33-supply = <®_dummy>; +}; + +&usbdrd_phy { + status = "okay"; +}; From e28c1117deda5a80df14b579170c1a90fc82bf5f Mon Sep 17 00:00:00 2001 From: Igor Belwon Date: Thu, 10 Jul 2025 18:50:09 +0200 Subject: [PATCH 182/931] arm64: dts: exynos990-r8s: Enable USB Enable both the USB PHY as well as the DWC3 controller nodes. Since we do not have any PMIC for USB implemented yet, use dummy regulators until we do. Signed-off-by: Igor Belwon Link: https://lore.kernel.org/r/20250710-resends-july-exynos990-dt-v2-5-55033f73d1b0@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos990-r8s.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos990-r8s.dts b/arch/arm64/boot/dts/exynos/exynos990-r8s.dts index 6bae3c0ecc1c..55342db61979 100644 --- a/arch/arm64/boot/dts/exynos/exynos990-r8s.dts +++ b/arch/arm64/boot/dts/exynos/exynos990-r8s.dts @@ -44,6 +44,12 @@ memory@80000000 { <0x8 0x80000000 0x0 0xc0000000>; }; + /* TODO: Remove this once PMIC is implemented */ + reg_dummy: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "dummy_reg"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -113,3 +119,13 @@ key_volup: key-volup-pins { samsung,pin-drv = ; }; }; + +&usbdrd { + status = "okay"; + vdd10-supply = <®_dummy>; + vdd33-supply = <®_dummy>; +}; + +&usbdrd_phy { + status = "okay"; +}; From 09449e48be7390ebc53812ab898d669e3832c704 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Wed, 16 Jul 2025 11:31:08 +0530 Subject: [PATCH 183/931] arm64: dts: ti: k3-j784s4-j742s2-main-common: Add DSI & DSI PHY Add DT nodes for DPI to DSI Bridge and DSI Phy. The DSI bridge is Cadence DSI and the PHY is a Cadence DPHY with TI wrapper. Signed-off-by: Jayesh Choudhary Tested-by: Harikrishna Shenoy Reviewed-by: Harikrishna Shenoy Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250716060114.52122-2-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- .../dts/ti/k3-j784s4-j742s2-main-common.dtsi | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 7c5b0c69897d..79d97d46b4c6 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -2522,6 +2522,45 @@ watchdog18: watchdog@2550000 { status = "reserved"; }; + dphy_tx0: phy@4480000 { + compatible = "ti,j721e-dphy"; + reg = <0x00 0x04480000 0x00 0x00001000>; + clocks = <&k3_clks 402 20>, <&k3_clks 402 3>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 402 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 402 3>; + assigned-clock-parents = <&k3_clks 402 4>; + assigned-clock-rates = <19200000>; + status = "disabled"; + }; + + dsi0: dsi@4800000 { + compatible = "ti,j721e-dsi"; + reg = <0x00 0x04800000 0x00 0x00100000>, + <0x00 0x04710000 0x00 0x00000100>; + clocks = <&k3_clks 215 2>, <&k3_clks 215 5>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; + interrupts = ; + phys = <&dphy_tx0>; + phy-names = "dphy"; + status = "disabled"; + + dsi0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + mhdp: bridge@a000000 { compatible = "ti,j721e-mhdp8546"; reg = <0x0 0xa000000 0x0 0x30a00>, From a5ed774877a38f2feeb45f0c2cd16184b47b476b Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Wed, 16 Jul 2025 11:31:09 +0530 Subject: [PATCH 184/931] arm64: dts: ti: k3-j784s4-j742s2-evm-common: Enable DisplayPort-1 Enable DSI display for J784S4 EVM. Add DT node for DSI-to-eDP bridge. The DSI to eDP bridge is SN65DSI86 on the board. Add the endpoint nodes to describe connection from: DSS => DSI => SN65DSI86 bridge => DisplayPort-1 Signed-off-by: Jayesh Choudhary Tested-by: Harikrishna Shenoy Reviewed-by: Harikrishna Shenoy Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250716060114.52122-3-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- .../dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 121 +++++++++++++++++- 1 file changed, 120 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index fa656b7b13a1..6afa802544e9 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -301,6 +301,52 @@ codec_audio: sound { clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", "cpb-codec-scki", "cpb-codec-scki-48000"; }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + edp1_refclk: clock-edp1-refclk { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; + + dp1_pwr_3v3: regulator-dp1-prw { + compatible = "regulator-fixed"; + regulator-name = "dp1-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + dp1: connector-dp1 { + compatible = "dp-connector"; + label = "DP1"; + type = "full-size"; + dp-pwr-supply = <&dp1_pwr_3v3>; + + port { + dp1_connector_in: endpoint { + remote-endpoint = <&dp1_out>; + }; + }; + }; }; &wkup_gpio0 { @@ -1340,12 +1386,26 @@ &mhdp { }; &dss_ports { + #address-cells = <1>; + #size-cells = <0>; + /* DP */ - port { + port@0 { + reg = <0>; + dpi0_out: endpoint { remote-endpoint = <&dp0_in>; }; }; + + /* DSI */ + port@2 { + reg = <2>; + + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; }; &main_i2c4 { @@ -1360,6 +1420,65 @@ exp4: gpio@20 { gpio-controller; #gpio-cells = <2>; }; + + bridge_dsi_edp: bridge-dsi-edp@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + clock-names = "refclk"; + clocks = <&edp1_refclk>; + enable-gpios = <&exp4 2 GPIO_ACTIVE_HIGH>; + vpll-supply = <&vsys_io_1v8>; + vccio-supply = <&vsys_io_1v8>; + vcca-supply = <&vsys_io_1v2>; + vcc-supply = <&vsys_io_1v2>; + + dsi_edp_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dp1_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + dp1_out: endpoint { + remote-endpoint = <&dp1_connector_in>; + }; + }; + }; + }; +}; + +&dsi0_ports { + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&dp1_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; }; &dp0_ports { From 19a4472e591d9945f4983d052adf7d7fa67efcce Mon Sep 17 00:00:00 2001 From: Rahul T R Date: Wed, 16 Jul 2025 11:31:10 +0530 Subject: [PATCH 185/931] arm64: dts: ti: k3-j721s2-main: Add DSI & DSI PHY Add DT nodes for DPI to DSI Bridge and DSI Phy. The DSI bridge is Cadence DSI and the PHY is a Cadence DPHY with TI wrapper. Signed-off-by: Rahul T R [j-choudhary@ti.com: disable dsi and dphy nodes, rename dphy node] Signed-off-by: Jayesh Choudhary Tested-by: Harikrishna Shenoy Reviewed-by: Harikrishna Shenoy Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250716060114.52122-4-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 62f45377a2c9..c31d7f3eab28 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1795,6 +1795,45 @@ main_spi7: spi@2170000 { status = "disabled"; }; + dphy_tx0: phy@4480000 { + compatible = "ti,j721e-dphy"; + reg = <0x00 0x04480000 0x00 0x00001000>; + clocks = <&k3_clks 363 8>, <&k3_clks 363 14>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 363 14>; + assigned-clock-parents = <&k3_clks 363 15>; + assigned-clock-rates = <19200000>; + status = "disabled"; + }; + + dsi0: dsi@4800000 { + compatible = "ti,j721e-dsi"; + reg = <0x00 0x04800000 0x00 0x00100000>, + <0x00 0x04710000 0x00 0x00000100>; + clocks = <&k3_clks 154 4>, <&k3_clks 154 1>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + interrupts = ; + phys = <&dphy_tx0>; + phy-names = "dphy"; + status = "disabled"; + + dsi0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ From 722a128adaf97fc2ecb64610a482f1399b3f4c2a Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Wed, 16 Jul 2025 11:31:11 +0530 Subject: [PATCH 186/931] arm64: dts: ti: k3-j721s2-common-proc-board: Add main_i2c4 instance Add dt node for main_i2c4 instance along with required pinmuxing. Also add the gpio expander 'exp4' required by display connector. Signed-off-by: Jayesh Choudhary Tested-by: Harikrishna Shenoy Reviewed-by: Harikrishna Shenoy Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250716060114.52122-5-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- .../dts/ti/k3-j721s2-common-proc-board.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index e2fc1288ed07..793d50344fad 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -148,6 +148,13 @@ J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ >; }; + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) I2C4_SCL */ + J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) I2C4_SDA */ + >; + }; + main_i2c5_pins_default: main-i2c5-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ @@ -370,6 +377,23 @@ exp2: gpio@22 { }; }; +&main_i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <400000>; + + exp4: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "DP0_PWR_SW_EN", "DP1_PWR_SW_EN", "UB981_PDB", + "UB981_GPIO0", "UB981_GPIO1", "UB981_GPIO2", + "UB981_GPIO3", "PWR_SW_CNTL_DSI0#"; + }; +}; + &main_i2c5 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c5_pins_default>; From 3c29300dcef587df697750e99f6375e2ca8907fb Mon Sep 17 00:00:00 2001 From: Rahul T R Date: Wed, 16 Jul 2025 11:31:12 +0530 Subject: [PATCH 187/931] arm64: dts: ti: k3-j721s2-som-p0: Add DSI to eDP Add DT nodes for DSI to eDP bridge. The DSI to eDP bridge used is SN65DSI86 on SOM. Signed-off-by: Rahul T R Signed-off-by: Jayesh Choudhary Tested-by: Harikrishna Shenoy Reviewed-by: Harikrishna Shenoy Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250716060114.52122-6-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 51 ++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index 54fc5c4f8c3f..a9dbe14fb0c9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -152,6 +152,30 @@ transceiver0: can-phy0 { #phy-cells = <0>; max-bitrate = <5000000>; }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vsys_io_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + edp1_refclk: clock-edp1-refclk { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; }; &wkup_pmx0 { @@ -630,3 +654,30 @@ &c71_1 { memory-region = <&c71_1_dma_memory_region>, <&c71_1_memory_region>; }; + +&main_i2c4 { + bridge_dsi_edp: bridge-dsi-edp@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + clock-names = "refclk"; + clocks = <&edp1_refclk>; + enable-gpios = <&exp_som 5 0>; + vpll-supply = <&vsys_io_1v8>; + vccio-supply = <&vsys_io_1v8>; + vcca-supply = <&vsys_io_1v2>; + vcc-supply = <&vsys_io_1v2>; + + dsi_edp_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; +}; From 2bca9f69225e8c6e3c270f20c69a1460761f9bd2 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Wed, 16 Jul 2025 11:31:13 +0530 Subject: [PATCH 188/931] arm64: dts: ti: k3-j721s2-common-proc-board: Enable DisplayPort-1 Enable DSI display for J721S2 EVM. Add the endpoint nodes to describe connection from: DSS => DSI Bridge => DSI to eDP bridge => DisplayPort-1 Signed-off-by: Jayesh Choudhary Tested-by: Harikrishna Shenoy Reviewed-by: Harikrishna Shenoy Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250716060114.52122-7-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- .../dts/ti/k3-j721s2-common-proc-board.dts | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 793d50344fad..9e43dcff8ef2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -93,6 +93,28 @@ vdd_sd_dv: gpio-regulator-TLV71033 { <3300000 0x1>; }; + dp1_pwr_3v3: regulator-dp1-prw { + compatible = "regulator-fixed"; + regulator-name = "dp1-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 1 GPIO_ACTIVE_HIGH>; /* P1 - DP1_PWR_SW_EN */ + enable-active-high; + }; + + dp1: connector-dp1 { + compatible = "dp-connector"; + label = "DP1"; + type = "full-size"; + dp-pwr-supply = <&dp1_pwr_3v3>; + + port { + dp1_connector_in: endpoint { + remote-endpoint = <&dp1_out>; + }; + }; + }; + transceiver1: can-phy1 { compatible = "ti,tcan1043"; #phy-cells = <0>; @@ -563,3 +585,74 @@ &main_mcan5 { pinctrl-0 = <&main_mcan5_pins_default>; phys = <&transceiver4>; }; + +&dss { + /* + * DSS on J721S2-EVM supports DP on VP0 and DSI on VP2. + * These clock assignments are chosen to enable the following outputs: + * VP0 - DisplayPort SST + * VP2 - DSI + */ + status = "okay"; + assigned-clocks = <&k3_clks 158 2>, + <&k3_clks 158 14>; + assigned-clock-parents = <&k3_clks 158 3>, + <&k3_clks 158 16>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&dsi0_ports { + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&dp1_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; +}; + +&dsi_edp_bridge_ports { + port@0 { + reg = <0>; + + dp1_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + dp1_out: endpoint { + remote-endpoint = <&dp1_connector_in>; + }; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; From 11b9e4517bfa8edecbef0acfcad1bdca4f4a4192 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Wed, 16 Jul 2025 11:31:14 +0530 Subject: [PATCH 189/931] arm64: dts: ti: k3-am68-sk: Enable DSI on DisplayPort-0 Enable DSI support for AM68-SK platform. Add DT node for DSI2eDP bridge. The DSI to eDP bridge is sn65dsi86 on the board. Add the endpoint nodes to describe connection from: DSS => DSI => SN65DSI86 bridge => DisplayPort-0 Signed-off-by: Jayesh Choudhary Tested-by: Harikrishna Shenoy Reviewed-by: Harikrishna Shenoy Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20250716060114.52122-8-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am68-sk-base-board.dts | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index e84c504c87d2..75a107456ce1 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -135,6 +135,34 @@ transceiver4: can-phy3 { max-bitrate = <5000000>; }; + edp0_refclk: clock-edp0-refclk { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; + + dp0_pwr_3v3: regulator-dp0-pwr { + compatible = "regulator-fixed"; + regulator-name = "dp0-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; /*P0 - DP0_3V3 _EN */ + enable-active-high; + }; + + dp0: dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; + connector-hdmi { compatible = "hdmi-connector"; label = "hdmi"; @@ -615,6 +643,39 @@ exp2: gpio@20 { gpio-line-names = "HDMI_PDn","HDMI_LS_OE", "DP0_3V3_EN","eDP_ENABLE"; }; + + bridge_dsi_edp: bridge-dsi-edp@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + clock-names = "refclk"; + clocks = <&edp0_refclk>; + enable-gpios = <&exp2 3 GPIO_ACTIVE_HIGH>; + vpll-supply = <&vsys_io_1v8>; + vccio-supply = <&vsys_io_1v8>; + vcca-supply = <&vsys_io_1v2>; + vcc-supply = <&vsys_io_1v2>; + + dsi_edp_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dp0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; + }; + }; }; &main_sdhci1 { @@ -711,6 +772,15 @@ dpi_out0: endpoint { remote-endpoint = <&tfp410_in>; }; }; + + /* DSI */ + port@2 { + reg = <2>; + + dpi0_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; }; &serdes_ln_ctrl { @@ -768,3 +838,30 @@ &usb0 { phys = <&serdes0_usb_link>; phy-names = "cdns3,usb3-phy"; }; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_ports { + + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; +}; From 6aa4c1a38cf10c9760f81d456b7f92ff157e5f83 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Mon, 4 Aug 2025 12:54:50 +0200 Subject: [PATCH 190/931] arm64: dts: ti: k3-am642-phyboard-electra: Add ti,pa-stats property Add ti,pa-stats phandles. This is a phandle to PA_STATS syscon regmap and will be used to dump IET related statistics for ICSSG Driver. Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20250804105450.2322647-1-w.egorov@phytec.de Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 129524eb5b91..e4afa8c0a8ca 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -100,6 +100,7 @@ ethernet { ti,mii-g-rt = <&icssg0_mii_g_rt>; ti,mii-rt = <&icssg0_mii_rt>; ti,iep = <&icssg0_iep0>, <&icssg0_iep1>; + ti,pa-stats = <&icssg0_pa_stats>; ethernet-ports { #address-cells = <1>; From f13db4f77d54a6db644f09a168919ad1b3432f52 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Tue, 5 Aug 2025 11:00:21 +0200 Subject: [PATCH 191/931] arm64: dts: ti: k3-am62a-phycore-som: Add 1.4GHz opp entry The phyCORE-AM62Ax is capable of supplying 0v85 to the VDD_CORE which allows the Cortex-A53s to operate at 1.4GHz according to chapter 7.5 of the SoC's data sheet[0]. Append the 1.4Ghz entry to the OPP table to enable this OPP [0] https://www.ti.com/lit/ds/symlink/am62a3.pdf Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20250805090021.1407753-2-w.egorov@phytec.de Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index 5dc5d2cb20cc..207ca00630d1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -200,6 +200,15 @@ AM62AX_IOPAD(0x1f4, PIN_INPUT, 0) /* (D16) EXTINTn */ }; }; +&a53_opp_table { + /* Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; +}; + &c7x_0 { mboxes = <&mailbox0_cluster1 &mbox_c7x_0>; memory-region = <&c7x_0_dma_memory_region>, From 94801d4bf1ed9277462ebe1afaf8323664fd6a85 Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Fri, 8 Aug 2025 15:27:58 +0530 Subject: [PATCH 192/931] arm64: dts: ti: k3-j721s2-main: Add CSI2 interrupts property Add interrupts property for CDNS CSI2RX. Interrupt IDs are taken from the J721S2 TRM [0]. Interrupt Line | Source Interrupt --------------------|----------------------------- GIC500SS_SPI_IN_185 | CSI_RX_IF0_CSI_ERR_IRQ_OUT_0 GIC500SS_SPI_IN_184 | CSI_RX_IF0_CSI_IRQ_OUT_0 GIC500SS_SPI_IN_189 | CSI_RX_IF1_CSI_ERR_IRQ_OUT_0 GIC500SS_SPI_IN_188 | CSI_RX_IF1_CSI_IRQ_OUT_0 [0]: https://www.ti.com/lit/zip/spruj28 Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar Reviewed-by: Jared McArthur Link: https://lore.kernel.org/r/20250808095804.544298-2-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index c31d7f3eab28..726374dc8795 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1248,6 +1248,9 @@ ti_csi2rx0: ticsi2rx@4500000 { cdns_csi2rx0: csi-bridge@4504000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x04504000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>, <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -1301,6 +1304,9 @@ ti_csi2rx1: ticsi2rx@4510000 { cdns_csi2rx1: csi-bridge@4514000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x04514000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>, <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", From 33b34bfa4f22216845f5fd738d320e78d75cf1ff Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Fri, 8 Aug 2025 15:27:59 +0530 Subject: [PATCH 193/931] arm64: dts: ti: k3-j721e-main: Add CSI2 interrupts property Add interrupts property for CSI2RX. Interrupt IDs are taken from the J721E TRM [0]. Interrupt Line | Source Interrupt ------------------|------------------------- GIC500_SPI_IN_185 | CSI_RX_IF0_CSI_ERR_IRQ_0 GIC500_SPI_IN_184 | CSI_RX_IF0_CSI_IRQ_0 GIC500_SPI_IN_189 | CSI_RX_IF1_CSI_ERR_IRQ_0 GIC500_SPI_IN_188 | CSI_RX_IF1_CSI_IRQ_0 [0]: http://www.ti.com/lit/pdf/spruil1 Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar Reviewed-by: Jared McArthur Link: https://lore.kernel.org/r/20250808095804.544298-3-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 5bd0d36bf33e..ab3666ff4297 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -608,6 +608,9 @@ ti_csi2rx0: ticsi2rx@4500000 { cdns_csi2rx0: csi-bridge@4504000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x0 0x4504000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -661,6 +664,9 @@ ti_csi2rx1: ticsi2rx@4510000 { cdns_csi2rx1: csi-bridge@4514000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x0 0x4514000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", From 84ba1f67c6169e4533aa109888accbbccef25705 Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Fri, 8 Aug 2025 15:28:00 +0530 Subject: [PATCH 194/931] arm64: dts: ti: k3-j784s4-j742s2-main-common: Add CSI2 interrupts property Add interrupts property for CSI2RX. Interrupt IDs are taken from the J784S4 TRM [0]. Interrupt Line | Source Interrupt --------------------|------------------------- GIC500SS_SPI_IN_185 | CSI_RX_IF0_CSI_ERR_IRQ_0 GIC500SS_SPI_IN_184 | CSI_RX_IF0_CSI_IRQ_0 GIC500SS_SPI_IN_189 | CSI_RX_IF1_CSI_ERR_IRQ_0 GIC500SS_SPI_IN_188 | CSI_RX_IF1_CSI_IRQ_0 GIC500SS_SPI_IN_193 | CSI_RX_IF2_CSI_ERR_IRQ_0 GIC500SS_SPI_IN_192 | CSI_RX_IF2_CSI_IRQ_0 [0]: https://www.ti.com/lit/zip/spruj52 Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar Reviewed-by: Jared McArthur Link: https://lore.kernel.org/r/20250808095804.544298-4-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 79d97d46b4c6..fbbe768e7a30 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -819,6 +819,9 @@ ti_csi2rx0: ticsi2rx@4500000 { cdns_csi2rx0: csi-bridge@4504000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x04504000 0x00 0x00001000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -872,6 +875,9 @@ ti_csi2rx1: ticsi2rx@4510000 { cdns_csi2rx1: csi-bridge@4514000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x04514000 0x00 0x00001000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -924,6 +930,9 @@ ti_csi2rx2: ticsi2rx@4520000 { cdns_csi2rx2: csi-bridge@4524000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x04524000 0x00 0x00001000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", From 347866a21ff447e868305426c294395b2cee68a7 Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Fri, 8 Aug 2025 15:28:01 +0530 Subject: [PATCH 195/931] arm64: dts: ti: k3-am62p-j722s-common-main: Add CSI2 interrupts property Add interrupts property for CDNS CSI2RX. Interrupt IDs are taken from the J722S TRM [0]. Interrupt Line | Source Interrupt -------------------|------------------------- GICSS0_SPI_IN_175 | CSI_RX_IF0_CSI_ERR_IRQ_0 GICSS0_SPI_IN_173 | CSI_RX_IF0_CSI_IRQ_0 [0]: https://www.ti.com/lit/zip/sprujb3 Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar Reviewed-by: Jared McArthur Link: https://lore.kernel.org/r/20250808095804.544298-5-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 2e5e25a8ca86..4427b12058a6 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -1045,6 +1045,9 @@ ti_csi2rx0: ticsi2rx@30102000 { cdns_csi2rx0: csi-bridge@30101000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30101000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", From 772cc597174486b85585ed02a74cc332ba25de01 Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Fri, 8 Aug 2025 15:28:02 +0530 Subject: [PATCH 196/931] arm64: dts: ti: k3-j722s-main: Add CSI2 interrupts property Add interrupts property for CDNS CSI2RX. Interrupt IDs are taken from the J722S TRM [0]. Interrupt Line | Source Interrupt -------------------|------------------------- GICSS0_SPI_IN_178 | CSI_RX_IF1_CSI_ERR_IRQ_0 GICSS0_SPI_IN_179 | CSI_RX_IF1_CSI_IRQ_0 GICSS0_SPI_IN_219 | CSI_RX_IF2_CSI_ERR_IRQ_0 GICSS0_SPI_IN_232 | CSI_RX_IF2_CSI_IRQ_0 GICSS0_SPI_IN_249 | CSI_RX_IF3_CSI_ERR_IRQ_0 GICSS0_SPI_IN_250 | CSI_RX_IF3_CSI_IRQ_0 [0]: https://www.ti.com/lit/zip/sprujb3 Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar Reviewed-by: Jared McArthur Link: https://lore.kernel.org/r/20250808095804.544298-6-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 5cfa7bf36641..6a8e5ff3b1d5 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -168,6 +168,9 @@ ti_csi2rx1: ticsi2rx@30122000 { cdns_csi2rx1: csi-bridge@30121000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30121000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>, <&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -221,6 +224,9 @@ ti_csi2rx2: ticsi2rx@30142000 { cdns_csi2rx2: csi-bridge@30141000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30141000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>, <&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", @@ -274,6 +280,9 @@ ti_csi2rx3: ticsi2rx@30162000 { cdns_csi2rx3: csi-bridge@30161000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30161000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>, <&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", From 96ba5ce55ec192ca28446d4045dfd501270769b3 Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Fri, 8 Aug 2025 15:28:03 +0530 Subject: [PATCH 197/931] arm64: dts: ti: k3-am62-main: Add CSI2 interrupts property Add interrupts property for CDNS CSI2RX. Interrupt IDs are taken from the AM62 TRM [0]. Interrupt Line | Source Interrupt ---------------|-------------------------- gicss0.spi.175 | csi_rx_if.0.csi_err_irq.0 gicss0.spi.173 | csi_rx_if.0.csi_irq.0 [0]: https://www.ti.com/lit/pdf/spruiv7 Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar Reviewed-by: Jared McArthur Link: https://lore.kernel.org/r/20250808095804.544298-7-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 120ba8f9dd0e..029380dc1a35 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -1031,6 +1031,9 @@ ti_csi2rx0: ticsi2rx@30102000 { cdns_csi2rx0: csi-bridge@30101000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30101000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", From 9307cad31efcfe3446847ee34effaaa5c4930fa8 Mon Sep 17 00:00:00 2001 From: Yemike Abhilash Chandra Date: Fri, 8 Aug 2025 15:28:04 +0530 Subject: [PATCH 198/931] arm64: dts: ti: k3-am62a-main: Add CSI2 interrupts property Add interrupts property for CDNS CSI2RX. Interrupt IDs are taken from the AM62A TRM [0]. Interrupt Line | Source Interrupt ---------------------------|---------------------------------- GICSS0_COMMON_0_SPI_IN_175 | CSI_RX_IF0_COMMON_0_CSI_ERR_IRQ_0 GICSS0_COMMON_0_SPI_IN_173 | CSI_RX_IF0_COMMON_0_CSI_IRQ_0 [0]: https://www.ti.com/lit/pdf/spruj16 Signed-off-by: Yemike Abhilash Chandra Reviewed-by: Udit Kumar Reviewed-by: Jared McArthur Link: https://lore.kernel.org/r/20250808095804.544298-8-y-abhilashchandra@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 44e7e459f176..9cad79d7bbc1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -1054,6 +1054,9 @@ ti_csi2rx0: ticsi2rx@30102000 { cdns_csi2rx0: csi-bridge@30101000 { compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; reg = <0x00 0x30101000 0x00 0x1000>; + interrupts = , + ; + interrupt-names = "error_irq", "irq"; clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; clock-names = "sys_clk", "p_clk", "pixel_if0_clk", From 47a32605c6e7f283f373b56e9caf97c56b7e5634 Mon Sep 17 00:00:00 2001 From: Brandon Brnich Date: Fri, 8 Aug 2025 10:55:55 -0500 Subject: [PATCH 199/931] arm64: dts: ti: k3-j722s-main: Add E5010 JPEG Encoder This adds node for E5010 JPEG Encoder which is a stateful JPEG Encoder present in J722s SoC, supporting baseline encoding of semiplanar based YUV420 and YUV422 raw video formats to JPEG encoding, with resolutions supported from 64x64 to 8kx8k. Signed-off-by: Brandon Brnich Reviewed-by: Devarsh Thakkar Link: https://lore.kernel.org/r/20250808155555.2632451-1-b-brnich@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 6a8e5ff3b1d5..993828872dfb 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -394,6 +394,16 @@ c7x_1: dsp@7e200000 { ti,sci-proc-ids = <0x31 0xff>; status = "disabled"; }; + + e5010: jpeg-encoder@fd20000 { + compatible = "ti,am62a-jpeg-enc", "img,e5010-jpeg-enc"; + reg = <0x00 0xfd20000 0x00 0x100>, + <0x00 0xfd20200 0x00 0x200>; + reg-names = "core", "mmu"; + clocks = <&k3_clks 201 0>; + power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; + interrupts = ; + }; }; &main_bcdma_csi { From 20b3c9a403ee23e57a7e6bf5370ca438c3cd2e99 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 6 Aug 2025 16:28:23 -0500 Subject: [PATCH 200/931] dt-bindings: arm: Convert ti,keystone to DT schema Signed-off-by: Rob Herring (Arm) Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20250806212824.1635084-1-robh@kernel.org Signed-off-by: Nishanth Menon --- .../bindings/arm/keystone/keystone.txt | 42 ------------------- .../bindings/arm/ti/ti,keystone.yaml | 42 +++++++++++++++++++ 2 files changed, 42 insertions(+), 42 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/keystone/keystone.txt create mode 100644 Documentation/devicetree/bindings/arm/ti/ti,keystone.yaml diff --git a/Documentation/devicetree/bindings/arm/keystone/keystone.txt b/Documentation/devicetree/bindings/arm/keystone/keystone.txt deleted file mode 100644 index f310bad04483..000000000000 --- a/Documentation/devicetree/bindings/arm/keystone/keystone.txt +++ /dev/null @@ -1,42 +0,0 @@ -TI Keystone Platforms Device Tree Bindings ------------------------------------------------ - -Boards with Keystone2 based devices (TCI66xxK2H) SOC shall have the -following properties. - -Required properties: - - compatible: All TI specific devices present in Keystone SOC should be in - the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550 - type UART should use the specified compatible for those devices. - -SoC families: - -- Keystone 2 generic SoC: - compatible = "ti,keystone" - -SoCs: - -- Keystone 2 Hawking/Kepler - compatible = "ti,k2hk", "ti,keystone" -- Keystone 2 Lamarr - compatible = "ti,k2l", "ti,keystone" -- Keystone 2 Edison - compatible = "ti,k2e", "ti,keystone" -- K2G - compatible = "ti,k2g", "ti,keystone" - -Boards: -- Keystone 2 Hawking/Kepler EVM - compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone" - -- Keystone 2 Lamarr EVM - compatible = "ti,k2l-evm", "ti, k2l", "ti,keystone" - -- Keystone 2 Edison EVM - compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone" - -- K2G EVM - compatible = "ti,k2g-evm", "ti,k2g", "ti-keystone" - -- K2G Industrial Communication Engine EVM - compatible = "ti,k2g-ice", "ti,k2g", "ti-keystone" diff --git a/Documentation/devicetree/bindings/arm/ti/ti,keystone.yaml b/Documentation/devicetree/bindings/arm/ti/ti,keystone.yaml new file mode 100644 index 000000000000..20d4084f4506 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ti/ti,keystone.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ti/ti,keystone.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Keystone Platforms + +maintainers: + - Nishanth Menon + - Santosh Shilimkar + +properties: + compatible: + oneOf: + - description: K2G + items: + - enum: + - ti,k2g-evm + - ti,k2g-ice + - const: ti,k2g + - const: ti,keystone + - description: Keystone 2 Edison + items: + - enum: + - ti,k2e-evm + - const: ti,k2e + - const: ti,keystone + - description: Keystone 2 Lamarr + items: + - enum: + - ti,k2l-evm + - const: ti,k2l + - const: ti,keystone + - description: Keystone 2 Hawking/Kepler + items: + - enum: + - ti,k2hk-evm + - const: ti,k2hk + - const: ti,keystone + +additionalProperties: true From f10512e2c44e6ee3242314d43102acab7340e2d3 Mon Sep 17 00:00:00 2001 From: Hendrik Hamerlinck Date: Wed, 13 Aug 2025 11:22:39 +0200 Subject: [PATCH 201/931] dt-bindings: riscv: spacemit: Add OrangePi RV2 board Document the compatible string for the OrangePi RV2 board [1]. The board is described as using the Ky X1 SoC, which, based on available downstream sources and testing, appears to be identical or very closely related to the SpacemiT K1 SoC [2]. Link: http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-RV2.html [1] Link: https://www.spacemit.com/en/key-stone-k1 [2] Signed-off-by: Hendrik Hamerlinck Reviewed-by: Yixun Lan Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250813092240.180333-2-hendrik.hamerlinck@hammernet.be Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/riscv/spacemit.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index 077b94f10dca..c56b62a6299a 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -22,6 +22,7 @@ properties: - enum: - bananapi,bpi-f3 - milkv,jupiter + - xunlong,orangepi-rv2 - const: spacemit,k1 additionalProperties: true From bab8dea259100a99e047fd11a48940b229d30031 Mon Sep 17 00:00:00 2001 From: Hendrik Hamerlinck Date: Wed, 13 Aug 2025 11:22:40 +0200 Subject: [PATCH 202/931] riscv: dts: spacemit: Add OrangePi RV2 board device tree Add initial device tree support for the OrangePi RV2 board [1]. The board is described as using the Ky X1 SoC, which, based on available downstream sources and testing, appears to be identical or very closely related to the SpacemiT K1 SoC [2]. The device tree is adapted from the OrangePi vendor tree [3], and similar integration can be found in the Banana Pi kernel tree [4], confirming SoC compatibility. The main difference with the current Banana Pi BPI-F3 tree is that status led is using GPIO_ACTIVE_LOW. This minimal device tree enables booting into a serial console with UART output and a blinking LED. Link: http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-RV2.html [1] Link: https://www.spacemit.com/en/key-stone-k1 [2] Link: https://github.com/BPI-SINOVOIP/pi-linux/blob/linux-6.6.63-k1/arch/riscv/boot/dts/spacemit/k1-x_orangepi-rv2.dts [3] Link: https://github.com/orangepi-xunlong/linux-orangepi/tree/orange-pi-6.6-ky [4] Signed-off-by: Hendrik Hamerlinck Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20250813092240.180333-3-hendrik.hamerlinck@hammernet.be Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/Makefile | 1 + .../boot/dts/spacemit/k1-orangepi-rv2.dts | 40 +++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile index 92e13ce1c16d..152832644870 100644 --- a/arch/riscv/boot/dts/spacemit/Makefile +++ b/arch/riscv/boot/dts/spacemit/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_SPACEMIT) += k1-bananapi-f3.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb +dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts new file mode 100644 index 000000000000..337240ebb7b7 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2024 Yangyu Chen + * Copyright (C) 2025 Hendrik Hamerlinck + */ + +/dts-v1/; + +#include "k1.dtsi" +#include "k1-pinctrl.dtsi" + +/ { + model = "OrangePi RV2"; + compatible = "xunlong,orangepi-rv2", "spacemit,k1"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0"; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + label = "sys-led"; + gpios = <&gpio K1_GPIO(96) GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; +}; From 2eb676f1410dd7c3aa91534cbf86dfb1dee3bc7c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 15 Aug 2025 08:51:32 -0500 Subject: [PATCH 203/931] Revert "arm64: dts: qcom: sm8450: add initial device tree for Samsung Galaxy S22" This reverts commit 46952305d2b6 ("arm64: dts: qcom: sm8450: add initial device tree for Samsung Galaxy S22"), as the merged version had been superseded and received further feedback. Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sm8450-samsung-r0q.dts | 364 ------------------ 1 file changed, 364 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts diff --git a/arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts b/arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts deleted file mode 100644 index e9e21c25444a..000000000000 --- a/arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts +++ /dev/null @@ -1,364 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2025, Eric Gonçalves - */ - -/dts-v1/; - -#include -#include -#include - -#include "sm8450.dtsi" -#include "pm8350.dtsi" -#include "pm8350b.dtsi" -#include "pm8350c.dtsi" -#include "pm8450.dtsi" -#include "pmk8350.dtsi" -#include "pmr735a.dtsi" - -/delete-node/ &xbl_ramdump_mem; -/delete-node/ &xbl_sc_mem; -/delete-node/ &adsp_mem; -/delete-node/ &rmtfs_mem; -/delete-node/ &mte_mem; -/delete-node/ &trusted_apps_mem; -/delete-node/ &trusted_apps_ext_mem; - -/ { - chassis-type = "handset"; - model = "Samsung Galaxy S22 (SM-S901E)"; - compatible = "samsung,r0q", "qcom,sm8450"; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - bootargs = "clk_ignore_unused pd_ignore_unused"; - linux,initrd-start = <0x00 0xb6915000>; - linux,initrd-end = <0x00 0xb7fff22c>; - stdout-path = "serial0:115200n8"; - - framebuffer: framebuffer@b8000000 { - compatible = "simple-framebuffer"; - reg = <0x0 0xb8000000 0x0 0x2b00000>; - width = <1080>; - height = <2340>; - stride = <(1080 * 4)>; - format = "a8r8g8b8"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - pinctrl-0 = <&vol_up_n>; - pinctrl-names = "default"; - - key-vol-up { - label = "Volume Up"; - linux,code = ; - gpios = <&pm8350_gpios 6 GPIO_ACTIVE_LOW>; - debounce-interval = <15>; - }; - }; - - memory { - ddr_device_type = <0x08>; - device_type = "memory"; - reg = <0x00 0x80000000 0x00 0x6a000000 0x00 0xf1c00000 0x00 0xe400000 0x08 0x00 0x00 0x3ab00000 0x08 0x40000000 0x01 0x40000000 0x08 0x3b100000 0x00 0x1e00000>; - }; - - reserved-memory { - xbl_ramdump_mem: memory@a6b80000 { - reg = <0x0 0xa7d00000 0x0 0x300000>; - no-map; - }; - - xbl_sc_mem: memory@a6e00000 { - reg = <0x0 0xa6e00000 0x0 0x40000>; - no-map; - }; - - adsp_mem: memory@9fd00000 { - reg = <0x0 0x84500000 0x0 0x3b00000>; - no-map; - }; - - rmtfs_mem: memory@fe200000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0xfe200000 0x0 0x280000>; - reg-names = "rmtfs"; - qcom,client-id = <1>; - no-map; - - qcom,vmid = ; - }; - - splash_region@b8000000 { - reg = <0x0 0xb8000000 0x0 0x2b00000>; - no-map; - }; - }; - - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - - regulator-always-on; - regulator-boot-on; - }; -}; - -&tlmm { - gpio-reserved-ranges = <36 4>, <50 1>, <93 1>; - - dsi_default: dsi-default-state { - pins = "gpio6"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - - dsi_suspend: dsi-suspend-state { - pins = "gpio6"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; -}; - -&apps_rsc { - regulators-0 { - compatible = "qcom,pm8350-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-s9-supply = <&vph_pwr>; - vdd-s10-supply = <&vph_pwr>; - vdd-s11-supply = <&vph_pwr>; - vdd-s12-supply = <&vph_pwr>; - - vdd-l1-l4-supply = <&vreg_s11b_0p95>; - vdd-l2-l7-supply = <&vreg_bob>; - vdd-l3-l5-supply = <&vreg_bob>; - vdd-l6-l9-l10-supply = <&vreg_s12b_1p25>; - vdd-l8-supply = <&vreg_s2h_0p95>; - - vreg_s11b_0p95: smps11 { - regulator-name = "vreg_s11b_0p95"; - regulator-min-microvolt = <848000>; - regulator-max-microvolt = <1104000>; - }; - - vreg_s12b_1p25: smps12 { - regulator-name = "vreg_s12b_1p25"; - regulator-min-microvolt = <1224000>; - regulator-max-microvolt = <1400000>; - }; - - vreg_l1b_0p91: ldo1 { - regulator-name = "vreg_l1b_0p91"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l2b_3p07: ldo2 { - regulator-name = "vreg_l2b_3p07"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l5b_0p88: ldo5 { - regulator-name = "vreg_l5b_0p88"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <888000>; - regulator-initial-mode = ; - }; - - vreg_l6b_1p2: ldo6 { - regulator-name = "vreg_l6b_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l7b_2p5: ldo7 { - regulator-name = "vreg_l7b_2p5"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2504000>; - regulator-initial-mode = ; - }; - - vreg_l9b_1p2: ldo9 { - regulator-name = "vreg_l9b_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - }; - - regulators-1 { - compatible = "qcom,pm8350c-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - vdd-s7-supply = <&vph_pwr>; - vdd-s8-supply = <&vph_pwr>; - vdd-s9-supply = <&vph_pwr>; - vdd-s10-supply = <&vph_pwr>; - - vdd-l1-l12-supply = <&vreg_bob>; - vdd-l2-l8-supply = <&vreg_bob>; - vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; - vdd-l6-l9-l11-supply = <&vreg_bob>; - - vdd-bob-supply = <&vph_pwr>; - - vreg_s1c_1p86: smps1 { - regulator-name = "vreg_s1c_1p86"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2024000>; - }; - - vreg_bob: bob { - regulator-name = "vreg_bob"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3960000>; - regulator-initial-mode = ; - }; - - vreg_l1c_1p8: ldo1 { - regulator-name = "vreg_l1c_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; - - regulators-2 { - compatible = "qcom,pm8450-rpmh-regulators"; - qcom,pmic-id = "h"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - vdd-s4-supply = <&vph_pwr>; - vdd-s5-supply = <&vph_pwr>; - vdd-s6-supply = <&vph_pwr>; - - vdd-l2-supply = <&vreg_bob>; - vdd-l3-supply = <&vreg_bob>; - vdd-l4-supply = <&vreg_bob>; - - vreg_s2h_0p95: smps2 { - regulator-name = "vreg_s2h_0p95"; - regulator-min-microvolt = <848000>; - regulator-max-microvolt = <1104000>; - }; - }; - - regulators-3 { - compatible = "qcom,pmr735a-rpmh-regulators"; - qcom,pmic-id = "e"; - - vdd-s1-supply = <&vph_pwr>; - vdd-s2-supply = <&vph_pwr>; - vdd-s3-supply = <&vph_pwr>; - - vdd-l1-l2-supply = <&vreg_s2e_0p85>; - vdd-l3-supply = <&vreg_s1e_1p25>; - vdd-l4-supply = <&vreg_s1c_1p86>; - vdd-l5-l6-supply = <&vreg_s1c_1p86>; - vdd-l7-bob-supply = <&vreg_bob>; - - vreg_s1e_1p25: smps1 { - regulator-name = "vreg_s1e_1p25"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1296000>; - }; - - vreg_s2e_0p85: smps2 { - regulator-name = "vreg_s2e_0p85"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1040000>; - }; - }; -}; - -&pm8350_gpios { - vol_up_n: vol-up-n-state { - pins = "gpio6"; - function = "normal"; - power-source = <1>; - input-enable; - }; -}; - -&pon_pwrkey { - status = "okay"; -}; - -&pon_resin { - status = "okay"; - linux,code = ; -}; - -&usb_1 { - qcom,select-utmi-as-pipe-clk; - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "peripheral"; - maximum-speed = "high-speed"; - - phys = <&usb_1_hsphy>; - phy-names = "usb2-phy"; -}; - -&usb_1_hsphy { - status = "okay"; - vdda-pll-supply = <&vreg_l5b_0p88>; - vdda18-supply = <&vreg_l1c_1p8>; - vdda33-supply = <&vreg_l2b_3p07>; -}; - -&ufs_mem_hc { - reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; - - vcc-supply = <&vreg_l7b_2p5>; - vcc-max-microamp = <1100000>; - vccq-supply = <&vreg_l9b_1p2>; - vccq-max-microamp = <1200000>; - vccq2-supply = <&vreg_l9b_1p2>; - vccq2-max-microamp = <1200000>; - vdd-hba-supply = <&vreg_l9b_1p2>; - - status = "okay"; -}; - -&ufs_mem_phy { - status = "okay"; - - vdda-phy-supply = <&vreg_l5b_0p88>; - vdda-pll-supply = <&vreg_l6b_1p2>; -}; From 27f94b71532203b079537180924023a5f636fca1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 8 Jul 2025 12:28:42 +0200 Subject: [PATCH 204/931] arm64: dts: qcom: qcm2290: Disable USB SS bus instances in park mode 2290 was found in the field to also require this quirk, as long & high-bandwidth workloads (e.g. USB ethernet) are consistently able to crash the controller otherwise. The same change has been made for a number of SoCs in [1], but QCM2290 somehow escaped the list (even though the very closely related SM6115 was there). Upon a controller crash, the log would read: xhci-hcd.12.auto: xHCI host not responding to stop endpoint command xhci-hcd.12.auto: xHCI host controller not responding, assume dead xhci-hcd.12.auto: HC died; cleaning up Add snps,parkmode-disable-ss-quirk to the DWC3 instance in order to prevent the aforementioned breakage. [1] https://lore.kernel.org/all/20240704152848.3380602-1-quic_kriskura@quicinc.com/ Cc: stable@vger.kernel.org Reported-by: Rob Clark Fixes: a64a0192b70c ("arm64: dts: qcom: Add initial QCM2290 device tree") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250708-topic-2290_usb-v1-1-661e70a63339@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index eb489d0a684a..77d7ee17ba90 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -1460,6 +1460,7 @@ usb_dwc3: usb@4e00000 { snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; + snps,parkmode-disable-ss-quirk; maximum-speed = "super-speed"; dr_mode = "otg"; usb-role-switch; From 287066b295051729fb08c3cff12ae17c6fe66133 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 27 Jun 2025 15:49:48 +0200 Subject: [PATCH 205/931] ARM: dts: renesas: porter: Fix CAN pin group According to the schematics, the CAN transceiver is connected to pins GP7_3 and GP7_4, which correspond to CAN0 data group B. Fixes: 0768fbad7fba1d27 ("ARM: shmobile: porter: add CAN0 DT support") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/70ad9bc44d6cea92197c42eedcad6b3d0641d26a.1751032025.git.geert+renesas@glider.be --- arch/arm/boot/dts/renesas/r8a7791-porter.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a7791-porter.dts b/arch/arm/boot/dts/renesas/r8a7791-porter.dts index f518eadd8b9c..81b3c5d74e9b 100644 --- a/arch/arm/boot/dts/renesas/r8a7791-porter.dts +++ b/arch/arm/boot/dts/renesas/r8a7791-porter.dts @@ -289,7 +289,7 @@ vin0_pins: vin0 { }; can0_pins: can0 { - groups = "can0_data"; + groups = "can0_data_b"; function = "can0"; }; From c222f860910f82fad2d63d8608f922e9704866c0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 13 Aug 2025 15:37:03 +0200 Subject: [PATCH 206/931] arm64: dts: renesas: rcar-gen3: Increase CANFD clock rates Currently, all R-Car Gen3 .dtsi files configure the CANFD core clocks to 40 MHz, which limits CAN-FD data transfer rates to 4 Mbps. However, all R-Car Gen3 SoCs except for R-Car D3 support CANFD clock rates up to 80 MHz. Now the R-Car CAN-FD driver has gained support for Transceiver Delay Compensation, increase all appropriate CANFD clock rates to the documented maximum, to support data rates up to 8 Mbps. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/d1ca3cd184193084b6de4332d47d0aee1923f6a6.1755090456.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 6ee9cdeb5a3a..c389ebc7e6ce 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -1373,7 +1373,7 @@ canfd: can@e66c0000 { <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index a323ac47ca70..6d039019905d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -1245,7 +1245,7 @@ canfd: can@e66c0000 { <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 49f6d31c5903..1637b534fc68 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1245,7 +1245,7 @@ canfd: can@e66c0000 { <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 136a22ca50b7..353a77187089 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1108,7 +1108,7 @@ canfd: can@e66c0000 { <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 01744496805c..e7a5800bf742 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -568,7 +568,7 @@ canfd: can@e66c0000 { <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index f7e506ad7a21..964aa14f3e65 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -621,7 +621,7 @@ canfd: can@e66c0000 { <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 6b8742045836..e16ede6eb379 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1061,7 +1061,7 @@ canfd: can@e66c0000 { <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; From 57875e1526987524efe5001ad6d198a4b145f54f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 13 Aug 2025 15:37:04 +0200 Subject: [PATCH 207/931] arm64: dts: renesas: rzg2: Increase CANFD clock rates Currently, all RZ/G2 .dtsi files configure the CANFD core clocks to 40 MHz, which limits CAN-FD data transfer rates to 4 Mbps. However, all RZ/G2 SoCs support CANFD clock rates up to 80 MHz. Now the R-Car CAN-FD driver has gained support for Transceiver Delay Compensation, increase all appropriate CANFD clock rates to the documented maximum, to support data rates up to 8 Mbps. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/0dd1c17135707587e9e9d6d68b2eaa1921fbcb7a.1755090456.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index c8b87aed92a3..6b737d91b320 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1186,7 +1186,7 @@ canfd: can@e66c0000 { <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index f2fc2a2035a1..3f15d656215e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1070,7 +1070,7 @@ canfd: can@e66c0000 { <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 530ffd29cf13..55df063cb323 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1029,7 +1029,7 @@ canfd: can@e66c0000 { <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index e4dbda8c34d9..5d730b488d46 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1298,7 +1298,7 @@ canfd: can@e66c0000 { <&can_clk>; clock-names = "fck", "canfd", "can_clk"; assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; - assigned-clock-rates = <40000000>; + assigned-clock-rates = <80000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 914>; status = "disabled"; From 9471de64c9cc15a74e11eaa0c6156fe866ec11c3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 15 Aug 2025 01:34:57 +0200 Subject: [PATCH 208/931] arm64: dts: renesas: sparrow-hawk: Update thermal trip points MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since the Sparrow Hawk has a smaller PCB than the White Hawk, it tends to generate more heat. To prevent potential damage to the board, adjust the temperature trip points. Add four "passive" trip points which increasingly throttle the CPU to prevent overheating. The first trip point at 68°C disables the 1.8 GHz and 1.7 GHz modes and limits the CPU to 1.5 GHz frequency. The second trip point at 72°C disables the 1.5 GHz mode and limits the CPU to 1.0 GHz frequency. The third trip point at 76°C uses thermal-idle to start inserting idle cycles into the CPU instruction stream to cool the CPU cores down. The fourth and last trip point at 80°C disables the 1.0 GHz mode and limits the CPU to 500 MHz frequency. In case the SoC heats up further, in case either of the thermal sensors readings passes the 100°C, a thermal shutdown is triggered to prevent any damage to the hardware. Reviewed-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Signed-off-by: Marek Vasut Link: https://lore.kernel.org/20250814233529.191874-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r8a779g3-sparrow-hawk.dts | 137 ++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts index 1f44005e1a11..75b1b789ae1d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts @@ -38,6 +38,7 @@ /dts-v1/; #include +#include #include "r8a779g3.dtsi" @@ -189,6 +190,41 @@ vcc_sdhi: regulator-vcc-sdhi { }; }; +/* Use thermal-idle cooling for all SoC cores */ +&a76_0 { + #cooling-cells = <2>; + + a76_0_thermal_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; +}; + +&a76_1 { + a76_1_thermal_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; +}; + +&a76_2 { + a76_2_thermal_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; +}; + +&a76_3 { + a76_3_thermal_idle: thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; +}; + &audio_clkin { clock-frequency = <24576000>; }; @@ -801,3 +837,104 @@ &rwdt { &scif_clk { /* X12 */ clock-frequency = <24000000>; }; + +/* THS sensors in SoC, critical temperature trip point is 100C */ +&sensor1_crit { + temperature = <100000>; +}; + +&sensor2_crit { + temperature = <100000>; +}; + +&sensor3_crit { + temperature = <100000>; +}; + +&sensor4_crit { + temperature = <100000>; +}; + +/* THS sensor in SoC near CA76 cores does more progressive cooling. */ +&sensor_thermal_ca76 { + critical-action = "shutdown"; + + cooling-maps { + /* + * The cooling-device minimum and maximum parameters inversely + * match opp-table-0 {} node entries in r8a779g0.dtsi, in other + * words, 0 refers to 1.8 GHz OPP and 4 refers to 500 MHz OPP. + * This is because they refer to cooling levels, where maximum + * cooling level happens at 500 MHz OPP, when the CPU core is + * running slowly and therefore generates least heat. + */ + map0 { + /* At 68C, inhibit 1.7 GHz and 1.8 GHz modes */ + trip = <&sensor3_passive_low>; + cooling-device = <&a76_0 2 4>; + contribution = <128>; + }; + + map1 { + /* At 72C, inhibit 1.5 GHz mode */ + trip = <&sensor3_passive_mid>; + cooling-device = <&a76_0 3 4>; + contribution = <256>; + }; + + map2 { + /* At 76C, start injecting idle states 0..80% of time */ + trip = <&sensor3_passive_hi>; + cooling-device = <&a76_0_thermal_idle 0 80>, + <&a76_1_thermal_idle 0 80>, + <&a76_2_thermal_idle 0 80>, + <&a76_3_thermal_idle 0 80>; + contribution = <512>; + }; + + map3 { + /* At 80C, inhibit 1.0 GHz mode */ + trip = <&sensor3_passive_crit>; + cooling-device = <&a76_0 4 4>; + contribution = <1024>; + }; + }; + + trips { + sensor3_passive_low: sensor3-passive-low { + temperature = <68000>; + hysteresis = <2000>; + type = "passive"; + }; + + sensor3_passive_mid: sensor3-passive-mid { + temperature = <72000>; + hysteresis = <2000>; + type = "passive"; + }; + + sensor3_passive_hi: sensor3-passive-hi { + temperature = <76000>; + hysteresis = <2000>; + type = "passive"; + }; + + sensor3_passive_crit: sensor3-passive-crit { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + }; +}; + +&sensor_thermal_cnn { + critical-action = "shutdown"; +}; + +&sensor_thermal_cr52 { + critical-action = "shutdown"; +}; + +&sensor_thermal_ddr1 { + critical-action = "shutdown"; +}; From 5ae2da6bddebcb2e0331d1cea0db81dd812babe2 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Sun, 13 Jul 2025 16:24:24 +0200 Subject: [PATCH 209/931] ARM: dts: sti: rename SATA phy-names Stick to the documentation and rename both SATA phy-names properties to what is expected. Signed-off-by: Raphael Gallais-Pou Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stih407-family.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/st/stih407-family.dtsi b/arch/arm/boot/dts/st/stih407-family.dtsi index 35a55aef7f4b..3e6a0542e3ae 100644 --- a/arch/arm/boot/dts/st/stih407-family.dtsi +++ b/arch/arm/boot/dts/st/stih407-family.dtsi @@ -669,7 +669,7 @@ sata0: sata@9b20000 { interrupt-names = "hostc"; phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "ahci_phy"; + phy-names = "sata-phy"; resets = <&powerdown STIH407_SATA0_POWERDOWN>, <&softreset STIH407_SATA0_SOFTRESET>, @@ -692,7 +692,7 @@ sata1: sata@9b28000 { interrupt-names = "hostc"; phys = <&phy_port1 PHY_TYPE_SATA>; - phy-names = "ahci_phy"; + phy-names = "sata-phy"; resets = <&powerdown STIH407_SATA1_POWERDOWN>, <&softreset STIH407_SATA1_SOFTRESET>, From cefbc3109932d7a34040b4d87746af1d36567358 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Sun, 13 Jul 2025 15:27:28 +0200 Subject: [PATCH 210/931] dt-bindings: arm: sti: drop B2120 board support B2120 boards are internal boards which never were commercialised. Remove them from bindings. Signed-off-by: Raphael Gallais-Pou Acked-by: Krzysztof Kozlowski Signed-off-by: Patrice Chotard --- Documentation/devicetree/bindings/arm/sti.yaml | 4 ---- 1 file changed, 4 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/sti.yaml b/Documentation/devicetree/bindings/arm/sti.yaml index 842def3e3f2b..177358895fe1 100644 --- a/Documentation/devicetree/bindings/arm/sti.yaml +++ b/Documentation/devicetree/bindings/arm/sti.yaml @@ -14,12 +14,8 @@ properties: const: '/' compatible: oneOf: - - items: - - const: st,stih407-b2120 - - const: st,stih407 - items: - enum: - - st,stih410-b2120 - st,stih410-b2260 - const: st,stih410 - items: From 6bbe133ee8327c0a8faa0673fee839e814bb7672 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Sun, 13 Jul 2025 15:27:29 +0200 Subject: [PATCH 211/931] ARM: sti: removal of stih415/stih416 related entries ST's STiH415 and STiH416 platforms have already been removed since a while. Remove some remaining bits within the mach-sti. Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard Signed-off-by: Raphael Gallais-Pou Signed-off-by: Patrice Chotard --- arch/arm/mach-sti/Kconfig | 20 +------------------- arch/arm/mach-sti/board-dt.c | 2 -- 2 files changed, 1 insertion(+), 21 deletions(-) diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index b3842c971d31..e58699e13e1a 100644 --- a/arch/arm/mach-sti/Kconfig +++ b/arch/arm/mach-sti/Kconfig @@ -19,31 +19,13 @@ menuconfig ARCH_STI select PL310_ERRATA_769419 if CACHE_L2X0 select RESET_CONTROLLER help - Include support for STMicroelectronics' STiH415/416, STiH407/10 and + Include support for STMicroelectronics' STiH407/10 and STiH418 family SoCs using the Device Tree for discovery. More information can be found in Documentation/arch/arm/sti/ and Documentation/devicetree. if ARCH_STI -config SOC_STIH415 - bool "STiH415 STMicroelectronics Consumer Electronics family" - default y - help - This enables support for STMicroelectronics Digital Consumer - Electronics family StiH415 parts, primarily targeted at set-top-box - and other digital audio/video applications using Flattned Device - Trees. - -config SOC_STIH416 - bool "STiH416 STMicroelectronics Consumer Electronics family" - default y - help - This enables support for STMicroelectronics Digital Consumer - Electronics family StiH416 parts, primarily targeted at set-top-box - and other digital audio/video applications using Flattened Device - Trees. - config SOC_STIH407 bool "STiH407 STMicroelectronics Consumer Electronics family" default y diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c index 488084b61b4a..1aaf61184685 100644 --- a/arch/arm/mach-sti/board-dt.c +++ b/arch/arm/mach-sti/board-dt.c @@ -10,8 +10,6 @@ #include "smp.h" static const char *const stih41x_dt_match[] __initconst = { - "st,stih415", - "st,stih416", "st,stih407", "st,stih410", "st,stih418", From dee546e1adefd75acf0d69ddc04dc9627d745986 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Sun, 13 Jul 2025 15:27:30 +0200 Subject: [PATCH 212/931] ARM: sti: drop B2120 board support B2120 boards are internal boards which never were commercialised. Drop them. Signed-off-by: Raphael Gallais-Pou Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/Makefile | 2 - arch/arm/boot/dts/st/stih407-b2120.dts | 27 ---- arch/arm/boot/dts/st/stih407.dtsi | 145 ----------------- arch/arm/boot/dts/st/stih410-b2120.dts | 66 -------- arch/arm/boot/dts/st/stihxxx-b2120.dtsi | 206 ------------------------ 5 files changed, 446 deletions(-) delete mode 100644 arch/arm/boot/dts/st/stih407-b2120.dts delete mode 100644 arch/arm/boot/dts/st/stih407.dtsi delete mode 100644 arch/arm/boot/dts/st/stih410-b2120.dts delete mode 100644 arch/arm/boot/dts/st/stihxxx-b2120.dtsi diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index 66d4f96da5dd..e906bf6ba004 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -13,8 +13,6 @@ dtb-$(CONFIG_ARCH_SPEAR3XX) += \ dtb-$(CONFIG_ARCH_SPEAR6XX) += \ spear600-evb.dtb dtb-$(CONFIG_ARCH_STI) += \ - stih407-b2120.dtb \ - stih410-b2120.dtb \ stih410-b2260.dtb \ stih418-b2199.dtb \ stih418-b2264.dtb diff --git a/arch/arm/boot/dts/st/stih407-b2120.dts b/arch/arm/boot/dts/st/stih407-b2120.dts deleted file mode 100644 index 9c79982ee7ba..000000000000 --- a/arch/arm/boot/dts/st/stih407-b2120.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Giuseppe Cavallaro - */ -/dts-v1/; -#include "stih407.dtsi" -#include "stihxxx-b2120.dtsi" -/ { - model = "STiH407 B2120"; - compatible = "st,stih407-b2120", "st,stih407"; - - chosen { - stdout-path = &sbc_serial0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - aliases { - serial0 = &sbc_serial0; - ethernet0 = ðernet0; - }; - -}; diff --git a/arch/arm/boot/dts/st/stih407.dtsi b/arch/arm/boot/dts/st/stih407.dtsi deleted file mode 100644 index aca43d2bdaad..000000000000 --- a/arch/arm/boot/dts/st/stih407.dtsi +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2015 STMicroelectronics Limited. - * Author: Gabriel Fernandez - */ -#include "stih407-clock.dtsi" -#include "stih407-family.dtsi" -#include -/ { - soc { - sti-display-subsystem@0 { - compatible = "st,sti-display-subsystem"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0 0>; - assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>; - - assigned-clock-parents = <0>, - <0>, - <0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - - assigned-clock-rates = <297000000>, - <108000000>, - <0>, - <400000000>, - <400000000>; - - ranges; - - sti-compositor@9d11000 { - compatible = "st,stih407-compositor"; - reg = <0x9d11000 0x1000>; - - clock-names = "compo_main", - "compo_aux", - "pix_main", - "pix_aux", - "pix_gdp1", - "pix_gdp2", - "pix_gdp3", - "pix_gdp4", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_c0_flexgen CLK_COMPO_DVP>, - <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, - <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, - <&clk_s_d2_flexgen CLK_PIX_GDP1>, - <&clk_s_d2_flexgen CLK_PIX_GDP2>, - <&clk_s_d2_flexgen CLK_PIX_GDP3>, - <&clk_s_d2_flexgen CLK_PIX_GDP4>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - reset-names = "compo-main", "compo-aux"; - resets = <&softreset STIH407_COMPO_SOFTRESET>, - <&softreset STIH407_COMPO_SOFTRESET>; - st,vtg = <&vtg_main>, <&vtg_aux>; - }; - - sti-tvout@8d08000 { - compatible = "st,stih407-tvout"; - reg = <0x8d08000 0x1000>; - reg-names = "tvout-reg"; - reset-names = "tvout"; - resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; - #address-cells = <1>; - #size-cells = <1>; - assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>; - - assigned-clock-parents = <&clk_s_d2_quadfs 0>, - <&clk_tmdsout_hdmi>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d0_quadfs 0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>; - }; - - sti_hdmi: sti-hdmi@8d04000 { - compatible = "st,stih407-hdmi"; - reg = <0x8d04000 0x1000>; - reg-names = "hdmi-reg"; - #sound-dai-cells = <0>; - interrupts = ; - interrupt-names = "irq"; - clock-names = "pix", - "tmds", - "phy", - "audio", - "main_parent", - "aux_parent"; - - clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, - <&clk_s_d2_flexgen CLK_TMDS_HDMI>, - <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, - <&clk_s_d0_flexgen CLK_PCM_0>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - - hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>; - reset-names = "hdmi"; - resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; - ddc = <&hdmiddc>; - }; - - sti-hda@8d02000 { - compatible = "st,stih407-hda"; - reg = <0x8d02000 0x400>, <0x92b0120 0x4>; - reg-names = "hda-reg", "video-dacs-ctrl"; - clock-names = "pix", - "hddac", - "main_parent", - "aux_parent"; - clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, - <&clk_s_d2_flexgen CLK_HDDAC>, - <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/st/stih410-b2120.dts b/arch/arm/boot/dts/st/stih410-b2120.dts deleted file mode 100644 index 538ff98ca1b1..000000000000 --- a/arch/arm/boot/dts/st/stih410-b2120.dts +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Peter Griffin - */ -/dts-v1/; -#include "stih410.dtsi" -#include "stihxxx-b2120.dtsi" -/ { - model = "STiH410 B2120"; - compatible = "st,stih410-b2120", "st,stih410"; - - chosen { - stdout-path = &sbc_serial0; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x80000000>; - }; - - aliases { - serial0 = &sbc_serial0; - ethernet0 = ðernet0; - }; - - usb2_picophy1: phy2 { - status = "okay"; - }; - - usb2_picophy2: phy3 { - status = "okay"; - }; - - soc { - - mmc0: sdhci@9060000 { - max-frequency = <200000000>; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; - }; - - ohci0: usb@9a03c00 { - status = "okay"; - }; - - ehci0: usb@9a03e00 { - status = "okay"; - }; - - ohci1: usb@9a83c00 { - status = "okay"; - }; - - ehci1: usb@9a83e00 { - status = "okay"; - }; - - sti-display-subsystem@0 { - sti-hda@8d02000 { - status = "okay"; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/st/stihxxx-b2120.dtsi b/arch/arm/boot/dts/st/stihxxx-b2120.dtsi deleted file mode 100644 index 8d9a2dfa76f1..000000000000 --- a/arch/arm/boot/dts/st/stihxxx-b2120.dtsi +++ /dev/null @@ -1,206 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics (R&D) Limited. - * Author: Giuseppe Cavallaro - */ -#include -#include -#include -/ { - leds { - compatible = "gpio-leds"; - led-red { - label = "Front Panel LED"; - gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - led-green { - gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; - - sound: sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "STI-B2120"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - - simple-audio-card,dai-link@0 { - reg = <0>; - /* HDMI */ - format = "i2s"; - mclk-fs = <128>; - cpu { - sound-dai = <&sti_uni_player0>; - }; - - codec { - sound-dai = <&sti_hdmi>; - }; - }; - - simple-audio-card,dai-link@1 { - reg = <1>; - /* DAC */ - format = "i2s"; - mclk-fs = <256>; - frame-inversion; - cpu { - sound-dai = <&sti_uni_player2>; - }; - - codec { - sound-dai = <&sti_sasg_codec 1>; - }; - }; - - simple-audio-card,dai-link@2 { - reg = <2>; - /* SPDIF */ - format = "left_j"; - mclk-fs = <128>; - cpu { - sound-dai = <&sti_uni_player3>; - }; - - codec { - sound-dai = <&sti_sasg_codec 0>; - }; - }; - }; - - miphy28lp_phy: miphy28lp { - - phy_port0: port@9b22000 { - st,osc-rdy; - }; - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - - soc { - sbc_serial0: serial@9530000 { - status = "okay"; - }; - - pwm0: pwm@9810000 { - status = "okay"; - }; - - pwm1: pwm@9510000 { - status = "okay"; - }; - - ssc2: i2c@9842000 { - status = "okay"; - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - - ssc3: i2c@9843000 { - status = "okay"; - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - - i2c@9844000 { - status = "okay"; - }; - - i2c@9845000 { - status = "okay"; - }; - - i2c@9540000 { - status = "okay"; - }; - - mmc0: sdhci@9060000 { - non-removable; - status = "okay"; - }; - - mmc1: sdhci@9080000 { - status = "okay"; - }; - - /* SSC11 to HDMI */ - hdmiddc: i2c@9541000 { - status = "okay"; - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - - st_dwc3: dwc3@8f94000 { - status = "okay"; - }; - - ethernet0: dwmac@9630000 { - st,tx-retime-src = "clkgen"; - status = "okay"; - phy-mode = "rgmii"; - fixed-link = <0 1 1000 0 0>; - }; - - demux@8a20000 { - compatible = "st,stih407-c8sectpfe"; - status = "okay"; - reg = <0x08a20000 0x10000>, - <0x08a00000 0x4000>; - reg-names = "c8sectpfe", "c8sectpfe-ram"; - interrupts = , - ; - interrupt-names = "c8sectpfe-error-irq", - "c8sectpfe-idle-irq"; - pinctrl-0 = <&pinctrl_tsin0_serial>; - pinctrl-1 = <&pinctrl_tsin0_parallel>; - pinctrl-2 = <&pinctrl_tsin3_serial>; - pinctrl-3 = <&pinctrl_tsin4_serial_alt3>; - pinctrl-4 = <&pinctrl_tsin5_serial_alt1>; - pinctrl-names = "tsin0-serial", - "tsin0-parallel", - "tsin3-serial", - "tsin4-serial", - "tsin5-serial"; - clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>; - clock-names = "c8sectpfe"; - - /* tsin0 is TSA on NIMA */ - tsin0: port { - tsin-num = <0>; - serial-not-parallel; - i2c-bus = <&ssc2>; - reset-gpios = <&pio15 4 GPIO_ACTIVE_LOW>; - dvb-card = ; - }; - }; - - sti_uni_player0: sti-uni-player@8d80000 { - status = "okay"; - }; - - sti_uni_player2: sti-uni-player@8d82000 { - status = "okay"; - }; - - sti_uni_player3: sti-uni-player@8d85000 { - status = "okay"; - }; - - syscfg_core: core-syscfg@92b0000 { - sti_sasg_codec: sti-sasg-codec { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif_out>; - }; - }; - }; -}; From cd09e96fbac54fa962750c8cecea4d3d5e7e72ae Mon Sep 17 00:00:00 2001 From: Quynh Nguyen Date: Thu, 7 Aug 2025 17:14:35 +0200 Subject: [PATCH 213/931] arm64: dts: renesas: r9a08g045: Add I3C node Add the I3C node to RZ/G3S SoC DTSI. Signed-off-by: Quynh Nguyen [wsa: adapted to upstream driver, moved bus frequencies to board file] Signed-off-by: Wolfram Sang Reviewed-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250807151434.5241-7-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 0364f89776e6..16e6ac614417 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -272,6 +272,42 @@ channel@8 { }; }; + i3c: i3c@1005b000 { + compatible = "renesas,r9a08g045-i3c"; + reg = <0 0x1005b000 0 0x1000>; + clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>, + <&cpg CPG_MOD R9A08G045_I3C_TCLK>; + clock-names = "pclk", "tclk"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ierr", "terr", "abort", "resp", + "cmd", "ibi", "rx", "tx", "rcv", + "st", "sp", "tend", "nack", "al", + "tmo", "wu", "exit"; + resets = <&cpg R9A08G045_I3C_PRESETN>, + <&cpg R9A08G045_I3C_TRESETN>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + vbattb: clock-controller@1005c000 { compatible = "renesas,r9a08g045-vbattb"; reg = <0 0x1005c000 0 0x1000>; From 6fb1e70e7a918969573bc5258975456bb7165cc0 Mon Sep 17 00:00:00 2001 From: Tommaso Merciai Date: Thu, 7 Aug 2025 17:14:36 +0200 Subject: [PATCH 214/931] arm64: dts: renesas: r9a09g047: Add I3C node Add the I3C node to RZ/G3E SoC DTSI. Signed-off-by: Tommaso Merciai Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250807151434.5241-8-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index eeccd1345f71..e5b24e46d645 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -492,6 +492,41 @@ scif0: serial@11c01400 { status = "disabled"; }; + i3c: i3c@12400000 { + compatible = "renesas,r9a09g047-i3c"; + reg = <0 0x12400000 0 0x10000>; + clocks = <&cpg CPG_MOD 0x91>, + <&cpg CPG_MOD 0x92>, + <&cpg CPG_MOD 0x90>; + clock-names = "pclk", "tclk", "pclkrw"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ierr", "terr", "abort", "resp", + "cmd", "ibi", "rx", "tx", "rcv", + "st", "sp", "tend", "nack", "al", + "tmo", "wu"; + resets = <&cpg 0x96>, <&cpg 0x97>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + canfd: can@12440000 { compatible = "renesas,r9a09g047-canfd"; reg = <0 0x12440000 0 0x40000>; From be5d60d94b982d46a734750d93624bd85a1c7089 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 12 Aug 2025 21:03:32 +0100 Subject: [PATCH 215/931] arm64: dts: renesas: r9a09g077: Add DT nodes for SCI channels 1-5 The RZ/T2H SoC exposes six SCI controllers; sci0 was already present in the SoC DTSI. Add the remaining SCI nodes (sci1-sci5). Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250812200344.3253781-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index b16fd9259d8d..8ee88b8e8f33 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -90,6 +90,76 @@ sci0: serial@80005000 { status = "disabled"; }; + sci1: serial@80005400 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x80005400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci2: serial@80005800 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x80005800 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci3: serial@80005c00 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x80005c00 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci4: serial@80006000 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x80006000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci5: serial@81005000 { + compatible = "renesas,r9a09g077-rsci"; + reg = <0 0x81005000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + i2c0: i2c@80088000 { compatible = "renesas,riic-r9a09g077"; reg = <0 0x80088000 0 0x400>; From 41e194978510a9910be2ed7b4d8b4edb61671a90 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 12 Aug 2025 21:03:33 +0100 Subject: [PATCH 216/931] arm64: dts: renesas: r9a09g087: Add DT nodes for SCI channels 1-5 The RZ/N2H SoC exposes six SCI controllers; sci0 was already present in the SoC DTSI. Add the remaining SCI nodes (sci1-sci5). Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250812200344.3253781-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 70 ++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index 4da21199d22e..7dcaee711486 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -90,6 +90,76 @@ sci0: serial@80005000 { status = "disabled"; }; + sci1: serial@80005400 { + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; + reg = <0 0x80005400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci2: serial@80005800 { + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; + reg = <0 0x80005800 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci3: serial@80005c00 { + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; + reg = <0 0x80005c00 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci4: serial@80006000 { + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; + reg = <0 0x80006000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + + sci5: serial@81005000 { + compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; + reg = <0 0x81005000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + clock-names = "operation", "bus"; + power-domains = <&cpg>; + status = "disabled"; + }; + i2c0: i2c@80088000 { compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; reg = <0 0x80088000 0 0x400>; From 98340bf91dd9e8f08f25364edd8819ee903c1b84 Mon Sep 17 00:00:00 2001 From: Thierry Bultel Date: Tue, 12 Aug 2025 21:03:34 +0100 Subject: [PATCH 217/931] arm64: dts: renesas: r9a09g077: Add pinctrl node Add pinctrl node to RZ/T2H ("R9A09G077") SoC DTSI. Signed-off-by: Thierry Bultel Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250812200344.3253781-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 8ee88b8e8f33..0929ce2db05c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -216,6 +216,19 @@ cpg: clock-controller@80280000 { #power-domain-cells = <0>; }; + pinctrl: pinctrl@802c0000 { + compatible = "renesas,r9a09g077-pinctrl"; + reg = <0 0x802c0000 0 0x10000>, + <0 0x812c0000 0 0x10000>, + <0 0x802b0000 0 0x10000>; + reg-names = "nsr", "srs", "srn"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 288>; + power-domains = <&cpg>; + }; + gic: interrupt-controller@83000000 { compatible = "arm,gic-v3"; reg = <0x0 0x83000000 0 0x40000>, From 6f21672c42fc432d69d8fd51e5d8cea145d5be5b Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 12 Aug 2025 21:03:39 +0100 Subject: [PATCH 218/931] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Enable I2C0 and I2C1 support Enable I2C0 and I2C1 on the RZ/T2H evaluation board. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250812200344.3253781-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 36 +++++++++++++++++++ .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 2 ++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 486584fefead..51ea295b3241 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include + #include "r9a09g077m44.dtsi" #include "rzt2h-n2h-evk-common.dtsi" @@ -14,3 +16,37 @@ / { model = "Renesas RZ/T2H EVK Board based on r9a09g077m44"; compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077"; }; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&pinctrl { + /* + * I2C0 Pin Configuration: + * ------------------------ + * Signal | Pin | SW6 + * -------|---------|-------------- + * SCL | P23_3 | 7: ON, 8: OFF + * SDA | P23_4 | 9: ON, 10: OFF + */ + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux = , /* SDA */ + ; /* SCL */ + }; +}; diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 5f17996bcd6b..263509cc3dc4 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -7,6 +7,8 @@ / { aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; serial0 = &sci0; }; From cec6e40a02ef66e28208dc808cd28cce418efc1d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:15:50 +0200 Subject: [PATCH 219/931] riscv: dts: microchip: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts index 47cf693beb68..55e30f3636df 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts @@ -88,7 +88,7 @@ &gpio2 { <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>; - ngpios=<32>; + ngpios = <32>; gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2", "P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5", "P8_PIN9_USER_LED_6", "P8_PIN10_USER_LED_7", "P8_PIN11_USER_LED_8", From 481ee0fcbb9a0f0706d6d29de9570d1048aff631 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Tue, 29 Jul 2025 07:11:35 -0700 Subject: [PATCH 220/931] riscv: dts: starfive: jh7110-common: drop no-sdio property from mmc1 Relax no-sdio restriction on mmc1 for jh7110 boards. Property was introduced for StarFive VisionFive2 dts to configure mmc1 for SD Card but this is not necessary, the restriction is only needed to block use of commands that would cause a device to malfunction. Signed-off-by: E Shattow Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index 2eaf01775ef5..a315113840e5 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -299,7 +299,6 @@ &mmc1 { assigned-clock-rates = <50000000>; bus-width = <4>; bootph-pre-ram; - no-sdio; no-mmc; cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; disable-wp; From 36def5f2b958113b9009144fb54b0cee2c11afb5 Mon Sep 17 00:00:00 2001 From: Christoph Stoidner Date: Sat, 24 May 2025 13:23:15 +0200 Subject: [PATCH 221/931] arm64: dts: freescale: imx93-phycore-som: Delay the phy reset by a gpio According to the datasheet the phy needs to be held in reset until the reference clock got stable. Even though no issue was observed, fix this as the software should always comply with the specification. Use gpio4 23, which is connected to the phy reset pin. On the same pin RX_ER was used before, but this signal is optional and can be dropped. Note: This comes into effect with the phyCOREs SOM hardware revision 4. In revisions before, this gpio is not connected, and the phy reset is managed with the global hardware reset circuit. Signed-off-by: Christoph Stoidner Reviewed-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index c6f5aa38ebf9..89552ae70660 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -85,6 +85,8 @@ mdio: mdio { ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; + reset-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; + reset-assert-us = <30>; }; }; }; @@ -206,14 +208,17 @@ pinctrl_fec: fecgrp { fsl,pins = < MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502 - MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e - MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e - MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe + /* the three pins below are connected to PHYs straps, + * that is what the pull-up/down setting is for. + */ + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x37e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x37e MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e + MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e >; }; From 566c269873c642856bceced2add800d2ce8b8c94 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Goran=20Ra=C4=91enovi=C4=87?= Date: Wed, 16 Jul 2025 17:48:05 +0200 Subject: [PATCH 222/931] dt-bindings: arm: imx8mp: Add Ultratronik Ultra-MACH SBC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document the Ultratronik Ultra-MACH SBC, based on the NXP i.MX8MP SoC. This board is manufactured by Ultratronik GmbH and uses the compatible string "ux,imx8mp-ultra-mach-sbc". Acked-by: Krzysztof Kozlowski Signed-off-by: Goran Rađenović Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index a3e9f9e0735a..839f428c9f75 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1112,6 +1112,7 @@ properties: - skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel - skov,imx8mp-skov-revc-bd500 # SKOV i.MX8MP climate control with LED frontplate - skov,imx8mp-skov-revc-tian-g07017 # SKOV i.MX8MP climate control with 7" panel + - ultratronik,imx8mp-ultra-mach-sbc # Ultratronik SBC i.MX8MP based board - ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Board - const: fsl,imx8mp From e0a4a651f7c8f274be0a937e8ac31c782c4af7ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Goran=20Ra=C4=91enovi=C4=87?= Date: Wed, 16 Jul 2025 17:48:04 +0200 Subject: [PATCH 223/931] MAINTAINERS: Add i.MX8MP Ultra-MACH SBC to ULTRATRONIK BOARD SUPPORT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The i.MX8MP-based Ultra-MACH SBC is supported by Ultratronik, and its device tree has been added under arch/arm64/boot/dts/freescale/. To ensure proper maintainer coverage and notification of relevant changes, add the imx8mp-ultra-mach-sbc.dts file to the existing ULTRATRONIK BOARD SUPPORT section. This follows the established pattern already used for the STM32MP157C- based Ultra-FLY SBC. Signed-off-by: Goran Rađenović Signed-off-by: Shawn Guo --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index fe168477caa4..e8ab36b47967 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25825,6 +25825,7 @@ M: Goran Rađenović M: Börge Strümpfel S: Maintained F: arch/arm/boot/dts/st/stm32mp157c-ultra-fly-sbc.dts +F: arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts UNICODE SUBSYSTEM M: Gabriel Krisman Bertazi From d1c1400bd3b8b436df3bc49d6b420b3184f7dda4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Goran=20Ra=C4=91enovi=C4=87?= Date: Wed, 16 Jul 2025 17:48:06 +0200 Subject: [PATCH 224/931] arm64: dts: imx8mp: Add initial support for Ultratronik imx8mp-ultra-mach-sbc board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial device tree support for the Ultratronik Ultra-MACH SBC based on the NXP i.MX8M Plus SoC with 2GB LPDDR4. The board features: - 1 x USB 2.0 Host - 1 x USB 2.0 via USB-C - Debug UART + 1 x UART + 1 x USART - SD card and eMMC support - 2 x Ethernet (RJ45) - HDMI This initial DTS enables basic board support for booting via SD card or eMMC. Signed-off-by: Goran Rađenović Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mp-ultra-mach-sbc.dts | 907 ++++++++++++++++++ 2 files changed, 908 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 23535ed47631..6ee4bd67802c 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -237,6 +237,7 @@ imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17-dtbs += imx8mp-tx8p-ml81-modu dtb-$(CONFIG_ARCH_MXC) += imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-ultra-mach-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts new file mode 100644 index 000000000000..9ecec1a41878 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts @@ -0,0 +1,907 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Ultratronik + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" + +/ { + model = "NXP i.MX8MPlus Ultratronik MMI_A53 board"; + compatible = "ultratronik,imx8mp-ultra-mach-sbc", "fsl,imx8mp"; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + rtc0 = &hwrtc; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart2; + }; + + gpio-sbu-mux { + compatible = "nxp,cbdtu02043", "gpio-sbu-mux"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sbu_mux>; + select-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-0 { + gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* Wakeup */ + label = "Wakeup"; + linux,code = ; + pinctrl-0 = <&pinctrl_gpio_key_wakeup>; + pinctrl-names = "default"; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led1 { + label = "red"; + gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led2 { + label = "green"; + gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led3 { + label = "yellow"; + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_usba_vbus: regulator-usba-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + regulator-name = "usb-A-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + slb9670: tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <32000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_slb9670>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 8 GPIO_ACTIVE_LOW>, + <&gpio1 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + nfc-transceiver@1 { + compatible = "st,st95hf"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + spi-max-frequency = <100000>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + enable-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x2>; + interrupt-parent = <&gpio4>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "#TPM_IRQ", "GPIO1", "", "#PMIC_INT", + "SD2_VSEL", "#TOUCH_IRQ", "#NFC_INT_I", "#NFC_INT", + "#SPI2_CS2", "#SPI2_CS3", "#RTS4", "", + "USB_PWR", "GPIO2", "GPIO3", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "#SD2_CD", "", "", "", + "", "", "", "", "#USB-C_EN", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "DISP_POW", "GPIO4", + "#", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "BKL_POW", "#ETH1_INT", "#TPM_RES", "#PCAP_RES", + "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "#ETH0_INT", "#USB-C_ALERT", + "#USB-C_SEL", "", "", "", + "LED_RED", "LED_GREEN", "LED_YELLOW", "#WAKEUP", + "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "#SPI1_CS", "", "", "", "#SPI2_CS1", "", "", + "", "", "", "", "ENA_KAM", "ENA_LED", "", "", + "", "", "", "", "", "", "", ""; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + ddc-i2c-bus = <&i2c5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + + /* + * i.MX 8M Plus Data Sheet for Consumer Products + * 3.1.4 Operating ranges + * MIMX8ML8DVNLZAB + */ + regulators { + buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { /* VDD_ARM */ + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4 { /* +3V3 */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5: BUCK5 { /* +1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6: BUCK6 { /* DRAM_1V1 */ + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1: LDO1 { /* NVCC_SNVS_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3: LDO3 { /* VDDA_1P8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4: LDO4 { /* ENET_2V5 */ + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo5: LDO5 { /* NVCC_SD2 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + crypto@35 { + compatible = "atmel,atecc508a"; + reg = <0x35>; + }; + + eeprom@50 { + compatible = "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + hwrtc: rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + epson,vdet-disable; + trickle-diode-disable; + }; + + tcpc@52 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x52>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5110>; + interrupt-parent = <&gpio4>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c5 { /* HDMI EDID bus */ + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&lcdif3 { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + /* system console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + /* expansion port serial connection */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + +&usb3_phy1 { + vbus-supply = <®_usba_vbus>; + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + snps,hsphy_interface = "utmi"; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <&ldo5>; + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + vmmc-supply = <&buck4>; + vqmmc-supply = <&buck5>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_ecspi1_cs: ecspi1-cs-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 /* #SPI1_CS */ + >; + }; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2-cs-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 /* #SPI2_CS */ + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 /* #SPI2_CS2 */ + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40 /* #SPI2_CS3 */ + >; + }; + + pinctrl_ecspi2: ecspi2-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + >; + }; + + pinctrl_eqos: eqos-grp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x0 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x0 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10 /* #ETH0_INT */ + >; + }; + + pinctrl_fec: fec-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x0 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x0 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x10 /* #ETH1_INT */ + >; + }; + + pinctrl_flexcan1: flexcan1-grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_gpio_key_wakeup: gpio-key-wakeup-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40 /* #WAKEUP */ + >; + }; + + pinctrl_gpio_leds: gpio-leds-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x40 /* LED_RED */ + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40 /* LED_GREEN */ + MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40 /* LED_YELLOW */ + >; + }; + + pinctrl_hdmi: hdmi-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154 + >; + }; + + pinctrl_hog: hog-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x40 /* GPIO1 */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40 /* GPIO2 */ + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40 /* GPIO3 */ + MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40 /* GPIO4 */ + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x40 /* ENA_KAM */ + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x40 /* ENA_LED */ + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40 /* #PCAP_RES */ + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40 /* #RTS4 */ + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c0 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c0 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0xc0 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0xc0 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c0 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c0 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0xc0 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0xc0 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0xc2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0xc2 + >; + }; + + pinctrl_i2c5: i2c5-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x400000c4 + MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x400000c4 + >; + }; + + pinctrl_i2c5_gpio: i2c5-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0xc4 + MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0xc4 + >; + }; + + pinctrl_nfc: nfc-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40 /* NFC_INT_I */ + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40 /* NFC_INT */ + >; + }; + + pinctrl_pmic: pmic-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40 /* #PMIC_INT */ + >; + }; + + pinctrl_ptn5110: ptn5110-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 /* #USB-C_ALERT */ + >; + }; + + pinctrl_pwm1: pwm1-grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116 /* EXT_PWM */ + >; + }; + + pinctrl_reg_usdhc2_vmmc: reg-usdhc2-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_sbu_mux: sbu-mux-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 /* #USB-C_SEL */ + MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x16 /* #USB-C_EN */ + >; + }; + + pinctrl_slb9670: slb9670-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x40 /* #TPM_IRQ */ + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40 /* #TPM_RES */ + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x40 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x40 + >; + }; + + pinctrl_uart4: uart4-grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x40 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x40 + >; + }; + + pinctrl_usb1: usb1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x40 /* USB_PWR */ + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 /* SD2_VSEL */ + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 /* SD2_VSEL */ + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 /* SD2_VSEL */ + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x40 /* #SD3_RESET */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x192 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d2 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x192 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 /* #WDOG */ + >; + }; +}; From 21179eae56de418ea360e31f1b69f66fc16aa4e3 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Mon, 14 Jul 2025 12:36:24 +0200 Subject: [PATCH 225/931] arm64: dts: freescale: imx93-phyboard-nash: Add current sense amplifier There is a current sensing circuitry on the phyBOARD-Nash-i.MX93 capable of measuring input current consumption of the phyCORE-i.MX93 SoM @ 3.3V. Circuity consists of MAX4372 current-sense amplifier (50V/V) with two 70 mOhm shunts resistors in parallel configuration (effective R = 35 mOhm) connected to the SoC internal 12-bit ADC channel #1 (Vref = 1.8V) via voltage divider with ratio of 1/2. This results in a current scaling factor of 0.502232142 mA/LSB. Signed-off-by: Primoz Fiser Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts index 475913cf0cb9..71a0e9f270af 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts @@ -27,6 +27,14 @@ chosen { stdout-path = &lpuart1; }; + current-sense { + compatible = "current-sense-amplifier"; + io-channels = <&adc1 1>; + sense-gain-div = <2>; + sense-gain-mult = <50>; + sense-resistor-micro-ohms = <35000>; + }; + flexcan1_tc: can-phy0 { compatible = "ti,tcan1042"; #phy-cells = <0>; From bc9dc8de130e3fd208cf489788ecb998069ce6bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= Date: Wed, 9 Jul 2025 09:32:44 +0200 Subject: [PATCH 226/931] ARM: dts: imx6-display5: Replace license text comment with SPDX identifier MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace verbatim license text with a `SPDX-License-Identifier`. The comment header mis-attributes this license to be "X11", but the license text does not include the last line "Except as contained in this notice, the name of the X Consortium shall not be used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from the X Consortium.". Therefore, this license is actually equivalent to the SPDX "MIT" license (confirmed by text diffing). Cc: Lukasz Majewski Signed-off-by: Bence Csókás Acked-by: Lukasz Majewski Signed-off-by: Shawn Guo --- .../imx6q-display5-tianma-tm070-1280x768.dts | 33 +------------------ arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi | 33 +------------------ 2 files changed, 2 insertions(+), 64 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-display5-tianma-tm070-1280x768.dts b/arch/arm/boot/dts/nxp/imx/imx6q-display5-tianma-tm070-1280x768.dts index 16658b76fc4e..059750270fc4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-display5-tianma-tm070-1280x768.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-display5-tianma-tm070-1280x768.dts @@ -1,38 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) /* * Copyright 2017 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi index 4ab31f2217cd..4e448b4810f2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi @@ -1,38 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) /* * Copyright 2017 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; From ae95807b00e1639b3f6ab94eb2cd887266e4f766 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 28 Jul 2025 01:58:11 +0200 Subject: [PATCH 227/931] arm64: dts: renesas: sparrow-hawk: Invert microSD voltage selector on EVTB1 Invert the polarity of microSD voltage selector on Retronix R-Car V4H Sparrow Hawk board. The voltage selector was not populated on prototype EVTA1 boards, and is implemented slightly different on EVTB1 boards. As the EVTA1 boards are from a limited run and generally not available, update the DT to make it compatible with EVTB1 microSD voltage selector. Fixes: a719915e76f2 ("arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support") Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250727235905.290427-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts index 75b1b789ae1d..33c6c2a5c2c5 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts @@ -186,7 +186,7 @@ vcc_sdhi: regulator-vcc-sdhi { regulator-max-microvolt = <3300000>; gpios = <&gpio8 13 GPIO_ACTIVE_HIGH>; gpios-states = <1>; - states = <3300000 0>, <1800000 1>; + states = <1800000 0>, <3300000 1>; }; }; From 7d1e3aa2826a22f68f1850c31ac96348272fa356 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 6 Aug 2025 21:28:04 +0200 Subject: [PATCH 228/931] arm64: dts: renesas: sparrow-hawk: Set VDDQ18_25_AVB voltage on EVTB1 The Retronix R-Car V4H Sparrow Hawk EVTB1 uses 1V8 IO voltage supply for VDDQ18_25_AVB power rail. Update the AVB0 pinmux to reflect the change in IO voltage. Since the VDDQ18_25_AVB power rail is shared, all four AVB0, AVB1, AVB2, TSN0 PFC/GPIO POC[7..4] registers have to be configured the same way. As the EVTA1 boards are from a limited run and generally not available, update the DT to make it compatible with EVTB1 IO voltage settings. Fixes: a719915e76f2 ("arm64: dts: renesas: r8a779g3: Add Retronix R-Car V4H Sparrow Hawk board support") Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250806192821.133302-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts index 33c6c2a5c2c5..1da8e476b219 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts @@ -592,6 +592,10 @@ pins-mii { drive-strength = <21>; }; + pins-vddq18-25-avb { + pins = "PIN_VDDQ_AVB0", "PIN_VDDQ_AVB1", "PIN_VDDQ_AVB2", "PIN_VDDQ_TSN0"; + power-source = <1800>; + }; }; /* Page 28 / CANFD_IF */ From 115b557b6f61ca279a4754b20b8686039fdb5234 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:16:20 +0200 Subject: [PATCH 229/931] arm64: dts: renesas: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250819131619.86396-2-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 16 ++++++++-------- .../boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts | 2 +- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 16 ++++++++-------- .../boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts | 2 +- .../boot/dts/renesas/r9a09g057h48-kakip.dts | 2 +- 5 files changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 10d3b9727ea5..50a3d42d192c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -735,10 +735,10 @@ eth0: ethernet@15c30000 { "rx-queue-0", "rx-queue-1", "rx-queue-2", "rx-queue-3", "tx-queue-0", "tx-queue-1", "tx-queue-2", "tx-queue-3"; - clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, - <&cpg CPG_CORE R9A09G056_GBETH_0_CLK_PTP_REF_I>, - <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, - <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; + clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, + <&cpg CPG_CORE R9A09G056_GBETH_0_CLK_PTP_REF_I>, + <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, + <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "rx", "tx-180", "rx-180"; resets = <&cpg 0xb0>; @@ -836,10 +836,10 @@ eth1: ethernet@15c40000 { "rx-queue-0", "rx-queue-1", "rx-queue-2", "rx-queue-3", "tx-queue-0", "tx-queue-1", "tx-queue-2", "tx-queue-3"; - clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, - <&cpg CPG_CORE R9A09G056_GBETH_1_CLK_PTP_REF_I>, - <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, - <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; + clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, + <&cpg CPG_CORE R9A09G056_GBETH_1_CLK_PTP_REF_I>, + <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, + <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "rx", "tx-180", "rx-180"; resets = <&cpg 0xb1>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index 03aeea781186..066e66b5d51a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -334,7 +334,7 @@ sd1-dat-cmd { usb20_pins: usb20 { ovc { - pinmux = ; /* OVC */ + pinmux = ; /* OVC */ }; vbus { diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 6d0c6449b9ff..e66f5654f2ab 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -1083,10 +1083,10 @@ eth0: ethernet@15c30000 { "rx-queue-0", "rx-queue-1", "rx-queue-2", "rx-queue-3", "tx-queue-0", "tx-queue-1", "tx-queue-2", "tx-queue-3"; - clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, - <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>, - <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, - <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; + clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, + <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>, + <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, + <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "rx", "tx-180", "rx-180"; resets = <&cpg 0xb0>; @@ -1184,10 +1184,10 @@ eth1: ethernet@15c40000 { "rx-queue-0", "rx-queue-1", "rx-queue-2", "rx-queue-3", "tx-queue-0", "tx-queue-1", "tx-queue-2", "tx-queue-3"; - clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, - <&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>, - <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, - <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; + clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, + <&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>, + <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, + <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "rx", "tx-180", "rx-180"; resets = <&cpg 0xb1>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 5c3f4e471e3d..5c06bce3d5b4 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -353,7 +353,7 @@ sd1_cd { usb20_pins: usb20 { ovc { - pinmux = ; /* OVC */ + pinmux = ; /* OVC */ }; vbus { diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts index f6f2cb7d2d25..adf3ab8aef2b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts @@ -84,7 +84,7 @@ &ostm7 { &pinctrl { scif_pins: scif { - pins = "SCIF_RXD", "SCIF_TXD"; + pins = "SCIF_RXD", "SCIF_TXD"; }; sd0-pwr-en-hog { From 4184f0190792aea06553af963741a24cc9b47689 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 13 Aug 2025 01:59:27 +0800 Subject: [PATCH 230/931] arm64: dts: allwinner: a527: cubie-a5e: Add LEDs The Radxa Cubie A5E has a 3-color LED. The green and blue LEDs are wired to GPIO pins on the SoC, and the green one is lit by default to serve as a power indicator. The red LED is wired to the M.2 slot. Add device nodes for the green and blue LEDs. A default "heartbeat" trigger is set for the green power LED, though in practice it might be better if it were inverted, i.e. lit most of the time. Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250812175927.2199219-1-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 553ad774ed13..70d439bc845c 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -6,6 +6,7 @@ #include "sun55i-a523.dtsi" #include +#include / { model = "Radxa Cubie A5E"; @@ -27,6 +28,24 @@ ext_osc32k: ext-osc32k-clk { clock-output-names = "ext_osc32k"; }; + leds { + compatible = "gpio-leds"; + + power-led { + function = LED_FUNCTION_POWER; + color = ; + gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + use-led { + function = LED_FUNCTION_ACTIVITY; + color = ; + gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ + }; + }; + reg_vcc5v: vcc5v { /* board wide 5V supply from the USB-C connector */ compatible = "regulator-fixed"; From 74403d260a4b5c12c15c1862c3df5b17b803549a Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Mon, 14 Jul 2025 11:13:45 -0400 Subject: [PATCH 231/931] dt-bindings: arm: fsl: add i.MX8ULP EVK9 board Add DT compatible string for the i.MX8ULP EVK9 board. Signed-off-by: Laurentiu Mihalcea Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 839f428c9f75..e21758546d13 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1383,6 +1383,7 @@ properties: - description: i.MX8ULP based Boards items: - enum: + - fsl,imx8ulp-9x9-evk # i.MX8ULP EVK9 Board - fsl,imx8ulp-evk # i.MX8ULP EVK Board - const: fsl,imx8ulp From 5bf5090bbfb611b30d3d8d896853640c946833ed Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Mon, 14 Jul 2025 11:13:46 -0400 Subject: [PATCH 232/931] arm64: dts: imx: add dts for the imx8ulp evk9 board Add DTS for the i.MX8ULP EVK9 board. Some notable differences from the i.MX8ULP EVK board include: 1) M.2 header uses SAI6 instead of SAI5. 2) Ethernet transceiver chip (KSZ8081RNB) uses different pads. 3) USB0 ID/OC signals are tied to different pads. 4) USB1 ID/OC signals are tied to different pads. 5) EVK9 board integrates the 9.4x9.4mm SoC package, while the EVK board integrates the 15x15mm package. Signed-off-by: Laurentiu Mihalcea Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8ulp-9x9-evk.dts | 69 +++++++++++++++++++ 2 files changed, 70 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 6ee4bd67802c..dcc520355c99 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -333,6 +333,7 @@ dtb-${CONFIG_ARCH_MXC} += imx8qxp-mek-ov5640-csi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts new file mode 100644 index 000000000000..5497e3d78136 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include "imx8ulp-evk.dts" + +/ { + model = "NXP i.MX8ULP EVK9"; + compatible = "fsl,imx8ulp-9x9-evk", "fsl,imx8ulp"; +}; + +&btcpu { + sound-dai = <&sai6>; +}; + +&iomuxc1 { + pinctrl_sai6: sai6grp { + fsl,pins = < + MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x43 + MX8ULP_PAD_PTE11__I2S6_TX_FS 0x43 + MX8ULP_PAD_PTE14__I2S6_TXD2 0x43 + MX8ULP_PAD_PTE6__I2S6_RXD0 0x43 + >; + }; +}; + +&pinctrl_enet { + fsl,pins = < + MX8ULP_PAD_PTF9__ENET0_MDC 0x43 + MX8ULP_PAD_PTF8__ENET0_MDIO 0x43 + MX8ULP_PAD_PTF5__ENET0_RXER 0x43 + MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x43 + MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 + MX8ULP_PAD_PTF0__ENET0_RXD1 0x43 + MX8ULP_PAD_PTF4__ENET0_TXEN 0x43 + MX8ULP_PAD_PTF3__ENET0_TXD0 0x43 + MX8ULP_PAD_PTF2__ENET0_TXD1 0x43 + MX8ULP_PAD_PTF7__ENET0_REFCLK 0x43 + MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 + >; +}; + +&pinctrl_usb1 { + fsl,pins = < + MX8ULP_PAD_PTE16__USB0_ID 0x10003 + MX8ULP_PAD_PTE18__USB0_OC 0x10003 + >; +}; + +&pinctrl_usb2 { + fsl,pins = < + MX8ULP_PAD_PTD23__USB1_ID 0x10003 + MX8ULP_PAD_PTE20__USB1_OC 0x10003 + >; +}; + +&sai6 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai6>; + pinctrl-1 = <&pinctrl_sai6>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>, <&cgc2 IMX8ULP_CLK_SAI6_SEL>; + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>; + assigned-clock-rates = <12288000>; + fsl,dataline = <1 0x01 0x04>; + status = "okay"; +}; From 9db115e231a665e82429ea63e2efda4abd4390fe Mon Sep 17 00:00:00 2001 From: Wolfgang Birkner Date: Tue, 15 Jul 2025 16:13:10 +0200 Subject: [PATCH 233/931] ARM: dts: imx6ulz-bsh-smm-m2: fix resume via console Despite the current configuration being compliant with the technical reference manual (TRM), testing on the system showed that resuming from suspend via UART4 (used as the console) fails unless any other UART is also enabled. In our use case, UART2 is enabled to ensure reliable resume when UART4 is used as the console. Signed-off-by: Wolfgang Birkner Signed-off-by: Dario Binacchi Acked-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts index 6159ed70d966..2d9f495660c9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts @@ -33,6 +33,10 @@ &snvs_poweroff { status = "okay"; }; +&uart2 { + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; From 6aa41c8833c7871d9c94d3f56586a9dca42e94f5 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Fri, 15 Aug 2025 18:23:15 +0800 Subject: [PATCH 234/931] arm64: dts: imx8mm-evk: support more sample rates for wm8524 card The wm8524 codec is connected to the SAI interface. There are two audio plls on i.MX8MM, one pll can be the clock source of 44kHz series rates, another pll can be clock source of 48kHz series rates. Previously it only supported 48kHz series rates, with this change the supported rates will include 44kHz series rates, from 8kHz to 192kHz. As commit 17cc308b1833 ("ASoC: wm8524: enable constraints when sysclk is configured.") make wm8524 release the constraint when codec's sysclk is not configured, so configure the cpu dai's sysclk to support more rates with the 'clocks' property removed. Add mclk-fs property for the sysclk ratio, which is required by calculating the sysclk, 256 is a common ratio for audio. 'system-clock-direction-out' is a required property after commit 5725bce709db ("ASoC: simple-card-utils: Unify clock direction by clk_direction") to specify the clock direction. Signed-off-by: Shengjiu Wang Reviewed-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 622caaa78eaf..ff7ca2075230 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -147,6 +147,7 @@ sound-wm8524 { simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&cpudai>; simple-audio-card,bitclock-master = <&cpudai>; + simple-audio-card,mclk-fs = <256>; simple-audio-card,widgets = "Line", "Left Line Out Jack", "Line", "Right Line Out Jack"; @@ -158,11 +159,11 @@ cpudai: simple-audio-card,cpu { sound-dai = <&sai3>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; + system-clock-direction-out; }; simple-audio-card,codec { sound-dai = <&wm8524>; - clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; }; }; @@ -570,9 +571,17 @@ &sai2 { &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; + assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, + <&clk IMX8MM_AUDIO_PLL2>, + <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <393216000>, <361267200>, <24576000>; + fsl,sai-mclk-direction-output; + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; status = "okay"; }; From c1477b3efb6143815f20cf4e5c27c3e936e73640 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Fri, 15 Aug 2025 18:23:16 +0800 Subject: [PATCH 235/931] arm64: dts: imx8mq-evk: support more sample rates for wm8524 card The wm8524 codec is connected to the SAI interface. There are two audio plls on i.MX8MQ, one pll can be the clock source of 44kHz series rates, another pll can be clock source of 48kHz series rates. Previously it only supported 48kHz series rates, with this change the supported rates will include 44kHz series rates, from 8kHz to 192kHz. As commit 17cc308b1833 ("ASoC: wm8524: enable constraints when sysclk is configured.") make wm8524 release the constraint when codec's sysclk is not configured, so configure the cpu dai's sysclk to support more rates with the 'clocks' property removed. Add mclk-fs property for the sysclk ratio, which is required by calculating the sysclk, 256 is a common ratio for audio. 'system-clock-direction-out' is a required property after commit 5725bce709db ("ASoC: simple-card-utils: Unify clock direction by clk_direction") to specify the clock direction. Signed-off-by: Shengjiu Wang Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 43e45b0bd0d1..a88bc9034663 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -108,6 +108,7 @@ sound-wm8524 { simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&cpudai>; simple-audio-card,bitclock-master = <&cpudai>; + simple-audio-card,mclk-fs = <256>; simple-audio-card,widgets = "Line", "Left Line Out Jack", "Line", "Right Line Out Jack"; @@ -117,11 +118,11 @@ sound-wm8524 { cpudai: simple-audio-card,cpu { sound-dai = <&sai2>; + system-clock-direction-out; }; link_codec: simple-audio-card,codec { sound-dai = <&wm8524>; - clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; }; }; @@ -440,6 +441,11 @@ &sai2 { assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>; assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>; assigned-clock-rates = <0>, <24576000>; + clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_SAI2_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, + <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, + <&clk IMX8MQ_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; status = "okay"; }; From 1a9480e4fe7b18109793cfd7e9cf49e596661351 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Fri, 15 Aug 2025 18:23:17 +0800 Subject: [PATCH 236/931] arm64: dts: imx8mn-evk: support more sample rates for wm8524 card The wm8524 codec is connected to the SAI interface. There are two audio plls on i.MX8MN, one pll can be the clock source of 44kHz series rates, another pll can be clock source of 48kHz series rates. Previously it only supported 48kHz series rates, with this change the supported rates will include 44kHz series rates, from 8kHz to 192kHz. Signed-off-by: Shengjiu Wang Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 33d73f3dc187..145355ff91b4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -387,6 +387,11 @@ &sai3 { assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; assigned-clock-rates = <24576000>; fsl,sai-mclk-direction-output; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; status = "okay"; }; From cd565458c66653dade942d60f17d60ed7ac30004 Mon Sep 17 00:00:00 2001 From: Annette Kobou Date: Mon, 21 Jul 2025 12:05:35 +0200 Subject: [PATCH 237/931] arm64: dts: imx8mm-kontron: Add overlay for LTE extension board This is an addon for the BL i.MX8MM that features an LTE modem, a TPM module, some LEDs and a pushbutton. Signed-off-by: Annette Kobou Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../dts/freescale/imx8mm-kontron-bl-lte.dtso | 186 ++++++++++++++++++ 2 files changed, 188 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index dcc520355c99..d00858cb1407 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -373,8 +373,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-pcie0-ep.dtb imx95-19x19-evk-pcie1-ep. dtb-$(CONFIG_ARCH_MXC) += imx95-libra-rdk-fpsc.dtb imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo +imx8mm-kontron-bl-lte-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-bl-lte.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-dl.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-lte.dtb imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso new file mode 100644 index 000000000000..324004b0eca3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2025 Kontron Electronics GmbH + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include "imx8mm-pinfunc.h" + +&{/} { + compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-user { + label = "user"; + linux,code = ; + gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led_lte>; + + lte-led1-b { + label = "lte-led1-blue"; + color = ; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + }; + + lte-led1-g { + label = "lte-led1-green"; + color = ; + gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + }; + + lte-led1-r { + label = "lte-led1-red"; + color = ; + gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; + }; + + lte-led2-b { + label = "lte-led2-blue"; + color = ; + gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; + }; + + lte-led2-g { + label = "lte-led2-green"; + color = ; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; + }; + + lte-led2-r { + label = "lte-led2-red"; + color = ; + gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ecspi3 { + status = "disabled"; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + tpm@2e { + compatible = "infineon,slb9673", "tcg,tpm-tis-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm>; + reg = <0x2e>; + interrupt-parent = <&gpio3>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio3>; + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "VDD_IO_REF", "TPM_PIRQ#", + "TPM_RESET# ", "", "", "", + "", "LTE_LED1_B", "LTE_LED1_G", "", + ""; + + vdd-io-ref-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + line-name = "VDD_IO_REF"; + output-high; + }; + + tpm-reset-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_LOW>; + line-name = "TPM_RESET#"; + output-low; + }; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>; + gpio-line-names = "", "", "LTE_RESET", "", + "", "", "", "", + "", "", "", "LTE_PWRKEY", + "", "", "", "", + "", "", "", "", + "LTE_PWR_EN"; +}; + +&gpio5 { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "LTE_LED2_G", "LTE_LED1_R", + "LTE_LED2_R", "LTE_LED2_B"; +}; + +&iomuxc { + pinctrl_gpio3: gpio3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* VDD_IO_REF */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x19 /* LTE_RESET */ + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x19 /* LTE_PWRKEY */ + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x19 /* LTE_PWR_EN */ + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x19 /* Pushbutton */ + >; + }; + + pinctrl_gpio_led_lte: gpioledltegrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* LTE_LED1_B */ + MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* LTE_LED1_G */ + MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x19 /* LTE_LED1_R */ + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 /* LTE_LED2_B */ + MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x19 /* LTE_LED2_G */ + MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24 0x19 /* LTE_LED2_R */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 /* I2C_A_SCL */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 /* I2C_A_SDA */ + >; + }; + + pinctrl_tpm: tpmgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* TPM_PIRQ# */ + MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x39 /* TPM_RESET# */ + >; + }; +}; From 4fc4ff0240e6ecbdb33c2a716091ae81e88e3e5d Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 21 Jul 2025 12:05:36 +0200 Subject: [PATCH 238/931] arm64: dts: imx8mm-kontron: Remove unused regulator This regulator is not used anywhere and is not available in hardware. Remove it. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index 33f8d7d1970e..3a166cf0afcb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -48,14 +48,6 @@ pwm-beeper { pwms = <&pwm2 0 5000 0>; }; - reg_rst_eth2: regulator-rst-eth2 { - compatible = "regulator-fixed"; - gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - regulator-name = "rst-usb-eth2"; - }; - reg_vdd_5v: regulator-5v { compatible = "regulator-fixed"; regulator-always-on; From 371a63c1920112524cc88b585113ffc664a19391 Mon Sep 17 00:00:00 2001 From: Eberhard Stoll Date: Mon, 21 Jul 2025 12:05:37 +0200 Subject: [PATCH 239/931] arm64: dts: imx8mm-kontron: Use GPIO for RS485 transceiver control For this IP the correct control of the CTS signal for transceiver direction switching is difficult and - maybe also buggy - in the driver. Especially the bootup requires special handling for most hardware implementations. Therefore we simply use a GPIO now, which is fully under software control and which is not problematic on bootup. Signed-off-by: Eberhard Stoll Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts index d16490d87687..e756fe5db56b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -268,8 +268,16 @@ &uart1 { &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; + /* + * During bootup the CTS needs to stay LOW, which is only possible if this + * pin is controlled by a GPIO. The UART IP always sets CTS to HIGH if not + * running. So using 'uart-has-rtscts' is not a good choice here! There are + * workarounds for this, but they introduce unnecessary complexity and are + * therefore avoided here. For more information about this see: + * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit?id=79d0224f6bf296d04cd843cfc49921b19c97bb09 + */ + rts-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; linux,rs485-enabled-at-boot-time; - uart-has-rtscts; status = "okay"; }; @@ -439,7 +447,7 @@ pinctrl_uart2: uart2grp { MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 + MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 >; }; From ebd53ca845cae4c6b7960e20b0a5730bf34c2857 Mon Sep 17 00:00:00 2001 From: Oualid Derouiche Date: Mon, 21 Jul 2025 12:05:38 +0200 Subject: [PATCH 240/931] arm64: dts: imx8mm-kontron: Add Sitronix touch controller in DL devicetree Some new panels have the Sitronix touch instead of Goodix. Support them by adding a node for the new controller. The bootloader needs to detect the correct controller and enable/disable the nodes accordingly. To make this easier add labels for both nodes. Signed-off-by: Oualid Derouiche Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso b/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso index 1db27731b581..57d0739fcce3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso @@ -107,7 +107,7 @@ &i2c2 { #size-cells = <0>; status = "okay"; - touchscreen@5d { + gt911: touchscreen@5d { compatible = "goodix,gt928"; reg = <0x5d>; pinctrl-names = "default"; @@ -117,6 +117,17 @@ touchscreen@5d { reset-gpios = <&gpio3 23 0>; irq-gpios = <&gpio3 22 0>; }; + + st1633: touchscreen@55 { + compatible = "sitronix,st1633"; + reg = <0x55>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupts = <22 8>; + interrupt-parent = <&gpio3>; + gpios = <&gpio3 22 0>; + status = "disabled"; + }; }; &lvds { From b00b83913a50217331e26334c4f9eb50e6a746e9 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 21 Jul 2025 12:05:39 +0200 Subject: [PATCH 241/931] arm64: dts: imx8mm-kontron: Sort reg nodes alphabetically Sort the regulator nodes alphabetically. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mm-kontron-osm-s.dtsi | 46 +++++++++---------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index d45542965230..264553248d5c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -30,29 +30,6 @@ chosen { stdout-path = &uart3; }; - reg_vdd_carrier: regulator-vdd-carrier { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_vdd_carrier>; - gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - regulator-name = "VDD_CARRIER"; - - regulator-state-standby { - regulator-on-in-suspend; - }; - - regulator-state-mem { - regulator-off-in-suspend; - }; - - regulator-state-disk { - regulator-off-in-suspend; - }; - }; - reg_usb1_vbus: regulator-usb1-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -96,6 +73,29 @@ reg_usdhc3_vcc: regulator-usdhc3-vcc { regulator-max-microvolt = <3300000>; regulator-name = "VCC_SDIO_B"; }; + + reg_vdd_carrier: regulator-vdd-carrier { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vdd_carrier>; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + regulator-name = "VDD_CARRIER"; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + regulator-state-disk { + regulator-off-in-suspend; + }; + }; }; &A53_0 { From 5971fb6bacafd0b8d9086d084472b8d737dfb903 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 21 Jul 2025 12:05:40 +0200 Subject: [PATCH 242/931] arm64: dts: imx8mm-kontron: Name USB regulators according to OSM scheme Use the names from the OSM specification. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 264553248d5c..96987910609f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -38,7 +38,7 @@ reg_usb1_vbus: regulator-usb1-vbus { gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-name = "VBUS_USB1"; + regulator-name = "VBUS_USB_A"; }; reg_usb2_vbus: regulator-usb2-vbus { @@ -49,7 +49,7 @@ reg_usb2_vbus: regulator-usb2-vbus { gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-name = "VBUS_USB2"; + regulator-name = "VBUS_USB_B"; }; reg_usdhc2_vcc: regulator-usdhc2-vcc { From f1b27d420b6ff0feed64208e28b033d7b931ceb1 Mon Sep 17 00:00:00 2001 From: Annette Kobou Date: Mon, 21 Jul 2025 12:05:41 +0200 Subject: [PATCH 243/931] arm64: dts: imx8mp-kontron: Fix CAN_ADDR0 and CAN_ADDR1 GPIOs Some signal assignments were modified between hardware revisions 1 and 2: Revision 1: - SPI_A_WP -> CAN_ADDR0 - SPI_A_HOLD -> CAN_ADDR1 Revision 2 and later: - SPI_A_SDI -> CAN_ADDR0 - SPI_A_SDO -> CAN_ADDR1 Fix the labels and add the missing pinctrls. Signed-off-by: Annette Kobou Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-kontron-bl-osm-s.dts | 31 ++++++++++++++++--- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts index 0eb9e726a9b8..4aa5c261b865 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts @@ -123,14 +123,12 @@ &gpio2 { /* * Rename SoM signals according to board usage: - * SPI_A_WP -> CAN_ADDR0 - * SPI_A_HOLD -> CAN_ADDR1 * GPIO_B_0 -> DIO1_OUT * GPIO_B_1 -> DIO2_OUT */ &gpio3 { gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5", - "SDIO_B_D6", "SDIO_B_D7", "CAN_ADDR0", "CAN_ADDR1", + "SDIO_B_D6", "SDIO_B_D7", "SPI_A_WP", "SPI_A_HOLD", "UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1", "SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4", "PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "DIO1_OUT", @@ -159,6 +157,24 @@ &gpio4 { "GPIO_A_7", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK"; }; +/* + * Rename SoM signals according to board usage: + * SPI_A_SDI -> CAN_ADDR0 + * SPI_A_SDO -> CAN_ADDR1 + */ +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; + gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "PWM_2", + "PWM_1", "PWM_0", "SPI_A_SCK", "CAN_ADDR1", + "CAN_ADDR0", "SPI_A_CS0", "SPI_B_SCK", "SPI_B_SDO", + "SPI_B_SDI", "SPI_B_CS0", "I2C_A_SCL", "I2C_A_SDA", + "I2C_B_SCL", "I2C_B_SDA", "PCIE_SMCLK", "PCIE_SMDAT", + "I2C_CAM_SCL", "I2C_CAM_SDA", "UART_A_RX", "UART_A_TX", + "UART_C_RX", "UART_C_TX", "UART_CON_RX", "UART_CON_TX", + "UART_B_RX", "UART_B_TX"; +}; + &hdmi_pvi { status = "okay"; }; @@ -297,9 +313,16 @@ MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x46 >; }; + pinctrl_gpio5: gpio5grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x46 /* CAN_ADR0 */ + MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x46 /* CAN_ADR1 */ + >; + }; + pinctrl_usb_hub: usbhubgrp { fsl,pins = < MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x46 >; }; -}; +}; \ No newline at end of file From 0153bcd37c61fdfd4953bc3e2953f00a19577e2a Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 21 Jul 2025 12:05:42 +0200 Subject: [PATCH 244/931] arm64: dts: imx8mp-kontron: Fix GPIO labels for latest BL board Hardware rev 3 changed a few signals. Reflect these changes in the GPIO labels. * digital IOs were moved to GPIO expander * remove labels for unused signals * add labels for TFT, CSI and USB hub IOs Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-kontron-bl-osm-s.dts | 30 +++++++++---------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts index 4aa5c261b865..bbcd76e9e991 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts @@ -123,38 +123,36 @@ &gpio2 { /* * Rename SoM signals according to board usage: - * GPIO_B_0 -> DIO1_OUT - * GPIO_B_1 -> DIO2_OUT + * GPIO_B_0 -> IO_EXP_INT + * GPIO_B_1 -> IO_EXP_RST */ &gpio3 { gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5", "SDIO_B_D6", "SDIO_B_D7", "SPI_A_WP", "SPI_A_HOLD", "UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1", "SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4", - "PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "DIO1_OUT", - "DIO2_OUT", "", "BOOT_SEL0", "BOOT_SEL1", + "PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "IO_EXP_INT", + "IO_EXP_RST", "", "BOOT_SEL0", "BOOT_SEL1", "", "", "SDIO_B_CD", "SDIO_B_PWR_EN", "HDMI_CEC", "HDMI_HPD"; }; /* - * Rename SoM signals according to board usage: - * GPIO_B_5 -> DIO2_IN - * GPIO_B_6 -> DIO3_IN - * GPIO_B_7 -> DIO4_IN - * GPIO_B_3 -> DIO4_OUT - * GPIO_B_4 -> DIO1_IN - * GPIO_B_2 -> DIO3_OUT + * Rename SoM signals according to board usage and remove labels for unsed pins: + * GPIO_A_6 -> TFT_RESET + * GPIO_A_7 -> TFT_STBY + * GPIO_B_3 -> CSI_ENABLE + * GPIO_B_2 -> USB_HUB_RST */ &gpio4 { - gpio-line-names = "DIO2_IN", "DIO3_IN", "DIO4_IN", "GPIO_C_0", + gpio-line-names = "", "", "", "", "ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1", "ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK", "ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3", - "ETH_A_TX_EN", "ETH_A_TX_CLK", "DIO4_OUT", "DIO1_IN", - "DIO3_OUT", "GPIO_A_6", "CAN_A_TX", "UART_A_CTS", + "ETH_A_TX_EN", "ETH_A_TX_CLK", "CSI_ENABLE", "", + "USB_HUB_RST", "TFT_RESET", "CAN_A_TX", "UART_A_CTS", "UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX", - "GPIO_A_7", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK"; + "TFT_STBY", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK"; }; /* @@ -325,4 +323,4 @@ pinctrl_usb_hub: usbhubgrp { MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x46 >; }; -}; \ No newline at end of file +}; From 384de84ae08b2e71aaf3432f412f97d979f1ac7e Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 21 Jul 2025 12:05:43 +0200 Subject: [PATCH 245/931] arm64: dts: imx8mp-kontron: Fix USB hub reset The latest hardware revision uses GPIO_B_2 as reset for the USB hub. Fix this and remove the pinctrl as we already have this in the OSM-S devicetree. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts index bbcd76e9e991..614b4ce330b1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts @@ -250,8 +250,6 @@ &usb_dwc3_0 { }; &usb_dwc3_1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_hub>; #address-cells = <1>; #size-cells = <0>; dr_mode = "host"; @@ -260,7 +258,7 @@ &usb_dwc3_1 { usb-hub@1 { compatible = "usb424,2514"; reg = <1>; - reset-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; }; }; @@ -317,10 +315,4 @@ MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x46 /* CAN_ADR0 */ MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x46 /* CAN_ADR1 */ >; }; - - pinctrl_usb_hub: usbhubgrp { - fsl,pins = < - MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x46 - >; - }; }; From 3daaf3d026d86a401121cc37fce03890bd32a10d Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 21 Jul 2025 12:05:44 +0200 Subject: [PATCH 246/931] arm64: dts: imx93-kontron: Add RTC interrupt signal The RTC INT ouptut is connected to a GPIO. Add the interrupt so it can be used by the RTC driver. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi index 119a16207059..c79b1df339db 100644 --- a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi @@ -205,6 +205,9 @@ eeprom@50 { rv3028: rtc@52 { compatible = "microcrystal,rv3028"; reg = <0x52>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupts-extended = <&gpio3 19 IRQ_TYPE_LEVEL_LOW>; }; }; @@ -468,6 +471,12 @@ MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x31e /* CARRIER_PWR_EN */ >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x31e + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e /* I2S_A_DATA_IN */ From f3e011388dd08d15e0414e3b6b974f946305e7af Mon Sep 17 00:00:00 2001 From: Annette Kobou Date: Mon, 21 Jul 2025 12:05:45 +0200 Subject: [PATCH 247/931] arm64: dts: imx93-kontron: Fix GPIO for panel regulator The regulator uses the wrong GPIO. Fix this. Signed-off-by: Annette Kobou Signed-off-by: Frieder Schrempf Fixes: 2b52fd6035b7 ("arm64: dts: Add support for Kontron i.MX93 OSM-S SoM and BL carrier board") Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-kontron-bl-osm-s.dts | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts index 89e97c604bd3..9a9e5d0daf3b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts @@ -33,7 +33,9 @@ pwm-beeper { reg_vcc_panel: regulator-vcc-panel { compatible = "regulator-fixed"; - gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vcc_panel>; + gpio = <&gpio2 21 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; @@ -161,3 +163,11 @@ &usdhc2 { vmmc-supply = <®_vdd_3v3>; status = "okay"; }; + +&iomuxc { + pinctrl_reg_vcc_panel: regvccpanelgrp { + fsl,pins = < + MX93_PAD_GPIO_IO21__GPIO2_IO21 0x31e /* PWM_2 */ + >; + }; +}; From c94737568b290e0547bff344046f02df49ed6373 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Mon, 21 Jul 2025 12:05:46 +0200 Subject: [PATCH 248/931] arm64: dts: imx93-kontron: Fix USB port assignment The assignment of the USB ports is wrong and needs to be swapped. The OTG (USB-C) port is on the first port and the host port with the onboard hub is on the second port. Signed-off-by: Frieder Schrempf Fixes: 2b52fd6035b7 ("arm64: dts: Add support for Kontron i.MX93 OSM-S SoM and BL carrier board") Signed-off-by: Shawn Guo --- .../dts/freescale/imx93-kontron-bl-osm-s.dts | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts index 9a9e5d0daf3b..c3d2ddd887fd 100644 --- a/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts @@ -137,6 +137,16 @@ &tpm6 { }; &usbotg1 { + adp-disable; + hnp-disable; + srp-disable; + disable-over-current; + dr_mode = "otg"; + usb-role-switch; + status = "okay"; +}; + +&usbotg2 { #address-cells = <1>; #size-cells = <0>; disable-over-current; @@ -149,16 +159,6 @@ usb1@1 { }; }; -&usbotg2 { - adp-disable; - hnp-disable; - srp-disable; - disable-over-current; - dr_mode = "otg"; - usb-role-switch; - status = "okay"; -}; - &usdhc2 { vmmc-supply = <®_vdd_3v3>; status = "okay"; From e18f0f68dba5d9d52cde99c360edcb6113fbb295 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 25 Jul 2025 08:13:26 +0200 Subject: [PATCH 249/931] ARM: dts: ls1021a: Fix gic node unit address Although the GIC base address stated in RM is 0x1400000, the first address being used is 0x1401000. This is similar to imx6ul.dtsi where the GIC base address in the RM is 0xa00000 but 0xa01000 being used in DTS. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi index e86998ca77d6..fb44c76bf1d1 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi @@ -96,7 +96,7 @@ ddr: memory-controller@1080000 { big-endian; }; - gic: interrupt-controller@1400000 { + gic: interrupt-controller@1401000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>; interrupt-controller; From b0187936b87b18e7d2141dba035b1881754d172a Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 25 Jul 2025 08:13:27 +0200 Subject: [PATCH 250/931] ARM: dts: ls1021a: Fix qspi node unit address 0x8390000 is reserved memory, but 0x8380000 is the QSPI base address in RM. But register have offset of 0x8000, so first 'reg' entry address is used for node unit address. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi index fb44c76bf1d1..74c5698e0b31 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi @@ -917,7 +917,7 @@ ocram2: sram@10010000 { ranges = <0x0 0x0 0x10010000 0x10000>; }; - qdma: dma-controller@8390000 { + qdma: dma-controller@8388000 { compatible = "fsl,ls1021a-qdma"; reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ <0x0 0x8389000 0x0 0x1000>, /* Status regs */ From 2fe896e7fed00d11ff35148309aeb2309c2dcade Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 25 Jul 2025 08:13:28 +0200 Subject: [PATCH 251/931] ARM: dts: ls1021a: Fix sai DMA order According to bindings Rx DMA channel comes first if Rx & Tx is used. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi index 74c5698e0b31..2351374c2e10 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi @@ -627,9 +627,9 @@ sai1: sai@2b50000 { clocks = <&clockgen 4 1>, <&clockgen 4 1>, <&clockgen 4 1>, <&clockgen 4 1>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 47>, - <&edma0 1 46>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 46>, + <&edma0 1 47>; status = "disabled"; }; @@ -641,9 +641,9 @@ sai2: sai@2b60000 { clocks = <&clockgen 4 1>, <&clockgen 4 1>, <&clockgen 4 1>, <&clockgen 4 1>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 45>, - <&edma0 1 44>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 44>, + <&edma0 1 45>; status = "disabled"; }; From 4a3a18ce49b635c17d07657753b5405f5519f5f2 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 25 Jul 2025 08:13:29 +0200 Subject: [PATCH 252/931] ARM: dts: ls1021a: Fix FTM node RTC nodes are supposed to be named rtc@. Also remove reg-names which is neither used nor specified. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi index 2351374c2e10..2c39981bb94e 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi @@ -944,10 +944,9 @@ rcpm: power-controller@1ee2140 { #power-domain-cells = <0>; }; - ftm_alarm0: timer0@29d0000 { + ftm_alarm0: rtc@29d0000 { compatible = "fsl,ls1021a-ftm-alarm"; reg = <0x0 0x29d0000 0x0 0x10000>; - reg-names = "ftm"; fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>; interrupts = ; big-endian; From eb55cf46957499b3e3b1e0c0836e48457740b2dd Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 25 Jul 2025 08:13:30 +0200 Subject: [PATCH 253/931] ARM: dts: ls1021a: Add reg property to enet nodes Add missing reg property to enet nodes. This fixes the dtbs_check warning: Warning (unit_address_vs_reg): /soc/ethernet@2d10000: node has a unit name, but no reg or ranges property Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi index 2c39981bb94e..2f4c0e468952 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi @@ -707,6 +707,7 @@ ptp_clock@2d10e00 { enet0: ethernet@2d10000 { compatible = "fsl,etsec2"; + reg = <0x0 0x2d10000 0x0 0x5000>; device_type = "network"; #address-cells = <2>; #size-cells = <2>; @@ -737,6 +738,7 @@ queue-group@2d14000 { enet1: ethernet@2d50000 { compatible = "fsl,etsec2"; + reg = <0x0 0x2d50000 0x0 0x5000>; device_type = "network"; #address-cells = <2>; #size-cells = <2>; @@ -766,6 +768,7 @@ queue-group@2d54000 { enet2: ethernet@2d90000 { compatible = "fsl,etsec2"; + reg = <0x0 0x2d90000 0x0 0x5000>; device_type = "network"; #address-cells = <2>; #size-cells = <2>; From 4df36c41090370c31c5e16d796830b2782fc71fa Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 25 Jul 2025 08:13:31 +0200 Subject: [PATCH 254/931] ARM: dts: ls1021a: Remove superfluous address and size cells for queue-group queue-group nodes don't need them anyway as they are inherited from the corresponding ethernet nodes. Fixes the dtbs_check warning: ethernet@2d10000 (fsl,etsec2): queue-group@2d10000: '#address-cells', '#size-cells' do not match any of the regexes: '^pinctrl-[0-9]+$' Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi index 2f4c0e468952..3fbc3254d06a 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi @@ -718,8 +718,6 @@ enet0: ethernet@2d10000 { dma-coherent; queue-group@2d10000 { - #address-cells = <2>; - #size-cells = <2>; reg = <0x0 0x2d10000 0x0 0x1000>; interrupts = , , @@ -727,8 +725,6 @@ queue-group@2d10000 { }; queue-group@2d14000 { - #address-cells = <2>; - #size-cells = <2>; reg = <0x0 0x2d14000 0x0 0x1000>; interrupts = , , @@ -748,8 +744,6 @@ enet1: ethernet@2d50000 { dma-coherent; queue-group@2d50000 { - #address-cells = <2>; - #size-cells = <2>; reg = <0x0 0x2d50000 0x0 0x1000>; interrupts = , , @@ -757,8 +751,6 @@ queue-group@2d50000 { }; queue-group@2d54000 { - #address-cells = <2>; - #size-cells = <2>; reg = <0x0 0x2d54000 0x0 0x1000>; interrupts = , , @@ -778,8 +770,6 @@ enet2: ethernet@2d90000 { dma-coherent; queue-group@2d90000 { - #address-cells = <2>; - #size-cells = <2>; reg = <0x0 0x2d90000 0x0 0x1000>; interrupts = , , @@ -787,8 +777,6 @@ queue-group@2d90000 { }; queue-group@2d94000 { - #address-cells = <2>; - #size-cells = <2>; reg = <0x0 0x2d94000 0x0 0x1000>; interrupts = , , From 00f63c4db083edddabb14a577e25b108c24a2a78 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 25 Jul 2025 08:13:32 +0200 Subject: [PATCH 255/931] ARM: dts: ls1021a: remove undocumented 'big-endian' for memory-controller node According to binding doc memory-controllers/fsl/fsl,ddr.yaml and driver drivers/edac/fsl_ddr_edac.c, default is big-endian, should use little-endian for little-endian system. Remove 'big-endian' to fix below warning: arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a.dtb: memory-controller@1080000 (fsl,qoriq-memory-controller): 'big-endian' does not match any of the regexes: '^pinctrl-[0-9]+$' Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi index 3fbc3254d06a..9c9044ce7bc6 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi @@ -93,7 +93,6 @@ ddr: memory-controller@1080000 { compatible = "fsl,qoriq-memory-controller"; reg = <0x0 0x1080000 0x0 0x1000>; interrupts = ; - big-endian; }; gic: interrupt-controller@1401000 { From cfcfea8eb91e9dcf51ee4f4766d6b393237f750a Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 25 Jul 2025 08:13:33 +0200 Subject: [PATCH 256/931] ARM: dts: ls1021a: Fix watchdog node There is a dedicated compatible for ls1021a. Using it also fixes the warning regarding big-endian: arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a.dtb: watchdog@2ad0000 (fsl,imx21-wdt): big-endian: False schema does not allow True Also remove clock-names which is neither used nor specified. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi index 9c9044ce7bc6..3879cfc3efc9 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi @@ -610,11 +610,10 @@ pwm7: pwm@2a40000 { }; wdog0: watchdog@2ad0000 { - compatible = "fsl,imx21-wdt"; + compatible = "fsl,ls1021a-wdt", "fsl,imx21-wdt"; reg = <0x0 0x2ad0000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; - clock-names = "wdog-en"; big-endian; }; From f4b4c014dfaafc56c0ca2c4d0a9f3461e36209df Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 25 Jul 2025 08:13:34 +0200 Subject: [PATCH 257/931] ARM: dts: ls1021a: remove property 'snps,host-vbus-glitches' Commit 7e0685a0c4c27 ("arm64: dts: ls1012a: fix DWC3 USB VBUS glitch issue") erroneously added this to ls1021a as well. Despite that apparently the workaround has already been applied unconditional at commit a6ba1e453174 ("usb: dwc3: apply snps,host-vbus-glitches workaround unconditionally") Remove it to fix CHECK_DTBS warning: usb@3100000 (snps,dwc3): Unevaluated properties are not allowed ('snps,host-vbus-glitches' was unexpected) Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi index 3879cfc3efc9..d8a43c5aac80 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi @@ -799,7 +799,6 @@ usb3: usb@3100000 { snps,dis_rxdet_inp3_quirk; usb3-lpm-capable; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - snps,host-vbus-glitches; }; pcie@3400000 { From 0185641721b89c965e3df2afb9a6a42618c74d38 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 25 Jul 2025 08:13:35 +0200 Subject: [PATCH 258/931] ARM: dts: ls1021a: remove undocumented 'big-endian' for memory-controller node According to binding doc mmc/fsl,esdhc.yaml and driver drivers/mmc/host/sdhci-of-esdhc.c, default is big-endian, should use little-endian for little-endian system. Remove 'big-endian' to fix below warning: esdhc@1560000 (fsl,ls1021a-esdhc): Unevaluated properties are not allowed ('big-endian', 'bus-width' were unexpected) Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi index d8a43c5aac80..abb3e5ed7e02 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi @@ -161,7 +161,6 @@ esdhc: esdhc@1560000 { clock-frequency = <0>; voltage-ranges = <1800 1800 3300 3300>; sdhci,auto-cmd12; - big-endian; bus-width = <4>; status = "disabled"; }; From 80c454859ff170924a77b9d412cf380d236ae407 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 25 Jul 2025 08:16:31 +0200 Subject: [PATCH 259/931] ARM: dts: ls1021a-tqmals1021a: Remove superfluous address and size cells for qflash The jedec SPI-NOR flash node itself has no partitions, but the partitions subnode. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a.dtsi index 271001eb5ad7..167559521ae1 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a.dtsi +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a.dtsi @@ -66,8 +66,6 @@ &qspi { qflash0: flash@0 { compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; spi-max-frequency = <20000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; From e9b7e94e91a2c6c55185feaeba89d2c754be88ae Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 25 Jul 2025 08:16:32 +0200 Subject: [PATCH 260/931] ARM: dts: ls1021a-tqmals1021a-mbsl1021a: Remove superfluous compatible The touchscreen compatible in the overlays has one extra entry. Remove it to fix the dtbs_check warning: touchscreen@38 (edt,edt-ft5406): compatible: ['edt,edt-ft5406', 'edt,edt-ft5x06'] is too long Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-dc44.dtso | 2 +- .../nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-fc21.dtso | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-dc44.dtso b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-dc44.dtso index 146d45601f69..66cedc2dcd96 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-dc44.dtso +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-dc44.dtso @@ -36,7 +36,7 @@ &i2c0 { #size-cells = <0>; polytouch: touchscreen@38 { - compatible = "edt,edt-ft5406", "edt,edt-ft5x06"; + compatible = "edt,edt-ft5406"; reg = <0x38>; interrupt-parent = <&pca9554_0>; interrupts = <6 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-fc21.dtso b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-fc21.dtso index db66831f31af..8b9455bffbd2 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-fc21.dtso +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-fc21.dtso @@ -36,7 +36,7 @@ &i2c0 { #size-cells = <0>; polytouch: touchscreen@38 { - compatible = "edt,edt-ft5406", "edt,edt-ft5x06"; + compatible = "edt,edt-ft5406"; reg = <0x38>; interrupt-parent = <&pca9554_0>; interrupts = <6 IRQ_TYPE_EDGE_FALLING>; From 255ca339320d6295d678398b54973dddc792e2d2 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 25 Jul 2025 08:24:50 +0200 Subject: [PATCH 261/931] dt-bindings: arm: fsl: add TQMLS1012AL TQMLS1012AL is a SOM using NXP LS1012A CPU. MBLS1012AL is a carrier reference design. [1] https://www.tq-group.com/en/products/tq-embedded/qoriq-layerscape/tqmls1012al Signed-off-by: Matthias Schiffer Signed-off-by: Alexander Stein Acked-by: Conor Dooley Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index e21758546d13..02431ab80aa6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1539,6 +1539,12 @@ properties: - fsl,ls1012a-qds - const: fsl,ls1012a + - description: TQ Systems TQMLS12AL SoM on MBLS1012AL board + items: + - const: tq,ls1012a-tqmls1012al-mbls1012al + - const: tq,ls1012a-tqmls1012al + - const: fsl,ls1012a + - description: LS1021A based Boards items: - enum: From db48d7b37e90ccdc7e4ed8e67597e0dcf985ff04 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 25 Jul 2025 08:24:51 +0200 Subject: [PATCH 262/931] arm64: dts: ls1012a: add DTS for TQMLS1012al module with MBLS1012AL board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial support for TQMLS1012AL module mounted on MBLS1012AL. It supports UART1 for console, PCIe, I2C, USB, µSD card (default), SATA and QSPI. There is an alternative ordering option which provides an eMMC instead of an SD card. This uses a different DT instead. Due missing Packet Forwarding Engine (PFE) driver support, there is no support for Ethernet so far. Signed-off-by: Max Merchel Signed-off-by: Matthias Schiffer Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + ...sl-ls1012a-tqmls1012al-mbls1012al-emmc.dts | 23 ++ .../fsl-ls1012a-tqmls1012al-mbls1012al.dts | 366 ++++++++++++++++++ .../freescale/fsl-ls1012a-tqmls1012al.dtsi | 81 ++++ 4 files changed, 472 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index d00858cb1407..2be724579632 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -5,6 +5,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-tqmls1012al-mbls1012al.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-kbox-a-230-ls.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var1.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dts new file mode 100644 index 000000000000..07026b067320 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Matthias Schiffer + * Author: Max Merchel + */ + +#include "fsl-ls1012a-tqmls1012al-mbls1012al.dts" + +&esdhc0 { + vqmmc-supply = <®_1v8>; + /delete-property/ no-mmc; + /delete-property/ sd-uhs-sdr12; + /delete-property/ sd-uhs-sdr25; + /delete-property/ sd-uhs-sdr50; + /delete-property/ sd-uhs-sdr104; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + no-sd; + voltage-ranges = <1800 1800>; + non-removable; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al.dts new file mode 100644 index 000000000000..e46cc1a07f0c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al.dts @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Matthias Schiffer + * Author: Max Merchel + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "fsl-ls1012a-tqmls1012al.dtsi" + +/ { + model = "TQ-Systems TQMLS1012AL on MBLS1012AL"; + compatible = "tq,ls1012a-tqmls1012al-mbls1012al", "tq,ls1012a-tqmls1012al", "fsl,ls1012a"; + chassis-type = "embedded"; + + aliases { + /* use MAC from U-Boot environment */ + /* TODO: PFE */ + ethernet2 = &swport0; + ethernet3 = &swport1; + ethernet4 = &swport2; + ethernet5 = &swport3; + serial0 = &duart0; + spi0 = &qspi; + }; + + chosen { + stdout-path = &duart0; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + switch-1 { + label = "S2"; + linux,code = ; + gpios = <&gpio_exp_3p3v 13 GPIO_ACTIVE_LOW>; + }; + + switch-2 { + label = "X15"; + linux,code = ; + gpios = <&gpio_exp_1p8v 5 GPIO_ACTIVE_LOW>; + }; + + switch-3 { + label = "X16"; + linux,code = ; + gpios = <&gpio_exp_1p8v 4 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio_exp_3p3v 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_exp_3p3v 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 64 MiB */ + size = <0 0x04000000>; + /* 512 - 128 MiB, our minimum RAM config will be 512 MiB */ + alloc-ranges = <0 0x80000000 0 0x98000000>; + linux,cma-default; + }; + }; + + reg_1v5: regulator-1v5 { + compatible = "regulator-fixed"; + regulator-name = "V_1V5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + reg_1p5v_pcie: regulator-1p5v-pcie { + compatible = "regulator-fixed"; + regulator-name = "V_1V5_PCIE"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio_exp_1p8v 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_1v5>; + }; + + reg_1p5v_wlan: regulator-1p5v-wlan { + compatible = "regulator-fixed"; + regulator-name = "V_1V5_WLAN"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio_exp_1p8v 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_1v5>; + }; + + reg_1v8: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "V_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_3v3_pcie: regulator-3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_PCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio_exp_3p3v 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3>; + }; + + reg_3v3_wlan: regulator-3v3-wlan { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_WLAN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio_exp_3p3v 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_3v3>; + }; +}; + +&duart0 { + status = "okay"; +}; + +&esdhc0 { + vmmc-supply = <®_3v3>; + no-mmc; + no-sdio; + disable-wp; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&i2c0 { + gpio_exp_3p3v: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + interrupt-parent = <&gpio0>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-line-names = "", "", "GPIO_3V3_3", "", + "", "", "", "", + "", "GPIO_3V3_1", "GPIO_3V3_2", "", + "", "", "", ""; + + wlan-disable-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "WLAN_DISABLE#"; + }; + + pcie-rst-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCIE_RST#"; + }; + + wlan-rst-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "WLAN_RST#"; + }; + + pcie-dis-hog { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCIE_DIS#"; + }; + + pcie-wake-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + input; + line-name = "PCIE_WAKE#"; + }; + }; + + lm75_48: temperature-sensor@48 { + compatible = "national,lm75a"; + reg = <0x48>; + vs-supply = <®_3v3>; + }; + + switch@5f { + compatible = "microchip,ksz9897"; + reg = <0x5f>; + reset-gpios = <&gpio_exp_3p3v 7 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + swport0: port@0 { + reg = <0>; + label = "swp0"; + phy-mode = "internal"; + }; + + swport1: port@1 { + reg = <1>; + label = "swp1"; + phy-mode = "internal"; + }; + + swport2: port@2 { + reg = <2>; + label = "swp2"; + phy-mode = "internal"; + }; + + swport3: port@3 { + reg = <3>; + label = "swp3"; + phy-mode = "internal"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + /* TODO: PFE */ + phy-mode = "rgmii-id"; + rx-internal-delay-ps = <1500>; + tx-internal-delay-ps = <1500>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + gpio_exp_1p8v: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_1v8>; + interrupt-parent = <&gpio0>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-line-names = "PCIE_CLK_PD#", "PMIC_INT#", "ETH_SW_INT#", "", + "", "", "", "", + "", "GPIO_3V3_1", "GPIO_3V3_2", "", + "", "", "", ""; + + /* do not change PCIE_CLK_PD */ + pcie-clk-pd-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCIE_CLK_PD#"; + }; + + pmic-int-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + input; + line-name = "PMIC_INT#"; + }; + + eth-sw-int-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + input; + line-name = "ETH_SW_INT#"; + }; + + eth-link-pwrdwn-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + input; + line-name = "ETH_LINK_PWRDWN#"; + }; + }; +}; + +&pcie1 { + status = "okay"; +}; + +/* TODO: PFE */ + +&sata { + status = "okay"; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio_exp_3p3v 6 GPIO_ACTIVE_LOW>; + vdd-supply = <®_vcc_3v3>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio_exp_3p3v 6 GPIO_ACTIVE_LOW>; + vdd-supply = <®_vcc_3v3>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al.dtsi new file mode 100644 index 000000000000..7c5a3dee91b9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Matthias Schiffer + * Author: Max Merchel + */ + +#include "fsl-ls1012a.dtsi" + +/ { + compatible = "tq,ls1012a-tqmls1012al", "fsl,ls1012a"; + + memory@80000000 { + device_type = "memory"; + /* our minimum RAM config will be 512 MiB */ + reg = <0x00000000 0x80000000 0 0x20000000>; + }; + + reg_vcc_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_vcc_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&i2c0 { + status = "okay"; + + jc42_19: temperature-sensor@19 { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x19>; + }; + + m24c64_50: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <®_vcc_3v3>; + }; + + m24c02_51: eeprom@51 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + read-only; + vcc-supply = <®_vcc_3v3>; + }; + + rtc1: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&qspi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <39000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + vcc-supply = <®_vcc_1v8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; From a0000b40dacd17ac0f1d7d59bdbbdd0639781165 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Fri, 25 Jul 2025 15:04:30 +0800 Subject: [PATCH 263/931] arm64: dts: freescale: Add dma err irq info on imx94 Add the err irq info for edma2 and edma4. These two err irq are connected to the GIC directly, not irqsteer. Signed-off-by: Jacky Bai Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx94.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 44dee2cbd42d..d4a880496b0e 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -212,7 +212,8 @@ edma2: dma-controller@42000000 { <&a55_irqsteer 88>, <&a55_irqsteer 89>, <&a55_irqsteer 90>, <&a55_irqsteer 91>, <&a55_irqsteer 92>, <&a55_irqsteer 93>, - <&a55_irqsteer 94>, <&a55_irqsteer 95>; + <&a55_irqsteer 94>, <&a55_irqsteer 95>, + <&gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; }; mu10: mailbox@42430000 { @@ -619,7 +620,8 @@ edma4: dma-controller@42df0000 { <&a55_irqsteer 216>, <&a55_irqsteer 217>, <&a55_irqsteer 218>, <&a55_irqsteer 219>, <&a55_irqsteer 220>, <&a55_irqsteer 221>, - <&a55_irqsteer 222>, <&a55_irqsteer 223>; + <&a55_irqsteer 222>, <&a55_irqsteer 223>, + <&gic GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; }; }; From 0f03b751b9e35398513d63d2bb7342564157c938 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Thu, 31 Jul 2025 16:01:34 +0200 Subject: [PATCH 264/931] arm64: dts: s32g2: Add the System Timer Module nodes The s32g2 has a STM module containing 8 timers. Each timer has a dedicated interrupt and share the same clock. Add the timers STM0->STM6 nodes for the s32g2 SoC. The STM7 node is not added because it is slightly different and needs an extra property which will be added later when supported by the driver. Signed-off-by: Daniel Lezcano Cc: Ghennadi Procopciuc Cc: Thomas Fossati Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 63 ++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 09d2fbbe1d8c..3bca469e75f7 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -325,6 +325,42 @@ usdhc0-200mhz-grp4 { }; }; + stm0: timer@4011c000 { + compatible = "nxp,s32g2-stm"; + reg = <0x4011c000 0x3000>; + interrupts = ; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm1: timer@40120000 { + compatible = "nxp,s32g2-stm"; + reg = <0x40120000 0x3000>; + interrupts = ; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm2: timer@40124000 { + compatible = "nxp,s32g2-stm"; + reg = <0x40124000 0x3000>; + interrupts = ; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + stm3: timer@40128000 { + compatible = "nxp,s32g2-stm"; + reg = <0x40128000 0x3000>; + interrupts = ; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + edma0: dma-controller@40144000 { compatible = "nxp,s32g2-edma"; reg = <0x40144000 0x24000>, @@ -479,6 +515,33 @@ i2c2: i2c@401ec000 { status = "disabled"; }; + stm4: timer@4021c000 { + compatible = "nxp,s32g2-stm"; + reg = <0x4021c000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = ; + status = "disabled"; + }; + + stm5: timer@40220000 { + compatible = "nxp,s32g2-stm"; + reg = <0x40220000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = ; + status = "disabled"; + }; + + stm6: timer@40224000 { + compatible = "nxp,s32g2-stm"; + reg = <0x40224000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = ; + status = "disabled"; + }; + edma1: dma-controller@40244000 { compatible = "nxp,s32g2-edma"; reg = <0x40244000 0x24000>, From 6aa892c0f180a9a19d407ebe26b66a18a291fc83 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Thu, 31 Jul 2025 16:01:35 +0200 Subject: [PATCH 265/931] arm64: dts: s32g274-rd2: Enable the STM timers Enable the timers STM0 -> STM3 on the s32g274-rd2 The platform has 4 CPUs, and the Linux STM timer driver is instantiated per CPU. Enable 4 STM timers that can be used as replacements for the ARM architected timers. The remaining STM timers are not useful to the Linux kernel and provide no benefit, so they are left disabled. Signed-off-by: Daniel Lezcano Cc: Ghennadi Procopciuc Cc: Thomas Fossati Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts index b5ba51696f43..505776d19151 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts @@ -40,6 +40,22 @@ &uart1 { status = "okay"; }; +&stm0 { + status = "okay"; +}; + +&stm1 { + status = "okay"; +}; + +&stm2 { + status = "okay"; +}; + +&stm3 { + status = "okay"; +}; + &usdhc0 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc0>; From 13c0e302a97e9d7d79ae65b051661c68c0b18d87 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Thu, 31 Jul 2025 16:01:36 +0200 Subject: [PATCH 266/931] arm64: dts: s32g3: Add the System Timer Module nodes The s32g3 has a STM module containing 12 timers. Each timer has a dedicated interrupt and share the same clock. Add the STM0->STM11 nodes for the s32g3 SoC. The STM7 node is not added because it is slightly different and needs an extra property which will be added later when supported by the driver. Signed-off-by: Daniel Lezcano Cc: Ghennadi Procopciuc Cc: Thomas Fossati Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g3.dtsi | 99 ++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 39effbe8217c..e986b1edd91b 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -383,6 +383,42 @@ usdhc0-200mhz-grp4 { }; }; + stm0: timer@4011c000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x4011c000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = ; + status = "disabled"; + }; + + stm1: timer@40120000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40120000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = ; + status = "disabled"; + }; + + stm2: timer@40124000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40124000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = ; + status = "disabled"; + }; + + stm3: timer@40128000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40128000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = ; + status = "disabled"; + }; + edma0: dma-controller@40144000 { compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; reg = <0x40144000 0x24000>, @@ -542,6 +578,33 @@ i2c2: i2c@401ec000 { status = "disabled"; }; + stm4: timer@4021c000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x4021c000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = ; + status = "disabled"; + }; + + stm5: timer@40220000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40220000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = ; + status = "disabled"; + }; + + stm6: timer@40224000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40224000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = ; + status = "disabled"; + }; + edma1: dma-controller@40244000 { compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; reg = <0x40244000 0x24000>, @@ -670,6 +733,42 @@ usdhc0: mmc@402f0000 { status = "disabled"; }; + stm8: timer@40520000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40520000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = ; + status = "disabled"; + }; + + stm9: timer@40524000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40524000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = ; + status = "disabled"; + }; + + stm10: timer@40528000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x40528000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = ; + status = "disabled"; + }; + + stm11: timer@4052c000 { + compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; + reg = <0x4052c000 0x3000>; + clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>; + clock-names = "counter", "module", "register"; + interrupts = ; + status = "disabled"; + }; + gic: interrupt-controller@50800000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From 7c4ad77ccaab2e91057f4b4f1391f76e3d01a525 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Thu, 31 Jul 2025 16:01:37 +0200 Subject: [PATCH 267/931] arm64: dts: s32g399a-rdb3: Enable the STM timers The platform has 8 CPUs, and the Linux STM timer driver is instantiated per CPU. Enable 8 STM timers that can be used as replacements for the ARM architected timers. The remaining STM timers are not useful to the Linux kernel and provide no benefit, so they are left disabled. Enable STM0 to STM6 and STM8 on the s32g399a-rdb3 platform. STM7 is skipped, as it differs slightly from the others and requires an additional property to be properly handled by the driver. Signed-off-by: Daniel Lezcano Cc: Ghennadi Procopciuc Cc: Thomas Fossati Signed-off-by: Shawn Guo --- .../boot/dts/freescale/s32g399a-rdb3.dts | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts index 802f543cae4a..467e0c105c3f 100644 --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts @@ -40,6 +40,38 @@ &uart1 { status = "okay"; }; +&stm0 { + status = "okay"; +}; + +&stm1 { + status = "okay"; +}; + +&stm2 { + status = "okay"; +}; + +&stm3 { + status = "okay"; +}; + +&stm4 { + status = "okay"; +}; + +&stm5 { + status = "okay"; +}; + +&stm6 { + status = "okay"; +}; + +&stm8 { + status = "okay"; +}; + &i2c4 { current-sensor@40 { compatible = "ti,ina231"; From efb4d287f1c00d402a9e83f768dd7b3ce888cd02 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Thu, 31 Jul 2025 16:01:38 +0200 Subject: [PATCH 268/931] arm64: dts: s32g2: Add the Software Timer Watchdog (SWT) nodes Referred in the documentation as the Software Timer Watchdog (SWT), the s32g2 has 7 watchdogs. The number of watchdogs is designed to allow dedicating one watchdog per Cortex-M7/A53 present on the SoC. Add the SWT nodes in the device tree. Signed-off-by: Daniel Lezcano Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 56 ++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 3bca469e75f7..3ff3b2ff09be 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -325,6 +325,38 @@ usdhc0-200mhz-grp4 { }; }; + swt0: watchdog@40100000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40100000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt1: watchdog@40104000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40104000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt2: watchdog@40108000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40108000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt3: watchdog@4010c000 { + compatible = "nxp,s32g2-swt"; + reg = <0x4010c000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + stm0: timer@4011c000 { compatible = "nxp,s32g2-stm"; reg = <0x4011c000 0x3000>; @@ -515,6 +547,30 @@ i2c2: i2c@401ec000 { status = "disabled"; }; + swt4: watchdog@40200000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40200000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt5: watchdog@40204000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40204000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt6: watchdog@40208000 { + compatible = "nxp,s32g2-swt"; + reg = <0x40208000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + stm4: timer@4021c000 { compatible = "nxp,s32g2-stm"; reg = <0x4021c000 0x3000>; From 88a1e2d86540f3753ef51b44830ec6254411ef19 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Thu, 31 Jul 2025 16:01:39 +0200 Subject: [PATCH 269/931] arm64: dts: s32g274-rd2: Enable the SWT watchdog The SWT0 is directly connected to the reset line and only one instance is useful for its purpose. Let's enable it for the s32g274-rd2. Signed-off-by: Daniel Lezcano Cc: Ghennadi Procopciuc Cc: Thomas Fossati Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts index 505776d19151..4f58be68c818 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts @@ -56,6 +56,10 @@ &stm3 { status = "okay"; }; +&swt0 { + status = "okay"; +}; + &usdhc0 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc0>; From 6db84f04274571be0ed7aad394625aa86c101fd0 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Thu, 31 Jul 2025 16:01:40 +0200 Subject: [PATCH 270/931] arm64: dts: s32g3: Add the Software Timer Watchdog (SWT) nodes Referred in the documentation as the Software Timer Watchdog (SWT), the s32g3 has 12 watchdogs. The number of watchdogs is designed to allow dedicating one watchdog per Cortex-M7/A53 present on the SoC. Add the SWT nodes in the device tree. Signed-off-by: Daniel Lezcano Cc: Ghennadi Procopciuc Cc: Thomas Fossati Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g3.dtsi | 96 ++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index e986b1edd91b..6292ae99883a 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -383,6 +383,38 @@ usdhc0-200mhz-grp4 { }; }; + swt0: watchdog@40100000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40100000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt1: watchdog@40104000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40104000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt2: watchdog@40108000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40108000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt3: watchdog@4010c000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x4010c000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + stm0: timer@4011c000 { compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; reg = <0x4011c000 0x3000>; @@ -578,6 +610,38 @@ i2c2: i2c@401ec000 { status = "disabled"; }; + swt4: watchdog@40200000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40200000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt5: watchdog@40204000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40204000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt6: watchdog@40208000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40208000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt7: watchdog@4020C000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x4020C000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + stm4: timer@4021c000 { compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; reg = <0x4021c000 0x3000>; @@ -733,6 +797,38 @@ usdhc0: mmc@402f0000 { status = "disabled"; }; + swt8: watchdog@40500000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <40500000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt9: watchdog@40504000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40504000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt10: watchdog@40508000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x40508000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + + swt11: watchdog@4050c000 { + compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; + reg = <0x4050c000 0x1000>; + clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; + clock-names = "counter", "module", "register"; + status = "disabled"; + }; + stm8: timer@40520000 { compatible = "nxp,s32g3-stm", "nxp,s32g2-stm"; reg = <0x40520000 0x3000>; From 48d86413d807c2db285f3bacfa26d9d211608439 Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Thu, 31 Jul 2025 16:01:41 +0200 Subject: [PATCH 271/931] arm64: dts: s32g399a-rdb3: Enable the SWT watchdog The SWT0 is directly connected to the reset line and only one instance is useful for its purpose. Let's enable it on the s32g399a-rdb3. Signed-off-by: Daniel Lezcano Cc: Ghennadi Procopciuc Cc: Thomas Fossati Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts index 467e0c105c3f..e94f70ad82d9 100644 --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts @@ -72,6 +72,10 @@ &stm8 { status = "okay"; }; +&swt0 { + status = "okay"; +}; + &i2c4 { current-sensor@40 { compatible = "ti,ina231"; From 6351806e5cd3290de6914327a7359e6f4a9e9a5f Mon Sep 17 00:00:00 2001 From: Pengfei Li Date: Wed, 6 Aug 2025 19:41:09 +0800 Subject: [PATCH 272/931] dt-bindings: arm: fsl: add i.MX91 11x11 evk board Add the board imx91-11x11-evk in the binding document. Signed-off-by: Pengfei Li Signed-off-by: Joy Zou Acked-by: Conor Dooley Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 02431ab80aa6..ebafa6ecbcb6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1387,6 +1387,12 @@ properties: - fsl,imx8ulp-evk # i.MX8ULP EVK Board - const: fsl,imx8ulp + - description: i.MX91 based Boards + items: + - enum: + - fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board + - const: fsl,imx91 + - description: i.MX93 based Boards items: - enum: From 395a9013890309fa47ea16f5d82791d90d54d6fa Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Mon, 11 Aug 2025 08:38:54 +0200 Subject: [PATCH 273/931] arm64: dts: imx8dxl-ss-conn: Disable USB3 nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The i.MX 8DualXLite/8SoloXLite has a different connectivity memory map than the generic i.MX8 has. One conflicting resource is usb, where the imx8dxl has a second usb2 phy @5b110000, while the generic imx8 dtsi has one usb2 phy and one usb3 phy, and the usb3otg @5b110000. When including both imx8dxl-ss-conn.dtsi and imx8-ss-conn.dtsi as done in imx8dxl.dtsi this leads to a duplicate unit-address warning. The usb3otg node was introduced after the initial imx8dxl support with commit a8bd7f155126 ("arm64: dts: imx8qxp: add cadence usb3 support") and since then leads to warnings like this (when built with W=2): DTC arch/arm64/boot/dts/freescale/imx8dxl-evk.dtb …/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi:148.24-182.4: Warning (unique_unit_address): /bus@5b000000/usb@5b110000: duplicate unit-address (also used in node /bus@5b000000/usbphy@5b110000) also defined at …/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi:41.23-50.4 also defined at …/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts:645.8-653.3 Delete usb3 related nodes at dxl to fix above warning. Signed-off-by: Alexander Dahl Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi index 9b114bed084b..a66ba6d0a8c0 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi @@ -5,6 +5,8 @@ /delete-node/ &enet1_lpcg; /delete-node/ &fec2; +/delete-node/ &usbotg3; +/delete-node/ &usb3_phy; / { conn_enet0_root_clk: clock-conn-enet0-root { From 3784c3819b201daa886cfe8aeabd7b765d382b29 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 12 Aug 2025 08:13:38 +0200 Subject: [PATCH 274/931] ARM: dts: ls1021a: rename rcpm as wakeup-control from power-control Invoke power-domain.yaml if node name as 'power-control'. Rcpm actually are not power domain controller. It just control wakeup capability. So rename it as wakeup-control. Implements the same change as commit e39f567e1c38c ("arm64: dts: layerscape: rename rcpm as wakeup-control from power-control") for arm64 layerscapes. While at it, also remove superfluous #power-domain-cells Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi index abb3e5ed7e02..29105773add7 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi @@ -924,11 +924,10 @@ qdma: dma-controller@8388000 { big-endian; }; - rcpm: power-controller@1ee2140 { + rcpm: wakeup-controller@1ee2140 { compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+"; reg = <0x0 0x1ee2140 0x0 0x8>; #fsl,rcpm-wakeup-cells = <2>; - #power-domain-cells = <0>; }; ftm_alarm0: rtc@29d0000 { From 3557df14346ddb4d17a87d5de08e72db2ee823c2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 13 Aug 2025 17:44:46 +0200 Subject: [PATCH 275/931] arm64: dts: freescale: Switch to hp-det-gpios Replace the deprecated "hp-det-gpio" property by "hp-det-gpios" in Freescale Generic ASoC Sound Card device nodes. Signed-off-by: Geert Uytterhoeven Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 2 +- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 2 +- arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 95523c538135..d0b3e66e0973 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -406,7 +406,7 @@ sound-wm8960 { model = "wm8960-audio"; audio-cpu = <&sai1>; audio-codec = <&wm8960>; - hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", "Ext Spk", "SPK_LP", diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index e54be7f649ff..7b0337445541 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -333,7 +333,7 @@ sound-wm8960 { model = "wm8960-audio"; audio-cpu = <&sai1>; audio-codec = <&wm8960>; - hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; + hp-det-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>; audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", "Ext Spk", "SPK_LP", diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 2f949a0d48d2..213eb5476b84 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -216,7 +216,7 @@ sound-wm8962 { model = "wm8962-audio"; audio-cpu = <&sai3>; audio-codec = <&wm8962>; - hp-det-gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + hp-det-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; audio-routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", "Ext Spk", "SPKOUTL", From 6fdaf3b1839c861931db0dd11747c056a76b68f9 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Mon, 18 Aug 2025 09:25:31 +0800 Subject: [PATCH 276/931] arm64: dts: imx95: Correct the lpuart7 and lpuart8 srcid According to the imx95 RM, the lpuart7 rx and tx DMA's srcid are 88 and 87, and the lpuart8 rx and tx DMA's srcid are 90 and 89. So correct them. Fixes: 915fd2e127e8 ("arm64: dts: imx95: add edma[1..3] nodes") Signed-off-by: Joy Zou Signed-off-by: Peng Fan Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 4ca6a7ea586e..dbcc557d07f5 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -913,7 +913,7 @@ lpuart7: serial@42690000 { interrupts = ; clocks = <&scmi_clk IMX95_CLK_LPUART7>; clock-names = "ipg"; - dmas = <&edma2 26 0 FSL_EDMA_RX>, <&edma2 25 0 0>; + dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -925,7 +925,7 @@ lpuart8: serial@426a0000 { interrupts = ; clocks = <&scmi_clk IMX95_CLK_LPUART8>; clock-names = "ipg"; - dmas = <&edma2 28 0 FSL_EDMA_RX>, <&edma2 27 0 0>; + dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; dma-names = "rx", "tx"; status = "disabled"; }; From 289948aa706dca8ca67167cdd95f1901aca8f32a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 18 Aug 2025 09:25:32 +0800 Subject: [PATCH 277/931] arm64: dts: imx95: Add System Counter node Add System Counter node to support cpuidle when arm generic timer stops Reviewed-by: Frank Li Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index dbcc557d07f5..642dc4b7a477 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1260,6 +1260,15 @@ mu1: mailbox@44220000 { status = "disabled"; }; + system_counter: timer@44290000 { + compatible = "nxp,imx95-sysctr-timer"; + reg = <0x44290000 0x30000>; + interrupts = ; + clocks = <&osc_24m>; + clock-names = "per"; + nxp,no-divider; + }; + tpm1: pwm@44310000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x44310000 0x1000>; From 770fcc6856e986b4dc976d22e64083a4a772a69f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 18 Aug 2025 09:25:33 +0800 Subject: [PATCH 278/931] arm64: dts: imx95: Add LMM/CPU nodes Add SCMI LMM and CPU nodes for managing Logical Machine and CPU. Reviewed-by: Frank Li Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 642dc4b7a477..e20feb1bcec6 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -351,10 +351,18 @@ scmi_iomuxc: protocol@19 { reg = <0x19>; }; + scmi_lmm: protocol@80 { + reg = <0x80>; + }; + scmi_bbm: protocol@81 { reg = <0x81>; }; + scmi_cpu: protocol@82 { + reg = <0x82>; + }; + scmi_misc: protocol@84 { reg = <0x84>; }; From 9b541c18a8cfbf9f01d3dc5e794104cda1708329 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 18 Aug 2025 09:25:34 +0800 Subject: [PATCH 279/931] arm64: dts: imx95: Add more V2X MUs Add more MUs for V2X communication Reviewed-by: Frank Li Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index e20feb1bcec6..02c0422a7aa3 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1500,6 +1500,13 @@ mu6: mailbox@44630000 { }; }; + mailbox@47300000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47300000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + mailbox@47320000 { compatible = "fsl,imx95-mu-v2x"; reg = <0x0 0x47320000 0x0 0x10000>; @@ -1507,6 +1514,20 @@ mailbox@47320000 { #mbox-cells = <2>; }; + mailbox@47330000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47330000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + mailbox@47340000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47340000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + mailbox@47350000 { compatible = "fsl,imx95-mu-v2x"; reg = <0x0 0x47350000 0x0 0x10000>; From c1288a46af3e5a6bac0ef67f0268ea893b9a7317 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 18 Aug 2025 09:25:35 +0800 Subject: [PATCH 280/931] arm64: dts: imx95: Add OCOTP node Add OCOTP node to allow reading fuse using nvmem API Reviewed-by: Frank Li Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 02c0422a7aa3..adc63448aa15 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1553,6 +1553,25 @@ gpio1: gpio@47400000 { status = "disabled"; }; + ocotp: efuse@47510000 { + compatible = "fsl,imx95-ocotp", "syscon"; + reg = <0x0 0x47510000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + eth_mac0: mac-address@0 { + reg = <0x0514 0x6>; + }; + + eth_mac1: mac-address@1 { + reg = <0x1514 0x6>; + }; + + eth_mac2: mac-address@2 { + reg = <0x2514 0x6>; + }; + }; + elemu0: mailbox@47520000 { compatible = "fsl,imx95-mu-ele"; reg = <0x0 0x47520000 0x0 0x10000>; From 530141de4d6598f88924c5b2c4d9ee7b7c72db77 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 18 Aug 2025 09:25:36 +0800 Subject: [PATCH 281/931] arm64: dts: imx95: Add coresight nodes Add etf, etm, etr, funnel nodes for coresight. Signed-off-by: Peng Fan Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 104 +++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index adc63448aa15..56d782f423bb 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -492,6 +492,110 @@ soc { #size-cells = <2>; ranges; + etm0: etm@40840000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x40840000 0x0 0x10000>; + arm,primecell-periphid = <0xbb95d>; + cpu = <&A55_0>; + clocks = <&scmi_clk IMX95_CLK_A55PERIPH>; + clock-names = "apb_pclk"; + status = "disabled"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + }; + + funnel0: funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + status = "disabled"; + + in-ports { + port { + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + }; + + out-ports { + port { + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + }; + }; + + funnel1: funnel-sys { + compatible = "arm,coresight-static-funnel"; + status = "disabled"; + + in-ports { + port { + hugo_funnel_in_port0: endpoint { + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + etf: etf@41030000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x41030000 0x0 0x1000>; + clocks = <&scmi_clk IMX95_CLK_A55PERIPH>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + }; + + etr: etr@41040000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x41040000 0x0 0x1000>; + clocks = <&scmi_clk IMX95_CLK_A55PERIPH>; + clock-names = "apb_pclk"; + status = "disabled"; + + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + aips2: bus@42000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x0 0x42000000 0x0 0x800000>; From 06d59feccdedee2888e98e43e13a9e0382745979 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 18 Aug 2025 09:25:37 +0800 Subject: [PATCH 282/931] arm64: dts: imx95-evk: Update alias Add i2c, gpio, mmc, serial alias for 15x15 EVK and add lpuart5 serial alias for 19x19 EVK. Reviewed-by: Frank Li Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx95-15x15-evk.dts | 17 +++++++++++++++++ .../boot/dts/freescale/imx95-19x19-evk.dts | 1 + 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index 46f6e0fbf2b0..de7f4321e5f9 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -28,7 +28,24 @@ / { aliases { ethernet0 = &enetc_port0; ethernet1 = &enetc_port1; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; serial0 = &lpuart1; + serial4 = &lpuart5; }; bt_sco_codec: bt-sco-codec { diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 213eb5476b84..fc19b29e179d 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -40,6 +40,7 @@ aliases { mmc0 = &usdhc1; mmc1 = &usdhc2; serial0 = &lpuart1; + serial4 = &lpuart5; }; bt_sco_codec: audio-codec-bt-sco { From 0898ed6832f5ce977e2a2c3d1556b156f2bc7502 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Mon, 18 Aug 2025 09:25:38 +0800 Subject: [PATCH 283/931] arm64: dts: imx95-19x19-evk: Add Tsettle delay in m2 regulator M.2 device only can be enabled after all Power Rails reach their minimum operating voltage (PCI Express M.2 Specification r5.1 3.1.4 Power-up Timing). Set a delay equal to the max value of Tsettle in m2 regulator. Signed-off-by: Richard Zhu Reviewed-by: Frank Li Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index fc19b29e179d..3df7a046fbc8 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -136,6 +136,13 @@ reg_m2_pwr: regulator-m2-pwr { regulator-max-microvolt = <3300000>; gpio = <&i2c7_pcal6524 20 GPIO_ACTIVE_HIGH>; enable-active-high; + /* + * M.2 device only can be enabled(W_DISABLE1#) after all Power + * Rails reach their minimum operating voltage (PCI Express M.2 + * Specification r5.1 3.1.4 Power-up Timing). + * Set a delay equal to the max value of Tsettle here. + */ + startup-delay-us = <5000>; }; reg_pcie0: regulator-pcie { From 72961e143de68d7b229d275329a37b9c99e8925e Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 18 Aug 2025 09:25:39 +0800 Subject: [PATCH 284/931] arm64: dts: imx95-19x19-evk: Add pca9632 node Add an I2C controlled 4-bit LED driver PCA9632 under lpi2c3. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 3df7a046fbc8..9e21fe1a438a 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -310,6 +310,19 @@ i2c3_gpio_expander_20: gpio@20 { reg = <0x20>; vcc-supply = <®_3p3v>; }; + + pca9632: pca9632@62 { + compatible = "nxp,pca9632"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + led_baclklight: led@0 { + reg = <0>; + label = "backlight"; + linux,default-trigger = "none"; + }; + }; }; &lpi2c4 { From fd7053e82fa6f915a36b4fd5a901e5e2174a6dbd Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 18 Aug 2025 09:25:40 +0800 Subject: [PATCH 285/931] arm64: dts: imx95-19x19-evk: Add pf09 and pf53 thermal zones System Manager supports reading out pf09 and pf53 temperature and SCMI Agent could get the values through SCMI sensor protocol. So add the nodes to allow Linux to get the temperature. Reviewed-by: Frank Li Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx95-19x19-evk.dts | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 9e21fe1a438a..5fab3e1d5776 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -1058,6 +1058,79 @@ map3 { }; }; }; + + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf09_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + cooling-maps { + map0 { + trip = <&pf5301_alert>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + pf5301_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5301_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5302_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; }; &tpm6 { From 3d25ef32f140533a1f954ec4c6e6b33ea9b08983 Mon Sep 17 00:00:00 2001 From: Luke Wang Date: Mon, 18 Aug 2025 09:25:41 +0800 Subject: [PATCH 286/931] arm64: dts: imx95-15x15-evk: Change pinctrl settings for usdhc2 The drive strength is too high for SDR104 mode. Change the drive strength to X3 as hardware team recommends. Signed-off-by: Luke Wang Reviewed-by: Frank Li Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index de7f4321e5f9..3c23022923e6 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -881,12 +881,12 @@ IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe - IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe - IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe - IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe - IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe - IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; From 9270fe91e9d2fd2323941825f5103a4ee58abe4c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:18:01 +0200 Subject: [PATCH 287/931] ARM: dts: nxp: imx6ull: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.dts index 5d1cc8a1f555..107b00b9a939 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-rmm.dts @@ -129,7 +129,7 @@ &i2c1 { status = "okay"; touchscreen: touchscreen@38 { - compatible ="edt,edt-ft5306"; + compatible = "edt,edt-ft5306"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_touchscreen>; From 22df6943dcdddcb2b833a8fb4d30813cde5be4d7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:18:02 +0200 Subject: [PATCH 288/931] arm64: dts: freescale: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' or '{' characters. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Frank Li Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8-apalis-v1.1.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 2 +- .../dts/freescale/imx8mm-emtop-baseboard.dts | 2 +- .../imx8mm-phyboard-polis-peb-av-10.dtso | 2 +- .../imx8mp-aristainetos3-proton2s.dts | 2 +- .../imx8mp-aristainetos3a-som-v1.dtsi | 6 +-- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +- .../dts/freescale/imx8mp-skov-revb-lt6.dts | 2 +- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 2 +- .../boot/dts/freescale/imx8x-colibri.dtsi | 4 +- .../boot/dts/freescale/imx93-14x14-evk.dts | 4 +- .../boot/dts/freescale/imx95-19x19-evk.dts | 2 +- arch/arm64/boot/dts/freescale/imx95.dtsi | 40 +++++++++---------- 13 files changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index 6f27a9cc2494..86d018f470c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -256,7 +256,7 @@ touchscreen: touchscreen { }; &asrc0 { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; }; &adc0 { diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index b6d64d3906ea..25a77cac6f0b 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -652,7 +652,7 @@ &pcie0 { status = "okay"; }; -&pcie0_ep{ +&pcie0_ep { phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts b/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts index 90e638b8e92a..87fe3ebedb8d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts @@ -333,7 +333,7 @@ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 >; }; - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp{ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso index e5ca5a664b61..79e4c3710ac3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso @@ -20,7 +20,7 @@ backlight: backlight { pwms = <&pwm4 0 50000 0>; power-supply = <®_vdd_3v3_s>; enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - brightness-levels= <0 4 8 16 32 64 128 255>; + brightness-levels = <0 4 8 16 32 64 128 255>; }; panel { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts index 2a736dbe96b4..58e36de7a2cd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts @@ -36,7 +36,7 @@ &eqos { max-speed = <100>; }; -&ecspi1{ +&ecspi1 { pinctrl-0 = <&pinctrl_ecspi1>; cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi index 231e480acfd4..f654d866e58c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi @@ -167,7 +167,7 @@ &clk { <&clk IMX8MP_VIDEO_PLL1>; }; -&ecspi1{ +&ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs2>; cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW &gpio1 6 GPIO_ACTIVE_LOW>; @@ -565,7 +565,7 @@ &mipi_dsi { status = "disabled"; }; -&pcie{ +&pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio4 20 GPIO_ACTIVE_LOW>; @@ -574,7 +574,7 @@ &pcie{ status = "okay"; }; -&pcie_phy{ +&pcie_phy { fsl,refclk-pad-mode = ; clocks = <&pcie0_refclk>; clock-names = "ref"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index c0cc5611048e..3730792daf50 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -309,7 +309,7 @@ &dsp { }; &easrc { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts index baecf768a2ee..e602c1c96143 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts @@ -83,7 +83,7 @@ adc_ts: adc@0 { compatible = "ti,tsc2046e-adc"; reg = <0>; pinctrl-0 = <&pinctrl_touch>; - pinctrl-names ="default"; + pinctrl-names = "default"; spi-max-frequency = <1000000>; interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; #io-channel-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index d0b3e66e0973..202d5c67ac40 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -407,7 +407,7 @@ sound-wm8960 { audio-cpu = <&sai1>; audio-codec = <&wm8960>; hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; - audio-routing = "Headphone Jack", "HP_L", + audio-routing = "Headphone Jack", "HP_L", "Headphone Jack", "HP_R", "Ext Spk", "SPK_LP", "Ext Spk", "SPK_LN", diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index e602d147e39b..8e9e841cc828 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -462,11 +462,11 @@ &lsio_pwm2 { /* VPU Mailboxes */ &mu_m0 { - status="okay"; + status = "okay"; }; &mu1_m0 { - status="okay"; + status = "okay"; }; /* TODO MIPI CSI */ diff --git a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts index c5d86b54ad33..8c5769f90746 100644 --- a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts @@ -276,7 +276,7 @@ buck2: BUCK2 { regulator-ramp-delay = <3125>; }; - buck4: BUCK4{ + buck4: BUCK4 { regulator-name = "BUCK4"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3400000>; @@ -284,7 +284,7 @@ buck4: BUCK4{ regulator-always-on; }; - buck5: BUCK5{ + buck5: BUCK5 { regulator-name = "BUCK5"; regulator-min-microvolt = <1620000>; regulator-max-microvolt = <3400000>; diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 5fab3e1d5776..1a9454ea531d 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -692,7 +692,7 @@ &wdog3 { }; &scmi_iomuxc { - pinctrl_emdio: emdiogrp{ + pinctrl_emdio: emdiogrp { fsl,pins = < IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 56d782f423bb..4e5a2d40c718 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -260,35 +260,35 @@ clk_ext1: clock-ext1 { sai1_mclk: clock-sai-mclk1 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <0>; + clock-frequency = <0>; clock-output-names = "sai1_mclk"; }; sai2_mclk: clock-sai-mclk2 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <0>; + clock-frequency = <0>; clock-output-names = "sai2_mclk"; }; sai3_mclk: clock-sai-mclk3 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <0>; + clock-frequency = <0>; clock-output-names = "sai3_mclk"; }; sai4_mclk: clock-sai-mclk4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <0>; + clock-frequency = <0>; clock-output-names = "sai4_mclk"; }; sai5_mclk: clock-sai-mclk5 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency= <0>; + clock-frequency = <0>; clock-output-names = "sai5_mclk"; }; @@ -1212,7 +1212,7 @@ usdhc1: mmc@42850000 { assigned-clock-rates = <400000000>; bus-width = <8>; fsl,tuning-start-tap = <1>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; status = "disabled"; }; @@ -1229,7 +1229,7 @@ usdhc2: mmc@42860000 { assigned-clock-rates = <400000000>; bus-width = <4>; fsl,tuning-start-tap = <1>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; status = "disabled"; }; @@ -1246,7 +1246,7 @@ usdhc3: mmc@428b0000 { assigned-clock-rates = <400000000>; bus-width = <4>; fsl,tuning-start-tap = <1>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; status = "disabled"; }; }; @@ -1846,9 +1846,9 @@ pcie0: pcie@4c300000 { <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, <&hsio_blk_ctl 0>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; - assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPLL>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; assigned-clock-rates = <3600000000>, <100000000>, <10000000>; assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; @@ -1880,9 +1880,9 @@ pcie0_ep: pcie-ep@4c300000 { <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; - assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPLL>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; assigned-clock-rates = <3600000000>, <100000000>, <10000000>; assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; @@ -1920,9 +1920,9 @@ pcie1: pcie@4c380000 { <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, <&hsio_blk_ctl 0>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; - assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPLL>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; assigned-clock-rates = <3600000000>, <100000000>, <10000000>; assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; @@ -1956,9 +1956,9 @@ pcie1_ep: pcie-ep@4c380000 { <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; - assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPLL>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; assigned-clock-rates = <3600000000>, <100000000>, <10000000>; assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; From d4c743c5b7b42550a5eab0d9ab63ba7511f7e21e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 19 Aug 2025 16:34:05 -0300 Subject: [PATCH 289/931] ARM: dts: vf: Change the pinctrl node name fsl,vf610-iomuxc.yaml references pinctrl.yaml, which only allows the node to be either 'pinctrl' or 'pinmux'. Change the node name to 'pinctrl' to fix the following dt-schema warning: iomuxc@40048000' does not match '^(pinctrl|pinmux)(@[0-9a-f]+)?$' Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/vf/vfxxx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi index 124003c0be26..19de9506e0c8 100644 --- a/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi +++ b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi @@ -304,7 +304,7 @@ qspi0: spi@40044000 { status = "disabled"; }; - iomuxc: iomuxc@40048000 { + iomuxc: pinctrl@40048000 { compatible = "fsl,vf610-iomuxc"; reg = <0x40048000 0x1000>; }; From e00664c9c6f94efef9b91b5c296a8d978efd056a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 19 Aug 2025 16:40:18 -0300 Subject: [PATCH 290/931] ARM: dts: vf: Change the NAND controller node name fsl,vf610-nfc.yaml references nand-controller.yaml, which only allows the node to be 'nand-controller'. Change it accordingly to fix the following dt-schema warning: $nodename:0: 'nand@400e0000' does not match '^nand-controller(@.*)?' Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/vf/vfxxx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi index 19de9506e0c8..568d81807c81 100644 --- a/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi +++ b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi @@ -682,7 +682,7 @@ can1: can@400d4000 { status = "disabled"; }; - nfc: nand@400e0000 { + nfc: nand-controller@400e0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,vf610-nfc"; From e479b8477f99448db3728ac08f140cedf1ac9ec4 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 19 Aug 2025 15:44:07 -0400 Subject: [PATCH 291/931] ARM: dts: vf610: add grp surfix to pinctrl Add grp surfix for pinctrl to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dtb: pinctrl@40048000 (fsl,vf610-iomuxc): i2c0grp-gpio: {'fsl,pins': [[144, 0, 0, 0, 12738, 148, 0, 0, 0, 12738]], 'phandle': 19} is not of type 'array' from schema $id: http://devicetree.org/schemas/gpio/gpio-consumer.yaml# Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts | 8 ++++---- arch/arm/boot/dts/nxp/vf/vf610-zii-dev.dtsi | 14 +++++++------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts index 029f49be40e3..be6147239362 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-b.dts @@ -412,13 +412,13 @@ &mdio1 { }; &iomuxc { - pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 { + pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0-grp { fsl,pins = < VF610_PAD_PTE27__GPIO_132 0x33e2 >; }; - pinctrl_gpio_spi0: pinctrl-gpio-spi0 { + pinctrl_gpio_spi0: pinctrl-gpio-spi0-grp { fsl,pins = < VF610_PAD_PTB22__GPIO_44 0x33e2 VF610_PAD_PTB21__GPIO_43 0x33e2 @@ -428,7 +428,7 @@ VF610_PAD_PTB18__GPIO_40 0x33e2 >; }; - pinctrl_mdio_mux: pinctrl-mdio-mux { + pinctrl_mdio_mux: pinctrl-mdio-mux-grp { fsl,pins = < VF610_PAD_PTA18__GPIO_8 0x31c2 VF610_PAD_PTA19__GPIO_9 0x31c2 @@ -437,7 +437,7 @@ VF610_PAD_PTB3__GPIO_25 0x31c2 >; }; - pinctrl_pca9554_22: pinctrl-pca95540-22 { + pinctrl_pca9554_22: pinctrl-pca95540-22-grp { fsl,pins = < VF610_PAD_PTB28__GPIO_98 0x219d >; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-zii-dev.dtsi b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev.dtsi index ce5e52896b19..91cc496ffb90 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-zii-dev.dtsi +++ b/arch/arm/boot/dts/nxp/vf/vf610-zii-dev.dtsi @@ -335,7 +335,7 @@ VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 >; }; - pinctrl_gpio_spi0: pinctrl-gpio-spi0 { + pinctrl_gpio_spi0: pinctrl-gpio-spi0-grp { fsl,pins = < VF610_PAD_PTB22__GPIO_44 0x33e2 VF610_PAD_PTB21__GPIO_43 0x33e2 @@ -345,19 +345,19 @@ VF610_PAD_PTB18__GPIO_40 0x33e2 >; }; - pinctrl_gpio_switch0: pinctrl-gpio-switch0 { + pinctrl_gpio_switch0: pinctrl-gpio-switch0-grp { fsl,pins = < VF610_PAD_PTB5__GPIO_27 0x219d >; }; - pinctrl_gpio_switch1: pinctrl-gpio-switch1 { + pinctrl_gpio_switch1: pinctrl-gpio-switch1-grp { fsl,pins = < VF610_PAD_PTB4__GPIO_26 0x219d >; }; - pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset { + pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset-grp { fsl,pins = < VF610_PAD_PTE14__GPIO_119 0x31c2 >; @@ -370,7 +370,7 @@ VF610_PAD_PTB15__I2C0_SDA 0x37ff >; }; - pinctrl_i2c0_gpio: i2c0grp-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { fsl,pins = < VF610_PAD_PTB14__GPIO_36 0x31c2 VF610_PAD_PTB15__GPIO_37 0x31c2 @@ -392,7 +392,7 @@ VF610_PAD_PTA23__I2C2_SDA 0x37ff >; }; - pinctrl_leds_debug: pinctrl-leds-debug { + pinctrl_leds_debug: pinctrl-leds-debug-grp { fsl,pins = < VF610_PAD_PTD20__GPIO_74 0x31c2 >; @@ -436,7 +436,7 @@ VF610_PAD_PTD22__UART2_RX 0x21a1 >; }; - pinctrl_usb_vbus: pinctrl-usb-vbus { + pinctrl_usb_vbus: pinctrl-usb-vbus-grp { fsl,pins = < VF610_PAD_PTA16__GPIO_6 0x31c2 >; From 58c4544f1c3f0a1ac07e2d3173cf52593f07fa4b Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 19 Aug 2025 15:44:09 -0400 Subject: [PATCH 292/931] ARM: dts: vfxxx: add arm,num-irq-priority-bits for nvic Add arm,num-irq-priority-bits(4) for nvic to fix below CHECK_DTB warnings: arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dtb: interrupt-controller@e000e100 (arm,armv7m-nvic): 'arm,num-irq-priority-bits' is a required property from schema $id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml# Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/vf/vf610m4.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi b/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi index 2bb331a87721..648d219e1d0e 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi +++ b/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi @@ -55,3 +55,7 @@ / { &mscm_ir { interrupt-parent = <&nvic>; }; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; From 5a796a700ff8a26b8c17bfa5b789dd24ce19c3b6 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Thu, 21 Aug 2025 19:08:28 +0800 Subject: [PATCH 293/931] arm64: dts: imx95: add fsl,phy-tx-vref-tune-percent tuning properties for USB3 PHY Add it to improve USB signal quality. Signed-off-by: Xu Yang Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 1 + arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index 3c23022923e6..148243470dd4 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -1099,6 +1099,7 @@ &usb3_phy { fsl,phy-pcs-tx-swing-full-percent = <100>; fsl,phy-tx-preemp-amp-tune-microamp = <600>; fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-tx-vref-tune-percent = <100>; status = "okay"; port { diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 1a9454ea531d..84ac7d5a31c3 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -643,6 +643,7 @@ &usb3_phy { fsl,phy-pcs-tx-swing-full-percent = <100>; fsl,phy-tx-preemp-amp-tune-microamp = <600>; fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-tx-vref-tune-percent = <100>; orientation-switch; status = "okay"; From 90741cc5bebd7671be43959f5cbbc32700867a50 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:16:34 +0200 Subject: [PATCH 294/931] arm64: dts: marvell: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 2 +- arch/arm64/boot/dts/marvell/cn9132-clearfog.dts | 4 ++-- arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index 605f5be1538c..4878773883c9 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -322,7 +322,7 @@ spi1: spi@805a8000 { nand: nand-controller@805b0000 { compatible = "marvell,ac5-nand-controller"; - reg = <0x0 0x805b0000 0x0 0x00000054>; + reg = <0x0 0x805b0000 0x0 0x00000054>; #address-cells = <0x1>; #size-cells = <0x0>; interrupts = ; diff --git a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts index 0f53745a6fa0..c872c8eca518 100644 --- a/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts +++ b/arch/arm64/boot/dts/marvell/cn9132-clearfog.dts @@ -559,7 +559,7 @@ led@2 { }; &cp2_ethernet { - status = "okay"; + status = "okay"; }; /* SRDS #2 - 5GE */ @@ -572,7 +572,7 @@ &cp2_eth0 { }; &cp2_gpio1 { - pinctrl-names= "default"; + pinctrl-names = "default"; pinctrl-0 = <&cp2_rsvd9_pins>; /* J21 */ diff --git a/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi b/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi index afc041c1c448..1c9996d8cb24 100644 --- a/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi @@ -442,7 +442,7 @@ tpm@0 { reg = <0>; compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; spi-max-frequency = <10000000>; - pinctrl-names = "default"; + pinctrl-names = "default"; pinctrl-0 = <&cp1_tpm_irq_pins>; interrupt-parent = <&cp1_gpio1>; interrupts = <17 IRQ_TYPE_LEVEL_LOW>; From 70bb21cbc8c704c664b5d3ea417f3e35376fc229 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Mon, 28 Jul 2025 10:29:48 +0000 Subject: [PATCH 295/931] arm64: dts: rockchip: Add naneng-combphy for RK3528 Rockchip RK3528 ships a naneng-combphy that is shared by PCIe and USB 3.0 controllers. Describe it and the pipe-phy grf which it depends on. Signed-off-by: Yao Zi Link: https://lore.kernel.org/r/20250728102947.38984-8-ziyao@disroot.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 54fa8089c4d3..58c8977249be 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -417,6 +417,11 @@ vpu_grf: syscon@ff340000 { reg = <0x0 0xff340000 0x0 0x8000>; }; + pipe_phy_grf: syscon@ff348000 { + compatible = "rockchip,rk3528-pipe-phy-grf", "syscon"; + reg = <0x0 0xff348000 0x0 0x8000>; + }; + vo_grf: syscon@ff360000 { compatible = "rockchip,rk3528-vo-grf", "syscon"; reg = <0x0 0xff360000 0x0 0x10000>; @@ -1085,6 +1090,25 @@ dmac: dma-controller@ffd60000 { #dma-cells = <1>; arm,pl330-periph-burst; }; + + combphy: phy@ffdc0000 { + compatible = "rockchip,rk3528-naneng-combphy"; + reg = <0x0 0xffdc0000 0x0 0x10000>; + assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>; + assigned-clock-rates = <100000000>; + clocks = <&cru CLK_REF_PCIE_INNER_PHY>, + <&cru PCLK_PCIE_PHY>, + <&cru PCLK_PIPE_GRF>; + clock-names = "ref", "apb", "pipe"; + power-domains = <&power RK3528_PD_VPU>; + resets = <&cru SRST_PCIE_PIPE_PHY>, + <&cru SRST_P_PCIE_PHY>; + reset-names = "phy", "apb"; + #phy-cells = <1>; + rockchip,pipe-grf = <&vpu_grf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf>; + status = "disabled"; + }; }; }; From d0fd848949eece04a3b935f5a80566fb013428c3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:17:37 +0200 Subject: [PATCH 296/931] ARM: dts: microchip: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' or '{' characters. Signed-off-by: Krzysztof Kozlowski Acked-by: Nicolas Ferre Link: https://lore.kernel.org/r/20250819131736.86862-2-krzysztof.kozlowski@linaro.org Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts | 2 +- arch/arm/boot/dts/microchip/sama7d65.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 7eaf6ca233ec..c14c52936ecc 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -346,7 +346,7 @@ pinctrl_gmac0_txck_default: gmac0-txck-default { bias-pull-up; }; - pinctrl_i2c10_default: i2c10-default{ + pinctrl_i2c10_default: i2c10-default { pinmux = , ; bias-pull-up; diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index c191acc2c89f..84bac1d29421 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -91,7 +91,7 @@ secumod: security-module@e0004000 { }; sfrbu: sfr@e0008000 { - compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; + compatible = "microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; reg = <0xe0008000 0x20>; }; From 44189ccdfc2c96af4b06303c265030cda0e0bf51 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:16:55 +0200 Subject: [PATCH 297/931] arm64: dts: ti: k3-am6548: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250819131651.86569-8-krzysztof.kozlowski@linaro.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts index b829f4bcab69..adf4da7dfa2d 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts @@ -145,7 +145,7 @@ &main_spi0 { pinctrl-0 = <&main_spi0_pins>; #address-cells = <1>; - #size-cells= <0>; + #size-cells = <0>; }; &mcu_spi0 { From 04f1c432b7ae38415a1cf374f39954d5a612c23a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:33:10 +0200 Subject: [PATCH 298/931] arm64: dts: ti: k3-j721s2: Add default PCI interrupt controller address cells Add missing address-cells 0 to the PCI interrupt node to silence W=1 warning: k3-j721s2-main.dtsi:1431.3-1434.29: Warning (interrupt_map): /bus@100000/pcie@2910000:interrupt-map: Missing property '#address-cells' in node /bus@100000/pcie@2910000/interrupt-controller, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250822133309.312189-2-krzysztof.kozlowski@linaro.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 726374dc8795..0ad752975acd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1437,6 +1437,7 @@ pcie1_rc: pcie@2910000 { pcie1_intc: interrupt-controller { interrupt-controller; + #address-cells = <0>; #interrupt-cells = <1>; interrupt-parent = <&gic500>; interrupts = ; From 76397d42e248335aa41acbf0af6d096220605202 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Tue, 19 Aug 2025 16:27:00 +0530 Subject: [PATCH 299/931] arm64: dts: ti: k3-am69-sk: Switch to PCIe Multilink + USB configuration The SERDES0 instance of SERDES on the AM69 SoC is a Cadence Torrent SERDES and it has 4 lanes which are allocated in the following manner: Lane0 and Lane1 to PCIe1 Lane2 to PCIe3 Lane3 to USB0 Until [0], the Cadence Torrent SERDES driver only supported configuring the SERDES for a PCIe + USB configuration whereby all lanes of the SERDES configured for PCIe will operate at the same speed. As a result, PCIe1 and PCIe3 instances of PCIe will either fall down to a common speed based on the PCIe peers that they are each connected to, or, the PCIe link could fail to be setup. Since [0] enables support for PCIe Multilink + USB configuration, it is now possible for the SERDES lanes allocated to PCIe1 and PCIe3 to link up and operate at different speeds. USB continues to remain functional. Hence, update the 'serdes0' node as well as the 'pcie1_rc' and 'pcie3_rc' nodes to switch to the PCIe Multilink + USB configuration that is now supported by the Cadence Torrent SERDES driver. [0]: commit 351e07e6b2ec ("phy: cadence-torrent: Add PCIe multilink + USB with same SSC register config for 100 MHz refclk") Signed-off-by: Siddharth Vadapalli Link: https://patch.msgid.link/20250819105717.372893-1-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 612ac27643d2..f4f7b89bf0d2 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -1321,12 +1321,20 @@ &serdes_wiz0 { &serdes0 { status = "okay"; - serdes0_pcie_link: phy@0 { + serdes0_pcie1_link: phy@0 { reg = <0>; - cdns,num-lanes = <3>; + cdns,num-lanes = <2>; #phy-cells = <0>; cdns,phy-type = ; - resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>; + resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; + }; + + serdes0_pcie3_link: phy@2 { + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 3>; }; serdes0_usb_link: phy@3 { @@ -1364,7 +1372,7 @@ &pcie0_rc { &pcie1_rc { status = "okay"; reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; + phys = <&serdes0_pcie1_link>; phy-names = "pcie-phy"; num-lanes = <2>; }; @@ -1372,7 +1380,7 @@ &pcie1_rc { &pcie3_rc { status = "okay"; reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; - phys = <&serdes0_pcie_link>; + phys = <&serdes0_pcie3_link>; phy-names = "pcie-phy"; num-lanes = <1>; }; From 0e3f3d7c7ae3dec5ff52325915e3efcbce652a82 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 7 Jul 2025 18:49:00 +0200 Subject: [PATCH 300/931] dt-bindings: soc: rockchip: add rk3576 mipi dcphy syscon RK3576 CSI and DSI support requires the GRF for its DC-PHY. The "general register files" provide additional setting-bits outside the regular ip-block reg-space. Acked-by: "Rob Herring (Arm)" Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250707164906.1445288-8-heiko@sntech.de --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 1ab0b092e2a5..6a94c271a6b1 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -31,6 +31,7 @@ properties: - rockchip,rk3568-usb2phy-grf - rockchip,rk3576-bigcore-grf - rockchip,rk3576-cci-grf + - rockchip,rk3576-dcphy-grf - rockchip,rk3576-gpu-grf - rockchip,rk3576-hdptxphy-grf - rockchip,rk3576-litcore-grf From 21bc1a7fcea4635a49f6b2eff3e4c661e80e8f43 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 7 Jul 2025 18:49:03 +0200 Subject: [PATCH 301/931] arm64: dts: rockchip: add mipi-dcphy to rk3576 Add the MIPI-DC-phy node to the RK3576, that will be used by the one DSI2 controller and hopefully in some future also for camera input. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250707164906.1445288-11-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index f28c5a3e4f4c..0536aa8c3cb7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -966,6 +966,12 @@ hdptxphy_grf: syscon@26032000 { reg = <0x0 0x26032000 0x0 0x100>; }; + mipidcphy_grf: syscon@26034000 { + compatible = "rockchip,rk3576-dcphy-grf", "syscon"; + reg = <0x0 0x26034000 0x0 0x2000>; + clocks = <&cru PCLK_PMUPHY_ROOT>; + }; + vo1_grf: syscon@26036000 { compatible = "rockchip,rk3576-vo1-grf", "syscon"; reg = <0x0 0x26036000 0x0 0x100>; @@ -2563,6 +2569,22 @@ uart11: serial@2afd0000 { status = "disabled"; }; + mipidcphy: phy@2b020000 { + compatible = "rockchip,rk3576-mipi-dcphy"; + reg = <0x0 0x2b020000 0x0 0x10000>; + clocks = <&cru PCLK_MIPI_DCPHY>, + <&cru CLK_PHY_REF_SRC>; + clock-names = "pclk", "ref"; + resets = <&cru SRST_M_MIPI_DCPHY>, + <&cru SRST_P_MIPI_DCPHY>, + <&cru SRST_P_DCPHY_GRF>, + <&cru SRST_S_MIPI_DCPHY>; + reset-names = "m_phy", "apb", "grf", "s_phy"; + rockchip,grf = <&mipidcphy_grf>; + #phy-cells = <1>; + status = "disabled"; + }; + combphy0_ps: phy@2b050000 { compatible = "rockchip,rk3576-naneng-combphy"; reg = <0x0 0x2b050000 0x0 0x100>; From e51828f80df99a2899e263b750cada6426f14c92 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 7 Jul 2025 18:49:04 +0200 Subject: [PATCH 302/931] arm64: dts: rockchip: add the dsi controller to rk3576 The RK3576 comes with one DSI2 controllers based on the same newer Synopsis IP as the ones on the RK3588. Add the necessary node for it. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250707164906.1445288-12-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 28 ++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 0536aa8c3cb7..93143e63898e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1389,6 +1389,34 @@ sai6: sai@27d50000 { status = "disabled"; }; + dsi: dsi@27d80000 { + compatible = "rockchip,rk3576-mipi-dsi2"; + reg = <0x0 0x27d80000 0x0 0x10000>; + interrupts = ; + clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; + clock-names = "pclk", "sys"; + power-domains = <&power RK3576_PD_VO0>; + resets = <&cru SRST_P_DSIHOST0>; + reset-names = "apb"; + phys = <&mipidcphy PHY_TYPE_DPHY>; + phy-names = "dcphy"; + rockchip,grf = <&vo0_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi_in: port@0 { + reg = <0>; + }; + + dsi_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi: hdmi@27da0000 { compatible = "rockchip,rk3576-dw-hdmi-qp"; reg = <0x0 0x27da0000 0x0 0x20000>; From 3d5c0c21d86fed05caeae43549e0c13ddd203c31 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 7 Jul 2025 18:49:05 +0200 Subject: [PATCH 303/931] arm64: dts: rockchip: add vcc3v3-lcd-s0 regulator to roc-rk3576-pc This fixed regulator is described by the schematics as being part of the baseboard and its output supply is then routed to the 30pin DSI connector on the board. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250707164906.1445288-13-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts index d4e437ea6cd8..d0ab1d1e0e11 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-roc-pc.dts @@ -107,6 +107,18 @@ vcc1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 { vin-supply = <&vcc_1v8_s3>; }; + vcc3v3_lcd_s0: regulator-vcc3v3-lcd-s0 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwren_h>; + regulator-name = "vcc3v3-lcd-s0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + vcc3v3_pcie: regulator-vcc3v3-pcie { compatible = "regulator-fixed"; enable-active-high; @@ -715,6 +727,10 @@ rtc_int_l: rtc-int-l { }; power { + lcd_pwren_h: lcd-pwren-h { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5vd_en: vcc5vd-en { rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; }; From e0d48bea315a4beef9e76c8d6ba7bc95948582cc Mon Sep 17 00:00:00 2001 From: Raymond Hackley Date: Tue, 8 Jul 2025 12:21:42 +0000 Subject: [PATCH 304/931] ARM: dts: qcom: msm8226-samsung-ms013g: Add touch keys Touch keys feature on Galaxy Grand 2 is provided by Zinitix touchscreen. Add property linux,keycodes to enable touch keys. Signed-off-by: Raymond Hackley Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250708122118.157791-1-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts index 2ecc5983d365..08b50dc63923 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts @@ -144,6 +144,8 @@ touchscreen@20 { pinctrl-0 = <&tsp_int_default>; pinctrl-names = "default"; + + linux,keycodes = ; }; }; From 340e57306a4aeaaa64f294553caa25453cc4c48d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 4 Jul 2025 19:31:56 +0300 Subject: [PATCH 305/931] arm64: dts: qcom: sc8180x: modernize MDSS device definition Follow the lead of other platforms and update DT description of the MDSS device: - Use generic node names (dislpay-subsystem, display-controller, phy) instead of the platform-specific ones (mdss, mdp, dsi-phy) - Add platform-specific compatible string to DSI controllers. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250704-mdss-schema-v1-4-e978e4e73e14@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 836ac9455147..70c87c79e132 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2940,7 +2940,7 @@ camcc: clock-controller@ad00000 { #power-domain-cells = <1>; }; - mdss: mdss@ae00000 { + mdss: display-subsystem@ae00000 { compatible = "qcom,sc8180x-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; @@ -2980,7 +2980,7 @@ &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; - mdss_mdp: mdp@ae01000 { + mdss_mdp: display-controller@ae01000 { compatible = "qcom,sc8180x-dpu"; reg = <0 0x0ae01000 0 0x8f000>, <0 0x0aeb0000 0 0x3000>; @@ -3074,7 +3074,8 @@ opp-460000000 { }; mdss_dsi0: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sc8180x-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; @@ -3140,7 +3141,7 @@ opp-358000000 { }; }; - mdss_dsi0_phy: dsi-phy@ae94400 { + mdss_dsi0_phy: phy@ae94400 { compatible = "qcom,dsi-phy-7nm"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, @@ -3160,7 +3161,8 @@ mdss_dsi0_phy: dsi-phy@ae94400 { }; mdss_dsi1: dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sc8180x-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; reg-names = "dsi_ctrl"; @@ -3207,7 +3209,7 @@ mdss_dsi1_out: endpoint { }; }; - mdss_dsi1_phy: dsi-phy@ae96400 { + mdss_dsi1_phy: phy@ae96400 { compatible = "qcom,dsi-phy-7nm"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, From b9a185198f96259311543b30d884d8c01da913f7 Mon Sep 17 00:00:00 2001 From: Aleksandrs Vinarskis Date: Tue, 1 Jul 2025 20:35:53 +0200 Subject: [PATCH 306/931] arm64: dts: qcom: x1e80100-pmics: Disable pm8010 by default pm8010 is a camera specific PMIC, and may not be present on some devices. These may instead use a dedicated vreg for this purpose (Dell XPS 9345, Dell Inspiron..) or use USB webcam instead of a MIPI one alltogether (Lenovo Thinbook 16, Lenovo Yoga..). Disable pm8010 by default, let platforms that actually have one onboard enable it instead. Cc: stable@vger.kernel.org Fixes: 2559e61e7ef4 ("arm64: dts: qcom: x1e80100-pmics: Add the missing PMICs") Reviewed-by: Bryan O'Donoghue Reviewed-by: Johan Hovold Reviewed-by: Konrad Dybcio Signed-off-by: Aleksandrs Vinarskis Link: https://lore.kernel.org/r/20250701183625.1968246-2-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi index e3888bc143a0..621890ada153 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi @@ -475,6 +475,8 @@ pm8010: pmic@c { #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + pm8010_temp_alarm: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; From 71b12166a2be511482226b21105f1952cd8b7fa5 Mon Sep 17 00:00:00 2001 From: Pengyu Luo Date: Thu, 12 Jun 2025 15:57:23 +0800 Subject: [PATCH 307/931] arm64: dts: qcom: sc8280xp: Describe GPI DMA controller nodes SPI on SC8280XP requires DMA (GSI) mode to function properly. Without it, SPI controllers fall back to FIFO mode, which causes: [ 0.901296] geni_spi 898000.spi: error -ENODEV: Failed to get tx DMA ch [ 0.901305] geni_spi 898000.spi: FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode ... [ 45.605974] goodix-spi-hid spi0.0: SPI transfer timed out [ 45.605988] geni_spi 898000.spi: Can't set CS when prev xfer running [ 46.621555] spi_master spi0: failed to transfer one message from queue [ 46.621568] spi_master spi0: noqueue transfer failed [ 46.621577] goodix-spi-hid spi0.0: spi transfer error: -110 [ 46.621585] goodix-spi-hid spi0.0: probe with driver goodix-spi-hid failed with error -110 Therefore, describe GPI DMA controller nodes for qup{0,1,2}, and describe DMA channels for SPI and I2C, UART is excluded for now, as it does not yet support this mode. Note that, since there is no public schematic, this is derived from Windows drivers. The drivers do not expose any DMA channel mask information, so all available channels are enabled. Signed-off-by: Pengyu Luo Link: https://lore.kernel.org/r/20250612075724.707457-3-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 368 +++++++++++++++++++++++++ 1 file changed, 368 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 421693208af0..fe62b5476054 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -912,6 +913,32 @@ gpu_speed_bin: gpu-speed-bin@18b { }; }; + gpi_dma2: dma-controller@800000 { + compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0xfff>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0xb6 0x0>; + + status = "disabled"; + }; + qup2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x2000>; @@ -939,6 +966,12 @@ i2c16: i2c@880000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, + <&gpi_dma2 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -955,6 +988,12 @@ spi16: spi@880000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -971,6 +1010,12 @@ i2c17: i2c@884000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -987,6 +1032,12 @@ spi17: spi@884000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1017,6 +1068,12 @@ i2c18: i2c@888000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1033,6 +1090,12 @@ spi18: spi@888000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1067,6 +1130,12 @@ i2c19: i2c@88c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1083,6 +1152,12 @@ spi19: spi@88c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1099,6 +1174,12 @@ i2c20: i2c@890000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1115,6 +1196,12 @@ spi20: spi@890000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1131,6 +1218,12 @@ i2c21: i2c@894000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1147,6 +1240,12 @@ spi21: spi@894000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1163,6 +1262,12 @@ i2c22: i2c@898000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, + <&gpi_dma2 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1179,6 +1284,12 @@ spi22: spi@898000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1195,6 +1306,12 @@ i2c23: i2c@89c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, + <&gpi_dma2 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1211,10 +1328,43 @@ spi23: spi@89c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, + <&gpi_dma2 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; }; + gpi_dma0: dma-controller@900000 { + compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x00900000 0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <13>; + dma-channel-mask = <0x1fff>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x576 0x0>; + + status = "disabled"; + }; + qup0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x6000>; @@ -1242,6 +1392,12 @@ i2c0: i2c@980000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1258,6 +1414,12 @@ spi0: spi@980000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1274,6 +1436,12 @@ i2c1: i2c@984000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1290,6 +1458,12 @@ spi1: spi@984000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1306,6 +1480,12 @@ i2c2: i2c@988000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1322,6 +1502,12 @@ spi2: spi@988000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1352,6 +1538,12 @@ i2c3: i2c@98c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1368,6 +1560,12 @@ spi3: spi@98c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1384,6 +1582,12 @@ i2c4: i2c@990000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1400,6 +1604,12 @@ spi4: spi@990000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1416,6 +1626,12 @@ i2c5: i2c@994000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1432,6 +1648,12 @@ spi5: spi@994000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1448,6 +1670,12 @@ i2c6: i2c@998000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1464,6 +1692,12 @@ spi6: spi@998000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1480,6 +1714,12 @@ i2c7: i2c@99c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1496,10 +1736,42 @@ spi7: spi@99c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; }; + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x00a00000 0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0xfff>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x96 0x0>; + + status = "disabled"; + }; + qup1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x00ac0000 0 0x6000>; @@ -1527,6 +1799,12 @@ i2c8: i2c@a80000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1543,6 +1821,12 @@ spi8: spi@a80000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1559,6 +1843,12 @@ i2c9: i2c@a84000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1575,6 +1865,12 @@ spi9: spi@a84000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1591,6 +1887,12 @@ i2c10: i2c@a88000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1607,6 +1909,12 @@ spi10: spi@a88000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1623,6 +1931,12 @@ i2c11: i2c@a8c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1639,6 +1953,12 @@ spi11: spi@a8c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1655,6 +1975,12 @@ i2c12: i2c@a90000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1671,6 +1997,12 @@ spi12: spi@a90000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1687,6 +2019,12 @@ i2c13: i2c@a94000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1703,6 +2041,12 @@ spi13: spi@a94000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1719,6 +2063,12 @@ i2c14: i2c@a98000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1735,6 +2085,12 @@ spi14: spi@a98000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1751,6 +2107,12 @@ i2c15: i2c@a9c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; @@ -1767,6 +2129,12 @@ spi15: spi@a9c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + status = "disabled"; }; }; From 013d01811a1ea4ce0f676e4110f94c80271586b9 Mon Sep 17 00:00:00 2001 From: Pengyu Luo Date: Thu, 12 Jun 2025 15:57:24 +0800 Subject: [PATCH 308/931] arm64: dts: qcom: sc8280xp: Enable GPI DMA Enable GPI DMA for sc8280xp based devices. Signed-off-by: Pengyu Luo Link: https://lore.kernel.org/r/20250612075724.707457-4-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 12 ++++++++++++ arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts | 12 ++++++++++++ .../boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 12 ++++++++++++ .../boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 12 ++++++++++++ .../boot/dts/qcom/sc8280xp-microsoft-blackrock.dts | 12 ++++++++++++ 5 files changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index bcbd668f562f..490e970c54a2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -495,6 +495,18 @@ &dispcc0 { status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + &gpu { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts index 1667c7157057..0374251d3329 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts @@ -586,6 +586,18 @@ &dispcc0 { status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + &gpu { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 0b479e98ba38..73447a2e897e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -708,6 +708,18 @@ &dispcc0 { status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + &gpu { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index d00889fa6f0b..aeed3ef152eb 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -448,6 +448,18 @@ &dispcc1 { status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + &gpu { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index 29efbef5ef69..a40dccd70dfd 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -565,6 +565,18 @@ &dispcc0 { status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + &gpu { status = "okay"; From c6fa3429cf3ccd806a4059706ebd0f2221b5b965 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Wed, 18 Jun 2025 22:14:09 +0200 Subject: [PATCH 309/931] arm64: dts: qcom: ipq9574: use 'pcie' as node name for 'pcie0' The PCI controller at address 28000000 supports PCIe only, so use 'pcie' as node name for that. This ensures that all PCIe controller instance nodes are using the same name. Signed-off-by: Gabor Juhos Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250618-ipq9574-pcie0-name-v1-1-f0a8016ea504@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 815b5f9540b8..8ae4b165c315 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -1161,7 +1161,7 @@ pcie2: pcie@20000000 { status = "disabled"; }; - pcie0: pci@28000000 { + pcie0: pcie@28000000 { compatible = "qcom,pcie-ipq9574"; reg = <0x28000000 0xf1d>, <0x28000f20 0xa8>, From cb2347ed822f77c6b04011ee3140f7483d206018 Mon Sep 17 00:00:00 2001 From: Casey Connolly Date: Thu, 19 Jun 2025 16:55:10 +0200 Subject: [PATCH 310/931] arm64: dts: qcom: sdm845-oneplus-*: set constant-charge-current-max-microamp Set the maximum constant charge current to use for this battery. While the battery is likely comfortably capable of 4A or so, OnePlus didn't include a secondary charger IC for parallel charging (instead they have their proprietary Dash Charging). It's possible that this value could be safely increased after some testing (and when we have support for modelling the charger as a cooling device properly), but for now this value is acceptable. This is references from qcom,usb-icl-ua property in the downstream vendor devicetree. Signed-off-by: Casey Connolly Link: https://lore.kernel.org/r/20250619-smb2-smb5-support-v1-2-ac5dec51b6e1@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts | 8 ++++++++ arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index cd5546b69d13..bfbc3e6e71bb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -18,6 +18,14 @@ battery: battery { charge-full-design-microamp-hours = <3300000>; voltage-min-design-microvolt = <3400000>; voltage-max-design-microvolt = <4400000>; + + /* + * Typical designs have multiple charger ICs which can handle more + * current but the OnePlus 6/T do not, hence the lower limit. This + * does not apply when using the Dash Charger, however this is not + * yet supported. + */ + constant-charge-current-max-microamp = <1800000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index b4212626b429..7e75decfda05 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -18,6 +18,14 @@ battery: battery { charge-full-design-microamp-hours = <3700000>; voltage-min-design-microvolt = <3400000>; voltage-max-design-microvolt = <4400000>; + + /* + * Typical designs have multiple charger ICs which can handle more + * current but the OnePlus 6/T do not, hence the lower limit. This + * does not apply when using the Dash Charger, however this is not + * yet supported. + */ + constant-charge-current-max-microamp = <1800000>; }; }; From 40f7b64fac9d7d37b8db750909321fa2b0b7eda3 Mon Sep 17 00:00:00 2001 From: Kamal Wadhwa Date: Fri, 20 Jun 2025 20:59:57 +0530 Subject: [PATCH 311/931] arm64: dts: qcom: sm8550: Correct the min/max voltages for vreg_l6n_3p3 Voltage regulator 'vreg_l6n_3p3' max-microvolt prop is currently configured at 3304000uV in different sm8550 board files. However this is not a valid voltage value for 'pmic5_pldo502ln' type voltage regulators. Check below the max value(3200mV) in the regulator summary for min/max used as 2800mV/3304mV in DT:- logs: [ 0.294781] vreg_l6n_3p3: Setting 2800000-3304000uV regulator summary: regulator use open bypass opmode voltage current min max --------------------------------------------------------------------- .. vreg_l6n_3p3 0 0 0 normal 2800mV 0mA 2800mV 3200mV .. Correct the min/max value to 3200000uV, as that is the closest valid value to 3.3V and Hardware team has also confirmed that its good to support the consumers(camera sensors) of this regulator. Reviewed-by: Neil Armstrong Signed-off-by: Kamal Wadhwa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250620-sm8550-correct-vreg_l6n_3p3-vol-v2-1-b397f3e91d7b@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 9dfb248f9ab5..162afaffa48b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -859,8 +859,8 @@ vreg_l5n_1p8: ldo5 { vreg_l6n_3p3: ldo6 { regulator-name = "vreg_l6n_3p3"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3304000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; regulator-initial-mode = ; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index fdcecd41297d..f5aa349f3194 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -626,8 +626,8 @@ vreg_l5n_1p8: ldo5 { vreg_l6n_3p3: ldo6 { regulator-name = "vreg_l6n_3p3"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3304000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; regulator-initial-mode = ; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 49438a7e77ce..c079c02550b8 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -702,8 +702,8 @@ vreg_l5n_1p8: ldo5 { vreg_l6n_3p3: ldo6 { regulator-name = "vreg_l6n_3p3"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3304000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; regulator-initial-mode = ; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts index 7d29a57a2b54..b4ef40ae2cd9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -487,8 +487,8 @@ vreg_l5n_1p8: ldo5 { vreg_l6n_3p3: ldo6 { regulator-name = "vreg_l6n_3p3"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3304000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; regulator-initial-mode = ; }; From a300bbd90c3b3c43b1668e1923cd170fc8d5fc89 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Tue, 1 Jul 2025 12:10:13 +0200 Subject: [PATCH 312/931] arm64: dts: qcom: ipq9574-rdp433: remove unused 'sdc-default-state' Since commit 8140d10568a8 ("arm64: dts: qcom: ipq9574: Remove eMMC node"), the 'sdc-default-state' pinctrl state is not used so remove that. Signed-off-by: Gabor Juhos Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250701-rdp433-remove-sdc-state-v1-1-ca0f156a42d5@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 32 --------------------- 1 file changed, 32 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index fa7bb521e786..5a546a14998b 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -128,36 +128,4 @@ wake-n-pins { bias-pull-up; }; }; - - sdc_default_state: sdc-default-state { - clk-pins { - pins = "gpio5"; - function = "sdc_clk"; - drive-strength = <8>; - bias-disable; - }; - - cmd-pins { - pins = "gpio4"; - function = "sdc_cmd"; - drive-strength = <8>; - bias-pull-up; - }; - - data-pins { - pins = "gpio0", "gpio1", "gpio2", - "gpio3", "gpio6", "gpio7", - "gpio8", "gpio9"; - function = "sdc_data"; - drive-strength = <8>; - bias-pull-up; - }; - - rclk-pins { - pins = "gpio10"; - function = "sdc_rclk"; - drive-strength = <8>; - bias-pull-down; - }; - }; }; From d7d28bcc2038bd66a4f5912b8e1b162f5ba6faa8 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 15 Aug 2025 18:46:04 +0300 Subject: [PATCH 313/931] arm64: dts: qcom: use DT label for DSI outputs Instead of keeping a copy of the DT tree going down to the DSI output endpoint use the label to reference it directly, making DTs less error-prone. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250815-msm-dsi-outs-v2-1-3662704e833f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 12 +++------ arch/arm64/boot/dts/qcom/sc7180-idp.dts | 12 +++------ .../qcom/sc7180-trogdor-quackingstick.dtsi | 12 +++------ .../dts/qcom/sc7180-trogdor-wormdingler.dtsi | 12 +++------ arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 24 ++++++----------- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 26 +++++++------------ .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 12 +++------ arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 24 ++++++----------- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 12 +++------ .../dts/qcom/sm8650-hdk-display-card.dtso | 15 +++-------- 10 files changed, 52 insertions(+), 109 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 33ecbc81997c..d99448a0732d 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -725,15 +725,11 @@ &mdss_dsi0 { qcom,dual-dsi-mode; qcom,master-dsi; #endif +}; - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; }; &mdss_dsi0_phy { diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 0146fb0036d4..19cf419cf531 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -323,15 +323,11 @@ panel0_in: endpoint { }; }; }; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <&panel0_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; }; &mdss_dsi0_phy { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi index ff8996b4de4e..4bea97e4246e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -90,15 +90,11 @@ panel_in: endpoint { }; }; }; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; }; &sdhc_2 { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index 17908c936520..6078308694ac 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -148,15 +148,11 @@ panel_in: endpoint { }; }; }; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; }; &pm6150_adc { diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 3ec2c7864f1e..8abf3e909502 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -534,15 +534,11 @@ &mdss_dsi0 { qcom,dual-dsi-mode; qcom,master-dsi; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; }; &mdss_dsi0_phy { @@ -560,15 +556,11 @@ &mdss_dsi1 { <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; status = "okay"; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_b>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi1_out { + remote-endpoint = <<9611_b>; + data-lanes = <0 1 2 3>; }; &mdss_dsi1_phy { diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index a98756e8b965..63d2993536ad 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -445,15 +445,6 @@ &mdss_dsi0 { qcom,dual-dsi-mode; qcom,master-dsi; - ports { - port@1 { - endpoint { - remote-endpoint = <&truly_in_0>; - data-lanes = <0 1 2 3>; - }; - }; - }; - panel@0 { compatible = "truly,nt35597-2K-display"; reg = <0>; @@ -483,6 +474,11 @@ truly_in_1: endpoint { }; }; +&mdss_dsi0_out { + remote-endpoint = <&truly_in_0>; + data-lanes = <0 1 2 3>; +}; + &mdss_dsi0_phy { status = "okay"; vdds-supply = <&vdda_mipi_dsi0_pll>; @@ -497,15 +493,11 @@ &mdss_dsi1 { /* DSI1 is slave, so use DSI0 clocks */ assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <&truly_in_1>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi1_out { + remote-endpoint = <&truly_in_1>; + data-lanes = <0 1 2 3>; }; &mdss_dsi1_phy { diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 480192c86fb7..90efbb7e3799 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -598,15 +598,11 @@ &mdss { &mdss_dsi0 { status = "okay"; vdda-supply = <&vreg_l26a_1p2>; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <&sn65dsi86_in_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <&sn65dsi86_in_a>; + data-lanes = <0 1 2 3>; }; &mdss_dsi0_phy { diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index e1e294f0f462..0339a572f34d 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -478,15 +478,11 @@ &mdss_dsi0 { qcom,dual-dsi-mode; qcom,master-dsi; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; }; &mdss_dsi0_phy { @@ -504,15 +500,11 @@ &mdss_dsi1 { <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; status = "okay"; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_b>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi1_out { + remote-endpoint = <<9611_b>; + data-lanes = <0 1 2 3>; }; &mdss_dsi1_phy { diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index f9de0e49fa24..24a8c91e9f70 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -385,15 +385,11 @@ &cdsp { &mdss_dsi0 { vdda-supply = <&vreg_l6b_1p2>; status = "okay"; +}; - ports { - port@1 { - endpoint { - remote-endpoint = <<9611_a>; - data-lanes = <0 1 2 3>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; }; &mdss_dsi0_phy { diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso b/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso index cb102535838d..5a594d7311a7 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk-display-card.dtso @@ -60,19 +60,10 @@ panel0_in: endpoint { }; }; }; +}; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - - mdss_dsi0_out: endpoint { - remote-endpoint = <&panel0_in>; - }; - }; - }; +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; }; &spi4 { From be541b843114d5c92f89b367b51f5dfb76a99124 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 16 Aug 2025 17:00:20 +0300 Subject: [PATCH 314/931] arm64: dts: qcom: sm6150: move standard clocks to SoC dtsi Follow the example of all other platforms and reference standard clocks (XO, sleep) from the SoC DT even if they are defined in the board DT file. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250816-qcs615-move-clocks-v1-1-bc5665d6e1c3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 14 -------------- arch/arm64/boot/dts/qcom/sm6150.dtsi | 5 +++++ 2 files changed, 5 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 59582d3dc4c4..e663343df75d 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -288,12 +288,6 @@ vreg_l17a: ldo17 { }; }; -&gcc { - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; -}; - &pcie { perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; @@ -369,10 +363,6 @@ &remoteproc_cdsp { status = "okay"; }; -&rpmhcc { - clocks = <&xo_board_clk>; -}; - &tlmm { bt_en_state: bt-en-state { pins = "gpio85"; @@ -523,7 +513,3 @@ &ufs_mem_phy { status = "okay"; }; - -&watchdog { - clocks = <&sleep_clk>; -}; diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi index b66bc13c0b5e..69e013a17c9f 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -495,6 +495,9 @@ soc: soc@0 { gcc: clock-controller@100000 { compatible = "qcom,qcs615-gcc"; reg = <0 0x00100000 0 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; #clock-cells = <1>; #reset-cells = <1>; @@ -3676,6 +3679,7 @@ watchdog: watchdog@17c10000 { compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt"; reg = <0x0 0x17c10000 0x0 0x1000>; interrupts = ; + clocks = <&sleep_clk>; }; timer@17c20000 { @@ -3765,6 +3769,7 @@ apps_bcm_voter: bcm-voter { rpmhcc: clock-controller { compatible = "qcom,qcs615-rpmh-clk"; + clocks = <&xo_board_clk>; clock-names = "xo"; #clock-cells = <1>; From f9c36698db91780eed4ee3a90794bda2a4252166 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 14 Aug 2025 14:25:23 +0530 Subject: [PATCH 315/931] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock Add support for video, camera, display and gpu clock controller nodes for QCS615 platform. Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20250814-qcs615-mm-cpu-dt-v6-v6-1-a06f69928ab5@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 57 ++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi index 69e013a17c9f..d72647f0045b 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -3,7 +3,11 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include #include +#include +#include #include #include #include @@ -1662,6 +1666,19 @@ data-pins { }; }; + gpucc: clock-controller@5090000 { + compatible = "qcom,qcs615-gpucc"; + reg = <0 0x05090000 0 0x9000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GPLL0>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x06002000 0x0 0x1000>, @@ -3523,6 +3540,46 @@ gem_noc: interconnect@9680000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + videocc: clock-controller@ab00000 { + compatible = "qcom,qcs615-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,qcs615-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,qcs615-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <0>, + <0>, + <0>, + <0>, + <0>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,qcs615-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, From fecc6e0b0260279cd1508903db62f370ef4530d4 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 14 Aug 2025 14:25:24 +0530 Subject: [PATCH 316/931] arm64: dts: qcom: qcs615: Add CPU scaling clock node Add cpufreq-hw node to support CPU frequency scaling. Reviewed-by: Dmitry Baryshkov Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20250814-qcs615-mm-cpu-dt-v6-v6-2-a06f69928ab5@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi index d72647f0045b..47ace8d414c0 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -36,6 +36,8 @@ cpu0: cpu@0 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_0>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; l2_0: l2-cache { @@ -56,6 +58,8 @@ cpu1: cpu@100 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_100>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_100: l2-cache { compatible = "cache"; @@ -75,6 +79,8 @@ cpu2: cpu@200 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_200>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_200: l2-cache { compatible = "cache"; @@ -94,6 +100,8 @@ cpu3: cpu@300 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_300>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_300: l2-cache { compatible = "cache"; @@ -113,6 +121,8 @@ cpu4: cpu@400 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_400>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_400: l2-cache { compatible = "cache"; @@ -132,6 +142,8 @@ cpu5: cpu@500 { capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&l2_500>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; l2_500: l2-cache { compatible = "cache"; @@ -151,6 +163,8 @@ cpu6: cpu@600 { capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <404>; next-level-cache = <&l2_600>; + clocks = <&cpufreq_hw 1>; + qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; l2_600: l2-cache { @@ -171,6 +185,8 @@ cpu7: cpu@700 { capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <404>; next-level-cache = <&l2_700>; + clocks = <&cpufreq_hw 1>; + qcom,freq-domain = <&cpufreq_hw 1>; l2_700: l2-cache { compatible = "cache"; @@ -4142,6 +4158,19 @@ compute-cb@6 { }; }; }; + + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw"; + reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + }; arch_timer: timer { From e2f4e0f1410d737061523852614ce492a9471265 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:17:18 +0200 Subject: [PATCH 317/931] ARM: dts: qcom: apq8064-mako: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' or '{' characters. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250819131717.86713-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts b/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts index c187c6875bc6..fdbbc1389297 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-lg-nexus4-mako.dts @@ -34,7 +34,7 @@ reserved-memory { #size-cells = <1>; ranges; - ramoops@88d00000{ + ramoops@88d00000 { compatible = "ramoops"; reg = <0x88d00000 0x100000>; record-size = <0x20000>; @@ -326,8 +326,8 @@ pm8921_s3: s3 { */ pm8921_s4: s4 { regulator-always-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; qcom,switch-mode-frequency = <1600000>; bias-pull-down; qcom,force-mode = ; From 69f0611c8937e343d4ef9b8349d9dd39aceb1636 Mon Sep 17 00:00:00 2001 From: Shashank Maurya Date: Thu, 21 Aug 2025 23:24:28 +0530 Subject: [PATCH 318/931] arm64: dts: qcom: lemans-evk: Enable Display Port Lemans EVK board has two mini-DP connectors, connected to EDP0 and EDP1 phys. Other EDP phys are available on expansion connectors for the mezzanine boards. Enable EDP0 and EDP1 along with their corresponding PHYs. Signed-off-by: Shashank Maurya Signed-off-by: Prahlad Valluru Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250821-enable-iq9-dp-v3-1-8c3a719e3b9a@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 70 +++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/lemans.dtsi | 12 +++++ 2 files changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 669ac52f4cf6..9e415012140b 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -22,6 +22,30 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + edp0-connector { + compatible = "dp-connector"; + label = "EDP0"; + type = "mini"; + + port { + edp0_connector_in: endpoint { + remote-endpoint = <&mdss0_dp0_out>; + }; + }; + }; + + edp1-connector { + compatible = "dp-connector"; + label = "EDP1"; + type = "mini"; + + port { + edp1_connector_in: endpoint { + remote-endpoint = <&mdss0_dp1_out>; + }; + }; + }; }; &apps_rsc { @@ -253,6 +277,52 @@ vreg_l8e: ldo8 { }; }; +&mdss0 { + status = "okay"; +}; + +&mdss0_dp0 { + pinctrl-0 = <&dp0_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss0_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp0_connector_in>; +}; + +&mdss0_dp0_phy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&mdss0_dp1 { + pinctrl-0 = <&dp1_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss0_dp1_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp1_connector_in>; +}; + +&mdss0_dp1_phy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 64f5378c6a47..7c9972c28a54 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -5004,6 +5004,18 @@ tlmm: pinctrl@f000000 { gpio-ranges = <&tlmm 0 0 149>; wakeup-parent = <&pdc>; + dp0_hot_plug_det: dp0-hot-plug-det-state { + pins = "gpio101"; + function = "edp0_hot"; + bias-disable; + }; + + dp1_hot_plug_det: dp1-hot-plug-det-state { + pins = "gpio102"; + function = "edp1_hot"; + bias-disable; + }; + qup_i2c0_default: qup-i2c0-state { pins = "gpio20", "gpio21"; function = "qup0_se0"; From 316294bb6695a43a9181973ecd4e6fb3e576a9f7 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 21 Aug 2025 10:15:09 +0200 Subject: [PATCH 319/931] arm64: dts: qcom: sdm845: Fix slimbam num-channels/ees Reading the hardware registers of the &slimbam on RB3 reveals that the BAM supports only 23 pipes (channels) and supports 4 EEs instead of 2. This hasn't caused problems so far since nothing is using the extra channels, but attempting to use them would lead to crashes. The bam_dma driver might warn in the future if the num-channels in the DT are wrong, so correct the properties in the DT to avoid future regressions. Cc: stable@vger.kernel.org Fixes: 27ca1de07dc3 ("arm64: dts: qcom: sdm845: add slimbus nodes") Signed-off-by: Stephan Gerhold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250821-sdm845-slimbam-channels-v1-1-498f7d46b9ee@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 828b55cb6baf..02536114edb8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5396,11 +5396,11 @@ slimbam: dma-controller@17184000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0 0x17184000 0 0x2a000>; - num-channels = <31>; + num-channels = <23>; interrupts = ; #dma-cells = <1>; qcom,ee = <1>; - qcom,num-ees = <2>; + qcom,num-ees = <4>; iommus = <&apps_smmu 0x1806 0x0>; }; From 013632a410873d2ac538deb981780407917b2200 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 20 Aug 2025 16:12:34 +0200 Subject: [PATCH 320/931] arm64: dts: qcom: sm8750-mtp: Add speaker Soundwire port mapping Add appropriate mappings of Soundwire ports of WSA883x speaker to correctly map the Speaker ports to the WSA macro ports. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250820141233.216713-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 75cfbb510be5..946ba53fe63a 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -938,6 +938,13 @@ left_spkr: speaker@0,1 { sound-name-prefix = "SpkrLeft"; #thermal-sensor-cells = <0>; vdd-supply = <&vreg_l15b_1p8>; + /* + * WSA8835 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L) + * WSA8835 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP) + * WSA8835 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST) + * WSA8835 Port 4 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI) + */ + qcom,port-mapping = <1 2 3 10>; }; /* WSA883x, right/back speaker */ @@ -951,6 +958,13 @@ right_spkr: speaker@0,2 { sound-name-prefix = "SpkrRight"; #thermal-sensor-cells = <0>; vdd-supply = <&vreg_l15b_1p8>; + /* + * WSA8835 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R) + * WSA8835 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP) + * WSA8835 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST) + * WSA8835 Port 4 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI) + */ + qcom,port-mapping = <4 5 6 11>; }; }; From 40db99f1b6aaf47064aa3891c92eae01da215d6e Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 20 Aug 2025 11:49:22 +0200 Subject: [PATCH 321/931] arm64: dts: qcom: sm8550: switch to interrupt-cells 4 to add PPI partitions The ARM PMUs shares the same per-cpu (PPI) interrupt, so we need to switch to interrupt-cells = <4> in the GIC node to allow adding an interrupt partition map phandle as the 4th cell value for GIC_PPI interrupts. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250820-topic-sm8550-upstream-pmu-ppi-4-cells-v1-1-a8915672e996@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 580 +++++++++++++-------------- 1 file changed, 290 insertions(+), 290 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 38d139d1dd4a..2ebe02e2ca8c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -399,22 +399,22 @@ memory@a0000000 { pmu-a510 { compatible = "arm,cortex-a510-pmu"; - interrupts = ; + interrupts = ; }; pmu-a710 { compatible = "arm,cortex-a710-pmu"; - interrupts = ; + interrupts = ; }; pmu-a715 { compatible = "arm,cortex-a715-pmu"; - interrupts = ; + interrupts = ; }; pmu-x3 { compatible = "arm,cortex-x3-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -842,7 +842,7 @@ gcc: clock-controller@100000 { ipcc: mailbox@408000 { compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; reg = <0 0x00408000 0 0x1000>; - interrupts = ; + interrupts = ; interrupt-controller; #interrupt-cells = <3>; #mbox-cells = <2>; @@ -852,18 +852,18 @@ gpi_dma2: dma-controller@800000 { compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; reg = <0 0x00800000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; dma-channels = <12>; dma-channel-mask = <0x3e>; iommus = <&apps_smmu 0x436 0>; @@ -891,7 +891,7 @@ i2c8: i2c@880000 { clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -914,7 +914,7 @@ spi8: spi@880000 { reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -941,7 +941,7 @@ i2c9: i2c@884000 { clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c9_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -964,7 +964,7 @@ spi9: spi@884000 { reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -991,7 +991,7 @@ i2c10: i2c@888000 { clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1014,7 +1014,7 @@ spi10: spi@888000 { reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1041,7 +1041,7 @@ i2c11: i2c@88c000 { clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c11_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1064,7 +1064,7 @@ spi11: spi@88c000 { reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1091,7 +1091,7 @@ i2c12: i2c@890000 { clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c12_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1114,7 +1114,7 @@ spi12: spi@890000 { reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1141,7 +1141,7 @@ i2c13: i2c@894000 { clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1164,7 +1164,7 @@ spi13: spi@894000 { reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1191,7 +1191,7 @@ uart14: serial@898000 { clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; - interrupts = ; + interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -1209,7 +1209,7 @@ i2c15: i2c@89c000 { clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c15_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1232,7 +1232,7 @@ spi15: spi@89c000 { reg = <0 0x0089c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1271,7 +1271,7 @@ i2c_hub_0: i2c@980000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c0_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1292,7 +1292,7 @@ i2c_hub_1: i2c@984000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c1_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1313,7 +1313,7 @@ i2c_hub_2: i2c@988000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c2_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1334,7 +1334,7 @@ i2c_hub_3: i2c@98c000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c3_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1355,7 +1355,7 @@ i2c_hub_4: i2c@990000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c4_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1376,7 +1376,7 @@ i2c_hub_5: i2c@994000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c5_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1397,7 +1397,7 @@ i2c_hub_6: i2c@998000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c6_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1418,7 +1418,7 @@ i2c_hub_7: i2c@99c000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c7_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1439,7 +1439,7 @@ i2c_hub_8: i2c@9a0000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c8_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1460,7 +1460,7 @@ i2c_hub_9: i2c@9a4000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names = "default"; pinctrl-0 = <&hub_i2c9_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1478,18 +1478,18 @@ gpi_dma1: dma-controller@a00000 { compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; reg = <0 0x00a00000 0 0x60000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; dma-channels = <12>; dma-channel-mask = <0x1e>; iommus = <&apps_smmu 0xb6 0>; @@ -1520,7 +1520,7 @@ i2c0: i2c@a80000 { clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1543,7 +1543,7 @@ spi0: spi@a80000 { reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1570,7 +1570,7 @@ i2c1: i2c@a84000 { clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c1_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1593,7 +1593,7 @@ spi1: spi@a84000 { reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1620,7 +1620,7 @@ i2c2: i2c@a88000 { clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1643,7 +1643,7 @@ spi2: spi@a88000 { reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1670,7 +1670,7 @@ i2c3: i2c@a8c000 { clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c3_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1693,7 +1693,7 @@ spi3: spi@a8c000 { reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1720,7 +1720,7 @@ i2c4: i2c@a90000 { clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c4_data_clk>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1743,7 +1743,7 @@ spi4: spi@a90000 { reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1770,7 +1770,7 @@ i2c5: i2c@a94000 { clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_data_clk>; - interrupts = ; + interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -1793,7 +1793,7 @@ spi5: spi@a94000 { reg = <0 0x00a94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1820,7 +1820,7 @@ i2c6: i2c@a98000 { clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_data_clk>; - interrupts = ; + interrupts = ; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -1843,7 +1843,7 @@ spi6: spi@a98000 { reg = <0 0x00a98000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1870,7 +1870,7 @@ uart7: serial@a9c000 { clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_default>; - interrupts = ; + interrupts = ; interconnect-names = "qup-core", "qup-config"; interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, @@ -1961,15 +1961,15 @@ pcie0: pcie@1c00000 { linux,pci-domain = <0>; num-lanes = <2>; - interrupts = , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1981,10 +1981,10 @@ pcie0: pcie@1c00000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, @@ -2122,15 +2122,15 @@ pcie1: pcie@1c08000 { linux,pci-domain = <1>; num-lanes = <2>; - interrupts = , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -2142,10 +2142,10 @@ pcie1: pcie@1c08000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */ + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, @@ -2280,7 +2280,7 @@ pcie1_phy: phy@1c0e000 { cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; - interrupts = ; + interrupts = ; #dma-cells = <1>; qcom,ee = <0>; qcom,num-ees = <4>; @@ -2327,7 +2327,7 @@ ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8550-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>; - interrupts = ; + interrupts = ; phys = <&ufs_mem_phy>; phy-names = "ufsphy"; lanes-per-direction = <2>; @@ -2440,7 +2440,7 @@ gpu: gpu@3d00000 { "cx_mem", "cx_dbgc"; - interrupts = ; + interrupts = ; iommus = <&adreno_smmu 0 0x0>, <&adreno_smmu 1 0x0>; @@ -2521,8 +2521,8 @@ gmu: gmu@3d6a000 { <0x0 0x0b280000 0x0 0x10000>; reg-names = "gmu", "rscc", "gmu_pdc"; - interrupts = , - ; + interrupts = , + ; interrupt-names = "hfi", "gmu"; clocks = <&gpucc GPU_CC_AHB_CLK>, @@ -2583,32 +2583,32 @@ adreno_smmu: iommu@3da0000 { reg = <0x0 0x03da0000 0x0 0x40000>; #iommu-cells = <2>; #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, @@ -2633,8 +2633,8 @@ ipa: ipa@3f40000 { "ipa-shared", "gsi"; - interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ipa", @@ -2666,7 +2666,7 @@ remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sm8550-mpss-pas"; reg = <0x0 0x04080000 0x0 0x10000>; - interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, @@ -2854,7 +2854,7 @@ lpass_wsa2macro: codec@6aa0000 { swr3: soundwire@6ab0000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06ab0000 0 0x10000>; - interrupts = ; + interrupts = ; clocks = <&lpass_wsa2macro>; clock-names = "iface"; label = "WSA2"; @@ -2898,7 +2898,7 @@ lpass_rxmacro: codec@6ac0000 { swr1: soundwire@6ad0000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06ad0000 0 0x10000>; - interrupts = ; + interrupts = ; clocks = <&lpass_rxmacro>; clock-names = "iface"; label = "RX"; @@ -2956,7 +2956,7 @@ lpass_wsamacro: codec@6b00000 { swr0: soundwire@6b10000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06b10000 0 0x10000>; - interrupts = ; + interrupts = ; clocks = <&lpass_wsamacro>; clock-names = "iface"; label = "WSA"; @@ -2986,8 +2986,8 @@ swr0: soundwire@6b10000 { swr2: soundwire@6d30000 { compatible = "qcom,soundwire-v2.0.0"; reg = <0 0x06d30000 0 0x10000>; - interrupts = , - ; + interrupts = , + ; interrupt-names = "core", "wakeup"; clocks = <&lpass_txmacro>; clock-names = "iface"; @@ -3169,8 +3169,8 @@ sdhc_2: mmc@8804000 { compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; - interrupts = , - ; + interrupts = , + ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, @@ -3225,7 +3225,7 @@ iris: video-codec@aa00000 { compatible = "qcom,sm8550-iris"; reg = <0 0x0aa00000 0 0xf0000>; - interrupts = ; + interrupts = ; power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, <&videocc VIDEO_CC_MVS0_GDSC>, @@ -3317,7 +3317,7 @@ videocc: clock-controller@aaf0000 { cci0: cci@ac15000 { compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; reg = <0 0x0ac15000 0 0x1000>; - interrupts = ; + interrupts = ; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, @@ -3350,7 +3350,7 @@ cci0_i2c1: i2c-bus@1 { cci1: cci@ac16000 { compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; reg = <0 0x0ac16000 0 0x1000>; - interrupts = ; + interrupts = ; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, @@ -3376,7 +3376,7 @@ cci1_i2c0: i2c-bus@0 { cci2: cci@ac17000 { compatible = "qcom,sm8550-cci", "qcom,msm8996-cci"; reg = <0 0x0ac17000 0 0x1000>; - interrupts = ; + interrupts = ; power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, @@ -3521,24 +3521,24 @@ camss: isp@acb7000 { "vfe_lite_cphy_rx", "vfe_lite_csid"; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; interrupt-names = "csid0", "csid1", "csid2", @@ -3635,7 +3635,7 @@ mdss: display-subsystem@ae00000 { reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; - interrupts = ; + interrupts = ; interrupt-controller; #interrupt-cells = <1>; @@ -4107,9 +4107,9 @@ usb_1: usb@a600000 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; @@ -4192,8 +4192,8 @@ tsens0: thermal-sensor@c271000 { reg = <0 0x0c271000 0 0x1000>, /* TM */ <0 0x0c222000 0 0x1000>; /* SROT */ #qcom,sensors = <16>; - interrupts = , - ; + interrupts = , + ; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; @@ -4203,8 +4203,8 @@ tsens1: thermal-sensor@c272000 { reg = <0 0x0c272000 0 0x1000>, /* TM */ <0 0x0c223000 0 0x1000>; /* SROT */ #qcom,sensors = <16>; - interrupts = , - ; + interrupts = , + ; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; @@ -4214,8 +4214,8 @@ tsens2: thermal-sensor@c273000 { reg = <0 0x0c273000 0 0x1000>, /* TM */ <0 0x0c224000 0 0x1000>; /* SROT */ #qcom,sensors = <16>; - interrupts = , - ; + interrupts = , + ; interrupt-names = "uplow", "critical"; #thermal-sensor-cells = <1>; }; @@ -4259,7 +4259,7 @@ spmi_bus: spmi@c400000 { tlmm: pinctrl@f100000 { compatible = "qcom,sm8550-tlmm"; reg = <0 0x0f100000 0 0x300000>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -4953,103 +4953,103 @@ apps_smmu: iommu@15000000 { reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; dma-coherent; }; @@ -5058,11 +5058,11 @@ intc: interrupt-controller@17100000 { reg = <0 0x17100000 0 0x10000>, /* GICD */ <0 0x17180000 0 0x200000>; /* GICR * 8 */ ranges; - #interrupt-cells = <3>; + #interrupt-cells = <4>; interrupt-controller; #redistributor-regions = <1>; redistributor-stride = <0 0x40000>; - interrupts = ; + interrupts = ; #address-cells = <2>; #size-cells = <2>; @@ -5085,49 +5085,49 @@ frame@17421000 { reg = <0x17421000 0x1000>, <0x17422000 0x1000>; frame-number = <0>; - interrupts = , - ; + interrupts = , + ; }; frame@17423000 { reg = <0x17423000 0x1000>; frame-number = <1>; - interrupts = ; + interrupts = ; status = "disabled"; }; frame@17425000 { reg = <0x17425000 0x1000>; frame-number = <2>; - interrupts = ; + interrupts = ; status = "disabled"; }; frame@17427000 { reg = <0x17427000 0x1000>; frame-number = <3>; - interrupts = ; + interrupts = ; status = "disabled"; }; frame@17429000 { reg = <0x17429000 0x1000>; frame-number = <4>; - interrupts = ; + interrupts = ; status = "disabled"; }; frame@1742b000 { reg = <0x1742b000 0x1000>; frame-number = <5>; - interrupts = ; + interrupts = ; status = "disabled"; }; frame@1742d000 { reg = <0x1742d000 0x1000>; frame-number = <6>; - interrupts = ; + interrupts = ; status = "disabled"; }; }; @@ -5140,9 +5140,9 @@ apps_rsc: rsc@17a00000 { <0 0x17a20000 0 0x10000>, <0 0x17a30000 0 0x10000>; reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; - interrupts = , - , - ; + interrupts = , + , + ; qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = , , @@ -5239,9 +5239,9 @@ cpufreq_hw: cpufreq@17d91000 { reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; - interrupts = , - , - ; + interrupts = , + , + ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; #clock-cells = <1>; @@ -5250,7 +5250,7 @@ cpufreq_hw: cpufreq@17d91000 { pmu@24091000 { compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0 0x24091000 0 0x1000>; - interrupts = ; + interrupts = ; interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; @@ -5300,7 +5300,7 @@ opp-8 { pmu@240b6400 { compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x240b6400 0 0x600>; - interrupts = ; + interrupts = ; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; @@ -5356,7 +5356,7 @@ system-cache-controller@25000000 { "llcc3_base", "llcc_broadcast_base", "llcc_broadcast_and_base"; - interrupts = ; + interrupts = ; }; nsp_noc: interconnect@320c0000 { @@ -5370,7 +5370,7 @@ remoteproc_cdsp: remoteproc@32300000 { compatible = "qcom,sm8550-cdsp-pas"; reg = <0x0 0x32300000 0x0 0x10000>; - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, @@ -6552,9 +6552,9 @@ trip-point2 { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; From 4f97774ac2ee37d29adfd9732009729e1cbf7bdf Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 20 Aug 2025 11:49:23 +0200 Subject: [PATCH 322/931] arm64: dts: qcom: sm8550: add PPI interrupt partitions for the ARM PMUs The PMUs shares the same per-cpu (PPI) interrupt, so declare the proper interrupt partition maps and use the 4th interrupt cell to pass the partition phandle for each ARM PMU node. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250820-topic-sm8550-upstream-pmu-ppi-4-cells-v1-2-a8915672e996@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 2ebe02e2ca8c..1b7fbbdba2df 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -399,22 +399,22 @@ memory@a0000000 { pmu-a510 { compatible = "arm,cortex-a510-pmu"; - interrupts = ; + interrupts = ; }; pmu-a710 { compatible = "arm,cortex-a710-pmu"; - interrupts = ; + interrupts = ; }; pmu-a715 { compatible = "arm,cortex-a715-pmu"; - interrupts = ; + interrupts = ; }; pmu-x3 { compatible = "arm,cortex-x3-pmu"; - interrupts = ; + interrupts = ; }; psci { @@ -5066,6 +5066,24 @@ intc: interrupt-controller@17100000 { #address-cells = <2>; #size-cells = <2>; + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu3 &cpu4>; + }; + + ppi_cluster2: interrupt-partition-2 { + affinity = <&cpu5 &cpu6>; + }; + + ppi_cluster3: interrupt-partition-3 { + affinity = <&cpu7>; + }; + }; + gic_its: msi-controller@17140000 { compatible = "arm,gic-v3-its"; reg = <0 0x17140000 0 0x20000>; From 41b9f3dae105a3e54c3d94e8c0d67f857109e8fd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:17:19 +0200 Subject: [PATCH 323/931] arm64: dts: qcom: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250819131717.86713-4-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8998.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 2 +- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 4ddb56d63f8f..2c7d74d9388d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -717,7 +717,7 @@ pcie1: pcie@80000000 { max-link-speed = <2>; phys = <&pcie1_phy>; - phy-names ="pciephy"; + phy-names = "pciephy"; ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>, <0x02000000 0 0x80300000 0x80300000 0 0x10000000>; @@ -818,7 +818,7 @@ pcie0: pcie@a0000000 { max-link-speed = <2>; phys = <&pcie0_phy>; - phy-names ="pciephy"; + phy-names = "pciephy"; ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>, <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 0b0a9379cb05..5c75fba16ce2 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -3082,9 +3082,9 @@ mdss_dsi1_phy: phy@c996400 { mdss_hdmi: hdmi-tx@c9a0000 { compatible = "qcom,hdmi-tx-8998"; - reg = <0x0c9a0000 0x50c>, - <0x00780000 0x6220>, - <0x0c9e0000 0x2c>; + reg = <0x0c9a0000 0x50c>, + <0x00780000 0x6220>, + <0x0c9e0000 0x2c>; reg-names = "core_physical", "qfprom_physical", "hdcp_physical"; diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 3cf1d4bc7e4a..5edb137d1471 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -1100,7 +1100,7 @@ uart1: serial@984000 { <&qup_uart1_tx>, <&qup_uart1_rx>; pinctrl-names = "default"; interrupts = ; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; @@ -1267,7 +1267,7 @@ i2c4: i2c@990000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, @@ -1340,7 +1340,7 @@ i2c5: i2c@994000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, @@ -1413,7 +1413,7 @@ i2c6: i2c@998000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 9076d8eb4d50..03b63b987a18 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -701,7 +701,7 @@ &sound { pinctrl-names = "default"; status = "okay"; - audio-routing = "RX_BIAS", "MCLK", + audio-routing = "RX_BIAS", "MCLK", "AMIC2", "MIC BIAS2", /* Headset Mic */ "AMIC3", "MIC BIAS2", /* FM radio left Tx */ "AMIC4", "MIC BIAS2", /* FM radio right Tx */ From 59a4b94a8c46c71f6c7aac00c21dc781b525fd6d Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 19 Aug 2025 12:45:20 +0200 Subject: [PATCH 324/931] arm64: dts: qcom: x1e001de-devkit: Fix swapped USB MP repeaters The &eusb3_repeater belongs to the first port of the USB MP controller and the &eusb6_repeater belongs to the second. This is obvious if one looks at e.g. the CRD or the Dell XPS where only the second port of the USB MP is used: They only have the &eusb6_repeater and already specify it for the &usb_mp_hsphy1. Swap them to set the correct repeater for each of the USB ports. Fixes: d12fbd11c5a3 ("arm64: dts: qcom: x1e001de-devkit: Enable support for both Type-A USB ports") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250819-x1e80100-fix-usb-mp-repeaters-v1-1-0f8c186458d3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index 2d9627e6c798..a3323d03f644 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -1474,7 +1474,7 @@ &usb_mp_hsphy0 { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb6_repeater>; + phys = <&eusb3_repeater>; status = "okay"; }; @@ -1483,7 +1483,7 @@ &usb_mp_hsphy1 { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb3_repeater>; + phys = <&eusb6_repeater>; status = "okay"; }; From c3994b495111bd0ae663c63fc96a869678d03e6c Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 19 Aug 2025 12:45:21 +0200 Subject: [PATCH 325/931] arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: Fix swapped USB MP repeaters The &eusb3_repeater belongs to the first port of the USB MP controller and the &eusb6_repeater belongs to the second. This is obvious if one looks at e.g. the CRD or the Dell XPS where only the second port of the USB MP is used: They only have the &eusb6_repeater and already specify it for the &usb_mp_hsphy1. Swap them to set the correct repeater for each of the USB ports. Fixes: ffbf3a8be766 ("arm64: dts: qcom: x1e78100-t14s: Enable support for both Type-A USB ports") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250819-x1e80100-fix-usb-mp-repeaters-v1-2-0f8c186458d3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 4cf61c2a34e3..e04df29a8853 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -1543,7 +1543,7 @@ &usb_mp_hsphy0 { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb6_repeater>; + phys = <&eusb3_repeater>; status = "okay"; }; @@ -1552,7 +1552,7 @@ &usb_mp_hsphy1 { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb3_repeater>; + phys = <&eusb6_repeater>; status = "okay"; }; From d5d72e326762c24f2fbc48e5f223cb674cecad1a Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 19 Aug 2025 12:45:22 +0200 Subject: [PATCH 326/931] arm64: dts: qcom: x1e80100-asus-vivobook-s15: Fix swapped USB MP repeaters The &eusb3_repeater belongs to the first port of the USB MP controller and the &eusb6_repeater belongs to the second. This is obvious if one looks at e.g. the CRD or the Dell XPS where only the second port of the USB MP is used: They only have the &eusb6_repeater and already specify it for the &usb_mp_hsphy1. Swap them to set the correct repeater for each of the USB ports. Fixes: c0c46eea2444 ("arm64: dts: qcom: x1e80100-vivobook-s15: Enable USB-A ports") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250819-x1e80100-fix-usb-mp-repeaters-v1-3-0f8c186458d3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index 62eba17cdc87..b571e8349d3b 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -971,7 +971,7 @@ &usb_mp_hsphy0 { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb6_repeater>; + phys = <&eusb3_repeater>; status = "okay"; }; @@ -980,7 +980,7 @@ &usb_mp_hsphy1 { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb3_repeater>; + phys = <&eusb6_repeater>; status = "okay"; }; From 6dcc44fc695b11bf4e654774a7c865abf96a2af3 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 19 Aug 2025 12:45:23 +0200 Subject: [PATCH 327/931] arm64: dts: qcom: x1e80100-qcp: Fix swapped USB MP repeaters The &eusb3_repeater belongs to the first port of the USB MP controller and the &eusb6_repeater belongs to the second. This is obvious if one looks at e.g. the CRD or the Dell XPS where only the second port of the USB MP is used: They only have the &eusb6_repeater and already specify it for the &usb_mp_hsphy1. Swap them to set the correct repeater for each of the USB ports. Fixes: 9f53c3611960 ("arm64: dts: qcom: x1e78100-qcp: Enable Type-A USB ports labeled 3 and 4/6") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250819-x1e80100-fix-usb-mp-repeaters-v1-4-0f8c186458d3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 9369b76c668b..b02a66f0895e 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -1507,7 +1507,7 @@ &usb_mp_hsphy0 { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb6_repeater>; + phys = <&eusb3_repeater>; status = "okay"; }; @@ -1516,7 +1516,7 @@ &usb_mp_hsphy1 { vdd-supply = <&vreg_l2e_0p8>; vdda12-supply = <&vreg_l3e_1p2>; - phys = <&eusb3_repeater>; + phys = <&eusb6_repeater>; status = "okay"; }; From dc3f005e6b1f5b49ff70b98164badd664978d60e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:04:01 +0200 Subject: [PATCH 328/931] arm64: dts: qcom: ipq5424: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: ipq5424.dtsi:961.4-964.30: Warning (interrupt_map): /soc@0/pcie@50000000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@f200000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-1-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index bbb539dbdf5c..b1a86b54c30f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -565,6 +565,7 @@ intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; reg = <0 0xf200000 0 0x10000>, /* GICD */ <0 0xf240000 0 0x80000>; /* GICR * 4 regions */ + #address-cells = <0>; #interrupt-cells = <0x3>; interrupt-controller; #redistributor-regions = <1>; From 0eb765666714ea310439107bab3182430cc4d11d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:04:02 +0200 Subject: [PATCH 329/931] arm64: dts: qcom: lemans: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: lemans.dtsi:7623.3-7626.29: Warning (interrupt_map): /pcie@1c00000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@17a00000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-2-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 7c9972c28a54..99a566b42ef2 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -5878,6 +5878,7 @@ intc: interrupt-controller@17a00000 { reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; interrupts = ; #redistributor-regions = <1>; From d434b7198a115a54c5f28bdffb6b77196c85758c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:04:03 +0200 Subject: [PATCH 330/931] arm64: dts: qcom: msm8996: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: msm8996.dtsi:1931.5-1934.31: Warning (interrupt_map): /soc@0/bus@0/pcie@600000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@9bc0000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-3-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index f91605de4909..b5aab21ac525 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3766,6 +3766,7 @@ cbf: clock-controller@9a11000 { intc: interrupt-controller@9bc0000 { compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; #redistributor-regions = <1>; From 0325653b1adeb8f47dd46874e4fe8ec894a3bbb0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:04:04 +0200 Subject: [PATCH 331/931] arm64: dts: qcom: qcs404: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: qcs404.dtsi:1496.4-1499.30: Warning (interrupt_map): /soc@0/pcie@10000000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@b000000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-4-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 5a9df6b12305..4328c1dda898 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1312,6 +1312,7 @@ pil-reloc@94c { intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; From 6cfdee6dca1e5073b52eda54fceb193a80651576 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:04:05 +0200 Subject: [PATCH 332/931] arm64: dts: qcom: sc8180x: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: sc8180x.dtsi:1743.4-1746.30: Warning (interrupt_map): /soc@0/pcie@1c00000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@17a00000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-5-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 70c87c79e132..87aa5a91fbcd 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3723,6 +3723,7 @@ remoteproc_adsp_glink: glink-edge { intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ From b8159aaf5ece22de52276d75b8b7d5ec517fe207 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:04:06 +0200 Subject: [PATCH 333/931] arm64: dts: qcom: sm6150: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: sm6150.dtsi:1122.4-1125.30: Warning (interrupt_map): /soc@0/pcie@1c08000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@17a00000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-6-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi index 47ace8d414c0..53496241479a 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -3735,6 +3735,7 @@ intc: interrupt-controller@17a00000 { reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ interrupts = ; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; #redistributor-regions = <1>; From d0054c3e5b8f737cda22c4b7625b8979fa3c8310 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:04:07 +0200 Subject: [PATCH 334/931] arm64: dts: qcom: sm8150: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: sm8150.dtsi:1869.4-1872.30: Warning (interrupt_map): /soc@0/pcie@1c00000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@17a00000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-7-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 4b347ee32441..12e7b74cde52 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -4366,6 +4366,7 @@ compute-cb@5 { intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ From 3e17f489e3f46ffe21d3d9d769b75ddf24905707 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:04:08 +0200 Subject: [PATCH 335/931] arm64: dts: qcom: sm8250: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: sm8250.dtsi:2166.4-2169.30: Warning (interrupt_map): /soc@0/pcie@1c00000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@17a00000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-8-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 244339cfbed5..8e0eb802d68e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -6084,6 +6084,7 @@ compute-cb@5 { intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ From 9c18757804e66304ed0287ed874a3575c7cb77e4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:04:09 +0200 Subject: [PATCH 336/931] arm64: dts: qcom: sm8350: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: sm8350.dtsi:1554.4-1557.30: Warning (interrupt_map): /soc@0/pcie@1c00000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@17a00000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-9-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 9a4207ead615..acaf40298f2e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3544,6 +3544,7 @@ apps_smmu: iommu@15000000 { intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; #redistributor-regions = <1>; From 2f8c7b179f283876871b9359be3ed947c9c56b56 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:04:10 +0200 Subject: [PATCH 337/931] arm64: dts: qcom: Use GIC_SPI for interrupt-map for readability Decoding interrupt-map is tricky, because it consists of five components. Use known GIC_SPI define in final interrupt specifier component makes easier to read. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-10-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 16 +++++------ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 16 +++++------ arch/arm64/boot/dts/qcom/ipq5424.dtsi | 32 ++++++++++----------- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 +++--- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 +++++------ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 32 ++++++++++----------- arch/arm64/boot/dts/qcom/msm8996.dtsi | 24 ++++++++-------- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 16 +++++------ arch/arm64/boot/dts/qcom/sc7280.dtsi | 16 +++++------ arch/arm64/boot/dts/qcom/sc8180x.dtsi | 32 ++++++++++----------- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 40 +++++++++++++------------- arch/arm64/boot/dts/qcom/sdm845.dtsi | 16 +++++------ arch/arm64/boot/dts/qcom/sm8150.dtsi | 16 +++++------ arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++-------- arch/arm64/boot/dts/qcom/sm8350.dtsi | 16 +++++------ arch/arm64/boot/dts/qcom/sm8450.dtsi | 16 +++++------ arch/arm64/boot/dts/qcom/sm8550.dtsi | 16 +++++------ arch/arm64/boot/dts/qcom/sm8650.dtsi | 16 +++++------ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 24 ++++++++-------- 19 files changed, 196 insertions(+), 196 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 2c7d74d9388d..e88b52006566 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -745,10 +745,10 @@ pcie1: pcie@80000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 142 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 143 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 144 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, <&gcc GCC_PCIE1_AXI_M_CLK>, @@ -846,10 +846,10 @@ pcie0: pcie@a0000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, <&gcc GCC_PCIE0_AXI_M_CLK>, diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index bd28c490415f..45fc512a3bab 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -632,10 +632,10 @@ pcie1: pcie@18000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 412 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 413 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 414 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 415 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE3X2_AXI_M_CLK>, <&gcc GCC_PCIE3X2_AXI_S_CLK>, @@ -736,10 +736,10 @@ pcie0: pcie@20000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 36 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 37 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 38 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE3X1_0_AXI_M_CLK>, <&gcc GCC_PCIE3X1_0_AXI_S_CLK>, diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index b1a86b54c30f..67877fbbdf3a 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -856,10 +856,10 @@ pcie3: pcie@40000000 { #interrupt-cells = <1>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 479 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 480 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 481 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 482 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE3_AXI_M_CLK>, <&gcc GCC_PCIE3_AXI_S_CLK>, @@ -959,10 +959,10 @@ pcie2: pcie@50000000 { #interrupt-cells = <1>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 464 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 465 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 466 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 467 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, <&gcc GCC_PCIE2_AXI_S_CLK>, @@ -1062,10 +1062,10 @@ pcie1: pcie@60000000 { #interrupt-cells = <1>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 449 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 450 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 451 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 452 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, <&gcc GCC_PCIE1_AXI_S_CLK>, @@ -1165,10 +1165,10 @@ pcie0: pcie@70000000 { #interrupt-cells = <1>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 436 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 437 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, <&gcc GCC_PCIE0_AXI_S_CLK>, diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index bfe59b020841..40f1c262126e 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -906,10 +906,10 @@ pcie0: pcie@20000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, <&gcc GCC_PCIE0_AXI_M_CLK>, diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index fffb47ec2448..256e12cf6d54 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -867,13 +867,13 @@ pcie1: pcie@10000000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 142 + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 143 + <0 0 0 2 &intc 0 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 144 + <0 0 0 3 &intc 0 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 145 + <0 0 0 4 &intc 0 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, @@ -955,13 +955,13 @@ pcie0: pcie@20000000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 75 + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 78 + <0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 79 + <0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 83 + <0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 8ae4b165c315..86c9cb9fffc9 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -946,10 +946,10 @@ pcie1: pcie@10000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, <&gcc GCC_PCIE1_AXI_S_CLK>, @@ -1032,10 +1032,10 @@ pcie3: pcie@18000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 189 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 190 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 191 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 192 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE3_AXI_M_CLK>, <&gcc GCC_PCIE3_AXI_S_CLK>, @@ -1118,10 +1118,10 @@ pcie2: pcie@20000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 164 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 165 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 186 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 187 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, <&gcc GCC_PCIE2_AXI_S_CLK>, @@ -1203,10 +1203,10 @@ pcie0: pcie@28000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 75 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 78 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 79 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, <&gcc GCC_PCIE0_AXI_S_CLK>, diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index b5aab21ac525..c75b522f6eba 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1928,10 +1928,10 @@ pcie0: pcie@600000 { "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ pinctrl-names = "default", "sleep"; pinctrl-0 = <&pcie0_state_on>; @@ -2005,10 +2005,10 @@ pcie1: pcie@608000 { "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ pinctrl-names = "default", "sleep"; pinctrl-0 = <&pcie1_state_on>; @@ -2080,10 +2080,10 @@ pcie2: pcie@610000 { "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ pinctrl-names = "default", "sleep"; pinctrl-0 = <&pcie2_state_on>; diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index 38f7869616ff..96c4d2e06d9a 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -1303,10 +1303,10 @@ pcie0: pcie@1c00000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, @@ -1422,10 +1422,10 @@ pcie1: pcie@1c08000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0dd6a5c91d10..8561fc217229 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2240,10 +2240,10 @@ pcie0: pcie@1c00000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, @@ -2369,10 +2369,10 @@ pcie1: pcie@1c08000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 87aa5a91fbcd..b8a64bf372cc 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1740,10 +1740,10 @@ pcie0: pcie@1c00000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, @@ -1859,10 +1859,10 @@ pcie3: pcie@1c08000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, <&gcc GCC_PCIE_3_AUX_CLK>, @@ -1979,10 +1979,10 @@ pcie1: pcie@1c10000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, @@ -2099,10 +2099,10 @@ pcie2: pcie@1c18000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, <&gcc GCC_PCIE_2_AUX_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index fe62b5476054..225233a37a4f 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2177,10 +2177,10 @@ pcie4: pcie@1c00000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_4_AUX_CLK>, <&gcc GCC_PCIE_4_CFG_AHB_CLK>, @@ -2290,10 +2290,10 @@ pcie3b: pcie@1c08000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, @@ -2401,10 +2401,10 @@ pcie3a: pcie@1c10000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, @@ -2515,10 +2515,10 @@ pcie2b: pcie@1c18000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, @@ -2626,10 +2626,10 @@ pcie2a: pcie@1c20000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 02536114edb8..f322ebf3b4c2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2347,10 +2347,10 @@ pcie0: pcie@1c00000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, @@ -2472,10 +2472,10 @@ pcie1: pcie@1c08000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 12e7b74cde52..6860816db6d2 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1866,10 +1866,10 @@ pcie0: pcie@1c00000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, @@ -1981,10 +1981,10 @@ pcie1: pcie@1c08000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 8e0eb802d68e..6591b8172e08 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2163,10 +2163,10 @@ pcie0: pcie@1c00000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, @@ -2285,10 +2285,10 @@ pcie1: pcie@1c08000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, @@ -2412,10 +2412,10 @@ pcie2: pcie@1c10000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, <&gcc GCC_PCIE_2_AUX_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index acaf40298f2e..de1fae97ce44 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1551,10 +1551,10 @@ pcie0: pcie@1c00000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, @@ -1662,10 +1662,10 @@ pcie1: pcie@1c08000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 2baef6869ed7..b31c09ec61a9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1987,10 +1987,10 @@ pcie0: pcie@1c00000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, @@ -2151,10 +2151,10 @@ pcie1: pcie@1c08000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 1b7fbbdba2df..ee5970974255 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1981,10 +1981,10 @@ pcie0: pcie@1c00000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */ - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, @@ -2142,10 +2142,10 @@ pcie1: pcie@1c08000 { "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */ - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index d6794901f06b..7ffdd26ff614 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3629,10 +3629,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, iommu-map = <0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH 0>, - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH 0>, - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH 0>, - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; @@ -3809,10 +3809,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, iommu-map = <0 &apps_smmu 0x1480 0x1>, <0x100 &apps_smmu 0x1481 0x1>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH 0>, - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH 0>, - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH 0>, - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-map-mask = <0 0 0 0x7>; #interrupt-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index f293b13ecc0c..e61c9010a3f2 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3404,10 +3404,10 @@ pcie6a: pci@1bf8000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, @@ -3536,10 +3536,10 @@ pcie5: pci@1c00000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_5_AUX_CLK>, <&gcc GCC_PCIE_5_CFG_AHB_CLK>, @@ -3666,10 +3666,10 @@ pcie4: pci@1c08000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_PCIE_4_AUX_CLK>, <&gcc GCC_PCIE_4_CFG_AHB_CLK>, From ccc7f16ea2e33366f7b7005daad81e316f8cb6e4 Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Sat, 23 Aug 2025 14:43:51 +0200 Subject: [PATCH 338/931] arm64: dts: rockchip: Enable HDMI receiver on orangepi 5 plus MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable support for the HDMI input port found on the orangepi 5 plus. Signed-off-by: Maud Spierings Reviewed-by: Ondřej Jirman Link: https://lore.kernel.org/r/20250823-orangepi5-v1-2-ae77dd0e06d7@hotmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588-orangepi-5-plus.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts index 121e4d1c3fa5..345686c59a87 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts @@ -160,6 +160,17 @@ &hdmi1_sound { status = "okay"; }; +&hdmi_receiver_cma { + status = "okay"; +}; + +&hdmi_receiver { + hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; + pinctrl-names = "default"; + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -279,6 +290,12 @@ blue_led_pin: blue-led { }; }; + hdmirx { + hdmirx_hpd: hdmirx-5v-detection { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + ir-receiver { ir_receiver_pin: ir-receiver-pin { rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; From 3dc7ba3548acbfb657614db4ca70d9878bdfca23 Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Sat, 23 Aug 2025 14:43:52 +0200 Subject: [PATCH 339/931] arm64: dts: rockchip: Enable the NPU on the orangepi 5 boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the NPU and the PMIC that powers it. Signed-off-by: Maud Spierings Reviewed-by: Ondřej Jirman Link: https://lore.kernel.org/r/20250823-orangepi5-v1-3-ae77dd0e06d7@hotmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-orangepi-5.dtsi | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi index 91d56c34a1e4..ac1df223d6a2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi @@ -258,6 +258,28 @@ regulator-state-mem { }; }; +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + &i2c6 { clock-frequency = <400000>; status = "okay"; @@ -352,6 +374,40 @@ &pd_gpu { domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8_s0>; status = "okay"; From 178879625f0f10ff708728087d91a5fe79990ce2 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 21 Aug 2025 21:18:41 +0000 Subject: [PATCH 340/931] arm64: dts: rockchip: Enable more power domains for RK3528 Describe device power-domains and enable the PD_RKVENC, PD_VO and PD_VPU power-domains on RK3528. The PD_RKVDEC is used by RKVDEC and DDRPHY CRU, and is kept disabled to prevent a full system reset trying to read the rate of the SCMI_CLK_DDR clock. Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20250821211843.3051349-2-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 30 +++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 58c8977249be..db5dbcac7756 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -155,6 +155,7 @@ gpio1: gpio@ffaf0000 { gpio-ranges = <&pinctrl 0 32 32>; interrupt-controller; #interrupt-cells = <2>; + power-domains = <&power RK3528_PD_VPU>; }; gpio2: gpio@ffb00000 { @@ -167,6 +168,7 @@ gpio2: gpio@ffb00000 { gpio-ranges = <&pinctrl 0 64 32>; interrupt-controller; #interrupt-cells = <2>; + power-domains = <&power RK3528_PD_VO>; }; gpio3: gpio@ffb10000 { @@ -179,6 +181,7 @@ gpio3: gpio@ffb10000 { gpio-ranges = <&pinctrl 0 96 32>; interrupt-controller; #interrupt-cells = <2>; + power-domains = <&power RK3528_PD_VPU>; }; gpio4: gpio@ffb20000 { @@ -191,6 +194,7 @@ gpio4: gpio@ffb20000 { gpio-ranges = <&pinctrl 0 128 32>; interrupt-controller; #interrupt-cells = <2>; + power-domains = <&power RK3528_PD_RKVENC>; }; }; @@ -506,7 +510,6 @@ power-domain@RK3528_PD_RKVENC { reg = ; pm_qos = <&qos_rkvenc>; #power-domain-cells = <0>; - status = "disabled"; }; power-domain@RK3528_PD_VO { reg = ; @@ -520,7 +523,6 @@ power-domain@RK3528_PD_VO { <&qos_vdpp>, <&qos_vop>; #power-domain-cells = <0>; - status = "disabled"; }; power-domain@RK3528_PD_VPU { reg = ; @@ -534,7 +536,6 @@ power-domain@RK3528_PD_VPU { <&qos_usb3otg>, <&qos_vpu>; #power-domain-cells = <0>; - status = "disabled"; }; }; }; @@ -576,6 +577,7 @@ spi0: spi@ff9c0000 { interrupts = ; dmas = <&dmac 25>, <&dmac 24>; dma-names = "tx", "rx"; + power-domains = <&power RK3528_PD_RKVENC>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -590,6 +592,7 @@ spi1: spi@ff9d0000 { interrupts = ; dmas = <&dmac 31>, <&dmac 30>; dma-names = "tx", "rx"; + power-domains = <&power RK3528_PD_VPU>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -614,6 +617,7 @@ uart1: serial@ff9f8000 { clock-names = "baudclk", "apb_pclk"; interrupts = ; dmas = <&dmac 11>, <&dmac 10>; + power-domains = <&power RK3528_PD_RKVENC>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -626,6 +630,7 @@ uart2: serial@ffa00000 { clock-names = "baudclk", "apb_pclk"; interrupts = ; dmas = <&dmac 13>, <&dmac 12>; + power-domains = <&power RK3528_PD_VPU>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -638,6 +643,7 @@ uart3: serial@ffa08000 { clock-names = "baudclk", "apb_pclk"; interrupts = ; dmas = <&dmac 15>, <&dmac 14>; + power-domains = <&power RK3528_PD_RKVENC>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -650,6 +656,7 @@ uart4: serial@ffa10000 { clock-names = "baudclk", "apb_pclk"; interrupts = ; dmas = <&dmac 17>, <&dmac 16>; + power-domains = <&power RK3528_PD_VO>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -662,6 +669,7 @@ uart5: serial@ffa18000 { clock-names = "baudclk", "apb_pclk"; interrupts = ; dmas = <&dmac 19>, <&dmac 18>; + power-domains = <&power RK3528_PD_VPU>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -674,6 +682,7 @@ uart6: serial@ffa20000 { clock-names = "baudclk", "apb_pclk"; interrupts = ; dmas = <&dmac 21>, <&dmac 20>; + power-domains = <&power RK3528_PD_VPU>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -686,6 +695,7 @@ uart7: serial@ffa28000 { clock-names = "baudclk", "apb_pclk"; interrupts = ; dmas = <&dmac 23>, <&dmac 22>; + power-domains = <&power RK3528_PD_VPU>; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; @@ -698,6 +708,7 @@ i2c0: i2c@ffa50000 { clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; clock-names = "i2c", "pclk"; interrupts = ; + power-domains = <&power RK3528_PD_RKVENC>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -710,6 +721,7 @@ i2c1: i2c@ffa58000 { clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; clock-names = "i2c", "pclk"; interrupts = ; + power-domains = <&power RK3528_PD_RKVENC>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -736,6 +748,7 @@ i2c3: i2c@ffa68000 { clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; clock-names = "i2c", "pclk"; interrupts = ; + power-domains = <&power RK3528_PD_VPU>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -750,6 +763,7 @@ i2c4: i2c@ffa70000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c4_xfer>; + power-domains = <&power RK3528_PD_VO>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -762,6 +776,7 @@ i2c5: i2c@ffa78000 { clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; clock-names = "i2c", "pclk"; interrupts = ; + power-domains = <&power RK3528_PD_VPU>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -774,6 +789,7 @@ i2c6: i2c@ffa80000 { clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; clock-names = "i2c", "pclk"; interrupts = ; + power-domains = <&power RK3528_PD_VPU>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -788,6 +804,7 @@ i2c7: i2c@ffa88000 { interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&i2c7_xfer>; + power-domains = <&power RK3528_PD_VO>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -879,6 +896,7 @@ saradc: adc@ffae0000 { clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; interrupts = ; + power-domains = <&power RK3528_PD_VPU>; resets = <&cru SRST_P_SARADC>; reset-names = "saradc-apb"; #io-channel-cells = <1>; @@ -899,6 +917,7 @@ gmac0: ethernet@ffbd0000 { interrupt-names = "macirq", "eth_wake_irq"; phy-handle = <&rmii0_phy>; phy-mode = "rmii"; + power-domains = <&power RK3528_PD_VO>; resets = <&cru SRST_A_MAC_VO>; reset-names = "stmmaceth"; rockchip,grf = <&vo_grf>; @@ -957,6 +976,7 @@ gmac1: ethernet@ffbe0000 { interrupts = , ; interrupt-names = "macirq", "eth_wake_irq"; + power-domains = <&power RK3528_PD_VPU>; resets = <&cru SRST_A_MAC>; reset-names = "stmmaceth"; rockchip,grf = <&vpu_grf>; @@ -1007,6 +1027,7 @@ sdhci: mmc@ffbf0000 { pinctrl-names = "default"; pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, <&emmc_strb>; + power-domains = <&power RK3528_PD_VPU>; resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, <&cru SRST_T_EMMC>; @@ -1028,6 +1049,7 @@ sdio0: mmc@ffc10000 { max-frequency = <200000000>; pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>; + power-domains = <&power RK3528_PD_VPU>; resets = <&cru SRST_H_SDIO0>; reset-names = "reset"; status = "disabled"; @@ -1047,6 +1069,7 @@ sdio1: mmc@ffc20000 { max-frequency = <200000000>; pinctrl-names = "default"; pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>; + power-domains = <&power RK3528_PD_VPU>; resets = <&cru SRST_H_SDIO1>; reset-names = "reset"; status = "disabled"; @@ -1067,6 +1090,7 @@ sdmmc: mmc@ffc30000 { pinctrl-names = "default"; pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_det>; + power-domains = <&power RK3528_PD_VO>; resets = <&cru SRST_H_SDMMC0>; reset-names = "reset"; rockchip,default-sample-phase = <90>; From 5487086c4dad869af0eeca0ee24d1ba5fe382b3c Mon Sep 17 00:00:00 2001 From: Kyle Petryszak Date: Tue, 19 Aug 2025 21:30:12 -0500 Subject: [PATCH 341/931] arm64: dts: rockchip: Add green power LED to rk3588s-rock-5a The Radxa ROCK 5A board includes a green power LED that is defined in the vendor device tree but is missing from the upstream kernel DTS file. This causes the LED to be uncontrollable from the operating system, as no entry is created for it under /sys/class/leds. This patch adds the missing node to the leds block, creating a "green:power" device and allowing the LED to be controlled by the kernel. Signed-off-by: Kyle Petryszak Link: https://lore.kernel.org/r/175565703702.6.15498212790604388615.862782045@projectinitiative.io Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index f894742b1ebe..19a08f7794e6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -58,6 +58,13 @@ io-led { gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; + + power-led { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; }; fan: pwm-fan { From 67b2c15d8fb3c1447a23358075e4f336d40d9797 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 19 Aug 2025 16:50:13 +0200 Subject: [PATCH 342/931] arm64: dts: rockchip: add USB-C support for ROCK 5B/5B+/5T Add hardware description for the USB-C port in the Radxa ROCK 5 Model B family. This describes the OHCI, EHCI and XHCI USB parts. The DisplayPort AltMode is only partially described, as bindings for the necessary DisplayPort controller are still being reviewed. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20250819-rock5bp-for-upstream-v4-1-7a2365ce7176@kernel.org Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 133 ++++++++++++++++++ .../boot/dts/rockchip/rk3588-rock-5b-plus.dts | 12 ++ .../boot/dts/rockchip/rk3588-rock-5b.dts | 12 ++ .../boot/dts/rockchip/rk3588-rock-5t.dts | 14 ++ 4 files changed, 171 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi index 612808d2b4c5..3bbe78810ec6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include #include "rk3588.dtsi" / { @@ -55,6 +56,18 @@ rfkill-bt { shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; }; + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus5v0_typec_en>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { compatible = "regulator-fixed"; enable-active-high; @@ -291,6 +304,76 @@ regulator-state-mem { }; }; +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "okay"; + + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + /* + * When the board is starting to send power-delivery messages + * too late (5 seconds according to the specification), the + * power-supply reacts with a hard-reset. That removes the + * power from VBUS for some time, which resets te whole board. + */ + status = "fail"; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + /* fusb302 supports PD Rev 2.0 Ver 1.2 */ + pd-revision = /bits/ 8 <0x2 0x0 0x1 0x2>; + power-role = "sink"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + , + ; + + altmodes { + displayport { + svid = /bits/ 16 <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_to_usbc0>; + }; + }; + + port@1 { + reg = <1>; + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_ss>; + }; + }; + + port@2 { + reg = <2>; + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_sbu>; + }; + }; + }; + }; + }; +}; + &i2c6 { status = "okay"; @@ -445,6 +528,16 @@ pcie3_vcc3v3_en: pcie3-vcc3v3-en { rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vbus5v0_typec_en: vbus5v0-typec-en { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm1 { @@ -860,6 +953,14 @@ &uart2 { status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + &u2phy1 { status = "okay"; }; @@ -887,6 +988,27 @@ &u2phy3_host { status = "okay"; }; +&usbdp_phy0 { + mode-switch; + orientation-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_ss>; + }; + + usbdp_phy0_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_sbu>; + }; + }; +}; + &usbdp_phy1 { status = "okay"; }; @@ -899,6 +1021,17 @@ &usb_host0_ohci { status = "okay"; }; +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + usb_host0_xhci_to_usbc0: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; +}; + &usb_host1_ehci { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts index 74c7b6502e4d..5e984a44120e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts @@ -99,12 +99,24 @@ pcie3x2_rst: pcie3x2-rst { }; usb { + usbc_sbu_dc: usbc-sbu-dc { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; +&usbdp_phy0 { + pinctrl-names = "default"; + pinctrl-0 = <&usbc_sbu_dc>; + sbu1-dc-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; +}; + &vcc5v0_host { enable-active-high; gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 9407a7c9910a..8ef01010d985 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -38,12 +38,24 @@ &uart6 { &pinctrl { usb { + usbc_sbu_dc: usbc-sbu-dc { + rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; +&usbdp_phy0 { + pinctrl-names = "default"; + pinctrl-0 = <&usbc_sbu_dc>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; +}; + &vcc5v0_host { enable-active-high; gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts index 258c7400301d..217954767845 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts @@ -95,6 +95,20 @@ hp_detect: hp-detect { rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb { + usbc_sbu_dc: usbc-sbu-dc { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&usbdp_phy0 { + pinctrl-names = "default"; + pinctrl-0 = <&usbc_sbu_dc>; + sbu1-dc-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; }; &vcc3v3_pcie2x1l0 { From eba84c94f9597a82f143997bfacc75e5b27a37de Mon Sep 17 00:00:00 2001 From: Hendrik Hamerlinck Date: Thu, 21 Aug 2025 17:26:19 +0200 Subject: [PATCH 343/931] riscv: dts: spacemit: add UART resets for Soc K1 The UARTs in the SpacemiT K1 device tree are probed by the 8250_of driver, but without reset lines they remain non-functional. Add reset control entries so that the UARTs can operate when mapped to devices. UART0 is already de-asserted by the bootloader, but include its reset as well to avoid relying on bootloader state. Tested on Orange Pi RV2 and Banana Pi BPI-F3 boards, with UART9 enabled and verified functional. Signed-off-by: Hendrik Hamerlinck Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20250821152619.597051-1-hendrik.hamerlinck@hammernet.be Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index abde8bb07c95..6c68b2e54675 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -667,6 +667,7 @@ uart0: serial@d4017000 { clocks = <&syscon_apbc CLK_UART0>, <&syscon_apbc CLK_UART0_BUS>; clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_UART0>; interrupts = <42>; reg-shift = <2>; reg-io-width = <4>; @@ -680,6 +681,7 @@ uart2: serial@d4017100 { clocks = <&syscon_apbc CLK_UART2>, <&syscon_apbc CLK_UART2_BUS>; clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_UART2>; interrupts = <44>; reg-shift = <2>; reg-io-width = <4>; @@ -693,6 +695,7 @@ uart3: serial@d4017200 { clocks = <&syscon_apbc CLK_UART3>, <&syscon_apbc CLK_UART3_BUS>; clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_UART3>; interrupts = <45>; reg-shift = <2>; reg-io-width = <4>; @@ -706,6 +709,7 @@ uart4: serial@d4017300 { clocks = <&syscon_apbc CLK_UART4>, <&syscon_apbc CLK_UART4_BUS>; clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_UART4>; interrupts = <46>; reg-shift = <2>; reg-io-width = <4>; @@ -719,6 +723,7 @@ uart5: serial@d4017400 { clocks = <&syscon_apbc CLK_UART5>, <&syscon_apbc CLK_UART5_BUS>; clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_UART5>; interrupts = <47>; reg-shift = <2>; reg-io-width = <4>; @@ -732,6 +737,7 @@ uart6: serial@d4017500 { clocks = <&syscon_apbc CLK_UART6>, <&syscon_apbc CLK_UART6_BUS>; clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_UART6>; interrupts = <48>; reg-shift = <2>; reg-io-width = <4>; @@ -745,6 +751,7 @@ uart7: serial@d4017600 { clocks = <&syscon_apbc CLK_UART7>, <&syscon_apbc CLK_UART7_BUS>; clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_UART7>; interrupts = <49>; reg-shift = <2>; reg-io-width = <4>; @@ -758,6 +765,7 @@ uart8: serial@d4017700 { clocks = <&syscon_apbc CLK_UART8>, <&syscon_apbc CLK_UART8_BUS>; clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_UART8>; interrupts = <50>; reg-shift = <2>; reg-io-width = <4>; @@ -771,6 +779,7 @@ uart9: serial@d4017800 { clocks = <&syscon_apbc CLK_UART9>, <&syscon_apbc CLK_UART9_BUS>; clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_UART9>; interrupts = <51>; reg-shift = <2>; reg-io-width = <4>; From 9c059700fee595142676a9bbaff6e40e3fcd9cbb Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 18 Aug 2025 19:18:40 +0200 Subject: [PATCH 344/931] arm64: dts: rockchip: Enable RK3576 watchdog The RK3576 watchdog does not need any board specific resources, so let's enable it by default just like we do for RK3588. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20250818-rk3576-watchdog-v1-1-28f82e01029c@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 93143e63898e..fc4e9e07f1cf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -2275,7 +2275,6 @@ wdt: watchdog@2ace0000 { clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; clock-names = "tclk", "pclk"; interrupts = ; - status = "disabled"; }; spi0: spi@2acf0000 { From 7d11b8c260ea68ce8f420ad467b04b21ea34b011 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 18 Aug 2025 18:00:06 +0800 Subject: [PATCH 345/931] dt-bindings: vendor-prefixes: Add HINLINK Add vendor prefix for HINLINK, which is an SBC manufacturer. Link: https://www.hinlink.cn/ Signed-off-by: Chukun Pan Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250818100009.170202-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 77160cd47f54..1305da271a68 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -646,6 +646,8 @@ patternProperties: description: HiDeep Inc. "^himax,.*": description: Himax Technologies, Inc. + "^hinlink,.*": + description: Shenzhen HINLINK Technology Co., Ltd. "^hirschmann,.*": description: Hirschmann Automation and Control GmbH "^hisi,.*": From 4bef07b79ab1ef7d963eaa2c37948030e418d538 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 18 Aug 2025 18:00:07 +0800 Subject: [PATCH 346/931] dt-bindings: arm: rockchip: Add HINLINK H66K / H68K The HINLINK H66K/H68K are 2.5GbE SBC based on the RK3568 SoC. Add devicetree binding documentation for them. Signed-off-by: Chukun Pan Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250818100009.170202-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 28db6bd6aa5b..870c318fc8d4 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -683,6 +683,13 @@ properties: - const: hardkernel,odroid-m2 - const: rockchip,rk3588s + - description: HINLINK H66K / H68K + items: + - enum: + - hinlink,h66k + - hinlink,h68k + - const: rockchip,rk3568 + - description: Hugsun X99 TV Box items: - const: hugsun,x99 From 86a504b82f8d0e34f99ab9607712e7942c919fa3 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 18 Aug 2025 18:00:08 +0800 Subject: [PATCH 347/931] arm64: dts: rockchip: Add HINLINK H68K The HINLINK H68K is a development board with the Rockchip RK3568 SoC. It has the following features: - 2/4GB LPDDR4 - 1x HDMI Type A - 3.5mm jack with mic - 1x PCIE 2.0 WiFi slot - 1x USB 3.0, 2x USB 2.0 - 2x 1GbE RTL8211F Ethernet - 2x 2.5GbE RTL8125B Ethernet - MicroSD card slot / eMMC 32GB Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20250818100009.170202-4-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3568-hinlink-h68k.dts | 83 +++ .../boot/dts/rockchip/rk3568-hinlink-opc.dtsi | 666 ++++++++++++++++++ 3 files changed, 750 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 099520962ffb..09c810cb64a4 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -130,6 +130,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h68k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mecsbc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts new file mode 100644 index 000000000000..793ee651b868 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3568-hinlink-opc.dtsi" + +/ { + model = "HINLINK H68K"; + compatible = "hinlink,h68k", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &gmac0_rstn>; + status = "okay"; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1_rstn>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + gmac { + gmac0_rstn: gmac0-rstn { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + gmac1_rstn: gmac1-rstn { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi new file mode 100644 index 000000000000..14f3839ca091 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi @@ -0,0 +1,666 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_ir_m0>; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&factory>; + + button-factory { + label = "factory"; + linux,code = ; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&green_led>, <&red_led>, <&work_led>; + + led-0 { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_DISK; + gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + vcc0v9_2g5: regulator-0v9-vcc-2g5 { + compatible = "regulator-fixed"; + regulator-name = "vcc0v9_2g5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc12v_dcinp: regulator-12v-vcc-dcinp { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcinp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pi6c_05: regulator-3v3-vcc-pi6c-05 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lan_power_en>; + regulator-name = "vcc3v3_pi6c_05"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sd: regulator-3v3-vcc-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pwren>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: regulator-3v3-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcinp>; + }; + + vcc5v0_usb30_otg0: regulator-5v0-vcc-usb30-otg0 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_power_en>; + regulator-name = "vcc5v0_usb30_otg0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + #clock-cells = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3: SWITCH_REG2 { + regulator-name = "vcc3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_perstn>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&lan_resetb>; + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&lan_reseta>; + reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pi6c_05>; + status = "okay"; +}; + +&pinctrl { + keys { + factory: factory { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + green_led: green-led { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + red_led: red-led { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + work_led: work-led { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ir { + pwm3_ir_m0: pwm3-ir-m0 { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mmc { + sd_pwren: sd-pwren { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + lan_power_en: lan-power-en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan_reseta: lan-reseta { + rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan_resetb: lan-resetb { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_perstn: wifi-perstn { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_power_en: usb-power-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +/* Via Type-C adapter */ +&sata0 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb30_otg0>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb30_otg0>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb30_otg0>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From bb9ef44f05c9558d58e3c9da141e93af1aa11c1f Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 18 Aug 2025 18:00:09 +0800 Subject: [PATCH 348/931] arm64: dts: rockchip: Add HINLINK H66K The HINLINK H66K is a development board with the Rockchip RK3568 SoC. It has the following features: - 2/4GB LPDDR4 - 1x HDMI Type A - 3.5mm jack with mic - 1x PCIE 2.0 WiFi slot - 1x USB 3.0, 2x USB 2.0 - 2x 2.5GbE RTL8125B Ethernet - MicroSD card slot / eMMC 32GB Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20250818100009.170202-5-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts | 10 ++++++++++ 2 files changed, 11 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 09c810cb64a4..93e547a1c77b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -130,6 +130,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h66k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h68k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mecsbc.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts new file mode 100644 index 000000000000..bc51123d53f5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3568-hinlink-opc.dtsi" + +/ { + model = "HINLINK H66K"; + compatible = "hinlink,h66k", "rockchip,rk3568"; +}; From 0adaae77862932a19cc14c086d7fd15ec0ef7703 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Wed, 13 Aug 2025 00:30:23 +0400 Subject: [PATCH 349/931] arm64: dts: rockchip: Add RTC on rk3576-evb1-v10 Add the I2C connected RTC chip to the Rockchip RK3576 EVB1 board. Apart from the realtime clock functionality, it also provides a 32 kHz clock source for the onboard WiFi chip. Tested-by: Pavel Zhovner Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20250813-evb1-rtcwifibt-v1-1-d13c83422971@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3576-evb1-v10.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index a60dee0de9f9..b756aba9328b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -680,6 +680,22 @@ regulator-state-mem { }; }; +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + wakeup-source; + #clock-cells = <0>; + }; +}; + &mdio0 { rgmii_phy0: phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -708,6 +724,12 @@ &pcie1 { }; &pinctrl { + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + usb { usb_host_pwren: usb-host-pwren { rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; From ebf8183ad08afc4fcabe1379a5098354829d950d Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Wed, 13 Aug 2025 00:30:24 +0400 Subject: [PATCH 350/931] arm64: dts: rockchip: Add WiFi on rk3576-evb1-v10 Add device tree nodes to enable the onboard Ampak AP6275P WiFi chip connected over a PCIe link on Rockchip RK3576 EVB1. It takes an external 32 kHz clock from the RTC chip and requires the WIFI_REG_ON signal to be enabled before the bus is enumerated to initialize properly. Tested-by: Pavel Zhovner Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20250813-evb1-rtcwifibt-v1-2-d13c83422971@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3576-evb1-v10.dts | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index b756aba9328b..1adbbcc1c569 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -232,6 +232,20 @@ vcc_ufs_s0: regulator-vcc-ufs-s0 { regulator-max-microvolt = <3300000>; vin-supply = <&vcc_sys>; }; + + vcc_wifi_reg_on: regulator-wifi-reg-on { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&wifi_reg_on>; + pinctrl-names = "default"; + regulator-name = "wifi_reg_on"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; }; &cpu_l0 { @@ -242,6 +256,10 @@ &cpu_b0 { cpu-supply = <&vdd_cpu_big_s0>; }; +&combphy0_ps { + status = "okay"; +}; + &combphy1_psu { status = "okay"; }; @@ -712,6 +730,30 @@ rgmii_phy1: phy@1 { }; }; +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_rst>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_s3>; + status = "okay"; + + pcie@0,0 { + reg = <0x0 0 0 0 0>; + bus-range = <0x0 0xf>; + device_type = "pci"; + ranges; + #address-cells = <3>; + #size-cells = <2>; + + wifi: wifi@0,0 { + compatible = "pci14e4,449d"; + reg = <0x10000 0 0 0 0>; + clocks = <&hym8563>; + clock-names = "lpo"; + }; + }; +}; + &pcie1 { reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie1>; @@ -730,6 +772,12 @@ rtc_int: rtc-int { }; }; + pcie0 { + pcie0_rst: pcie0-rst { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { usb_host_pwren: usb-host-pwren { rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; @@ -743,6 +791,16 @@ usbc0_int: usbc0-int { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + wifi { + wifi_reg_on: wifi-reg-on { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_wake_host: wifi-wake-host { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; }; &sdhci { From 34f7620912bb0f881a23dfea529e69fd2e8fdcf2 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Wed, 13 Aug 2025 00:30:25 +0400 Subject: [PATCH 351/931] arm64: dts: rockchip: Add Bluetooth on rk3576-evb1-v10 Add device tree nodes to enable Bluetooth in the Ampak AP6275P module found on Rockchip RK3576 EVB1 and connected over a UART link. Note that this doesn't enable the out-of-band PCM connection. It's routed to SAI2 M0 pins in case anyone wishes to add it. Tested-by: Pavel Zhovner Signed-off-by: Alexey Charkov Link: https://lore.kernel.org/r/20250813-evb1-rtcwifibt-v1-3-d13c83422971@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3576-evb1-v10.dts | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index 1adbbcc1c569..439831715cbb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -766,6 +766,20 @@ &pcie1 { }; &pinctrl { + bluetooth { + bt_reg_on: bt-reg-on { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + hym8563 { rtc_int: rtc-int { rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; @@ -855,6 +869,27 @@ &uart0 { status = "okay"; }; +&uart4 { + pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn &uart4m1_rtsn>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&hym8563>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&bt_reg_on &bt_wake_host &host_wake_bt>; + pinctrl-names = "default"; + shutdown-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3_s3>; + vddio-supply = <&vcc_1v8_s3>; + }; +}; + &ufshc { status = "okay"; }; From b3d7fb3fb2227259aa2fc54916cc808614f3ac24 Mon Sep 17 00:00:00 2001 From: Jimmy Hon Date: Mon, 11 Aug 2025 21:57:55 -0500 Subject: [PATCH 352/931] arm64: dts: rockchip: enable NPU on OPI5/5B The NPU on the Orange Pi 5/5B uses the same regulator for both the sram-supply and the npu's supply. Enable all the NPU bits. Also add the regulator as a domain-supply to the pd_npu power domain. Signed-off-by: Jimmy Hon Link: https://lore.kernel.org/r/20250812025755.2078-2-honyuenkwun@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588s-orangepi-5.dtsi | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi index 4fedc50cce8c..65a06ce8c131 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi @@ -377,6 +377,10 @@ &pd_gpu { domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -407,6 +411,36 @@ &pwm0 { status = "okay"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; From 5052d5cf1359e9057ec311788c12997406fdb2fc Mon Sep 17 00:00:00 2001 From: Michal Wilczynski Date: Fri, 22 Aug 2025 00:20:17 +0200 Subject: [PATCH 353/931] riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD TH1520 SoC used by the Lichee Pi 4A board. This node enables support for the GPU using the drm/imagination driver. By adding this node, the kernel can recognize and initialize the GPU, providing graphics acceleration capabilities on the Lichee Pi 4A and other boards based on the TH1520 SoC. Add fixed clock gpu_mem_clk, as the MEM clock on the T-HEAD SoC can't be controlled programatically. Reviewed-by: Ulf Hansson Reviewed-by: Drew Fustini Reviewed-by: Bartosz Golaszewski Acked-by: Matt Coster Signed-off-by: Michal Wilczynski Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 42724bf7e90e..6ae5c632205b 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -225,6 +225,13 @@ aonsys_clk: clock-73728000 { #clock-cells = <0>; }; + gpu_mem_clk: mem-clk { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "gpu_mem_clk"; + #clock-cells = <0>; + }; + stmmac_axi_config: stmmac-axi-config { snps,wr_osr_lmt = <15>; snps,rd_osr_lmt = <15>; @@ -500,6 +507,20 @@ clk: clock-controller@ffef010000 { #clock-cells = <1>; }; + gpu: gpu@ffef400000 { + compatible = "thead,th1520-gpu", "img,img-bxm-4-64", + "img,img-rogue"; + reg = <0xff 0xef400000 0x0 0x100000>; + interrupt-parent = <&plic>; + interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_vo CLK_GPU_CORE>, + <&gpu_mem_clk>, + <&clk_vo CLK_GPU_CFG_ACLK>; + clock-names = "core", "mem", "sys"; + power-domains = <&aon TH1520_GPU_PD>; + resets = <&rst TH1520_RESET_ID_GPU>; + }; + rst: reset-controller@ffef528000 { compatible = "thead,th1520-reset"; reg = <0xff 0xef528000 0x0 0x4f>; From 08468d0bf1ae52ece5394eaca6a6fd3543817f9f Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 11 Aug 2025 20:37:10 +0200 Subject: [PATCH 354/931] ARM: dts: cirrus: ep7211: use recent scl/sda gpio bindings We have dedictaded bindings for scl/sda nowadays. Switch away from the deprecated plain 'gpios' property. Reviewed-by: Linus Walleij Signed-off-by: Wolfram Sang --- arch/arm/boot/dts/cirrus/ep7211-edb7211.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts b/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts index adc74243ed19..0b15ccaa762e 100644 --- a/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts +++ b/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts @@ -46,8 +46,8 @@ timing0: timing-320x240 { i2c: i2c { compatible = "i2c-gpio"; - gpios = <&portd 4 GPIO_ACTIVE_HIGH>, - <&portd 5 GPIO_ACTIVE_HIGH>; + sda-gpios = <&portd 4 GPIO_ACTIVE_HIGH>; + scl-gpios = <&portd 5 GPIO_ACTIVE_HIGH>; i2c-gpio,delay-us = <2>; i2c-gpio,scl-output-only; #address-cells = <1>; From ed8c952aee4183ac866a83397e12ceb99493c6ad Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 11 Aug 2025 20:37:11 +0200 Subject: [PATCH 355/931] ARM: dts: stm32: use recent scl/sda gpio bindings We have dedictaded bindings for scl/sda nowadays. Switch away from the deprecated plain 'gpios' property. Reviewed-by: Linus Walleij Signed-off-by: Wolfram Sang --- arch/arm/boot/dts/st/ste-nomadik-s8815.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/st/ste-nomadik-s8815.dts b/arch/arm/boot/dts/st/ste-nomadik-s8815.dts index c905c2643a12..aeb58d2c08a1 100644 --- a/arch/arm/boot/dts/st/ste-nomadik-s8815.dts +++ b/arch/arm/boot/dts/st/ste-nomadik-s8815.dts @@ -117,8 +117,8 @@ lis3lv02dl@1d { /* GPIO I2C connected to the USB portions of the STw4811 only */ gpio-i2c { compatible = "i2c-gpio"; - gpios = <&gpio2 10 0>, /* sda */ - <&gpio2 9 0>; /* scl */ + sda-gpios = <&gpio2 10 0>; + scl-gpios = <&gpio2 9 0>; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; From dfdda0881b353453afc376f7f2bf6a8306fcada3 Mon Sep 17 00:00:00 2001 From: Anton Kirilov Date: Wed, 27 Aug 2025 15:22:10 +0100 Subject: [PATCH 356/931] arm64: dts: rockchip: Enable the NPU on NanoPi R6C/R6S Enable the NPU on FriendlyElec NanoPi R6C/R6S boards. Signed-off-by: Anton Kirilov Link: https://lore.kernel.org/r/20250827142210.2221606-1-anton.kirilov@arm.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi index 2e9d5143476d..1b6a59f7cabc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi @@ -371,6 +371,10 @@ &pd_gpu { domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { gpio-key { key1_pin: key1-pin { @@ -429,6 +433,36 @@ rtl8211f_rst: rtl8211f-rst { }; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; From 6d54d935062e2d4a7d3f779ceb9eeff108d0535d Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 27 Aug 2025 15:30:37 +0100 Subject: [PATCH 357/931] arm64: dts: rockchip: Further describe the WiFi for the Pinebook Pro Update the wake-up pin and associated interupt details for the Pinebook Pro WiFi module. Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20250827143040.1644867-1-pbrobinson@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-pinebook-pro.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts index 5a8551d9ffe4..191feaecf7bf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts @@ -883,6 +883,12 @@ vcc5v0_host_en_pin: vcc5v0-host-en-pin { }; }; + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + wireless-bluetooth { bt_wake_pin: bt-wake-pin { rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; @@ -940,7 +946,19 @@ &sdio0 { pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; }; &sdhci { From 4ce3d8526d95f414228908048a1313fe322f0d9b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 15 Jan 2025 22:16:27 +0100 Subject: [PATCH 358/931] ARM: dts: st: ste-nomadik: Align GPIO hog name with bindings Bindings expect GPIO hog names to end with 'hog' suffix, so correct it to fix dtbs_check warning: ste-nomadik-s8815.dtb: mmcsd-gpio: $nodename:0: 'mmcsd-gpio' does not match '^.+-hog(-[0-9]+)?$' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250115211627.193961-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/st/ste-nomadik-s8815.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/ste-nomadik-s8815.dts b/arch/arm/boot/dts/st/ste-nomadik-s8815.dts index c905c2643a12..2f642c88f288 100644 --- a/arch/arm/boot/dts/st/ste-nomadik-s8815.dts +++ b/arch/arm/boot/dts/st/ste-nomadik-s8815.dts @@ -23,7 +23,7 @@ aliases { gpio3: gpio@101e7000 { /* This hog will bias the MMC/SD card detect line */ - mmcsd-gpio { + mmcsd-hog { gpio-hog; gpios = <16 0x0>; output-low; From 9c66753641765cc2f5ee1528a23f3fd2fd77cb93 Mon Sep 17 00:00:00 2001 From: Alex Tran Date: Sat, 23 Aug 2025 14:27:32 -0700 Subject: [PATCH 359/931] ARM: dts: ste-ux500-samsung: dts bluetooth wakeup interrupt Interrupt support on host wakeup gpio for ste-ux500-samsung bluetooth. Signed-off-by: Alex Tran Link: https://lore.kernel.org/r/20250823212732.356620-1-alex.t.tran@gmail.com Signed-off-by: Linus Walleij --- arch/arm/boot/dts/st/ste-ux500-samsung-codina-tmo.dts | 5 +++-- arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts | 5 +++-- arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts | 5 +++-- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-codina-tmo.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-codina-tmo.dts index 404d4ea9347b..8f1780d560ff 100644 --- a/arch/arm/boot/dts/st/ste-ux500-samsung-codina-tmo.dts +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-codina-tmo.dts @@ -383,8 +383,9 @@ bluetooth { /* BT_WAKE on GPIO199 */ device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; /* BT_HOST_WAKE on GPIO97 */ - /* FIXME: convert to interrupt */ - host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio3>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "host-wakeup"; /* BT_RST_N on GPIO209 */ reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts index 40b0d92dfb15..9f58a3c2d06d 100644 --- a/arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts @@ -479,8 +479,9 @@ bluetooth { /* BT_WAKE on GPIO199 */ device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; /* BT_HOST_WAKE on GPIO97 */ - /* FIXME: convert to interrupt */ - host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio3>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "host-wakeup"; /* BT_RST_N on GPIO209 */ reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts index 229f7c32103c..64562a3a262c 100644 --- a/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts @@ -481,8 +481,9 @@ bluetooth { /* BT_WAKE on GPIO199 */ device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; /* BT_HOST_WAKE on GPIO97 */ - /* FIXME: convert to interrupt */ - host-wakeup-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio3>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "host-wakeup"; /* BT_RST_N on GPIO209 */ reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; From b60b74f82e3ed4910a5f96a412e89bdd44875842 Mon Sep 17 00:00:00 2001 From: Harini T Date: Thu, 10 Jul 2025 11:43:09 +0530 Subject: [PATCH 360/931] arm64: versal-net: Update rtc calibration value As per the design specification "The 16-bit Seconds Calibration Value represents the number of Oscillator Ticks that are required to measure the largest time period that is less than or equal to 1 second. For an oscillator that is 32.768kHz, this value will be 0x7FFF." Signed-off-by: Harini T Link: https://lore.kernel.org/r/20250710061309.25601-1-harini.t@amd.com Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/versal-net.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/versal-net.dtsi b/arch/arm64/boot/dts/xilinx/versal-net.dtsi index fc9f49e57385..c037a7819967 100644 --- a/arch/arm64/boot/dts/xilinx/versal-net.dtsi +++ b/arch/arm64/boot/dts/xilinx/versal-net.dtsi @@ -556,7 +556,7 @@ rtc: rtc@f12a0000 { reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; - calibration = <0x8000>; + calibration = <0x7FFF>; }; sdhci0: mmc@f1040000 { From 00acd6d441070c5dd2513f4417aed8a918909afb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 18 Jul 2025 12:45:06 +0200 Subject: [PATCH 361/931] arm64: zynqmp: Use generic spi@ name in zcu111-revA DT schema requires to use spi@ name for SPI devices that's why fix it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/95979240cf09929c81a6f74199b0cb7027dd8798.1752835501.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index b67ff7ecf3c3..a0cddaa64424 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -494,7 +494,7 @@ i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; - sc18is603@2f { /* sc18is602 - u93 */ + sc18is603: spi@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ From 7044b13e008d7033f2e966603a507401b11f913a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 18 Jul 2025 12:45:07 +0200 Subject: [PATCH 362/931] arm64: zynqmp: Remove undocumented arasan,has-mdma property arasan,has-mdma is not described in DT binding that's why remove it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/6567a0855ad73b5ff01d9945063014fbacdcc845.1752835501.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 1 - arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index 1850325e1d6c..2ad7423c2f05 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -135,7 +135,6 @@ &nand0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; - arasan,has-mdma; nand@0 { reg = <0x0>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts index f553b317e6b2..8fbc33562bc4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts @@ -129,7 +129,6 @@ &i2c1 { /* MT29F64G08AECDBJ4-6 */ &nand0 { status = "okay"; - arasan,has-mdma; num-cs = <2>; }; From c7d5ca726ddc9a4d0e6d31873ffa203ee7803037 Mon Sep 17 00:00:00 2001 From: Paul Alvin Date: Fri, 18 Jul 2025 12:45:08 +0200 Subject: [PATCH 363/931] arm64: zynqmp: Add cap-mmc-hw-reset and no-sd, no-sdio property to eMMC Add "cap-mmc-hw-reset" property to the eMMC DT node to perform the eMMC device hardware reset. Also, add "no-sd", "no-sdio" properties to eMMC DT node to skip unwanted sd, sdio related commands during initialization for eMMC device as this may lead to unnecessary register dump. Signed-off-by: Paul Alvin Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/10132834c0509539b0d01ff5097591cd2e3ae125.1752835501.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 3 +++ arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index bfa7ea6b9224..51778df5540c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -233,6 +233,9 @@ &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */ pinctrl-0 = <&pinctrl_sdhci0_default>; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; bus-width = <8>; xlnx,mio-bank = <0>; assigned-clock-rates = <187498123>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 62c2503a502a..3542844e6977 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -509,6 +509,9 @@ &sdhci1 { xlnx,mio-bank = <0>; non-removable; disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; From 0f961857d3437bba9b2e1801085c9c39484d4541 Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Fri, 18 Jul 2025 12:45:09 +0200 Subject: [PATCH 364/931] arm64: zynqmp: Update the usb5744 hub node as per binding Updating the usb5744 hub node as per the latest upstream DT binding. Signed-off-by: Venkatesh Yadav Abbarapu Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/564a09b84dfdce1e54c93e95f9156150e05b8f43.1752835502.git.michal.simek@amd.com --- .../boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 19 +++++++++++++- .../boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 25 ++++++++++++++++++- 2 files changed, 42 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 95d16904d765..a98a888d1385 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -129,7 +129,6 @@ &usb0 { pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; - /* missing usb5744 - u43 */ }; &dwc3_0 { @@ -137,6 +136,24 @@ &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; }; &sdhci1 { /* on CC with tuned parameters */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index a74d0ac7e07a..7490efea98bd 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -92,7 +92,10 @@ u14: ina260@40 { /* u14 */ label = "ina260-u14"; reg = <0x40>; }; - /* u43 - 0x2d - USB hub */ + hub: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ }; @@ -138,6 +141,26 @@ &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub>; + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; + }; }; &sdhci1 { /* on CC with tuned parameters */ From 7cf18a364ed2d56cf44769d1a3690aa0bf4d5e9e Mon Sep 17 00:00:00 2001 From: Vishal Patel Date: Fri, 18 Jul 2025 12:45:10 +0200 Subject: [PATCH 365/931] arm64: zynqmp: Fix pwm-fan polarity The correct operating mode for the fan is inversed (1). The previous pwm driver implementation had a bug and the polarity information was propagated incorrectly to the kernel. The normal (0) polarity specified in the device tree was incorrectly clearing the polarity bit in the counter control register. After the bug fix, setting the polarity to inversed (1) in the device tree will clear the polarity bit. Also provide label for custom description based on this SOM. Signed-off-by: Vishal Patel Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e6dc9ce1e0b97c9d9b073c323cc94a5d7a88b94a.1752835502.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 51778df5540c..500af1d2232f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -90,10 +90,10 @@ ds36-led { }; }; - pwm-fan { + pwm_fan: pwm-fan { compatible = "pwm-fan"; status = "okay"; - pwms = <&ttc0 2 40000 0>; + pwms = <&ttc0 2 40000 1>; }; }; From ea0e0089f7c5a9650f8562e04e20f479689d9dec Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 18 Jul 2025 12:45:11 +0200 Subject: [PATCH 366/931] arm64: zynqmp: Introduce DP port labels Describe every port by unique label for easier wiring with DT overlays. And also labels help to describe which port is used for what. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/99ec1532d0cce877b1d365ede9bd15a909706637.1752835502.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 10 ++++------ arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 10 ++++------ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 12 ++++++------ 3 files changed, 14 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 7490efea98bd..1d2b46d7949e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -112,13 +112,11 @@ &zynqmp_dpsub { phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; +}; - ports { - port@5 { - dpsub_dp_out: endpoint { - remote-endpoint = <&dpcon_in>; - }; - }; +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 7beedd730f94..cd132abf6e00 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -1042,12 +1042,10 @@ &zynqmp_dpsub { phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 3>, <&psgtr 0 PHY_TYPE_DP 1 3>; +}; - ports { - port@5 { - dpsub_dp_out: endpoint { - remote-endpoint = <&dpcon_in>; - }; - }; +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index e11d282462bd..b20a560741e5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -1319,22 +1319,22 @@ ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + live_video: port@0 { reg = <0>; }; - port@1 { + live_gfx: port@1 { reg = <1>; }; - port@2 { + live_audio: port@2 { reg = <2>; }; - port@3 { + out_video: port@3 { reg = <3>; }; - port@4 { + out_audio: port@4 { reg = <4>; }; - port@5 { + out_dp: port@5 { reg = <5>; }; }; From 722a3df12e5e56b4d95e77878522c7fbaba19b39 Mon Sep 17 00:00:00 2001 From: Rohit Visavalia Date: Fri, 18 Jul 2025 12:45:12 +0200 Subject: [PATCH 367/931] arm64: zynqmp: Enable DP for zcu100, zcu102, zcu104, zcu111 Upstream DP DT binding enforcing dp-connector and port description to operate properly. Signed-off-by: Rohit Visavalia Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/0ac8df0c942ed9068e0b60a840fee6b9f7df2293.1752835502.git.michal.simek@amd.com --- .../boot/dts/xilinx/zynqmp-zcu100-revC.dts | 18 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 18 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu104-revA.dts | 18 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu104-revC.dts | 18 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu111-revA.dts | 18 ++++++++++++++++++ 5 files changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 3542844e6977..4ec8a400494e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -134,6 +134,18 @@ si5335_1: si5335-1 { /* clk1_dp - u23 */ #clock-cells = <0>; clock-frequency = <27000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &dcc { @@ -607,3 +619,9 @@ &zynqmp_dpsub { phys = <&psgtr 1 PHY_TYPE_DP 0 1>, <&psgtr 0 PHY_TYPE_DP 1 1>; }; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 7e26489a1539..e172a30e7b21 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -151,6 +151,18 @@ refhdmi: refhdmi { #clock-cells = <0>; clock-frequency = <114285000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &can1 { @@ -1045,3 +1057,9 @@ &zynqmp_dpsub { phy-names = "dp-phy0"; phys = <&psgtr 1 PHY_TYPE_DP 0 3>; }; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index eb2090673ec1..fe8f151ed706 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -60,6 +60,18 @@ clock_8t49n287_3: clk27 { #clock-cells = <0>; clock-frequency = <27000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &can1 { @@ -529,3 +541,9 @@ &zynqmp_dpsub { phys = <&psgtr 1 PHY_TYPE_DP 0 3>, <&psgtr 0 PHY_TYPE_DP 1 3>; }; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 4694d0a841f1..3ee8ab224722 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -65,6 +65,18 @@ clock_8t49n287_3: clk27 { #clock-cells = <0>; clock-frequency = <27000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &can1 { @@ -541,3 +553,9 @@ &zynqmp_dpsub { phys = <&psgtr 1 PHY_TYPE_DP 0 3>, <&psgtr 0 PHY_TYPE_DP 1 3>; }; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index a0cddaa64424..428b5558fbba 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -129,6 +129,18 @@ ref48: ref48M { #clock-cells = <0>; clock-frequency = <48000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &dcc { @@ -864,3 +876,9 @@ &zynqmp_dpsub { phys = <&psgtr 1 PHY_TYPE_DP 0 1>, <&psgtr 0 PHY_TYPE_DP 1 1>; }; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; From f4c3831ba8b771d308f6989d40e0d539d5cd69f6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 18 Jul 2025 13:50:10 +0200 Subject: [PATCH 368/931] arm64: zynqmp: Enable PSCI 1.0 TF-A is using PSCI 1.0 version for quite a long time but it was never reflected in DT. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/32be8050838512d4340486227c32f38298ddde57.1752839409.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index b20a560741e5..5f26649c9e11 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -187,7 +187,7 @@ pmu { }; psci { - compatible = "arm,psci-0.2"; + compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; From 2b0bff8c69d73cc33fc74c1e197f58ff9c7fd8c2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 18 Jul 2025 13:24:06 +0200 Subject: [PATCH 369/931] dt-bindings: soc: xilinx: Add support for K24, KR260 and KD240 CCs The commit 7a4c31ee877a ("arm64: zynqmp: Add support for Xilinx Kria SOM board") has added support for k26 and kv260 and the commit dbcd27526e6a ("dt-bindings: soc: xilinx: Add support for KV260 CC") has added support for KV260 and this is follow up patch for adding description for k24 SOM, KR260 (robotics platform) and KD240 (driver platform). The bootflow is the same that's why for more information please take a look at above commits. The KD240 kit is based on smaller k24 SOM with only 2GB of memory. Reviewed-by: Rob Herring (Arm) Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8ff66d0dc4e0de6f239c25d43a2a96b4224305e8.1752837842.git.michal.simek@amd.com --- .../bindings/soc/xilinx/xilinx.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml index fb5c39c79d28..c9f99e0df2b3 100644 --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml @@ -116,6 +116,36 @@ properties: - const: xlnx,zynqmp-zcu111 - const: xlnx,zynqmp + - description: Xilinx Kria SOMs K24 + minItems: 3 + items: + enum: + - xlnx,zynqmp-sm-k24-rev1 + - xlnx,zynqmp-sm-k24-revB + - xlnx,zynqmp-sm-k24-revA + - xlnx,zynqmp-sm-k24 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp + - contains: + const: xlnx,zynqmp-sm-k24 + + - description: Xilinx Kria SOMs K24 (starter) + minItems: 3 + items: + enum: + - xlnx,zynqmp-smk-k24-rev1 + - xlnx,zynqmp-smk-k24-revB + - xlnx,zynqmp-smk-k24-revA + - xlnx,zynqmp-smk-k24 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp + - contains: + const: xlnx,zynqmp-smk-k24 + - description: Xilinx Kria SOMs minItems: 3 items: @@ -148,6 +178,57 @@ properties: - contains: const: xlnx,zynqmp-smk-k26 + - description: Xilinx Kria SOM KD240 revA/B/1 + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kd240-rev1 + - xlnx,zynqmp-sk-kd240-revB + - xlnx,zynqmp-sk-kd240-revA + - xlnx,zynqmp-sk-kd240 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kd240-revA + - contains: + const: xlnx,zynqmp-sk-kd240 + - contains: + const: xlnx,zynqmp + + - description: Xilinx Kria SOM KR260 revA/Y/Z + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kr260-revA + - xlnx,zynqmp-sk-kr260-revY + - xlnx,zynqmp-sk-kr260-revZ + - xlnx,zynqmp-sk-kr260 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kr260-revA + - contains: + const: xlnx,zynqmp-sk-kr260 + - contains: + const: xlnx,zynqmp + + - description: Xilinx Kria SOM KR260 rev2/1/B + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kr260-rev2 + - xlnx,zynqmp-sk-kr260-rev1 + - xlnx,zynqmp-sk-kr260-revB + - xlnx,zynqmp-sk-kr260 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kr260-revB + - contains: + const: xlnx,zynqmp-sk-kr260 + - contains: + const: xlnx,zynqmp + - description: Xilinx Kria SOM KV260 revA/Y/Z minItems: 3 items: From 7030418d4ea3ee50f1be4cefb2c6fe67016ce2ad Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 18 Jul 2025 13:24:07 +0200 Subject: [PATCH 370/931] arm64: zynqmp: Add support for kr260 board The kit based on K26 SOM is built for robotics and industrial application. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/650ff5407528b8a90867ff1ac072b4112c91c866.1752837842.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/Makefile | 9 + .../boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso | 438 +++++++++++++++++ .../boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso | 451 ++++++++++++++++++ 3 files changed, 898 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index 7f5a8801cad1..5e84e3c725e2 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -30,4 +30,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revA.dtb zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revB.dtb +zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revA.dtb +zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revB.dtb +zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revA.dtb +zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revB.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += versal-net-vn-x-b2197-01-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso new file mode 100644 index 000000000000..fbacfa984d76 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KR260 revA Carrier Card + * + * (C) Copyright 2021, Xilinx, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sk-kr260-revA", + "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; + model = "ZynqMP KR260 revA"; + + aliases { + ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */ + ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; + }; + + clk_27: clock0 { /* u86 - DP */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clk_125: si5332-0 { /* u17 - GEM0/1 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk_74: si5332-5 { /* u17 - SLVC-EC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; + + clk_26: si5332-2 { /* u17 - USB */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_156: si5332-3 { /* u17 - SFP+ */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + + clk_25_0: si5332-1 { /* u17 - GEM2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk_25_1: si5332-4 { /* u17 - GEM3 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + + slg7xl45106: gpio@11 { /* u19 - reset logic */ + compatible = "dlg,slg7xl45106"; + reg = <0x11>; + label = "resetchip"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", + "SD_RESET_B", "USB0_HUB_RESET_B", + "USB1_HUB_RESET_B", "PS_GEM0_RESET_B", + "PS_GEM1_RESET_B", ""; + }; + + i2c-mux@74 { /* u18 */ + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + usbhub_i2c0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + hub_1: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; + }; + usbhub_i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + hub_2: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; + }; + /* Bus 2/3 are not connected */ + }; + + /* si5332@6a - u17 - clock-generator */ +}; + +/* GEM SGMII/DP and USB 3.0 */ +&psgtr { + status = "okay"; + /* gem0/1, dp, usb */ + clocks = <&clk_125>, <&clk_27>, <&clk_26>; + clock-names = "ref0", "ref1", "ref2"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0"; + phys = <&psgtr 1 PHY_TYPE_DP 0 1>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; +}; + +&zynqmp_dpdma { + status = "okay"; + assigned-clock-rates = <600000000>; +}; + +&usb0 { /* mio52 - mio63 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; +}; + +&usb1 { /* mio64 - mio75 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; + reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; +}; + +&dwc3_1 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub1_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub1_3_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub1_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub1_2_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; +}; + +&gem0 { /* mdio mio50/51 */ + status = "okay"; + phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + assigned-clock-rates = <250000000>; +}; + +&gem1 { /* mdio mio50/51, gem mio38 - mio49 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem1_default>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@4 { /* u81 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <4>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <300>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; + }; + phy1: ethernet-phy@8 { /* u36 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <8>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* gem2/gem3 via PL with phys u79@2 and u80@3 */ + +&pinctrl0 { + status = "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + output-enable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups = "ethernet1_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO44", "MIO46", "MIO48"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO45", "MIO47", "MIO49"; + bias-disable; + output-enable; + low-power-disable; + }; + + conf-tx { + pins = "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + output-enable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + output-enable; + }; + + mux-mdio { + function = "mdio1"; + groups = "mdio1_0_grp"; + }; + + mux { + function = "ethernet1"; + groups = "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + power-source = ; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = ; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = ; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups = "usb1_0_grp"; + power-source = ; + }; + + conf-rx { + pins = "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = ; + }; + + conf-tx { + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = ; + }; + + mux { + groups = "usb1_0_grp"; + function = "usb1"; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso new file mode 100644 index 000000000000..b7cda216b179 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KR260 revB Carrier Card (A03 revision) + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sk-kr260-revB", + "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; + model = "ZynqMP KR260 revB"; + + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; + }; + + clk_125: clock0 { /* u87 - GEM0/1 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk_27: clock1 { /* u86 - DP */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clk_26: clock2 { /* u89 - USB */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_156: clock3 { /* u90 - SFP+ */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + + clk_25_0: clock4 { /* u92/u91 - GEM2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk_25_1: clock5 { /* u92/u91 - GEM3 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk_74: clock6 { /* u88 - SLVC-EC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + + slg7xl45106: gpio@11 { /* u19 - reset logic */ + compatible = "dlg,slg7xl45106"; + reg = <0x11>; + label = "resetchip"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", + "SD_RESET_B", "USB0_HUB_RESET_B", + "USB1_HUB_RESET_B", "PS_GEM0_RESET_B", + "PS_GEM1_RESET_B", ""; + }; + + i2c-mux@74 { /* u18 */ + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + usbhub_i2c0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + hub_1: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; + }; + usbhub_i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + hub_2: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; + }; + /* Bus 2/3 are not connected */ + }; + + /* si5332@6a - u17 - clock-generator */ +}; + +/* GEM SGMII/DP and USB 3.0 */ +&psgtr { + status = "okay"; + /* gem0/1, dp, usb */ + clocks = <&clk_125>, <&clk_27>, <&clk_26>; + clock-names = "ref0", "ref1", "ref2"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0"; + phys = <&psgtr 1 PHY_TYPE_DP 0 1>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; +}; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; + +&zynqmp_dpdma { + status = "okay"; + assigned-clock-rates = <600000000>; +}; + +&usb0 { /* mio52 - mio63 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub_1>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; +}; + +&usb1 { /* mio64 - mio75 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; + reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; +}; + +&dwc3_1 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub1_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub1_3_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub1_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub1_2_0>; + i2c-bus = <&hub_2>; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; +}; + +&gem0 { /* mdio mio50/51 */ + status = "okay"; + phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + assigned-clock-rates = <250000000>; +}; + +&gem1 { /* mdio mio50/51, gem mio38 - mio49 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem1_default>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@4 { /* u81 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <4>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <300>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; + }; + phy1: ethernet-phy@8 { /* u36 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <8>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* gem2/gem3 via PL with phys u79@2 and u80@3 */ + +&pinctrl0 { + status = "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + output-enable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups = "ethernet1_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO44", "MIO46", "MIO48"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO45", "MIO47", "MIO49"; + bias-disable; + output-enable; + low-power-disable; + }; + + conf-tx { + pins = "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + output-enable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + output-enable; + }; + + mux-mdio { + function = "mdio1"; + groups = "mdio1_0_grp"; + }; + + mux { + function = "ethernet1"; + groups = "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + power-source = ; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = ; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = ; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups = "usb1_0_grp"; + power-source = ; + }; + + conf-rx { + pins = "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = ; + }; + + conf-tx { + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = ; + }; + + mux { + groups = "usb1_0_grp"; + function = "usb1"; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; From 4f96c5db61f238e8a957df2b81d6343a5e38ca59 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 18 Jul 2025 13:24:08 +0200 Subject: [PATCH 371/931] arm64: zynqmp: Add support for kd240 board The kit is using k24 SOM by default and it is used for motor control and DSP applications. K24 SOM is also possible to used with kv260 and kr260 CC which are also wired in Makefile. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/05ff505c6b6517e3aba983a21454c568c5e86389.1752837842.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/Makefile | 15 + .../boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso | 390 ++++++++++++++++++ .../boot/dts/xilinx/zynqmp-sm-k24-revA.dts | 23 ++ .../boot/dts/xilinx/zynqmp-smk-k24-revA.dts | 21 + 4 files changed, 449 insertions(+) create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile index 5e84e3c725e2..70fac0b276df 100644 --- a/arch/arm64/boot/dts/xilinx/Makefile +++ b/arch/arm64/boot/dts/xilinx/Makefile @@ -39,4 +39,19 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revA.dtb zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revB.dtb +zynqmp-sm-k24-revA-sck-kd-g-revA-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kd-g-revA.dtb +zynqmp-smk-k24-revA-sck-kd-g-revA-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kd-g-revA.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kd-g-revA.dtb + +zynqmp-sm-k24-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kv-g-revB.dtb +zynqmp-smk-k24-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kv-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kv-g-revB.dtb + +zynqmp-sm-k24-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kr-g-revB.dtb +zynqmp-smk-k24-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k24-revA.dtb zynqmp-sck-kr-g-revB.dtbo +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kr-g-revB.dtb + dtb-$(CONFIG_ARCH_ZYNQMP) += versal-net-vn-x-b2197-01-revA.dtb diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso new file mode 100644 index 000000000000..02be5e1e8686 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KD240 revA Carrier Card + * + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include +#include +#include + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sk-kd240-rev1", + "xlnx,zynqmp-sk-kd240-revB", + "xlnx,zynqmp-sk-kd240-revA", + "xlnx,zynqmp-sk-kd240", "xlnx,zynqmp"; + model = "ZynqMP KD240 revA/B/1"; + + aliases { + ethernet0 = "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + + ina260-u3 { + compatible = "iio-hwmon"; + io-channels = <&u3 0>, <&u3 1>, <&u3 2>; + }; + + clk_26: clock2 { /* u17 - USB */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_25_0: clock4 { /* u92/u91 - GEM2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk_25_1: clock5 { /* u92/u91 - GEM3 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&can0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + u3: ina260@40 { /* u3 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + + slg7xl45106: gpio@11 { /* u13 - reset logic */ + compatible = "dlg,slg7xl45106"; + reg = <0x11>; + label = "resetchip"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB0_PHY_RESET_B", "", + "SD_RESET_B", "USB0_HUB_RESET_B", + "", "PS_GEM0_RESET_B", + "", ""; + }; + + hub: usb-hub@2d { /* u36 */ + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; +}; + +/* USB 3.0 */ +&psgtr { + status = "okay"; + /* usb */ + clocks = <&clk_26>; + clock-names = "ref2"; +}; + +&usb0 { /* mio52 - mio63 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + #address-cells = <1>; + #size-cells = <0>; + + /* 2.0 hub on port 1 */ + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&hub>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + /* 3.0 hub on port 2 */ + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&hub>; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; +}; + +&gem1 { /* mdio mio50/51 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem1_default>; + assigned-clock-rates = <250000000>; + + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@8 { /* Adin u31 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id0283.bc30"; + reg = <8>; + adi,rx-internal-delay-ps = <2000>; + adi,tx-internal-delay-ps = <2000>; + adi,fifo-depth-bits = <8>; + reset-assert-us = <10>; + reset-deassert-us = <5000>; + reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* 2 more ethernet phys u32@2 and u34@3 */ + +&pinctrl0 { /* required by spec */ + status = "okay"; + + pinctrl_can0_default: can0-default { + mux { + function = "can0"; + groups = "can0_16_grp"; + }; + + conf { + groups = "can0_16_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO66"; + bias-pull-up; + }; + + conf-tx { + pins = "MIO67"; + bias-pull-up; + drive-strength = <4>; + }; + }; + + pinctrl_uart0_default: uart0-default { + conf { + groups = "uart0_17_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO70"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO71"; + bias-disable; + }; + + mux { + groups = "uart0_17_grp"; + function = "uart0"; + }; + }; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = ; + power-source = ; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + output-enable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = ; + power-source = ; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups = "ethernet1_0_grp"; + slew-rate = ; + power-source = ; + }; + + conf-rx { + pins = "MIO45", "MIO46", "MIO47", "MIO48"; + bias-disable; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO44", "MIO49"; + bias-disable; + output-enable; + low-power-disable; + }; + + conf-tx { + pins = "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + output-enable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio1_0_grp"; + slew-rate = ; + power-source = ; + bias-disable; + output-enable; + }; + + mux-mdio { + function = "mdio1"; + groups = "mdio1_0_grp"; + }; + + mux { + function = "ethernet1"; + groups = "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + power-source = ; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = ; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = ; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups = "usb1_0_grp"; + power-source = ; + }; + + conf-rx { + pins = "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + drive-strength = <12>; + slew-rate = ; + }; + + conf-tx { + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + output-enable; + drive-strength = <4>; + slew-rate = ; + }; + + mux { + groups = "usb1_0_grp"; + function = "usb1"; + }; + }; +}; + +&uart0 { + status = "okay"; + rts-gpios = <&gpio 72 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + rs485-rts-delay = <10 10>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; + assigned-clock-rates = <100000000>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; + +&zynqmp_dpsub { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts new file mode 100644 index 000000000000..653bd9362264 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k24-revA.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP SM-K24 RevA + * + * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2022, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include "zynqmp-sm-k26-revA.dts" + +/ { + model = "ZynqMP SM-K24 RevA/B/1"; + compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", + "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", + "xlnx,zynqmp"; + + memory@0 { + device_type = "memory"; /* 2GB */ + reg = <0 0 0 0x80000000>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts new file mode 100644 index 000000000000..7308983b15a0 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-smk-k24-revA.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP SMK-K24 RevA + * + * (C) Copyright 2020 - 2021, Xilinx, Inc. + * (C) Copyright 2022, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include "zynqmp-sm-k24-revA.dts" + +/ { + model = "ZynqMP SMK-K24 RevA"; + compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", + "xlnx,zynqmp"; +}; + +&sdhci0 { + status = "disabled"; +}; From 400915493f53b10085648b387cdbb4da5612ebfc Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 22 Aug 2025 19:56:14 +0200 Subject: [PATCH 372/931] dt-bindings: Add Actiontec vendor prefix Actiontec is a US manufacturer of telecom equipment. Acked-by: Conor Dooley Signed-off-by: Linus Walleij Link: https://lore.kernel.org/20250822-ixp4xx-mi424wr-dts-v2-1-cc804884474d@linaro.org --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 77160cd47f54..a0abe9e39291 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -48,6 +48,8 @@ patternProperties: description: Acme Systems srl "^actions,.*": description: Actions Semiconductor Co., Ltd. + "^actiontec,.*": + description: Actiontec Electronics, Inc "^active-semi,.*": description: Active-Semi International Inc "^ad,.*": From 873c5c0a2baf11d7101df3fc7485a0183c8c6c29 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 22 Aug 2025 19:56:15 +0200 Subject: [PATCH 373/931] dt-bindings: arm: ixp4xx: List actiontec devices Add two IXP4xx device families from OpenWrts backlog: Actiontec MI424WR revision A/C and revision D, both of these are IXP4xx devices. Revisions E and later use different chipsets. Acked-by: Conor Dooley Signed-off-by: Linus Walleij Link: https://lore.kernel.org/20250822-ixp4xx-mi424wr-dts-v2-2-cc804884474d@linaro.org --- Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml index d60792b1d995..b7b430896596 100644 --- a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml +++ b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml @@ -16,6 +16,8 @@ properties: oneOf: - items: - enum: + - actiontec,mi424wr-ac + - actiontec,mi424wr-d - adieng,coyote - arcom,vulcan - dlink,dsm-g600-a From 85ac6b806993200fe117f4fd047c74784ec6b515 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 22 Aug 2025 19:56:16 +0200 Subject: [PATCH 374/931] ARM: dts: Add ixp4xx Actiontec MI424WR device trees The Actiontex MI424WR is a pretty widespread home router, made in many different revisions. Revisions A, C and D are based on IXP42x. We add a device tree for the A/C variant and one for the D variant as these differ in the location of the WAN PHY on the MDIO bus, and the ethernet interfaces for the WAN PHY and the DSA switch are switched around. Signed-off-by: Linus Walleij Link: https://lore.kernel.org/20250822-ixp4xx-mi424wr-dts-v2-3-cc804884474d@linaro.org --- arch/arm/boot/dts/intel/ixp/Makefile | 2 + .../ixp/intel-ixp42x-actiontec-mi424wr-ac.dts | 37 +++ .../ixp/intel-ixp42x-actiontec-mi424wr-d.dts | 38 +++ .../ixp/intel-ixp42x-actiontec-mi424wr.dtsi | 272 ++++++++++++++++++ 4 files changed, 349 insertions(+) create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi diff --git a/arch/arm/boot/dts/intel/ixp/Makefile b/arch/arm/boot/dts/intel/ixp/Makefile index ab8525f1ea1d..cb30d8d55016 100644 --- a/arch/arm/boot/dts/intel/ixp/Makefile +++ b/arch/arm/boot/dts/intel/ixp/Makefile @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_IXP4XX) += \ + intel-ixp42x-actiontec-mi424wr-ac.dtb \ + intel-ixp42x-actiontec-mi424wr-d.dtb \ intel-ixp42x-linksys-nslu2.dtb \ intel-ixp42x-linksys-wrv54g.dtb \ intel-ixp42x-freecom-fsg-3.dtb \ diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts new file mode 100644 index 000000000000..413b9255f9e3 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the IXP425-based Actiontec MI424WR revision A and C + * Based on a board file from OpenWrt by Jose Vasconcellos. + */ + +/dts-v1/; + +#include "intel-ixp42x-actiontec-mi424wr.dtsi" + +/ { + model = "Actiontec MI424WR rev A/C"; + compatible = "actiontec,mi424wr-ac", "intel,ixp42x"; + + soc { + /* EthB used for WAN */ + ethernet@c8009000 { + phy-handle = <&phy17>; // 17 on revision A-C + + mdio { + phy17: ethernet-phy@17 { + /* WAN */ + reg = <17>; + }; + }; + }; + + /* EthC used for LAN */ + ethernet@c800a000 { + /* Fixed link to the CPU MII port on the KS8995 */ + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts new file mode 100644 index 000000000000..3619c6411a5c --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the IXP425-based Actiontec MI424WR revision D + * Based on a board file from OpenWrt by Jose Vasconcellos. + */ + +/dts-v1/; + +#include "intel-ixp42x-actiontec-mi424wr.dtsi" + +/ { + model = "Actiontec MI424WR rev D"; + compatible = "actiontec,mi424wr-d", "intel,ixp42x"; + + soc { + /* EthB used for LAN */ + ethernet@c8009000 { + /* Fixed link to the CPU MII port on the KS8995 */ + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio { + /* PHY ID 0x00221450 */ + phy5: ethernet-phy@5 { + /* WAN */ + reg = <5>; + }; + }; + }; + + /* EthC used for WAN */ + ethernet@c800a000 { + phy-handle = <&phy5>; // 5 on revision D + }; + }; +}; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi new file mode 100644 index 000000000000..76fd97c5beb6 --- /dev/null +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the IXP425-based Actiontec MI424WR + * Based on a board file from OpenWrt by Jose Vasconcellos. + */ + +#include "intel-ixp42x.dtsi" +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "uart1:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-wan-coax { + color = ; + function = "wan-coax"; + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-power-alarm { + color = ; + function = LED_FUNCTION_ALARM; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-power { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + led-wireless { + color = ; + function = LED_FUNCTION_WLAN; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led-internet-down { + color = ; + function = "internet-down"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-internet-up { + color = ; + function = "internet-up"; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-lan-coax { + color = ; + function = "lan-coax"; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led-wan-ethernet-alarm { + color = ; + function = "wan-ethernet-alarm"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + /* The last three LEDs are not mounted but traces exist on the PCB */ + led-phone-1 { + color = ; + function = "phone-1"; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led-phone-2 { + color = ; + function = "phone-2"; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led-voip { + color = ; + function = "voip"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-reset { + wakeup-source; + linux,code = ; + label = "reset"; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + }; + + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + ethernet-switch@0 { + compatible = "micrel,ks8995"; + reg = <0>; + spi-max-frequency = <50000000>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-port@0 { + reg = <0>; + label = "lan1"; + phy-mode = "mii"; + phy-handle = <&phy1>; + }; + ethernet-port@1 { + reg = <1>; + label = "lan2"; + phy-mode = "mii"; + phy-handle = <&phy2>; + }; + ethernet-port@2 { + reg = <2>; + label = "lan3"; + phy-mode = "mii"; + phy-handle = <&phy3>; + }; + ethernet-port@3 { + reg = <3>; + label = "lan4"; + phy-mode = "mii"; + phy-handle = <&phy4>; + }; + ethernet-port@4 { + reg = <4>; + ethernet = <ðc>; + phy-mode = "mii"; + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + }; + }; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* + * 8 MB of Flash in 64 0x20000 sized blocks + * mapped in at CS0. + */ + reg = <0 0x00000000 0x0800000>; + + /* Configure expansion bus to allow writes */ + intel,ixp4xx-eb-write-enable = <1>; + + partitions { + compatible = "redboot-fis"; + fis-index-block = <0x3f>; + }; + }; + gpio1: gpio@1,0 { + /* MMIO GPIO at CS1 */ + compatible = "intel,ixp4xx-expansion-bus-mmio-gpio"; + gpio-controller; + #gpio-cells = <2>; + big-endian; + reg = <1 0x00000000 0x2>; + reg-names = "dat"; + /* Expansion bus settings */ + intel,ixp4xx-eb-write-enable = <1>; + + pci-reset-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCI reset"; + }; + pstn-relay-hog-1 { + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "PSTN relay control 1"; + }; + pstn-relay-hog-2 { + gpio-hog; + gpios = <12 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "PSTN relay control 2"; + }; + }; + }; + + pci@c0000000 { + status = "okay"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = + /* IDSEL 13 */ + <0x6800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 8 */ + <0x6800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 6 */ + /* IDSEL 14 */ + <0x7000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */ + <0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 8 */ + /* IDSEL 15 */ + <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 6 */ + <0x7800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 15 is irq 7 */ + }; + + ethb: ethernet@c8009000 { + status = "okay"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "mii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* 1, 2, 3 and 4 are ports on the KS8995 switch */ + phy1: ethernet-phy@1 { + /* LAN1 */ + reg = <1>; + }; + phy2: ethernet-phy@2 { + /* LAN2 */ + reg = <2>; + }; + phy3: ethernet-phy@3 { + /* LAN3 */ + reg = <3>; + }; + phy4: ethernet-phy@4 { + /* LAN4 */ + reg = <4>; + }; + }; + }; + + ethc: ethernet@c800a000 { + status = "okay"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "mii"; + }; + }; +}; From 04334f9e8ed2c5763f5633ad53199d12c96fc795 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Wed, 17 Sep 2025 14:04:08 -0700 Subject: [PATCH 375/931] ARM: dts: microchip: sama7d65: Add GPIO buttons and LEDs Add the USER button as a GPIO input as well as add the LEDs and enable the blue LED as a heartbeat. Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/20250917210409.503830-1-Ryan.Wanner@microchip.com Signed-off-by: Nicolas Ferre --- .../dts/microchip/at91-sama7d65_curiosity.dts | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index c14c52936ecc..ed77c98e3d01 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -11,6 +11,8 @@ #include "sama7d65-pinfunc.h" #include "sama7d65.dtsi" #include +#include +#include #include / { @@ -26,6 +28,43 @@ chosen { stdout-path = "serial0:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button { + label = "PB_USER"; + gpios = <&pioa PIN_PC10 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + + led0: led-red { + color = ; + gpios = <&pioa PIN_PB17 GPIO_ACTIVE_HIGH>; /* Conflict with pwm. */ + }; + + led1: led-green { + color = ; + gpios = <&pioa PIN_PB15 GPIO_ACTIVE_HIGH>; /* Conflict with pwm. */ + }; + + led2: led-blue { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&pioa PIN_PA21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; @@ -352,6 +391,18 @@ pinctrl_i2c10_default: i2c10-default { bias-pull-up; }; + pinctrl_key_gpio_default: key-gpio-default { + pinmux = ; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led-gpio-default { + pinmux = , + , + ; + bias-pull-up; + }; + pinctrl_sdmmc1_default: sdmmc1-default { cmd-data { pinmux = , From 82ab67d762e922bb5df1cbb442e8d4f12c26a7ae Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 5 Sep 2025 11:20:44 +0200 Subject: [PATCH 376/931] ARM: dts: microchip: sama7d65: add uart3 definition for flexcom3 peripheral Add the definition of uart3 at the side of i2c3 for flexcom3. Signed-off-by: Nicolas Ferre Reviewed-by: Ryan Wanner Link: https://lore.kernel.org/r/20250905092044.25429-1-nicolas.ferre@microchip.com [claudiu.beznea: moved atmel,usart-mode at the end of the node to comply with dts coding style] Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 84bac1d29421..e53e2dd6d530 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -506,6 +506,21 @@ flx3: flexcom@e182c000 { #size-cells = <1>; status = "disabled"; + uart3: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + clock-names = "usart"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, + <&dma0 AT91_XDMAC_DT_PERID(11)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,usart-mode = ; + status = "disabled"; + }; + i2c3: i2c@600 { compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; From 1219992e16689f4937a333c98d90cf80ba91860a Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Fri, 15 Aug 2025 10:04:57 +0300 Subject: [PATCH 377/931] arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label The '2' in 'hsi2c23' was missed while making the device tree. Fix that so we can properly reference the node. Signed-off-by: Ivaylo Ivanov Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20250815070500.3275491-2-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi index f618ff290604..5877da7baf5c 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi @@ -1438,7 +1438,7 @@ i3c11_bus: i3c11-bus-pins { samsung,pin-drv = ; }; - hsi223_bus: hsi2c23-bus-pins { + hsi2c23_bus: hsi2c23-bus-pins { samsung,pins = "gpp11-2", "gpp11-3"; samsung,pin-function = ; samsung,pin-pud = ; From ad8ea30db80f825215d071370989b8ac45298a1a Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Fri, 15 Aug 2025 10:04:58 +0300 Subject: [PATCH 378/931] arm64: dts: exynos2200: use 32-bit address space for /soc All peripherals on this SoC are mapped under the 32-bit address space (0x0 -> 0x20000000), so enforce that. Suggested-by: Sam Protsenko Signed-off-by: Ivaylo Ivanov Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20250815070500.3275491-3-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 72 +++++++++++----------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi index 6b5ac02d010f..943e83851782 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -221,22 +221,22 @@ psci { method = "smc"; }; - soc { + soc@0 { compatible = "simple-bus"; - ranges; + ranges = <0x0 0x0 0x0 0x20000000>; - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; chipid@10000000 { compatible = "samsung,exynos2200-chipid", "samsung,exynos850-chipid"; - reg = <0x0 0x10000000 0x0 0x24>; + reg = <0x10000000 0x24>; }; cmu_peris: clock-controller@10020000 { compatible = "samsung,exynos2200-cmu-peris"; - reg = <0x0 0x10020000 0x0 0x8000>; + reg = <0x10020000 0x8000>; #clock-cells = <1>; clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>, @@ -250,7 +250,7 @@ cmu_peris: clock-controller@10020000 { mct_peris: timer@10040000 { compatible = "samsung,exynos2200-mct-peris", "samsung,exynos4210-mct"; - reg = <0x0 0x10040000 0x0 0x800>; + reg = <0x10040000 0x800>; clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>, <&cmu_peris CLK_MOUT_PERIS_GIC>; clock-names = "fin_pll", "mct"; interrupts = , @@ -270,8 +270,8 @@ mct_peris: timer@10040000 { gic: interrupt-controller@10200000 { compatible = "arm,gic-v3"; - reg = <0x0 0x10200000 0x0 0x10000>, /* GICD */ - <0x0 0x10240000 0x0 0x200000>; /* GICR * 8 */ + reg = <0x10200000 0x10000>, /* GICD */ + <0x10240000 0x200000>; /* GICR * 8 */ #interrupt-cells = <4>; interrupt-controller; @@ -294,7 +294,7 @@ ppi_cluster2: interrupt-partition-2 { cmu_peric0: clock-controller@10400000 { compatible = "samsung,exynos2200-cmu-peric0"; - reg = <0x0 0x10400000 0x0 0x8000>; + reg = <0x10400000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -306,17 +306,17 @@ cmu_peric0: clock-controller@10400000 { syscon_peric0: syscon@10420000 { compatible = "samsung,exynos2200-peric0-sysreg", "syscon"; - reg = <0x0 0x10420000 0x0 0x2000>; + reg = <0x10420000 0x2000>; }; pinctrl_peric0: pinctrl@10430000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x10430000 0x0 0x1000>; + reg = <0x10430000 0x1000>; }; cmu_peric1: clock-controller@10700000 { compatible = "samsung,exynos2200-cmu-peric1"; - reg = <0x0 0x10700000 0x0 0x8000>; + reg = <0x10700000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -328,23 +328,23 @@ cmu_peric1: clock-controller@10700000 { syscon_peric1: syscon@10720000 { compatible = "samsung,exynos2200-peric1-sysreg", "syscon"; - reg = <0x0 0x10720000 0x0 0x2000>; + reg = <0x10720000 0x2000>; }; pinctrl_peric1: pinctrl@10730000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x10730000 0x0 0x1000>; + reg = <0x10730000 0x1000>; }; cmu_hsi0: clock-controller@10a00000 { compatible = "samsung,exynos2200-cmu-hsi0"; - reg = <0x0 0x10a00000 0x0 0x8000>; + reg = <0x10a00000 0x8000>; #clock-cells = <1>; }; usb32drd: phy@10aa0000 { compatible = "samsung,exynos2200-usb32drd-phy"; - reg = <0x0 0x10aa0000 0x0 0x10000>; + reg = <0x10aa0000 0x10000>; clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; clock-names = "phy"; @@ -360,7 +360,7 @@ usb32drd: phy@10aa0000 { usb_hsphy: phy@10ab0000 { compatible = "samsung,exynos2200-eusb2-phy"; - reg = <0x0 0x10ab0000 0x0 0x10000>; + reg = <0x10ab0000 0x10000>; clocks = <&cmu_hsi0 CLK_MOUT_HSI0_USB32DRD>, <&cmu_hsi0 CLK_MOUT_HSI0_NOC>, @@ -374,7 +374,7 @@ usb_hsphy: phy@10ab0000 { usb: usb@10b00000 { compatible = "samsung,exynos2200-dwusb3"; - ranges = <0x0 0x0 0x10b00000 0x10000>; + ranges = <0x0 0x10b00000 0x10000>; clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; clock-names = "link_aclk"; @@ -406,7 +406,7 @@ usb_dwc3: usb@0 { cmu_ufs: clock-controller@11000000 { compatible = "samsung,exynos2200-cmu-ufs"; - reg = <0x0 0x11000000 0x0 0x8000>; + reg = <0x11000000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -418,27 +418,27 @@ cmu_ufs: clock-controller@11000000 { syscon_ufs: syscon@11020000 { compatible = "samsung,exynos2200-ufs-sysreg", "syscon"; - reg = <0x0 0x11020000 0x0 0x2000>; + reg = <0x11020000 0x2000>; }; pinctrl_ufs: pinctrl@11040000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x11040000 0x0 0x1000>; + reg = <0x11040000 0x1000>; }; pinctrl_hsi1ufs: pinctrl@11060000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x11060000 0x0 0x1000>; + reg = <0x11060000 0x1000>; }; pinctrl_hsi1: pinctrl@11240000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x11240000 0x0 0x1000>; + reg = <0x11240000 0x1000>; }; cmu_peric2: clock-controller@11c00000 { compatible = "samsung,exynos2200-cmu-peric2"; - reg = <0x0 0x11c00000 0x0 0x8000>; + reg = <0x11c00000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -450,17 +450,17 @@ cmu_peric2: clock-controller@11c00000 { syscon_peric2: syscon@11c20000 { compatible = "samsung,exynos2200-peric2-sysreg", "syscon"; - reg = <0x0 0x11c20000 0x0 0x4000>; + reg = <0x11c20000 0x4000>; }; pinctrl_peric2: pinctrl@11c30000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x11c30000 0x0 0x1000>; + reg = <0x11c30000 0x1000>; }; cmu_cmgp: clock-controller@14e00000 { compatible = "samsung,exynos2200-cmu-cmgp"; - reg = <0x0 0x14e00000 0x0 0x8000>; + reg = <0x14e00000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -471,12 +471,12 @@ cmu_cmgp: clock-controller@14e00000 { syscon_cmgp: syscon@14e20000 { compatible = "samsung,exynos2200-cmgp-sysreg", "syscon"; - reg = <0x0 0x14e20000 0x0 0x2000>; + reg = <0x14e20000 0x2000>; }; pinctrl_cmgp: pinctrl@14e30000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x14e30000 0x0 0x1000>; + reg = <0x14e30000 0x1000>; wakeup-interrupt-controller { compatible = "samsung,exynos2200-wakeup-eint", @@ -487,7 +487,7 @@ wakeup-interrupt-controller { cmu_vts: clock-controller@15300000 { compatible = "samsung,exynos2200-cmu-vts"; - reg = <0x0 0x15300000 0x0 0x8000>; + reg = <0x15300000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -497,12 +497,12 @@ cmu_vts: clock-controller@15300000 { pinctrl_vts: pinctrl@15320000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x15320000 0x0 0x1000>; + reg = <0x15320000 0x1000>; }; cmu_alive: clock-controller@15800000 { compatible = "samsung,exynos2200-cmu-alive"; - reg = <0x0 0x15800000 0x0 0x8000>; + reg = <0x15800000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -512,7 +512,7 @@ cmu_alive: clock-controller@15800000 { pinctrl_alive: pinctrl@15850000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x15850000 0x0 0x1000>; + reg = <0x15850000 0x1000>; wakeup-interrupt-controller { compatible = "samsung,exynos2200-wakeup-eint", @@ -524,7 +524,7 @@ wakeup-interrupt-controller { pmu_system_controller: system-controller@15860000 { compatible = "samsung,exynos2200-pmu", "samsung,exynos7-pmu", "syscon"; - reg = <0x0 0x15860000 0x0 0x10000>; + reg = <0x15860000 0x10000>; reboot: syscon-reboot { compatible = "syscon-reboot"; @@ -536,7 +536,7 @@ reboot: syscon-reboot { cmu_top: clock-controller@1a320000 { compatible = "samsung,exynos2200-cmu-top"; - reg = <0x0 0x1a320000 0x0 0x8000>; + reg = <0x1a320000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>; From 0dff00633bbc8566fed6483daddddfa0dfdcf83a Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Fri, 15 Aug 2025 10:04:59 +0300 Subject: [PATCH 379/931] arm64: dts: exynos2200: increase the size of all syscons As IP cores are aligned by 0x10000, increase the size of all system register instances to the maximum (0x10000) to allow using accessing registers over the currently set limit. Suggested-by: Sam Protsenko Signed-off-by: Ivaylo Ivanov Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20250815070500.3275491-4-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi index 943e83851782..b3a8933a43c3 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -306,7 +306,7 @@ cmu_peric0: clock-controller@10400000 { syscon_peric0: syscon@10420000 { compatible = "samsung,exynos2200-peric0-sysreg", "syscon"; - reg = <0x10420000 0x2000>; + reg = <0x10420000 0x10000>; }; pinctrl_peric0: pinctrl@10430000 { @@ -328,7 +328,7 @@ cmu_peric1: clock-controller@10700000 { syscon_peric1: syscon@10720000 { compatible = "samsung,exynos2200-peric1-sysreg", "syscon"; - reg = <0x10720000 0x2000>; + reg = <0x10720000 0x10000>; }; pinctrl_peric1: pinctrl@10730000 { @@ -418,7 +418,7 @@ cmu_ufs: clock-controller@11000000 { syscon_ufs: syscon@11020000 { compatible = "samsung,exynos2200-ufs-sysreg", "syscon"; - reg = <0x11020000 0x2000>; + reg = <0x11020000 0x10000>; }; pinctrl_ufs: pinctrl@11040000 { @@ -450,7 +450,7 @@ cmu_peric2: clock-controller@11c00000 { syscon_peric2: syscon@11c20000 { compatible = "samsung,exynos2200-peric2-sysreg", "syscon"; - reg = <0x11c20000 0x4000>; + reg = <0x11c20000 0x10000>; }; pinctrl_peric2: pinctrl@11c30000 { @@ -471,7 +471,7 @@ cmu_cmgp: clock-controller@14e00000 { syscon_cmgp: syscon@14e20000 { compatible = "samsung,exynos2200-cmgp-sysreg", "syscon"; - reg = <0x14e20000 0x2000>; + reg = <0x14e20000 0x10000>; }; pinctrl_cmgp: pinctrl@14e30000 { From 1bc8f09ce98ca8a56f2059c9a8fe26cc351318f0 Mon Sep 17 00:00:00 2001 From: Ivaylo Ivanov Date: Fri, 15 Aug 2025 10:05:00 +0300 Subject: [PATCH 380/931] arm64: dts: exynos2200: define all usi nodes Universal Serial Interface (USI) supports three types of serial interfaces - uart, i2c and spi. Each protocol can work independently and configured using external configuration inputs. As each USI instance has access to 4 pins, there are multiple possible configurations: - the first 2 and the last 2 pins can be i2c (sda/scl) or uart (rx/tx) - the 4 pins can be used for 4 pin uart or spi For each group of 4 pins, there is one usi instance that can access all 4 pins, and a second usi instance that can be used to set the last 2 pins in i2c mode. Such configuration can be achieved by setting the mode property of usiX and usiX_i2c nodes correctly - if usiX is set to take up 2 pins, then usiX_i2c can be set to take the other 2. If usiX is set for 4 pins, then usiX_i2c should be left disabled. Define all the USI nodes from peric0 (usi4), peric1 (usi7-10), peric2 (usi0-6, usi11) and cmgp (usi0-6_cmgp, 2 pin usi7_cmgp) blocks, as well as their respective uart and i2c subnodes. Suffix labels for blocks in CMGP instances with _cmgpX, and follow the naming conventions from the vendor kernel to avoid confusion. Spi support will be added later on. Signed-off-by: Ivaylo Ivanov Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20250815070500.3275491-5-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 1361 ++++++++++++++++++++ 1 file changed, 1361 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi index b3a8933a43c3..933ab7818ab2 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -7,6 +7,7 @@ #include #include +#include / { compatible = "samsung,exynos2200"; @@ -314,6 +315,76 @@ pinctrl_peric0: pinctrl@10430000 { reg = <0x10430000 0x1000>; }; + usi4: usi@105000c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x105000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI04>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric0 0x1024>; + status = "disabled"; + + hsi2c_8: i2c@10500000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10500000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_DOUT_PERIC0_USI04>, + <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c8_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_6: serial@10500000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10500000 0xc0>; + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI04>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart6_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi4_i2c: usi@105100c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x105100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_peric0 0x1024>; + status = "disabled"; + + hsi2c_9: i2c@10510000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10510000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_DOUT_PERIC0_I2C>, + <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c9_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + cmu_peric1: clock-controller@10700000 { compatible = "samsung,exynos2200-cmu-peric1"; reg = <0x10700000 0x8000>; @@ -336,6 +407,287 @@ pinctrl_peric1: pinctrl@10730000 { reg = <0x10730000 0x1000>; }; + usi7: usi@109000c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric1 0x2030>; + status = "disabled"; + + hsi2c_14: i2c@10900000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10900000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI07>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c14_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_9: serial@10900000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10900000 0xc0>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart9_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi7_i2c: usi@109100c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07_SPI_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_peric1 0x2034>; + status = "disabled"; + + hsi2c_15: i2c@10910000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10910000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI07_SPI_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c15_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi8: usi@109200c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric1 0x2038>; + status = "disabled"; + + hsi2c_16: i2c@10920000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10920000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI08>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c16_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_10: serial@10920000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10920000 0xc0>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart10_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi8_i2c: usi@109300c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08_SPI_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_peric1 0x203c>; + status = "disabled"; + + hsi2c_17: i2c@10930000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10930000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI08_SPI_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c17_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi9: usi@109400c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI09>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric1 0x2040>; + status = "disabled"; + + hsi2c_18: i2c@10940000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10940000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI09>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c18_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_11: serial@10940000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10940000 0xc0>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI09>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart11_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi9_i2c: usi@109500c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_peric1 0x2044>; + status = "disabled"; + + hsi2c_19: i2c@10950000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10950000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c19_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi10: usi@109600c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI10>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric1 0x2048>; + status = "disabled"; + + hsi2c_20: i2c@10960000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10960000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI10>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c20_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_12: serial@10960000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10960000 0xc0>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI10>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart12_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi10_i2c: usi@109700c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_peric1 0x204c>; + status = "disabled"; + + hsi2c_21: i2c@10970000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10970000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c21_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + }; + cmu_hsi0: clock-controller@10a00000 { compatible = "samsung,exynos2200-cmu-hsi0"; reg = <0x10a00000 0x8000>; @@ -458,6 +810,496 @@ pinctrl_peric2: pinctrl@11c30000 { reg = <0x11c30000 0x1000>; }; + usi0: usi@11d000c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI00>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x2000>; + status = "disabled"; + + hsi2c_0: i2c@11d00000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d00000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI00>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c0_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_2: serial@11d00000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11d00000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI00>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart2_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi0_i2c: usi@11d100c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI00_SPI_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_peric2 0x2004>; + status = "disabled"; + + hsi2c_1: i2c@11d10000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d10000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI00_SPI_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c1_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi1: usi@11d200c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI01>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x2008>; + status = "disabled"; + + hsi2c_2: i2c@11d20000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d20000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI01>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c2_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_3: serial@11d20000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11d20000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI01>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart3_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi1_i2c: usi@11d300c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI01_SPI_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_peric2 0x200c>; + status = "disabled"; + + hsi2c_3: i2c@11d30000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d30000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI01_SPI_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c3_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi2: usi@11d400c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI02>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x2010>; + status = "disabled"; + + hsi2c_4: i2c@11d40000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d40000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI02>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c4_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_4: serial@11d40000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11d40000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI02>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart4_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi2_i2c: usi@11d500c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_peric2 0x2014>; + status = "disabled"; + + hsi2c_5: i2c@11d50000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d50000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c5_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi3: usi@11d600c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI03>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x2018>; + status = "disabled"; + + hsi2c_6: i2c@11d60000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d60000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI03>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c6_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_5: serial@11d60000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11d60000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI03>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart5_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi3_i2c: usi@11d700c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_peric2 0x201c>; + status = "disabled"; + + hsi2c_7: i2c@11d70000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d70000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c7_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi5_i2c: usi@11d800c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d800c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_peric2 0x102c>; + status = "disabled"; + + hsi2c_11: i2c@11d80000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d80000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c11_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi6_i2c: usi@11d900c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d900c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_peric2 0x1004>; + status = "disabled"; + + hsi2c_13: i2c@11d90000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d90000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c13_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi11: usi@11da00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11da00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI11>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x1058>; + status = "disabled"; + + hsi2c_22: i2c@11da0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11da0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI11>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c22_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_13: serial@11da0000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11da0000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI11>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart13_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi11_i2c: usi@11db00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11db00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_peric2 0x105c>; + status = "disabled"; + + hsi2c_23: i2c@11db0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11db0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c23_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi5: usi@11dd00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11dd00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI05>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x117c>; + status = "disabled"; + + hsi2c_10: i2c@11dd0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11dd0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI05>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c10_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_7: serial@11dd0000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11dd0000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI05>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart7_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi6: usi@11de00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11de00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI06>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x1180>; + status = "disabled"; + + hsi2c_12: i2c@11de0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11de0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI06>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c12_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_8: serial@11de0000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11de0000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI06>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart8_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + cmu_cmgp: clock-controller@14e00000 { compatible = "samsung,exynos2200-cmu-cmgp"; reg = <0x14e00000 0x8000>; @@ -485,6 +1327,525 @@ wakeup-interrupt-controller { }; }; + usi_cmgp0: usi@14f000c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI0>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2000>; + status = "disabled"; + + hsi2c_24: i2c@14f00000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f00000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI0>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c24_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_14: serial@14f00000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14f00000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI0>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart14_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_cmgp0: usi@14f100c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C0>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_cmgp 0x2070>; + status = "disabled"; + + hsi2c_25: i2c@14f10000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f10000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C0>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c25_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi_cmgp1: usi@14f200c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI1>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2010>; + status = "disabled"; + + hsi2c_26: i2c@14f20000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f20000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI1>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c26_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_15: serial@14f20000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14f20000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI1>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart15_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_cmgp1: usi@14f300c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C1>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_cmgp 0x2074>; + status = "disabled"; + + hsi2c_27: i2c@14f30000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f30000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C1>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c27_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi_cmgp2: usi@14f400c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI2>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2020>; + status = "disabled"; + + hsi2c_28: i2c@14f40000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f40000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI2>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c28_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_16: serial@14f40000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14f40000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI2>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart16_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_cmgp2: usi@14f500c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_cmgp 0x2024>; + status = "disabled"; + + hsi2c_29: i2c@14f50000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f50000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c29_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi_cmgp3: usi@14f600c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI3>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2030>; + status = "disabled"; + + hsi2c_30: i2c@14f60000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f60000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI3>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c30_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_17: serial@14f60000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14f60000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI3>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart17_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_cmgp3: usi@14f700c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_cmgp 0x2034>; + status = "disabled"; + + hsi2c_31: i2c@14f70000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f70000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c31_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi_cmgp4: usi@14f800c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f800c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI4>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2040>; + status = "disabled"; + + hsi2c_32: i2c@14f80000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f80000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI4>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c32_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_18: serial@14f80000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14f80000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI4>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart18_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_cmgp4: usi@14f900c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f900c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_cmgp 0x2044>; + status = "disabled"; + + hsi2c_33: i2c@14f90000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f90000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c33_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi_cmgp5: usi@14fa00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14fa00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI5>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2050>; + status = "disabled"; + + hsi2c_34: i2c@14fa0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14fa0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI5>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c34_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_19: serial@14fa0000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14fa0000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI5>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart19_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_cmgp5: usi@14fb00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14fb00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_cmgp 0x2054>; + status = "disabled"; + + hsi2c_35: i2c@14fb0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14fb0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c35_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi_cmgp6: usi@14fc00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14fc00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI6>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2060>; + status = "disabled"; + + hsi2c_36: i2c@14fc0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14fc0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI6>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c36_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_20: serial@14fc0000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14fc0000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI6>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart20_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi_i2c_cmgp6: usi@14fd00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14fd00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_cmgp 0x2064>; + status = "disabled"; + + hsi2c_37: i2c@14fd0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14fd0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c37_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi_i2c_cmgp7: usi@14fe00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14fe00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = ; + samsung,sysreg = <&syscon_cmgp 0x2080>; + status = "disabled"; + + hsi2c_38: i2c@14fe0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14fe0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = ; + pinctrl-0 = <&hsi2c38_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + cmu_vts: clock-controller@15300000 { compatible = "samsung,exynos2200-cmu-vts"; reg = <0x15300000 0x8000>; From b3a62f6c3573e448e8b0697a622e7bba0ddf9945 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:14:24 +0200 Subject: [PATCH 381/931] arm64: dts: exynos5433: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: exynos5433-tm2-common.dtsi:1000.2-41: Warning (interrupt_map): /soc@0/pcie@15700000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@11001000, using 0 as fallbac Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20250822121423.228500-5-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 0b9053b9b2b5..fa2029e280a5 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -937,6 +937,7 @@ reboot: syscon-reboot { gic: interrupt-controller@11001000 { compatible = "arm,gic-400"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x11001000 0x1000>, From a75d45adb261cbced86701d2512098044a6d310f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:14:25 +0200 Subject: [PATCH 382/931] arm64: dts: google: gs101: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node. Value '0' is correct because GIC interrupt controller does not have children. Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20250822121423.228500-6-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index c0f8c25861a9..31c99526470d 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -341,6 +341,7 @@ watchdog_cl1: watchdog@10070000 { gic: interrupt-controller@10400000 { compatible = "arm,gic-v3"; + #address-cells = <0>; #interrupt-cells = <4>; interrupt-controller; reg = <0x10400000 0x10000>, /* GICD */ From a874b387213bd80b1288884aeb427cb7599eb5ea Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:14:26 +0200 Subject: [PATCH 383/931] arm64: dts: fsd: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node. Value '0' is correct because GIC interrupt controller does not have children. Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20250822121423.228500-7-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/tesla/fsd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index a5ebb3f9b18f..5b06e2667b89 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -363,6 +363,7 @@ soc: soc@0 { gic: interrupt-controller@10400000 { compatible = "arm,gic-v3"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */ From 096bd8c679185f898cae9933c6a68650fa26ea4f Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Fri, 29 Aug 2025 12:38:24 +0100 Subject: [PATCH 384/931] arm64: dts: rockchip: Further describe the WiFi for the Pinephone Pro Update the wake-up pin and associated interupt details for the Pinephone Pro WiFi module. Details obtained from the published PinephonePro-Schematic-V1.0-20211127.pdf page 19. Signed-off-by: Peter Robinson Link: https://lore.kernel.org/r/20250829113826.2029755-1-pbrobinson@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-pinephone-pro.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 585ef0fd88ef..a4031dc12e48 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -689,6 +689,12 @@ vcc1v8_codec_en: vcc1v8-codec-en { }; }; + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + wireless-bluetooth { bt_wake_pin: bt-wake-pin { rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; @@ -715,7 +721,19 @@ &sdio0 { pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio4>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; }; &pwm0 { From 7c50e0cea2549a8d673bad62abf9be82b71e5477 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Fri, 29 Aug 2025 05:45:47 +0000 Subject: [PATCH 385/931] arm64: dts: rockchip: add IR receiver to rk3328-roc Add the ir-receiver and ir pinctrl nodes to enable the IR receiver on the ROC-RK3328-CC board. Signed-off-by: Alex Bee Signed-off-by: Christian Hewitt Link: https://lore.kernel.org/r/20250829054547.4053558-1-christianshewitt@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi index b5bd5e7d5748..2449a344f4ec 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi @@ -84,6 +84,13 @@ vcc_phy: regulator-vcc-phy { regulator-boot-on; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int>; + pinctrl-names = "default"; + }; + leds { compatible = "gpio-leds"; @@ -300,6 +307,12 @@ &io_domains { }; &pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; From 2850f6f1ecf2a42c6ae7a6d55874c9eb17eeb622 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 28 Aug 2025 16:54:21 +0000 Subject: [PATCH 386/931] ARM: dts: rockchip: add CEC pinctrl to rk3288-miqi Enable CEC control on the HDMI port for MiQi. Signed-off-by: Alex Bee Signed-off-by: Christian Hewitt Link: https://lore.kernel.org/r/20250828165421.3829740-1-christianshewitt@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts index dd42f8d31f70..96c8827aedd3 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts @@ -130,6 +130,8 @@ &gpu { &hdmi { ddc-i2c-bus = <&i2c5>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec_c0>; status = "okay"; }; From 2a91dcd5be9dde3239c87e4309f5878d3e4fb9d2 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 28 Aug 2025 16:35:01 +0000 Subject: [PATCH 387/931] ARM: dts: rockchip: add HDMI audio to rk3288-miqi Add the sound and i2s nodes to enable HDMI audio output on the MiQi board. Signed-off-by: Alex Bee Signed-off-by: Christian Hewitt Link: https://lore.kernel.org/r/20250828163501.3829226-1-christianshewitt@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3288-miqi.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts index 96c8827aedd3..a5f5c6d38f80 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-miqi.dts @@ -78,6 +78,21 @@ vcc_sys: regulator-vsys { regulator-always-on; regulator-boot-on; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "HDMI"; + simple-audio-card,mclk-fs = <512>; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s>; + }; + }; }; &cpu0 { @@ -285,6 +300,11 @@ &i2c5 { status = "okay"; }; +&i2s { + #sound-dai-cells = <0>; + status = "okay"; +}; + &io_domains { status = "okay"; From 343ea11a2fe32550c1d37b947803f4087a3a94c4 Mon Sep 17 00:00:00 2001 From: Mun Yew Tham Date: Mon, 18 Aug 2025 09:39:32 -0700 Subject: [PATCH 388/931] arm64: dts: Agilex5 Add gmac nodes to DTSI for Agilex5 Add the base device tree nodes for gmac0, gmac1, and gmac2 to the DTSI for the Agilex5 SOCFPGA. Agilex5 has three Ethernet controllers based on Synopsys DWC XGMAC IP version 2.10. Signed-off-by: Mun Yew Tham Signed-off-by: Matthew Gerlach Signed-off-by: Dinh Nguyen --- .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 336 ++++++++++++++++++ 1 file changed, 336 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 7d9394a04302..04e99cd7e74b 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -486,5 +486,341 @@ qspi: spi@108d2000 { clocks = <&qspi_clk>; status = "disabled"; }; + + gmac0: ethernet@10810000 { + compatible = "altr,socfpga-stmmac-agilex5", + "snps,dwxgmac-2.10"; + reg = <0x10810000 0x3500>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr AGILEX5_EMAC0_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + snps,axi-config = <&stmmac_axi_emac0_setup>; + snps,mtl-rx-config = <&mtl_rx_emac0_setup>; + snps,mtl-tx-config = <&mtl_tx_emac0_setup>; + snps,pbl = <32>; + snps,tso; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + snps,clk-csr = <0>; + status = "disabled"; + + stmmac_axi_emac0_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac0_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + mtl_tx_emac0_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight = <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight = <0x0B>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue3 { + snps,weight = <0x0C>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue4 { + snps,weight = <0x0D>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue5 { + snps,weight = <0x0E>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue6 { + snps,weight = <0x0F>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue7 { + snps,weight = <0x10>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + }; + }; + + gmac1: ethernet@10820000 { + compatible = "altr,socfpga-stmmac-agilex5", + "snps,dwxgmac-2.10"; + reg = <0x10820000 0x3500>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr AGILEX5_EMAC1_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + snps,axi-config = <&stmmac_axi_emac1_setup>; + snps,mtl-rx-config = <&mtl_rx_emac1_setup>; + snps,mtl-tx-config = <&mtl_tx_emac1_setup>; + snps,pbl = <32>; + snps,tso; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + snps,clk-csr = <0>; + status = "disabled"; + + stmmac_axi_emac1_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac1_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + mtl_tx_emac1_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight = <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight = <0x0B>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue3 { + snps,weight = <0x0C>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue4 { + snps,weight = <0x0D>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue5 { + snps,weight = <0x0E>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue6 { + snps,weight = <0x0F>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue7 { + snps,weight = <0x10>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + }; + }; + + gmac2: ethernet@10830000 { + compatible = "altr,socfpga-stmmac-agilex5", + "snps,dwxgmac-2.10"; + reg = <0x10830000 0x3500>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr AGILEX5_EMAC2_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + mac-address = [00 00 00 00 00 00]; + tx-fifo-depth = <32768>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + snps,axi-config = <&stmmac_axi_emac2_setup>; + snps,mtl-rx-config = <&mtl_rx_emac2_setup>; + snps,mtl-tx-config = <&mtl_tx_emac2_setup>; + snps,pbl = <32>; + snps,tso; + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + snps,clk-csr = <0>; + status = "disabled"; + + stmmac_axi_emac2_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac2_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + mtl_tx_emac2_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x09>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight = <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight = <0x0B>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue3 { + snps,weight = <0x0C>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue4 { + snps,weight = <0x0D>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue5 { + snps,weight = <0x0E>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue6 { + snps,weight = <0x0F>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + queue7 { + snps,weight = <0x10>; + snps,coe-unsupported; + snps,dcb-algorithm; + }; + }; + }; }; }; From 9cb76813425956f82cf598c357da0c9f36a1d9a8 Mon Sep 17 00:00:00 2001 From: Matthew Gerlach Date: Mon, 18 Aug 2025 09:39:33 -0700 Subject: [PATCH 389/931] arm64: dts: socfpga: agilex5: enable gmac2 on the Agilex5 dev kit Enable gmac2 on the Agilex5 SOCFGPA Development Kit. The MAC is connected to a RGMII PHY on a daughter card. There are no RGMII clock delays implemented the on PCB. Signed-off-by: Matthew Gerlach Signed-off-by: Dinh Nguyen --- .../boot/dts/intel/socfpga_agilex5_socdk.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts index d3b913b7902c..e9776e1cdc9a 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -10,6 +10,9 @@ / { aliases { serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; }; chosen { @@ -37,6 +40,23 @@ &gpio0 { status = "okay"; }; +&gmac2 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac2_phy0>; + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + &gpio1 { status = "okay"; }; From 59abe5c87267f1f3bd627af20355b490b59f9901 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Aug 2025 11:39:19 +0200 Subject: [PATCH 390/931] arm64: dts: exynos2200: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node. Value '0' is correct because GIC interrupt controller does not have children. Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20250830093918.24619-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi index 933ab7818ab2..6487ccb58ae7 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -274,6 +274,7 @@ gic: interrupt-controller@10200000 { reg = <0x10200000 0x10000>, /* GICD */ <0x10240000 0x200000>; /* GICR * 8 */ + #address-cells = <0>; #interrupt-cells = <4>; interrupt-controller; interrupts = ; From 613fb0c8bd49df4fb28bca89aa5363856487096f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:33:19 +0200 Subject: [PATCH 391/931] arm64: dts: socionext: uniphier-ld20: Add default PCI interrup controller address cells Add missing address-cells 0 to the PCI interrupt node to silence W=1 warning: uniphier-ld20.dtsi:941.4-944.29: Warning (interrupt_map): /soc@0/pcie@66000000:interrupt-map: Missing property '#address-cells' in node /soc@0/pcie@66000000/legacy-interrupt-controller, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Reviewed-by: Kunihiko Hayashi Link: https://lore.kernel.org/r/20250822133318.312232-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 335093da6573..875b93856a64 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -947,6 +947,7 @@ pcie: pcie@66000000 { pcie_intc: legacy-interrupt-controller { interrupt-controller; + #address-cells = <0>; #interrupt-cells = <1>; interrupt-parent = <&gic>; interrupts = ; From a29bf0b10a1a7f51afb91c1ff9edd73b0ca1fd18 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:33:20 +0200 Subject: [PATCH 392/931] arm64: dts: socionext: uniphier-pxs3: Add default PCI interrup controller address cells Add missing address-cells 0 to the PCI interrupt node to silence W=1 warning: uniphier-pxs3.dtsi:915.4-918.29: Warning (interrupt_map): /soc@0/pcie@66000000:interrupt-map: Missing property '#address-cells' in node /soc@0/pcie@66000000/legacy-interrupt-controller, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Reviewed-by: Kunihiko Hayashi Link: https://lore.kernel.org/r/20250822133318.312232-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index d6e3cc6fdb25..4d6c3c2dbea6 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -921,6 +921,7 @@ pcie: pcie@66000000 { pcie_intc: legacy-interrupt-controller { interrupt-controller; + #address-cells = <0>; #interrupt-cells = <1>; interrupt-parent = <&gic>; interrupts = ; From ea0484e4b82b3496310a94684dfad5e61421f633 Mon Sep 17 00:00:00 2001 From: Ravi Patel Date: Mon, 25 Aug 2025 17:14:32 +0530 Subject: [PATCH 393/931] dt-bindings: arm: Convert Axis board/soc bindings to json-schema Convert Axis SoC bindings to DT schema format using json-schema. Existing bindings supports ARTPEC-6 SoC and board. Signed-off-by: SungMin Park Signed-off-by: SeonGu Kang Reviewed-by: Rob Herring (Arm) Signed-off-by: Ravi Patel Link: https://lore.kernel.org/r/20250825114436.46882-7-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/axis.txt | 13 --------- .../devicetree/bindings/arm/axis.yaml | 29 +++++++++++++++++++ 2 files changed, 29 insertions(+), 13 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/axis.txt create mode 100644 Documentation/devicetree/bindings/arm/axis.yaml diff --git a/Documentation/devicetree/bindings/arm/axis.txt b/Documentation/devicetree/bindings/arm/axis.txt deleted file mode 100644 index ebd33a88776f..000000000000 --- a/Documentation/devicetree/bindings/arm/axis.txt +++ /dev/null @@ -1,13 +0,0 @@ -Axis Communications AB -ARTPEC series SoC Device Tree Bindings - -ARTPEC-6 ARM SoC -================ - -Required root node properties: -- compatible = "axis,artpec6"; - -ARTPEC-6 Development board: ---------------------------- -Required root node properties: -- compatible = "axis,artpec6-dev-board", "axis,artpec6"; diff --git a/Documentation/devicetree/bindings/arm/axis.yaml b/Documentation/devicetree/bindings/arm/axis.yaml new file mode 100644 index 000000000000..f9c218dc6883 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/axis.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/axis.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axis ARTPEC platforms + +maintainers: + - Jesper Nilsson + - linux-arm-kernel@axis.com + +description: | + ARM platforms using SoCs designed by Axis branded as "ARTPEC". + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Axis ARTPEC-6 SoC board + items: + - enum: + - axis,artpec6-dev-board + - const: axis,artpec6 + +additionalProperties: true + +... From 6e08cdd604edcec2c277af17c7d36caf827057ff Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Sat, 23 Aug 2025 11:49:44 +0200 Subject: [PATCH 394/931] arm64: dts: apple: t8103-j457: Fix PCIe ethernet iommu-map PCIe `port01` of t8103-j457 (iMac, M1, 2 USB-C ports, 2021) is unused and disabled. Linux' PCI subsystem assigns the ethernet nic from `port02` to bus 02. This results into assigning `pcie0_dart_1` from the disabled port as iommu. The `pcie0_dart_1` instance is disabled and probably fused off (it is on the M2 Pro Mac mini which has a disabled PCIe port as well). Without iommu the ethernet nic is not expected work. Adjusts the "bus-range" and the PCIe devices "reg" property to PCI subsystem's bus number. Fixes: 7c77ab91b33d ("arm64: dts: apple: Add missing M1 (t8103) devices") Reviewed-by: Neal Gompa Reviewed-by: Sven Peter Signed-off-by: Janne Grunau Link: https://lore.kernel.org/r/20250823-apple-dt-sync-6-17-v2-1-6dc0daeb4786@jannau.net Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8103-j457.dts | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8103-j457.dts b/arch/arm64/boot/dts/apple/t8103-j457.dts index 152f95fd49a2..7089ccf3ce55 100644 --- a/arch/arm64/boot/dts/apple/t8103-j457.dts +++ b/arch/arm64/boot/dts/apple/t8103-j457.dts @@ -21,6 +21,14 @@ aliases { }; }; +/* + * Adjust pcie0's iommu-map to account for the disabled port01. + */ +&pcie0 { + iommu-map = <0x100 &pcie0_dart_0 1 1>, + <0x200 &pcie0_dart_2 1 1>; +}; + &bluetooth0 { brcm,board-type = "apple,santorini"; }; @@ -36,10 +44,10 @@ &wifi0 { */ &port02 { - bus-range = <3 3>; + bus-range = <2 2>; status = "okay"; ethernet0: ethernet@0,0 { - reg = <0x30000 0x0 0x0 0x0 0x0>; + reg = <0x20000 0x0 0x0 0x0 0x0>; /* To be filled by the loader */ local-mac-address = [00 10 18 00 00 00]; }; From 3050713d84f58d2e4ba463c5474092fa6738c527 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Sat, 23 Aug 2025 11:49:45 +0200 Subject: [PATCH 395/931] arm64: dts: apple: t600x: Add missing WiFi properties Add compatible and antenna-sku properties to the shared node and brcm,board-type property to individuall board device trees. Signed-off-by: Hector Martin Reviewed-by: Neal Gompa Reviewed-by: Sven Peter Signed-off-by: Janne Grunau Link: https://lore.kernel.org/r/20250823-apple-dt-sync-6-17-v2-2-6dc0daeb4786@jannau.net Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t6000-j314s.dts | 4 ++++ arch/arm64/boot/dts/apple/t6000-j316s.dts | 4 ++++ arch/arm64/boot/dts/apple/t6001-j314c.dts | 4 ++++ arch/arm64/boot/dts/apple/t6001-j316c.dts | 4 ++++ arch/arm64/boot/dts/apple/t6001-j375c.dts | 4 ++++ arch/arm64/boot/dts/apple/t6002-j375d.dts | 4 ++++ arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi | 2 ++ arch/arm64/boot/dts/apple/t600x-j375.dtsi | 2 ++ 8 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t6000-j314s.dts b/arch/arm64/boot/dts/apple/t6000-j314s.dts index c9e192848fe3..ac35870ca129 100644 --- a/arch/arm64/boot/dts/apple/t6000-j314s.dts +++ b/arch/arm64/boot/dts/apple/t6000-j314s.dts @@ -16,3 +16,7 @@ / { compatible = "apple,j314s", "apple,t6000", "apple,arm-platform"; model = "Apple MacBook Pro (14-inch, M1 Pro, 2021)"; }; + +&wifi0 { + brcm,board-type = "apple,maldives"; +}; diff --git a/arch/arm64/boot/dts/apple/t6000-j316s.dts b/arch/arm64/boot/dts/apple/t6000-j316s.dts index ff1803ce2300..77d6d8c14d74 100644 --- a/arch/arm64/boot/dts/apple/t6000-j316s.dts +++ b/arch/arm64/boot/dts/apple/t6000-j316s.dts @@ -16,3 +16,7 @@ / { compatible = "apple,j316s", "apple,t6000", "apple,arm-platform"; model = "Apple MacBook Pro (16-inch, M1 Pro, 2021)"; }; + +&wifi0 { + brcm,board-type = "apple,madagascar"; +}; diff --git a/arch/arm64/boot/dts/apple/t6001-j314c.dts b/arch/arm64/boot/dts/apple/t6001-j314c.dts index 1761d15b98c1..0a5655792a8f 100644 --- a/arch/arm64/boot/dts/apple/t6001-j314c.dts +++ b/arch/arm64/boot/dts/apple/t6001-j314c.dts @@ -16,3 +16,7 @@ / { compatible = "apple,j314c", "apple,t6001", "apple,arm-platform"; model = "Apple MacBook Pro (14-inch, M1 Max, 2021)"; }; + +&wifi0 { + brcm,board-type = "apple,maldives"; +}; diff --git a/arch/arm64/boot/dts/apple/t6001-j316c.dts b/arch/arm64/boot/dts/apple/t6001-j316c.dts index 750e9beeffc0..9c215531ea54 100644 --- a/arch/arm64/boot/dts/apple/t6001-j316c.dts +++ b/arch/arm64/boot/dts/apple/t6001-j316c.dts @@ -16,3 +16,7 @@ / { compatible = "apple,j316c", "apple,t6001", "apple,arm-platform"; model = "Apple MacBook Pro (16-inch, M1 Max, 2021)"; }; + +&wifi0 { + brcm,board-type = "apple,madagascar"; +}; diff --git a/arch/arm64/boot/dts/apple/t6001-j375c.dts b/arch/arm64/boot/dts/apple/t6001-j375c.dts index 62ea437b58b2..88ca2037556c 100644 --- a/arch/arm64/boot/dts/apple/t6001-j375c.dts +++ b/arch/arm64/boot/dts/apple/t6001-j375c.dts @@ -16,3 +16,7 @@ / { compatible = "apple,j375c", "apple,t6001", "apple,arm-platform"; model = "Apple Mac Studio (M1 Max, 2022)"; }; + +&wifi0 { + brcm,board-type = "apple,okinawa"; +}; diff --git a/arch/arm64/boot/dts/apple/t6002-j375d.dts b/arch/arm64/boot/dts/apple/t6002-j375d.dts index 3365429bdc8b..f56d13b37eaf 100644 --- a/arch/arm64/boot/dts/apple/t6002-j375d.dts +++ b/arch/arm64/boot/dts/apple/t6002-j375d.dts @@ -38,6 +38,10 @@ hpm5: usb-pd@3a { }; }; +&wifi0 { + brcm,board-type = "apple,okinawa"; +}; + /* delete unused always-on power-domains on die 1 */ /delete-node/ &ps_atc2_usb_aon_die1; diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi index 22ebc78e120b..b699672a5543 100644 --- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi @@ -99,9 +99,11 @@ &port00 { /* WLAN */ bus-range = <1 1>; wifi0: wifi@0,0 { + compatible = "pci14e4,4433"; reg = <0x10000 0x0 0x0 0x0 0x0>; /* To be filled by the loader */ local-mac-address = [00 10 18 00 00 10]; + apple,antenna-sku = "XX"; }; }; diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dts/apple/t600x-j375.dtsi index d5b985ad5679..95560bf3798b 100644 --- a/arch/arm64/boot/dts/apple/t600x-j375.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi @@ -84,9 +84,11 @@ &port00 { /* WLAN */ bus-range = <1 1>; wifi0: wifi@0,0 { + compatible = "pci14e4,4433"; reg = <0x10000 0x0 0x0 0x0 0x0>; /* To be filled by the loader */ local-mac-address = [00 10 18 00 00 10]; + apple,antenna-sku = "XX"; }; }; From c34e2ec6a84ea3f7a01d8fcd3073f858c4f47605 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Sat, 23 Aug 2025 11:49:46 +0200 Subject: [PATCH 396/931] arm64: dts: apple: t600x: Add bluetooth device nodes Add bluetooth PCIe device nodes to specify per device brcm,board-type and provide the bootloader filled "local-bd-address" and calibration data. Signed-off-by: Hector Martin Reviewed-by: Neal Gompa Reviewed-by: Sven Peter Signed-off-by: Janne Grunau Link: https://lore.kernel.org/r/20250823-apple-dt-sync-6-17-v2-3-6dc0daeb4786@jannau.net Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t6000-j314s.dts | 4 ++++ arch/arm64/boot/dts/apple/t6000-j316s.dts | 4 ++++ arch/arm64/boot/dts/apple/t6001-j314c.dts | 4 ++++ arch/arm64/boot/dts/apple/t6001-j316c.dts | 4 ++++ arch/arm64/boot/dts/apple/t6001-j375c.dts | 4 ++++ arch/arm64/boot/dts/apple/t6002-j375d.dts | 4 ++++ arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi | 8 ++++++++ arch/arm64/boot/dts/apple/t600x-j375.dtsi | 8 ++++++++ 8 files changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t6000-j314s.dts b/arch/arm64/boot/dts/apple/t6000-j314s.dts index ac35870ca129..1430b91ff1b1 100644 --- a/arch/arm64/boot/dts/apple/t6000-j314s.dts +++ b/arch/arm64/boot/dts/apple/t6000-j314s.dts @@ -20,3 +20,7 @@ / { &wifi0 { brcm,board-type = "apple,maldives"; }; + +&bluetooth0 { + brcm,board-type = "apple,maldives"; +}; diff --git a/arch/arm64/boot/dts/apple/t6000-j316s.dts b/arch/arm64/boot/dts/apple/t6000-j316s.dts index 77d6d8c14d74..da0cbe7d9673 100644 --- a/arch/arm64/boot/dts/apple/t6000-j316s.dts +++ b/arch/arm64/boot/dts/apple/t6000-j316s.dts @@ -20,3 +20,7 @@ / { &wifi0 { brcm,board-type = "apple,madagascar"; }; + +&bluetooth0 { + brcm,board-type = "apple,madagascar"; +}; diff --git a/arch/arm64/boot/dts/apple/t6001-j314c.dts b/arch/arm64/boot/dts/apple/t6001-j314c.dts index 0a5655792a8f..c37097dcfdb3 100644 --- a/arch/arm64/boot/dts/apple/t6001-j314c.dts +++ b/arch/arm64/boot/dts/apple/t6001-j314c.dts @@ -20,3 +20,7 @@ / { &wifi0 { brcm,board-type = "apple,maldives"; }; + +&bluetooth0 { + brcm,board-type = "apple,maldives"; +}; diff --git a/arch/arm64/boot/dts/apple/t6001-j316c.dts b/arch/arm64/boot/dts/apple/t6001-j316c.dts index 9c215531ea54..3bc6e0c3294c 100644 --- a/arch/arm64/boot/dts/apple/t6001-j316c.dts +++ b/arch/arm64/boot/dts/apple/t6001-j316c.dts @@ -20,3 +20,7 @@ / { &wifi0 { brcm,board-type = "apple,madagascar"; }; + +&bluetooth0 { + brcm,board-type = "apple,madagascar"; +}; diff --git a/arch/arm64/boot/dts/apple/t6001-j375c.dts b/arch/arm64/boot/dts/apple/t6001-j375c.dts index 88ca2037556c..2e7c23714d4d 100644 --- a/arch/arm64/boot/dts/apple/t6001-j375c.dts +++ b/arch/arm64/boot/dts/apple/t6001-j375c.dts @@ -20,3 +20,7 @@ / { &wifi0 { brcm,board-type = "apple,okinawa"; }; + +&bluetooth0 { + brcm,board-type = "apple,okinawa"; +}; diff --git a/arch/arm64/boot/dts/apple/t6002-j375d.dts b/arch/arm64/boot/dts/apple/t6002-j375d.dts index f56d13b37eaf..2b7f80119618 100644 --- a/arch/arm64/boot/dts/apple/t6002-j375d.dts +++ b/arch/arm64/boot/dts/apple/t6002-j375d.dts @@ -42,6 +42,10 @@ &wifi0 { brcm,board-type = "apple,okinawa"; }; +&bluetooth0 { + brcm,board-type = "apple,okinawa"; +}; + /* delete unused always-on power-domains on die 1 */ /delete-node/ &ps_atc2_usb_aon_die1; diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi index b699672a5543..c0aac59a6fae 100644 --- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi @@ -13,6 +13,7 @@ / { aliases { + bluetooth0 = &bluetooth0; serial0 = &serial0; wifi0 = &wifi0; }; @@ -105,6 +106,13 @@ wifi0: wifi@0,0 { local-mac-address = [00 10 18 00 00 10]; apple,antenna-sku = "XX"; }; + + bluetooth0: bluetooth@0,1 { + compatible = "pci14e4,5f71"; + reg = <0x10100 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-bd-address = [00 00 00 00 00 00]; + }; }; &port01 { diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dts/apple/t600x-j375.dtsi index 95560bf3798b..ed38acc0dfc3 100644 --- a/arch/arm64/boot/dts/apple/t600x-j375.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi @@ -11,6 +11,7 @@ / { aliases { + bluetooth0 = &bluetooth0; serial0 = &serial0; wifi0 = &wifi0; }; @@ -90,6 +91,13 @@ wifi0: wifi@0,0 { local-mac-address = [00 10 18 00 00 10]; apple,antenna-sku = "XX"; }; + + bluetooth0: bluetooth@0,1 { + compatible = "pci14e4,5f71"; + reg = <0x10100 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-bd-address = [00 00 00 00 00 00]; + }; }; &port01 { From efad8eaf6f2f00460a2227c618ebb7c8e0dca201 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Sat, 23 Aug 2025 11:49:47 +0200 Subject: [PATCH 397/931] dt-bindings: arm: apple: Add t8112 j415 compatible This adds the "apple,j415" (MacBook Air (15-inch, M2, 2023) to the apple,t8112 platform. Reviewed-by: Neal Gompa Reviewed-by: Sven Peter Signed-off-by: Janne Grunau Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250823-apple-dt-sync-6-17-v2-4-6dc0daeb4786@jannau.net Signed-off-by: Sven Peter --- Documentation/devicetree/bindings/arm/apple.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index da60e9de1cfb..7073535b7c5b 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -92,6 +92,7 @@ description: | Devices based on the "M2" SoC: - MacBook Air (M2, 2022) + - MacBook Air (15-inch, M2, 2023) - MacBook Pro (13-inch, M2, 2022) - Mac mini (M2, 2023) @@ -279,6 +280,7 @@ properties: items: - enum: - apple,j413 # MacBook Air (M2, 2022) + - apple,j415 # MacBook Air (15-inch, M2, 2023) - apple,j473 # Mac mini (M2, 2023) - apple,j493 # MacBook Pro (13-inch, M2, 2022) - const: apple,t8112 From 273be31e5afd31f9de7ca8e5ec5acf1290da90c7 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Sat, 23 Aug 2025 11:49:48 +0200 Subject: [PATCH 398/931] arm64: dts: apple: Add devicetreee for t8112-j415 The 15-inch M2 MacBook Air was released a year after the 13-inch one thus missed in initial submission of devicetrees for M2 based devices. It is currently a copy of t8112-j413 with edited identifiers but will eventually differ in a meaningful way. It has for example a different speaker configuration than the 13-inch model. Reviewed-by: Neal Gompa Reviewed-by: Sven Peter Signed-off-by: Janne Grunau Link: https://lore.kernel.org/r/20250823-apple-dt-sync-6-17-v2-5-6dc0daeb4786@jannau.net Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/Makefile | 1 + arch/arm64/boot/dts/apple/t8112-j415.dts | 80 ++++++++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t8112-j415.dts diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index 4f337bff36cd..df4ba8ef6213 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -80,5 +80,6 @@ dtb-$(CONFIG_ARCH_APPLE) += t6001-j316c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6001-j375c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6002-j375d.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j413.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8112-j415.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j473.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j493.dtb diff --git a/arch/arm64/boot/dts/apple/t8112-j415.dts b/arch/arm64/boot/dts/apple/t8112-j415.dts new file mode 100644 index 000000000000..b54e218e5384 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8112-j415.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple MacBook Air (15-inch, M2, 2023) + * + * target-type: J415 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8112.dtsi" +#include "t8112-jxxx.dtsi" +#include + +/ { + compatible = "apple,j415", "apple,t8112", "apple,arm-platform"; + model = "Apple MacBook Air (15-inch, M2, 2023)"; + + aliases { + bluetooth0 = &bluetooth0; + wifi0 = &wifi0; + }; + + led-controller { + compatible = "pwm-leds"; + led-0 { + pwms = <&fpwm1 0 40000>; + label = "kbd_backlight"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + max-brightness = <255>; + default-state = "keep"; + }; + }; +}; + +/* + * Force the bus number assignments so that we can declare some of the + * on-board devices and properties that are populated by the bootloader + * (such as MAC addresses). + */ +&port00 { + bus-range = <1 1>; + wifi0: wifi@0,0 { + compatible = "pci14e4,4433"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 10 18 00 00 10]; + apple,antenna-sku = "XX"; + brcm,board-type = "apple,snake"; + }; + + bluetooth0: bluetooth@0,1 { + compatible = "pci14e4,5f71"; + reg = <0x10100 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-bd-address = [00 00 00 00 00 00]; + brcm,board-type = "apple,snake"; + }; +}; + +&i2c0 { + /* MagSafe port */ + hpm5: usb-pd@3a { + compatible = "apple,cd321x"; + reg = <0x3a>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&fpwm1 { + status = "okay"; +}; From d407ad36dd3451220f318af28e4f5813943ad4ce Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 12 Aug 2025 12:41:55 +0200 Subject: [PATCH 399/931] Documentation/process: maintainer-soc: Use "DTS" instead of "devicetree" Devicetree is a data structure and it is a bit generic term, because some treat Devicetree bindings as Devicetree. What the SoC maintainers profile is mentioning in ABI stability are the Devicetree sources, so DTS files. It is also more common during reviews to refer to these as per "DTS" instead "devicetree". Clarify that by using "DTS" name in few more places. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20250812104154.42289-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann --- Documentation/process/maintainer-soc.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/process/maintainer-soc.rst b/Documentation/process/maintainer-soc.rst index fe9d8bcfbd2b..3ba886f52a51 100644 --- a/Documentation/process/maintainer-soc.rst +++ b/Documentation/process/maintainer-soc.rst @@ -10,7 +10,7 @@ Overview The SoC subsystem is a place of aggregation for SoC-specific code. The main components of the subsystem are: -* devicetrees for 32- & 64-bit ARM and RISC-V +* devicetrees (DTS) for 32- & 64-bit ARM and RISC-V * 32-bit ARM board files (arch/arm/mach*) * 32- & 64-bit ARM defconfigs * SoC-specific drivers across architectures, in particular for 32- & 64-bit @@ -97,8 +97,8 @@ Perhaps one of the most important things to highlight is that dt-bindings document the ABI between the devicetree and the kernel. Please read Documentation/devicetree/bindings/ABI.rst. -If changes are being made to a devicetree that are incompatible with old -kernels, the devicetree patch should not be applied until the driver is, or an +If changes are being made to a DTS that are incompatible with old +kernels, the DTS patch should not be applied until the driver is, or an appropriate time later. Most importantly, any incompatible changes should be clearly pointed out in the patch description and pull request, along with the expected impact on existing users, such as bootloaders or other operating From 7d75eda45690ce17a2935174a7ed370dfeeb48ef Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:04:11 +0200 Subject: [PATCH 400/931] ARM: dts: qcom: ipq4019: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: qcom-ipq4019.dtsi:431.4-434.30: Warning (interrupt_map): /soc/pcie@40000000:interrupt-map: Missing property '#address-cells' in node /soc/interrupt-controller@b000000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-11-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index f77542fb3d4f..5bf5027e1ad9 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -175,6 +175,7 @@ soc { intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; From 1e54cf1f383adde02e49ccc9bb0cb9d3b0662a1e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:04:12 +0200 Subject: [PATCH 401/931] ARM: dts: qcom: apq8064: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: qcom-apq8064.dtsi:1353.4-1356.29: Warning (interrupt_map): /soc/pcie@1b500000:interrupt-map: Missing property '#address-cells' in node /soc/interrupt-controller@2000000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-12-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 17e506ca2438..4c9743423ea8 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -342,6 +342,7 @@ sfpb_mutex: hwmutex@1200600 { intc: interrupt-controller@2000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; reg = <0x02000000 0x1000>, <0x02002000 0x1000>; From 014a53ed24e33cc2cab112ad17df60d15ec97997 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:04:13 +0200 Subject: [PATCH 402/931] ARM: dts: qcom: ipq8064: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: qcom-ipq8064.dtsi:1201.4-1204.29: Warning (interrupt_map): /soc/pcie@1b900000:interrupt-map: Missing property '#address-cells' in node /soc/interrupt-controller@2000000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-13-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 96e973501535..03299078fc5a 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -527,6 +527,7 @@ sfpb_mutex: hwlock@1200600 { intc: interrupt-controller@2000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; reg = <0x02000000 0x1000>, <0x02002000 0x1000>; From 27cc4d100495faa0fa7272ef8fb9fc3e3abc4349 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:04:14 +0200 Subject: [PATCH 403/931] ARM: dts: qcom: sdx55: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: qcom-sdx55.dtsi:343.4-346.30: Warning (interrupt_map): /soc/pcie@1c00000:interrupt-map: Missing property '#address-cells' in node /soc/interrupt-controller@17800000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-14-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 20fdae9825e0..8d0aabfa1ee0 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -707,6 +707,7 @@ intc: interrupt-controller@17800000 { compatible = "qcom,msm-qgic2"; interrupt-controller; interrupt-parent = <&intc>; + #address-cells = <0>; #interrupt-cells = <3>; reg = <0x17800000 0x1000>, <0x17802000 0x1000>; From ba1045c76be299896528ac48021501fc9de78512 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 14:04:15 +0200 Subject: [PATCH 404/931] ARM: dts: qcom: Use GIC_SPI for interrupt-map for readability Decoding interrupt-map is tricky, because it consists of five components. Use known GIC_SPI define in final interrupt specifier component makes easier to read. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822-dts-interrupt-address-cells-v1-15-d54d44b74460@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 8 ++++---- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 8 ++++---- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 8 ++++---- 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 4c9743423ea8..09062b2ad8ba 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -1351,10 +1351,10 @@ pcie: pcie@1b500000 { interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc PCIE_A_CLK>, <&gcc PCIE_H_CLK>, <&gcc PCIE_PHY_REF_CLK>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 5bf5027e1ad9..8eeaab1c0be1 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -429,10 +429,10 @@ pcie0: pcie@40000000 { interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_AHB_CLK>, <&gcc GCC_PCIE_AXI_M_CLK>, <&gcc GCC_PCIE_AXI_S_CLK>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 03299078fc5a..adedcc6da1da 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -1077,10 +1077,10 @@ pcie0: pcie@1b500000 { interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc PCIE_A_CLK>, <&gcc PCIE_H_CLK>, @@ -1138,10 +1138,10 @@ pcie1: pcie@1b700000 { interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc PCIE_1_A_CLK>, <&gcc PCIE_1_H_CLK>, @@ -1199,10 +1199,10 @@ pcie2: pcie@1b900000 { interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc PCIE_2_A_CLK>, <&gcc PCIE_2_H_CLK>, diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 8d0aabfa1ee0..05b79281df57 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -340,10 +340,10 @@ pcie_rc: pcie@1c00000 { "msi8"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc GCC_PCIE_PIPE_CLK>, <&gcc GCC_PCIE_AUX_CLK>, From 235399565582d092ff8fb5757eee63b1367ea6b9 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Fri, 22 Aug 2025 11:26:33 +0200 Subject: [PATCH 405/931] arm64: dts: qcom: sm8450: Additionally manage MXC power domain in videocc Videocc requires both MMCX and MXC rails to be powered ON to configure the video PLLs on SM8450 platform. Hence add MXC power domain to videocc node on SM8450. Reviewed-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Jagadeesh Kona Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-1-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index b31c09ec61a9..7c10a500c35c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3199,8 +3199,10 @@ videocc: clock-controller@aaf0000 { reg = <0 0x0aaf0000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From d49e683574537d416aa0fb022d800430e7c045b6 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Fri, 22 Aug 2025 11:26:34 +0200 Subject: [PATCH 406/931] arm64: dts: qcom: sm8550: Additionally manage MXC power domain in videocc Videocc requires both MMCX and MXC rails to be powered ON to configure the video PLLs on SM8550 platform. Hence add MXC power domain to videocc node on SM8550. Reviewed-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Jagadeesh Kona Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-2-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ee5970974255..3c6f52499465 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3307,8 +3307,10 @@ videocc: clock-controller@aaf0000 { reg = <0 0x0aaf0000 0 0x10000>; clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From 086079090571910ead0510e756cea14ff3759d4e Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Fri, 22 Aug 2025 11:26:35 +0200 Subject: [PATCH 407/931] arm64: dts: qcom: sm8650: Additionally manage MXC power domain in videocc Videocc requires both MMCX and MXC rails to be powered ON to configure the video PLLs on SM8650 platform. Hence add MXC power domain to videocc node on SM8650. Reviewed-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Jagadeesh Kona Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-3-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 7ffdd26ff614..e3eabd5d17f8 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5236,7 +5236,8 @@ videocc: clock-controller@aaf0000 { reg = <0 0x0aaf0000 0 0x10000>; clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd RPMHPD_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From ad43a5317a8bda7fd9d6ad5f0b6248ba11900b44 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Fri, 22 Aug 2025 11:26:36 +0200 Subject: [PATCH 408/931] arm64: dts: qcom: sm8450: Additionally manage MXC power domain in camcc Camcc requires both MMCX and MXC rails to be powered ON to configure the camera PLLs on SM8450 platform. Hence add MXC power domain to camcc node on SM8450. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Signed-off-by: Jagadeesh Kona Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-4-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 7c10a500c35c..dc539318662d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3293,8 +3293,10 @@ camcc: clock-controller@ade0000 { <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From 169ccd7cec9b702778ffb58a436f757db23154f2 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 22 Aug 2025 11:26:37 +0200 Subject: [PATCH 409/931] arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc Camcc requires both MMCX and MXC rails to be powered ON to configure the camera PLLs on SM8550 platform. Hence add MXC power domain to camcc node on SM8550. Fixes: e271b59e39a6f ("arm64: dts: qcom: sm8550: Add camera clock controller") Reviewed-by: Taniya Das Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Signed-off-by: Vladimir Zapolskiy Signed-off-by: Jagadeesh Kona Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-5-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 3c6f52499465..04bd12169971 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3625,8 +3625,10 @@ camcc: clock-controller@ade0000 { <&bi_tcxo_div2>, <&bi_tcxo_ao_div2>, <&sleep_clk>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From 673fa9a42606a755068e7ab6ab92cf61db243149 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Fri, 22 Aug 2025 11:26:38 +0200 Subject: [PATCH 410/931] arm64: dts: qcom: sm8650: Additionally manage MXC power domain in camcc Camcc requires both MMCX and MXC rails to be powered ON to configure the camera PLLs on SM8650 platform. Hence add MXC power domain to camcc node on SM8650. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Bryan O'Donoghue Signed-off-by: Jagadeesh Kona Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-6-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index e3eabd5d17f8..7fc2d737306d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5349,7 +5349,8 @@ camcc: clock-controller@ade0000 { <&bi_tcxo_div2>, <&bi_tcxo_ao_div2>, <&sleep_clk>; - power-domains = <&rpmhpd RPMHPD_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From 38c0af1f3fe437ac2f7a5ddce4f35e0fb8a49aea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Sat, 30 Aug 2025 17:57:29 +0200 Subject: [PATCH 411/931] arm64: dts: qcom: sdm845-shift-axolotl: set chassis type MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's a handset. Signed-off-by: Guido Günther Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/3e04efc06a795a32b0080b2f23a138e139057b02.1756569434.git.agx@sigxcpu.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 87e913343cbb..89260fce6513 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -18,6 +18,7 @@ / { model = "SHIFT SHIFT6mq"; compatible = "shift,axolotl", "qcom,sdm845"; + chassis-type = "handset"; qcom,msm-id = ; qcom,board-id = <11 0>; From 4faee358fea854fddba95843c55d9eb9013a4f00 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Barnab=C3=A1s=20Cz=C3=A9m=C3=A1n?= Date: Sat, 30 Aug 2025 23:13:19 +0200 Subject: [PATCH 412/931] arm64: dts: qcom: msm8953: fix SPI clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix SPI clocks, accidentally I2C clocks was assigned for SPI interfaces. Fixes: be69109e93c78 ("arm64: dts: qcom: msm8953: add SPI interfaces") Signed-off-by: Barnabás Czémán Link: https://lore.kernel.org/r/20250830-msm8953-spi-fix-v1-1-89950eaf10fe@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index c5205d09c442..14dd17278ae0 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -1660,7 +1660,7 @@ spi_3: spi@78b7000 { reg = <0x078b7000 0x600>; interrupts = ; clock-names = "core", "iface"; - clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; dma-names = "tx", "rx"; @@ -1751,7 +1751,7 @@ spi_5: spi@7af5000 { reg = <0x07af5000 0x600>; interrupts = ; clock-names = "core", "iface"; - clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; dma-names = "tx", "rx"; @@ -1791,7 +1791,7 @@ spi_6: spi@7af6000 { reg = <0x07af6000 0x600>; interrupts = ; clock-names = "core", "iface"; - clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, + clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; dma-names = "tx", "rx"; From 690bc19286407cf1c0fc189910a936261ae1344c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Barnab=C3=A1s=20Cz=C3=A9m=C3=A1n?= Date: Sat, 30 Aug 2025 23:13:20 +0200 Subject: [PATCH 413/931] arm64: dts: qcom: msm8953: correct SPI pinctrls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SPI pinctrls should handle 4 pins MOSI, MISO, CLK and CS. This change adding the missing pins for pinctrls and correcting CS pins according to downstream sources. Fixes: be69109e93c78 ("arm64: dts: qcom: msm8953: add SPI interfaces") Signed-off-by: Barnabás Czémán Link: https://lore.kernel.org/r/20250830-msm8953-spi-fix-v1-2-89950eaf10fe@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 102 ++++++++++++++++++++------ 1 file changed, 78 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 14dd17278ae0..1b3e68aed945 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -775,45 +775,99 @@ i2c_8_sleep: i2c-8-sleep-state { }; spi_3_default: spi-3-default-state { - pins = "gpio10", "gpio11"; - function = "blsp_spi3"; - drive-strength = <2>; - bias-disable; + cs-pins { + pins = "gpio10"; + function = "blsp_spi3"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + drive-strength = <12>; + bias-disable; + }; }; spi_3_sleep: spi-3-sleep-state { - pins = "gpio10", "gpio11"; - function = "gpio"; - drive-strength = <2>; - bias-disable; + cs-pins { + pins = "gpio10"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; }; spi_5_default: spi-5-default-state { - pins = "gpio18", "gpio19"; - function = "blsp_spi5"; - drive-strength = <2>; - bias-disable; + cs-pins { + pins = "gpio18"; + function = "blsp_spi5"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "blsp_spi5"; + drive-strength = <12>; + bias-disable; + }; }; spi_5_sleep: spi-5-sleep-state { - pins = "gpio18", "gpio19"; - function = "gpio"; - drive-strength = <2>; - bias-disable; + cs-pins { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; }; spi_6_default: spi-6-default-state { - pins = "gpio22", "gpio23"; - function = "blsp_spi6"; - drive-strength = <2>; - bias-disable; + cs-pins { + pins = "gpio22"; + function = "blsp_spi6"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + drive-strength = <12>; + bias-disable; + }; }; spi_6_sleep: spi-6-sleep-state { - pins = "gpio22", "gpio23"; - function = "gpio"; - drive-strength = <2>; - bias-disable; + cs-pins { + pins = "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; }; uart_5_default: uart-5-default-state { From 73f7dc09f8e363736a3d3509820666e2006ab277 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Barnab=C3=A1s=20Cz=C3=A9m=C3=A1n?= Date: Sat, 30 Aug 2025 23:13:21 +0200 Subject: [PATCH 414/931] arm64: dts: qcom: msm8953: add spi_7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add spi_7 can be found in MSM8953 devices. Signed-off-by: Barnabás Czémán Link: https://lore.kernel.org/r/20250830-msm8953-spi-fix-v1-3-89950eaf10fe@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 52 +++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 1b3e68aed945..76317c578349 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -870,6 +870,38 @@ spi-pins { }; }; + spi_7_default: spi-7-default-state { + cs-pins { + pins = "gpio136"; + function = "blsp_spi7"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio135", "gpio137", "gpio138"; + function = "blsp_spi7"; + drive-strength = <12>; + bias-disable; + }; + }; + + spi_7_sleep: spi-7-sleep-state { + cs-pins { + pins = "gpio136"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio135", "gpio137", "gpio138"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + uart_5_default: uart-5-default-state { pins = "gpio16", "gpio17", "gpio18", "gpio19"; function = "blsp_uart5"; @@ -1880,6 +1912,26 @@ i2c_7: i2c@7af7000 { status = "disabled"; }; + spi_7: spi@7af7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07af7000 0x600>; + interrupts = ; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; + dma-names = "tx", "rx"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi_7_default>; + pinctrl-1 = <&spi_7_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + i2c_8: i2c@7af8000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07af8000 0x600>; From 6e71c5812856d67881572159098f701184c9356a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20Gon=C3=A7alves?= Date: Thu, 28 Aug 2025 20:49:28 +0000 Subject: [PATCH 415/931] arm64: dts: qcom: starqltechn: remove extra empty line MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove empty white line ine starqltechn device tree at the end of max77705_charger node. Signed-off-by: Eric Gonçalves Link: https://lore.kernel.org/r/20250828204929.35402-1-ghatto404@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 03b63b987a18..9eeb4b807465 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -633,7 +633,6 @@ max77705_charger: charger@69 { monitored-battery = <&battery>; interrupt-parent = <&pm8998_gpios>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - }; fuel-gauge@36 { From 6605a07f441cf1e056ec8ea6e553c893151d5527 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Apitzsch?= Date: Thu, 28 Aug 2025 22:25:50 +0200 Subject: [PATCH 416/931] arm64: dts: qcom: msm8976-longcheer-l9360: Add touch keys MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The phone has three capacitive buttons on the screen bezel. Enable them by adding the keycodes in the dt. Signed-off-by: André Apitzsch Link: https://lore.kernel.org/r/20250828-l9360_touch_keys-v1-1-1ce5a279c399@apitzsch.eu Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts b/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts index e524d58cf0a4..18832a3b9a1c 100644 --- a/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts +++ b/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts @@ -190,6 +190,12 @@ rmi4-f12@12 { reg = <0x12>; syna,sensor-type = <1>; }; + + rmi4-f1a@1a { + reg = <0x1a>; + /* Keys listed from right to left */ + linux,keycodes = ; + }; }; }; From 19f1395333f80479a3a5fce29e4c7a8255322a9c Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Tue, 26 Aug 2025 16:32:54 +0530 Subject: [PATCH 417/931] arm64: dts: qcom: sm8750: Add PCIe PHY and controller node Add PCIe controller and PHY nodes which supports data rates of 8GT/s and x2 lane. Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/r/20250826-pakala-v3-2-721627bd5bb0@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 180 ++++++++++++++++++++++++++- 1 file changed, 179 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 79ca262f5811..a82d9867c7cb 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -631,7 +631,7 @@ gcc: clock-controller@100000 { clocks = <&bi_tcxo_div2>, <0>, <&sleep_clk>, - <0>, + <&pcie0_phy>, <0>, <0>, <0>, @@ -3304,6 +3304,184 @@ gic_its: msi-controller@16040000 { }; }; + pcie0: pcie@1c00000 { + device_type = "pci"; + compatible = "qcom,pcie-sm8750", "qcom,pcie-sm8550"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01C03000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>, + <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x00000000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <0>; + + msi-map = <0x0 &gic_its 0x1400 0x1>, + <0x100 &gic_its 0x1401 0x1>; + msi-map-mask = <0xff00>; + + num-lanes = <2>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr", + "cnoc_sf_axi"; + + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc GCC_PCIE_0_GDSC>; + + operating-points-v2 = <&pcie0_opp_table>; + + status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + + }; + + pcieport0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + phys = <&pcie0_phy>; + }; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c06000 0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&tcsrcc TCSR_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + ufs_mem_phy: phy@1d80000 { compatible = "qcom,sm8750-qmp-ufs-phy"; reg = <0x0 0x01d80000 0x0 0x2000>; From 99d741245e7a6d8b533511f96fc110a7d89aee1b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 22 Aug 2025 17:56:49 +0200 Subject: [PATCH 418/931] arm64: dts: qcom: sm8550: allow mode-switch events to reach the QMP Combo PHY Allow mode-switch events to reach the QMP Combo PHY to support setting the QMP Combo PHY in DP 4Lanes Altmode. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-topic-x1e80100-4lanes-v3-1-5363acad9e32@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 04bd12169971..276faa5db0f1 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -4055,6 +4055,7 @@ usb_dp_qmpphy: phy@88e8000 { #clock-cells = <1>; #phy-cells = <1>; + mode-switch; orientation-switch; status = "disabled"; From 6cc36611ac7925a6a6bc64c625b85f80d36fa1a6 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 22 Aug 2025 17:56:50 +0200 Subject: [PATCH 419/931] arm64: dts: qcom: sm8650: allow mode-switch events to reach the QMP Combo PHY Allow mode-switch events to reach the QMP Combo PHY to support setting the QMP Combo PHY in DP 4Lanes Altmode. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-topic-x1e80100-4lanes-v3-2-5363acad9e32@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 7fc2d737306d..944b02098dd4 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5012,6 +5012,7 @@ usb_dp_qmpphy: phy@88e8000 { #clock-cells = <1>; #phy-cells = <1>; + mode-switch; orientation-switch; status = "disabled"; From 7b8849178ecf183880dbdf19d853c92d0877a280 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 22 Aug 2025 17:56:51 +0200 Subject: [PATCH 420/931] arm64: dts: qcom: x1e80100: allow mode-switch events to reach the QMP Combo PHYs Allow mode-switch events to reach the QMP Combo PHYs to support setting the QMP Combo PHY in DP 4Lanes Altmode. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-topic-x1e80100-4lanes-v3-3-5363acad9e32@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index e61c9010a3f2..c9e96f615711 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2857,6 +2857,7 @@ usb_1_ss0_qmpphy: phy@fd5000 { #clock-cells = <1>; #phy-cells = <1>; + mode-switch; orientation-switch; status = "disabled"; @@ -2927,6 +2928,7 @@ usb_1_ss1_qmpphy: phy@fda000 { #clock-cells = <1>; #phy-cells = <1>; + mode-switch; orientation-switch; status = "disabled"; @@ -2997,6 +2999,7 @@ usb_1_ss2_qmpphy: phy@fdf000 { #clock-cells = <1>; #phy-cells = <1>; + mode-switch; orientation-switch; status = "disabled"; From bdd235f2df6d5d6cf00cdf474970b1e6d177f2bd Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 22 Aug 2025 17:56:52 +0200 Subject: [PATCH 421/931] arm64: dts: qcom: sm8550: move dp0 data-lanes to SoC dtsi The connection between the QMP Combo PHY and the DisplayPort controller is fixed in SoC, so move the data-lanes property in the SoC dtsi. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-topic-x1e80100-4lanes-v3-4-5363acad9e32@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 + 4 files changed, 1 insertion(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 162afaffa48b..b5d7f0cd443a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1002,10 +1002,6 @@ &mdss_dp0 { status = "okay"; }; -&mdss_dp0_out { - data-lanes = <0 1>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index f5aa349f3194..38f2928f23cc 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -738,10 +738,6 @@ &mdss_dp0 { status = "okay"; }; -&mdss_dp0_out { - data-lanes = <0 1>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index c079c02550b8..a3f4200a1145 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -857,10 +857,6 @@ &mdss_dp0 { status = "okay"; }; -&mdss_dp0_out { - data-lanes = <0 1>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 276faa5db0f1..032640aa9eb5 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3795,6 +3795,7 @@ mdss_dp0_in: endpoint { port@1 { reg = <1>; mdss_dp0_out: endpoint { + data-lanes = <0 1>; remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; }; From 35f549fcf5f1d99997cd865170fd7cb1bb66c1d7 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 22 Aug 2025 17:56:53 +0200 Subject: [PATCH 422/931] arm64: dts: qcom: sm8650: move dp0 data-lanes to SoC dtsi The connection between the QMP Combo PHY and the DisplayPort controller is fixed in SoC, so move the data-lanes property in the SoC dtsi. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-topic-x1e80100-4lanes-v3-5-5363acad9e32@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650.dtsi | 1 + 3 files changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index a00da76a6062..d4e5c95e9339 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -941,10 +941,6 @@ &mdss_dp0 { status = "okay"; }; -&mdss_dp0_out { - data-lanes = <0 1>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 081b7e40f574..d71031cb26e2 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -892,10 +892,6 @@ &mdss_dp0 { status = "okay"; }; -&mdss_dp0_out { - data-lanes = <0 1>; -}; - &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 944b02098dd4..994fd241948d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5723,6 +5723,7 @@ port@1 { reg = <1>; mdss_dp0_out: endpoint { + data-lanes = <0 1>; remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; }; From 458de584248a5630878ed11ea23188f6007036b2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 22 Aug 2025 17:56:54 +0200 Subject: [PATCH 423/931] arm64: dts: qcom: x1e80100: move dp0/1/2 data-lanes to SoC dtsi The connection between the QMP Combo PHY and the DisplayPort controller is fixed in SoC, so move the data-lanes properties in the SoC dtsi. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-topic-x1e80100-4lanes-v3-6-5363acad9e32@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi | 2 -- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 3 --- arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 3 --- arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 2 -- arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts | 2 -- arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts | 2 -- arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 3 --- arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi | 2 -- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 3 --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 3 +++ 10 files changed, 3 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi index 16d045cf64c0..beb484e36b04 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi @@ -985,7 +985,6 @@ &mdss_dp0 { }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -994,7 +993,6 @@ &mdss_dp1 { }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index e3d2fc342bd1..47dd99ecf026 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1149,7 +1149,6 @@ &mdss_dp0 { }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -1158,7 +1157,6 @@ &mdss_dp1 { }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -1167,7 +1165,6 @@ &mdss_dp2 { }; &mdss_dp2_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index a3323d03f644..bfc649d4b643 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -983,7 +983,6 @@ &mdss_dp0 { }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -992,7 +991,6 @@ &mdss_dp1 { }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -1001,7 +999,6 @@ &mdss_dp2 { }; &mdss_dp2_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index e04df29a8853..81e42d42b3f7 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -994,7 +994,6 @@ &mdss_dp0 { }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -1003,7 +1002,6 @@ &mdss_dp1 { }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index 6b27067f0be6..6f646b23305e 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -884,7 +884,6 @@ &mdss_dp0 { }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -893,7 +892,6 @@ &mdss_dp1 { }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts index f9ce2a63767c..ce1885e4c563 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts @@ -1028,7 +1028,6 @@ &mdss_dp0 { }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -1037,7 +1036,6 @@ &mdss_dp1 { }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index 71becfc5e6f6..c03dbded1624 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -1061,7 +1061,6 @@ &mdss_dp0 { }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -1070,7 +1069,6 @@ &mdss_dp1 { }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -1079,7 +1077,6 @@ &mdss_dp2 { }; &mdss_dp2_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 27dd5e4e9939..eeef0cb2606a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -949,7 +949,6 @@ &mdss_dp0 { }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -958,7 +957,6 @@ &mdss_dp1 { }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index b02a66f0895e..cac22e50e266 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -890,7 +890,6 @@ &mdss_dp0 { }; &mdss_dp0_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -899,7 +898,6 @@ &mdss_dp1 { }; &mdss_dp1_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; @@ -908,7 +906,6 @@ &mdss_dp2 { }; &mdss_dp2_out { - data-lanes = <0 1>; link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index c9e96f615711..951703a60c64 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5380,6 +5380,7 @@ port@1 { reg = <1>; mdss_dp0_out: endpoint { + data-lanes = <0 1>; remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; }; }; @@ -5463,6 +5464,7 @@ port@1 { reg = <1>; mdss_dp1_out: endpoint { + data-lanes = <0 1>; remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; }; }; @@ -5545,6 +5547,7 @@ port@1 { reg = <1>; mdss_dp2_out: endpoint { + data-lanes = <0 1>; remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; }; }; From b942e087564b0c1b0bf1c31c1058a59dfd5df841 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 22 Aug 2025 17:56:55 +0200 Subject: [PATCH 424/931] arm64: dts: qcom: sm8550: Set up 4-lane DP Allow up to 4 lanes for the DisplayPort link from the PHY to the controller now the mode-switch events can reach the QMP Combo PHY. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-topic-x1e80100-4lanes-v3-7-5363acad9e32@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 032640aa9eb5..2df6ba05e0cd 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3795,7 +3795,7 @@ mdss_dp0_in: endpoint { port@1 { reg = <1>; mdss_dp0_out: endpoint { - data-lanes = <0 1>; + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; }; From 630c05a1dd350822e9166857ab120c0a7269b57a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 22 Aug 2025 17:56:56 +0200 Subject: [PATCH 425/931] arm64: dts: qcom: sm8650: Set up 4-lane DP Allow up to 4 lanes for the DisplayPort link from the PHY to the controller now the mode-switch events can reach the QMP Combo PHY. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-topic-x1e80100-4lanes-v3-8-5363acad9e32@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 994fd241948d..367f448a743a 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5723,7 +5723,7 @@ port@1 { reg = <1>; mdss_dp0_out: endpoint { - data-lanes = <0 1>; + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; }; From 2e66c88bb2649133da470d2685646f6536d1e0d5 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 22 Aug 2025 17:56:57 +0200 Subject: [PATCH 426/931] arm64: dts: qcom: x1e80100: Set up 4-lane DP Allow up to 4 lanes for the DisplayPort link from the PHYs to the controllers now the mode-switch events can reach the QMP Combo PHYs. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-topic-x1e80100-4lanes-v3-9-5363acad9e32@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 951703a60c64..b017f47e832f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5380,7 +5380,7 @@ port@1 { reg = <1>; mdss_dp0_out: endpoint { - data-lanes = <0 1>; + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; }; }; @@ -5464,7 +5464,7 @@ port@1 { reg = <1>; mdss_dp1_out: endpoint { - data-lanes = <0 1>; + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; }; }; @@ -5547,7 +5547,7 @@ port@1 { reg = <1>; mdss_dp2_out: endpoint { - data-lanes = <0 1>; + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; }; }; From 6dfa62182c3b2b31b3da5e7e5b87c294dc3ddb5c Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 22 Aug 2025 11:28:52 +0200 Subject: [PATCH 427/931] arm64: dts: qcom: x1e80100: Add pinctrl template for eDP0 HPD At the moment, we indirectly rely on the boot firmware to set up the pinctrl for the eDP HPD line coming from the internal display. If the boot firmware does not configure the display (e.g. because a different display is selected for output in the UEFI settings), then the display fails to come up and there are several errors in the kernel log: [drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041 [drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110 [drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout ... Add a new &edp0_hpd_default pinctrl template that can be used by boards to set up the eDP HPD pin correctly. All boards upstream so far need the same configuration; if a board needs a different configuration it can just avoid using this template and define a custom one in the board DT. Signed-off-by: Stephan Gerhold Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-1-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index b017f47e832f..737c5dbd1c80 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5814,6 +5814,12 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 239>; wakeup-parent = <&pdc>; + edp0_hpd_default: edp0-hpd-default-state { + pins = "gpio119"; + function = "edp0_hot"; + bias-disable; + }; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { /* SDA, SCL */ pins = "gpio0", "gpio1"; From 35fab4bedcf1fb4a7b2e2f6a5e35b43e9447ad70 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 22 Aug 2025 11:28:53 +0200 Subject: [PATCH 428/931] arm64: dts: qcom: x1-asus-zenbook-a14: Add missing pinctrl for eDP HPD At the moment, we indirectly rely on the boot firmware to set up the pinctrl for the eDP HPD line coming from the internal display. If the boot firmware does not configure the display (e.g. because a different display is selected for output in the UEFI settings), then the display fails to come up and there are several errors in the kernel log: [drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041 [drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110 [drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout ... Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and bias-disable according to the ACPI DSDT), which is defined as &edp0_hpd_default template in x1e80100.dtsi. Fixes: 6516961352a1 ("arm64: dts: qcom: Add support for X1-based Asus Zenbook A14") Tested-by: Aleksandrs Vinarskis # FHD OLED Reviewed-by: Aleksandrs Vinarskis Signed-off-by: Stephan Gerhold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-2-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi index beb484e36b04..ee3c8c5e2c50 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi @@ -999,6 +999,9 @@ &mdss_dp1_out { &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { From 540020f93b22219690d591fcfd5081ab3d34ad66 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 22 Aug 2025 11:28:54 +0200 Subject: [PATCH 429/931] arm64: dts: qcom: x1-crd: Add missing pinctrl for eDP HPD At the moment, we indirectly rely on the boot firmware to set up the pinctrl for the eDP HPD line coming from the internal display. If the boot firmware does not configure the display (e.g. because a different display is selected for output in the UEFI settings), then the display fails to come up and there are several errors in the kernel log: [drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041 [drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110 [drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout ... Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and bias-disable according to the ACPI DSDT), which is defined as &edp0_hpd_default template in x1e80100.dtsi. Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support") Signed-off-by: Stephan Gerhold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-3-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 47dd99ecf026..3c9455fede5c 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1171,6 +1171,9 @@ &mdss_dp2_out { &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { From d1126668533eedebd6130515c7626af1ef808abb Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 22 Aug 2025 11:28:55 +0200 Subject: [PATCH 430/931] arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: Add missing pinctrl for eDP HPD At the moment, we indirectly rely on the boot firmware to set up the pinctrl for the eDP HPD line coming from the internal display. If the boot firmware does not configure the display (e.g. because a different display is selected for output in the UEFI settings), then the display fails to come up and there are several errors in the kernel log: [drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041 [drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110 [drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout ... Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and bias-disable according to the ACPI DSDT), which is defined as &edp0_hpd_default template in x1e80100.dtsi. Fixes: 7d1cbe2f4985 ("arm64: dts: qcom: Add X1E78100 ThinkPad T14s Gen 6") Tested-by: Christopher Obbard Reviewed-by: Christopher Obbard Signed-off-by: Stephan Gerhold Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong # on Lenovo Thinkpad T14s OLED Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-4-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 81e42d42b3f7..23213b0d9582 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -1008,6 +1008,9 @@ &mdss_dp1_out { &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { From c95c1ba079f604c504feb8cf7bb038341e2d7805 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 22 Aug 2025 11:28:56 +0200 Subject: [PATCH 431/931] arm64: dts: qcom: x1e80100-asus-vivobook-s15: Add missing pinctrl for eDP HPD At the moment, we indirectly rely on the boot firmware to set up the pinctrl for the eDP HPD line coming from the internal display. If the boot firmware does not configure the display (e.g. because a different display is selected for output in the UEFI settings), then the display fails to come up and there are several errors in the kernel log: [drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041 [drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110 [drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout ... Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and bias-disable according to the ACPI DSDT), which is defined as &edp0_hpd_default template in x1e80100.dtsi. Fixes: d0e2f8f62dff ("arm64: dts: qcom: Add device tree for ASUS Vivobook S 15") Tested-by: Maud Spierings Signed-off-by: Stephan Gerhold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-5-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index b571e8349d3b..0113d856b3ad 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -593,6 +593,9 @@ &mdss { &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { From a41d23142d8773614cb2745d7b224e5784cc71ab Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 22 Aug 2025 11:28:57 +0200 Subject: [PATCH 432/931] arm64: dts: qcom: x1e80100-dell-xps13-9345: Add missing pinctrl for eDP HPD At the moment, we indirectly rely on the boot firmware to set up the pinctrl for the eDP HPD line coming from the internal display. If the boot firmware does not configure the display (e.g. because a different display is selected for output in the UEFI settings), then the display fails to come up and there are several errors in the kernel log: [drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041 [drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110 [drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout ... Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and bias-disable according to the ACPI DSDT), which is defined as &edp0_hpd_default template in x1e80100.dtsi. Fixes: f5b788d0e8cd ("arm64: dts: qcom: Add support for X1-based Dell XPS 13 9345") Tested-by: Aleksandrs Vinarskis # 3K OLED Reviewed-by: Aleksandrs Vinarskis Signed-off-by: Stephan Gerhold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-6-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index 6f646b23305e..19a2604038a8 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -898,6 +898,9 @@ &mdss_dp1_out { &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { From 0e94604702eb9f141ef862b10757d67e3880235c Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 22 Aug 2025 11:28:58 +0200 Subject: [PATCH 433/931] arm64: dts: qcom: x1e80100-hp-omnibook-x14: Add missing pinctrl for eDP HPD At the moment, we indirectly rely on the boot firmware to set up the pinctrl for the eDP HPD line coming from the internal display. If the boot firmware does not configure the display (e.g. because a different display is selected for output in the UEFI settings), then the display fails to come up and there are several errors in the kernel log: [drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041 [drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110 [drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout ... Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and bias-disable according to the ACPI DSDT), which is defined as &edp0_hpd_default template in x1e80100.dtsi. Fixes: 6f18b8d4142c ("arm64: dts: qcom: x1e80100-hp-x14: dt for HP Omnibook X Laptop 14") Signed-off-by: Stephan Gerhold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-7-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts index ce1885e4c563..716205b437df 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts @@ -1042,6 +1042,9 @@ &mdss_dp1_out { &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { From f6470367bdb2cde247cd88864208db998fed03ac Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 22 Aug 2025 11:28:59 +0200 Subject: [PATCH 434/931] arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add missing pinctrl for eDP HPD At the moment, we indirectly rely on the boot firmware to set up the pinctrl for the eDP HPD line coming from the internal display. If the boot firmware does not configure the display (e.g. because a different display is selected for output in the UEFI settings), then the display fails to come up and there are several errors in the kernel log: [drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041 [drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110 [drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout ... Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and bias-disable according to the ACPI DSDT), which is defined as &edp0_hpd_default template in x1e80100.dtsi. Fixes: 45247fe17db2 ("arm64: dts: qcom: x1e80100: add Lenovo Thinkpad Yoga slim 7x devicetree") Signed-off-by: Stephan Gerhold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-8-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index c03dbded1624..dae616cd93bd 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -1083,6 +1083,9 @@ &mdss_dp2_out { &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { From 4b9165960bf2d25817de6f5fda3d2cd07f787927 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 22 Aug 2025 11:29:00 +0200 Subject: [PATCH 435/931] arm64: dts: qcom: x1e80100-microsoft-romulus: Add missing pinctrl for eDP HPD At the moment, we indirectly rely on the boot firmware to set up the pinctrl for the eDP HPD line coming from the internal display. If the boot firmware does not configure the display (e.g. because a different display is selected for output in the UEFI settings), then the display fails to come up and there are several errors in the kernel log: [drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041 [drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110 [drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout ... Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and bias-disable according to the ACPI DSDT), which is defined as &edp0_hpd_default template in x1e80100.dtsi. Fixes: 09d77be56093 ("arm64: dts: qcom: Add support for X1-based Surface Laptop 7 devices") Signed-off-by: Stephan Gerhold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-9-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index eeef0cb2606a..0ad4276e9c5f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -963,6 +963,9 @@ &mdss_dp1_out { &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { From 1616877626228a6ef05ddae4017c9b0f65803a8b Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Fri, 22 Aug 2025 11:29:01 +0200 Subject: [PATCH 436/931] arm64: dts: qcom: x1e80100-qcp: Add missing pinctrl for eDP HPD At the moment, we indirectly rely on the boot firmware to set up the pinctrl for the eDP HPD line coming from the internal display. If the boot firmware does not configure the display (e.g. because a different display is selected for output in the UEFI settings), then the display fails to come up and there are several errors in the kernel log: [drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041 [drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110 [drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout ... Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and bias-disable according to the ACPI DSDT), which is defined as &edp0_hpd_default template in x1e80100.dtsi. Fixes: f9a9c11471da ("arm64: dts: qcom: x1e80100-qcp: Enable more support") Signed-off-by: Stephan Gerhold Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-10-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index cac22e50e266..4a9b6d791e7f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -912,6 +912,9 @@ &mdss_dp2_out { &mdss_dp3 { /delete-property/ #sound-dai-cells; + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + status = "okay"; aux-bus { From 63727c59a917b6ffdb13d51c251727a3e21d38d9 Mon Sep 17 00:00:00 2001 From: Jens Glathe Date: Fri, 22 Aug 2025 08:44:10 +0200 Subject: [PATCH 437/931] dt-bindings: arm: qcom: Add Lenovo TB16 support Document the x1p-42-100/x1-26-100 variants of the Thinkbook 16 G7 QOY. [1]: https://psref.lenovo.com/syspool/Sys/PDF/ThinkBook/ThinkBook_16_G7_QOY/ThinkBook_16_G7_QOY_Spec.pdf Acked-by: Rob Herring (Arm) Signed-off-by: Jens Glathe Link: https://lore.kernel.org/r/20250822-tb16-dt-v12-1-bab6c2986351@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index fa929698229e..f0a6f6f7b839 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1066,6 +1066,7 @@ properties: - items: - enum: - asus,zenbook-a14-ux3407qa + - lenovo,thinkbook-16 - qcom,x1p42100-crd - const: qcom,x1p42100 From d3f600dc452df45f0f404eba65a88f4aecc48b43 Mon Sep 17 00:00:00 2001 From: Jens Glathe Date: Fri, 22 Aug 2025 08:44:12 +0200 Subject: [PATCH 438/931] arm64: dts: qcom: Add Lenovo ThinkBook 16 G7 QOY device tree Device tree for the Lenovo Thinkbook 16 G7 QOY The Laptop is a Snapdragon X1 / X1 Plus (Purwa) based device [1]. Supported features: - USB type-c and type-a ports - Keyboard - Touchpad (all that are described in the dsdt) - Touchscreen (described in the dsdt, no known SKUss) - Display including PWM backlight control - PCIe devices - nvme - SDHC card reader - ath12k WCN7850 Wifi and Bluetooth - ADSP and CDSP - GPIO keys (Lid switch) - Sound via internal speakers / DMIC / USB / headphone jack - DP Altmode with 2 lanes (as all of these still do) - Integrated fingerprint reader (FPC) - Integrated UVC camera - X1-45 GPU Not supported yet: - HDMI port. - EC and some fn hotkeys. Limited support yet: - SDHC card reader is based on the on-chip sdhc_2 controller, but the driver from the Snapdragon Dev Kit is only a partial match. It can do normal slow sd cards, but not UHS-I (SD104) and UHS-II. This work was done without any schematics or non-public knowledge of the device. So, it is based on the existing x1e device trees, dsdt analysis, using HWInfo ARM64, and pure guesswork. It has been confirmed, however, that the device really has 4 NXP PTN3222 eUSB2 repeaters, one of which doesn't have a reset GPIO (eusb5 @43). Co-developed-by: Aleksandrs Vinarskis Signed-off-by: Aleksandrs Vinarskis Signed-off-by: Jens Glathe Link: https://lore.kernel.org/r/20250822-tb16-dt-v12-3-bab6c2986351@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../dts/qcom/x1p42100-lenovo-thinkbook-16.dts | 1625 +++++++++++++++++ 2 files changed, 1627 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 94a84770b080..4d449eb87a20 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -331,3 +331,5 @@ x1p42100-asus-zenbook-a14-el2-dtbs := x1p42100-asus-zenbook-a14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-zenbook-a14.dtb x1p42100-asus-zenbook-a14-el2.dtb x1p42100-crd-el2-dtbs := x1p42100-crd.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-crd.dtb x1p42100-crd-el2.dtb +x1p42100-lenovo-thinkbook-16-el2-dtbs := x1p42100-lenovo-thinkbook-16.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-thinkbook-16.dtb x1p42100-lenovo-thinkbook-16-el2.dtb diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts new file mode 100644 index 000000000000..1ac46cdc4386 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -0,0 +1,1625 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Linaro Limited + * Copyright (c) 2025, Jens Glathe + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "x1p42100.dtsi" +#include "x1e80100-pmics.dtsi" + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "Lenovo ThinkBook 16 Gen 7 QOY"; + compatible = "lenovo,thinkbook-16", "qcom,x1p42100"; + chassis-type = "laptop"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pm8550_pwm 3 500000>; + + power-supply = <&vreg_edp_bl>; + }; + + /* + * This is an odd one. The camera is physically behind the eusb9 repeater (confirmed) but + * if it is placed below the usb_2_dwc3 node, it will be switched off after ~30 seconds. + * The reason seems to be that the dwc3 driver does not probe for child nodes when in + * host-only mode. But that's the default setting for the xhci controllers due to issues + * when in OTG mode. https://lore.kernel.org/all/20241210111444.26240-1-johan+linaro@kernel.org/ + * The whole reason it is described in the dt (as an USB device) is its requirement for + * that additional regulator, and to get power management to switch it off when suspended. + * Defining it stand-alone does work. + */ + camera { + compatible = "usb5986,1198"; + + vdd-supply = <&vreg_cam_5p0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + + /* Display-adjacent port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_sbu: endpoint { + remote-endpoint = <&usb_1_ss0_sbu_mux>; + }; + }; + }; + }; + + /* User-adjacent port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "host"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_sbu: endpoint { + remote-endpoint = <&usb_1_ss1_sbu_mux>; + }; + }; + }; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-LENOVO-ThinkBook-16"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + usb-1-ss0-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 167 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 168 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss0_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss0_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss0_sbu>; + }; + }; + }; + + usb-1-ss1-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 179 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss1_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss1_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss1_sbu>; + }; + }; + }; + + vreg_cam_5p0: regulator-cam-5p0 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_CAM_5P0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&tlmm 44 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VBL9"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_bl_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&misc_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name = "vreg_l5b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name = "vreg_l16b_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1f_1p0: ldo1 { + regulator-name = "vreg_l1f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l2f_1p0: ldo2 { + regulator-name = "vreg_l2f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l3f_1p0: ldo3 { + regulator-name = "vreg_l3f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/LENOVO/21NH/qcdxkmsucpurwa.mbn"; +}; + +&i2c2 { + clock-frequency = <400000>; + + pinctrl-0 = <&qup_i2c2_data_clk>, <&tpad_default>, <&kybd_default>; + pinctrl-names = "default"; + status = "okay"; + + /* ELAN06FA */ + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + /* CIRQ1080 or SYNA2BA6 */ + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + /* FTCS0038 */ + touchpad@38 { + compatible = "hid-over-i2c"; + reg = <0x38>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; + + /* GXTP5100 */ + touchpad@5d { + compatible = "hid-over-i2c"; + reg = <0x5d>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + wakeup-source; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + }; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb9_repeater: redriver@4b { + compatible = "nxp,ptn3222"; + reg = <0x4b>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb9_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + /* ILIT2911 or GTCH1563 */ + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_1p8>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + + backlight = <&backlight>; + + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pm8550_pwm { + status = "okay"; +}; + +&pm8550ve_8_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-disable; + output-enable; + drive-push-pull; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; /* 1.8V */ + input-disable; + output-enable; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio10"; + function = "normal"; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/LENOVO/21NH/qcadsp8380.mbn", + "qcom/x1p42100/LENOVO/21NH/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/LENOVO/21NH/qccdsp8380.mbn", + "qcom/x1p42100/LENOVO/21NH/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l6b_1p8>; + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <72 2>; /* Secure EC I2C connection (?) */ + + edp_hpd_default: edp-hpd-default-state { + pins = "gpio119"; + function = "edp0_hot"; + bias-disable; + }; + + cam_reg_en: cam-reg-en-state { + pins = "gpio44"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb9_reset_n: eusb9-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; + + usb_1_ss0_sbu_default: usb-1-ss0-sbu-state { + oe-n-pins { + pins = "gpio167"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio168"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + }; + + usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { + oe-n-pins { + pins = "gpio178"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio179"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; + +&usb_1_ss2 { + status = "okay"; +}; + +&usb_1_ss2_dwc3 { + dr_mode = "host"; + maximum-speed = "high-speed"; + phys = <&usb_1_ss2_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&eusb5_repeater>; + + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb9_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; From 5fa902fb5716f419915fdb11c6b7e62f5ba7d14f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20Gon=C3=A7alves?= Date: Fri, 15 Aug 2025 15:14:25 +0000 Subject: [PATCH 439/931] dt-bindings: arm: qcom: document r8q board binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add binding for the Samsung Galaxy S20 FE 4G/5G (SM-G980/SM-G981B) board, codenamed R8Q, which is based on the Qualcomm Snapdragon 865 SoC. Signed-off-by: Eric Gonçalves Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250815151426.32023-2-ghatto404@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f0a6f6f7b839..520e355d9cc9 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -981,6 +981,7 @@ properties: - qcom,qrb5165-rb5 - qcom,sm8250-hdk - qcom,sm8250-mtp + - samsung,r8q - sony,pdx203-generic - sony,pdx206-generic - xiaomi,elish From 6657fe9e9f23b1c61d0bcc14a3af732f92fdc19b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20Gon=C3=A7alves?= Date: Fri, 15 Aug 2025 15:14:26 +0000 Subject: [PATCH 440/931] arm64: dts: qcom: add initial support for Samsung Galaxy S20 FE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add new device support for the Samsung Galaxy S20 FE 4G/5G (SM-G980/SM-G981B) phone What works: - SimpleFB - Pstore/ramoops Signed-off-by: Eric Gonçalves Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250815151426.32023-3-ghatto404@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm8250-samsung-r8q.dts | 47 +++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8250-samsung-r8q.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4d449eb87a20..0383b888cce0 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -273,6 +273,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-bahamut.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8250-samsung-r8q.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-boe.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8250-samsung-r8q.dts b/arch/arm64/boot/dts/qcom/sm8250-samsung-r8q.dts new file mode 100644 index 000000000000..2fb6108ed5a9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-samsung-r8q.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sm8250.dtsi" + +/ { + model = "Samsung Galaxy S20 FE"; + compatible = "samsung,r8q", "qcom,sm8250"; + chassis-type = "handset"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@9c000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9c000000 0x0 (1080 * 2400 * 4)>; + width = <1080>; + height = <2400>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + reserved-memory { + cont_splash_mem: memory@9c000000 { + reg = <0x0 0x9c000000 0x0 (1080 * 2400 * 4)>; + no-map; + }; + + ramoops@9fa00000 { + compatible = "ramoops"; + reg = <0x0 0x9fa00000 0x0 0x100000>; + record-size = <0x4000>; + console-size = <0x40000>; + pmsg-size = <0x40000>; + ecc-size = <16>; + no-map; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <40 4>; /* I2C (not linked to anything) */ +}; From 036505842076eb8d2d39575628d6e7f7982e8c87 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Wed, 13 Aug 2025 21:39:14 +0530 Subject: [PATCH 441/931] arm64: dts: qcom: sm8450: Fix address for usb controller node Correct the address in usb controller node to fix the following warning: Warning (simple_bus_reg): /soc@0/usb@a6f8800: simple-bus unit address format error, expected "a600000" Fixes: c5a87e3a6b3e ("arm64: dts: qcom: sm8450: Flatten usb controller node") Cc: stable@vger.kernel.org Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202508121834.953Mvah2-lkp@intel.com/ Signed-off-by: Krishna Kurapati Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250813160914.2258033-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index dc539318662d..9ebf2b8700d2 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5421,7 +5421,7 @@ opp-202000000 { }; }; - usb_1: usb@a6f8800 { + usb_1: usb@a600000 { compatible = "qcom,sm8450-dwc3", "qcom,snps-dwc3"; reg = <0 0x0a600000 0 0xfc100>; status = "disabled"; From efc28845524843f199e420695eab3841299b05d2 Mon Sep 17 00:00:00 2001 From: Ling Xu Date: Wed, 13 Aug 2025 08:36:35 +0530 Subject: [PATCH 442/931] arm64: dts: qcom: lemans: add GDSP fastrpc-compute-cb nodes Add GDSP0 and GDSP1 fastrpc compute-cb nodes for lemans SoC. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Ling Xu Reviewed-by: Ekansh Gupta Link: https://lore.kernel.org/r/20250813030638.1075-3-quic_lxu5@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 58 ++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 99a566b42ef2..f5ec60086d60 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -6105,6 +6105,35 @@ IPCC_MPROC_SIGNAL_GLINK_QMP label = "gpdsp0"; qcom,remote-pid = <17>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "gdsp0"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x38a1 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x38a2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x38a3 0x0>; + dma-coherent; + }; + }; }; }; @@ -6148,6 +6177,35 @@ IPCC_MPROC_SIGNAL_GLINK_QMP label = "gpdsp1"; qcom,remote-pid = <18>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "gdsp1"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x38c1 0x0>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x38c2 0x0>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x38c3 0x0>; + dma-coherent; + }; + }; }; }; From 3d7f446472cb0d9e0dbae0aa09f3647d5649c758 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 12 Aug 2025 12:48:15 +0200 Subject: [PATCH 443/931] arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent data paths USB connector bindings describe a ports subnode, which describes how its High-/SuperSpeed data lines (as well as the SBU pins for Type-C) are connected. On Linux, skipping the graph results in the 'connect_type' sysfs attribute returning 'unknown', instead of 'hotplug' or similar. This in turn is parsed by some operating systems (such as CrOS), to e.g. make security policy decisions. Define ports {} for the DWC controller & the QMPPHY and connect them together for the SS lanes. Leave the DP endpoint unconnected for now, as both Aspire 1 and the Chromebooks (unmerged, see [1]) seem to have a non-trivial topology. Take the creative liberty to add a newline before its ports' subnodes though. [1] https://lore.kernel.org/linux-arm-msm/20240210070934.2549994-23-swboyd@chromium.org/ Suggested-by: Rob Herring (Arm) Closes: https://lore.kernel.org/linux-arm-msm/175462129176.394940.16810637795278334342.robh@kernel.org/ Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250812-topic-7180_qmpphy_ports-v2-1-7dc87e9a1f73@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 48 ++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 8f827f1d8515..a0df10a97c7f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2897,6 +2897,31 @@ usb_1_qmpphy: phy@88e8000 { #clock-cells = <1>; #phy-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_qmpphy_out: endpoint { }; + }; + + port@1 { + reg = <1>; + + usb_1_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_1_qmpphy_dp_in: endpoint { }; + }; + }; }; pmu@90b6300 { @@ -3070,6 +3095,26 @@ usb_1_dwc3: usb@a600000 { phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; maximum-speed = "super-speed"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; + }; + }; + }; }; }; @@ -3384,8 +3429,10 @@ mdss_dp: displayport-controller@ae90000 { ports { #address-cells = <1>; #size-cells = <0>; + port@0 { reg = <0>; + dp_in: endpoint { remote-endpoint = <&dpu_intf0_out>; }; @@ -3393,6 +3440,7 @@ dp_in: endpoint { port@1 { reg = <1>; + mdss_dp_out: endpoint { }; }; }; From 8517204c982b1b36db766099a38cf752258dcd06 Mon Sep 17 00:00:00 2001 From: Vignesh Viswanathan Date: Tue, 12 Aug 2025 10:22:12 +0530 Subject: [PATCH 444/931] arm64: dts: qcom: ipq5424: Add reserved memory for TF-A IPQ5424 supports both TZ and TF-A as secure software options and various DDR sizes. In most cases, TF-A or TZ is loaded at the same memory location, but in the 256MB DDR configuration TF-A is loaded at a different region. So, add the reserved memory node for TF-A and keep it disabled by default. During bootup, U-Boot will detect which secure software is running and enable or disable the node accordingly. Signed-off-by: Vignesh Viswanathan Reviewed-by: Konrad Dybcio Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20250812-atf-reserved-mem-v2-1-1adb94a998c1@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 67877fbbdf3a..ef2b52f3597d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -211,6 +211,12 @@ smem@8a800000 { hwlocks = <&tcsr_mutex 3>; }; + + tfa@8a832000 { + reg = <0x0 0x8a832000 0x0 0x7d000>; + no-map; + status = "disabled"; + }; }; soc@0 { From 922e16d1770624e25e2c751a257c88690f121b1c Mon Sep 17 00:00:00 2001 From: Cristian Cozzolino Date: Mon, 11 Aug 2025 23:08:09 +0200 Subject: [PATCH 445/931] dt-bindings: vendor-prefixes: Add Flipkart Add Flipkart to the vendor prefixes. Acked-by: Rob Herring (Arm) Signed-off-by: Cristian Cozzolino Link: https://lore.kernel.org/r/20250811-rimob-initial-devicetree-v4-1-b3194f14aa33@protonmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 77160cd47f54..b60957808e5f 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -548,6 +548,8 @@ patternProperties: description: Foxconn Industrial Internet "^firefly,.*": description: Firefly + "^flipkart,.*": + description: Flipkart Inc. "^focaltech,.*": description: FocalTech Systems Co.,Ltd "^forlinx,.*": From ba4857cc649a7a113252e849fbf12bc282399480 Mon Sep 17 00:00:00 2001 From: Cristian Cozzolino Date: Mon, 11 Aug 2025 23:08:10 +0200 Subject: [PATCH 446/931] dt-bindings: arm: qcom: Add Billion Capture+ Billion Capture+ (flipkart,rimob) is a smartphone based on Qualcomm Snapdragon 625 (MSM8953). Acked-by: Rob Herring (Arm) Signed-off-by: Cristian Cozzolino Link: https://lore.kernel.org/r/20250811-rimob-initial-devicetree-v4-2-b3194f14aa33@protonmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 520e355d9cc9..1221fb5f0665 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -187,6 +187,7 @@ properties: - items: - enum: + - flipkart,rimob - motorola,potter - xiaomi,daisy - xiaomi,mido From a2dd7cf8477e825b8028b4e36c787cee0f00a033 Mon Sep 17 00:00:00 2001 From: Cristian Cozzolino Date: Mon, 11 Aug 2025 23:08:11 +0200 Subject: [PATCH 447/931] arm64: dts: qcom: msm8953: Add device tree for Billion Capture+ Billion Capture+ (flipkart,rimob) is a smartphone released in 2017, based on Snapdragon 625 (MSM8953) SoC. Add a device tree with initial support for: - GPIO keys - SDHCI (internal and external storage) - USB Device Mode - Regulators - Simple framebuffer Reviewed-by: Konrad Dybcio Signed-off-by: Cristian Cozzolino Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250811-rimob-initial-devicetree-v4-3-b3194f14aa33@protonmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8953-flipkart-rimob.dts | 255 ++++++++++++++++++ 2 files changed, 256 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 0383b888cce0..fd4672c08e23 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8939-samsung-a7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-sony-xperia-kanuti-tulip.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-wingtech-wt82918.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-wingtech-wt82918hd.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8953-flipkart-rimob.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-mido.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts new file mode 100644 index 000000000000..ef4faf763132 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Cristian Cozzolino + */ +/dts-v1/; + +#include "msm8953.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" + +/delete-node/ &cont_splash_mem; +/delete-node/ &qseecom_mem; + +/ { + model = "Billion Capture+"; + compatible = "flipkart,rimob", "qcom,msm8953"; + chassis-type = "handset"; + qcom,msm-id = <293 0>; + qcom,board-id = <0x340008 0>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@90001000 { + compatible = "simple-framebuffer"; + reg = <0 0x90001000 0 (1920 * 1080 * 3)>; + + width = <1080>; + height = <1920>; + stride = <(1080 * 3)>; + format = "r8g8b8"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_key_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84a00000 { + reg = <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + cont_splash_mem: cont-splash@90001000 { + reg = <0x0 0x90001000 0x0 (1080 * 1920 * 3)>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&pm8953_resin { + linux,code = ; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + vdd_l23-supply = <&pm8953_s3>; + + pm8953_s1: s1 { + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <1156000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2050000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-allow-set-load; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + cd-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <135 4>; + + gpio_key_default: gpio-key-default-state { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; From 7a6ad5dd551a20672edceed087408ea6bcbfe8f2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 7 Aug 2025 18:33:24 +0200 Subject: [PATCH 448/931] arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13: Set up 4-lane DP Allow up to 4 lanes for the DisplayPort link from the PHYs to the controllers and allow mode-switch events to reach the QMP Combo PHYs. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov [konrad: reword] Signed-off-by: Konrad Dybcio Tested-by: Neil Armstrong # on Lenovo Thinkpad T14S Link: https://lore.kernel.org/r/20250807-topic-4ln_dp_respin-v4-6-43272d6eca92@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 73447a2e897e..637430719e6d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -738,7 +738,7 @@ &mdss0_dp0 { }; &mdss0_dp0_out { - data-lanes = <0 1>; + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_0_qmpphy_dp_in>; }; @@ -747,7 +747,7 @@ &mdss0_dp1 { }; &mdss0_dp1_out { - data-lanes = <0 1>; + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_1_qmpphy_dp_in>; }; @@ -1367,6 +1367,7 @@ &usb_0_qmpphy { vdda-phy-supply = <&vreg_l9d>; vdda-pll-supply = <&vreg_l4d>; + mode-switch; orientation-switch; status = "okay"; @@ -1404,6 +1405,7 @@ &usb_1_qmpphy { vdda-phy-supply = <&vreg_l4b>; vdda-pll-supply = <&vreg_l3b>; + mode-switch; orientation-switch; status = "okay"; From f116ec4e149e2b8a36579284af7b0630d7f57723 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Tue, 15 Jul 2025 21:26:57 -0300 Subject: [PATCH 449/931] dt-bindings: arm: qcom: Add Dell Inspiron 14 Plus 7441 Document the X1E80100-based Dell Inspiron 14 Plus 7441 laptop, codename: Thena. Signed-off-by: Bryan O'Donoghue Acked-by: Krzysztof Kozlowski Signed-off-by: Val Packett Reviewed-by: Laurentiu Tudor Tested-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250716003139.18543-2-val@packett.cool Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1221fb5f0665..1fc6319bec6b 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1054,6 +1054,7 @@ properties: - enum: - asus,vivobook-s15 - asus,zenbook-a14-ux3407ra + - dell,inspiron-14-plus-7441 - dell,latitude-7455 - dell,xps13-9345 - hp,elitebook-ultra-g1q From e7733b42111ca83a60745b9b9db411ae74811ce9 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Tue, 15 Jul 2025 21:26:59 -0300 Subject: [PATCH 450/931] arm64: dts: qcom: Add support for Dell Inspiron 7441 / Latitude 7455 Add device trees for both SKUs of the X1E80100 Thena laptop: - Dell Latitude 7455 - Dell Inspiron 14 Plus 7441 Works: - Wi-Fi (WCN7850 hw2.0) - Bluetooth - USB Type-C x2 (with DP alt mode) - USB Type-A - USB Fingerprint reader - eDP Display (with brightness) - NVMe - SDHC (microSD slot) - Keyboard - Touchpad - Touchscreen - Audio (4 Speakers, 2 DMICs, Combo Jack) - Battery Not included: - Camera Signed-off-by: Bryan O'Donoghue Co-developed-by: Val Packett Signed-off-by: Val Packett Reviewed-by: Laurentiu Tudor Reviewed-by: Konrad Dybcio Tested-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250716003139.18543-4-val@packett.cool Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 4 + arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi | 1666 +++++++++++++++++ .../x1e80100-dell-inspiron-14-plus-7441.dts | 52 + .../dts/qcom/x1e80100-dell-latitude-7455.dts | 53 + 4 files changed, 1775 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index fd4672c08e23..0a7c308dec36 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -315,6 +315,10 @@ x1e80100-asus-zenbook-a14-el2-dtbs := x1e80100-asus-zenbook-a14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-zenbook-a14.dtb x1e80100-asus-zenbook-a14-el2.dtb x1e80100-crd-el2-dtbs := x1e80100-crd.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb x1e80100-crd-el2.dtb +x1e80100-dell-inspiron-14-plus-7441-el2-dtbs := x1e80100-dell-inspiron-14-plus-7441.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-inspiron-14-plus-7441.dtb x1e80100-dell-inspiron-14-plus-7441-el2.dtb +x1e80100-dell-latitude-7455-el2-dtbs := x1e80100-dell-latitude-7455.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-latitude-7455.dtb x1e80100-dell-latitude-7455-el2.dtb x1e80100-dell-xps13-9345-el2-dtbs := x1e80100-dell-xps13-9345.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-dell-xps13-9345.dtb x1e80100-dell-xps13-9345-el2.dtb x1e80100-hp-elitebook-ultra-g1q-el2-dtbs := x1e80100-hp-elitebook-ultra-g1q.dtb x1-el2.dtbo diff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi new file mode 100644 index 000000000000..cc64558ed5e6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi @@ -0,0 +1,1666 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024 Aleksandrs Vinarskis + * Copyright (c) 2025 Bryan O'Donoghue + * Copyright (c) 2025 Val Packett + */ + +#include +#include +#include +#include +#include + +#include "x1e80100-pmics.dtsi" + +/ { + chassis-type = "laptop"; + + aliases { + serial0 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <40000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + /* Display-adjacent port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + /* User-adjacent port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&cam_indicator_en>; + pinctrl-names = "default"; + + led-camera-indicator { + label = "white:camera-indicator"; + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + /* Reuse as a panic indicator until we get a "camera on" trigger */ + panic-indicator; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound: sound { + compatible = "qcom,x1e80100-sndcard"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK1 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vreg_cam_1p8: regulator-cam-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_CAM_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 91 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&cam_ldo_en>; + pinctrl-names = "default"; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + keyboard@5 { + compatible = "hid-over-i2c"; + reg = <0x5>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8833", "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + /* EC @0x3b */ + + /* Type A Port */ + eusb3_typea_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + /* Fingerprint scanner */ + eusb5_frp_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8833", "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr1_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c20 { + clock-frequency = <400000>; + + status = "okay"; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + enable-gpios = <&tlmm 74 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 71 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l6b_1p8>; + bus-width = <4>; + no-sdio; + no-mmc; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <44 4>, /* SPI11 (TPM) */ + <76 4>, /* SPI19 (TZ Protected) */ + <238 1>; /* UFS Reset */ + + cam_rgb_default: cam-rgb-default-state { + mclk-pins { + pins = "gpio100"; + function = "cam_aon"; + drive-strength = <16>; + bias-disable; + }; + + reset-n-pins { + pins = "gpio237"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam_indicator_en: cam-indicator-en-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam_ldo_en: cam-ldo-en-state { + pins = "gpio91"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + edp_bl_en: edp-bl-en-state { + pins = "gpio74"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-pull-up; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + rtmr1_default: rtmr1-reset-n-active-state { + pins = "gpio176"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + tpad_default: tpad-default-state { + disable-pins { + pins = "gpio38"; + function = "gpio"; + output-high; + }; + + int-n-pins { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + reset-n-pins { + pins = "gpio52"; + function = "gpio"; + bias-disable; + }; + }; + + ts0_default: ts0-default-state { + disable-pins { + pins = "gpio75"; + function = "gpio"; + output-high; + }; + + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-pull-up; + }; + + reset-n-pins { + /* Technically should be High-Z input */ + pins = "gpio48"; + function = "gpio"; + output-low; + drive-strength = <2>; + }; + }; + + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&retimer_ss1_ss_in>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb5_frp_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_typea_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts new file mode 100644 index 000000000000..f728d298c72f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Val Packett + */ +/dts-v1/; + +#include "x1e80100.dtsi" +#include "x1-dell-thena.dtsi" + +/ { + model = "Dell Inspiron 14 Plus 7441"; + compatible = "dell,inspiron-14-plus-7441", "qcom,x1e80100"; +}; + +&sound { + model = "X1E80100-Dell-Inspiron-14p-7441"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/dell/inspiron-14-plus-7441/qcdxkmsuc8380.mbn"; +}; + +&i2c8 { + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/dell/inspiron-14-plus-7441/qcadsp8380.mbn", + "qcom/x1e80100/dell/inspiron-14-plus-7441/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/dell/inspiron-14-plus-7441/qccdsp8380.mbn", + "qcom/x1e80100/dell/inspiron-14-plus-7441/cdsp_dtbs.elf"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts new file mode 100644 index 000000000000..ace2a905e443 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Val Packett + */ +/dts-v1/; + +#include "x1e80100.dtsi" +#include "x1-dell-thena.dtsi" + +/ { + model = "Dell Latitude 7455"; + compatible = "dell,latitude-7455", "qcom,x1e80100"; +}; + +&sound { + model = "X1E80100-Dell-Latitude-7455"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/dell/latitude-7455/qcdxkmsuc8380.mbn"; +}; + +&i2c8 { + /* LXST2021 */ + touchscreen@9 { + compatible = "hid-over-i2c"; + reg = <0x09>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/dell/latitude-7455/qcadsp8380.mbn", + "qcom/x1e80100/dell/latitude-7455/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/dell/latitude-7455/qccdsp8380.mbn", + "qcom/x1e80100/dell/latitude-7455/cdsp_dtbs.elf"; + + status = "okay"; +}; From 03253befa1d1f36b297889c7ce2805c9319814ff Mon Sep 17 00:00:00 2001 From: Satya Priya Kakitapalli Date: Thu, 10 Jul 2025 18:30:40 +0530 Subject: [PATCH 451/931] arm64: dts: qcom: sc8180x: Add video clock controller node Add device node for video clock controller on Qualcomm sc8180x platform. Reviewed-by: Konrad Dybcio Signed-off-by: Satya Priya Kakitapalli Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250710-sc8180x-videocc-dt-v4-2-07a9d9d5e0e6@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index b8a64bf372cc..815095c2f8c7 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -2927,6 +2928,20 @@ usb_sec_dwc3_ss: endpoint { }; }; + videocc: clock-controller@ab00000 { + compatible = "qcom,sc8180x-videocc", + "qcom,sm8150-videocc"; + reg = <0 0x0ab00000 0 0x10000>; + clocks = <&gcc GCC_VIDEO_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bi_tcxo"; + power-domains = <&rpmhpd SC8180X_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sc8180x-camcc"; reg = <0 0x0ad00000 0 0x20000>; From bdc4d388c6452498ab62ef2564589f40e0c8c262 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 28 Aug 2025 16:43:00 +0000 Subject: [PATCH 452/931] arm64: dts: rockchip: add SPDIF audio to Beelink A1 Add the required nodes to enable SPDIF audio output on the Beelink A1 set-top-box. Signed-off-by: Alex Bee Signed-off-by: Christian Hewitt Link: https://lore.kernel.org/r/20250828164300.3829488-1-christianshewitt@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts index f7c4578865c5..e0f0e5791a57 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts @@ -58,6 +58,24 @@ ir-receiver { gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; linux,rc-map-name = "rc-beelink-gs1"; }; + + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; }; &analog_sound { @@ -325,6 +343,11 @@ &sdmmc { status = "okay"; }; +&spdif { + pinctrl-0 = <&spdifm0_tx>; + status = "okay"; +}; + &tsadc { rockchip,hw-tshut-mode = <0>; rockchip,hw-tshut-polarity = <0>; From c05dac8e54bfd1e3af2e971f01c56f9ddeca4a0f Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 28 Aug 2025 17:16:45 +0000 Subject: [PATCH 453/931] arm64: dts: rockchip: add USB3 on Beelink A1 Enable USB3 for the Beelink A1 set-top box. Signed-off-by: Alex Bee Signed-off-by: Christian Hewitt Link: https://lore.kernel.org/r/20250828171645.3830437-1-christianshewitt@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts index e0f0e5791a57..30bdb38f0727 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts @@ -381,6 +381,11 @@ &usb_host0_ehci { status = "okay"; }; +&usbdrd3 { + dr_mode = "host"; + status = "okay"; +}; + &vop { status = "okay"; }; From faeb2bede83475fc74230d4ee4f4cc126eb6a444 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 28 Aug 2025 15:11:07 +0200 Subject: [PATCH 454/931] dt-bindings: soc: rockchip: add missing clock reference for rk3576-dcphy syscon The rk3576 mipi dcphy syscon controls a clock, so needs to allow the clock property. Add the missing entry in the list for it. Fixes: 0e3f3d7c7ae3 ("dt-bindings: soc: rockchip: add rk3576 mipi dcphy syscon") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202508271156.z3wDB6bX-lkp@intel.com/ Acked-by: Conor Dooley Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20250828131107.3531769-1-heiko@sntech.de --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 6a94c271a6b1..1d0f35e26311 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -301,6 +301,7 @@ allOf: compatible: contains: enum: + - rockchip,rk3576-dcphy-grf - rockchip,rk3576-vo1-grf - rockchip,rk3588-vo-grf - rockchip,rk3588-vo0-grf From af13e0089e98a135757ae46f6f9d5a96d33af840 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 17 Jul 2025 10:37:03 +0000 Subject: [PATCH 455/931] dt-bindings: arm: rockchip: Add Radxa ROCK 2A/2F The ROCK 2A and ROCK 2F is a high-performance single board computer developed by Radxa, based on the Rockchip RK3528A SoC. Add devicetree binding documentation for the Radxa ROCK 2A and ROCK 2F boards. Signed-off-by: Jonas Karlman Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250717103720.2853031-2-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 870c318fc8d4..9c34630c11de 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -888,6 +888,13 @@ properties: - const: radxa,rock - const: rockchip,rk3188 + - description: Radxa ROCK 2A/2F + items: + - enum: + - radxa,rock-2a + - radxa,rock-2f + - const: rockchip,rk3528 + - description: Radxa ROCK Pi 4A/A+/B/B+/C items: - enum: From 5b71b3d9aa61626d6a93ed2f761a748aa2ecfa95 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 17 Jul 2025 10:37:04 +0000 Subject: [PATCH 456/931] arm64: dts: rockchip: Add Radxa ROCK 2A/2F The ROCK 2A and ROCK 2F is a high-performance single board computer developed by Radxa, based on the Rockchip RK3528A SoC. Add initial device tree for the Radxa ROCK 2A and ROCK 2F boards. Signed-off-by: Jonas Karlman Tested-by: Yao Zi Reviewed-by: Nicolas Frattaroli Tested-by: Nicolas Frattaroli Link: https://lore.kernel.org/r/20250717103720.2853031-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 2 + .../boot/dts/rockchip/rk3528-rock-2.dtsi | 293 ++++++++++++++++++ .../boot/dts/rockchip/rk3528-rock-2a.dts | 82 +++++ .../boot/dts/rockchip/rk3528-rock-2f.dts | 10 + 4 files changed, 387 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 93e547a1c77b..132565836e80 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -90,6 +90,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-radxa-e20c.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2f.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg-arc-d.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg-arc-s.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi new file mode 100644 index 000000000000..aedc7ee9ee46 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi @@ -0,0 +1,293 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3528.dtsi" + +/ { + aliases { + i2c1 = &i2c1; + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "MASKROM"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&state_led_b>; + + led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vdd_0v9: regulator-0v9-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr: regulator-1v1-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_wifi: regulator-3v3-vcc-wifi { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_wifi_pwr>; + regulator-name = "vcc_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb20: regulator-5v0-vcc-usb20 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_en>; + regulator-name = "vcc5v0_usb20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vccio_sd: regulator-vccio-sd { + compatible = "regulator-gpio"; + gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_vol_ctrl_h>; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, <3300000 0x1>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_arm: regulator-vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-settling-time-up-us = <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-settling-time-up-us = <250>; + }; + + rfkill { + compatible = "rfkill-gpio"; + label = "rfkill-wlan"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + radio-type = "wlan"; + shutdown-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + status = "okay"; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v3>; + }; +}; + +&pinctrl { + bluetooth { + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + state_led_b: state-led-b { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_en: usb-host-en { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + usb_wifi_pwr: usb-wifi-pwr { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1m0_pins>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <100000000>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts b/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts new file mode 100644 index 000000000000..c03ae1dd3456 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3528-rock-2.dtsi" + +/ { + model = "Radxa ROCK 2A"; + compatible = "radxa,rock-2a", "rockchip,rk3528"; + + aliases { + ethernet0 = &gmac1; + }; + + vcc5v0_usb30_otg: regulator-5v0-vcc-usb30-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_en>; + regulator-name = "vcc5v0_usb30_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>, + <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>; + status = "okay"; +}; + +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&state_led_b>, <&sys_led_g>; + + led-1 { + color = ; + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn_l>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + gmac1_rstn_l: gmac1-rstn-l { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + sys_led_g: sys-led-g { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_otg_en: usb-otg-en { + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts b/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts new file mode 100644 index 000000000000..3e2b9b685cb2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3528-rock-2.dtsi" + +/ { + model = "Radxa ROCK 2F"; + compatible = "radxa,rock-2f", "rockchip,rk3528"; +}; From 10e6b1caacb85bb41cacb9271cdb794ae323ee52 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 17 Jul 2025 10:37:05 +0000 Subject: [PATCH 457/931] dt-bindings: arm: rockchip: Add ArmSoM Sige1 The Sige1 is a single board computer developed by ArmSoM, based on the Rockchip RK3528A SoC. Add devicetree binding documentation for the ArmSoM Sige1 board. Signed-off-by: Jonas Karlman Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250717103720.2853031-4-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 9c34630c11de..ab4f0512da43 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -54,6 +54,11 @@ properties: - const: ariaboard,photonicat - const: rockchip,rk3568 + - description: ArmSoM Sige1 board + items: + - const: armsom,sige1 + - const: rockchip,rk3528 + - description: ArmSoM Sige5 board items: - const: armsom,sige5 From 1c6b12ef9575bc18dad2393e50ca1ebf96f0a0c8 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 17 Jul 2025 10:37:06 +0000 Subject: [PATCH 458/931] arm64: dts: rockchip: Add ArmSoM Sige1 The Sige1 is a single board computer developed by ArmSoM, based on the Rockchip RK3528A SoC. Add initial device tree for the ArmSoM Sige1 board. Signed-off-by: Jonas Karlman Link: https://lore.kernel.org/r/20250717103720.2853031-5-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3528-armsom-sige1.dts | 464 ++++++++++++++++++ 2 files changed, 465 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 132565836e80..4ea9a68f97ef 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -89,6 +89,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-screen.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-armsom-sige1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-radxa-e20c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2f.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts new file mode 100644 index 000000000000..6e21579365a5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts @@ -0,0 +1,464 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3528.dtsi" + +/ { + model = "ArmSoM Sige1"; + compatible = "armsom,sige1", "rockchip,rk3528"; + + aliases { + ethernet0 = &gmac1; + i2c0 = &i2c0; + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio0; + serial0 = &uart0; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "MASKROM"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&g_led>, <&r_led>; + + led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + color = ; + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + vcc0v6_ddr: regulator-0v6-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc0v6_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_0v9: regulator-0v9-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr: regulator-1v1-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + vcc1v8_ddr: regulator-1v8-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_dcin>; + }; + + vcc3v3_sd: regulator-3v3-vcc-sd { + compatible = "regulator-fixed"; + gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren_l>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_dcin>; + }; + + vcc5v0_usb1_host: regulator-5v0-vcc-usb1-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host1_drv_h>; + regulator-name = "vcc5v0_usb1_host"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb2_host: regulator-5v0-vcc-usb2-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host2_drv_h>; + regulator-name = "vcc5v0_usb2_host"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_otg0_drv_h>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_dcin: regulator-vcc-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc_dcin"; + regulator-always-on; + regulator-boot-on; + }; + + vccio_sd: regulator-vccio-sd { + compatible = "regulator-gpio"; + gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_vol_ctrl_h>; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, <3300000 0x1>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_arm: regulator-vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-settling-time-up-us = <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-settling-time-up-us = <250>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>, <&clkm1_32k_out>; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>, + <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m0_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + interrupt-parent = <&gpio4>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_l>; + wakeup-source; + }; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn_l>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + gmac1_rstn_l: gmac1-rstn-l { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + g_led: g-led { + rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + r_led: r-led { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtc { + rtc_int_l: rtc-int-l { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb20_host1_drv_h: usb20-host1-drv-h { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb20_host2_drv_h: usb20-host2-drv-h { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb20_otg0_drv_h: usb20-otg0-drv-h { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + clocks = <&cru CLK_DEEPSLOW>; + clock-names = "lpo"; + interrupt-parent = <&gpio1>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host_h>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&uart2 { + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>, <&uart2m1_ctsn>, <&uart2m1_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&cru CLK_DEEPSLOW>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + interrupts = ; + interrupt-names = "host-wakeup"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h>, <&bt_wake_host_h>, <&host_wake_bt_h>; + shutdown-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3>; + vddio-supply = <&vcc_1v8>; + }; +}; From 11100e8f407e99adac2d311803540540b9726699 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 17 Jul 2025 10:37:07 +0000 Subject: [PATCH 459/931] dt-bindings: arm: rockchip: Add FriendlyElec NanoPi Zero2 The NanoPi Zero2 is small single board computer developed by FriendlyElec, based on the Rockchip RK3528A SoC. Add devicetree binding documentation for the FriendlyElec NanoPi Zero2 board. Signed-off-by: Jonas Karlman Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250717103720.2853031-6-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index ab4f0512da43..f9ee77f17ad7 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -325,6 +325,11 @@ properties: - friendlyarm,nanopi-r6s - const: rockchip,rk3588s + - description: FriendlyElec NanoPi Zero2 + items: + - const: friendlyarm,nanopi-zero2 + - const: rockchip,rk3528 + - description: FriendlyElec NanoPC T6 series boards items: - enum: From b944112abef4e52e81b19be44a7bac5b45779ba1 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Thu, 17 Jul 2025 10:37:08 +0000 Subject: [PATCH 460/931] arm64: dts: rockchip: Add FriendlyElec NanoPi Zero2 The NanoPi Zero2 is a small single board computer developed by FriendlyElec, based on the Rockchip RK3528A SoC. Add initial device tree for the FriendlyElec NanoPi Zero2 board. Signed-off-by: Jonas Karlman Tested-by: Yao Zi Link: https://lore.kernel.org/r/20250717103720.2853031-7-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3528-nanopi-zero2.dts | 340 ++++++++++++++++++ 2 files changed, 341 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 4ea9a68f97ef..9d56d4146b20 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -90,6 +90,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-armsom-sige1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-nanopi-zero2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-radxa-e20c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2f.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts new file mode 100644 index 000000000000..9f683033c5f3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-nanopi-zero2.dts @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3528.dtsi" + +/ { + model = "FriendlyElec NanoPi Zero2"; + compatible = "friendlyarm,nanopi-zero2", "rockchip,rk3528"; + + aliases { + ethernet0 = &gmac1; + i2c1 = &i2c1; + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc-keys-0 { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "MASK"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + adc-keys-1 { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "RECOVERY"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led1>, <&led_sys>; + + led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + color = ; + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + }; + + vcc0v6_ddr: regulator-0v6-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc0v6_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_0v9: regulator-0v9-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr: regulator-1v1-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sd: regulator-3v3-vcc-sd { + compatible = "regulator-fixed"; + gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren_l>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + usb2_host_5v: regulator-5v0-usb2-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host1_pwren>; + regulator-name = "usb2_host_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vccio_sd: regulator-vccio-sd { + compatible = "regulator-gpio"; + gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_vol_ctrl_h>; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, <3300000 0x1>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_arm: regulator-vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-settling-time-up-us = <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-settling-time-up-us = <250>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>, + <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + interrupt-parent = <&gpio4>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_l>; + wakeup-source; + }; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn_l>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + gmac1_rstn_l: gmac1-rstn-l { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led1: led1 { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_sys: led-sys { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtc { + rtc_int_l: rtc-int-l { + rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb20_host1_pwren: usb20-host1-pwren { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1m0_pins>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; From 680826a5299bbb4cec839a04ac6032be719c4c05 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 22 Aug 2025 14:39:51 +0800 Subject: [PATCH 461/931] arm64: dts: rockchip: Add DP0 for rk3588 The DP0 is compliant with the DisplayPort Specification Version 1.4, and share the USBDP combo PHY0 with USB 3.1 HOST0 controller. Signed-off-by: Andy Yan Reviewed-by: Sebastian Reichel Link: https://lore.kernel.org/r/20250822063959.692098-8-andyshrk@163.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index a18aa1e6c3f1..23a41c151c5d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1563,6 +1563,36 @@ dsi1_out: port@1 { }; }; + dp0: dp@fde50000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x0 0xfde50000 0x0 0x4000>; + interrupts = ; + assigned-clocks = <&cru CLK_AUX16M_0>; + assigned-clock-rates = <16000000>; + clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>, + <&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>, + <&cru MCLK_SPDIF2_DP0>; + clock-names = "apb", "aux", "hdcp", "i2s", "spdif"; + phys = <&usbdp_phy0 PHY_TYPE_DP>; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_DP0>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp0_in: port@0 { + reg = <0>; + }; + + dp0_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi0: hdmi@fde80000 { compatible = "rockchip,rk3588-dw-hdmi-qp"; reg = <0x0 0xfde80000 0x0 0x20000>; From 64566e35757faded57a65d65e84b5ca95974ee19 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 22 Aug 2025 14:39:52 +0800 Subject: [PATCH 462/931] arm64: dts: rockchip: Add DP1 for rk3588 The DP1 is compliant with the DisplayPort Specification Version 1.4, and share the USBDP combo PHY1 with USB 3.1 HOST1 controller. Signed-off-by: Andy Yan Reviewed-by: Sebastian Reichel Link: https://lore.kernel.org/r/20250822063959.692098-9-andyshrk@163.com Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 90414486e466..6e5a58428bba 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -210,6 +210,36 @@ i2s10_8ch: i2s@fde00000 { status = "disabled"; }; + dp1: dp@fde60000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x0 0xfde60000 0x0 0x4000>; + interrupts = ; + assigned-clocks = <&cru CLK_AUX16M_1>; + assigned-clock-rates = <16000000>; + clocks = <&cru PCLK_DP1>, <&cru CLK_AUX16M_1>, + <&cru CLK_DP1>, <&cru MCLK_I2S8_8CH_TX>, + <&cru MCLK_SPDIF5_DP1>; + clock-names = "apb", "aux", "hdcp", "i2s", "spdif"; + phys = <&usbdp_phy1 PHY_TYPE_DP>; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_DP1>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp1_in: port@0 { + reg = <0>; + }; + + dp1_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi1: hdmi@fdea0000 { compatible = "rockchip,rk3588-dw-hdmi-qp"; reg = <0x0 0xfdea0000 0x0 0x20000>; From 7260b0f1d6a1555a57f6e94db18c932af8e0e714 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 22 Aug 2025 14:39:53 +0800 Subject: [PATCH 463/931] arm64: dts: rockchip: Enable DisplayPort for rk3588s Cool Pi 4B Enable the Mini DisplayPort on this board. Note that ROCKCHIP_VOP2_EP_DP0 is defined as 10 in dt-binding header, but it will trigger a dtc warning like "graph node unit address error, expected "a"" if we use it directly after endpoint, so we use "a" instead here. Signed-off-by: Andy Yan Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822063959.692098-10-andyshrk@163.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588s-coolpi-4b.dts | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts index b2947b36fada..189444d20779 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-coolpi-4b.dts @@ -39,6 +39,18 @@ chosen { stdout-path = "serial2:1500000n8"; }; + dp-con { + compatible = "dp-connector"; + label = "DP OUT"; + type = "mini"; + + port { + dp_con_in: endpoint { + remote-endpoint = <&dp0_out_con>; + }; + }; + }; + hdmi-con { compatible = "hdmi-connector"; type = "d"; @@ -215,6 +227,24 @@ &cpu_b2 { cpu-supply = <&vdd_cpu_big1_s0>; }; +&dp0 { + pinctrl-0 = <&dp0m0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp0_in { + dp0_in_vp2: endpoint { + remote-endpoint = <&vp2_out_dp0>; + }; +}; + +&dp0_out { + dp0_out_con: endpoint { + remote-endpoint = <&dp_con_in>; + }; +}; + &gpu { mali-supply = <&vdd_gpu_s0>; status = "okay"; @@ -890,3 +920,10 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp2 { + vp2_out_dp0: endpoint@a { + reg = ; + remote-endpoint = <&dp0_in_vp2>; + }; +}; From 07c53a9e970712b1a479dd0ec4adfe184482c22f Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 22 Aug 2025 14:39:54 +0800 Subject: [PATCH 464/931] arm64: dts: rockchip: Enable DP2HDMI for ROCK 5 ITX The HDMI0(Port next to Headphone Jack) is driven by DP1 on rk3588 via RA620(a dp2hdmi converter). Add related dt nodes to enable it. Note: ROCKCHIP_VOP2_EP_DP1 is defined as 11 in dt-binding header, but it will trigger a dtc warning like "graph node unit address error, expected "b"" if we use it directly after endpoint, so we use "b" instead here. Signed-off-by: Andy Yan Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250822063959.692098-11-andyshrk@163.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-rock-5-itx.dts | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts index 7de17117df7a..bc8140883de4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -57,6 +57,31 @@ analog-sound { "Headphone", "Headphones"; }; + bridge { + compatible = "radxa,ra620"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_in: endpoint { + remote-endpoint = <&dp1_out_con>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_out: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + }; + }; + gpio-leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -73,6 +98,17 @@ hdd-led2 { }; }; + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_bridge_out>; + }; + }; + }; + hdmi1-con { compatible = "hdmi-connector"; type = "a"; @@ -268,6 +304,24 @@ &cpu_l3 { cpu-supply = <&vdd_cpu_lit_s0>; }; +&dp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp1m0_pins>; +}; + +&dp1_in { + dp1_in_vp2: endpoint { + remote-endpoint = <&vp2_out_dp1>; + }; +}; + +&dp1_out { + dp1_out_con: endpoint { + remote-endpoint = <&hdmi_bridge_in>; + }; +}; + &gpu { mali-supply = <&vdd_gpu_s0>; status = "okay"; @@ -1261,3 +1315,10 @@ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { remote-endpoint = <&hdmi1_in_vp1>; }; }; + +&vp2 { + vp2_out_dp1: endpoint@b { + reg = ; + remote-endpoint = <&dp1_in_vp2>; + }; +}; From 1557c2eb023d9cdf97b4686fd206048c070d4e70 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Aug 2025 13:32:54 +0200 Subject: [PATCH 465/931] dt-bindings: arm: samsung: Drop S3C2416 Samsung S3C24xx family of SoCs was removed from the Linux kernel in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January 2023. There are no in-kernel users of remaining S3C24xx compatibles. Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250830113253.131974-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ------ 1 file changed, 6 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index 26fe899badc5..f8e20e602c20 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -14,12 +14,6 @@ properties: const: '/' compatible: oneOf: - - description: S3C2416 based boards - items: - - enum: - - samsung,smdk2416 # Samsung SMDK2416 - - const: samsung,s3c2416 - - description: S3C6410 based boards items: - enum: From 81d79ad0ddcaeaf6136abe870b2386bde31b7ed4 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 22 Aug 2025 11:06:32 +0800 Subject: [PATCH 466/931] riscv: dts: spacemit: Add PDMA node for K1 SoC Add PDMA dma-controller node under dma_bus for SpacemiT K1 SoC. The PDMA node is marked as disabled by default, allowing board-specific device trees to enable it as needed. Signed-off-by: Guodong Xu Reviewed-by: Troy Mitchell Link: https://lore.kernel.org/r/20250822-working_dma_0701_v2-v5-6-f5c0eda734cc@riscstar.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 6c68b2e54675..19dc9c94e5b5 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -660,6 +660,17 @@ dma-bus { dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, <0x1 0x00000000 0x1 0x80000000 0x3 0x00000000>; + pdma: dma-controller@d4000000 { + compatible = "spacemit,k1-pdma"; + reg = <0x0 0xd4000000 0x0 0x4000>; + clocks = <&syscon_apmu CLK_DMA>; + resets = <&syscon_apmu RESET_DMA>; + interrupts = <72>; + dma-channels = <16>; + #dma-cells= <1>; + status = "disabled"; + }; + uart0: serial@d4017000 { compatible = "spacemit,k1-uart", "intel,xscale-uart"; From 0e28eab0ca51282e3d14f3e2dba9fc92e3fddbe6 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Fri, 22 Aug 2025 11:06:33 +0800 Subject: [PATCH 467/931] riscv: dts: spacemit: Enable PDMA on Banana Pi F3 and Milkv Jupiter Enable the PDMA on the SpacemiT K1-based Banana Pi F3 and Milkv Jupiter boards by setting its status to "okay". Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20250822-working_dma_0701_v2-v5-7-f5c0eda734cc@riscstar.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 ++++ arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index fe22c747c501..6013be258542 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -40,6 +40,10 @@ &emmc { status = "okay"; }; +&pdma { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index 448319214104..c615fcadbd33 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -20,6 +20,10 @@ chosen { }; }; +&pdma { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; From 7d506a8905590f2741079fb3444be0afacf101b0 Mon Sep 17 00:00:00 2001 From: Peter Yin Date: Thu, 28 Aug 2025 15:49:51 +0800 Subject: [PATCH 468/931] ARM: dts: aspeed: harma: add power monitor support Add INA238 device on I2C bus 4 for the PDB board power monitoring. Signed-off-by: Peter Yin Link: https://patch.msgid.link/20250828074955.542711-2-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts index b9a93f23bd0a..741d2d9b6d03 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts @@ -373,6 +373,12 @@ power-monitor@40 { compatible = "infineon,xdp710"; reg = <0x40>; }; + + power-sensor@45 { + compatible = "ti,ina238"; + reg = <0x45>; + shunt-resistor = <500>; + }; }; &i2c5 { From c2487598b1fefde51fca06a27111f8630698b0d2 Mon Sep 17 00:00:00 2001 From: Peter Yin Date: Thu, 28 Aug 2025 15:49:52 +0800 Subject: [PATCH 469/931] ARM: dts: aspeed: harma: revise gpio name Update GPIO label definitions in the device tree to reflect the correct power and control signal names. This includes: - Rename "fcb0-activate" to "fcb1-activate" and "fcb2-activate" - Add labels for: - power-p3v3-standby - power-p1v8-good - power-pvdd33-s5 - power-pvdd18-s5 - power-asic-good - power-12v-memory-good - Replace unnamed GPIOs with appropriate labels such as: - irq-pvddcore0-ocp-alert - irq-pvddcore1-ocp-alert Signed-off-by: Peter Yin Link: https://patch.msgid.link/20250828074955.542711-3-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery --- .../dts/aspeed/aspeed-bmc-facebook-harma.dts | 21 +++++++++++-------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts index 741d2d9b6d03..81278a7702de 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts @@ -234,7 +234,7 @@ gpio@12 { "","", "","", "","", - "","fcb1-activate", + "","fcb2-activate", "",""; }; }; @@ -308,7 +308,7 @@ gpio@12 { "","", "","", "","", - "","fcb0-activate", + "","fcb1-activate", "",""; }; }; @@ -698,14 +698,14 @@ &sgpiom0 { "","", /*A4-A7 line 8-15*/ "","power-config-asic-module-enable", - "","power-config-asic-power-good", - "","power-config-pdb-power-good", + "power-p3v3-standby","power-config-asic-power-good", + "power-p1v8-good","power-config-pdb-power-good", "presence-cpu","smi-control-n", /*B0-B3 line 16-23*/ "","nmi-control-n", - "","nmi-control-sync-flood-n", - "","", + "power-pvdd33-s5","nmi-control-sync-flood-n", "","", + "power-pvdd18-s5","", /*B4-B7 line 24-31*/ "","FM_CPU_SP5R1", "reset-cause-rsmrst","FM_CPU_SP5R2", @@ -749,7 +749,7 @@ &sgpiom0 { /*F4-F7 line 88-95*/ "presence-asic-modules-0","rt-cpu0-p1-force-enable", "presence-asic-modules-1","bios-debug-msg-disable", - "","uart-control-buffer-select", + "power-asic-good","uart-control-buffer-select", "presence-cmm","ac-control-n", /*G0-G3 line 96-103*/ "FM_CPU_CORETYPE2","", @@ -801,7 +801,7 @@ &sgpiom0 { "asic0-card-type-detection2-n","", "uart-switch-lsb","", "uart-switch-msb","", - "","", + "power-12v-memory-good","", /*M4-M7 line 200-207*/ "","","","","","","","", /*N0-N3 line 208-215*/ @@ -809,7 +809,10 @@ &sgpiom0 { /*N4-N7 line 216-223*/ "","","","","","","","", /*O0-O3 line 224-231*/ - "","","","","","","","", + "","", + "irq-pvddcore0-ocp-alert","", + "irq-pvddcore1-ocp-alert","", + "","", /*O4-O7 line 232-239*/ "","","","","","","","", /*P0-P3 line 240-247*/ From 3f3d7dbe3c63716a11211861513222d52655a2cb Mon Sep 17 00:00:00 2001 From: Peter Yin Date: Thu, 28 Aug 2025 15:49:53 +0800 Subject: [PATCH 470/931] ARM: dts: aspeed: harma: add mp5990 Add support for the HSC MP5990 device on the Harma platform. This change updates the device tree to include the MP5990 HSC (Hot Swap Controller), allowing proper configuration and integration with the platform. Signed-off-by: Peter Yin Link: https://patch.msgid.link/20250828074955.542711-4-peteryin.openbmc@gmail.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts index 81278a7702de..23eaf47a38e8 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts @@ -520,6 +520,10 @@ imux28: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; + power-sensor@20 { + compatible = "mps,mp5990"; + reg = <0x20>; + }; power-monitor@61 { compatible = "isil,isl69260"; reg = <0x61>; From 2c01536aae3e3591f27b945e85fc6b92f789580c Mon Sep 17 00:00:00 2001 From: Leo Wang Date: Wed, 13 Aug 2025 18:04:13 +0800 Subject: [PATCH 471/931] dt-bindings: arm: aspeed: add Meta Clemente board Document the new compatibles used on Meta Clemente. Acked-by: Conor Dooley Signed-off-by: Leo Wang Link: https://patch.msgid.link/20250813-add-support-for-meta-clemente-bmc-v11-1-8970d41f88b0@fii-foxconn.com Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index b3c9d3310d57..aedefca7cf4a 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -82,6 +82,7 @@ properties: - asus,x4tf-bmc - facebook,bletchley-bmc - facebook,catalina-bmc + - facebook,clemente-bmc - facebook,cloudripper-bmc - facebook,darwin-bmc - facebook,elbert-bmc From 92a56149f5e60c31d31c7b6060e5270f1cf1b3be Mon Sep 17 00:00:00 2001 From: Leo Wang Date: Wed, 13 Aug 2025 18:04:14 +0800 Subject: [PATCH 472/931] ARM: dts: aspeed: Add NCSI3 and NCSI4 pinctrl nodes Add pinctrl nodes for NCSI3 and NCSI4 to the AST2600 pinctrl description, enabling support for RMII3 and RMII4 interfaces. Signed-off-by: Leo Wang Link: https://patch.msgid.link/20250813-add-support-for-meta-clemente-bmc-v11-2-8970d41f88b0@fii-foxconn.com [arj: Remove 'clemente' from commit subject] Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi index 289668f051eb..e87c4b58994a 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi @@ -412,6 +412,16 @@ pinctrl_mdio4_default: mdio4_default { groups = "MDIO4"; }; + pinctrl_ncsi3_default: ncsi3_default { + function = "RMII3"; + groups = "NCSI3"; + }; + + pinctrl_ncsi4_default: ncsi4_default { + function = "RMII4"; + groups = "NCSI4"; + }; + pinctrl_ncts1_default: ncts1_default { function = "NCTS1"; groups = "NCTS1"; From 20ae14024aab6c9b5468e6c056abf397a6fa4aa1 Mon Sep 17 00:00:00 2001 From: Leo Wang Date: Wed, 13 Aug 2025 18:04:15 +0800 Subject: [PATCH 473/931] ARM: dts: aspeed: clemente: add Meta Clemente BMC Add linux device tree entry for Meta Clemente compute-tray BMC using AST2600 SoC. Signed-off-by: Leo Wang Link: https://patch.msgid.link/20250813-add-support-for-meta-clemente-bmc-v11-3-8970d41f88b0@fii-foxconn.com [arj: Fix node ordering and whitespace] Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-facebook-clemente.dts | 1283 +++++++++++++++++ 2 files changed, 1284 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index 8062c685f7e8..0f0b5b707654 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -19,6 +19,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-delta-ahe50dc.dtb \ aspeed-bmc-facebook-bletchley.dtb \ aspeed-bmc-facebook-catalina.dtb \ + aspeed-bmc-facebook-clemente.dtb \ aspeed-bmc-facebook-cmm.dtb \ aspeed-bmc-facebook-darwin.dtb \ aspeed-bmc-facebook-elbert.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts new file mode 100644 index 000000000000..ecef44d89977 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts @@ -0,0 +1,1283 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2021 Facebook Inc. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include +#include +#include +#include + +/ { + model = "Facebook Clemente BMC"; + compatible = "facebook,clemente-bmc", "aspeed,ast2600"; + + aliases { + serial0 = &uart1; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + i2c16 = &i2c1mux0ch0; + i2c17 = &i2c1mux0ch1; + i2c18 = &i2c1mux0ch2; + i2c19 = &i2c1mux0ch3; + i2c20 = &i2c1mux0ch4; + i2c21 = &i2c1mux0ch5; + i2c22 = &i2c1mux0ch6; + i2c23 = &i2c1mux0ch7; + i2c24 = &i2c0mux0ch0; + i2c25 = &i2c0mux0ch1; + i2c26 = &i2c0mux0ch2; + i2c27 = &i2c0mux0ch3; + i2c28 = &i2c0mux1ch0; + i2c29 = &i2c0mux1ch1; + i2c30 = &i2c0mux1ch2; + i2c31 = &i2c0mux1ch3; + i2c32 = &i2c0mux2ch0; + i2c33 = &i2c0mux2ch1; + i2c34 = &i2c0mux2ch2; + i2c35 = &i2c0mux2ch3; + i2c36 = &i2c0mux3ch0; + i2c37 = &i2c0mux3ch1; + i2c38 = &i2c0mux3ch2; + i2c39 = &i2c0mux3ch3; + i2c40 = &i2c0mux4ch0; + i2c41 = &i2c0mux4ch1; + i2c42 = &i2c0mux4ch2; + i2c43 = &i2c0mux4ch3; + i2c44 = &i2c0mux5ch0; + i2c45 = &i2c0mux5ch1; + i2c46 = &i2c0mux5ch2; + i2c47 = &i2c0mux5ch3; + i2c48 = &i2c0mux0ch1mux0ch0; + i2c49 = &i2c0mux0ch1mux0ch1; + i2c50 = &i2c0mux0ch1mux0ch2; + i2c51 = &i2c0mux0ch1mux0ch3; + i2c52 = &i2c0mux3ch1mux0ch0; + i2c53 = &i2c0mux3ch1mux0ch1; + i2c54 = &i2c0mux3ch1mux0ch2; + i2c55 = &i2c0mux3ch1mux0ch3; + }; + + chosen { + stdout-path = "serial4:57600n8"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "bmc_heartbeat_amber"; + gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "fp_id_amber"; + default-state = "off"; + gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "bmc_ready_noled"; + gpios = <&gpio0 ASPEED_GPIO(B, 3) (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>; + }; + + led-3 { + label = "bmc_ready_cpld_noled"; + gpios = <&gpio0 ASPEED_GPIO(P, 5) (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + p1v8_bmc_aux: regulator-p1v8-bmc-aux { + compatible = "regulator-fixed"; + regulator-name = "p1v8_bmc_aux"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + p2v5_bmc_aux: regulator-p2v5-bmc-aux { + compatible = "regulator-fixed"; + regulator-name = "p2v5_bmc_aux"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@b3e00000 { + compatible = "ramoops"; + reg = <0xbb000000 0x200000>; /* 16 * (4 * 0x8000) */ + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x8000>; + pmsg-size = <0x8000>; + max-reason = <3>; + }; + }; + + spi1_gpio: spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; +}; + +&adc0 { + vref-supply = <&p1v8_bmc_aux>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + vref-supply = <&p2v5_bmc_aux>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc10_default>; +}; + +&ehci0 { + status = "okay"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; + }; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "BATTERY_DETECT","PRSNT1_HPM_SCM_N", + "BMC_I2C1_FPGA_ALERT_L","BMC_READY", + "IOEXP_INT_L","FM_ID_LED", + "","", + /*C0-C7*/ "BMC_GPIOC0","","","", + "PMBUS_REQ_N","PSU_FW_UPDATE_REQ_N", + "","BMC_I2C_SSIF_ALERT_L", + /*D0-D7*/ "","","","","BMC_GPIOD4","","","", + /*E0-E7*/ "BMC_GPIOE0","BMC_GPIOE1","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","", + "FM_DEBUG_PORT_PRSNT_N","FM_BMC_DBP_PRESENT_N", + /*H0-H7*/ "PWR_BRAKE_L","RUN_POWER_EN", + "SHDN_FORCE_L","SHDN_REQ_L", + "","","","", + /*I0-I7*/ "","","","", + "","FLASH_WP_STATUS", + "FM_PDB_HEALTH_N","RUN_POWER_PG", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "PCIE_EP_RST_EN","BMC_FRU_WP", + "SCM_HPM_STBY_RST_N","SCM_HPM_STBY_EN", + "STBY_POWER_PG_3V3","TH500_SHDN_OK_L","","", + /*N0-N7*/ "LED_POSTCODE_0","LED_POSTCODE_1", + "LED_POSTCODE_2","LED_POSTCODE_3", + "LED_POSTCODE_4","LED_POSTCODE_5", + "LED_POSTCODE_6","LED_POSTCODE_7", + /*O0-O7*/ "HMC_I2C3_FPGA_ALERT_L","FPGA_READY_HMC", + "CHASSIS_AC_LOSS_L","BSM_PRSNT_R_N", + "PSU_SMB_ALERT_L","FM_TPM_PRSNT_0_N", + "","USBDBG_IPMI_EN_L", + /*P0-P7*/ "PWR_BTN_BMC_N","IPEX_CABLE_PRSNT_L", + "ID_RST_BTN_BMC_N","RST_BMC_RSTBTN_OUT_N", + "host0-ready","BMC_READY_CPLD","BMC_GPIOP6","BMC_HEARTBEAT_N", + /*Q0-Q7*/ "IRQ_PCH_TPM_SPI_N","USB_OC0_REAR_R_N", + "UART_MUX_SEL","I2C_MUX_RESET_L", + "RSVD_NV_PLT_DETECT","SPI_TPM_INT_L", + "CPU_JTAG_MUX_SELECT","THERM_BB_OVERT_L", + /*R0-R7*/ "THERM_BB_WARN_L","SPI_BMC_FPGA_INT_L", + "CPU_BOOT_DONE","PMBUS_GNT_L", + "CHASSIS_PWR_BRK_L","PCIE_WAKE_L", + "PDB_THERM_OVERT_L","HMC_I2C2_FPGA_ALERT_L", + /*S0-S7*/ "","","SYS_BMC_PWRBTN_R_N","FM_TPM_PRSNT_1_N", + "FM_BMC_DEBUG_SW_N","UID_LED_N", + "SYS_FAULT_LED_N","RUN_POWER_FAULT_L", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "L2_RST_REQ_OUT_L","L0L1_RST_REQ_OUT_L", + "BMC_ID_BEEP_SEL","BMC_I2C0_FPGA_ALERT_L", + "SMB_BMC_TMP_ALERT","PWR_LED_N", + "SYS_RST_OUT_L","IRQ_TPM_SPI_N", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","RST_BMC_SELF_HW", + "FM_FLASH_LATCH_N","BMC_EMMC_RST_N", + "BMC_GPIOY4","BMC_GPIOY5","","", + /*Z0-Z7*/ "","","","","","","BMC_GPIOZ6","BMC_GPIOZ7"; +}; + +&gpio1 { + gpio-line-names = + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B3*/ "","","","", + /*18B4-18B7*/ "FM_BOARD_BMC_REV_ID0","FM_BOARD_BMC_REV_ID1","FM_BOARD_BMC_REV_ID2","", + /*18C0-18C7*/ "","","PI_BMC_BIOS_ROM_IRQ0_N","","","","","", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "","","","AC_PWR_BMC_BTN_N","","","",""; +}; + +&i2c0 { + status = "okay"; + + i2c-mux@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c0mux0ch0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c0mux0ch1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + // HDD FRU EEPROM + eeprom@56 { + compatible = "atmel,24c128"; + reg = <0x56>; + }; + + // E1.S Backplane + i2c0mux0ch1mux0: i2c-mux@74 { + compatible = "nxp,pca9546"; + reg = <0x74>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c0mux0ch1mux0ch0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c0mux0ch1mux0ch1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c0mux0ch1mux0ch2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c0mux0ch1mux0ch3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + i2c0mux0ch2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c0mux0ch3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + i2c-mux@72 { + compatible = "nxp,pca9546"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c0mux1ch0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c0mux1ch1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + // IO Mezz 0 IOEXP + io_expander7: gpio@20 { + compatible = "nxp,pca9535"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "RST_CX7_0", + "RST_CX7_1", + "CX0_SSD0_PRSNT_L", + "CX1_SSD1_PRSNT_L", + "CX_BOOT_CMPLT_CX0", + "CX_BOOT_CMPLT_CX1", + "CX_TWARN_CX0_L", + "CX_TWARN_CX1_L", + "CX_OVT_SHDN_CX0", + "CX_OVT_SHDN_CX1", + "FNP_L_CX0", + "FNP_L_CX1", + "", + "MCU_GPIO", + "MCU_RST_N", + "MCU_RECOVERY_N"; + }; + + // IO Mezz 0 FRU EEPROM + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + // OSFP 0 FRU EEPROM + eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + }; + }; + + i2c0mux1ch2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c0mux1ch3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + i2c-mux@73 { + compatible = "nxp,pca9546"; + reg = <0x73>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c0mux2ch0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + // IOB0 NIC0 TEMP + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + }; + + i2c0mux2ch1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c0mux2ch2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c0mux2ch3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + // IOB0 NIC1 TEMP + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + }; + }; + + i2c-mux@75 { + compatible = "nxp,pca9546"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c0mux3ch0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c0mux3ch1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + // E1.S Backplane HDD FRU EEPROM + eeprom@56 { + compatible = "atmel,24c128"; + reg = <0x56>; + }; + + // E1.S Backplane MUX + i2c0mux3ch1mux0: i2c-mux@74 { + compatible = "nxp,pca9546"; + reg = <0x74>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c0mux3ch1mux0ch0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c0mux3ch1mux0ch1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c0mux3ch1mux0ch2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c0mux3ch1mux0ch3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + i2c0mux3ch2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c0mux3ch3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + i2c-mux@76 { + compatible = "nxp,pca9546"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c0mux4ch0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c0mux4ch1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + // IO Mezz 1 IOEXP + io_expander8: gpio@21 { + compatible = "nxp,pca9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "SEC_RST_CX7_0", + "SEC_RST_CX7_1", + "SEC_CX0_SSD0_PRSNT_L", + "SEC_CX1_SSD1_PRSNT_L", + "SEC_CX_BOOT_CMPLT_CX0", + "SEC_CX_BOOT_CMPLT_CX1", + "SEC_CX_TWARN_CX0_L", + "SEC_CX_TWARN_CX1_L", + "SEC_CX_OVT_SHDN_CX0", + "SEC_CX_OVT_SHDN_CX1", + "SEC_FNP_L_CX0", + "SEC_FNP_L_CX1", + "", + "SEC_MCU_GPIO", + "SEC_MCU_RST_N", + "SEC_MCU_RECOVERY_N"; + }; + + // IO Mezz 1 FRU EEPROM + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + // OSFP 1 FRU EEPROM + eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + }; + }; + + i2c0mux4ch2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c0mux4ch3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + i2c-mux@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c0mux5ch0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + // IOB1 NIC0 TEMP + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + }; + + i2c0mux5ch1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c0mux5ch2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c0mux5ch3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + // IOB1 NIC1 TEMP + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + // PDB + power-monitor@12 { + compatible = "ti,lm5066i"; + reg = <0x12>; + }; + + // PDB + power-monitor@14 { + compatible = "ti,lm5066i"; + reg = <0x14>; + }; + + // Module 0 + fanctl0: fan-controller@20{ + compatible = "maxim,max31790"; + reg = <0x20>; + }; + + // Module 0 + fanctl1: fan-controller@23{ + compatible = "maxim,max31790"; + reg = <0x23>; + }; + + // Module 1 + fanctl2: fan-controller@2c{ + compatible = "maxim,max31790"; + reg = <0x2c>; + }; + + // Module 1 + fanctl3: fan-controller@2f{ + compatible = "maxim,max31790"; + reg = <0x2f>; + }; + + // Module 0 Leak Sensor + adc@34 { + compatible = "maxim,max1363"; + reg = <0x34>; + }; + + // Module 1 Leak Sensor + adc@35 { + compatible = "maxim,max1363"; + reg = <0x35>; + }; + + // PDB TEMP SENSOR + temperature-sensor@4e { + compatible = "ti,tmp1075"; + reg = <0x4e>; + }; + + // PDB FRU EEPROM + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + + // PDB + vrm@60 { + compatible = "renesas,raa228004"; + reg = <0x60>; + }; + + // PDB + vrm@61 { + compatible = "renesas,raa228004"; + reg = <0x61>; + }; + + // Interposer + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + i2c1mux0ch0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + i2c1mux0ch1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + i2c1mux0ch2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + i2c1mux0ch3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + i2c1mux0ch4: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + + i2c1mux0ch5: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + + // Interposer TEMP SENSOR + temperature-sensor@4f { + compatible = "ti,tmp75"; + reg = <0x4f>; + }; + + // Interposer FRU EEPROM + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; + }; + + i2c1mux0ch6: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + + // Interposer IOEXP + io_expander5: gpio@27 { + compatible = "nxp,pca9554"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "JTAG_MUX_SEL", + "IOX_BMC_RESET", + "RTC_CLR_L", + "RTC_U77_ALRT_N", + "", + "PSU_ALERT_N", + "", + "RST_P12V_STBY_N"; + }; + }; + + i2c1mux0ch7: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + + // FIO TEMP SENSOR + temperature-sensor@4b { + compatible = "ti,tmp75"; + reg = <0x4b>; + }; + + // FIO FRU EEPROM + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + // Module 0, Expander @0x20 + io_expander0: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "FPGA_THERM_OVERT_L-I", + "FPGA_READY_BMC-I", + "HMC_BMC_DETECT-O", + "HMC_PGOOD-O", + "", + "BMC_STBY_CYCLE-O", + "FPGA_EROT_FATAL_ERROR_L-I", + "WP_HW_EXT_CTRL_L-O", + "EROT_FPGA_RST_L-O", + "FPGA_EROT_RECOVERY_L-O", + "BMC_EROT_FPGA_SPI_MUX_SEL-O", + "USB2_HUB_RST_L-O", + "", + "SGPIO_EN_L-O", + "B2B_IOEXP_INT_L-I", + "I2C_BUS_MUX_RESET_L-O"; + }; + + // Module 1, Expander @0x21 + io_expander1: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "SEC_FPGA_THERM_OVERT_L", + "SEC_FPGA_READY_BMC", + "SEC_HMC_BMC_DETECT", + "SEC_HMC_PGOOD", + "", + "SEC_BMC_SELF_POWER_CYCLE", + "SEC_SEC_FPGA_EROT_FATAL_ERROR_L", + "SEC_WP_HW_EXT_CTRL_L", + "SEC_EROT_FPGA_RST_L", + "SEC_FPGA_EROT_RECOVERY_L", + "SEC_BMC_EROT_FPGA_SPI_MUX_SEL", + "SEC_USB2_HUB_RST_L", + "", + "SEC_SGPIO_EN_L", + "SEC_IOB_IOEXP_INT_L", + "SEC_I2C_BUS_MUX_RESET_L"; + }; + + // HMC Expander @0x27 + io_expander2: gpio@27 { + compatible = "nxp,pca9555"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "HMC_PRSNT_L-I", + "HMC_READY-I", + "HMC_EROT_FATAL_ERROR_L-I", + "I2C_MUX_SEL-O", + "HMC_EROT_SPI_MUX_SEL-O", + "HMC_EROT_RECOVERY_L-O", + "HMC_EROT_RST_L-O", + "GLOBAL_WP_HMC-O", + "FPGA_RST_L-O", + "USB2_HUB_RST-O", + "CPU_UART_MUX_SEL-O", + "", + "", + "", + "", + ""; + }; + + // Module 0 Aux EEPROM + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + // Module 1 Aux EEPROM + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + io_expander3: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "RTC_MUX_SEL", + "PCI_MUX_SEL", + "TPM_MUX_SEL", + "FAN_MUX-SEL", + "SGMII_MUX_SEL", + "DP_MUX_SEL", + "UPHY3_USB_SEL", + "NCSI_MUX_SEL", + "BMC_PHY_RST", + "RTC_CLR_L", + "BMC_12V_CTRL", + "PS_RUN_IO0_PG", + "", + "", + "", + ""; + }; + + rtc@6f { + compatible = "nuvoton,nct3018y"; + reg = <0x6f>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; + // SCM TEMP SENSOR BOARD + temperature-sensor@4b { + compatible = "national,lm75b"; + reg = <0x4b>; + }; + + // SCM CPLD IOEXP + io_expander4: gpio@4f { + compatible = "nxp,pca9555"; + reg = <0x4f>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "stby_power_en_cpld", + "stby_power_gd_cpld", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; + }; + + // SCM FRU EEPROM + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + // BSM FRU EEPROM + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + }; +}; + +&i2c10 { + status = "okay"; + multi-master; + mctp-controller; + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + // OCP NIC0 TEMP + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + + // OCP NIC0 FRU EEPROM + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c11 { + status = "okay"; + + ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + }; +}; + +&i2c12 { + status = "okay"; + multi-master; + + // HPM 1 FRU EEPROM + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + // CBC 2 FRU + eeprom@54 { + compatible = "atmel,24c02"; + reg = <0x54>; + }; + // CBC 3 FRU + eeprom@55 { + compatible = "atmel,24c02"; + reg = <0x55>; + }; +}; + +&i2c13 { + status = "okay"; + multi-master; + + // HPM FRU EEPROM + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + // CBC 0 FRU + eeprom@54 { + compatible = "atmel,24c02"; + reg = <0x54>; + }; + + // CBC 1 FRU + eeprom@55 { + compatible = "atmel,24c02"; + reg = <0x55>; + }; + + // HMC FRU EEPROM + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + }; +}; + +&i2c14 { + status = "okay"; + + // PDB CPLD IOEXP 0x10 + io_expander9: gpio@10 { + compatible = "nxp,pca9555"; + interrupt-parent = <&gpio0>; + interrupts = ; + reg = <0x10>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "wSequence_Latch_State_N", + "wP12V_N1N2_RUNTIME_FLT_N", + "wP12V_FAN_RUNTIME_FLT_N", + "wP12V_AUX_RUNTIME_FLT_N", + "wHost_PERST_SEQPWR_FLT_N", + "wP12V_N1N2_SEQPWR_FLT_N", + "wP12V_FAN_SEQPWR_FLT_N", + "wP12V_AUX_SEQPWR_FLT_N", + "wP12V_RUNTIME_FLT_NIC1_N", + "wAUX_RUNTIME_FLT_NIC1_N", + "wP12V_SEQPWR_FLT_NIC1_N", + "wAUX_SEQPWR_FLT_NIC1_N", + "wP12V_RUNTIME_FLT_NIC0_N", + "wAUX_RUNTIME_FLT_NIC0_N", + "wP12V_SEQPWR_FLT_NIC0_N", + "wAUX_SEQPWR_FLT_NIC0_N"; + }; + + // PDB CPLD IOEXP 0x11 + io_expander10: gpio@11 { + compatible = "nxp,pca9555"; + interrupt-parent = <&gpio0>; + interrupts = ; + reg = <0x11>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "FM_P12V_NIC1_FLTB_R_N", + "FM_P3V3_NIC1_FAULT_R_N", + "FM_P12V_NIC0_FLTB_R_N", + "FM_P3V3_NIC0_FAULT_R_N", + "P48V_HS2_FAULT_N_PLD", + "P48V_HS1_FAULT_N_PLD", + "P12V_AUX_FAN_OC_PLD_N", + "P12V_AUX_FAN_FAULT_PLD_N", + "", + "", + "", + "", + "", + "FM_SYS_THROTTLE_N", + "OCP_V3_2_PWRBRK_FROM_HOST_ISO_PLD_N", + "OCP_SFF_PWRBRK_FROM_HOST_ISO_PLD_N"; + }; + + // PDB CPLD IOEXP 0x12 + io_expander11: gpio@12 { + compatible = "nxp,pca9555"; + interrupt-parent = <&gpio0>; + interrupts = ; + reg = <0x12>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "P12V_AUX_PSU_SMB_ALERT_R_L", + "P12V_SCM_SENSE_ALERT_R_N", + "P12V_AUX_NIC1_SENSE_ALERT_R_N", + "P12V_AUX_NIC0_SENSE_ALERT_R_N", + "NODEB_PSU_SMB_ALERT_R_L", + "NODEA_PSU_SMB_ALERT_R_L", + "P12V_AUX_FAN_ALERT_PLD_N", + "P52V_SENSE_ALERT_PLD_N", + "PRSNT_RJ45_FIO_N_R", + "FM_MAIN_PWREN_RMC_EN_ISO_R", + "CHASSIS3_LEAK_Q_N_PLD", + "CHASSIS2_LEAK_Q_N_PLD", + "CHASSIS1_LEAK_Q_N_PLD", + "CHASSIS0_LEAK_Q_N_PLD", + "", + "SMB_RJ45_FIO_TMP_ALERT"; + }; + + // PDB CPLD IOEXP 0x13 + io_expander12: gpio@13 { + compatible = "nxp,pca9555"; + interrupt-parent = <&gpio0>; + interrupts = ; + reg = <0x13>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "FAN_7_PRESENT_N", + "FAN_6_PRESENT_N", + "FAN_5_PRESENT_N", + "FAN_4_PRESENT_N", + "FAN_3_PRESENT_N", + "FAN_2_PRESENT_N", + "FAN_1_PRESENT_N", + "FAN_0_PRESENT_N", + "HP_LVC3_OCP_V3_2_PRSNT2_PLD_N", + "HP_LVC3_OCP_V3_1_PRSNT2_PLD_N", + "PRSNT_HDDBD_POWER_CABLE_N", + "PRSNT_OSFP0_POWER_CABLE_N", + "PRSNT_CHASSIS3_LEAK_CABLE_R_N", + "PRSNT_CHASSIS2_LEAK_CABLE_R_N", + "PRSNT_CHASSIS1_LEAK_CABLE_R_N", + "PRSNT_CHASSIS0_LEAK_CABLE_R_N"; + }; + + // PDB CPLD IOEXP 0x14 + io_expander13: gpio@14 { + compatible = "nxp,pca9555"; + reg = <0x14>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "rmc_en_dc_pwr_on", + "", + "", + "", + "", + "", + "", + "", + "leak_config_0", + "leak_config_1", + "leak_config_2", + "leak_config_3", + "mfg_led_test_mode_l", + "small_leak_err_inj", + "large_leak_err_inj", + ""; + }; +}; + +&i2c15 { + status = "okay"; + multi-master; + mctp-controller; + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + // OCP NIC1 TEMP + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + + // OCP NIC1 FRU EEPROM + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; +}; + +&mac2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ncsi3_default>; + use-ncsi; +}; + +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ncsi4_default>; + use-ncsi; +}; + +&udma { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&wdt1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; +}; From fe42f567c387964ca5660d66242d30837fc488a2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:17:44 +0200 Subject: [PATCH 474/931] ARM: dts: aspeed: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' or '{' characters. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250819131743.86905-2-krzysztof.kozlowski@linaro.org Signed-off-by: Andrew Jeffery --- .../dts/aspeed/aspeed-bmc-ampere-mtjefferson.dts | 2 +- .../boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts | 4 ++-- .../boot/dts/aspeed/aspeed-bmc-facebook-harma.dts | 4 ++-- .../boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts | 12 ++++++------ .../dts/aspeed/aspeed-bmc-facebook-santabarbara.dts | 2 +- .../dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 12 ++++++------ arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts | 2 +- arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-sbp1.dts | 8 ++++---- .../boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts | 2 +- .../dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts | 2 +- arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts | 2 +- arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi | 2 +- 12 files changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjefferson.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjefferson.dts index c435359a4bd9..53b4372f1a08 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjefferson.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtjefferson.dts @@ -243,7 +243,7 @@ temperature-sensor@49 { compatible = "ti,tmp75"; reg = <0x49>; }; - temperature-sensor@4a{ + temperature-sensor@4a { compatible = "ti,tmp75"; reg = <0x4a>; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts index 8d786510167f..14dd0ab64130 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts @@ -526,11 +526,11 @@ fan-3 { tach-ch = /bits/ 8 <0x03>; }; }; - fanctl0: fan-controller@21{ + fanctl0: fan-controller@21 { compatible = "maxim,max31790"; reg = <0x21>; }; - fanctl1: fan-controller@27{ + fanctl1: fan-controller@27 { compatible = "maxim,max31790"; reg = <0x27>; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts index 23eaf47a38e8..1ed79f41ef0b 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts @@ -183,7 +183,7 @@ &kcs3 { &i2c0 { status = "okay"; - pwm@5e{ + pwm@5e { compatible = "max31790"; reg = <0x5e>; #address-cells = <1>; @@ -257,7 +257,7 @@ eeprom@50 { &i2c2 { status = "okay"; - pwm@5e{ + pwm@5e { compatible = "max31790"; reg = <0x5e>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts index ef96b17becb2..399e244bcd79 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts @@ -312,7 +312,7 @@ eeprom@50 { reg = <0x50>; }; - pwm@5e{ + pwm@5e { compatible = "max31790"; reg = <0x5e>; #address-cells = <1>; @@ -435,7 +435,7 @@ eeprom@50 { reg = <0x50>; }; - pwm@5e{ + pwm@5e { compatible = "max31790"; reg = <0x5e>; #address-cells = <1>; @@ -558,7 +558,7 @@ eeprom@50 { reg = <0x50>; }; - pwm@5e{ + pwm@5e { compatible = "max31790"; reg = <0x5e>; #address-cells = <1>; @@ -681,7 +681,7 @@ eeprom@50 { reg = <0x50>; }; - pwm@5e{ + pwm@5e { compatible = "max31790"; reg = <0x5e>; #address-cells = <1>; @@ -804,7 +804,7 @@ eeprom@50 { reg = <0x50>; }; - pwm@5e{ + pwm@5e { compatible = "max31790"; reg = <0x5e>; #address-cells = <1>; @@ -926,7 +926,7 @@ eeprom@50 { reg = <0x50>; }; - pwm@5e{ + pwm@5e { compatible = "max31790"; reg = <0x5e>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts index ee93a971c500..72c84f31bdf6 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts @@ -233,7 +233,7 @@ gpio@20 { "FM_NIC_PPS_IN_S0_R","FM_NIC_PPS_IN_S1_R"; }; - fan-controller@21{ + fan-controller@21 { compatible = "maxim,max31790"; reg = <0x21>; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts index aae789854c52..60b98d602e80 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts @@ -1186,19 +1186,19 @@ adc@1f { ti,mode = /bits/ 8 <1>; }; - pwm@20{ + pwm@20 { compatible = "maxim,max31790"; reg = <0x20>; }; - gpio@22{ + gpio@22 { compatible = "ti,tca6424"; reg = <0x22>; gpio-controller; #gpio-cells = <2>; }; - pwm@2f{ + pwm@2f { compatible = "maxim,max31790"; reg = <0x2f>; }; @@ -1234,19 +1234,19 @@ adc@1f { ti,mode = /bits/ 8 <1>; }; - pwm@20{ + pwm@20 { compatible = "maxim,max31790"; reg = <0x20>; }; - gpio@22{ + gpio@22 { compatible = "ti,tca6424"; reg = <0x22>; gpio-controller; #gpio-cells = <2>; }; - pwm@2f{ + pwm@2f { compatible = "maxim,max31790"; reg = <0x2f>; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts index 757421bc3605..c5fb5d410001 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts @@ -263,7 +263,7 @@ eeprom@51 { reg = <0x51>; }; - tca_pres1: tca9554@20{ + tca_pres1: tca9554@20 { compatible = "ti,tca9554"; reg = <0x20>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-sbp1.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-sbp1.dts index 8d98be3d5f2e..dbadba8eb698 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-sbp1.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-sbp1.dts @@ -3778,10 +3778,10 @@ smb_svc_pex_rssd01_16: pinctrl@20 { pinctrl-0 = <&U65200_pins>; pinctrl-names = "default"; U65200_pins: cfg-pins { - pins = "gp60", "gp61", "gp62", - "gp63", "gp64", "gp65", "gp66", - "gp67", "gp70", "gp71", "gp72", - "gp73", "gp74", "gp75", "gp76", "gp77"; + pins = "gp60", "gp61", "gp62", "gp63", "gp64", + "gp65", "gp66", "gp67", "gp70", "gp71", + "gp72", "gp73", "gp74", "gp75", "gp76", + "gp77"; function = "gpio"; input-enable; bias-pull-up; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts index de61eac54585..c63f0b43090e 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts @@ -151,7 +151,7 @@ &mac1 { pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; }; -&adc{ +&adc { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_adc0_default diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts index 72dafebc080d..4de38613b0ea 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts @@ -282,7 +282,7 @@ &uhci { }; &sgpiom0 { - status="okay"; + status = "okay"; ngpios = <128>; gpio-line-names = "","", diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts index 627c91f178e6..af3a9d39d277 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts @@ -64,7 +64,7 @@ event-checkstop { linux,code = ; }; - event-pcie-e2b-present{ + event-pcie-e2b-present { label = "pcie-e2b-present"; gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi index 16815eede710..8c953e3a1d41 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman.dtsi @@ -30,7 +30,7 @@ video_engine_memory: jpegbuffer { reusable; }; - ramoops@9eff0000{ + ramoops@9eff0000 { compatible = "ramoops"; reg = <0x9eff0000 0x10000>; record-size = <0x2000>; From 61a913644a8c5b6c8bd9da09f78f88e50edfaeb1 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 15 Aug 2025 18:08:39 -0500 Subject: [PATCH 475/931] ARM: dts: aspeed: Fix/add I2C device vendor prefixes The ASpeed DTS files have various I2C devices with missing or incorrect vendor prefixes in their compatible strings. This hasn't really mattered and doesn't impact ABI compatibility as I2C devices get matched with their vendor prefix stripped. With this, the "maxim,max31790" nodes now validate and have some warnings. Remove the spurious "#address-cells" and "#size-cells" properties to fix the warnings. Signed-off-by: Rob Herring (Arm) [arj: Fix conflicts with fe42f567c387 ("ARM: dts: aspeed: Minor whitespace cleanup")] Signed-off-by: Andrew Jeffery --- .../aspeed-bmc-arm-stardragon4800-rep2.dts | 2 +- .../dts/aspeed/aspeed-bmc-facebook-harma.dts | 8 ++----- .../aspeed/aspeed-bmc-facebook-minerva.dts | 24 +++++-------------- .../aspeed/aspeed-bmc-facebook-tiogapass.dts | 2 +- .../dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts | 2 +- .../dts/aspeed/aspeed-bmc-opp-palmetto.dts | 2 +- .../boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts | 4 ++-- 7 files changed, 14 insertions(+), 30 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-arm-stardragon4800-rep2.dts index 9605ccade155..b550a48f48f0 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-arm-stardragon4800-rep2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-arm-stardragon4800-rep2.dts @@ -171,7 +171,7 @@ eeprom@50 { reg = <0x50>; }; dps650ab@58 { - compatible = "dps650ab"; + compatible = "delta,dps650ab"; reg = <0x58>; }; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts index 1ed79f41ef0b..b733efe31e8d 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts @@ -184,10 +184,8 @@ &i2c0 { status = "okay"; pwm@5e { - compatible = "max31790"; + compatible = "maxim,max31790"; reg = <0x5e>; - #address-cells = <1>; - #size-cells = <0>; }; power-sensor@40 { @@ -258,10 +256,8 @@ &i2c2 { status = "okay"; pwm@5e { - compatible = "max31790"; + compatible = "maxim,max31790"; reg = <0x5e>; - #address-cells = <1>; - #size-cells = <0>; }; power-sensor@40 { diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts index 399e244bcd79..eb8d4b95596c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minerva.dts @@ -313,10 +313,8 @@ eeprom@50 { }; pwm@5e { - compatible = "max31790"; + compatible = "maxim,max31790"; reg = <0x5e>; - #address-cells = <1>; - #size-cells = <0>; }; power-sensor@40 { @@ -436,10 +434,8 @@ eeprom@50 { }; pwm@5e { - compatible = "max31790"; + compatible = "maxim,max31790"; reg = <0x5e>; - #address-cells = <1>; - #size-cells = <0>; }; power-sensor@40 { @@ -559,10 +555,8 @@ eeprom@50 { }; pwm@5e { - compatible = "max31790"; + compatible = "maxim,max31790"; reg = <0x5e>; - #address-cells = <1>; - #size-cells = <0>; }; power-sensor@40 { @@ -682,10 +676,8 @@ eeprom@50 { }; pwm@5e { - compatible = "max31790"; + compatible = "maxim,max31790"; reg = <0x5e>; - #address-cells = <1>; - #size-cells = <0>; }; power-sensor@40 { @@ -805,10 +797,8 @@ eeprom@50 { }; pwm@5e { - compatible = "max31790"; + compatible = "maxim,max31790"; reg = <0x5e>; - #address-cells = <1>; - #size-cells = <0>; }; power-sensor@40 { @@ -927,10 +917,8 @@ eeprom@50 { }; pwm@5e { - compatible = "max31790"; + compatible = "maxim,max31790"; reg = <0x5e>; - #address-cells = <1>; - #size-cells = <0>; }; power-sensor@40 { diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts index 704ee684e0fb..5d4c7d979f1e 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts @@ -508,7 +508,7 @@ &i2c7 { status = "okay"; //HSC, AirMax Conn A adm1278@45 { - compatible = "adm1275"; + compatible = "adi,adm1275"; reg = <0x45>; shunt-resistor-micro-ohms = <250>; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts index c63f0b43090e..fdcf4492fb4e 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts @@ -211,7 +211,7 @@ &i2c1 { status = "okay"; bus-frequency = <90000>; HotSwap@10 { - compatible = "adm1272"; + compatible = "adi,adm1272"; reg = <0x10>; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts index a1d3e046d4a2..7953059a6c67 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-palmetto.dts @@ -151,7 +151,7 @@ eeprom@50 { }; rtc@68 { - compatible = "dallas,ds3231"; + compatible = "maxim,ds3231"; reg = <0x68>; }; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts index fd361cf073c2..86451227847b 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts @@ -509,7 +509,7 @@ U197_PCA9546_CH1: i2c@1 { reg = <1>; cpu0_pvccin@60 { - compatible = "isil,raa229004"; + compatible = "renesas,raa229004"; reg = <0x60>; }; @@ -530,7 +530,7 @@ U197_PCA9546_CH2: i2c@2 { reg = <2>; cpu1_pvccin@72 { - compatible = "isil,raa229004"; + compatible = "renesas,raa229004"; reg = <0x72>; }; From 0586ac82e62b0fdbaa811e4da6e04be157b495f3 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 29 Aug 2025 16:13:17 -0500 Subject: [PATCH 476/931] ARM: dts: aspeed: Drop "sdhci" compatibles The "sdhci" compatible is not documented nor very useful on its own given the various features and quirks of SDHCI implementations. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250829211318.1335862-1-robh@kernel.org Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index acdb6ae74b27..61983feb2a4e 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -662,7 +662,7 @@ sdc: sdc@1e740000 { status = "disabled"; sdhci0: sdhci@1e740100 { - compatible = "aspeed,ast2600-sdhci", "sdhci"; + compatible = "aspeed,ast2600-sdhci"; reg = <0x100 0x100>; interrupts = ; sdhci,auto-cmd12; @@ -671,7 +671,7 @@ sdhci0: sdhci@1e740100 { }; sdhci1: sdhci@1e740200 { - compatible = "aspeed,ast2600-sdhci", "sdhci"; + compatible = "aspeed,ast2600-sdhci"; reg = <0x200 0x100>; interrupts = ; sdhci,auto-cmd12; From 0b367e60c73c05721cf2156fe8fe077320115ffd Mon Sep 17 00:00:00 2001 From: Jihed Chaibi Date: Sun, 31 Aug 2025 00:51:15 +0200 Subject: [PATCH 477/931] ARM: dts: stm32: stm32mp151c-plyaqm: Use correct dai-format property The stm32-i2s binding inherits from the standard audio-graph-port schema for its 'port' subnode, audio-graph-port requires the use of the 'dai-format' property. The stm32mp151c-plyaqm dts file was using the non-standard name 'format'. Correct the property name to 'dai-format' to fix the dtbs_check validation error. Fixes: 9365fa46be358 ("ARM: dts: stm32: Add Plymovent AQM devicetree") Signed-off-by: Jihed Chaibi Link: https://lore.kernel.org/r/20250830225115.303663-1-jihed.chaibi.dev@gmail.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts b/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts index 39a3211c6133..55fe916740d7 100644 --- a/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts +++ b/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts @@ -239,7 +239,7 @@ &i2s1 { i2s1_port: port { i2s1_endpoint: endpoint { - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; remote-endpoint = <&codec_endpoint>; }; From fc5aa426280e7d98113d8674187464813f712a82 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:17:08 +0200 Subject: [PATCH 478/931] ARM: dts: stm32: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' or '{' characters. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250819131707.86657-3-krzysztof.kozlowski@linaro.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts | 2 +- arch/arm/boot/dts/st/stm32mp157c-ultra-fly-sbc.dts | 2 +- arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts b/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts index 55fe916740d7..5d219a448763 100644 --- a/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts +++ b/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts @@ -255,7 +255,7 @@ &m4_rproc { /delete-property/ st,syscfg-holdboot; resets = <&scmi_reset RST_SCMI_MCU>, <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; - reset-names = "mcu_rst", "hold_boot"; + reset-names = "mcu_rst", "hold_boot"; }; &mdma1 { diff --git a/arch/arm/boot/dts/st/stm32mp157c-ultra-fly-sbc.dts b/arch/arm/boot/dts/st/stm32mp157c-ultra-fly-sbc.dts index ac42d462d449..2531f4bc8ca4 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ultra-fly-sbc.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ultra-fly-sbc.dts @@ -92,7 +92,7 @@ gpu_reserved: gpu@f8000000 { leds: leds { compatible = "gpio-leds"; - led0{ + led0 { label = "buzzer"; gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi index be0c355d3105..154698f87b0e 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi @@ -262,7 +262,7 @@ &i2c5 { status = "okay"; usbhub: usbhub@2c { - compatible ="microchip,usb2514b"; + compatible = "microchip,usb2514b"; reg = <0x2c>; vdd-supply = <&v3v3>; reset-gpios = <&gpiob 6 GPIO_ACTIVE_LOW>; From 3f2265078156c97941e08a1a3274d76e78128585 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:17:09 +0200 Subject: [PATCH 479/931] arm64: dts: stm32: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250819131707.86657-4-krzysztof.kozlowski@linaro.org Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 836b1958ce65..4ff334563599 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -100,7 +100,7 @@ &combophy { }; &csi { - vdd-supply = <&scmi_vddcore>; + vdd-supply = <&scmi_vddcore>; vdda18-supply = <&scmi_v1v8>; status = "okay"; ports { @@ -151,7 +151,7 @@ phy0_eth2: ethernet-phy@1 { reg = <1>; reset-assert-us = <10000>; reset-deassert-us = <300>; - reset-gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; }; }; }; From 4952fb7f53d4c9f007147ffb250c04ed40c959f7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 18 Aug 2025 16:37:31 +0200 Subject: [PATCH 480/931] ARM: dts: stm32: Drop redundant status=okay Device nodes are enabled by default, so remove confusing or duplicated enabling of few nodes. No practical impact, verified with dtx_diff. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Marek Vasut Link: https://lore.kernel.org/r/20250818143730.244379-2-krzysztof.kozlowski@linaro.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 2 -- arch/arm/boot/dts/st/stm32mp157f-dk2.dts | 2 -- arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi | 1 - arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi | 3 --- arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi | 2 -- 5 files changed, 10 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts index 1b34fbe10b4f..78165c7865e1 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -45,7 +45,6 @@ panel@0 { reg = <0>; reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; power-supply = <&v3v3>; - status = "okay"; port { panel_in: endpoint { @@ -71,7 +70,6 @@ touchscreen@38 { interrupt-parent = <&gpiof>; touchscreen-size-x = <480>; touchscreen-size-y = <800>; - status = "okay"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts b/arch/arm/boot/dts/st/stm32mp157f-dk2.dts index 43375c4d62a3..8fa61e54d026 100644 --- a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2.dts @@ -51,7 +51,6 @@ panel@0 { reg = <0>; reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; power-supply = <&scmi_v3v3>; - status = "okay"; port { panel_in: endpoint { @@ -77,7 +76,6 @@ touchscreen@38 { interrupt-parent = <&gpiof>; touchscreen-size-x = <480>; touchscreen-size-y = <800>; - status = "okay"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi index abe2dfe70636..52c4e69597a4 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-drc02.dtsi @@ -62,7 +62,6 @@ &i2c2 { pinctrl-0 = <&i2c2_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; - status = "okay"; /* spare dmas for other usage */ /delete-property/dmas; /delete-property/dma-names; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi index 0fb4e55843b9..5c77202ee196 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi @@ -20,7 +20,6 @@ display_bl: display-bl { default-brightness-level = <8>; enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; power-supply = <®_panel_bl>; - status = "okay"; }; gpio-keys-polled { @@ -135,7 +134,6 @@ sound { "MIC_IN", "Microphone Jack", "Microphone Jack", "Mic Bias"; dais = <&sai2a_port &sai2b_port>; - status = "okay"; }; }; @@ -150,7 +148,6 @@ &i2c2 { /* Header X22 */ pinctrl-0 = <&i2c2_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; - status = "okay"; /* spare dmas for other usage */ /delete-property/dmas; /delete-property/dma-names; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi index 142d4a8731f8..4cc633683c6b 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi @@ -269,7 +269,6 @@ pmic: stpmic@33 { interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; - status = "okay"; regulators { compatible = "st,stpmic1-regulators"; @@ -388,7 +387,6 @@ onkey { interrupts = , ; interrupt-names = "onkey-falling", "onkey-rising"; power-off-time-sec = <10>; - status = "okay"; }; watchdog { From 045bf0f825cf8dd53468e70fa494b06aa17e2d33 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:16:42 +0200 Subject: [PATCH 481/931] arm64: dts: exynos8895: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' character. Link: https://lore.kernel.org/r/20250819131641.86520-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi index 51e9c9c4b166..16903ce63a32 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi @@ -202,7 +202,7 @@ bt_btwake: bt-btwake-pins { }; bt_en: bt-en-pins { - samsung,pins ="gpj1-7"; + samsung,pins = "gpj1-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-con-pdn = ; From fa36b8209ba600828646287ad14e527074b48247 Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Tue, 10 Jun 2025 17:23:07 +0200 Subject: [PATCH 482/931] ARM: dts: stm32: Add pinmux for CM4 leds pins The GPIO H7 on boards stm32mp15xx-dkx and the GPIO D8 on boards stm32mp15xx-ed1 are used by the coprocessor Cortex-M4. Linux running on Cortex-A should not use the GPIO and should left it available for the coprocessor. Add two pinmux groups, one for each families of boards, setting the GPIO function as Reserved (RSVD). Signed-off-by: Antonio Borneo Link: https://lore.kernel.org/r/20250610152309.299438-4-antonio.borneo@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi index 40605ea85ee1..835b034d0aa7 100644 --- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -1304,6 +1304,20 @@ pins { }; }; + /omit-if-no-ref/ + m4_leds_orange_pins_a: m4-leds-orange-0 { + pins { + pinmux = ; + }; + }; + + /omit-if-no-ref/ + m4_leds_orange_pins_b: m4-leds-orange-1 { + pins { + pinmux = ; + }; + }; + /omit-if-no-ref/ mco1_pins_a: mco1-0 { pins { From 0d9673e19c37b2ff334811ee6b7bfc50f21bf95e Mon Sep 17 00:00:00 2001 From: Antonio Borneo Date: Tue, 10 Jun 2025 17:23:08 +0200 Subject: [PATCH 483/931] ARM: dts: stm32: Add leds for CM4 on stm32mp15xx-ed1 and stm32mp15xx-dkx Add to the node m4_rproc the pinctrl property corresponding to the orange LED. The GPIO is reserved for the coprocessor Cortex-M4 and will be ignored by Linux. Signed-off-by: Antonio Borneo Link: https://lore.kernel.org/r/20250610152309.299438-5-antonio.borneo@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 2 ++ arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts index 9cf5ed111b52..f6c478dbd041 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts @@ -328,6 +328,8 @@ &m4_rproc { <&vdev0vring1>, <&vdev0buffer>; mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; mbox-names = "vq0", "vq1", "shutdown", "detach"; + pinctrl-names = "default"; + pinctrl-0 = <&m4_leds_orange_pins_b>; interrupt-parent = <&exti>; interrupts = <68 1>; status = "okay"; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi index 46692d8f566a..8cea6facd27b 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -479,6 +479,8 @@ &m4_rproc { <&vdev0vring1>, <&vdev0buffer>; mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; mbox-names = "vq0", "vq1", "shutdown", "detach"; + pinctrl-names = "default"; + pinctrl-0 = <&m4_leds_orange_pins_a>; interrupt-parent = <&exti>; interrupts = <68 1>; status = "okay"; From b3646b905272e14d8bf9173e14b79d4d625cb84d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= Date: Fri, 11 Jul 2025 09:41:22 +0200 Subject: [PATCH 484/931] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp13 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the hdp devicetree node for stm32mp13 SoC family. Keep the node disabled as HDP needs the pinctrl SoC configuration to be able to output its mux output signal outside of the SoC, on the SoC pad. This configuration is provided in the board dtsi file through 'pinctrl-*' properties as well as HDP mux configuration. Thus, if needed, HDP should be enabled in board dtsi file. Signed-off-by: Clément Le Goffic Link: https://lore.kernel.org/r/20250711-hdp-upstream-v7-4-faeecf7aaee1@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp131.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index ace9495b9b06..151ffd0bdef9 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -954,6 +954,13 @@ dts: thermal@50028000 { status = "disabled"; }; + hdp: pinctrl@5002a000 { + compatible = "st,stm32mp131-hdp"; + reg = <0x5002a000 0x400>; + clocks = <&rcc HDP>; + status = "disabled"; + }; + mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; From 62ba9a86eac78e21a13b71c36a006d8c99d87270 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= Date: Fri, 11 Jul 2025 09:41:23 +0200 Subject: [PATCH 485/931] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp15 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the hdp devicetree node for stm32mp15 SoC family Keep the node disabled as HDP needs the pinctrl SoC configuration to be able to output its mux output signal outside of the SoC, on the SoC pad. This configuration is provided in the board dtsi file through 'pinctrl-*' properties as well as HDP mux configuration. Thus, if needed, HDP should be enabled in board dtsi file. Signed-off-by: Clément Le Goffic Link: https://lore.kernel.org/r/20250711-hdp-upstream-v7-5-faeecf7aaee1@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp151.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index 0daa8ffe2ff5..b1b568dfd126 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -270,6 +270,13 @@ dts: thermal@50028000 { status = "disabled"; }; + hdp: pinctrl@5002a000 { + compatible = "st,stm32mp151-hdp"; + reg = <0x5002a000 0x400>; + clocks = <&rcc HDP>; + status = "disabled"; + }; + mdma1: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; From 278b6cabf18bd804f956b98a2f1068717acdbfe3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:34:08 +0200 Subject: [PATCH 486/931] arm64: dts: broadcom: bcm2712: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: bcm2712.dtsi:494.4-497.31: Warning (interrupt_map): /axi/pcie@1000110000:interrupt-map: Missing property '#address-cells' in node /soc@107c000000/interrupt-controller@7fff9000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250822133407.312505-2-krzysztof.kozlowski@linaro.org Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 0a9212d3106f..940f1c483198 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -270,6 +270,7 @@ gicv2: interrupt-controller@7fff9000 { <0x7fffc000 0x2000>, <0x7fffe000 0x2000>; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; }; From 279ea197d9bd56d2a4d0058a55fd0eb88626ad6a Mon Sep 17 00:00:00 2001 From: Taishi Shimizu Date: Sun, 13 Jul 2025 16:18:24 +0900 Subject: [PATCH 487/931] dt-bindings: arm: bcm: Add support for Buffalo WXR-1750DHP Add Buffalo WXR-1750DHP under BCM4708 based boards. Signed-off-by: Taishi Shimizu Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250713071826.726682-2-s.taishi14142@gmail.com Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index d925e7a3b5ef..f47d74a5b0b6 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -25,6 +25,7 @@ properties: - enum: - asus,rt-ac56u - asus,rt-ac68u + - buffalo,wxr-1750dhp - buffalo,wzr-1166dhp - buffalo,wzr-1166dhp2 - buffalo,wzr-1750dhp From 484199a02aca6c7ea99501eec2fc73cb808e209d Mon Sep 17 00:00:00 2001 From: Taishi Shimizu Date: Sun, 13 Jul 2025 16:18:25 +0900 Subject: [PATCH 488/931] ARM: dts: BCM5301X: Add support for Buffalo WXR-1750DHP Add initial device tree support for the Buffalo WXR-1750DHP, a consumer Wi-Fi router based on the Broadcom BCM4708A0 SoC. Hardware specifications: * Processor: Broadcom BCM4708A0 dual-core @ 800 MHz * RAM: DDR3 256 MB * Ethernet Switch: Broadcom BCM53011 integrated via SRAB * NAND Flash: 128 MB (8-bit ECC) * SPI Flash: None * Ports: 4 LAN Ports, 1 WAN Port * USB: 1x USB 3.0 Type-A port Signed-off-by: Taishi Shimizu Link: https://lore.kernel.org/r/20250713071826.726682-3-s.taishi14142@gmail.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/broadcom/Makefile | 1 + .../broadcom/bcm4708-buffalo-wxr-1750dhp.dts | 138 ++++++++++++++++++ 2 files changed, 139 insertions(+) create mode 100644 arch/arm/boot/dts/broadcom/bcm4708-buffalo-wxr-1750dhp.dts diff --git a/arch/arm/boot/dts/broadcom/Makefile b/arch/arm/boot/dts/broadcom/Makefile index 71062ff9adbe..2552e11b5e31 100644 --- a/arch/arm/boot/dts/broadcom/Makefile +++ b/arch/arm/boot/dts/broadcom/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4708-asus-rt-ac56u.dtb \ bcm4708-asus-rt-ac68u.dtb \ + bcm4708-buffalo-wxr-1750dhp.dtb \ bcm4708-buffalo-wzr-1750dhp.dtb \ bcm4708-buffalo-wzr-1166dhp.dtb \ bcm4708-buffalo-wzr-1166dhp2.dtb \ diff --git a/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wxr-1750dhp.dts b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wxr-1750dhp.dts new file mode 100644 index 000000000000..f5c95c9a712e --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm4708-buffalo-wxr-1750dhp.dts @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Author: Taishi Shimizu + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" +#include + +/ { + compatible = "buffalo,wxr-1750dhp", "brcm,bcm4708"; + model = "Buffalo WXR-1750DHP"; + + memory@0 { + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + device_type = "memory"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-aoss { + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + label = "AOSS"; + linux,code = ; + }; + + /* GPIO 3 is a switch button with AUTO / MANUAL. */ + button-manual { + gpios = <&chipcommon 3 GPIO_ACTIVE_HIGH>; + label = "MANUAL"; + linux,code = ; + linux,input-type = ; + }; + + button-restart { + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + label = "Reset"; + linux,code = ; + }; + + /* GPIO 8 and 9 are a tri-state switch button with + * ROUTER / AP / WB. + */ + button-router { + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + label = "ROUTER"; + linux,code = ; + linux,input-type = ; + }; + + button-wb { + gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; + label = "WB"; + linux,code = ; + linux,input-type = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-internet { + color = ; + function = "internet"; + gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + }; + + led-power0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + }; + + led-power1 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + + led-router0 { + color = ; + function = "router"; + gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; + }; + + led-router1 { + color = ; + function = "router"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + }; + + led-usb { + color = ; + function = LED_FUNCTION_USB; + gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "usbport"; + trigger-sources = <&xhci_port1 &ehci_port1 &ohci_port1>; + }; + }; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + label = "wan"; + }; + + port@1 { + label = "lan4"; + }; + + port@2 { + label = "lan3"; + }; + + port@3 { + label = "lan2"; + }; + + port@4 { + label = "lan1"; + }; + }; +}; + +&usb3 { + vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_HIGH>; +}; + +&usb3_phy { + status = "okay"; +}; From 0f084b221e2c5ba16eca85b3d2497f9486bd0329 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 2 Sep 2025 20:26:58 +0800 Subject: [PATCH 489/931] riscv: dts: spacemit: uart: remove sec_uart1 device node sec_uart1 is not available from Linux, and no clock is implemented in CCF framework, thus 'make dtbs_check' will pop up this warning message: serial@f0612000: 'clock-names' is a required property Removing the node from device tree to silence the DT check warning. Link: https://lore.kernel.org/r/20250902-02-k1-uart-clock-v2-1-f146918d44f6@gentoo.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 19dc9c94e5b5..66b33a9110cc 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -797,16 +797,7 @@ uart9: serial@d4017800 { status = "disabled"; }; - sec_uart1: serial@f0612000 { - compatible = "spacemit,k1-uart", - "intel,xscale-uart"; - reg = <0x0 0xf0612000 0x0 0x100>; - interrupts = <43>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "reserved"; /* for TEE usage */ - }; + /* sec_uart1: 0xf0612000, not available from Linux */ }; multimedia-bus { From 965e37ec0f8d4926809526e5ee0916774376f007 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 20 Aug 2025 21:06:51 +0100 Subject: [PATCH 490/931] arm64: dts: renesas: r9a09g087: Add pinctrl node Add pinctrl node to RZ/N2H ("R9A09G087") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250820200659.2048755-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index 7dcaee711486..ecbb7b93aed2 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -216,6 +216,19 @@ cpg: clock-controller@80280000 { #power-domain-cells = <0>; }; + pinctrl: pinctrl@802c0000 { + compatible = "renesas,r9a09g087-pinctrl"; + reg = <0 0x802c0000 0 0x10000>, + <0 0x812c0000 0 0x10000>, + <0 0x802b0000 0 0x10000>; + reg-names = "nsr", "srs", "srn"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 280>; + power-domains = <&cpg>; + }; + gic: interrupt-controller@83000000 { compatible = "arm,gic-v3"; reg = <0x0 0x83000000 0 0x40000>, From 77aae5255c6d2ef4981f7fcedf35333466abcb06 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 20 Aug 2025 21:06:52 +0100 Subject: [PATCH 491/931] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add user LEDs Add USER LED0-LED8, which are available on RZ/T2H EVK. In addition, move the header file inclusion into the common rzt2h-n2h-evk-common.dtsi, so that both RZ/T2H and RZ/N2H EVK DTS/I files share the same set of bindings. This avoids duplication and keeps the board files consistent. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250820200659.2048755-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 77 ++++++++++++++++++- .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 4 + 2 files changed, 79 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 51ea295b3241..a7b91c96f311 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -7,14 +7,87 @@ /dts-v1/; -#include - #include "r9a09g077m44.dtsi" #include "rzt2h-n2h-evk-common.dtsi" / { model = "Renesas RZ/T2H EVK Board based on r9a09g077m44"; compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077"; + + leds { + compatible = "gpio-leds"; + + led-0 { + /* SW8-9: ON, SW8-10: OFF */ + gpios = <&pinctrl RZT2H_GPIO(23, 1) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <0>; + }; + + led-1 { + /* SW5-1: OFF, SW5-2: ON */ + gpios = <&pinctrl RZT2H_GPIO(32, 2) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + }; + + led-2 { + gpios = <&pinctrl RZT2H_GPIO(6, 7) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + }; + + led-3 { + /* SW2-3: OFF */ + gpios = <&pinctrl RZT2H_GPIO(8, 5) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <3>; + }; + + led-4 { + /* SW8-3: ON, SW8-4: OFF */ + gpios = <&pinctrl RZT2H_GPIO(18, 0) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <4>; + }; + + led-5 { + /* SW8-1: ON, SW8-2: OFF */ + gpios = <&pinctrl RZT2H_GPIO(18, 1) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <5>; + }; + + led-6 { + /* SW5-9: OFF, SW5-10: ON */ + gpios = <&pinctrl RZT2H_GPIO(22, 7) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <6>; + }; + + led-7 { + /* SW5-7: OFF, SW5-8: ON */ + gpios = <&pinctrl RZT2H_GPIO(23, 0) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <7>; + }; + + led-8 { + /* SW7-5: OFF, SW7-6: ON */ + gpios = <&pinctrl RZT2H_GPIO(23, 5) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <8>; + }; + }; }; &i2c0 { diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 263509cc3dc4..28330ff63b2b 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -5,6 +5,10 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ +#include +#include +#include + / { aliases { i2c0 = &i2c0; From 23cb8eb3286d7f2df646eaf7cbcb63b0f1f2ee45 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 20 Aug 2025 21:06:53 +0100 Subject: [PATCH 492/931] arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add user LEDs Add USER LED3-LED11, which are available on RZ/N2H EVK. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250820200659.2048755-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index d6ba14a26f03..fb2651c4c338 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -13,4 +13,95 @@ / { model = "Renesas RZ/N2H EVK Board based on r9a09g087m44"; compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087"; + + leds { + compatible = "gpio-leds"; + + led-3 { + /* DSW18-7: ON, DSW18-8: OFF */ + gpios = <&pinctrl RZT2H_GPIO(31, 6) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <4>; + }; + + led-4 { + /* DSW18-9: ON, DSW18-10: OFF */ + gpios = <&pinctrl RZT2H_GPIO(18, 1) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <5>; + }; + + led-5 { + /* DSW18-1: ON, DSW18-2: OFF */ + gpios = <&pinctrl RZT2H_GPIO(22, 7) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <6>; + }; + + led-6 { + /* DSW18-3: ON, DSW18-4: OFF */ + gpios = <&pinctrl RZT2H_GPIO(23, 0) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <7>; + }; + + led-7 { + /* + * DSW18-5: ON, DSW18-6: OFF + * DSW19-3: OFF, DSW19-4: ON + */ + gpios = <&pinctrl RZT2H_GPIO(14, 3) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <8>; + }; + + led-8 { + /* + * USER_LED0 + * DSW15-8: OFF, DSW15-9: OFF, DSW15-10: ON + */ + gpios = <&pinctrl RZT2H_GPIO(14, 6) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <0>; + }; + + led-9 { + /* + * USER_LED1 + * DSW15-5: OFF, DSW15-6: ON + */ + gpios = <&pinctrl RZT2H_GPIO(14, 7) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + }; + + led-10 { + /* + * USER_LED2 + * DSW17-3: OFF, DSW17-4: ON + */ + gpios = <&pinctrl RZT2H_GPIO(2, 7) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + }; + + led-11 { + /* + * USER_LED3 + * DSW17-1: OFF, DSW17-2: ON + */ + gpios = <&pinctrl RZT2H_GPIO(3, 0) GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <3>; + }; + }; }; From 1366c160df036d5596240ea4b36b88afe2cd0d2a Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 20 Aug 2025 21:06:54 +0100 Subject: [PATCH 493/931] arm64: dts: renesas: rzt2h-n2h-evk-common: Add pinctrl for SCI0 node Add pinctrl for SCI0 node. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250820200659.2048755-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzt2h-n2h-evk-common.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 28330ff63b2b..06300f806685 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -25,6 +25,23 @@ &extal_clk { clock-frequency = <25000000>; }; +&pinctrl { + /* + * SCI0 Pin Configuration: + * ------------------------ + * Signal | Pin | RZ/T2H (SW4) | RZ/N2H (DSW9) + * -----------|---------|--------------|--------------- + * SCI0_RXD | P27_4 | 5: ON, 6: OFF| 1: ON, 2: OFF + * SCI0_TXD | P27_5 | 7: ON, 8: OFF| 3: ON, 4: OFF + */ + sci0_pins: sci0-pins { + pinmux = , + ; + }; +}; + &sci0 { + pinctrl-0 = <&sci0_pins>; + pinctrl-names = "default"; status = "okay"; }; From fc14be9667ee06301c3fff578357c8d78749bb13 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 20 Aug 2025 21:06:55 +0100 Subject: [PATCH 494/931] arm64: dts: renesas: r9a09g087m44-rzt2h-evk: Enable I2C0 and I2C1 support Enable I2C0 and I2C1 on the RZ/N2H evaluation board. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250820200659.2048755-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index fb2651c4c338..a068661fc442 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -10,6 +10,14 @@ #include "r9a09g087m44.dtsi" #include "rzt2h-n2h-evk-common.dtsi" +/* + * I2C0 and LED8/9 share the same pins use the below + * macro to choose (and set approopriate DIP switches). + */ +#define I2C0 1 +#define LED8 (!I2C0) +#define LED9 (!I2C0) + / { model = "Renesas RZ/N2H EVK Board based on r9a09g087m44"; compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087"; @@ -60,6 +68,7 @@ led-7 { function-enumerator = <8>; }; +#if LED8 led-8 { /* * USER_LED0 @@ -70,7 +79,9 @@ led-8 { function = LED_FUNCTION_DEBUG; function-enumerator = <0>; }; +#endif +#if LED9 led-9 { /* * USER_LED1 @@ -81,6 +92,7 @@ led-9 { function = LED_FUNCTION_DEBUG; function-enumerator = <1>; }; +#endif led-10 { /* @@ -105,3 +117,47 @@ led-11 { }; }; }; + +#if I2C0 +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; +#endif + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&pinctrl { + /* + * I2C0 Pin Configuration: + * ------------------------ + * Signal | Pin | DSW15 + * -------|---------|-------------- + * SCL | P14_6 | 8: OFF, 9: ON, 10: OFF + * SDA | P14_7 | 5: ON, 6: OFF + */ + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + /* + * I2C1 Pin Configuration: + * ------------------------ + * Signal | Pin | DSW7 + * -------|---------|-------------- + * SCL | P03_3 | 1: ON, 2: OFF + * SDA | P03_4 | 3: ON, 4: OFF + */ + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; +}; From 0176c9e82e1080952828b3badcdccf51206a8189 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 20 Aug 2025 21:06:56 +0100 Subject: [PATCH 495/931] arm64: dts: renesas: rzt2h-n2h-evk-common: Enable EEPROM on I2C0 Enable support for the R1EX24016 EEPROM connected to I2C0 on the Renesas RZ/T2H and RZ/N2H Evaluation Kits. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250820200659.2048755-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 06300f806685..1b7e16ffe6b6 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -25,6 +25,14 @@ &extal_clk { clock-frequency = <25000000>; }; +&i2c0 { + eeprom: eeprom@50 { + compatible = "renesas,r1ex24016", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + &pinctrl { /* * SCI0 Pin Configuration: From 59b4c260582a74e641c973d016725e5dca32f300 Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Thu, 17 Jul 2025 17:38:38 +0800 Subject: [PATCH 496/931] arm64: dts: amlogic: C3: Add RTC controller node Add the RTC controller node for C3 SoC family. Signed-off-by: Xianwei Zhao Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250717-rtc-c3-node-v1-2-4f9ae059b8e6@amlogic.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi index cb9ea3ca6ee0..b81bffac7732 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -53,6 +53,13 @@ xtal: xtal-clk { #clock-cells = <0>; }; + xtal_32k: xtal-clk-32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xtal_32k"; + #clock-cells = <0>; + }; + sm: secure-monitor { compatible = "amlogic,meson-gxbb-sm"; @@ -967,6 +974,15 @@ nand: nand-controller@8d000 { clock-names = "core", "device"; status = "disabled"; }; + + rtc@9a000 { + compatible = "amlogic,c3-rtc", + "amlogic,a5-rtc"; + reg = <0x0 0x9a000 0x0 0x38>; + interrupts = ; + clocks = <&xtal_32k>, <&clkc_periphs CLKID_SYS_RTC>; + clock-names = "osc", "sys"; + }; }; ethmac: ethernet@fdc00000 { From d7fc05da8ba28d22fb9bd79d9308f928fcb81c19 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Mon, 25 Aug 2025 12:21:41 +0530 Subject: [PATCH 497/931] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC As per S905 and S905X datasheet add missing cache information to the Amlogic GXBB and GXL SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20250825065240.22577-2-linux.amoon@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 27 +++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 7d99ca44e660..c1d8e81d95cb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -95,6 +95,12 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; #cooling-cells = <2>; @@ -105,6 +111,12 @@ cpu1: cpu@1 { compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; #cooling-cells = <2>; @@ -115,6 +127,12 @@ cpu2: cpu@2 { compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; #cooling-cells = <2>; @@ -125,6 +143,12 @@ cpu3: cpu@3 { compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; #cooling-cells = <2>; @@ -134,6 +158,9 @@ l2: l2-cache0 { compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; From fd7b48b1f91e1830e22e73744e7525af24d8ae25 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Mon, 25 Aug 2025 12:21:42 +0530 Subject: [PATCH 498/931] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC As per S905X3 datasheet add missing cache information to the Amlogic SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache. - Each Cortex-A55 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 256KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20250825065240.22577-3-linux.amoon@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 966ebb19cc55..e5db8ce94062 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -55,6 +55,12 @@ cpu0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -64,6 +70,12 @@ cpu1: cpu@1 { compatible = "arm,cortex-a55"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -73,6 +85,12 @@ cpu2: cpu@2 { compatible = "arm,cortex-a55"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -82,6 +100,12 @@ cpu3: cpu@3 { compatible = "arm,cortex-a55"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -90,6 +114,9 @@ l2: l2-cache0 { compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x40000>; /* L2. 256 KB */ + cache-line-size = <64>; + cache-sets = <256>; }; }; From a4428e52babdb682f47f99b0b816e227e51a3835 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Mon, 25 Aug 2025 12:21:43 +0530 Subject: [PATCH 499/931] arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS As per the S905X2 datasheet add missing cache information to the Amlogic G12A SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20250825065240.22577-4-linux.amoon@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 +++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index deee61dbe074..1321ad95923d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -17,6 +17,12 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -26,6 +32,12 @@ cpu1: cpu@1 { compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -35,6 +47,12 @@ cpu2: cpu@2 { compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -44,6 +62,12 @@ cpu3: cpu@3 { compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -52,6 +76,9 @@ l2: l2-cache0 { compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; From 3b6ad2a433672f4ed9e1c90e4ae6b94683d1f1a2 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Mon, 25 Aug 2025 12:21:44 +0530 Subject: [PATCH 500/931] arm64: dts: amlogic: Add cache information to the Amlogic AXG SoCS As per the AXG datasheet add missing cache information to the Amlogic AXG SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20250825065240.22577-5-linux.amoon@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 2df143aa77ce..04fb130ac7c6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -83,6 +83,12 @@ cpu1: cpu@1 { compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; dynamic-power-coefficient = <140>; @@ -94,6 +100,12 @@ cpu2: cpu@2 { compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; dynamic-power-coefficient = <140>; @@ -105,6 +117,12 @@ cpu3: cpu@3 { compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; dynamic-power-coefficient = <140>; @@ -115,6 +133,9 @@ l2: l2-cache0 { compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; From fe2c12bc0a8f9e5db87bfbf231658eadef4cdd47 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Mon, 25 Aug 2025 12:21:45 +0530 Subject: [PATCH 501/931] arm64: dts: amlogic: Add cache information to the Amlogic GXM SoCS As per the GXM datasheet add missing cache information to the Amlogic GXM SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20250825065240.22577-6-linux.amoon@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi index 411cc312fc62..514c9bea6423 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi @@ -64,6 +64,12 @@ cpu4: cpu@100 { reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; @@ -75,6 +81,12 @@ cpu5: cpu@101 { reg = <0x0 0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; @@ -86,6 +98,12 @@ cpu6: cpu@102 { reg = <0x0 0x102>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; @@ -97,6 +115,12 @@ cpu7: cpu@103 { reg = <0x0 0x103>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; From 2d97773212f8516b2fe3177077b1ecf7b67a4e09 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Mon, 25 Aug 2025 12:21:46 +0530 Subject: [PATCH 502/931] arm64: dts: amlogic: Add cache information to the Amlogic A1 SoC As per the A1 datasheet add missing cache information to the Amlogic A1 SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20250825065240.22577-7-linux.amoon@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index f7f25a10f409..27b68ed85c4c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -27,6 +27,12 @@ cpu0: cpu@0 { compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -36,6 +42,12 @@ cpu1: cpu@1 { compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -44,6 +56,9 @@ l2: l2-cache0 { compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; From 57273dc063d5a80e8cebc20878369099992be01a Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Mon, 25 Aug 2025 12:21:47 +0530 Subject: [PATCH 503/931] arm64: dts: amlogic: Add cache information to the Amlogic A4 SoC As per A4 datasheet add missing cache information to the Amlogic A4 SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20250825065240.22577-8-linux.amoon@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi | 37 +++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi index 563bc2e662fa..fce45933fa28 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi @@ -17,6 +17,13 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -24,6 +31,13 @@ cpu1: cpu@1 { compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; cpu2: cpu@2 { @@ -31,6 +45,13 @@ cpu2: cpu@2 { compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; cpu3: cpu@3 { @@ -38,6 +59,22 @@ cpu3: cpu@3 { compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; From 6d4ab38a0a21c82076105e4cc37087ef92253c7b Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Mon, 25 Aug 2025 12:21:48 +0530 Subject: [PATCH 504/931] arm64: dts: amlogic: Add cache information to the Amlogic C3 SoC As per C3 datasheet add missing cache information to the Amlogic C3 SoC. - Each Cortex-A53 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20250825065240.22577-9-linux.amoon@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 23 +++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi index b81bffac7732..e8529e8c4b15 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -23,6 +23,13 @@ cpu0: cpu@0 { compatible = "arm,cortex-a35"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -30,6 +37,22 @@ cpu1: cpu@1 { compatible = "arm,cortex-a35"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x7d000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; From 494c362fa1633bba127045ace8f0eea0b277af28 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Mon, 25 Aug 2025 12:21:49 +0530 Subject: [PATCH 505/931] arm64: dts: amlogic: Add cache information to the Amlogic S7 SoC As per S7 datasheet add missing cache information to the Amlogic S7 SoC. ARM Cortex-A55 CPU uses unified L2 cache. - Each Cortex-A55 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 256KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20250825065240.22577-10-linux.amoon@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi | 36 +++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi index 260918b37b9a..d262c0b66e4b 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi @@ -18,6 +18,13 @@ cpu0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; cpu1: cpu@100 { @@ -25,6 +32,13 @@ cpu1: cpu@100 { compatible = "arm,cortex-a55"; reg = <0x0 0x100>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; cpu2: cpu@200 { @@ -32,6 +46,13 @@ cpu2: cpu@200 { compatible = "arm,cortex-a55"; reg = <0x0 0x200>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; cpu3: cpu@300 { @@ -39,8 +60,23 @@ cpu3: cpu@300 { compatible = "arm,cortex-a55"; reg = <0x0 0x300>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2>; }; + l2: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x40000>; /* L2. 256 KB */ + cache-line-size = <64>; + cache-sets = <512>; + }; }; timer { From e7f85e6c155aed3e10e698dd05bd04b2d52edb59 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Mon, 25 Aug 2025 12:21:50 +0530 Subject: [PATCH 506/931] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC As per S922X datasheet add missing cache information to the Amlogic S922X SoC. - Each Cortex-A53 core has 32 KB of instruction cache and 32 KB of L1 data cache available. - Each Cortex-A73 core has 64 KB of L1 instruction cache and 64 KB of L1 data cache available. - The little (A53) cluster has 256 KB of unified L2 cache available. - The big (A73) cluster has 1 MB of unified L2 cache available. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20250825065240.22577-11-linux.amoon@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 62 ++++++++++++++++++--- 1 file changed, 55 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi index 86e6ceb31d5e..f04efa828256 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -49,7 +49,13 @@ cpu0: cpu@0 { reg = <0x0 0x0>; enable-method = "psci"; capacity-dmips-mhz = <592>; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; #cooling-cells = <2>; }; @@ -59,7 +65,13 @@ cpu1: cpu@1 { reg = <0x0 0x1>; enable-method = "psci"; capacity-dmips-mhz = <592>; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; #cooling-cells = <2>; }; @@ -69,7 +81,13 @@ cpu100: cpu@100 { reg = <0x0 0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; #cooling-cells = <2>; }; @@ -79,7 +97,13 @@ cpu101: cpu@101 { reg = <0x0 0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; #cooling-cells = <2>; }; @@ -89,7 +113,13 @@ cpu102: cpu@102 { reg = <0x0 0x102>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; + d-cache-line-size = <64>; + d-cache-size = <0x10000>; + d-cache-sets = <64>; + i-cache-line-size = <64>; + i-cache-size = <0x10000>; + i-cache-sets = <64>; + next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; }; @@ -99,14 +129,32 @@ cpu103: cpu@103 { reg = <0x0 0x103>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - next-level-cache = <&l2>; + d-cache-line-size = <64>; + d-cache-size = <0x10000>; + d-cache-sets = <64>; + i-cache-line-size = <64>; + i-cache-size = <0x10000>; + i-cache-sets = <64>; + next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; }; - l2: l2-cache0 { + l2_cache_l: l2-cache-cluster0 { compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x40000>; /* L2. 256 KB */ + cache-line-size = <64>; + cache-sets = <512>; + }; + + l2_cache_b: l2-cache-cluster1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; /* L2. 1MB */ + cache-line-size = <64>; + cache-sets = <512>; }; }; }; From e97fdb9b8a0f8bd349de48815694f8a7200e3d62 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Mon, 25 Aug 2025 12:21:51 +0530 Subject: [PATCH 507/931] arm64: dts: amlogic: Add cache information to the Amlogic T7 SoC As per T7 datasheet add missing cache information to the Amlogic T7 SoC. - Each Cortex-A53 core has 32 KB of instruction cache and 32 KB of L1 data cache available. - Each Cortex-A73 core has 64 KB of L1 instruction cache and 64 KB of L1 data cache available. - The little (A53) cluster has 256 KB of unified L2 cache available. - The big (A73) cluster has 1 MB of unified L2 cache available. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20250825065240.22577-12-linux.amoon@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 74 +++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi index ec743cad57db..6510068bcff9 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -53,6 +53,13 @@ cpu100: cpu@100 { compatible = "arm,cortex-a53"; reg = <0x0 0x100>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; }; cpu101: cpu@101 { @@ -60,6 +67,13 @@ cpu101: cpu@101 { compatible = "arm,cortex-a53"; reg = <0x0 0x101>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; }; cpu102: cpu@102 { @@ -67,6 +81,13 @@ cpu102: cpu@102 { compatible = "arm,cortex-a53"; reg = <0x0 0x102>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; }; cpu103: cpu@103 { @@ -74,6 +95,13 @@ cpu103: cpu@103 { compatible = "arm,cortex-a53"; reg = <0x0 0x103>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l2_cache_l>; }; cpu0: cpu@0 { @@ -81,6 +109,13 @@ cpu0: cpu@0 { compatible = "arm,cortex-a73"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <64>; + d-cache-size = <0x10000>; + d-cache-sets = <64>; + i-cache-line-size = <64>; + i-cache-size = <0x10000>; + i-cache-sets = <64>; + next-level-cache = <&l2_cache_b>; }; cpu1: cpu@1 { @@ -88,6 +123,13 @@ cpu1: cpu@1 { compatible = "arm,cortex-a73"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <64>; + d-cache-size = <0x10000>; + d-cache-sets = <64>; + i-cache-line-size = <64>; + i-cache-size = <0x10000>; + i-cache-sets = <64>; + next-level-cache = <&l2_cache_b>; }; cpu2: cpu@2 { @@ -95,6 +137,13 @@ cpu2: cpu@2 { compatible = "arm,cortex-a73"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <64>; + d-cache-size = <0x10000>; + d-cache-sets = <64>; + i-cache-line-size = <64>; + i-cache-size = <0x10000>; + i-cache-sets = <64>; + next-level-cache = <&l2_cache_b>; }; cpu3: cpu@3 { @@ -102,6 +151,31 @@ cpu3: cpu@3 { compatible = "arm,cortex-a73"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <64>; + d-cache-size = <0x10000>; + d-cache-sets = <64>; + i-cache-line-size = <64>; + i-cache-size = <0x10000>; + i-cache-sets = <64>; + next-level-cache = <&l2_cache_b>; + }; + + l2_cache_l: l2-cache-cluster0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x40000>; /* L2. 256 KB */ + cache-line-size = <64>; + cache-sets = <512>; + }; + + l2_cache_b: l2-cache-cluster1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; /* L2. 1 Mb */ + cache-line-size = <64>; + cache-sets = <512>; }; }; From 916fa558cb27182933fdfe82d6d84b437e69349c Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 5 May 2025 14:37:00 +0000 Subject: [PATCH 508/931] arm64: dts: amlogic: sm1-bananapi: lower SD card speed for stability Users report being able to boot (u-boot) from SD card but kernel init then fails to mount partitions on the card containing boot media resulting in first-boot failure. System logs show only the probe of the mmc devices: the SD card is seen, but no partitions are found so init fails to mount them and boot stalls. Reducing the speed of the SD card from 50MHz to 35MHz results in complete probing of the card and successful boot. Signed-off-by: Christian Hewitt Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20250505143700.4029484-1-christianshewitt@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi index 538b35036954..5e07f0f9538e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi @@ -380,11 +380,10 @@ &sd_emmc_b { bus-width = <4>; cap-sd-highspeed; - max-frequency = <50000000>; + /* Boot failures are observed at 50MHz */ + max-frequency = <35000000>; disable-wp; - /* TOFIX: SD card is barely usable in SDR modes */ - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; vmmc-supply = <&tflash_vdd>; vqmmc-supply = <&vddio_c>; From 604a932fa924e7b15be47c6208a305f289cfa309 Mon Sep 17 00:00:00 2001 From: SungMin Park Date: Mon, 1 Sep 2025 10:49:23 +0530 Subject: [PATCH 509/931] dt-bindings: arm: axis: Add ARTPEC-8 grizzly board Document the Axis ARTPEC-8 SoC binding and the grizzly board which uses ARTPEC-8 SoC. Signed-off-by: SungMin Park Signed-off-by: SeonGu Kang Signed-off-by: Ravi Patel Reviewed-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250901051926.59970-4-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/axis.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/axis.yaml b/Documentation/devicetree/bindings/arm/axis.yaml index f9c218dc6883..63e9aca85db7 100644 --- a/Documentation/devicetree/bindings/arm/axis.yaml +++ b/Documentation/devicetree/bindings/arm/axis.yaml @@ -8,6 +8,7 @@ title: Axis ARTPEC platforms maintainers: - Jesper Nilsson + - Lars Persson - linux-arm-kernel@axis.com description: | @@ -24,6 +25,12 @@ properties: - axis,artpec6-dev-board - const: axis,artpec6 + - description: Axis ARTPEC-8 SoC board + items: + - enum: + - axis,artpec8-grizzly + - const: axis,artpec8 + additionalProperties: true ... From d5cb16361f89e7f60da76c7e9e32c72c49db3e82 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:34:17 +0200 Subject: [PATCH 510/931] arm64: dts: apm: storm: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: apm-storm.dtsi:636.4-639.42: Warning (interrupt_map): /soc/pcie@1f2b0000:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@78010000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Link: https://lore.kernel.org/r/20250822133416.312544-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/apm/apm-storm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 872093b05ce1..1b9588f7536c 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -103,6 +103,7 @@ xgene_L2_3: l2-cache-3 { gic: interrupt-controller@78010000 { compatible = "arm,cortex-a15-gic"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ From b32a24f21283fbc86922006cc7d19fd23f70b8b8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:34:24 +0200 Subject: [PATCH 511/931] arm64: dts: amazon: alpine-v2: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: alpine-v2.dtsi:138.4-139.33: Warning (interrupt_map): /soc/pci@fbc00000:interrupt-map: Missing property '#address-cells' in node /soc/interrupt-controller@f0200000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Link: https://lore.kernel.org/r/20250822133423.312621-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/amazon/alpine-v2.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi index 5a72f0b64247..f49209fddbbb 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v2.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v2.dtsi @@ -123,6 +123,7 @@ gic: interrupt-controller@f0200000 { <0x0 0xf0120000 0x0 0x2000>; /* GICH */ interrupts = ; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; }; From 3d1963e503d752ba33446ad056435c687f6d8d83 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:34:25 +0200 Subject: [PATCH 512/931] arm64: dts: amazon: alpine-v3: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: alpine-v3.dtsi:342.4-349.33: Warning (interrupt_map): /soc/pcie@fbd00000:interrupt-map: Missing property '#address-cells' in node /soc/interrupt-controller@f0800000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Link: https://lore.kernel.org/r/20250822133423.312621-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi index dea60d136c2e..bd35e0e9d0ab 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi @@ -320,6 +320,7 @@ soc { gic: interrupt-controller@f0800000 { compatible = "arm,gic-v3"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0xf0800000 0 0x10000>, /* GICD */ From 7ee0f223cabe9b9384250024fec577c731cbcf72 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:33:41 +0200 Subject: [PATCH 513/931] arm64: dts: toshiba: tmpv7708: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: tmpv7708.dtsi:503.4-507.28: Warning (interrupt_map): /soc/pcie@28400000:interrupt-map: Missing property '#address-cells' in node /soc/interrupt-controller@24001000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Reviewed-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20250822133340.312380-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 39806f0ae513..9aa7b1872bd6 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -152,6 +152,7 @@ soc { gic: interrupt-controller@24001000 { compatible = "arm,gic-400"; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; interrupts = ; reg = <0 0x24001000 0 0x1000>, From 639f8e36baf1c7c6592ef267f696db981c62c2b6 Mon Sep 17 00:00:00 2001 From: SungMin Park Date: Mon, 1 Sep 2025 10:49:24 +0530 Subject: [PATCH 514/931] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support Add initial device tree support for Axis ARTPEC-8 SoC. This SoC contains 4 Cortex-A53 CPUs and several other peripheral IPs. Signed-off-by: SungMin Park Signed-off-by: SeonGu Kang Signed-off-by: Ravi Patel Link: https://lore.kernel.org/r/20250901051926.59970-5-ravi.patel@samsung.com Acked-by: Jesper Nilsson Signed-off-by: Krzysztof Kozlowski --- MAINTAINERS | 12 + arch/arm64/Kconfig.platforms | 7 + arch/arm64/boot/dts/exynos/Makefile | 1 + .../boot/dts/exynos/axis/artpec-pinctrl.h | 36 +++ .../boot/dts/exynos/axis/artpec8-pinctrl.dtsi | 120 +++++++++ arch/arm64/boot/dts/exynos/axis/artpec8.dtsi | 244 ++++++++++++++++++ 6 files changed, 420 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index fe168477caa4..4d0c1f10ffd4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4102,6 +4102,18 @@ S: Maintained F: Documentation/devicetree/bindings/sound/axentia,* F: sound/soc/atmel/tse850-pcm5142.c +AXIS ARTPEC ARM64 SoC SUPPORT +M: Jesper Nilsson +M: Lars Persson +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: linux-samsung-soc@vger.kernel.org +L: linux-arm-kernel@axis.com +S: Maintained +F: Documentation/devicetree/bindings/clock/axis,artpec*-clock.yaml +F: arch/arm64/boot/dts/exynos/axis/ +F: drivers/clk/samsung/clk-artpec*.c +F: include/dt-bindings/clock/axis,artpec*-clk.h + AXI-FAN-CONTROL HARDWARE MONITOR DRIVER M: Nuno Sá L: linux-hwmon@vger.kernel.org diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a88f5ad9328c..959f79d73b40 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -40,6 +40,13 @@ config ARCH_APPLE This enables support for Apple's in-house ARM SoC family, such as the Apple M1. +config ARCH_ARTPEC + bool "Axis Communications ARTPEC SoC Family" + depends on ARCH_EXYNOS + select ARM_GIC + help + This enables support for the ARMv8 based ARTPEC SoC Family. + config ARCH_AXIADO bool "Axiado SoC Family" select GPIOLIB diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile index bdb9e9813e50..bcca63136557 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +subdir-y += axis subdir-y += google dtb-$(CONFIG_ARCH_EXYNOS) += \ diff --git a/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h new file mode 100644 index 000000000000..2c151aa98c96 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Axis ARTPEC-8 SoC device tree pinctrl constants + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ +#define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ + +#define ARTPEC_PIN_PULL_NONE 0 +#define ARTPEC_PIN_PULL_DOWN 1 +#define ARTPEC_PIN_PULL_UP 3 + +#define ARTPEC_PIN_FUNC_INPUT 0 +#define ARTPEC_PIN_FUNC_OUTPUT 1 +#define ARTPEC_PIN_FUNC_2 2 +#define ARTPEC_PIN_FUNC_3 3 +#define ARTPEC_PIN_FUNC_4 4 +#define ARTPEC_PIN_FUNC_5 5 +#define ARTPEC_PIN_FUNC_6 6 +#define ARTPEC_PIN_FUNC_EINT 0xf +#define ARTPEC_PIN_FUNC_F ARTPEC_PIN_FUNC_EINT + +/* Drive strength for ARTPEC */ +#define ARTPEC_PIN_DRV_SR1 0x8 +#define ARTPEC_PIN_DRV_SR2 0x9 +#define ARTPEC_PIN_DRV_SR3 0xa +#define ARTPEC_PIN_DRV_SR4 0xb +#define ARTPEC_PIN_DRV_SR5 0xc +#define ARTPEC_PIN_DRV_SR6 0xd + +#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */ diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi new file mode 100644 index 000000000000..8d239a70f1b4 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +#include "artpec-pinctrl.h" + +&pinctrl_fsys { + gpe0: gpe0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe2: gpe2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf4: gpf4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gps0: gps0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gps1: gps1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + serial0_bus: serial0-bus-pins { + samsung,pins = "gpf4-4", "gpf4-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_peric { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk0: gpk0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi new file mode 100644 index 000000000000..db9833297982 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 SoC device tree source + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +#include +#include + +/ { + compatible = "axis,artpec8"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + pinctrl0 = &pinctrl_fsys; + pinctrl1 = &pinctrl_peric; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + clocks = <&cmu_cpucl CLK_GOUT_CPUCL_CLUSTER_CPU>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + idle-states { + entry-method = "psci"; + + cpu_sleep: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2000>; + }; + }; + }; + + fin_pll: clock-finpll { + compatible = "fixed-factor-clock"; + clocks = <&osc_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "fin_pll"; + }; + + osc_clk: clock-osc { + /* XXTI */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "osc_clk"; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0x0 0x17000000>; + #address-cells = <1>; + #size-cells = <1>; + + cmu_imem: clock-controller@10010000 { + compatible = "axis,artpec8-cmu-imem"; + reg = <0x10010000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_IMEM_ACLK>, + <&cmu_cmu CLK_DOUT_CMU_IMEM_JPEG>; + clock-names = "fin_pll", "aclk", "jpeg"; + }; + + timer@10040000 { + compatible = "axis,artpec8-mct", "samsung,exynos4210-mct"; + reg = <0x10040000 0x1000>; + clocks = <&fin_pll>, <&cmu_imem CLK_GOUT_IMEM_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + gic: interrupt-controller@10201000 { + compatible = "arm,gic-400"; + reg = <0x10201000 0x1000>, + <0x10202000 0x2000>, + <0x10204000 0x2000>, + <0x10206000 0x2000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + cmu_cpucl: clock-controller@11410000 { + compatible = "axis,artpec8-cmu-cpucl"; + reg = <0x11410000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_CPUCL_SWITCH>; + clock-names = "fin_pll", "switch"; + }; + + cmu_cmu: clock-controller@12400000 { + compatible = "axis,artpec8-cmu-cmu"; + reg = <0x12400000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + }; + + cmu_core: clock-controller@12410000 { + compatible = "axis,artpec8-cmu-core"; + reg = <0x12410000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_CORE_MAIN>, + <&cmu_cmu CLK_DOUT_CMU_CORE_DLP>; + clock-names = "fin_pll", "main", "dlp"; + }; + + cmu_bus: clock-controller@12c10000 { + compatible = "axis,artpec8-cmu-bus"; + reg = <0x12c10000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_BUS>, + <&cmu_cmu CLK_DOUT_CMU_BUS_DLP>; + clock-names = "fin_pll", "bus", "dlp"; + }; + + cmu_peri: clock-controller@16410000 { + compatible = "axis,artpec8-cmu-peri"; + reg = <0x16410000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_PERI_IP>, + <&cmu_cmu CLK_DOUT_CMU_PERI_AUDIO>, + <&cmu_cmu CLK_DOUT_CMU_PERI_DISP>; + clock-names = "fin_pll", "ip", "audio", "disp"; + }; + + pinctrl_peric: pinctrl@165f0000 { + compatible = "axis,artpec8-pinctrl"; + reg = <0x165f0000 0x1000>; + interrupts = ; + }; + + cmu_fsys: clock-controller@16c10000 { + compatible = "axis,artpec8-cmu-fsys"; + reg = <0x16c10000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_IP>; + clock-names = "fin_pll", "scan0", "scan1", "bus", "ip"; + }; + + pinctrl_fsys: pinctrl@16c30000 { + compatible = "axis,artpec8-pinctrl"; + reg = <0x16c30000 0x1000>; + interrupts = ; + }; + + serial_0: serial@16cc0000 { + compatible = "axis,artpec8-uart"; + reg = <0x16cc0000 0x100>; + clocks = <&cmu_fsys CLK_GOUT_FSYS_UART0_PCLK>, + <&cmu_fsys CLK_GOUT_FSYS_UART0_SCLK_UART>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&serial0_bus>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From b1763769917723743284389803b4a0e0e09b849b Mon Sep 17 00:00:00 2001 From: SeonGu Kang Date: Mon, 1 Sep 2025 10:49:25 +0530 Subject: [PATCH 515/931] arm64: dts: axis: Add ARTPEC-8 Grizzly dts support Add initial devcie tree for the ARTPEC-8 Grizzly board. The ARTPEC-8 Grizzly is a small board developed by Axis, based on the Axis ARTPEC-8 SoC. Signed-off-by: SeonGu Kang Signed-off-by: Ravi Patel Link: https://lore.kernel.org/r/20250901051926.59970-6-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/axis/Makefile | 4 +++ .../boot/dts/exynos/axis/artpec8-grizzly.dts | 35 +++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/axis/Makefile create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts diff --git a/arch/arm64/boot/dts/exynos/axis/Makefile b/arch/arm64/boot/dts/exynos/axis/Makefile new file mode 100644 index 000000000000..ccf00de64016 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_ARTPEC) += \ + artpec8-grizzly.dtb diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts b/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts new file mode 100644 index 000000000000..5ae864ec3193 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec8-grizzly.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 Grizzly board device tree source + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +/dts-v1/; +#include "artpec8.dtsi" +#include "artpec8-pinctrl.dtsi" +#include +/ { + model = "ARTPEC-8 grizzly board"; + compatible = "axis,artpec8-grizzly", "axis,artpec8"; + + aliases { + serial0 = &serial_0; + }; + + chosen { + stdout-path = &serial_0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; +}; + +&osc_clk { + clock-frequency = <50000000>; +}; From f5e36ecc9e4a2a4bcd942ad1e9947e018ffd15b5 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Sat, 23 Aug 2025 03:01:41 -0700 Subject: [PATCH 516/931] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC Describe JH7110 SoC DDR external memory interface. Signed-off-by: E Shattow Reviewed-by: Krzysztof Kozlowski Reviewed-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- .../starfive,jh7110-dmc.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml new file mode 100644 index 000000000000..d65313b33a3e --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 DMC + +maintainers: + - E Shattow + +description: + JH7110 DDR external memory interface LPDDR4/DDR4/DDR3/LPDDR3 32-bit at + 2133Mbps (up to 2800Mbps). + +properties: + compatible: + items: + - const: starfive,jh7110-dmc + + reg: + items: + - description: controller registers + - description: phy registers + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pll + + resets: + items: + - description: axi + - description: osc + - description: apb + + reset-names: + items: + - const: axi + - const: osc + - const: apb + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + memory-controller@15700000 { + compatible = "starfive,jh7110-dmc"; + reg = <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names = "pll"; + resets = <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names = "axi", "osc", "apb"; + }; + }; From 7114969021ec5c4c0f3df1da3a8790f75dda92e2 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Sat, 23 Aug 2025 03:01:42 -0700 Subject: [PATCH 517/931] riscv: dts: starfive: jh7110: add DMC memory controller Add JH7110 SoC DDR external memory controller. Signed-off-by: E Shattow Reviewed-by: Hal Feng Reviewed-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 0ba74ef04679..f3876660c07f 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -931,6 +931,18 @@ watchdog@13070000 { <&syscrg JH7110_SYSRST_WDT_CORE>; }; + memory-controller@15700000 { + compatible = "starfive,jh7110-dmc"; + reg = <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names = "pll"; + resets = <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names = "axi", "osc", "apb"; + }; + crypto: crypto@16000000 { compatible = "starfive,jh7110-crypto"; reg = <0x0 0x16000000 0x0 0x4000>; From 8181cc2f3f21657392da912eb20ee17514c87828 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Sat, 23 Aug 2025 03:01:43 -0700 Subject: [PATCH 518/931] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader Add bootph-pre-ram hinting to jh7110.dtsi: - CPU interrupt controller(s) - gmac1_rgmii_rxin fixed-clock (dependency of syscrg) - gmac1_rmii_refin fixed-clock (dependency of syscrg) - oscillator - core local interrupt timer - syscrg clock-controller - pllclk clock-controller (dependency of syscrg) - DDR memory controller Signed-off-by: E Shattow Reviewed-by: Hal Feng Reviewed-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index f3876660c07f..6e56e9d20bb0 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -35,6 +35,7 @@ S7_0: cpu@0 { cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells = <1>; }; @@ -68,6 +69,7 @@ U74_1: cpu@1 { cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells = <1>; }; @@ -101,6 +103,7 @@ U74_2: cpu@2 { cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells = <1>; }; @@ -134,6 +137,7 @@ U74_3: cpu@3 { cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells = <1>; }; @@ -167,6 +171,7 @@ U74_4: cpu@4 { cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells = <1>; }; @@ -273,12 +278,14 @@ gmac0_rmii_refin: gmac0-rmii-refin-clock { gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { compatible = "fixed-clock"; + bootph-pre-ram; clock-output-names = "gmac1_rgmii_rxin"; #clock-cells = <0>; }; gmac1_rmii_refin: gmac1-rmii-refin-clock { compatible = "fixed-clock"; + bootph-pre-ram; clock-output-names = "gmac1_rmii_refin"; #clock-cells = <0>; }; @@ -321,6 +328,7 @@ mclk_ext: mclk-ext-clock { osc: oscillator { compatible = "fixed-clock"; + bootph-pre-ram; clock-output-names = "osc"; #clock-cells = <0>; }; @@ -354,6 +362,7 @@ soc { clint: timer@2000000 { compatible = "starfive,jh7110-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0x10000>; + bootph-pre-ram; interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, <&cpu1_intc 3>, <&cpu1_intc 7>, <&cpu2_intc 3>, <&cpu2_intc 7>, @@ -880,6 +889,7 @@ qspi: spi@13010000 { syscrg: clock-controller@13020000 { compatible = "starfive,jh7110-syscrg"; reg = <0x0 0x13020000 0x0 0x10000>; + bootph-pre-ram; clocks = <&osc>, <&gmac1_rmii_refin>, <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, @@ -904,6 +914,7 @@ sys_syscon: syscon@13030000 { pllclk: clock-controller { compatible = "starfive,jh7110-pll"; + bootph-pre-ram; clocks = <&osc>; #clock-cells = <1>; }; @@ -935,6 +946,7 @@ memory-controller@15700000 { compatible = "starfive,jh7110-dmc"; reg = <0x0 0x15700000 0x0 0x10000>, <0x0 0x13000000 0x0 0x10000>; + bootph-pre-ram; clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; clock-names = "pll"; resets = <&syscrg JH7110_SYSRST_DDR_AXI>, From 7e1aa57c2d14908c1faf0bcbf3e746dcf650eaa0 Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Thu, 28 Aug 2025 15:17:11 +0200 Subject: [PATCH 519/931] arm64: dts: broadcom: bcm2712: Add pin controller nodes Add pin-control devicetree nodes and used them to explicitly define uSD card interface pin configuration. Signed-off-by: Ivan T. Ivanov Reviewed-by: Stefan Wahren Signed-off-by: Andrea della Porta Link: https://lore.kernel.org/r/5ceba8558e0007a9685f19b51d681d0ce79e7634.1756386531.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli --- .../dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts | 18 ++++++++++++++++++ arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 10 ++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts index 6ea3c102e0d6..6091a1ff365c 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts @@ -53,6 +53,21 @@ sd_vcc_reg: sd-vcc-reg { }; }; +&pinctrl { + emmc_sd_default: emmc-sd-default-state { + pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3"; + bias-pull-up; + }; +}; + +&pinctrl_aon { + emmc_aon_cd_default: emmc-aon-cd-default-state { + function = "sd_card_g"; + pins = "aon_gpio5"; + bias-pull-up; + }; +}; + /* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector * labeled "UART", i.e. the interface with the system console. */ @@ -62,12 +77,15 @@ &uart10 { /* SDIO1 is used to drive the SD card */ &sdio1 { + pinctrl-0 = <&emmc_sd_default>, <&emmc_aon_cd_default>; + pinctrl-names = "default"; vqmmc-supply = <&sd_io_1v8_reg>; vmmc-supply = <&sd_vcc_reg>; bus-width = <4>; sd-uhs-sdr50; sd-uhs-ddr50; sd-uhs-sdr104; + cd-gpios = <&gio_aon 5 GPIO_ACTIVE_LOW>; }; &soc { diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 940f1c483198..c1374cf383ae 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -243,6 +243,16 @@ uart10: serial@7d001000 { status = "disabled"; }; + pinctrl: pinctrl@7d504100 { + compatible = "brcm,bcm2712c0-pinctrl"; + reg = <0x7d504100 0x30>; + }; + + pinctrl_aon: pinctrl@7d510700 { + compatible = "brcm,bcm2712c0-aon-pinctrl"; + reg = <0x7d510700 0x20>; + }; + interrupt-controller@7d517000 { compatible = "brcm,bcm7271-l2-intc"; reg = <0x7d517000 0x10>; From 72eb12b99d3539060d93191c502e7b7e259ead56 Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Thu, 28 Aug 2025 15:17:12 +0200 Subject: [PATCH 520/931] arm64: dts: broadcom: bcm2712: Add one more GPIO node Add GPIO and related interrupt controller nodes and wire one of the lines to power button. Signed-off-by: Ivan T. Ivanov Signed-off-by: Andrea della Porta Link: https://lore.kernel.org/r/6d311b2f629bbc0e1dd9821e4aa8e5af9f8e5362.1756386531.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli --- .../dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts | 21 +++++++++++++++++++ arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 12 +++++++++++ 2 files changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts index 6091a1ff365c..f0883c903527 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts @@ -2,6 +2,7 @@ /dts-v1/; #include +#include #include "bcm2712.dtsi" / { @@ -29,6 +30,20 @@ memory@0 { reg = <0 0 0 0x28000000>; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_button_default>; + status = "okay"; + + power_button: power-button { + label = "pwr_button"; + linux,code = ; + gpios = <&gio 20 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + }; + }; + sd_io_1v8_reg: sd-io-1v8-reg { compatible = "regulator-gpio"; regulator-name = "vdd-sd-io"; @@ -58,6 +73,12 @@ emmc_sd_default: emmc-sd-default-state { pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3"; bias-pull-up; }; + + pwr_button_default: pwr-button-default-state { + function = "gpio"; + pins = "gpio20"; + bias-pull-up; + }; }; &pinctrl_aon { diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index c1374cf383ae..a1af86208d9e 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -248,6 +248,18 @@ pinctrl: pinctrl@7d504100 { reg = <0x7d504100 0x30>; }; + gio: gpio@7d508500 { + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + reg = <0x7d508500 0x40>; + interrupt-parent = <&main_irq>; + interrupts = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + brcm,gpio-bank-widths = <32 22>; + }; + pinctrl_aon: pinctrl@7d510700 { compatible = "brcm,bcm2712c0-aon-pinctrl"; reg = <0x7d510700 0x20>; From 55ec7b1b97267fd552848e7e3ba70cbbfc1eba73 Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Thu, 28 Aug 2025 15:17:13 +0200 Subject: [PATCH 521/931] arm64: dts: broadcom: bcm2712: Add second SDHCI controller node Add SDIO2 node. On RPi5 it is connected to WiFi chip. Add related pin, gpio and regulator definitions and add WiFi node. With this and firmware already provided by distributions, at least on openSUSE Tumbleweed, this is sufficient to make WiFi operational on RPi5 \o/. Signed-off-by: Ivan T. Ivanov Signed-off-by: Andrea della Porta Link: https://lore.kernel.org/r/4ff3a58e98d90a43deb2448b23754808afc7153b.1756386531.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli --- .../dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts | 52 +++++++++++++++++++ arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 15 ++++++ 2 files changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts index f0883c903527..411b58c1dddf 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts @@ -66,6 +66,18 @@ sd_vcc_reg: sd-vcc-reg { enable-active-high; gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>; }; + + wl_on_reg: wl-on-reg { + compatible = "regulator-fixed"; + regulator-name = "wl-on-regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-0 = <&wl_on_default>; + pinctrl-names = "default"; + gpio = <&gio 28 GPIO_ACTIVE_HIGH>; + startup-delay-us = <150000>; + enable-active-high; + }; }; &pinctrl { @@ -79,6 +91,29 @@ pwr_button_default: pwr-button-default-state { pins = "gpio20"; bias-pull-up; }; + + sdio2_30_default: sdio2-30-default-state { + clk-pins { + function = "sd2"; + pins = "gpio30"; + bias-disable; + }; + cmd-pins { + function = "sd2"; + pins = "gpio31"; + bias-pull-up; + }; + dat-pins { + function = "sd2"; + pins = "gpio32", "gpio33", "gpio34", "gpio35"; + bias-pull-up; + }; + }; + + wl_on_default: wl-on-default-state { + function = "gpio"; + pins = "gpio28"; + }; }; &pinctrl_aon { @@ -109,6 +144,23 @@ &sdio1 { cd-gpios = <&gio_aon 5 GPIO_ACTIVE_LOW>; }; +&sdio2 { + pinctrl-0 = <&sdio2_30_default>; + pinctrl-names = "default"; + bus-width = <4>; + vmmc-supply = <&wl_on_reg>; + sd-uhs-ddr50; + non-removable; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + wifi: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + &soc { firmware: firmware { compatible = "raspberrypi,bcm2835-firmware", "simple-mfd"; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index a1af86208d9e..6068cb75ef5a 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -285,6 +285,21 @@ gio_aon: gpio@7d517c00 { */ }; + sdio2: mmc@1100000 { + compatible = "brcm,bcm2712-sdhci", + "brcm,sdhci-brcmstb"; + reg = <0x01100000 0x260>, + <0x01100400 0x200>; + reg-names = "host", "cfg"; + interrupts = ; + clocks = <&clk_emmc2>; + clock-names = "sw_sdio"; + sdhci-caps-mask = <0x0000C000 0x0>; + sdhci-caps = <0x0 0x0>; + mmc-ddr-3_3v; + status = "disabled"; + }; + gicv2: interrupt-controller@7fff9000 { compatible = "arm,gic-400"; reg = <0x7fff9000 0x1000>, From 72323b141691beeab8809c1dc0b98b1bcf058d88 Mon Sep 17 00:00:00 2001 From: "Ivan T. Ivanov" Date: Thu, 28 Aug 2025 15:17:14 +0200 Subject: [PATCH 522/931] arm64: dts: broadcom: bcm2712: Add UARTA controller node On RPi5 device Bluetooth chips is connected to UARTA port. Add Bluetooth chips and related pin definitions. With this and firmware already provided by distributions, at least on openSUSE Tumbleweed, this is sufficient to make Bluetooth operational on RPi5 \o/. Signed-off-by: Ivan T. Ivanov Signed-off-by: Andrea della Porta Link: https://lore.kernel.org/r/35c0da6a741019efefc3c8e405e210a3a8156830.1756386531.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli --- .../dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts | 42 +++++++++++++++++++ arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 18 ++++++++ 2 files changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts index 411b58c1dddf..04738bf281eb 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts @@ -81,6 +81,11 @@ wl_on_reg: wl-on-reg { }; &pinctrl { + bt_shutdown_default: bt-shutdown-default-state { + function = "gpio"; + pins = "gpio29"; + }; + emmc_sd_default: emmc-sd-default-state { pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3"; bias-pull-up; @@ -110,6 +115,29 @@ dat-pins { }; }; + uarta_24_default: uarta-24-default-state { + rts-pins { + function = "uart0"; + pins = "gpio24"; + bias-disable; + }; + cts-pins { + function = "uart0"; + pins = "gpio25"; + bias-pull-up; + }; + txd-pins { + function = "uart0"; + pins = "gpio26"; + bias-disable; + }; + rxd-pins { + function = "uart0"; + pins = "gpio27"; + bias-pull-up; + }; + }; + wl_on_default: wl-on-default-state { function = "gpio"; pins = "gpio28"; @@ -188,6 +216,20 @@ power: power { }; }; +/* uarta communicates with the BT module */ +&uarta { + uart-has-rtscts; + pinctrl-0 = <&uarta_24_default &bt_shutdown_default>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth: bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gio 29 GPIO_ACTIVE_HIGH>; + }; +}; + &hvs { clocks = <&firmware_clocks 4>, <&firmware_clocks 16>; clock-names = "core", "disp"; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 6068cb75ef5a..e77a66adc22a 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -38,6 +38,13 @@ clk_emmc2: clk-emmc2 { clock-frequency = <200000000>; clock-output-names = "emmc2-clock"; }; + + clk_sw_baud: clk-sw-baud { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <96000000>; + clock-output-names = "sw-baud"; + }; }; cpus: cpus { @@ -260,6 +267,17 @@ gio: gpio@7d508500 { brcm,gpio-bank-widths = <32 22>; }; + uarta: serial@7d50c000 { + compatible = "brcm,bcm7271-uart"; + reg = <0x7d50c000 0x20>; + reg-names = "uart"; + clocks = <&clk_sw_baud>; + clock-names = "sw_baud"; + interrupts = ; + interrupt-names = "uart"; + status = "disabled"; + }; + pinctrl_aon: pinctrl@7d510700 { compatible = "brcm,bcm2712c0-aon-pinctrl"; reg = <0x7d510700 0x20>; From 725386ca1949a570d8b73b179518998d399031bf Mon Sep 17 00:00:00 2001 From: Andrea della Porta Date: Thu, 28 Aug 2025 15:17:10 +0200 Subject: [PATCH 523/931] dt-bindings: mmc: Add support for capabilities to Broadcom SDHCI controller The Broadcom BRCMSTB SDHCI Controller device supports Common properties in terms of Capabilities. Reference sdhci-common schema instead of mmc-controller in order for capabilities to be specified in DT nodes avoiding warnings from the DT compiler. Signed-off-by: Andrea della Porta Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/181cc905566f2d9b2e5076295cd285230f81ed07.1756386531.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml index eee6be7a7867..493655a38b37 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -61,7 +61,7 @@ properties: description: Specifies that controller should use auto CMD12 allOf: - - $ref: mmc-controller.yaml# + - $ref: sdhci-common.yaml# - if: properties: clock-names: From cbdd3e7613200ee49ae8fa00020c39c4a2e1ee42 Mon Sep 17 00:00:00 2001 From: Stanimir Varbanov Date: Fri, 22 Aug 2025 12:34:39 +0300 Subject: [PATCH 524/931] arm64: dts: rp1: Add ethernet DT node Add macb GEM ethernet DT node. Signed-off-by: Stanimir Varbanov Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20250822093440.53941-5-svarbanov@suse.de Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/rp1-common.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi index 5002a375eb0b..6bdc304c5f24 100644 --- a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi +++ b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi @@ -39,4 +39,20 @@ rp1_gpio: pinctrl@400d0000 { <1 IRQ_TYPE_LEVEL_HIGH>, <2 IRQ_TYPE_LEVEL_HIGH>; }; + + rp1_eth: ethernet@40100000 { + compatible = "raspberrypi,rp1-gem"; + reg = <0x00 0x40100000 0x0 0x4000>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rp1_clocks RP1_CLK_SYS>, + <&rp1_clocks RP1_CLK_SYS>, + <&rp1_clocks RP1_CLK_ETH>, + <&rp1_clocks RP1_CLK_ETH_TSU>; + clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; }; From 43456fdfc014f302fdcbb85903efe9548330dc32 Mon Sep 17 00:00:00 2001 From: Stanimir Varbanov Date: Fri, 22 Aug 2025 12:34:40 +0300 Subject: [PATCH 525/931] arm64: dts: broadcom: Enable RP1 ethernet for Raspberry Pi 5 Enable RP1 ethernet DT node for Raspberry Pi 5. Signed-off-by: Stanimir Varbanov Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20250822093440.53941-6-svarbanov@suse.de Signed-off-by: Florian Fainelli --- .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts index a70a9b158df3..c70d1cb7f3b6 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -23,3 +23,21 @@ &pcie1 { &pcie2 { status = "okay"; }; + +&rp1_eth { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&phy1>; + + mdio { + reg = <0x1>; + reset-gpios = <&rp1_gpio 32 GPIO_ACTIVE_LOW>; + reset-delay-us = <5000>; + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; +}; From 2cb82bf8c160117b4036865e75f9997a84aa6cd7 Mon Sep 17 00:00:00 2001 From: Andrea della Porta Date: Mon, 11 Aug 2025 16:12:34 +0200 Subject: [PATCH 526/931] arm64: dts: broadcom: delete redundant pcie enablement nodes The pcie1 and pcie2 override nodes to enable the respective peripherals are declared both in bcm2712-rpi-5-b.dts and bcm2712-rpi-5-b-ovl-rp1.dts, which makes those declared in the former file redundant. Drop those redundant nodes from the board devicetree. Signed-off-by: Andrea della Porta Link: https://lore.kernel.org/r/2865b787d893fd1dcf816e1c96856711754d612d.1754914766.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts index c70d1cb7f3b6..55dbacf5a6fc 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -16,14 +16,6 @@ &pcie2 { #include "rp1-nexus.dtsi" }; -&pcie1 { - status = "okay"; -}; - -&pcie2 { - status = "okay"; -}; - &rp1_eth { status = "okay"; phy-mode = "rgmii-id"; From 911b1a6443bbdeed25c5459768793953bf846dcb Mon Sep 17 00:00:00 2001 From: Andrea della Porta Date: Mon, 11 Aug 2025 16:12:35 +0200 Subject: [PATCH 527/931] arm64: dts: broadcom: amend the comment about the role of BCM2712 board DTS Current board DTS for Raspberry Pi5 states that bcm2712-rpi-5-b.dts should not be modified and all declarations should go in the overlay board DTS instead (bcm2712-rpi-5-b-ovl-rp1.dts). There's a caveat though: there's currently no infrastructure to reliably reference nodes that have not been declared yet, as is the case when loading those nodes from a runtime overlay. For more details about these limitations see [1] and follow-ups. Change the comment to make it clear which DTS file will host specific nodes, especially the RP1 related nodes which should be customized outside the overlay DTS. Link [1] - https://lore.kernel.org/all/CAMEGJJ3=W8_R0xBvm8r+Q7iExZx8xPBHEWWGAT9ngpGWDSKCaQ@mail.gmail.com/ Signed-off-by: Andrea della Porta Link: https://lore.kernel.org/r/47f6368a77d6bd846c02942d20c07dd48e0ae7df.1754914766.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts index 55dbacf5a6fc..2045a221c393 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -4,8 +4,14 @@ * the RP1 driver to load the RP1 dtb overlay at runtime, while * bcm2712-rpi-5-b.dts (this file) is the fully defined one (i.e. it * already contains RP1 node, so no overlay is loaded nor needed). - * This file is not intended to be modified, nodes should be added - * to the included bcm2712-rpi-5-b-ovl-rp1.dts. + * This file is intended to host the override nodes for the RP1 peripherals, + * e.g. to declare the phy of the ethernet interface or the custom pin setup + * for several RP1 peripherals. + * This in turn is due to the fact that there's no current generic + * infrastructure to reference nodes (i.e. the nodes in rp1-common.dtsi) that + * are not yet defined in the DT since they are loaded at runtime via overlay. + * All other nodes that do not have anything to do with RP1 should be added + * to the included bcm2712-rpi-5-b-ovl-rp1.dts instead. */ /dts-v1/; From 7c3e113ef09d474c4b076c42f1264c4fa78d1dc8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Jul 2025 16:22:13 +0200 Subject: [PATCH 528/931] ARM: dts: ti: omap4: Use generic "ethernet" as node name Common name for Ethernet controllers is "ethernet", not "eth", also recommended by Devicetree specification in "Generic Names Recommendation". Verified lack of impact using dtx_diff. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250717142212.92333-2-krzysztof.kozlowski@linaro.org Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/ti/omap/omap4-sdp.dts | 2 +- arch/arm/boot/dts/ti/omap/omap4-var-om44customboard.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/omap4-sdp.dts b/arch/arm/boot/dts/ti/omap/omap4-sdp.dts index b535d24c6140..b550105585a1 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-sdp.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-sdp.dts @@ -467,7 +467,7 @@ &mcspi1 { pinctrl-names = "default"; pinctrl-0 = <&mcspi1_pins>; - eth@0 { + ethernet@0 { pinctrl-names = "default"; pinctrl-0 = <&ks8851_pins>; diff --git a/arch/arm/boot/dts/ti/omap/omap4-var-om44customboard.dtsi b/arch/arm/boot/dts/ti/omap/omap4-var-om44customboard.dtsi index cadc7e02592b..80e89a2f8be1 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-var-om44customboard.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-var-om44customboard.dtsi @@ -194,7 +194,7 @@ &mcspi1 { pinctrl-0 = <&mcspi1_pins>; status = "okay"; - eth@0 { + ethernet@0 { compatible = "ks8851"; pinctrl-names = "default"; pinctrl-0 = <&ks8851_irq_pins>; From ca8be8fc2c306efb090791835acfb5b33542ca1d Mon Sep 17 00:00:00 2001 From: Bruno Thomsen Date: Mon, 21 Jul 2025 19:37:41 +0200 Subject: [PATCH 529/931] ARM: dts: am33xx-l4: fix UART compatible Fixes the following dtschema check warning: serial@0 (ti,am3352-uart): compatible: 'oneOf' conditional failed, one must be fixed: ['ti,am3352-uart', 'ti,omap3-uart'] is too long 'ti,am3352-uart' is not one of ['ti,am64-uart', 'ti,j721e-uart'] 'ti,am654-uart' was expected from schema $id: http://devicetree.org/schemas/serial/8250_omap.yaml# Signed-off-by: Bruno Thomsen Reviewed-by: Judith Mendez Link: https://lore.kernel.org/r/20250721173741.6369-1-bruno.thomsen@gmail.com Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi index d6a143abae5f..cef24aafed1a 100644 --- a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi @@ -200,7 +200,7 @@ SYSC_OMAP2_SOFTRESET | ranges = <0x0 0x9000 0x1000>; uart0: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; + compatible = "ti,am3352-uart"; clock-frequency = <48000000>; reg = <0x0 0x1000>; interrupts = <72>; @@ -1108,7 +1108,7 @@ SYSC_OMAP2_SOFTRESET | ranges = <0x0 0x22000 0x1000>; uart1: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; + compatible = "ti,am3352-uart"; clock-frequency = <48000000>; reg = <0x0 0x1000>; interrupts = <73>; @@ -1139,7 +1139,7 @@ SYSC_OMAP2_SOFTRESET | ranges = <0x0 0x24000 0x1000>; uart2: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; + compatible = "ti,am3352-uart"; clock-frequency = <48000000>; reg = <0x0 0x1000>; interrupts = <74>; @@ -1770,7 +1770,7 @@ SYSC_OMAP2_SOFTRESET | ranges = <0x0 0xa6000 0x1000>; uart3: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; + compatible = "ti,am3352-uart"; clock-frequency = <48000000>; reg = <0x0 0x1000>; interrupts = <44>; @@ -1799,7 +1799,7 @@ SYSC_OMAP2_SOFTRESET | ranges = <0x0 0xa8000 0x1000>; uart4: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; + compatible = "ti,am3352-uart"; clock-frequency = <48000000>; reg = <0x0 0x1000>; interrupts = <45>; @@ -1828,7 +1828,7 @@ SYSC_OMAP2_SOFTRESET | ranges = <0x0 0xaa000 0x1000>; uart5: serial@0 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; + compatible = "ti,am3352-uart"; clock-frequency = <48000000>; reg = <0x0 0x1000>; interrupts = <46>; From 46179394d4e45d561a2c0185774c2f7b88fa7c14 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:16:52 +0200 Subject: [PATCH 530/931] ARM: dts: omap: dm814x: Split 'reg' per entry Multiple entries in 'reg' should be encoded in separate <>. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250819131651.86569-5-krzysztof.kozlowski@linaro.org Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/ti/omap/dm814x.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dm814x.dtsi b/arch/arm/boot/dts/ti/omap/dm814x.dtsi index a8cd724ce4bc..27d1f35a31fd 100644 --- a/arch/arm/boot/dts/ti/omap/dm814x.dtsi +++ b/arch/arm/boot/dts/ti/omap/dm814x.dtsi @@ -155,10 +155,10 @@ &cppi41dma 26 1 &cppi41dma 27 1 cppi41dma: dma-controller@47402000 { compatible = "ti,am3359-cppi41"; - reg = <0x47400000 0x1000 - 0x47402000 0x1000 - 0x47403000 0x1000 - 0x47404000 0x4000>; + reg = <0x47400000 0x1000>, + <0x47402000 0x1000>, + <0x47403000 0x1000>, + <0x47404000 0x4000>; reg-names = "glue", "controller", "scheduler", "queuemgr"; interrupts = <17>; interrupt-names = "glue"; From 7d7df1bc644a29e880181579994bd2da9fb1a6ce Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:16:53 +0200 Subject: [PATCH 531/931] ARM: dts: omap: dm816x: Split 'reg' per entry Multiple entries in 'reg' should be encoded in separate <>. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250819131651.86569-6-krzysztof.kozlowski@linaro.org Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/ti/omap/dm816x.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/dm816x.dtsi b/arch/arm/boot/dts/ti/omap/dm816x.dtsi index b68686f0643b..407d7bc5b13a 100644 --- a/arch/arm/boot/dts/ti/omap/dm816x.dtsi +++ b/arch/arm/boot/dts/ti/omap/dm816x.dtsi @@ -643,10 +643,10 @@ &cppi41dma 26 1 &cppi41dma 27 1 cppi41dma: dma-controller@47402000 { compatible = "ti,am3359-cppi41"; - reg = <0x47400000 0x1000 - 0x47402000 0x1000 - 0x47403000 0x1000 - 0x47404000 0x4000>; + reg = <0x47400000 0x1000>, + <0x47402000 0x1000>, + <0x47403000 0x1000>, + <0x47404000 0x4000>; reg-names = "glue", "controller", "scheduler", "queuemgr"; interrupts = <17>; interrupt-names = "glue"; From 9df7366a29192f860e9e35a258f0b000b6e4a754 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:16:54 +0200 Subject: [PATCH 532/931] ARM: dts: omap: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250819131651.86569-7-krzysztof.kozlowski@linaro.org Signed-off-by: Kevin Hilman --- .../arm/boot/dts/ti/omap/am335x-myirtech-myd.dts | 4 ++-- arch/arm/boot/dts/ti/omap/am335x-sl50.dts | 2 +- arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi | 8 ++++---- arch/arm/boot/dts/ti/omap/am33xx.dtsi | 8 ++++---- .../dts/ti/omap/am57xx-beagle-x15-common.dtsi | 2 +- arch/arm/boot/dts/ti/omap/dra7-l4.dtsi | 14 +++++++------- arch/arm/boot/dts/ti/omap/dra71-evm.dts | 16 ++++++++-------- .../dts/ti/omap/omap3-devkit8000-common.dtsi | 4 ++-- arch/arm/boot/dts/ti/omap/omap3-sbc-t3517.dts | 4 ++-- 9 files changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts index fd91a3c01a63..06a352f98b22 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-myirtech-myd.dts @@ -143,7 +143,7 @@ &i2c1 { sgtl5000: sgtl5000@a { compatible = "fsl,sgtl5000"; - reg =<0xa>; + reg = <0xa>; clocks = <&clk12m>; micbias-resistor-k-ohms = <4>; micbias-voltage-m-volts = <2250>; @@ -155,7 +155,7 @@ sgtl5000: sgtl5000@a { tda9988: tda9988@70 { compatible = "nxp,tda998x"; - reg =<0x70>; + reg = <0x70>; audio-ports = ; #sound-dai-cells = <0>; diff --git a/arch/arm/boot/dts/ti/omap/am335x-sl50.dts b/arch/arm/boot/dts/ti/omap/am335x-sl50.dts index 757ebd96b3f0..f3524e5ee43e 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-sl50.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-sl50.dts @@ -109,7 +109,7 @@ clocks { audio_mclk_fixed: oscillator@0 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <24576000>; /* 24.576MHz */ + clock-frequency = <24576000>; /* 24.576MHz */ }; audio_mclk: audio_mclk_gate@0 { diff --git a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi index cef24aafed1a..18ad52e93955 100644 --- a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi @@ -1457,10 +1457,10 @@ SYSC_OMAP2_SOFTRESET | gpio1: gpio@0 { compatible = "ti,omap4-gpio"; - gpio-ranges = <&am33xx_pinmux 0 0 8>, - <&am33xx_pinmux 8 90 4>, - <&am33xx_pinmux 12 12 16>, - <&am33xx_pinmux 28 30 4>; + gpio-ranges = <&am33xx_pinmux 0 0 8>, + <&am33xx_pinmux 8 90 4>, + <&am33xx_pinmux 12 12 16>, + <&am33xx_pinmux 28 30 4>; gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/arch/arm/boot/dts/ti/omap/am33xx.dtsi b/arch/arm/boot/dts/ti/omap/am33xx.dtsi index 0614ffdc1578..43ec2a95f4bb 100644 --- a/arch/arm/boot/dts/ti/omap/am33xx.dtsi +++ b/arch/arm/boot/dts/ti/omap/am33xx.dtsi @@ -461,10 +461,10 @@ &cppi41dma 26 1 &cppi41dma 27 1 cppi41dma: dma-controller@2000 { compatible = "ti,am3359-cppi41"; - reg = <0x0000 0x1000>, - <0x2000 0x1000>, - <0x3000 0x1000>, - <0x4000 0x4000>; + reg = <0x0000 0x1000>, + <0x2000 0x1000>, + <0x3000 0x1000>, + <0x4000 0x4000>; reg-names = "glue", "controller", "scheduler", "queuemgr"; interrupts = <17>; interrupt-names = "glue"; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-common.dtsi index 994e69ab38d7..87b61a98d5e9 100644 --- a/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am57xx-beagle-x15-common.dtsi @@ -149,7 +149,7 @@ led3 { gpio_fan: gpio_fan { /* Based on 5v 500mA AFB02505HHB */ compatible = "gpio-fan"; - gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; + gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; gpio-fan,speed-map = <0 0>, <13000 1>; #cooling-cells = <2>; diff --git a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi index ba7fdaae9c6e..c9282f57ffa5 100644 --- a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi @@ -267,8 +267,8 @@ usb2_phy1: phy@4000 { syscon-phy-power = <&scm_conf 0x300>; clocks = <&usb_phy1_always_on_clk32k>, <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; - clock-names = "wkupclk", - "refclk"; + clock-names = "wkupclk", + "refclk"; #phy-cells = <0>; }; @@ -279,8 +279,8 @@ usb2_phy2: phy@5000 { syscon-phy-power = <&scm_conf 0xe74>; clocks = <&usb_phy2_always_on_clk32k>, <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>; - clock-names = "wkupclk", - "refclk"; + clock-names = "wkupclk", + "refclk"; #phy-cells = <0>; }; @@ -294,9 +294,9 @@ usb3_phy1: phy@4400 { clocks = <&usb_phy3_always_on_clk32k>, <&sys_clkin1>, <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; - clock-names = "wkupclk", - "sysclk", - "refclk"; + clock-names = "wkupclk", + "sysclk", + "refclk"; #phy-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/ti/omap/dra71-evm.dts b/arch/arm/boot/dts/ti/omap/dra71-evm.dts index f747ac56eb92..1d2df8128cfe 100644 --- a/arch/arm/boot/dts/ti/omap/dra71-evm.dts +++ b/arch/arm/boot/dts/ti/omap/dra71-evm.dts @@ -83,10 +83,10 @@ lp8733: lp8733@60 { compatible = "ti,lp8733"; reg = <0x60>; - buck0-in-supply =<&vsys_3v3>; - buck1-in-supply =<&vsys_3v3>; - ldo0-in-supply =<&evm_5v0>; - ldo1-in-supply =<&evm_5v0>; + buck0-in-supply = <&vsys_3v3>; + buck1-in-supply = <&vsys_3v3>; + ldo0-in-supply = <&evm_5v0>; + ldo1-in-supply = <&evm_5v0>; lp8733_regulators: regulators { lp8733_buck0_reg: buck0 { @@ -131,10 +131,10 @@ lp8732: lp8732@61 { compatible = "ti,lp8732"; reg = <0x61>; - buck0-in-supply =<&vsys_3v3>; - buck1-in-supply =<&vsys_3v3>; - ldo0-in-supply =<&vsys_3v3>; - ldo1-in-supply =<&vsys_3v3>; + buck0-in-supply = <&vsys_3v3>; + buck1-in-supply = <&vsys_3v3>; + ldo0-in-supply = <&vsys_3v3>; + ldo1-in-supply = <&vsys_3v3>; lp8732_regulators: regulators { lp8732_buck0_reg: buck0 { diff --git a/arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi index 07d5894ebb74..910e3b54f530 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-common.dtsi @@ -275,8 +275,8 @@ filesystem@680000 { ethernet@6,0 { compatible = "davicom,dm9000"; - reg = <6 0x000 2>, - <6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */ + reg = <6 0x000 2>, + <6 0x400 2>; /* CS6, offset 0 and 0x400, IO size 2 */ bank-width = <2>; interrupt-parent = <&gpio1>; interrupts = <25 IRQ_TYPE_LEVEL_LOW>; diff --git a/arch/arm/boot/dts/ti/omap/omap3-sbc-t3517.dts b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3517.dts index 07bec48dc441..959fdeeb769e 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-sbc-t3517.dts +++ b/arch/arm/boot/dts/ti/omap/omap3-sbc-t3517.dts @@ -57,8 +57,8 @@ &mmc1_pins &mmc1_aux_pins >; - wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */ - cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ + wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */ + cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ }; &dss { From 9658a92fad1889ff92fa4bd668cd61052687245a Mon Sep 17 00:00:00 2001 From: Jihed Chaibi Date: Sat, 23 Aug 2025 00:25:30 +0200 Subject: [PATCH 533/931] ARM: dts: ti: omap: am335x-baltos: Fix ti,en-ck32k-xtal property in DTS to use correct boolean syntax The ti,en-ck32k-xtal property, defined as a boolean in the Device Tree schema, was incorrectly assigned a value (<1>) in the DTS file, causing a validation error: "size (4) error for type flag". The driver uses of_property_read_bool(), expecting a boolean. Remove the value to fix the dtbs_check error. Fixes: 262178b6b8e5 ("ARM: dts: split am335x-baltos-ir5221 into dts and dtsi files") Signed-off-by: Jihed Chaibi Link: https://lore.kernel.org/all/20250822222530.113520-1-jihed.chaibi.dev@gmail.com/ Link: https://lore.kernel.org/r/20250822222530.113520-1-jihed.chaibi.dev@gmail.com Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi b/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi index ae2e8dffbe04..ea47f9960c35 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos.dtsi @@ -269,7 +269,7 @@ &tps { vcc7-supply = <&vbat>; vccio-supply = <&vbat>; - ti,en-ck32k-xtal = <1>; + ti,en-ck32k-xtal; regulators { vrtc_reg: regulator@0 { From 5af5b85505bc859adb338fe5d6e4842e72cdf932 Mon Sep 17 00:00:00 2001 From: Jihed Chaibi Date: Sat, 23 Aug 2025 00:50:52 +0200 Subject: [PATCH 534/931] ARM: dts: ti: omap: omap3-devkit8000-lcd: Fix ti,keep-vref-on property to use correct boolean syntax in DTS The ti,keep-vref-on property, defined as a boolean flag in the Device Tree schema, was incorrectly assigned a value (<1>) in the DTS file, causing a validation error: "size (4) error for type flag". Remove the value to match the schema and ensure compatibility with the driver using device_property_read_bool(). This fixes the dtbs_check error. Fixes: ed05637c30e6 ("ARM: dts: omap3-devkit8000: Add ADS7846 Touchscreen support") Signed-off-by: Jihed Chaibi Link: https://lore.kernel.org/r/20250822225052.136919-1-jihed.chaibi.dev@gmail.com Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd-common.dtsi b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd-common.dtsi index a7f99ae0c1fe..78c657429f64 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-devkit8000-lcd-common.dtsi @@ -65,7 +65,7 @@ ads7846@0 { ti,debounce-max = /bits/ 16 <10>; ti,debounce-tol = /bits/ 16 <5>; ti,debounce-rep = /bits/ 16 <1>; - ti,keep-vref-on = <1>; + ti,keep-vref-on; ti,settle-delay-usec = /bits/ 16 <150>; wakeup-source; From 27322753c8b913fba05250e7b5abb1da31e6ed23 Mon Sep 17 00:00:00 2001 From: Jihed Chaibi Date: Sat, 30 Aug 2025 23:59:57 +0200 Subject: [PATCH 535/931] ARM: dts: omap: am335x-cm-t335: Remove unused mcasp num-serializer property The dtbs_check validation for am335x-cm-t335.dtb flags an error for an unevaluated 'num-serializer' property in the mcasp0 node. This property is obsolete; it is not defined in the davinci-mcasp-audio schema and is not used by the corresponding (or any) driver. Remove this unused property to fix the schema validation warning. Fixes: 48ab364478e77 ("ARM: dts: cm-t335: add audio support") Signed-off-by: Jihed Chaibi Link: https://lore.kernel.org/r/20250830215957.285694-1-jihed.chaibi.dev@gmail.com Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts b/arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts index 06767ea164b5..ece7f7854f6a 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-cm-t335.dts @@ -483,8 +483,6 @@ &mcasp1 { op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; - /* 16 serializers */ - num-serializer = <16>; serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 >; From 55a1ed25fa8b6fefbbc61704fd8fb2e4fe8ffc6f Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Tue, 26 Aug 2025 20:09:14 +0800 Subject: [PATCH 536/931] arm64: dts: apple: t8015: Fix PCIE power domains dependencies Fix the dependency topology of PCIE power domain nodes, as required by ANS2 NVME controller. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250826-t8015-nvme-v5-3-caee6ab00144@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8015-pmgr.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi index e238c2d2732f..1d8da9c7863e 100644 --- a/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi +++ b/arch/arm64/boot/dts/apple/t8015-pmgr.dtsi @@ -658,6 +658,7 @@ ps_pcie: power-controller@80318 { #power-domain-cells = <0>; #reset-cells = <0>; label = "pcie"; + power-domains = <&ps_pcie_aux>, <&ps_pcie_direct>, <&ps_pcie_ref>; }; ps_pcie_aux: power-controller@80320 { From eef7336dc6c11f80c08b55b09b24faf124baeb0d Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Tue, 26 Aug 2025 20:09:15 +0800 Subject: [PATCH 537/931] arm64: dts: apple: t8015: Add NVMe nodes Add nodes for NVMe and associated mailbox and sart for Apple A11 SoC. Signed-off-by: Nick Chan Link: https://lore.kernel.org/r/20250826-t8015-nvme-v5-4-caee6ab00144@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8015.dtsi | 34 ++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/apple/t8015.dtsi index e002ecee3390..794140eb7650 100644 --- a/arch/arm64/boot/dts/apple/t8015.dtsi +++ b/arch/arm64/boot/dts/apple/t8015.dtsi @@ -478,6 +478,40 @@ pinctrl_smc: pinctrl@236024000 { */ status = "disabled"; }; + + ans_mbox: mbox@257008000 { + compatible = "apple,t8015-asc-mailbox"; + reg = <0x2 0x57008000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + power-domains = <&ps_ans2>; + }; + + sart: iommu@259c50000 { + compatible = "apple,t8015-sart"; + reg = <0x2 0x59c50000 0x0 0x10000>; + power-domains = <&ps_ans2>; + }; + + nvme@259cc0000 { + compatible = "apple,t8015-nvme-ans2"; + reg = <0x2 0x59cc0000 0x0 0x40000>, + <0x2 0x59d20000 0x0 0x2000>; + reg-names = "nvme", "ans"; + interrupt-parent = <&aic>; + interrupts = ; + mboxes = <&ans_mbox>; + apple,sart = <&sart>; + power-domains = <&ps_ans2>, <&ps_pcie>; + power-domain-names = "ans", "apcie0"; + resets = <&ps_ans2>; + }; }; timer { From dfa743da83ab7ba51ec5692d5939ba1bab4b78c1 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Thu, 4 Sep 2025 12:42:48 -0700 Subject: [PATCH 538/931] MAINTAINERS: Add RISC-V T-HEAD SoC patchwork Add patchwork entry for RISC-V T-HEAD SoC support. Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index fe168477caa4..b77eb5cd1d38 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21718,6 +21718,7 @@ M: Guo Ren M: Fu Wei L: linux-riscv@lists.infradead.org S: Maintained +Q: https://patchwork.kernel.org/project/riscv-thead/list/ T: git https://github.com/pdp7/linux.git F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml F: Documentation/devicetree/bindings/firmware/thead,th1520-aon.yaml From 44b0a8e433aaad8aac51593a052f043aeb9a18d1 Mon Sep 17 00:00:00 2001 From: Denzeel Oliva Date: Thu, 4 Sep 2025 14:07:14 +0000 Subject: [PATCH 539/931] arm64: dts: exynos990: Enable PERIC0 and PERIC1 clock controllers Add clock controller nodes for PERIC0 and PERIC1 blocks for USI nodes. Signed-off-by: Denzeel Oliva Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos990.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi index bd5e086ac46d..7179109c49d0 100644 --- a/arch/arm64/boot/dts/exynos/exynos990.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi @@ -249,12 +249,34 @@ gic: interrupt-controller@10101000 { #size-cells = <1>; }; + cmu_peric0: clock-controller@10400000 { + compatible = "samsung,exynos990-cmu-peric0"; + reg = <0x10400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + pinctrl_peric0: pinctrl@10430000 { compatible = "samsung,exynos990-pinctrl"; reg = <0x10430000 0x1000>; interrupts = ; }; + cmu_peric1: clock-controller@10700000 { + compatible = "samsung,exynos990-cmu-peric1"; + reg = <0x10700000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; + clock-names = "oscclk", "bus", "ip"; + }; + pinctrl_peric1: pinctrl@10730000 { compatible = "samsung,exynos990-pinctrl"; reg = <0x10730000 0x1000>; From fdab01864390db7ef0bea28804c7a3147dc0a386 Mon Sep 17 00:00:00 2001 From: Marcin Juszkiewicz Date: Fri, 5 Sep 2025 13:02:30 +0200 Subject: [PATCH 540/931] arm64: dts: rockchip: enable HDMI Receiver on NanoPC T6 Let enable HDMI input port. Signed-off-by: Marcin Juszkiewicz Link: https://lore.kernel.org/r/579370818ef3b70b57bc5b8846f3b330d091d9a4.1757068166.git.marcin@juszkiewicz.com.pl Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index 3d8b6f0c5541..e647a30dca62 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -391,6 +391,17 @@ &hdmi1_sound { status = "okay"; }; +&hdmi_receiver_cma { + status = "okay"; +}; + +&hdmi_receiver { + hpd-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; + pinctrl-names = "default"; + status = "okay"; +}; + &hdptxphy0 { status = "okay"; }; @@ -629,6 +640,12 @@ usr_led_pin: usr-led-pin { }; }; + hdmirx { + hdmirx_hpd: hdmirx-5v-detection { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + headphone { hp_det: hp-det { rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; From 42bbc32c7e9e974ae4eb830ae1381cb016133e5c Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Fri, 1 Aug 2025 16:00:25 +0800 Subject: [PATCH 541/931] arm64: dts: rockchip: Add rk3528 CPU frequency scaling support By default, the CPUs on RK3528 operates at 1.5GHz. Add CPU frequency and voltage mapping to the device tree to enable dynamic scaling via cpufreq. The OPP values come from downstream kernel[1], using a voltage close to the actual frequency. Frequencies below 1.2GHz have been removed due to the same voltage. [1] https://github.com/rockchip-linux/kernel/blob/develop-5.10/arch/arm64/boot/dts/rockchip/rk3528.dtsi Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20250801080025.558935-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 39 ++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index db5dbcac7756..d5f8f7b9bf01 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -54,6 +54,7 @@ cpu0: cpu@0 { device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_clk SCMI_CLK_CPU>; + operating-points-v2 = <&cpu_opp_table>; }; cpu1: cpu@1 { @@ -62,6 +63,7 @@ cpu1: cpu@1 { device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_clk SCMI_CLK_CPU>; + operating-points-v2 = <&cpu_opp_table>; }; cpu2: cpu@2 { @@ -70,6 +72,7 @@ cpu2: cpu@2 { device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_clk SCMI_CLK_CPU>; + operating-points-v2 = <&cpu_opp_table>; }; cpu3: cpu@3 { @@ -78,6 +81,7 @@ cpu3: cpu@3 { device_type = "cpu"; enable-method = "psci"; clocks = <&scmi_clk SCMI_CLK_CPU>; + operating-points-v2 = <&cpu_opp_table>; }; }; @@ -96,6 +100,41 @@ scmi_clk: protocol@14 { }; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <875000 875000 1100000>; + clock-latency-ns = <40000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <925000 925000 1100000>; + clock-latency-ns = <40000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <975000 975000 1100000>; + clock-latency-ns = <40000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1037500 1037500 1100000>; + clock-latency-ns = <40000>; + }; + + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1100000 1100000 1100000>; + clock-latency-ns = <40000>; + }; + }; + gpu_opp_table: opp-table-gpu { compatible = "operating-points-v2"; From 31f5a855f706f8b14055b6b4df083c3997e42907 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Mon, 8 Sep 2025 09:26:55 +0200 Subject: [PATCH 542/931] ARM: dts: samsung: exynos5410: use multiple tuples for sromc ranges Preferred style is to have comma separated tuples when multiple addresses and sizes are defined in ranges. Therefore, change the format to clarify the node. Signed-off-by: Henrik Grimler Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/samsung/exynos5410.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/samsung/exynos5410.dtsi b/arch/arm/boot/dts/samsung/exynos5410.dtsi index 546035e78f40..350bc8d6aa5c 100644 --- a/arch/arm/boot/dts/samsung/exynos5410.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5410.dtsi @@ -372,10 +372,10 @@ &sss { &sromc { #address-cells = <2>; #size-cells = <1>; - ranges = <0 0 0x04000000 0x20000 - 1 0 0x05000000 0x20000 - 2 0 0x06000000 0x20000 - 3 0 0x07000000 0x20000>; + ranges = <0 0 0x04000000 0x20000>, + <1 0 0x05000000 0x20000>, + <2 0 0x06000000 0x20000>, + <3 0 0x07000000 0x20000>; }; &trng { From 6016813c888ec7d4a1f592eab3aebf289a42e865 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Mon, 8 Sep 2025 09:26:56 +0200 Subject: [PATCH 543/931] ARM: dts: samsung: exynos5250: describe sromc bank memory map According to public user manual for Exynos 5250 [1], the SROM controller has 4 banks, at same addresses as for example Exynos 5410. Describe the bank memory map of the SoC. [1] https://web.archive.org/web/20130921194458/http://www.samsung.com/global/business/semiconductor/file/product/Exynos_5_Dual_User_Manaul_Public_REV100-0.pdf Signed-off-by: Henrik Grimler Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/samsung/exynos5250.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos5250.dtsi b/arch/arm/boot/dts/samsung/exynos5250.dtsi index b9e7c4938818..4616794b19e8 100644 --- a/arch/arm/boot/dts/samsung/exynos5250.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5250.dtsi @@ -1214,6 +1214,15 @@ &serial_3 { dma-names = "rx", "tx"; }; +&sromc { + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x04000000 0x20000>, + <1 0 0x05000000 0x20000>, + <2 0 0x06000000 0x20000>, + <3 0 0x07000000 0x20000>; +}; + &sss { clocks = <&clock CLK_SSS>; clock-names = "secss"; From d19b1773362adfe8c0d5ccc4faf6aea0249976a6 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Mon, 8 Sep 2025 09:26:57 +0200 Subject: [PATCH 544/931] ARM: dts: samsung: smdk5250: add sromc node The smdk5250 board has an ethernet port which is connected to bank 1 of the SROM controller. Describe it. Signed-off-by: Henrik Grimler Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/samsung/exynos5250-smdk5250.dts | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts b/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts index bb623726ef1e..6af1f64c984b 100644 --- a/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/samsung/exynos5250-smdk5250.dts @@ -422,6 +422,43 @@ max77686_irq: max77686-irq-pins { samsung,pin-pud = ; samsung,pin-drv = ; }; + + srom_ctl: srom-ctl-pins { + samsung,pins = "gpy0-3", "gpy0-4", "gpy0-5", + "gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3"; + samsung,pin-function = ; + samsung,pin-drv = ; + }; + + srom_ebi: srom-ebi-pins { + samsung,pins = "gpy3-0", "gpy3-1", "gpy3-2", "gpy3-3", + "gpy3-4", "gpy3-5", "gpy3-6", "gpy3-7", + "gpy5-0", "gpy5-1", "gpy5-2", "gpy5-3", + "gpy5-4", "gpy5-5", "gpy5-6", "gpy5-7", + "gpy6-0", "gpy6-1", "gpy6-2", "gpy6-3", + "gpy6-4", "gpy6-5", "gpy6-6", "gpy6-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&sromc { + pinctrl-names = "default"; + pinctrl-0 = <&srom_ctl>, <&srom_ebi>; + + ethernet@1,0 { + compatible = "smsc,lan9115"; + reg = <1 0 0x100>; + phy-mode = "mii"; + smsc,irq-push-pull; + interrupt-parent = <&gpx0>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + reg-io-width = <2>; + + samsung,srom-page-mode; + samsung,srom-timing = <9 12 1 6 1 1>; + }; }; &usbdrd { From fad32e8ac460198d086c6468dafe47ecbd9d03e8 Mon Sep 17 00:00:00 2001 From: Hongliang Yang Date: Wed, 3 Sep 2025 16:47:13 +0800 Subject: [PATCH 545/931] arm64: dts: cix: add DT nodes for all I2C and I3C ports for sky1 The CIX SKY1 SoC supports the integration of 8 I2C bus controllers and 2 I3C bus controllers. Signed-off-by: Hongliang Yang Signed-off-by: Jun Guo Signed-off-by: Peter Chen --- arch/arm64/boot/dts/cix/sky1.dtsi | 100 ++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index 7dfe7677e649..2fb2c99c0796 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -192,6 +192,78 @@ soc@0 { #address-cells = <2>; #size-cells = <2>; + i2c0: i2c@4010000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04010000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C0_APB>; + interrupts = ; + status = "disabled"; + }; + + i2c1: i2c@4020000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04020000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C1_APB>; + interrupts = ; + status = "disabled"; + }; + + i2c2: i2c@4030000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04030000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C2_APB>; + interrupts = ; + status = "disabled"; + }; + + i2c3: i2c@4040000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04040000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C3_APB>; + interrupts = ; + status = "disabled"; + }; + + i2c4: i2c@4050000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04050000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C4_APB>; + interrupts = ; + status = "disabled"; + }; + + i2c5: i2c@4060000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04060000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C5_APB>; + interrupts = ; + status = "disabled"; + }; + + i2c6: i2c@4070000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04070000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C6_APB>; + interrupts = ; + status = "disabled"; + }; + + i2c7: i2c@4080000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x04080000 0x0 0x10000>; + clock-frequency = <400000>; + clocks = <&scmi_clk CLK_TREE_FCH_I2C7_APB>; + interrupts = ; + status = "disabled"; + }; + uart0: serial@40b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0x040b0000 0x0 0x1000>; @@ -228,6 +300,34 @@ uart3: serial@40e0000 { status = "disabled"; }; + i3c0: i3c@40f0000 { + compatible = "cdns,i3c-master"; + reg = <0x0 0x040f0000 0x0 0x10000>; + #address-cells = <3>; + #size-cells = <0>; + interrupts = ; + clocks = <&scmi_clk CLK_TREE_FCH_I3C0_APB>, + <&scmi_clk CLK_TREE_FCH_I3C0_FUNC>; + clock-names = "pclk", "sysclk"; + i3c-scl-hz = <400000>; + i2c-scl-hz = <100000>; + status = "disabled"; + }; + + i3c1: i3c@4100000 { + compatible = "cdns,i3c-master"; + reg = <0x0 0x04100000 0x0 0x10000>; + #address-cells = <3>; + #size-cells = <0>; + interrupts = ; + clocks = <&scmi_clk CLK_TREE_FCH_I3C1_APB>, + <&scmi_clk CLK_TREE_FCH_I3C1_FUNC>; + clock-names = "pclk", "sysclk"; + i3c-scl-hz = <400000>; + i2c-scl-hz = <100000>; + status = "disabled"; + }; + mbox_ap2se: mailbox@5060000 { compatible = "cix,sky1-mbox"; reg = <0x0 0x05060000 0x0 0x10000>; From 7c6de7511149da119b3aa9476ce5f746b9a3c786 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Wed, 3 Sep 2025 20:43:31 +0530 Subject: [PATCH 546/931] arm64: dts: qcom: qcs6490-audioreach: Add AudioReach support for QCS6490 Introduce qcs6490-audioreach.dtsi to support AudioReach architecture on QCS6490 platforms. The existing ADSP Bypass DTSI files such as sc7280.dtsi, which is tailored for ADSP Bypass architecture as they lack DSP-specific nodes required for AudioReach. The new qcs6490-audioreach.dtsi file defines nodes for AudioReach specific components such as APM (Audio Process Manager), PRM (Proxy Resource Manager), and GPR (Generic Packet Router). This change enable the audio from the legacy ADSP Bypass solution to the AudioReach framework. Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250903151337.1037246-3-mohammad.rafi.shaik@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcs6490-audioreach.dtsi | 52 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 2 files changed, 53 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi diff --git a/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi b/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi new file mode 100644 index 000000000000..980499fb3c35 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Common definitions for SC7280-based boards with AudioReach. + */ + +#include +#include +#include +#include + +&remoteproc_adsp_glink { + /delete-node/ apr; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1801 0x0>; + }; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 8561fc217229..9fa294cc9a3e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3944,7 +3944,7 @@ remoteproc_adsp: remoteproc@3700000 { status = "disabled"; - glink-edge { + remoteproc_adsp_glink: glink-edge { interrupts-extended = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; From eec852a4c84259c0fe68aaaed60c26dbf49b4ff2 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Wed, 3 Sep 2025 20:43:32 +0530 Subject: [PATCH 547/931] arm64: dts: qcom: sc7280: Add WSA SoundWire and LPASS support Add WSA LPASS macro Codec along with SoundWire controller. Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250903151337.1037246-4-mohammad.rafi.shaik@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 77 ++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 9fa294cc9a3e..4f7aca76f364 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -2773,6 +2774,66 @@ swr1: soundwire@3230000 { status = "disabled"; }; + lpass_wsa_macro: codec@3240000 { + compatible = "qcom,sc7280-lpass-wsa-macro"; + reg = <0x0 0x03240000 0x0 0x1000>; + + clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, + <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names = "mclk", + "npl", + "macro", + "dcodec", + "fsgen"; + + pinctrl-0 = <&lpass_wsa_swr_clk>, <&lpass_wsa_swr_data>; + pinctrl-names = "default"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + + swr2: soundwire@3250000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0x0 0x03250000 0x0 0x2000>; + + interrupts = ; + clocks = <&lpass_wsa_macro>; + clock-names = "iface"; + + resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; + reset-names = "swr_audio_cgcr"; + + qcom,din-ports = <2>; + qcom,dout-ports = <6>; + + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 + 0x1f 0x3f 0x0f 0x0f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 + 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + lpass_audiocc: clock-controller@3300000 { compatible = "qcom,sc7280-lpassaudiocc"; reg = <0 0x03300000 0 0x30000>, @@ -2976,6 +3037,22 @@ lpass_tx_swr_data: tx-swr-data-state { pins = "gpio1", "gpio2", "gpio14"; function = "swr_tx_data"; }; + + lpass_wsa_swr_clk: wsa-swr-clk-state { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + lpass_wsa_swr_data: wsa-swr-data-state { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; }; gpu: gpu@3d00000 { From d3c438554c6600fdc49430279e147aae1cb33876 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Wed, 3 Sep 2025 20:43:33 +0530 Subject: [PATCH 548/931] arm64: dts: qcom: qcs6490-audioreach: Enable LPASS macros clock settings for audioreach Enable LPASS macros (WSA, VA, RX, TX) and the lpass_tlmm clock required for audioreach functionality. In audioreach solution mclk, npl, and fsgen clocks are managed via the Q6PRM. On SC7280-based boards, the TX CORE clock is used to drive both RX and WSA audio paths following as per hardware design. Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250903151337.1037246-5-mohammad.rafi.shaik@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcs6490-audioreach.dtsi | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi b/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi index 980499fb3c35..bdf4b6c3fc6d 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi @@ -10,6 +10,67 @@ #include #include +&lpass_rx_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names = "mclk", + "npl", + "macro", + "dcodec", + "fsgen"; +}; + +&lpass_tlmm { + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", + "audio"; +}; + +&lpass_tx_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names = "mclk", + "npl", + "macro", + "dcodec", + "fsgen"; +}; + +&lpass_va_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks = <&q6prmcc LPASS_CLK_ID_VA_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", + "macro", + "dcodec"; +}; + +&lpass_wsa_macro { + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names = "mclk", + "npl", + "macro", + "dcodec", + "fsgen"; +}; + &remoteproc_adsp_glink { /delete-node/ apr; From b6b4c9f76a8b173a1a1455d181d19b5ab8842a47 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Wed, 3 Sep 2025 20:43:34 +0530 Subject: [PATCH 549/931] arm64: dts: qcom: qcs6490-rb3gen2: Add WSA8830 speakers amplifier Add nodes for WSA8830 speakers amplifier on qcs6490-rb3gen2 board. Enable lpass_wsa and lpass_va macros along with pinctrl settings for audio. Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250903151337.1037246-6-mohammad.rafi.shaik@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcs6490-audioreach.dtsi | 6 ++++ arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 35 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 +++++ 3 files changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi b/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi index bdf4b6c3fc6d..c1867711298b 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi @@ -56,6 +56,12 @@ &lpass_va_macro { clock-names = "mclk", "macro", "dcodec"; + + pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>, + <&lpass_dmic23_clk>, <&lpass_dmic23_data>; + pinctrl-names = "default"; + + qcom,dmic-sample-rate = <4800000>; }; &lpass_wsa_macro { diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 7509c27bd3f8..09e2cb9053a6 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -19,6 +19,7 @@ #include "pm7325.dtsi" #include "pm8350c.dtsi" #include "pmk8350.dtsi" +#include "qcs6490-audioreach.dtsi" /delete-node/ &ipa_fw_mem; /delete-node/ &rmtfs_mem; @@ -765,6 +766,14 @@ redriver_usb_con_sbu: endpoint { }; }; +&lpass_va_macro { + status = "okay"; +}; + +&lpass_wsa_macro { + status = "okay"; +}; + &mdss { status = "okay"; }; @@ -1039,6 +1048,32 @@ &sdhc_2 { status = "okay"; }; +&swr2 { + status = "okay"; + + left_spkr: speaker@0,1 { + compatible = "sdw10217020200"; + reg = <0 1>; + reset-gpios = <&tlmm 158 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #thermal-sensor-cells = <0>; + vdd-supply = <&vreg_l18b_1p8>; + qcom,port-mapping = <1 2 3 7>; + }; + + right_spkr: speaker@0,2 { + compatible = "sdw10217020200"; + reg = <0 2>; + reset-gpios = <&tlmm 158 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + #thermal-sensor-cells = <0>; + vdd-supply = <&vreg_l18b_1p8>; + qcom,port-mapping = <4 5 6 8>; + }; +}; + &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 4f7aca76f364..5b78d111b2f2 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3001,21 +3001,29 @@ lpass_tlmm: pinctrl@33c0000 { lpass_dmic01_clk: dmic01-clk-state { pins = "gpio6"; function = "dmic1_clk"; + drive-strength = <8>; + bias-disable; }; lpass_dmic01_data: dmic01-data-state { pins = "gpio7"; function = "dmic1_data"; + drive-strength = <8>; + bias-pull-down; }; lpass_dmic23_clk: dmic23-clk-state { pins = "gpio8"; function = "dmic2_clk"; + drive-strength = <8>; + bias-disable; }; lpass_dmic23_data: dmic23-data-state { pins = "gpio9"; function = "dmic2_data"; + drive-strength = <8>; + bias-pull-down; }; lpass_rx_swr_clk: rx-swr-clk-state { From 48b5ea6de47f58a0b5d1641ea8eb78157666d4a5 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Wed, 3 Sep 2025 20:43:35 +0530 Subject: [PATCH 550/931] arm64: dts: qcom: qcs6490-rb3gen2: Add sound card Add the sound card node with tested playback over WSA8835 speakers and digital on-board mics. Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250903151337.1037246-7-mohammad.rafi.shaik@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 45 ++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 09e2cb9053a6..18cea8812001 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1048,6 +1048,51 @@ &sdhc_2 { status = "okay"; }; +&sound { + compatible = "qcom,qcs6490-rb3gen2-sndcard"; + model = "QCS6490-RB3Gen2"; + + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "VA DMIC2", "vdd-micb", + "VA DMIC3", "vdd-micb"; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, + <&swr2 0>, <&lpass_wsa_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_va_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; +}; + &swr2 { status = "okay"; From aa04c298619ff2621691ef1df5e243637d777222 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Wed, 3 Sep 2025 20:43:36 +0530 Subject: [PATCH 551/931] arm64: dts: qcom: qcm6490-idp: Add WSA8830 speakers and WCD9370 headset codec Add nodes for WSA8830 speakers and WCD9370 headset codec on qcm6490-idp board and enable lpass macros along with audio support pin controls. Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250903151337.1037246-8-mohammad.rafi.shaik@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 123 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 +++ 2 files changed, 135 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 8ed6e28b0c29..379ee346a33a 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -18,6 +18,7 @@ #include "pm7325.dtsi" #include "pm8350c.dtsi" #include "pmk8350.dtsi" +#include "qcs6490-audioreach.dtsi" /delete-node/ &ipa_fw_mem; /delete-node/ &rmtfs_mem; @@ -169,6 +170,30 @@ vph_pwr: vph-pwr-regulator { regulator-min-microvolt = <3700000>; regulator-max-microvolt = <3700000>; }; + + wcd9370: audio-codec-0 { + compatible = "qcom,wcd9370-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>; + + vdd-buck-supply = <&vreg_l17b_1p7>; + vdd-rxtx-supply = <&vreg_l18b_1p8>; + vdd-px-supply = <&vreg_l18b_1p8>; + vdd-mic-bias-supply = <&vreg_bob_3p296>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + + qcom,rx-device = <&wcd937x_rx>; + qcom,tx-device = <&wcd937x_tx>; + + #sound-dai-cells = <1>; + }; }; &apps_rsc { @@ -536,6 +561,22 @@ &gpu_zap_shader { firmware-name = "qcom/qcm6490/a660_zap.mbn"; }; +&lpass_rx_macro { + status = "okay"; +}; + +&lpass_tx_macro { + status = "okay"; +}; + +&lpass_va_macro { + status = "okay"; +}; + +&lpass_wsa_macro { + status = "okay"; +}; + &mdss { status = "okay"; }; @@ -716,6 +757,81 @@ &sdhc_2 { cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; }; +&swr0 { + status = "okay"; + + wcd937x_rx: codec@0,4 { + compatible = "sdw20217010a00"; + reg = <0 4>; + + /* + * WCD9370 RX Port 1 (HPH_L/R) <==> SWR1 Port 1 (HPH_L/R) + * WCD9370 RX Port 2 (CLSH) <==> SWR1 Port 2 (CLSH) + * WCD9370 RX Port 3 (COMP_L/R) <==> SWR1 Port 3 (COMP_L/R) + * WCD9370 RX Port 4 (LO) <==> SWR1 Port 4 (LO) + * WCD9370 RX Port 5 (DSD_L/R) <==> SWR1 Port 5 (DSD) + */ + qcom,rx-port-mapping = <1 2 3 4 5>; + + /* + * Static channels mapping between slave and master rx port channels. + * In the order of slave port channels, which is + * hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l. + */ + qcom,rx-channel-mapping = /bits/ 8 <1 2 1 1 2 1 1 2>; + }; +}; + +&swr1 { + status = "okay"; + + wcd937x_tx: codec@0,3 { + compatible = "sdw20217010a00"; + reg = <0 3>; + + /* + * WCD9370 TX Port 1 (ADC1) <=> SWR2 Port 2 + * WCD9370 TX Port 2 (ADC2, 3) <=> SWR2 Port 2 + * WCD9370 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 + * WCD9370 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 + */ + qcom,tx-port-mapping = <1 1 2 3>; + + /* + * Static channel mapping between slave and master tx port channels. + * In the order of slave port channels which is adc1, adc2, adc3, + * mic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7. + */ + qcom,tx-channel-mapping = /bits/ 8 <1 2 1 1 2 3 3 4 1 2 3 4>; + }; +}; + +&swr2 { + status = "okay"; + + left_spkr: speaker@0,1 { + compatible = "sdw10217020200"; + reg = <0 1>; + powerdown-gpios = <&tlmm 63 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #thermal-sensor-cells = <0>; + vdd-supply = <&vreg_l18b_1p8>; + qcom,port-mapping = <1 2 3 7>; + }; + + right_spkr: speaker@0,2 { + compatible = "sdw10217020200"; + reg = <0 2>; + powerdown-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + #thermal-sensor-cells = <0>; + vdd-supply = <&vreg_l18b_1p8>; + qcom,port-mapping = <4 5 6 8>; + }; +}; + &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ @@ -725,6 +841,13 @@ sd_cd: sd-cd-state { function = "gpio"; bias-pull-up; }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio83"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; }; &uart5 { diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5b78d111b2f2..4ac909214a86 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3029,21 +3029,33 @@ lpass_dmic23_data: dmic23-data-state { lpass_rx_swr_clk: rx-swr-clk-state { pins = "gpio3"; function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; }; lpass_rx_swr_data: rx-swr-data-state { pins = "gpio4", "gpio5"; function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; }; lpass_tx_swr_clk: tx-swr-clk-state { pins = "gpio0"; function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; }; lpass_tx_swr_data: tx-swr-data-state { pins = "gpio1", "gpio2", "gpio14"; function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; }; lpass_wsa_swr_clk: wsa-swr-clk-state { From 7fd5b4a203cf88d1ad87aff27f9f23aed7b6dbd4 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Wed, 3 Sep 2025 20:43:37 +0530 Subject: [PATCH 552/931] arm64: dts: qcom: qcm6490-idp: Add sound card Add the sound card node with tested playback over WSA8835 speakers, digital on-board mics along with wcd9370 headset playabck and record. Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250903151337.1037246-9-mohammad.rafi.shaik@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 84 ++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 379ee346a33a..73fce639370c 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -757,6 +757,90 @@ &sdhc_2 { cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; }; +&sound { + compatible = "qcom,qcm6490-idp-sndcard"; + model = "QCM6490-IDP"; + + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "MIC BIAS2", + "TX DMIC2", "MIC BIAS3", + "TX SWR_ADC1", "ADC2_OUTPUT", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1"; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, + <&swr2 0>, <&lpass_wsa_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd9370 0>, <&swr0 0>, <&lpass_rx_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd9370 1>, <&swr1 0>, <&lpass_tx_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_va_macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; +}; + &swr0 { status = "okay"; From 49e55bdbcbe0abf04d7c8c882d69755ecf43d878 Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Sat, 6 Sep 2025 00:53:47 +0530 Subject: [PATCH 553/931] dt-bindings: arm: qcom: Add Monaco EVK support Introduce new bindings for the Monaco Evaluation Kit (EVK), an IoT board based on the QCS8300 SoC. Signed-off-by: Umang Chheda Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250905192350.1223812-2-umang.chheda@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1fc6319bec6b..2698ba87cd93 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -849,6 +849,7 @@ properties: - items: - enum: + - qcom,monaco-evk - qcom,qcs8300-ride - const: qcom,qcs8300 From 117d6bc9326b1ff38591289f9677e273a9a467ae Mon Sep 17 00:00:00 2001 From: Umang Chheda Date: Sat, 6 Sep 2025 00:53:48 +0530 Subject: [PATCH 554/931] arm64: dts: qcom: qcs8300: Add Monaco EVK board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Monaco EVK is a single board computer, based on the Qualcomm QCS8300 SoC, with the following features : - Storage: 1 × 128 GB UFS, micro-SD card, EEPROMs for MACs, and eMMC. - Audio/Video, Camera & Display ports. - Connectivity: RJ45 2.5GbE, WLAN/Bluetooth, CAN/CAN-FD. - PCIe ports. - USB & UART ports. On top of Monaco EVK board additional mezzanine boards can be stacked in future. Add support for the following components : - GPI (Generic Peripheral Interface) and QUPv3-0/1 controllers to facilitate DMA and peripheral communication. - TCA9534 I/O expander via I2C to provide 8 additional GPIO lines for extended I/O functionality. - USB1 controller in device mode to support USB peripheral operations. USB OTG mode will be enabled for USB1 controller once the VBUS control based on ID pin is implemented in hd3ss3220.c. - Remoteproc subsystems for supported DSPs such as Audio DSP, Compute DSP and Generic DSP, along with their corresponding firmware. - Configure nvmem-layout on the I2C EEPROM to store data for Ethernet and other consumers. - QCA8081 2.5G Ethernet PHY on port-0 and expose the Ethernet MAC address via nvmem for network configuration. It depends on CONFIG_QCA808X_PHY to use QCA8081 PHY. - Support for the Iris video codec. Written with inputs from : Rakesh Kota - Regulators. Nirmesh Kumar Singh - GPIO expander. Viken Dadhaniya - GPI/QUP. Mohd Ayaan Anwar - Ethernet. Monish Chunara - EEPROM. Vikash Garodia - Iris Video codec. Swati Agarwal - USB. Signed-off-by: Umang Chheda Link: https://lore.kernel.org/r/20250905192350.1223812-3-umang.chheda@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/monaco-evk.dts | 449 ++++++++++++++++++++++++ 2 files changed, 450 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 0a7c308dec36..0e4e0e0b833b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb +dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts new file mode 100644 index 000000000000..93e9e5322a39 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -0,0 +1,449 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include + +#include "qcs8300.dtsi" +#include "qcs8300-pmics.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco EVK"; + compatible = "qcom,monaco-evk", "qcom,qcs8300"; + + aliases { + ethernet0 = ðernet0; + i2c1 = &i2c1; + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s5c: smps5 { + regulator-name = "vreg_s5c"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + }; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <512000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + +ðernet0 { + phy-mode = "2500base-x"; + phy-handle = <&hsgmii_phy0>; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + nvmem-cells = <&mac_addr0>; + nvmem-cell-names = "mac-address"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + hsgmii_phy0: ethernet-phy@1c { + compatible = "ethernet-phy-id004d.d101"; + reg = <0x1c>; + reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-names = "default"; + + status = "okay"; + + eeprom0: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + mac_addr0: mac-addr@0 { + reg = <0x0 0x6>; + }; + }; + }; +}; + +&i2c15 { + pinctrl-0 = <&qup_i2c15_default>; + pinctrl-names = "default"; + + status = "okay"; + + expander0: gpio@38 { + compatible = "ti,tca9538"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander1: gpio@39 { + compatible = "ti,tca9538"; + reg = <0x39>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander2: gpio@3a { + compatible = "ti,tca9538"; + reg = <0x3a>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander3: gpio@3b { + compatible = "ti,tca9538"; + reg = <0x3b>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander4: gpio@3c { + compatible = "ti,tca9538"; + reg = <0x3c>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander5: gpio@3d { + compatible = "ti,tca9538"; + reg = <0x3d>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander6: gpio@3e { + compatible = "ti,tca9538"; + reg = <0x3e>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&iris { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs8300/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs8300/cdsp0.mbn"; + + status = "okay"; +}; + +&remoteproc_gpdsp { + firmware-name = "qcom/qcs8300/gpdsp0.mbn"; + + status = "okay"; +}; + +&serdes0 { + phy-supply = <&vreg_l4a>; + + status = "okay"; +}; + +&tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio5"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio6"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + qup_i2c1_default: qup-i2c1-state { + pins = "gpio19", "gpio20"; + function = "qup0_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c15_default: qup-i2c15-state { + pins = "gpio91", "gpio92"; + function = "qup1_se7"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&uart7 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l8a>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l4c>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l7c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; From 89c85214735b633e846d8f6473fa57ba4cc11b81 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Sat, 6 Sep 2025 00:53:49 +0530 Subject: [PATCH 555/931] arm64: dts: qcom: qcs8300: Add gpr node Add GPR(Generic Pack router) node along with APM(Audio Process Manager) and PRM(Proxy resource Manager) audio services. Signed-off-by: Mohammad Rafi Shaik Signed-off-by: Umang Chheda Link: https://lore.kernel.org/r/20250905192350.1223812-4-umang.chheda@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 40 +++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 5edb137d1471..8ae843567ea4 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -18,6 +18,7 @@ #include #include #include +#include #include / { @@ -2427,6 +2428,45 @@ compute-cb@5 { dma-coherent; }; }; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x2001 0x0>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; }; }; From bb12da95a183253b619ca1691d6fd320b7e445e9 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Sat, 6 Sep 2025 00:53:50 +0530 Subject: [PATCH 556/931] arm64: dts: qcom: monaco-evk: Add sound card Add the sound card for monaco-evk board and verified playback functionality using the max98357a I2S speaker amplifier and I2S microphones. The max98357a speaker amplifier is connected via High-Speed MI2S HS0 interface, while the microphones utilize the Secondary MI2S interface and also enable required pin controller gpios for audio. Signed-off-by: Mohammad Rafi Shaik Signed-off-by: Umang Chheda Link: https://lore.kernel.org/r/20250905192350.1223812-5-umang.chheda@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 52 +++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 ++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index 93e9e5322a39..f3c5d363921e 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include "qcs8300.dtsi" @@ -24,6 +25,57 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + dmic: audio-codec-0 { + compatible = "dmic-codec"; + #sound-dai-cells = <0>; + num-channels = <1>; + }; + + max98357a: audio-codec-1 { + compatible = "maxim,max98357a"; + #sound-dai-cells = <0>; + }; + + sound { + compatible = "qcom,qcs8275-sndcard"; + model = "MONACO-EVK"; + + pinctrl-0 = <&hs0_mi2s_active>, <&mi2s1_active>; + pinctrl-names = "default"; + + hs0-mi2s-playback-dai-link { + link-name = "HS0 MI2S Playback"; + + codec { + sound-dai = <&max98357a>; + }; + + cpu { + sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + sec-mi2s-capture-dai-link { + link-name = "Secondary MI2S Capture"; + + codec { + sound-dai = <&dmic>; + }; + + cpu { + sound-dai = <&q6apmbedai SECONDARY_MI2S_TX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; }; &apps_rsc { diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 8ae843567ea4..8afd77a2d737 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -4804,6 +4804,43 @@ tlmm: pinctrl@f100000 { #interrupt-cells = <2>; wakeup-parent = <&pdc>; + hs0_mi2s_active: hs0-mi2s-active-state { + pins = "gpio106", "gpio107", "gpio108", "gpio109"; + function = "hs0_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + mi2s1_active: mi2s1-active-state { + data0-pins { + pins = "gpio100"; + function = "mi2s1_data0"; + drive-strength = <8>; + bias-disable; + }; + + data1-pins { + pins = "gpio101"; + function = "mi2s1_data1"; + drive-strength = <8>; + bias-disable; + }; + + sclk-pins { + pins = "gpio98"; + function = "mi2s1_sck"; + drive-strength = <8>; + bias-disable; + }; + + ws-pins { + pins = "gpio99"; + function = "mi2s1_ws"; + drive-strength = <8>; + bias-disable; + }; + }; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { pins = "gpio17", "gpio18"; function = "qup0_se0"; From 08128670a931a4117f7b93c703d0186c67c9e1e2 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Wed, 3 Sep 2025 03:13:35 -0700 Subject: [PATCH 557/931] riscv: dts: starfive: jh7110-common: drop no-mmc property from mmc1 Relax no-mmc restriction on mmc1 for jh7110 boards. The restriction is only needed to block use of commands that would cause a device to malfunction, which by testing and observation [1] is not any problem. 1: https://lore.kernel.org/lkml/NT0PR01MB1312E0D9EE9F158A57B77700E63D2@NT0PR01MB1312.CHNPR01.prod.partner.outlook.cn/ Signed-off-by: E Shattow Tested-by: Hal Feng Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index a315113840e5..4fa77ffd54e3 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -299,7 +299,6 @@ &mmc1 { assigned-clock-rates = <50000000>; bus-width = <4>; bootph-pre-ram; - no-mmc; cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; disable-wp; cap-sd-highspeed; From b5a861a438d1a456952665cf6167969f01209479 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Wed, 3 Sep 2025 03:13:36 -0700 Subject: [PATCH 558/931] riscv: dts: starfive: jh7110-common: drop mmc post-power-on-delay-ms Drop post-power-on-delay-ms from mmc0 mmc1 interfaces. There is no known reason for these properties to continue, testing appears to be fine without them [1]. 1: https://lore.kernel.org/lkml/NT0PR01MB1312E0D9EE9F158A57B77700E63D2@NT0PR01MB1312.CHNPR01.prod.partner.outlook.cn/ Signed-off-by: E Shattow Tested-by: Hal Feng Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index 4fa77ffd54e3..5dc15e48b74b 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -285,7 +285,6 @@ &mmc0 { mmc-ddr-1_8v; mmc-hs200-1_8v; cap-mmc-hw-reset; - post-power-on-delay-ms = <200>; pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; vmmc-supply = <&vcc_3v3>; @@ -302,7 +301,6 @@ &mmc1 { cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; disable-wp; cap-sd-highspeed; - post-power-on-delay-ms = <200>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; status = "okay"; From 3374b5fb26b300809ecd6aed9f414987dd17c313 Mon Sep 17 00:00:00 2001 From: Guoqing Jiang Date: Mon, 21 Jul 2025 17:59:59 +0800 Subject: [PATCH 559/931] arm64: dts: mediatek: mt8195: Remove suspend-breaking reset from pcie0 When test suspend resume with 6.8 based kernel, system can't resume and I got below error which can be also reproduced with 6.16 rc6+ kernel. mtk-pcie-gen3 112f0000.pcie: PCIe link down, current LTSSM state: detect.quiet (0x0) mtk-pcie-gen3 112f0000.pcie: PM: dpm_run_callback(): genpd_resume_noirq returns -110 mtk-pcie-gen3 112f0000.pcie: PM: failed to resume noirq: error -110 After investigation, looks pcie0 has the same problem as pcie1 as decribed in commit 3d7fdd8e38aa ("arm64: dts: mediatek: mt8195: Remove suspend-breaking reset from pcie1"). Fixes: ecc0af6a3fe6 ("arm64: dts: mt8195: Add pcie and pcie phy nodes") Signed-off-by: Guoqing Jiang Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Macpaul Lin Link: https://lore.kernel.org/r/20250721095959.57703-1-guoqing.jiang@canonical.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 8877953ce292..ab0b2f606eb4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1588,9 +1588,6 @@ pcie0: pcie@112f0000 { power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; - resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; - reset-names = "mac"; - #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc0 0>, From 0aeb7ed4bcb244862a35f880053cd64d28c6fb04 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 22 Jul 2025 12:11:52 -0500 Subject: [PATCH 560/931] arm64: dts: mediatek: mt8183: Fix out of range pull values A value of 10 is not valid for "mediatek,pull-down-adv" and "mediatek,pull-up-adv" properties which have defined values of 0-3. It appears the "10" was written as a binary value. The driver only looks at the lowest 2 bits, so the value "10" decimal works out the same as if "2" was used. Fixes: cd894e274b74 ("arm64: dts: mt8183: Add krane-sku176 board") Fixes: 19b6403f1e2a ("arm64: dts: mt8183: add mt8183 pumpkin board") Signed-off-by: Rob Herring (Arm) Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250722171152.58923-2-robh@kernel.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 14 +++++++------- arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 14 +++++++------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 400c61d11035..fff93e26eb76 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -580,7 +580,7 @@ pins-cmd-dat { pins-clk { pinmux = ; drive-strength = ; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins-rst { @@ -609,13 +609,13 @@ pins-cmd-dat { pins-clk { pinmux = ; drive-strength = ; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins-ds { pinmux = ; drive-strength = ; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins-rst { @@ -633,13 +633,13 @@ pins-cmd-dat { , ; input-enable; - mediatek,pull-up-adv = <10>; + mediatek,pull-up-adv = <2>; }; pins-clk { pinmux = ; input-enable; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; }; @@ -652,13 +652,13 @@ pins-cmd-dat { ; drive-strength = <6>; input-enable; - mediatek,pull-up-adv = <10>; + mediatek,pull-up-adv = <2>; }; pins-clk { pinmux = ; drive-strength = <8>; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; input-enable; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index dbdee604edab..7c3010889ae7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -324,7 +324,7 @@ pins_cmd_dat { pins_clk { pinmux = ; drive-strength = ; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins_rst { @@ -353,13 +353,13 @@ pins_cmd_dat { pins_clk { pinmux = ; drive-strength = ; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins_ds { pinmux = ; drive-strength = ; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins_rst { @@ -377,13 +377,13 @@ pins_cmd_dat { , ; input-enable; - mediatek,pull-up-adv = <10>; + mediatek,pull-up-adv = <2>; }; pins_clk { pinmux = ; input-enable; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; }; pins_pmu { @@ -401,13 +401,13 @@ pins_cmd_dat { ; drive-strength = <6>; input-enable; - mediatek,pull-up-adv = <10>; + mediatek,pull-up-adv = <2>; }; pins_clk { pinmux = ; drive-strength = <8>; - mediatek,pull-down-adv = <10>; + mediatek,pull-down-adv = <2>; input-enable; }; }; From d22e9b8c96452ae0fead5e26651be66fe298100e Mon Sep 17 00:00:00 2001 From: Julien Massot Date: Fri, 5 Sep 2025 15:21:19 +0200 Subject: [PATCH 561/931] arm64: dts: mediatek: mt8395-nio-12l: Enable UFS UFS is the primary storage for the Radxa NIO 12L. Enable it now that the ufshci and ufsphy nodes are available in the common mt8195 dtsi. Signed-off-by: Julien Massot Link: https://lore.kernel.org/r/20250905-radxa-nio-12l-ufs-v1-1-e2468bfd2c69@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index 329c60cc6a6b..4cbd78c126f6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -990,6 +990,16 @@ &uart1 { status = "okay"; }; +&ufshci { + vcc-supply = <&mt6359_vemc_1_ldo_reg>; + vccq2-supply = <&mt6359_vufs_ldo_reg>; + status = "okay"; +}; + +&ufsphy { + status = "okay"; +}; + &ssusb0 { pinctrl-names = "default"; pinctrl-0 = <&usb3_port0_pins>; From 1383007f85fbb06aac5061b756b1ae4e701fef59 Mon Sep 17 00:00:00 2001 From: Julien Massot Date: Fri, 5 Sep 2025 13:51:59 +0200 Subject: [PATCH 562/931] arm64: dts: mediatek: mt8395-nio-12l: add PMIC and GPIO keys support Add support for PMIC and GPIO keys on the Radxa NIO 12L board: Declare a gpio-keys node for the Volume Up button using GPIO106. Add the corresponding pin configuration in the pinctrl node. Add a mediatek,mt6359-keys subnode under the PMIC to handle the power and home buttons exposed by the MT6359. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Julien Massot Link: https://lore.kernel.org/r/20250905-radxa-nio-12-l-gpio-v3-2-40f11377fb55@collabora.com Signed-off-by: Matthias Brugger --- .../dts/mediatek/mt8395-radxa-nio-12l.dts | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index 4cbd78c126f6..d32f973f5e05 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -8,6 +8,7 @@ #include "mt8195.dtsi" #include "mt6359.dtsi" #include +#include #include #include #include @@ -60,6 +61,18 @@ backlight: backlight { status = "disabled"; }; + keys: gpio-keys { + compatible = "gpio-keys"; + + button-volume-up { + wakeup-source; + debounce-interval = <100>; + gpios = <&pio 106 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = ; + }; + }; + wifi_vreg: regulator-wifi-3v3-en { compatible = "regulator-fixed"; regulator-name = "wifi_3v3_en"; @@ -626,6 +639,14 @@ pins-txd { }; }; + gpio_key_pins: gpio-keys-pins { + pins { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; + i2c2_pins: i2c2-pins { pins-bus { pinmux = , @@ -880,6 +901,21 @@ &pciephy { &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + + mt6359keys: keys { + compatible = "mediatek,mt6359-keys"; + mediatek,long-press-mode = <1>; + power-off-time-sec = <0>; + + power-key { + linux,keycodes = ; + wakeup-source; + }; + + home { + linux,keycodes = ; + }; + }; }; &scp { From 0da6f7a0ab5322eb6d091a9c89d799adfeae078d Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski Date: Sun, 7 Sep 2025 13:15:09 +0200 Subject: [PATCH 563/931] arm64: dts: mediatek: add thermal sensor support on mt7981 The temperature sensor in the MT7981 is same as in the MT7986. Signed-off-by: Aleksander Jan Bajkowski Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250907111742.23195-2-olek2@wp.pl Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 31 ++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 5cbea9cd411f..277c11247c13 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -76,7 +76,7 @@ watchdog: watchdog@1001c000 { #reset-cells = <1>; }; - clock-controller@1001e000 { + apmixedsys: clock-controller@1001e000 { compatible = "mediatek,mt7981-apmixedsys"; reg = <0 0x1001e000 0 0x1000>; #clock-cells = <1>; @@ -184,6 +184,31 @@ spi@1100b000 { status = "disabled"; }; + thermal@1100c800 { + compatible = "mediatek,mt7981-thermal", + "mediatek,mt7986-thermal"; + reg = <0 0x1100c800 0 0x800>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM_CK>, + <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "therm", "auxadc"; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + #thermal-sensor-cells = <1>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + }; + + auxadc: adc@1100d000 { + compatible = "mediatek,mt7981-auxadc", + "mediatek,mt7986-auxadc"; + reg = <0 0x1100d000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + pio: pinctrl@11d00000 { compatible = "mediatek,mt7981-pinctrl"; reg = <0 0x11d00000 0 0x1000>, @@ -211,6 +236,10 @@ efuse@11f20000 { reg = <0 0x11f20000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + thermal_calibration: thermal-calib@274 { + reg = <0x274 0xc>; + }; }; clock-controller@15000000 { From d0c970091abf11805cb629f20760c0e67eb73f82 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 9 Jul 2025 13:09:43 +0200 Subject: [PATCH 564/931] arm64: dts: mediatek: mt7986: add sram node Currently sram is allocated in driver via offset from reg of ethernet node. Change it to use a dedicated sram node like mt7988. Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20250709111147.11843-8-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 559990dcd1d1..550f569451fb 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -523,7 +523,7 @@ wed1: wed@15011000 { eth: ethernet@15100000 { compatible = "mediatek,mt7986-eth"; - reg = <0 0x15100000 0 0x80000>; + reg = <0 0x15100000 0 0x40000>; interrupts = , , , @@ -553,6 +553,7 @@ eth: ethernet@15100000 { <&topckgen CLK_TOP_SGM_325M_SEL>; assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, <&apmixedsys CLK_APMIXED_SGMPLL>; + sram = <ð_sram>; #address-cells = <1>; #size-cells = <0>; mediatek,ethsys = <ðsys>; @@ -562,6 +563,15 @@ eth: ethernet@15100000 { status = "disabled"; }; + /*15100000+0x40000*/ + eth_sram: sram@15140000 { + compatible = "mmio-sram"; + reg = <0 0x15140000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x15140000 0 0x40000>; + }; + wo_ccif0: syscon@151a5000 { compatible = "mediatek,mt7986-wo-ccif", "syscon"; reg = <0 0x151a5000 0 0x1000>; From 93e435336ab4bfb115e546e5a31b895b1ce0b83d Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 9 Jul 2025 13:09:44 +0200 Subject: [PATCH 565/931] arm64: dts: mediatek: mt7986: add interrupts for RSS and interrupt names Add interrupts for RSS/LRO and names to access them via name instead of index. Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20250709111147.11843-9-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 550f569451fb..a9e079fd42c6 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -527,7 +527,13 @@ eth: ethernet@15100000 { interrupts = , , , - ; + , + , + , + , + ; + interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0", + "pdma1", "pdma2", "pdma3"; clocks = <ðsys CLK_ETH_FE_EN>, <ðsys CLK_ETH_GP2_EN>, <ðsys CLK_ETH_GP1_EN>, From 65f0e3970143ec5d24271a51e0bc8c0588383280 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 9 Jul 2025 13:09:45 +0200 Subject: [PATCH 566/931] arm64: dts: mediatek: mt7988: add basic ethernet-nodes Add basic ethernet related nodes. Mac1+2 needs pcs (sgmii+usxgmii) to work correctly which will be linked later when driver is merged. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20250709111147.11843-10-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 137 +++++++++++++++++++++- 1 file changed, 134 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 560ec86dbec0..897b5a82b53e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -680,7 +680,28 @@ xphyu3port0: usb-phy@11e13000 { }; }; - clock-controller@11f40000 { + xfi_tphy0: phy@11f20000 { + compatible = "mediatek,mt7988-xfi-tphy"; + reg = <0 0x11f20000 0 0x10000>; + clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, + <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; + clock-names = "xfipll", "topxtal"; + resets = <&watchdog 14>; + mediatek,usxgmii-performance-errata; + #phy-cells = <0>; + }; + + xfi_tphy1: phy@11f30000 { + compatible = "mediatek,mt7988-xfi-tphy"; + reg = <0 0x11f30000 0 0x10000>; + clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, + <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>; + clock-names = "xfipll", "topxtal"; + resets = <&watchdog 15>; + #phy-cells = <0>; + }; + + xfi_pll: clock-controller@11f40000 { compatible = "mediatek,mt7988-xfi-pll"; reg = <0 0x11f40000 0 0x1000>; resets = <&watchdog 16>; @@ -714,19 +735,129 @@ phy_calibration_p3: calib@97c { }; }; - clock-controller@15000000 { + ethsys: clock-controller@15000000 { compatible = "mediatek,mt7988-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; - clock-controller@15031000 { + ethwarp: clock-controller@15031000 { compatible = "mediatek,mt7988-ethwarp"; reg = <0 0x15031000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7988-eth"; + reg = <0 0x15100000 0 0x40000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0", + "pdma1", "pdma2", "pdma3"; + clocks = <ðsys CLK_ETHDMA_CRYPT0_EN>, + <ðsys CLK_ETHDMA_FE_EN>, + <ðsys CLK_ETHDMA_GP2_EN>, + <ðsys CLK_ETHDMA_GP1_EN>, + <ðsys CLK_ETHDMA_GP3_EN>, + <ðwarp CLK_ETHWARP_WOCPU2_EN>, + <ðwarp CLK_ETHWARP_WOCPU1_EN>, + <ðwarp CLK_ETHWARP_WOCPU0_EN>, + <ðsys CLK_ETHDMA_ESW_EN>, + <&topckgen CLK_TOP_ETH_GMII_SEL>, + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_SEL>, + <&topckgen CLK_TOP_ETH_XGMII_SEL>, + <&topckgen CLK_TOP_ETH_MII_SEL>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>, + <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_WARP_SEL>, + <ðsys CLK_ETHDMA_XGP1_EN>, + <ðsys CLK_ETHDMA_XGP2_EN>, + <ðsys CLK_ETHDMA_XGP3_EN>; + clock-names = "crypto", "fe", "gp2", "gp1", "gp3", + "ethwarp_wocpu2", "ethwarp_wocpu1", + "ethwarp_wocpu0", "esw", "top_eth_gmii_sel", + "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", + "top_eth_sys_sel", "top_eth_xgmii_sel", + "top_eth_mii_sel", "top_netsys_sel", + "top_netsys_500m_sel", "top_netsys_pao_2x_sel", + "top_netsys_sync_250m_sel", + "top_netsys_ppefb_250m_sel", + "top_netsys_warp_sel","xgp1", "xgp2", "xgp3"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_GSW_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&topckgen CLK_TOP_SGM_1_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&topckgen CLK_TOP_NET1PLL_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&apmixedsys CLK_APMIXED_SGMPLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + sram = <ð_sram>; + #address-cells = <1>; + #size-cells = <0>; + mediatek,ethsys = <ðsys>; + mediatek,infracfg = <&topmisc>; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "internal"; + + /* Connected to internal switch */ + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + }; + + gmac2: mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; + status = "disabled"; + }; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + /* internal 2.5G PHY */ + int_2p5g_phy: ethernet-phy@15 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <15>; + }; + }; + }; + + eth_sram: sram@15400000 { + compatible = "mmio-sram"; + reg = <0 0x15400000 0 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x15400000 0 0x200000>; + }; }; thermal-zones { From 32d5a82c5dd60f3f5e34cade74f92f0604cda096 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 9 Jul 2025 13:09:46 +0200 Subject: [PATCH 567/931] arm64: dts: mediatek: mt7988: add switch node Add mt7988 builtin mt753x switch nodes. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250709111147.11843-11-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 148 ++++++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 897b5a82b53e..366203a72d6d 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -742,6 +742,154 @@ ethsys: clock-controller@15000000 { #reset-cells = <1>; }; + switch: switch@15020000 { + compatible = "mediatek,mt7988-switch"; + reg = <0 0x15020000 0 0x8000>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = ; + resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + gsw_port0: port@0 { + reg = <0>; + phy-handle = <&gsw_phy0>; + phy-mode = "internal"; + }; + + gsw_port1: port@1 { + reg = <1>; + phy-handle = <&gsw_phy1>; + phy-mode = "internal"; + }; + + gsw_port2: port@2 { + reg = <2>; + phy-handle = <&gsw_phy2>; + phy-mode = "internal"; + }; + + gsw_port3: port@3 { + reg = <3>; + phy-handle = <&gsw_phy3>; + phy-mode = "internal"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + mediatek,pio = <&pio>; + + gsw_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupts = <0>; + nvmem-cells = <&phy_calibration_p0>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy0_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy0_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + + gsw_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + interrupts = <1>; + nvmem-cells = <&phy_calibration_p1>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy1_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy1_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + + gsw_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + interrupts = <2>; + nvmem-cells = <&phy_calibration_p2>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy2_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy2_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + + gsw_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + interrupts = <3>; + nvmem-cells = <&phy_calibration_p3>; + nvmem-cell-names = "phy-cal-data"; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy3_led0: led@0 { + reg = <0>; + status = "disabled"; + }; + + gsw_phy3_led1: led@1 { + reg = <1>; + status = "disabled"; + }; + }; + }; + }; + }; + ethwarp: clock-controller@15031000 { compatible = "mediatek,mt7988-ethwarp"; reg = <0 0x15031000 0 0x1000>; From 0333aa8fa2d5f0dcc92afcbb38f7b286163dc0cc Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 9 Jul 2025 13:09:47 +0200 Subject: [PATCH 568/931] arm64: dts: mediatek: mt7988a-bpi-r4: add aliases for ethernet Add aliases for gmacs to allow bootloader setting mac-adresses. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250709111147.11843-12-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi index 5fd222df440d..6a62da34a51e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi @@ -9,6 +9,12 @@ #include "mt7988a.dtsi" / { + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + chosen { stdout-path = "serial0:115200n8"; }; From c1347c688bf1889ba9e974a828f1f0f26717cd04 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 9 Jul 2025 13:09:48 +0200 Subject: [PATCH 569/931] arm64: dts: mediatek: mt7988a-bpi-r4: add sfp cages and link to gmac Add SFP cages to Bananapi-R4 board. The 2.5g phy variant only contains the wan-SFP, so add this to common dtsi and the lan-sfp only to the dual-SFP variant. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250709111147.11843-13-linux@fw-web.de Signed-off-by: Matthias Brugger --- .../mediatek/mt7988a-bananapi-bpi-r4-2g5.dts | 11 +++++++++++ .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 19 +++++++++++++++++++ .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 19 +++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts index 53de9c113f60..6f0c81e3fd94 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4-2g5.dts @@ -9,3 +9,14 @@ / { model = "Banana Pi BPI-R4 (1x SFP+, 1x 2.5GbE)"; chassis-type = "embedded"; }; + +&gmac1 { + phy = <&int_2p5g_phy>; + phy-mode = "internal"; + status = "okay"; +}; + +&int_2p5g_phy { + pinctrl-0 = <&i2p5gbe_led0_pins>; + pinctrl-names = "i2p5gbe-led"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts index 36bd1ef2efab..4b3796ba82e3 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts @@ -8,6 +8,25 @@ / { compatible = "bananapi,bpi-r4", "mediatek,mt7988a"; model = "Banana Pi BPI-R4 (2x SFP+)"; chassis-type = "embedded"; + + /* SFP2 cage (LAN) */ + sfp2: sfp2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + maximum-power-milliwatt = <3000>; + + los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&gmac1 { + managed = "in-band-status"; + phy-mode = "usxgmii"; + sfp = <&sfp2>; }; &pca9545 { diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi index 6a62da34a51e..34c1bc7f6c09 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi @@ -64,6 +64,19 @@ reg_3p3v: regulator-3p3v { regulator-boot-on; regulator-always-on; }; + + /* SFP1 cage (WAN) */ + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + maximum-power-milliwatt = <3000>; + + los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>; + }; }; &cci { @@ -134,6 +147,12 @@ map-cpu-active-low { }; }; +&gmac2 { + managed = "in-band-status"; + phy-mode = "usxgmii"; + sfp = <&sfp1>; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; From 16c1f659860be36541ab89c2cfd3674fbe706cd7 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 9 Jul 2025 13:09:49 +0200 Subject: [PATCH 570/931] arm64: dts: mediatek: mt7988a-bpi-r4: configure switch phys and leds Assign pinctrl to switch phys and leds. Signed-off-by: Daniel Golle Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250709111147.11843-14-linux@fw-web.de Signed-off-by: Matthias Brugger --- .../dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi index 34c1bc7f6c09..0ff69dae45d3 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include #include "mt7988a.dtsi" @@ -153,6 +154,66 @@ &gmac2 { sfp = <&sfp1>; }; +&gsw_phy0 { + pinctrl-0 = <&gbe0_led0_pins>; + pinctrl-names = "gbe-led"; +}; + +&gsw_phy0_led0 { + function = LED_FUNCTION_WAN; + color = ; + status = "okay"; +}; + +&gsw_port0 { + label = "wan"; +}; + +&gsw_phy1 { + pinctrl-0 = <&gbe1_led0_pins>; + pinctrl-names = "gbe-led"; +}; + +&gsw_phy1_led0 { + function = LED_FUNCTION_LAN; + color = ; + status = "okay"; +}; + +&gsw_port1 { + label = "lan1"; +}; + +&gsw_phy2 { + pinctrl-0 = <&gbe2_led0_pins>; + pinctrl-names = "gbe-led"; +}; + +&gsw_phy2_led0 { + function = LED_FUNCTION_LAN; + color = ; + status = "okay"; +}; + +&gsw_port2 { + label = "lan2"; +}; + +&gsw_phy3 { + pinctrl-0 = <&gbe3_led0_pins>; + pinctrl-names = "gbe-led"; +}; + +&gsw_phy3_led0 { + function = LED_FUNCTION_LAN; + color = ; + status = "okay"; +}; + +&gsw_port3 { + label = "lan3"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; From 7a37bf31e3a736d86c3c801ec2116fde4fb395ce Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Thu, 14 Aug 2025 10:52:47 +0200 Subject: [PATCH 571/931] arm64: dts: qcom: qcm2290: Add Venus video node Add DT entries for the qcm2290 Venus encoder/decoder. Co-developed-by: Loic Poulain Signed-off-by: Loic Poulain Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250814085248.2371130-8-jorge.ramirez@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 55 +++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 77d7ee17ba90..527705c7d212 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -2103,6 +2103,61 @@ apps_smmu: iommu@c600000 { ; }; + venus: video-codec@5a00000 { + compatible = "qcom,qcm2290-venus"; + reg = <0 0x5a00000 0 0xf0000>; + interrupts = ; + + power-domains = <&gcc GCC_VENUS_GDSC>, + <&gcc GCC_VCODEC0_GDSC>, + <&rpmpd QCM2290_VDDCX>; + power-domain-names = "venus", + "vcodec0", + "cx"; + operating-points-v2 = <&venus_opp_table>; + + clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>, + <&gcc GCC_VENUS_CTL_AXI_CLK>, + <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>, + <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>, + <&gcc GCC_VCODEC0_AXI_CLK>; + clock-names = "core", + "iface", + "bus", + "throttle", + "vcodec0_core", + "vcodec0_bus"; + + memory-region = <&pil_video_mem>; + iommus = <&apps_smmu 0x860 0x0>, + <&apps_smmu 0x880 0x0>, + <&apps_smmu 0x861 0x04>, + <&apps_smmu 0x863 0x0>, + <&apps_smmu 0x804 0xe0>; + + interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, + <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG + &config_noc SLAVE_VENUS_CFG RPM_ACTIVE_TAG>; + interconnect-names = "video-mem", + "cpu-cfg"; + + venus_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133333333 { + opp-hz = /bits/ 64 <133333333>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmpd_opp_svs>; + }; + }; + }; + wifi: wifi@c800000 { compatible = "qcom,wcn3990-wifi"; reg = <0x0 0x0c800000 0x0 0x800000>; From 9a45e985d4e8dae4226af5a8eddea4c48c62e2ea Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Thu, 14 Aug 2025 10:52:48 +0200 Subject: [PATCH 572/931] arm64: dts: qcom: qrb2210-rb1: Enable Venus Enable Venus on the QRB2210 RB1 development board. Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bryan O'Donoghue Reviewed-by: Dikshita Agarwal Link: https://lore.kernel.org/r/20250814085248.2371130-9-jorge.ramirez@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 277b33100ac0..67ba508e92ba 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -699,6 +699,10 @@ &usb_qmpphy_out { remote-endpoint = <&pm4125_ss_in>; }; +&venus { + status = "okay"; +}; + &wifi { vdd-0.8-cx-mx-supply = <&pm4125_l7>; vdd-1.8-xo-supply = <&pm4125_l13>; From fc8089535425897b6efacc8531e4b5b63b85b435 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 9 Sep 2025 10:24:07 +0200 Subject: [PATCH 573/931] arm64: dts: qcom: x1e80100-romulus: Add WCN7850 Wi-Fi/BT It comes soldered onboard, just like on the QCP. Unfortunately, the rfkill pin is triggered by default, so a workaround is needed to convince the Linux driver to enable the hw, after which it works just fine. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250909-topic-romulus_wifi_pci-v2-1-3dc495d5559f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/x1e80100-microsoft-romulus.dtsi | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 0ad4276e9c5f..ed468b93ba50 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -331,6 +331,42 @@ vph_pwr: regulator-vph-pwr { regulator-boot-on; }; + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + sound { compatible = "qcom,x1e80100-sndcard"; model = "X1E80100-Romulus"; @@ -410,6 +446,65 @@ platform { }; }; }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -1028,6 +1123,23 @@ &pcie4_phy { status = "okay"; }; +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pcie6a { perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; @@ -1234,6 +1346,13 @@ ssam_state: ssam-state-state { bias-disable; }; + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + pcie3_default: pcie3-default-state { perst-n-pins { pins = "gpio143"; @@ -1309,6 +1428,13 @@ wcd_default: wcd-reset-n-active-state { output-low; }; + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + cam_indicator_en: cam-indicator-en-state { pins = "gpio225"; function = "gpio"; @@ -1332,6 +1458,23 @@ embedded-controller { }; }; +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + &usb_1_ss0_hsphy { vdd-supply = <&vreg_l3j>; vdda12-supply = <&vreg_l2j>; From b83d3cc7a59c29918964cc0961dc3fef9ad32b53 Mon Sep 17 00:00:00 2001 From: Renjiang Han Date: Tue, 26 Aug 2025 16:23:38 +0530 Subject: [PATCH 574/931] arm64: dts: qcom: sm6150: add venus node to devicetree Add the venus node to the devicetree for the sm6150 platform to enable video functionality. The sm6150 platform currently lacks video functionality due to the absence of the venus node. Fallback to sc7180 due to the same video core. Reviewed-by: Konrad Dybcio Signed-off-by: Renjiang Han Link: https://lore.kernel.org/r/20250826-enable-venus-for-sm6150-v9-1-486d167639a1@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 78 ++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi index 53496241479a..8757e0501591 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -494,6 +494,11 @@ smem_region: smem@86000000 { hwlocks = <&tcsr_mutex 3>; }; + pil_video_mem: pil-video@93400000 { + reg = <0x0 0x93400000 0x0 0x500000>; + no-map; + }; + rproc_cdsp_mem: rproc-cdsp@93b00000 { reg = <0x0 0x93b00000 0x0 0x1e00000>; no-map; @@ -3556,6 +3561,79 @@ gem_noc: interconnect@9680000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + venus: video-codec@aa00000 { + compatible = "qcom,qcs615-venus", "qcom,sc7180-venus"; + reg = <0x0 0x0aa00000 0x0 0x100000>; + interrupts = ; + + clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, + <&videocc VIDEO_CC_VENUS_AHB_CLK>, + <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, + <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, + <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; + clock-names = "core", + "iface", + "bus", + "vcodec0_core", + "vcodec0_bus"; + + power-domains = <&videocc VENUS_GDSC>, + <&videocc VCODEC0_GDSC>, + <&rpmhpd RPMHPD_CX>; + power-domain-names = "venus", + "vcodec0", + "cx"; + + operating-points-v2 = <&venus_opp_table>; + + interconnects = <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "video-mem", + "cpu-cfg"; + + iommus = <&apps_smmu 0xe60 0x20>; + + memory-region = <&pil_video_mem>; + + status = "disabled"; + + venus_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133330000 { + opp-hz = /bits/ 64 <133330000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-410000000 { + opp-hz = /bits/ 64 <410000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + videocc: clock-controller@ab00000 { compatible = "qcom,qcs615-videocc"; reg = <0 0x0ab00000 0 0x10000>; From cafb56f78a04c90b41109d077a1b8aef2736980b Mon Sep 17 00:00:00 2001 From: Renjiang Han Date: Tue, 26 Aug 2025 16:23:39 +0530 Subject: [PATCH 575/931] arm64: dts: qcom: qcs615-ride: enable venus node to initialize video codec Enable the venus node to allow the video codec to start working properly by setting its status to "okay". Acked-by: Nicolas Dufresne Reviewed-by: Dmitry Baryshkov Signed-off-by: Renjiang Han Link: https://lore.kernel.org/r/20250826-enable-venus-for-sm6150-v9-2-486d167639a1@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index e663343df75d..705ea71b07a1 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -513,3 +513,7 @@ &ufs_mem_phy { status = "okay"; }; + +&venus { + status = "okay"; +}; From e696e7aa439f1134ca5f91d6c86b332b72e57d9c Mon Sep 17 00:00:00 2001 From: Christopher Obbard Date: Thu, 14 Aug 2025 21:16:19 +0100 Subject: [PATCH 576/931] arm64: dts: qcom: x1e78100-t14s-oled: Add eDP panel Add the Samsung ATNA40YK20 eDP panel to the device tree for the Snapdragon T14s OLED model. Signed-off-by: Christopher Obbard Tested-by: Jens Glathe Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250814-wip-obbardc-qcom-t14s-oled-panel-v7-1-89966ae886a3@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts index be65fafafa73..d524afa12d19 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s-oled.dts @@ -10,3 +10,11 @@ / { compatible = "lenovo,thinkpad-t14s-oled", "lenovo,thinkpad-t14s", "qcom,x1e78100", "qcom,x1e80100"; }; + +&panel { + compatible = "samsung,atna40yk20", "samsung,atna33xc20"; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; +}; From 3f2d6cbbf4c46fbb9e9aa6fa25a70b0003471b26 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Fri, 22 Aug 2025 18:49:01 +0530 Subject: [PATCH 577/931] arm64: dts: qcom: lemans: Add gpr node Add GPR(Generic Pack router) node along with APM(Audio Process Manager) and PRM(Proxy resource Manager) audio services. Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250822131902.1848802-2-mohammad.rafi.shaik@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index f5ec60086d60..77724805ae8c 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -18,6 +18,7 @@ #include #include #include +#include #include / { @@ -6667,6 +6668,45 @@ compute-cb@5 { dma-coherent; }; }; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x3001 0x0>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; }; }; }; From 473a19211c4dc762e6ecab9c3e6583afd3200817 Mon Sep 17 00:00:00 2001 From: Mohammad Rafi Shaik Date: Fri, 22 Aug 2025 18:49:02 +0530 Subject: [PATCH 578/931] arm64: dts: qcom: lemans-evk: Add sound card Add the sound card node with tested playback over max98357a I2S speakers amplifier and I2S mic. Introduce HS (High-Speed) MI2S pin control support. The I2S max98357a speaker amplifier is connected via HS0 and I2S microphones utilize the HS2 interface. Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250822131902.1848802-3-mohammad.rafi.shaik@oss.qualcomm.com [bjorn: Sorted nodes] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 52 +++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/lemans.dtsi | 14 +++++++ 2 files changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 9e415012140b..f79e826bd5d4 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include "lemans.dtsi" @@ -19,6 +20,17 @@ aliases { serial0 = &uart10; }; + dmic: audio-codec-0 { + compatible = "dmic-codec"; + #sound-dai-cells = <0>; + num-channels = <1>; + }; + + max98357a: audio-codec-1 { + compatible = "maxim,max98357a"; + #sound-dai-cells = <0>; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -46,6 +58,46 @@ edp1_connector_in: endpoint { }; }; }; + + sound { + compatible = "qcom,qcs9100-sndcard"; + model = "LEMANS-EVK"; + + pinctrl-0 = <&hs0_mi2s_active>, <&hs2_mi2s_active>; + pinctrl-names = "default"; + + hs0-mi2s-playback-dai-link { + link-name = "HS0 MI2S Playback"; + + codec { + sound-dai = <&max98357a>; + }; + + cpu { + sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + hs2-mi2s-capture-dai-link { + link-name = "HS2 MI2S Capture"; + + codec { + sound-dai = <&dmic>; + }; + + cpu { + sound-dai = <&q6apmbedai TERTIARY_MI2S_TX>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; }; &apps_rsc { diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 77724805ae8c..fd6eb6fbe29a 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -5017,6 +5017,20 @@ dp1_hot_plug_det: dp1-hot-plug-det-state { bias-disable; }; + hs0_mi2s_active: hs0-mi2s-active-state { + pins = "gpio114", "gpio115", "gpio116", "gpio117"; + function = "hs0_mi2s"; + drive-strength = <8>; + bias-disable; + }; + + hs2_mi2s_active: hs2-mi2s-active-state { + pins = "gpio122", "gpio123", "gpio124", "gpio125"; + function = "hs2_mi2s"; + drive-strength = <8>; + bias-disable; + }; + qup_i2c0_default: qup-i2c0-state { pins = "gpio20", "gpio21"; function = "qup0_se0"; From 194c7636faf8bab8deea3800e168b23319a9c198 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20Gon=C3=A7alves?= Date: Fri, 5 Sep 2025 19:09:29 +0000 Subject: [PATCH 579/931] arm64: dts: qcom: sm8250-samsung-r8q: Move common parts to dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move common parts of the device tree to a separate dtsi in preparation for adding other Samsung devices from the S20, Tab S7 or Note 20 families, creating sm8250-samsung-common.dtsi. Also add support for UFS, USB and GPIO keys. Signed-off-by: Eric Gonçalves Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250905190931.27481-2-ghatto404@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sm8250-samsung-common.dtsi | 204 ++++++++++++++++++ .../boot/dts/qcom/sm8250-samsung-r8q.dts | 49 ++--- 2 files changed, 218 insertions(+), 35 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sm8250-samsung-common.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm8250-samsung-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-samsung-common.dtsi new file mode 100644 index 000000000000..cf3d917addd8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-samsung-common.dtsi @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include +#include "sm8250.dtsi" +#include "pm8150.dtsi" + +/ { + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@9c000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9c000000 0x0 0x2300000>; + width = <1080>; + height = <2400>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_n>; + + key-vol-up { + label = "Volume Up"; + gpios = <&pm8150_gpios 3 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + reserved-memory { + cont_splash_mem: memory@9c000000 { + reg = <0x0 0x9c000000 0x0 0x2300000>; + no-map; + }; + + ramoops@9fa00000 { + compatible = "ramoops"; + reg = <0x0 0x9fa00000 0x0 0x100000>; + record-size = <0x4000>; + console-size = <0x40000>; + ftrace-size = <0x40000>; + pmsg-size = <0x40000>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vreg_s4a_1p8: smps4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2a_3p1: ldo2 { + regulator-name = "vreg_l2a_3p1"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l5a_0p88: ldo5 { + regulator-name = "vreg_l5a_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9a_1p2: ldo9 { + regulator-name = "vreg_l9a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l17a_3p0: ldo17 { + regulator-name = "vreg_l17a_3p0"; + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + +&pm8150_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + input-enable; + bias-pull-up; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <40 4>; /* I2C (Unused) */ +}; + +&usb_1 { + /* Limit to USB 2.0 for now */ + qcom,select-utmi-as-pipe-clk; + + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + /* Remove USB3 phy */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l2a_3p1>; + + status = "okay"; +}; + +&ufs_mem_hc { + vcc-supply = <&vreg_l17a_3p0>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l6a_1p2>; + vccq-max-microamp = <800000>; + vccq2-supply = <&vreg_s4a_1p8>; + vccq2-max-microamp = <800000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-samsung-r8q.dts b/arch/arm64/boot/dts/qcom/sm8250-samsung-r8q.dts index 2fb6108ed5a9..dc7c3816f156 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-samsung-r8q.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-samsung-r8q.dts @@ -2,46 +2,25 @@ /dts-v1/; -#include "sm8250.dtsi" +#include "sm8250-samsung-common.dtsi" / { model = "Samsung Galaxy S20 FE"; compatible = "samsung,r8q", "qcom,sm8250"; chassis-type = "handset"; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - framebuffer: framebuffer@9c000000 { - compatible = "simple-framebuffer"; - reg = <0x0 0x9c000000 0x0 (1080 * 2400 * 4)>; - width = <1080>; - height = <2400>; - stride = <(1080 * 4)>; - format = "a8r8g8b8"; - }; - }; - - reserved-memory { - cont_splash_mem: memory@9c000000 { - reg = <0x0 0x9c000000 0x0 (1080 * 2400 * 4)>; - no-map; - }; - - ramoops@9fa00000 { - compatible = "ramoops"; - reg = <0x0 0x9fa00000 0x0 0x100000>; - record-size = <0x4000>; - console-size = <0x40000>; - pmsg-size = <0x40000>; - ecc-size = <16>; - no-map; - }; - }; }; -&tlmm { - gpio-reserved-ranges = <40 4>; /* I2C (not linked to anything) */ +&adsp { + firmware-name = "qcom/sm8250/Samsung/r8q/adsp.mbn"; + status = "okay"; +}; + +&cdsp { + firmware-name = "qcom/sm8250/Samsung/r8q/cdsp.mbn"; + status = "okay"; +}; + +&slpi { + firmware-name = "qcom/sm8250/Samsung/r8q/slpi.mbn"; + status = "okay"; }; From 818045d1658fd4ceec06fb6efa62ed9c5b7f23cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20Gon=C3=A7alves?= Date: Fri, 5 Sep 2025 19:09:30 +0000 Subject: [PATCH 580/931] dt-bindings: arm: qcom: document x1q board binding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add binding for the Samsung Galaxy S20 board, codenamed X1Q, which is based on the Qualcomm Snapdragon 865 SoC. Signed-off-by: Eric Gonçalves Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250905190931.27481-3-ghatto404@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 2698ba87cd93..cf49dd0000e0 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -984,6 +984,7 @@ properties: - qcom,sm8250-hdk - qcom,sm8250-mtp - samsung,r8q + - samsung,x1q - sony,pdx203-generic - sony,pdx206-generic - xiaomi,elish From af7bf2a2bf8fe01b6e2f68af19517a4eec48bdbb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20Gon=C3=A7alves?= Date: Fri, 5 Sep 2025 19:09:31 +0000 Subject: [PATCH 581/931] arm64: dts: qcom: add initial support for Samsung Galaxy S20 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add new device support for the Samsung Galaxy S20 phone What works (common dtsi): - SimpleFB - Pstore/ramoops - GPIO keys - UFS - USB Signed-off-by: Eric Gonçalves Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250905190931.27481-4-ghatto404@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm8250-samsung-x1q.dts | 26 +++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8250-samsung-x1q.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 0e4e0e0b833b..5b52f9e4e5f3 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -276,6 +276,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-samsung-r8q.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8250-samsung-x1q.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-boe.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8250-samsung-x1q.dts b/arch/arm64/boot/dts/qcom/sm8250-samsung-x1q.dts new file mode 100644 index 000000000000..d6aeb5af2ba4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-samsung-x1q.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sm8250-samsung-common.dtsi" + +/ { + model = "Samsung Galaxy S20"; + compatible = "samsung,x1q", "qcom,sm8250"; + chassis-type = "handset"; +}; + +&adsp { + firmware-name = "qcom/sm8250/Samsung/x1q/adsp.mbn"; + status = "okay"; +}; + +&cdsp { + firmware-name = "qcom/sm8250/Samsung/x1q/cdsp.mbn"; + status = "okay"; +}; + +&slpi { + firmware-name = "qcom/sm8250/Samsung/x1q/slpi.mbn"; + status = "okay"; +}; From 318d441dfe6f40002dedb163f7d0fa493e225f67 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 8 Sep 2025 10:53:32 +0200 Subject: [PATCH 582/931] arm64: dts: qcom: sm8650: Drop redundant status from PMK8550 RTC The PMK8550 RTC is always enabled in its DTSI file since commit a791fc19965e ("arm64: dts: qcom: pmk8550: always enable RTC PMIC device"), so drop redundant status=okay in SM8650 boards. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250908085331.56478-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 4 ---- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index d4e5c95e9339..87d7190dc991 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -1046,10 +1046,6 @@ &pm8550b_eusb2_repeater { vdd3-supply = <&vreg_l5b_3p1>; }; -&pmk8550_rtc { - status = "okay"; -}; - &pon_pwrkey { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index d71031cb26e2..9e790cf44804 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -1002,10 +1002,6 @@ &pm8550b_eusb2_repeater { vdd3-supply = <&vreg_l5b_3p1>; }; -&pmk8550_rtc { - status = "okay"; -}; - &qup_i2c3_data_clk { /* Use internal I2C pull-up */ bias-pull-up = <2200>; From be6f43c64ca0f7929904f31c2a034c81093eb5c0 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Tue, 1 Jul 2025 21:50:46 +0530 Subject: [PATCH 583/931] arm64: dts: qcom: x1e80100: Update GPU OPP table Update the GPU OPP table with new opp levels along with the speedbin configurations. Signed-off-by: Akhil P Oommen Tested-by: Jens Glathe Link: https://lore.kernel.org/r/20250701-x1e-speedbin-b4-v2-3-a8a7e06d39fb@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 57 +++++++++++++++++++++++++- arch/arm64/boot/dts/qcom/x1p42100.dtsi | 1 + 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 737c5dbd1c80..ba602eddfb54 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3794,6 +3794,9 @@ gpu: gpu@3d00000 { qcom,gmu = <&gmu>; #cooling-cells = <2>; + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; @@ -3806,11 +3809,28 @@ gpu_zap_shader: zap-shader { gpu_opp_table: opp-table { compatible = "operating-points-v2-adreno", "operating-points-v2"; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x03>; + }; + + opp-1375000000 { + opp-hz = /bits/ 64 <1375000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x03>; + }; + opp-1250000000 { opp-hz = /bits/ 64 <1250000000>; opp-level = ; opp-peak-kBps = <16500000>; qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x07>; }; opp-1175000000 { @@ -3818,13 +3838,24 @@ opp-1175000000 { opp-level = ; opp-peak-kBps = <14398438>; qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x07>; }; - opp-1100000000 { + opp-1100000000-0 { opp-hz = /bits/ 64 <1100000000>; opp-level = ; opp-peak-kBps = <14398438>; qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x07>; + }; + + /* Only applicable for SKUs which has 1100Mhz as Fmax */ + opp-1100000000-1 { + opp-hz = /bits/ 64 <1100000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0xa82a5ffd>; + opp-supported-hw = <0x08>; }; opp-1000000000 { @@ -3832,6 +3863,7 @@ opp-1000000000 { opp-level = ; opp-peak-kBps = <14398438>; qcom,opp-acd-level = <0xa82b5ffd>; + opp-supported-hw = <0x0f>; }; opp-925000000 { @@ -3839,6 +3871,7 @@ opp-925000000 { opp-level = ; opp-peak-kBps = <14398438>; qcom,opp-acd-level = <0xa82b5ffd>; + opp-supported-hw = <0x0f>; }; opp-800000000 { @@ -3846,6 +3879,7 @@ opp-800000000 { opp-level = ; opp-peak-kBps = <12449219>; qcom,opp-acd-level = <0xa82c5ffd>; + opp-supported-hw = <0x0f>; }; opp-744000000 { @@ -3853,13 +3887,24 @@ opp-744000000 { opp-level = ; opp-peak-kBps = <10687500>; qcom,opp-acd-level = <0x882e5ffd>; + opp-supported-hw = <0x0f>; }; - opp-687000000 { + opp-687000000-0 { opp-hz = /bits/ 64 <687000000>; opp-level = ; opp-peak-kBps = <8171875>; qcom,opp-acd-level = <0x882e5ffd>; + opp-supported-hw = <0x0f>; + }; + + /* Only applicable for SKUs which has 687Mhz as Fmax */ + opp-687000000-1 { + opp-hz = /bits/ 64 <687000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + qcom,opp-acd-level = <0x882e5ffd>; + opp-supported-hw = <0x10>; }; opp-550000000 { @@ -3867,6 +3912,7 @@ opp-550000000 { opp-level = ; opp-peak-kBps = <6074219>; qcom,opp-acd-level = <0xc0285ffd>; + opp-supported-hw = <0x1f>; }; opp-390000000 { @@ -3874,6 +3920,7 @@ opp-390000000 { opp-level = ; opp-peak-kBps = <3000000>; qcom,opp-acd-level = <0xc0285ffd>; + opp-supported-hw = <0x1f>; }; opp-300000000 { @@ -3881,6 +3928,7 @@ opp-300000000 { opp-level = ; opp-peak-kBps = <2136719>; qcom,opp-acd-level = <0xc02b5ffd>; + opp-supported-hw = <0x1f>; }; }; }; @@ -8297,6 +8345,11 @@ qfprom: efuse@221c8000 { reg = <0 0x221c8000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@119 { + reg = <0x119 0x2>; + bits = <7 8>; + }; }; pmu@24091000 { diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi index b7326be4d064..10d26958d3c6 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi @@ -18,6 +18,7 @@ /delete-node/ &cpu_pd10; /delete-node/ &cpu_pd11; /delete-node/ &gpu_opp_table; +/delete-node/ &gpu_speed_bin; /delete-node/ &pcie3_phy; /delete-node/ &thermal_zones; From f401a8ba756e31dcc47d643da8d1363a342da1a8 Mon Sep 17 00:00:00 2001 From: Valentina Fernandez Date: Mon, 8 Sep 2025 12:57:27 +0100 Subject: [PATCH 584/931] riscv: dts: microchip: add common board dtsi for icicle kit variants In preparation for supporting the Icicle Kit with production silicon, add a common board dtsi for the icicle kit with hardware shared by both the engineering sample and production versions. Signed-off-by: Valentina Fernandez Signed-off-by: Conor Dooley --- .../dts/microchip/mpfs-icicle-kit-common.dtsi | 247 ++++++++++++++++++ .../boot/dts/microchip/mpfs-icicle-kit.dts | 241 +---------------- 2 files changed, 248 insertions(+), 240 deletions(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi new file mode 100644 index 000000000000..eafea3b69cd7 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2025 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-icicle-kit-fabric.dtsi" +#include +#include + +/ { + aliases { + ethernet0 = &mac1; + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + color = ; + label = "led1"; + }; + + led-2 { + gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + color = ; + label = "led2"; + }; + + led-3 { + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + color = ; + label = "led3"; + }; + + led-4 { + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + color = ; + label = "led4"; + }; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1040000000 { + device_type = "memory"; + reg = <0x10 0x40000000 0x0 0x40000000>; + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hss_payload: region@BFC00000 { + reg = <0x0 0xBFC00000 0x0 0x400000>; + no-map; + }; + }; +}; + +&core_pwm0 { + status = "okay"; +}; + +&gpio2 { + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + power-monitor@10 { + compatible = "microchip,pac1934"; + reg = <0x10>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <0x1>; + shunt-resistor-micro-ohms = <10000>; + label = "VDDREG"; + }; + + channel@2 { + reg = <0x2>; + shunt-resistor-micro-ohms = <10000>; + label = "VDDA25"; + }; + + channel@3 { + reg = <0x3>; + shunt-resistor-micro-ohms = <10000>; + label = "VDD25"; + }; + + channel@4 { + reg = <0x4>; + shunt-resistor-micro-ohms = <10000>; + label = "VDDA_REG"; + }; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&mac0 { + phy-mode = "sgmii"; + phy-handle = <&phy0>; + status = "okay"; +}; + +&mac1 { + phy-mode = "sgmii"; + phy-handle = <&phy1>; + status = "okay"; + + phy1: ethernet-phy@9 { + reg = <9>; + }; + + phy0: ethernet-phy@8 { + reg = <8>; + }; +}; + +&mbox { + status = "okay"; +}; + +&mmc { + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +&mmuart2 { + status = "okay"; +}; + +&mmuart3 { + status = "okay"; +}; + +&mmuart4 { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&qspi { + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&refclk_ccc { + clock-frequency = <50000000>; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +}; + +&syscontroller_qspi { + /* + * The flash *is* there, but Icicle kits that have engineering sample + * silicon (write?) access to this flash to non-functional. The system + * controller itself can actually access it, but the MSS cannot write + * an image there. Instantiating a coreQSPI in the fabric & connecting + * it to the flash instead should work though. Pre-production or later + * silicon does not have this issue. + */ + status = "disabled"; + + sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + spi-rx-bus-width = <1>; + reg = <0>; + }; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index f80df225f72b..2cb08ed0946d 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -3,249 +3,10 @@ /dts-v1/; -#include "mpfs.dtsi" -#include "mpfs-icicle-kit-fabric.dtsi" -#include -#include +#include "mpfs-icicle-kit-common.dtsi" / { model = "Microchip PolarFire-SoC Icicle Kit"; compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", "microchip,mpfs"; - - aliases { - ethernet0 = &mac1; - serial0 = &mmuart0; - serial1 = &mmuart1; - serial2 = &mmuart2; - serial3 = &mmuart3; - serial4 = &mmuart4; - }; - - chosen { - stdout-path = "serial1:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-1 { - gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; - color = ; - label = "led1"; - }; - - led-2 { - gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; - color = ; - label = "led2"; - }; - - led-3 { - gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; - color = ; - label = "led3"; - }; - - led-4 { - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - color = ; - label = "led4"; - }; - }; - - ddrc_cache_lo: memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; - status = "okay"; - }; - - ddrc_cache_hi: memory@1040000000 { - device_type = "memory"; - reg = <0x10 0x40000000 0x0 0x40000000>; - status = "okay"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hss_payload: region@BFC00000 { - reg = <0x0 0xBFC00000 0x0 0x400000>; - no-map; - }; - }; -}; - -&core_pwm0 { - status = "okay"; -}; - -&gpio2 { - interrupts = <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>, - <53>, <53>, <53>, <53>; - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; - - power-monitor@10 { - compatible = "microchip,pac1934"; - reg = <0x10>; - - #address-cells = <1>; - #size-cells = <0>; - - channel@1 { - reg = <0x1>; - shunt-resistor-micro-ohms = <10000>; - label = "VDDREG"; - }; - - channel@2 { - reg = <0x2>; - shunt-resistor-micro-ohms = <10000>; - label = "VDDA25"; - }; - - channel@3 { - reg = <0x3>; - shunt-resistor-micro-ohms = <10000>; - label = "VDD25"; - }; - - channel@4 { - reg = <0x4>; - shunt-resistor-micro-ohms = <10000>; - label = "VDDA_REG"; - }; - }; -}; - -&i2c2 { - status = "okay"; -}; - -&mac0 { - phy-mode = "sgmii"; - phy-handle = <&phy0>; - status = "okay"; -}; - -&mac1 { - phy-mode = "sgmii"; - phy-handle = <&phy1>; - status = "okay"; - - phy1: ethernet-phy@9 { - reg = <9>; - }; - - phy0: ethernet-phy@8 { - reg = <8>; - }; -}; - -&mbox { - status = "okay"; -}; - -&mmc { - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&mmuart1 { - status = "okay"; -}; - -&mmuart2 { - status = "okay"; -}; - -&mmuart3 { - status = "okay"; -}; - -&mmuart4 { - status = "okay"; -}; - -&pcie { - status = "okay"; -}; - -&qspi { - status = "okay"; -}; - -&refclk { - clock-frequency = <125000000>; -}; - -&refclk_ccc { - clock-frequency = <50000000>; -}; - -&rtc { - status = "okay"; -}; - -&spi0 { - status = "okay"; -}; - -&spi1 { - status = "okay"; -}; - -&syscontroller { - status = "okay"; -}; - -&syscontroller_qspi { - /* - * The flash *is* there, but Icicle kits that have engineering sample - * silicon (write?) access to this flash to non-functional. The system - * controller itself can actually access it, but the MSS cannot write - * an image there. Instantiating a coreQSPI in the fabric & connecting - * it to the flash instead should work though. Pre-production or later - * silicon does not have this issue. - */ - status = "disabled"; - - sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - spi-max-frequency = <20000000>; - spi-rx-bus-width = <1>; - reg = <0>; - }; -}; - -&usb { - status = "okay"; - dr_mode = "host"; }; From 87f8ae1d0faebbaaf163ecfd1321432d85ada178 Mon Sep 17 00:00:00 2001 From: Valentina Fernandez Date: Mon, 8 Sep 2025 12:57:28 +0100 Subject: [PATCH 585/931] dt-bindings: riscv: microchip: document icicle kit with production device With the introduction of the Icicle Kit using the production MPFS250T device, it's necessary to distinguish it from the engineering sample (-es) variant. Engineering samples cannot write to flash from the MSS, as noted in the PolarFire SoC FPGA ES errata. Add specific compatibles for the Icicle Kit with Production device (MPFS250T) and Icicle Kit with Engineering Sample (MPFS250T_ES). The icicle kit reference designs in the v2025.07 release include the Mi-V IHC IP v2, used to send/receive data between clusters when using Asymmetric Multiprocessing (AMP) mode. In reference design releases prior to v2025.07, the MI-V IHC subsystem was included as a proof of concept in the design prior to becoming an IP available in the Libero catalog. Among other improvements, the new Mi-V IHC IP v2 includes some changes to the register map. For this reason, make use of a new reference design compatible to denote that v2025.07 reference design releases are not backwards compatible. Signed-off-by: Valentina Fernandez Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 78ce76ae1b6d..8ddc5c02973e 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -18,10 +18,18 @@ properties: const: '/' compatible: oneOf: + - items: + - const: microchip,mpfs-icicle-prod-reference-rtl-v2507 + - const: microchip,mpfs-icicle-kit-prod + - const: microchip,mpfs-icicle-kit + - const: microchip,mpfs-prod + - const: microchip,mpfs + - items: - enum: - microchip,mpfs-icicle-reference-rtlv2203 - microchip,mpfs-icicle-reference-rtlv2210 + - microchip,mpfs-icicle-es-reference-rtl-v2507 - const: microchip,mpfs-icicle-kit - const: microchip,mpfs From 2775e87c343c0e355512849dd7364b6c09f4f73d Mon Sep 17 00:00:00 2001 From: Valentina Fernandez Date: Mon, 8 Sep 2025 12:57:29 +0100 Subject: [PATCH 586/931] riscv: dts: microchip: add icicle kit with production device With the introduction of the Icicle Kit using the production MPFS250T device, it's necessary to distinguish it from the engineering sample (-es) variant. Engineering samples cannot write to flash from the MSS, as noted in the PolarFire SoC FPGA ES errata. Add a new device tree (mpfs-icicle-kit-prod.dts) for the production board which includes the icicle kit common dtsi and enable the system controller SPI flash, which is only accessible on production silicon. Remove redundant board compatible from fabric dtsi and update board compatibles for v2025.07 release, which includes Mi-V IHC v2 for AMP cluster communication. Signed-off-by: Valentina Fernandez Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-icicle-kit-common.dtsi | 4 ++++ .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 23 ++++++++++++++++--- .../dts/microchip/mpfs-icicle-kit-prod.dts | 23 +++++++++++++++++++ .../boot/dts/microchip/mpfs-icicle-kit.dts | 3 ++- 5 files changed, 50 insertions(+), 4 deletions(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index f51aeeb9fd3b..1e2f4e41bf0d 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit-prod.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi index eafea3b69cd7..5c7a8ffad85b 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi @@ -134,6 +134,10 @@ &i2c2 { status = "okay"; }; +&ihc { + status = "okay"; +}; + &mac0 { phy-mode = "sgmii"; phy-handle = <&phy0>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index a6dda55a2d1d..e673b676fd1a 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,9 +2,6 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ / { - compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", - "microchip,mpfs"; - core_pwm0: pwm@40000000 { compatible = "microchip,corepwm-rtl-v4"; reg = <0x0 0x40000000 0x0 0xF0>; @@ -26,6 +23,26 @@ i2c2: i2c@40000200 { status = "disabled"; }; + ihc: mailbox { + compatible = "microchip,sbi-ipc"; + interrupt-parent = <&plic>; + interrupts = <180>, <179>, <178>, <177>; + interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4"; + #mbox-cells = <1>; + status = "disabled"; + }; + + mailbox@50000000 { + compatible = "microchip,miv-ihc-rtl-v2"; + reg = <0x0 0x50000000 0x0 0x1c000>; + interrupt-parent = <&plic>; + interrupts = <180>, <179>, <178>, <177>; + interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4"; + #mbox-cells = <1>; + microchip,ihc-chan-disabled-mask = /bits/ 16 <0>; + status = "disabled"; + }; + pcie: pcie@3000000000 { compatible = "microchip,pcie-host-1.0"; #address-cells = <0x3>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts new file mode 100644 index 000000000000..8afedece89d1 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2025 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs-icicle-kit-common.dtsi" + +/ { + model = "Microchip PolarFire-SoC Icicle Kit (Production Silicon)"; + compatible = "microchip,mpfs-icicle-prod-reference-rtl-v2507", + "microchip,mpfs-icicle-kit-prod", + "microchip,mpfs-icicle-kit", + "microchip,mpfs-prod", + "microchip,mpfs"; +}; + +&syscontroller { + microchip,bitstream-flash = <&sys_ctrl_flash>; +}; + +&syscontroller_qspi { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index 2cb08ed0946d..556aa9638282 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -7,6 +7,7 @@ / { model = "Microchip PolarFire-SoC Icicle Kit"; - compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", + compatible = "microchip,mpfs-icicle-es-reference-rtl-v2507", + "microchip,mpfs-icicle-kit", "microchip,mpfs"; }; From 02428682b2eb5ff1669e256f8f94ee1511d22ee1 Mon Sep 17 00:00:00 2001 From: Valentina Fernandez Date: Mon, 8 Sep 2025 12:57:30 +0100 Subject: [PATCH 587/931] riscv: dts: microchip: rename icicle kit ccc clock and other minor fixes Rename the Clock Conditioning Circuit (CCC) reference clock to match the fixed clock bindings naming recommendation. Update the reserved memory regions in the Icicle Kit common dtsi to use lowercase hex and drop the redundant status properties from the memory regions, as they are not required. Signed-off-by: Valentina Fernandez Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi | 6 ++---- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi index 5c7a8ffad85b..e01a216e6c3a 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi @@ -53,13 +53,11 @@ led-4 { ddrc_cache_lo: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; - status = "okay"; }; ddrc_cache_hi: memory@1040000000 { device_type = "memory"; reg = <0x10 0x40000000 0x0 0x40000000>; - status = "okay"; }; reserved-memory { @@ -67,8 +65,8 @@ reserved-memory { #size-cells = <2>; ranges; - hss_payload: region@BFC00000 { - reg = <0x0 0xBFC00000 0x0 0x400000>; + hss_payload: region@bfc00000 { + reg = <0x0 0xbfc00000 0x0 0x400000>; no-map; }; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index e673b676fd1a..71f724325578 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -74,7 +74,7 @@ pcie_intc: interrupt-controller { }; }; - refclk_ccc: cccrefclk { + refclk_ccc: clock-cccref { compatible = "fixed-clock"; #clock-cells = <0>; }; From d6d9d9be2aa407c10911967a3115654b21a5c23d Mon Sep 17 00:00:00 2001 From: Valentina Fernandez Date: Mon, 8 Sep 2025 12:57:31 +0100 Subject: [PATCH 588/931] dt-bindings: riscv: microchip: document Discovery Kit The Discovery Kit (MPFS-DISCO-KIT) is a development board featuring a Microchip PolarFire SoC MPFS095T. Link: https://www.microchip.com/en-us/development-tool/mpfs-disco-kit Signed-off-by: Valentina Fernandez Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 8ddc5c02973e..381d6eb6672e 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -33,6 +33,11 @@ properties: - const: microchip,mpfs-icicle-kit - const: microchip,mpfs + - items: + - const: microchip,mpfs-disco-kit-reference-rtl-v2507 + - const: microchip,mpfs-disco-kit + - const: microchip,mpfs + - items: - enum: - aldec,tysom-m-mpfs250t-rev2 From acc211539c81b2f2f0d15827dad2bf308b1712d0 Mon Sep 17 00:00:00 2001 From: Valentina Fernandez Date: Mon, 8 Sep 2025 12:57:32 +0100 Subject: [PATCH 589/931] riscv: dts: microchip: add a device tree for Discovery Kit Add a minimal device tree for the Microchip PolarFire SoC Discovery Kit. The Discovery Kit is a cost-optimized board based on PolarFire SoC MPFS095T and features: - 1 GB DDR4x16 - 1x Gigabit Ethernet - 3x UARTs - Raspberry Pi connector - mikroBus connector - microSD card connector Link: https://www.microchip.com/en-us/development-tool/mpfs-disco-kit Signed-off-by: Valentina Fernandez Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-disco-kit-fabric.dtsi | 58 ++++++ .../boot/dts/microchip/mpfs-disco-kit.dts | 190 ++++++++++++++++++ 3 files changed, 249 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index 1e2f4e41bf0d..345ed7a48cc1 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-disco-kit.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit-prod.dtb dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi new file mode 100644 index 000000000000..ae8be7d6f392 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2025 Microchip Technology Inc */ + +/ { + core_pwm0: pwm@40000000 { + compatible = "microchip,corepwm-rtl-v4"; + reg = <0x0 0x40000000 0x0 0xF0>; + microchip,sync-update-mask = /bits/ 32 <0>; + #pwm-cells = <3>; + clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>; + status = "disabled"; + }; + + i2c2: i2c@40000200 { + compatible = "microchip,corei2c-rtl-v7"; + reg = <0x0 0x40000200 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>; + interrupt-parent = <&plic>; + interrupts = <122>; + clock-frequency = <100000>; + status = "disabled"; + }; + + ihc: mailbox { + compatible = "microchip,sbi-ipc"; + interrupt-parent = <&plic>; + interrupts = <180>, <179>, <178>, <177>; + interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4"; + #mbox-cells = <1>; + status = "disabled"; + }; + + mailbox@50000000 { + compatible = "microchip,miv-ihc-rtl-v2"; + reg = <0x0 0x50000000 0x0 0x1c000>; + interrupt-parent = <&plic>; + interrupts = <180>, <179>, <178>, <177>; + interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4"; + #mbox-cells = <1>; + microchip,ihc-chan-disabled-mask = /bits/ 16 <0>; + status = "disabled"; + }; + + refclk_ccc: clock-cccref { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; +}; + +&ccc_sw { + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts new file mode 100644 index 000000000000..c068b9bb5bfd --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2025 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-disco-kit-fabric.dtsi" +#include +#include + +/ { + model = "Microchip PolarFire-SoC Discovery Kit"; + compatible = "microchip,mpfs-disco-kit-reference-rtl-v2507", + "microchip,mpfs-disco-kit", + "microchip,mpfs"; + + aliases { + ethernet0 = &mac0; + serial4 = &mmuart4; + }; + + chosen { + stdout-path = "serial4:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + color = ; + label = "led1"; + }; + + led-2 { + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + color = ; + label = "led2"; + }; + + led-3 { + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + color = ; + label = "led3"; + }; + + led-4 { + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + color = ; + label = "led4"; + }; + + led-5 { + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + color = ; + label = "led5"; + }; + + led-6 { + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + color = ; + label = "led6"; + }; + + led-7 { + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + color = ; + label = "led7"; + }; + + led-8 { + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + color = ; + label = "led8"; + }; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hss_payload: region@bfc00000 { + reg = <0x0 0xbfc00000 0x0 0x400000>; + no-map; + }; + }; +}; + +&core_pwm0 { + status = "okay"; +}; + +&gpio1 { + interrupts = <27>, <28>, <29>, <30>, + <31>, <32>, <33>, <47>, + <35>, <36>, <37>, <38>, + <39>, <40>, <41>, <42>, + <43>, <44>, <45>, <46>, + <47>, <48>, <49>, <50>; + status = "okay"; +}; + +&gpio2 { + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&ihc { + status = "okay"; +}; + +&mac0 { + phy-mode = "sgmii"; + phy-handle = <&phy0>; + status = "okay"; + + phy0: ethernet-phy@b { + reg = <0xb>; + }; +}; + +&mbox { + status = "okay"; +}; + +&mmc { + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-1-8-v; + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +&mmuart4 { + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&refclk_ccc { + clock-frequency = <50000000>; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +}; From b11aa9565f800fe33369936a1730de2e344ea5ef Mon Sep 17 00:00:00 2001 From: Andrea della Porta Date: Fri, 5 Sep 2025 11:42:39 +0200 Subject: [PATCH 590/931] arm64: dts: broadcom: rp1: Add USB nodes The RaspberryPi 5 has RP1 chipset containing two USB host controller, while presenting two USB 2.0 and two USB 3.0 ports to the outside. Add the relevant USB nodes to the devicetree. Signed-off-by: Andrea della Porta Link: https://lore.kernel.org/r/16d753cb4bf37beb5e9c6f0e03576cf13708f27d.1757065053.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/rp1-common.dtsi | 28 ++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi index 6bdc304c5f24..5a815c379794 100644 --- a/arch/arm64/boot/dts/broadcom/rp1-common.dtsi +++ b/arch/arm64/boot/dts/broadcom/rp1-common.dtsi @@ -55,4 +55,32 @@ rp1_eth: ethernet@40100000 { #address-cells = <1>; #size-cells = <0>; }; + + rp1_usb0: usb@40200000 { + compatible = "snps,dwc3"; + reg = <0x00 0x40200000 0x0 0x100000>; + interrupts = <31 IRQ_TYPE_EDGE_RISING>; + dr_mode = "host"; + usb3-lpm-capable; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + snps,tx-max-burst = /bits/ 8 <8>; + snps,tx-thr-num-pkt = /bits/ 8 <2>; + status = "disabled"; + }; + + rp1_usb1: usb@40300000 { + compatible = "snps,dwc3"; + reg = <0x00 0x40300000 0x0 0x100000>; + interrupts = <36 IRQ_TYPE_EDGE_RISING>; + dr_mode = "host"; + usb3-lpm-capable; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + snps,tx-max-burst = /bits/ 8 <8>; + snps,tx-thr-num-pkt = /bits/ 8 <2>; + status = "disabled"; + }; }; From 70bab1937e39fd8f6efc80fd1a8b4da63622dd81 Mon Sep 17 00:00:00 2001 From: Andrea della Porta Date: Fri, 5 Sep 2025 11:42:40 +0200 Subject: [PATCH 591/931] arm64: dts: broadcom: Enable USB devicetree entries for Rpi5 RaspberryPi 5 presents two USB 2.0 and two USB 3.0 ports. Configure and enable the USB nodes in the devicetree. Signed-off-by: Andrea della Porta Link: https://lore.kernel.org/r/c6b17f0f896b5cdd790fc10aeb2b76b71df9b58d.1757065053.git.andrea.porta@suse.com Signed-off-by: Florian Fainelli --- .../arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts index 2045a221c393..b8f256545022 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -39,3 +39,20 @@ phy1: ethernet-phy@1 { }; }; }; + +&rp1_gpio { + usb_vbus_default_state: usb-vbus-default-state { + function = "vbus1"; + groups = "vbus1"; + }; +}; + +&rp1_usb0 { + pinctrl-0 = <&usb_vbus_default_state>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rp1_usb1 { + status = "okay"; +}; From 3708a165a98c23cc83216deda88bc7d64ba85527 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 29 Aug 2025 16:13:29 -0500 Subject: [PATCH 592/931] ARM: dts: aspeed: Drop syscon "reg-io-width" properties The default width is 4 bytes for "syscon" devices, so "reg-io-width" is redundant and can be dropped. Signed-off-by: Rob Herring (Arm) Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-g4.dtsi | 1 - arch/arm/boot/dts/aspeed/aspeed-g5.dtsi | 2 -- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 2 -- 3 files changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi index 78c967812492..c3d4d916c69b 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi @@ -356,7 +356,6 @@ vuart: serial@1e787000 { lpc: lpc@1e789000 { compatible = "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"; reg = <0x1e789000 0x1000>; - reg-io-width = <4>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi index 57a699a7c149..39500bdb4747 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi @@ -273,7 +273,6 @@ hace: crypto@1e6e3000 { gfx: display@1e6e6000 { compatible = "aspeed,ast2500-gfx", "syscon"; reg = <0x1e6e6000 0x1000>; - reg-io-width = <4>; clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; resets = <&syscon ASPEED_RESET_CRT1>; syscon = <&syscon>; @@ -441,7 +440,6 @@ vuart: serial@1e787000 { lpc: lpc@1e789000 { compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; reg = <0x1e789000 0x1000>; - reg-io-width = <4>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 61983feb2a4e..f8662c8ac089 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -382,7 +382,6 @@ rng: hwrng@1e6e2524 { gfx: display@1e6e6000 { compatible = "aspeed,ast2600-gfx", "syscon"; reg = <0x1e6e6000 0x1000>; - reg-io-width = <4>; clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; resets = <&syscon ASPEED_RESET_GRAPHICS>; syscon = <&syscon>; @@ -572,7 +571,6 @@ peci0: peci-controller@1e78b000 { lpc: lpc@1e789000 { compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"; reg = <0x1e789000 0x1000>; - reg-io-width = <4>; #address-cells = <1>; #size-cells = <1>; From f8c9fabf2f3d87773613734a8479d0ef9b662b11 Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Thu, 17 Jul 2025 17:29:54 +0800 Subject: [PATCH 593/931] dts: arm: amlogic: fix pwm node for c3 Fix reg address for c3 pwm node. Fixes: be90cd4bd422 ("arm64: dts: amlogic: Add Amlogic C3 PWM") Signed-off-by: Xianwei Zhao Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20250717-fix-pwm-node-v2-1-7365ac7d5320@amlogic.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi index e8529e8c4b15..07aaaf71ea9a 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -822,7 +822,7 @@ spicc1: spi@52000 { pwm_mn: pwm@54000 { compatible = "amlogic,c3-pwm", "amlogic,meson-s4-pwm"; - reg = <0x0 54000 0x0 0x24>; + reg = <0x0 0x54000 0x0 0x24>; clocks = <&clkc_periphs CLKID_PWM_M>, <&clkc_periphs CLKID_PWM_N>; #pwm-cells = <3>; From 663bfe77b6f70bcb33b2607e16c94fcb1029580e Mon Sep 17 00:00:00 2001 From: Valerio Setti Date: Mon, 8 Sep 2025 21:50:03 +0200 Subject: [PATCH 594/931] arm64: dts: amlogic: gxbb-odroidc2: remove UHS capability for SD card This is meant to resolve reboot not working on this board. The problem is as follows. In order to be able to switch from HS to UHS mode the bus voltage needs to be reduced from 3.3V down to 1.8V and this is achieved by the "vqmmc-supply" regulator. The ROM bootloader is only able to manage the card in HS mode (3.3V) and the switch HS->UHS happen at boottime in the kernel. The problem appears when the reboot command is issued or watchdog expires because in this case the "vqmmc-supply" voltage is not returned back at 3.3V before rebooting the board so the ROM bootloader will be completely stuck. Therefore this commit removes all UHS modes which would cause "vqmmc-summply" to switch from 3.3V to 1.8V. In terms of performance the main drawback of this commit is limiting the SD card bus speed to HS (25 MB/s) instead of UHS DDR50 (50 MB/s). However this comes with the benefit of being able to reboot the board, so it sounds like a reasonable compromise. Reviewed-by: Jerome Brunet Signed-off-by: Valerio Setti Link: https://lore.kernel.org/r/20250908-fix-reboot-v2-1-354d0e57c855@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 959bd8d77a82..12e26f99d4f0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -348,10 +348,6 @@ &sd_emmc_b { bus-width = <4>; cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; max-frequency = <100000000>; disable-wp; From dada1966cc3c342e3e700cc943b7c947c5e9aa93 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= Date: Wed, 9 Jul 2025 09:28:47 +0200 Subject: [PATCH 595/931] ARM: dts: imx6-aristainetos2: Replace license text comment with SPDX identifier MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace verbatim license text with a `SPDX-License-Identifier`. The comment header mis-attributes this license to be "X11", but the license text does not include the last line "Except as contained in this notice, the name of the X Consortium shall not be used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from the X Consortium.". Therefore, this license is actually equivalent to the SPDX "MIT" license (confirmed by text diffing). Cc: Heiko Schocher Signed-off-by: Bence Csókás Reviewed-by: Heiko Schocher Signed-off-by: Shawn Guo --- .../dts/nxp/imx/imx6dl-aristainetos2_4.dts | 38 +------------------ .../dts/nxp/imx/imx6dl-aristainetos2_7.dts | 38 +------------------ .../dts/nxp/imx/imx6qdl-aristainetos2.dtsi | 38 +------------------ 3 files changed, 3 insertions(+), 111 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts index c9b2ea2b24b2..fc62ba2a4fcb 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) /* * support for the imx6 based aristainetos2 board * * Copyright (C) 2015 Heiko Schocher - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; #include "imx6dl.dtsi" diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts index 5e15212eaf3a..a7400d42475b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_7.dts @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) /* * support for the imx6 based aristainetos2 board * * Copyright (C) 2015 Heiko Schocher - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; #include "imx6dl.dtsi" diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi index 7cc7ae195988..57970f29367d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi @@ -1,44 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) /* * support for the imx6 based aristainetos2 board * * Copyright (C) 2015 Heiko Schocher - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include #include From 2f572b0def6e90e4a6cf90f3a8cb11d4def7b637 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 18 Jul 2025 17:47:22 +0800 Subject: [PATCH 596/931] dt-bindings: firmware: imx95-scmi: Allow linux,code for protocol@81 BBM protocol supports a single power button, supported by driver imx-sm-bbm-key.c. By default this is KEY_POWER, but can also be overwritten using linux,code. Add a reference to this schema and add linux,code as a supported property. Reviewed-by: Rob Herring (Arm) Signed-off-by: Alexander Stein Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- .../devicetree/bindings/firmware/nxp,imx95-scmi.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml b/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml index 2bda2e0e1369..7a5a02da2719 100644 --- a/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml @@ -24,13 +24,19 @@ properties: const: 0x80 protocol@81: - $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' - unevaluatedProperties: false + type: object + allOf: + - $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' + - $ref: /schemas/input/input.yaml# + additionalProperties: false properties: reg: const: 0x81 + linux,code: + default: 116 # KEY_POWER + protocol@82: description: SCMI CPU Protocol which allows an agent to start or stop a CPU. It is From 930b6fe1a50c7ba69608230322614c87ea3dd35e Mon Sep 17 00:00:00 2001 From: Mateusz Koza Date: Mon, 8 Sep 2025 15:05:35 +0200 Subject: [PATCH 597/931] dt-bindings: arm: mediatek: Add grinn,genio-700-sbc Add device tree bindings support for the Grinn GenioSBC-700, a single-board computer based on the MediaTek Genio 700 SoC. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-700 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Acked-by: Conor Dooley Signed-off-by: Mateusz Koza Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250908130620.2309399-3-mateusz.koza@grinn-global.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 19ed9448c9c2..448241939a75 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -436,6 +436,7 @@ properties: - const: mediatek,mt8188 - items: - enum: + - grinn,genio-700-sbc - mediatek,mt8390-evk - const: mediatek,mt8390 - const: mediatek,mt8188 From 12a565af705542c4380e95f4e3a505a2c25ad754 Mon Sep 17 00:00:00 2001 From: Mateusz Koza Date: Mon, 8 Sep 2025 15:05:37 +0200 Subject: [PATCH 598/931] dt-bindings: arm: mediatek: Add grinn,genio-510-sbc Add device tree bindings support for the Grinn GenioSBC-510, a single-board computer based on the MediaTek Genio 510 SoC. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-510 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Acked-by: Conor Dooley Signed-off-by: Mateusz Koza Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250908130620.2309399-5-mateusz.koza@grinn-global.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 448241939a75..f04277873694 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -431,6 +431,7 @@ properties: - const: mediatek,mt8365 - items: - enum: + - grinn,genio-510-sbc - mediatek,mt8370-evk - const: mediatek,mt8370 - const: mediatek,mt8188 From 0e3f9140ad04dca9a6a93dd6a6decdc53fd665ca Mon Sep 17 00:00:00 2001 From: Quanyang Wang Date: Tue, 2 Sep 2025 09:56:18 +0200 Subject: [PATCH 599/931] arm64: zynqmp: Disable coresight by default When secure-boot mode of bootloader is enabled, the registers of coresight are not permitted to access that's why disable it by default. Signed-off-by: Quanyang Wang Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/7e308b8efe977c4912079b4d1b1ab3d24908559e.1756799774.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 5f26649c9e11..938b014ca923 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -550,6 +550,7 @@ cpu0_debug: debug@fec10000 { reg = <0x0 0xfec10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu0>; + status = "disabled"; }; cpu1_debug: debug@fed10000 { @@ -557,6 +558,7 @@ cpu1_debug: debug@fed10000 { reg = <0x0 0xfed10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu1>; + status = "disabled"; }; cpu2_debug: debug@fee10000 { @@ -564,6 +566,7 @@ cpu2_debug: debug@fee10000 { reg = <0x0 0xfee10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu2>; + status = "disabled"; }; cpu3_debug: debug@fef10000 { @@ -571,6 +574,7 @@ cpu3_debug: debug@fef10000 { reg = <0x0 0xfef10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu3>; + status = "disabled"; }; /* GDMA */ From 767ecf9da7b31e5c0c22c273001cb2784705fe8c Mon Sep 17 00:00:00 2001 From: Radhey Shyam Pandey Date: Tue, 2 Sep 2025 09:56:19 +0200 Subject: [PATCH 600/931] arm64: zynqmp: Revert usb node drive strength and slew rate for zcu106 On a few zcu106 boards USB devices (Dell MS116 USB Optical Mouse, Dell USB Entry Keyboard) are not enumerated on linux boot due to commit 'b8745e7eb488 ("arm64: zynqmp: Fix usb node drive strength and slew rate")'. To fix it as a workaround revert to working version and then investigate at board level why drive strength from 12mA to 4mA and slew from fast to slow is not working. Signed-off-by: Radhey Shyam Pandey Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/85a70cb014ec1f07972fccb60b875596eeaa6b5c.1756799774.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index cd132abf6e00..7f6c87d4d77e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -808,8 +808,8 @@ conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; - drive-strength = <4>; - slew-rate = ; + drive-strength = <12>; + slew-rate = ; }; }; From eb4a09d8cc31c90adaa12136ffdb7b57a6410873 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 Sep 2025 09:56:20 +0200 Subject: [PATCH 601/931] arm64: zynqmp: Describe ethernet controllers via aliases on SOM Add ethernet aliases to CC (Carrier card) description to create a connection which is used by U-BOOT (fdt_fixup_ethernet()) for updating local-mac-address in DT. On Kria SOM MAC address is read from i2c eeprom at start and based on it environment variables are created. Without creating aliases U-Boot is not able to inject local-mac-address DT property and OS won't get the same MAC address unless another i2c read is happening in OS. Also aliases are using string not phandle (because of dtso) that's why full path has to be provided but that shouldn't be a big issue because location of ethernet controller is fixed. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/72304150f87fd5e3338e31e2be8cf5d29955cc02.1756799774.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso | 5 +++++ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 4 ++++ 3 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso index b7cda216b179..99ad220d13d6 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso @@ -20,6 +20,11 @@ "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; model = "ZynqMP KR260 revB"; + aliases { + ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */ + ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + ina260-u14 { compatible = "iio-hwmon"; io-channels = <&u14 0>, <&u14 1>, <&u14 2>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index a98a888d1385..3c36eb52e968 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -28,6 +28,10 @@ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; model = "ZynqMP KV260 revA"; + aliases { + ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ + }; + ina260-u14 { compatible = "iio-hwmon"; io-channels = <&u14 0>, <&u14 1>, <&u14 2>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 1d2b46d7949e..a4ae37ebaccf 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -23,6 +23,10 @@ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; model = "ZynqMP KV260 revB"; + aliases { + ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ + }; + ina260-u14 { compatible = "iio-hwmon"; io-channels = <&u14 0>, <&u14 1>, <&u14 2>; From 21ad89cfade7724960a02ce675f6cd33f89515ed Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 Sep 2025 09:56:21 +0200 Subject: [PATCH 602/931] arm64: zynqmp: Enable DP in kr260/kv260 revA Enable DP output in both CC (Carrier Cards). Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/3160658ea2c4dd09a1d68918271177cf55437a8f.1756799774.git.michal.simek@amd.com --- .../boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso | 17 +++++++++++++++++ .../boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 17 +++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso index fbacfa984d76..b92dcb86e87e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso @@ -71,6 +71,17 @@ clk_25_1: si5332-4 { /* u17 - GEM3 */ #clock-cells = <0>; clock-frequency = <25000000>; }; + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ @@ -145,6 +156,12 @@ &zynqmp_dpsub { assigned-clock-rates = <27000000>, <25000000>, <300000000>; }; +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; + &zynqmp_dpdma { status = "okay"; assigned-clock-rates = <600000000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 3c36eb52e968..d7351a17d3e8 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -72,6 +72,17 @@ si5332_5: si5332-5 { /* u17 */ #clock-cells = <0>; clock-frequency = <27000000>; }; + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -122,6 +133,12 @@ &zynqmp_dpsub { assigned-clock-rates = <27000000>, <25000000>, <300000000>; }; +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; + &zynqmp_dpdma { status = "okay"; assigned-clock-rates = <600000000>; From 0e81960419ad186378b4cb55d7939d03c85262ab Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 8 Sep 2025 15:33:48 +0200 Subject: [PATCH 603/931] arm64: versal-net: Describe L1/L2/L3/LLC caches Add missing cache layout description. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f740bf2d0af1e7e50d76196ec050c0fdbeceb049.1757338426.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/versal-net.dtsi | 408 +++++++++++++++++++++ 1 file changed, 408 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/versal-net.dtsi b/arch/arm64/boot/dts/xilinx/versal-net.dtsi index c037a7819967..412af9a394aa 100644 --- a/arch/arm64/boot/dts/xilinx/versal-net.dtsi +++ b/arch/arm64/boot/dts/xilinx/versal-net.dtsi @@ -104,6 +104,28 @@ cpu0: cpu@0 { reg = <0>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_00>; + l2_00: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_0>; + }; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; @@ -112,6 +134,28 @@ cpu100: cpu@100 { reg = <0x100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_01>; + l2_01: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_0>; + }; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; @@ -120,6 +164,28 @@ cpu200: cpu@200 { reg = <0x200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_02>; + l2_02: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_0>; + }; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; @@ -128,6 +194,28 @@ cpu300: cpu@300 { reg = <0x300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_03>; + l2_03: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_0>; + }; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; @@ -136,6 +224,28 @@ cpu10000: cpu@10000 { reg = <0x10000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_10>; + l2_10: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_1>; + }; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; @@ -144,6 +254,28 @@ cpu10100: cpu@10100 { reg = <0x10100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_11>; + l2_11: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_1>; + }; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; @@ -152,6 +284,28 @@ cpu10200: cpu@10200 { reg = <0x10200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_12>; + l2_12: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_1>; + }; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; @@ -160,6 +314,28 @@ cpu10300: cpu@10300 { reg = <0x10300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_13>; + l2_13: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_1>; + }; }; cpu20000: cpu@20000 { compatible = "arm,cortex-a78"; @@ -168,6 +344,28 @@ cpu20000: cpu@20000 { reg = <0x20000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_20>; + l2_20: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_2>; + }; }; cpu20100: cpu@20100 { compatible = "arm,cortex-a78"; @@ -176,6 +374,28 @@ cpu20100: cpu@20100 { reg = <0x20100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_21>; + l2_21: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_2>; + }; }; cpu20200: cpu@20200 { compatible = "arm,cortex-a78"; @@ -184,6 +404,28 @@ cpu20200: cpu@20200 { reg = <0x20200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_22>; + l2_22: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_2>; + }; }; cpu20300: cpu@20300 { compatible = "arm,cortex-a78"; @@ -192,6 +434,28 @@ cpu20300: cpu@20300 { reg = <0x20300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_23>; + l2_23: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_2>; + }; }; cpu30000: cpu@30000 { compatible = "arm,cortex-a78"; @@ -200,6 +464,28 @@ cpu30000: cpu@30000 { reg = <0x30000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_30>; + l2_30: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_3>; + }; }; cpu30100: cpu@30100 { compatible = "arm,cortex-a78"; @@ -208,6 +494,28 @@ cpu30100: cpu@30100 { reg = <0x30100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_31>; + l2_31: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_3>; + }; }; cpu30200: cpu@30200 { compatible = "arm,cortex-a78"; @@ -216,6 +524,28 @@ cpu30200: cpu@30200 { reg = <0x30200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_32>; + l2_32: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_3>; + }; }; cpu30300: cpu@30300 { compatible = "arm,cortex-a78"; @@ -224,7 +554,85 @@ cpu30300: cpu@30300 { reg = <0x30300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + d-cache-size = <0x10000>; /* 64kB */ + d-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + d-cache-sets = <256>; + i-cache-size = <0x10000>; /* 64kB */ + i-cache-line-size = <64>; + /* 4 ways set associativity */ + /* cache_size / (line_size / associativity) */ + i-cache-sets = <256>; + next-level-cache = <&l2_33>; + l2_33: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; /* 512kB */ + cache-line-size = <64>; + /* 8 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <1024>; + cache-unified; + next-level-cache = <&l3_3>; + }; }; + + l3_0: l3-0-cache { /* cluster private */ + compatible = "cache"; + cache-level = <3>; + cache-size = <0x200000>; /* 2MB */ + cache-line-size = <64>; + /* 16 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <2048>; + cache-unified; + next-level-cache = <&llc>; + }; + + l3_1: l3-1-cache { /* cluster private */ + compatible = "cache"; + cache-level = <3>; + cache-size = <0x200000>; /* 2MB */ + cache-line-size = <64>; + /* 16 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <2048>; + cache-unified; + next-level-cache = <&llc>; + }; + + l3_2: l3-2-cache { /* cluster private */ + compatible = "cache"; + cache-level = <3>; + cache-size = <0x200000>; /* 2MB */ + cache-line-size = <64>; + /* 16 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <2048>; + cache-unified; + next-level-cache = <&llc>; + }; + + l3_3: l3-3-cache { /* cluster private */ + compatible = "cache"; + cache-level = <3>; + cache-size = <0x200000>; /* 2MB */ + cache-line-size = <64>; + /* 16 ways set associativity */ + /* cache_size / (line_size/associativity) */ + cache-sets = <2048>; + cache-unified; + next-level-cache = <&llc>; + }; + + llc: l4-cache { /* LLC inside CMN */ + compatible = "cache"; + cache-level = <4>; + cache-size = <0x1000000>; /* 16MB */ + cache-unified; + }; + idle-states { entry-method = "psci"; From a15f095b590bcc1968fbf2ced8fe87fbd8d012e0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 9 Sep 2025 02:10:55 +0800 Subject: [PATCH 604/931] arm64: dts: allwinner: a527: cubie-a5e: Add ethernet PHY reset setting The external Ethernet PHY has a reset pin that is connected to the SoC. It is missing from the original submission. Add it to complete the description. Fixes: acca163f3f51 ("arm64: dts: allwinner: a527: add EMAC0 to Radxa A5E board") Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250908181059.1785605-7-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 70d439bc845c..d4cee2222104 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -94,6 +94,9 @@ &mdio0 { ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; + reset-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ + reset-assert-us = <10000>; + reset-deassert-us = <150000>; }; }; From 8dc3f973b2ff7ea19f7637983c11b005daa8fe45 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 9 Sep 2025 02:10:57 +0800 Subject: [PATCH 605/931] arm64: dts: allwinner: t527: avaota-a1: Add ethernet PHY reset setting The external Ethernet PHY has a reset pin that is connected to the SoC. It is missing from the original submission. Add it to complete the description. Fixes: c6800f15998b ("arm64: dts: allwinner: t527: add EMAC0 to Avaota-A1 board") Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250908181059.1785605-9-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index b9eeb6753e9e..e7713678208d 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -85,6 +85,9 @@ &mdio0 { ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; + reset-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ + reset-assert-us = <10000>; + reset-deassert-us = <150000>; }; }; From c3ad87de22e57e35b1c516f85aa6ea5c81ec5754 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:46:57 -0400 Subject: [PATCH 606/931] ARM: dts: lpc18xx: rename node name flash-controller to spi Anyway it is SPI controller although intent to connect qspi flash. Rename node name flash-controller to spi to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: flash-controller@40003000 (nxp,lpc1773-spifi): $nodename:0: 'flash-controller@40003000' does not match '^spi(@.*|-([0-9]|[1-9][0-9]+))?$ Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi index 6dd73290f0c6..e17298e89eeb 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi @@ -100,7 +100,7 @@ dmac: dma-controller@40002000 { memcpy-bus-width = <32>; }; - spifi: flash-controller@40003000 { + spifi: spi@40003000 { compatible = "nxp,lpc1773-spifi"; reg = <0x40003000 0x1000>, <0x14000000 0x4000000>; reg-names = "spifi", "flash"; From 3d2a00271e0b425073750b6b2ca51460061d3fdd Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:46:58 -0400 Subject: [PATCH 607/931] ARM: dts: lpc18xx: rename node name mmcsd to mmc Change node name mmcsd to mmc to fix CHECK_DTB warnings: arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: mmcsd@40004000 (snps,dw-mshc): $nodename:0: 'mmcsd@40004000' does not match '^mmc(@.*)?$' Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi index e17298e89eeb..80da477bae3d 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi @@ -111,7 +111,7 @@ spifi: spi@40003000 { status = "disabled"; }; - mmcsd: mmcsd@40004000 { + mmcsd: mmc@40004000 { compatible = "snps,dw-mshc"; reg = <0x40004000 0x1000>; interrupts = <6>; From 4e328041248c5f8a85f576fac16de6118c8d9bec Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:46:59 -0400 Subject: [PATCH 608/931] ARM: dts: lpc4350-hitex-eval: change node name flash to flash@0 Change node name 'flash' to 'flash@0' to fix below CHECK_DTB warnings. arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dtb: flash-controller@40003000 (nxp,lpc1773-spifi): Unevaluated properties are not allowed ('flash' was unexpected) from schema $id: http://devicetree.org/schemas/mtd/nxp,lpc1773-spifi.yaml# Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts | 3 ++- arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts | 3 ++- arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts index 93d0c2e99e7c..8fc89fb6eef1 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts @@ -451,8 +451,9 @@ &spifi { pinctrl-names = "default"; pinctrl-0 = <&spifi_pins>; - flash { + flash@0 { compatible = "jedec,spi-nor"; + reg = <0>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts index 4aefbc01dfc0..60bcfa5e0518 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts @@ -582,8 +582,9 @@ &spifi { pinctrl-names = "default"; pinctrl-0 = <&spifi_pins>; - flash { + flash@0 { compatible = "jedec,spi-nor"; + reg = <0>; spi-cpol; spi-cpha; spi-rx-bus-width = <4>; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts index 846afb8ccbf1..22f7dd671c90 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts @@ -569,8 +569,9 @@ &spifi { pinctrl-0 = <&spifi_pins>; /* Atmel AT25DF321A */ - flash { + flash@0 { compatible = "jedec,spi-nor"; + reg = <0>; spi-max-frequency = <51000000>; spi-cpol; spi-cpha; From 5460b42b65cd36113114d45e519359f129c7331c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:00 -0400 Subject: [PATCH 609/931] ARM: dts: lpc18xx: swap clock-names bic and cui Swap clock-names bic and cui to fix below CHECK_DTB warnings: /home/lizhi/source/linux-upstream-pci/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dtb: mmc@40004000 (snps,dw-mshc): clock-names:0: 'biu' was expected from schema $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml# /home/lizhi/source/linux-upstream-pci/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dtb: mmc@40004000 (snps,dw-mshc): clock-names:1: 'ciu' was expected Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi index 80da477bae3d..0be2486f0717 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi @@ -115,8 +115,8 @@ mmcsd: mmc@40004000 { compatible = "snps,dw-mshc"; reg = <0x40004000 0x1000>; interrupts = <6>; - clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>; - clock-names = "ciu", "biu"; + clocks = <&ccu1 CLK_CPU_SDIO>, <&ccu2 CLK_SDIO>; + clock-names = "biu", "ciu"; resets = <&rgu 20>; status = "disabled"; }; From 9276abee591ae0a82cc7184653ac8d77d2eb7b88 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:01 -0400 Subject: [PATCH 610/931] ARM: dts: lpc: add #address-cells and #size-cells for sram node Add #address-cells and #size-cells for sram node to fix below DTB_CHECK warnings: arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dtb: sram@2,0 (mmio-sram): '#address-cells' is a required property Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts | 3 +++ arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi | 9 +++++++++ arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi | 9 +++++++++ 3 files changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts index 8fc89fb6eef1..9d36283efe0f 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts @@ -406,6 +406,9 @@ cs2 { ext_sram: sram@2,0 { compatible = "mmio-sram"; reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 2 0 0x80000>; }; }; }; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi index c4422f587055..707d22a219d8 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi @@ -24,16 +24,25 @@ soc { sram0: sram@10000000 { compatible = "mmio-sram"; reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; sram1: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; sram2: sram@20000000 { compatible = "mmio-sram"; reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; }; }; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi index 72f12db8d53a..d138ee7869ff 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi @@ -24,16 +24,25 @@ soc { sram0: sram@10000000 { compatible = "mmio-sram"; reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; sram1: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; sram2: sram@20000000 { compatible = "mmio-sram"; reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */ + #address-cells = <1>; + #size-cells = <1>; + ranges; }; }; }; From fcc5f89e3050e3bb3c25c49c87ea8d3100e2cf34 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:02 -0400 Subject: [PATCH 611/931] ARM: dts: lpc: add cfg surfix in pinctrl child node Add cfg surfix in pinctrl child node to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: pinctrl@40086000 (nxp,lpc1850-scu): ssp-pins: 'ssp1_cs', 'ssp1_miso_mosi', 'ssp1_sck' do not match any of the regexes: '^pinctrl-[0-9]+$', '_cfg$' from schema $id: http://devicetree.org/schemas/pinctrl/nxp,lpc1850-scu.yaml# Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts | 6 +++--- arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts b/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts index beddaba85393..5ff43c825944 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts @@ -108,14 +108,14 @@ i2c0_pins_cfg { }; ssp_pins: ssp-pins { - ssp1_cs { + ssp1_cs_cfg { pins = "p6_7"; function = "gpio"; bias-pull-up; bias-disable; }; - ssp1_miso_mosi { + ssp1_miso_mosi_cfg { pins = "p1_3", "p1_4"; function = "ssp1"; slew-rate = <1>; @@ -124,7 +124,7 @@ ssp1_miso_mosi { input-schmitt-disable; }; - ssp1_sck { + ssp1_sck_cfg { pins = "pf_4"; function = "ssp1"; slew-rate = <1>; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts index 60bcfa5e0518..9dc8c3cc2211 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts @@ -403,7 +403,7 @@ spifi_cs_cfg { }; ssp0_pins: ssp0-pins { - ssp0_sck_miso_mosi { + ssp0_sck_miso_mosi_cfg { pins = "pf_0", "pf_2", "pf_3"; function = "ssp0"; slew-rate = <1>; @@ -412,7 +412,7 @@ ssp0_sck_miso_mosi { input-schmitt-disable; }; - ssp0_ssel { + ssp0_ssel_cfg { pins = "pf_1"; function = "ssp0"; bias-pull-up; @@ -452,12 +452,12 @@ uart3_tx_cfg { }; usb0_pins: usb0-pins { - usb0_pwr_enable { + usb0_pwr_enable_cfg { pins = "p2_3"; function = "usb0"; }; - usb0_pwr_fault { + usb0_pwr_fault_cfg { pins = "p8_0"; function = "usb0"; bias-disable; From 332d4e0092e8cb09f1cc0809260f1215d9371268 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:03 -0400 Subject: [PATCH 612/931] ARM: dts: lpc4357-myd-lpc4357: add power-supply for innolux,at070tn92 Add power-supply for innolux,at070tn92 to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dtb: panel (innolux,at070tn92): 'power-supply' is a required property Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts index 22f7dd671c90..ca91bb8f6ada 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts @@ -63,6 +63,7 @@ led6 { panel: panel { compatible = "innolux,at070tn92"; + power-supply = <&vcc>; port { panel_input: endpoint { From caa9c67398d129ec8ab2d1db9a6038d0a35e31df Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:04 -0400 Subject: [PATCH 613/931] ARM: dts: lpc: change node name 'button[0-9]' to button-[0-9]' Change node name 'button[0-9]' to button-[0-9]' to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dtb: pca_buttons (gpio-keys-polled): 'button0', ... do not match any of the regexes: '^(button|...', 'pinctrl-[0-9]+' Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts | 16 ++++++++-------- .../boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts | 10 +++++----- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts index 9d36283efe0f..18f757c56905 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts @@ -43,50 +43,50 @@ pca_buttons { poll-interval = <100>; autorepeat; - button0 { + button-0 { label = "joy:right"; linux,code = ; gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>; }; - button1 { + button-1 { label = "joy:up"; linux,code = ; gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>; }; - button2 { + button-2 { label = "joy:enter"; linux,code = ; gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>; }; - button3 { + button-3 { label = "joy:left"; linux,code = ; gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>; }; - button4 { + button-4 { label = "joy:down"; linux,code = ; gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>; }; - button5 { + button-5 { label = "user:sw3"; linux,code = ; gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>; }; - button6 { + button-6 { label = "user:sw4"; linux,code = ; gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>; }; - button7 { + button-7 { label = "user:sw5"; linux,code = ; gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts index 9dc8c3cc2211..7ccb4c2ca571 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts @@ -60,31 +60,31 @@ gpio_joystick { poll-interval = <100>; autorepeat; - button0 { + button-0 { label = "joy_enter"; linux,code = ; gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; }; - button1 { + button-1 { label = "joy_left"; linux,code = ; gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>; }; - button2 { + button-2 { label = "joy_up"; linux,code = ; gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>; }; - button3 { + button-3 { label = "joy_right"; linux,code = ; gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>; }; - button4 { + button-4 { label = "joy_down"; linux,code = ; gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>; From 212480c0e7cdfaf22b2cbb2f9144c9f357de2b1a Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:05 -0400 Subject: [PATCH 614/931] ARM: dts: lpc4357-myd-lpc4357: change node name mdio0 to mdio Change node name mdio0 to mdio to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dtb: ethernet@40010000 (nxp,lpc1850-dwmac): Unevaluated properties are not allowed ('mdio0' was unexpected) from schema $id: http://devicetree.org/schemas/net/nxp,lpc1850-dwmac.yaml Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts index ca91bb8f6ada..d18f2b2caf68 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts @@ -544,7 +544,7 @@ &mac { pinctrl-0 = <&enet_rmii_pins>; phy-handle = <&phy1>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; From a884b8fc2efd44665cd05a6878aa23345d97a5cb Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:06 -0400 Subject: [PATCH 615/931] ARM: dts: lpc18xx: add #address-cell and #szie-cell for spi flash controller Add #address-cells and #szie-cells for spi flash controller to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi:103.23-112.5: Warning (spi_bus_bridge): /soc/spi@40003000: incorrect #address-cells for SPI bus also defined at arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts:452.8-479.3 arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi:103.23-112.5: Warning (spi_bus_bridge): /soc/spi@40003000: incorrect #size-cells for SPI bus also defined at arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts:452.8-479.3 Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi index 0be2486f0717..d212ca252b06 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi @@ -107,6 +107,8 @@ spifi: spi@40003000 { interrupts = <30>; clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>; clock-names = "spifi", "reg"; + #address-cells = <1>; + #size-cells = <0>; resets = <&rgu 53>; status = "disabled"; }; From 70e42a63542e0d82ecfe2ae6c5fb5033a73c8c71 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Sun, 6 Jul 2025 14:47:07 -0400 Subject: [PATCH 616/931] ARM: dts: lpc18xx: add missed arm,num-irq-priority-bits Add missed arm,num-irq-priority-bits to fix below CHECK_DTBS warning: arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: interrupt-controller@e000e100 (arm,armv7m-nvic): 'arm,num-irq-priority-bits' is a required property from schema $id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml# Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi index d212ca252b06..152e98cf0c4e 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi @@ -537,3 +537,7 @@ gpio: gpio@400f4000 { }; }; }; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; From b17b850da6f9c4440a49d96cded5faa85123aadf Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Sep 2025 21:46:41 +0300 Subject: [PATCH 617/931] dt-bindings: arm: nxp: lpc: Assign myself as maintainer of NXP LPC32xx platforms Make a formal change to reflect the actual NXP LPC32xx maintainership for the last years. Cc: Roland Stigge Acked-by: Rob Herring (Arm) Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml b/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml index f1bd6f50e726..6b7f5e6f99cf 100644 --- a/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml +++ b/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: NXP LPC32xx Platforms maintainers: - - Roland Stigge + - Vladimir Zapolskiy properties: compatible: From 65ae9ea77e1f2a20ad2866f99596df7ccdbd3b95 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Sep 2025 21:46:42 +0300 Subject: [PATCH 618/931] ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cells MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since commit 4cd2f417a0ac ("dt-bindings: pwm: Convert lpc32xx-pwm.txt to yaml format") both types of PWM controlles on NXP LPC32xx SoC fairly gained 3 cells, reflect it in the platform dtsi file. The change removes a dt binding checker warning: mpwm@400e8000: #pwm-cells:0:0: 3 was expected Cc: Uwe Kleine-König Acked-by: Uwe Kleine-König Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 6cf405e9b082..916ab38f0a4c 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -301,8 +301,8 @@ i2c2: i2c@400a8000 { mpwm: mpwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; + #pwm-cells = <3>; status = "disabled"; - #pwm-cells = <2>; }; }; From 2695035dc347a27f16268f8ab8e510a564c96d38 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Sep 2025 21:46:43 +0300 Subject: [PATCH 619/931] ARM: dts: lpc32xx: Correct motor PWM device tree node name Change once a customly selected 'mpwm' node name in favour of the expected 'pwm' one. The change eliminates a reported warning: mpwm@400e8000: $nodename:0: 'mpwm@400e8000' does not match '^pwm(@.*|-([0-9]|[1-9][0-9]+))?$' Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 916ab38f0a4c..761432673c39 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -298,7 +298,7 @@ i2c2: i2c@400a8000 { clocks = <&clk LPC32XX_CLK_I2C2>; }; - mpwm: mpwm@400e8000 { + mpwm: pwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; #pwm-cells = <3>; From 88f55f0a985e3d612c47e754b807a455b92db360 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Sep 2025 21:46:44 +0300 Subject: [PATCH 620/931] ARM: dts: lpc32xx: Correct SD/MMC controller device node name Change the PL180 SD/MMC controller device node name to the expected 'mmc' one. The change removes a reported warning: sd@20098000: $nodename:0: 'sd@20098000' does not match '^mmc(@.*)?$' Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 761432673c39..c8b9d70e9362 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -224,7 +224,7 @@ i2s0: i2s@20094000 { status = "disabled"; }; - sd: sd@20098000 { + sd: mmc@20098000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x20098000 0x1000>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, From c4ceb7eeac34db30cd0c85b684b9ab26e9eb3cd2 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Sep 2025 21:46:45 +0300 Subject: [PATCH 621/931] ARM: dts: lpc32xx: Specify a precise version of the SD/MMC controller IP The SD/MMC controller on NXP LPC32xx SoC is ARM PrimeCell PL180, it is reported by the driver: mmci-pl18x 20098000.sd: mmc0: PL180 manf 41 rev0 at 0x20098000 irq 36,37 (pio) Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index c8b9d70e9362..522d616a9205 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -225,7 +225,7 @@ i2s0: i2s@20094000 { }; sd: mmc@20098000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl180", "arm,primecell"; reg = <0x20098000 0x1000>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, <13 IRQ_TYPE_LEVEL_HIGH>; From 181ffb8b06848d7f1fd289d2497f5e134f55b09e Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Sep 2025 21:46:46 +0300 Subject: [PATCH 622/931] ARM: dts: lpc32xx: Specify #dma-cells property of PL080 DMA controller For DMA controllers it is required to specify a number of the cells for users. The change eliminates the next build time reported warning: dma@31000000: '#dma-cells' is a required property Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 522d616a9205..a38f3c6dbe47 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -83,6 +83,7 @@ dma: dma@31000000 { interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_DMA>; clock-names = "apb_pclk"; + #dma-cells = <2>; }; usb { From d2dab63098bde9a6373eeb4672df806ad62a12da Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Sep 2025 21:46:47 +0300 Subject: [PATCH 623/931] ARM: dts: lpc32xx: Correct PL080 DMA controller device node name Rename PL080 DMA controller device node name to the expected one. The issue was reported by a dt binding checker: dma@31000000: $nodename:0: 'dma@31000000' does not match '^dma-controller(@.*)?$' Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index a38f3c6dbe47..2236901a0031 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -77,7 +77,7 @@ mlc: flash@200a8000 { status = "disabled"; }; - dma: dma@31000000 { + dma: dma-controller@31000000 { compatible = "arm,pl080", "arm,primecell"; reg = <0x31000000 0x1000>; interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; From 5ed941c73b7f501e32610ef0e82affa7ec36a71f Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 22 Aug 2025 10:49:58 -0400 Subject: [PATCH 624/931] ARM: dts: ls1021a: Rename node name nor to flash Rename node name nor to flash to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-twr.dtb: memory-controller@1530000 (fsl,ifc): 'nor@0,0' does not match any of the regexes: '(flash|fpga|board-control|cpld)@[a-f0-9]+(,[a-f0-9]+)+$', '^nand@[a-f0-9]+(,[a-f0-9]+)+$', '^pinctrl-[0-9]+$' Signed-off-by: Frank Li Reviewed-by: Alexander Stein Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts | 4 ++-- arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts index f1acb97aee69..8bc8ff2e3b03 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts @@ -66,7 +66,7 @@ &dspi0 { bus-num = <0>; status = "okay"; - dspiflash: at45db021d@0 { + dspiflash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash"; @@ -187,7 +187,7 @@ &ifc { <0x3 0x0 0x0 0x7fb00000 0x00000100>; status = "okay"; - nor@0,0 { + flash@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts index f5c03871b205..38281b904301 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts @@ -151,7 +151,7 @@ &ifc { ranges = <0x0 0x0 0x0 0x60000000 0x08000000>; status = "okay"; - nor@0,0 { + flash@0,0 { #address-cells = <1>; #size-cells = <1>; compatible = "cfi-flash"; From 6067121fbe1ac30c525da6069e0865e91db50541 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 22 Aug 2025 10:49:59 -0400 Subject: [PATCH 625/931] ARM: dts: ls1021a: Rename 'mdio-mux-emi1' to 'mdio-mux@54' Rename 'mdio-mux-emi1' to 'mdio-mux@54'. Add fallback compatible string mdio-mux. Fix below warning: arch/arm/boot/dts/nxp/ls/ls1021a-qds.dtb: memory-controller@1530000 (fsl,ifc): board-control@3,0: 'oneOf' conditional failed, one must be fixed: 'bank-width', 'device-width', 'mdio-mux-emi1' do not match any of the regexes: '^mdio-mux@[a-f0-9,]+$', 'pinctrl-[0-9]+' Signed-off-by: Frank Li Reviewed-by: Alexander Stein Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts index 8bc8ff2e3b03..a880875ced83 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts @@ -211,8 +211,8 @@ fpga: board-control@3,0 { device-width = <1>; ranges = <0 3 0 0x100>; - mdio-mux-emi1 { - compatible = "mdio-mux-mmioreg"; + mdio-mux@54 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; mdio-parent-bus = <&mdio0>; #address-cells = <1>; #size-cells = <0>; From e42a515aff9c42d7164ecd5ae40e63e7e4cfa13e Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 22 Aug 2025 10:50:00 -0400 Subject: [PATCH 626/931] ARM: dts: ls1021a: Rename esdhc@1560000 to mmc@1560000 Rename node name esdhc@1560000 to mmc@1560000 to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a-rgb-cdtech-fc21.dtb: esdhc@1560000 (fsl,ls1021a-esdhc): $nodename:0: 'esdhc@1560000' does not match '^mmc(@.*)?$' from schema $id: http://devicetree.org/schemas/mmc/fsl,esdhc.yaml# Signed-off-by: Frank Li Reviewed-by: Alexander Stein Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi index 29105773add7..e0b9ea6dd510 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi +++ b/arch/arm/boot/dts/nxp/ls/ls1021a.dtsi @@ -154,7 +154,7 @@ qspi: spi@1550000 { status = "disabled"; }; - esdhc: esdhc@1560000 { + esdhc: mmc@1560000 { compatible = "fsl,ls1021a-esdhc", "fsl,esdhc"; reg = <0x0 0x1560000 0x0 0x10000>; interrupts = ; From 01ed2910b220615dd7f291946edf5d0709796ce2 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 22 Aug 2025 10:50:01 -0400 Subject: [PATCH 627/931] ARM: dts: ls1021a-tsn: Remove redundant #address-cells for ethernet-switch@1 Remove redundant #address-cells and #size-cells for ethernet-switch@1 because children node have not address. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dtb: ethernet-switch@1 (nxp,sja1105t): Unevaluated properties are not allowed ('#address-cells', '#size-cells' were unexpected) from schema $id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml# Signed-off-by: Frank Li Reviewed-by: Alexander Stein Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts index 1ea32fff4120..da76566f3510 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-tsn.dts @@ -40,8 +40,6 @@ &dspi0 { /* ADG704BRMZ 1:4 SPI mux/demux */ sja1105: ethernet-switch@1 { reg = <0x1>; - #address-cells = <1>; - #size-cells = <0>; compatible = "nxp,sja1105t"; /* 12 MHz */ spi-max-frequency = <12000000>; From 5e38d940a36c419622286251dd0efa96956d0ed5 Mon Sep 17 00:00:00 2001 From: Ray Chang Date: Fri, 22 Aug 2025 15:33:08 +0800 Subject: [PATCH 628/931] dt-bindings: arm: fsl: Add EDM-G-IMX8M-PLUS SOM and WB-EDM-G carrier board Add support for TechNexion EDM-G-IMX8M-PLUS SOM and WB-EDM-G carrier board. Signed-off-by: Ray Chang Signed-off-by: Richard Hu Acked-by: Rob Herring (Arm) Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index ebafa6ecbcb6..8e48a34af890 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1201,6 +1201,13 @@ properties: - const: polyhex,imx8mp-debix-som-a # Polyhex Debix SOM A - const: fsl,imx8mp + - description: TechNexion EDM-G-IMX8M-PLUS SoM based boards + items: + - enum: + - technexion,edm-g-imx8mp-wb # TechNexion EDM-G-IMX8MP SOM on WB-EDM-G + - const: technexion,edm-g-imx8mp # TechNexion EDM-G-IMX8MP SOM + - const: fsl,imx8mp + - description: Toradex Boards with SMARC iMX8M Plus Modules items: - const: toradex,smarc-imx8mp-dev # Toradex SMARC iMX8M Plus on Toradex SMARC Development Board From 1419c28eb246e181e7b917b1b0b65282201dfc34 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 22 Aug 2025 09:02:41 -0300 Subject: [PATCH 629/931] dt-bindings: soc: fsl,imx-iomuxc-gpr: Document i.MX53 imx53.dtsi has the following compatible entry: compatible = "fsl,imx53-iomuxc-gpr", "syscon"; Document the "fsl,imx53-iomuxc-gpr" entry to fix the following dt-schema warning: failed to match any schema with compatible: ['fsl,imx53-iomuxc-gpr', 'syscon'] Signed-off-by: Fabio Estevam Acked-by: Conor Dooley Signed-off-by: Shawn Guo --- .../devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml index 8451cb4dd87c..b77ce8c6a935 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml @@ -38,6 +38,7 @@ properties: - const: simple-mfd - items: - enum: + - fsl,imx53-iomuxc-gpr - fsl,imx8mm-iomuxc-gpr - fsl,imx8mn-iomuxc-gpr - fsl,imx8mp-iomuxc-gpr From 8523931a20b780af752327d248c83ec8896f306b Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 22 Aug 2025 15:49:54 +0200 Subject: [PATCH 630/931] ARM: dts: mba6ul: Add MicIn routing MicIn is connected to IN3_L. Add routing including the Mic Bias. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi index 67a3d484bc9f..65fde4f52587 100644 --- a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi @@ -146,6 +146,13 @@ sound { ssi-controller = <&sai1>; audio-codec = <&tlv320aic32x4>; audio-asrc = <&asrc>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; }; }; From a22a9e1271fb505f2c85d526d05aad5dde2f50e1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= Date: Mon, 25 Aug 2025 14:52:09 +0200 Subject: [PATCH 631/931] ARM: dts: imx6ul-tx6ul: Switch away from deprecated `phy-reset-gpios` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Ethernet PHY's reset GPIO should be specified in the node of the PHY itself, instead of the MAC (`fec`). The latter is deprecated, and was an i.MX-specific extension, incompatible with the new reset controller subsystem. Co-developed-by: Csaba Buday Signed-off-by: Csaba Buday Signed-off-by: Bence Csókás Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi index f053358bc931..5c7e9556b5ce 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi @@ -246,7 +246,6 @@ &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>; phy-mode = "rmii"; - phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; phy-supply = <®_3v3_etn>; phy-handle = <&etnphy0>; status = "okay"; @@ -262,6 +261,11 @@ etnphy0: ethernet-phy@0 { pinctrl-0 = <&pinctrl_etnphy0_int>; interrupt-parent = <&gpio5>; interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <100>; + reset-deassert-us = <25000>; + /* Energy detect sometimes causes link failures */ + smsc,disable-energy-detect; status = "okay"; }; @@ -272,6 +276,9 @@ etnphy1: ethernet-phy@2 { pinctrl-0 = <&pinctrl_etnphy1_int>; interrupt-parent = <&gpio4>; interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + reset-assert-us = <100>; + reset-deassert-us = <25000>; status = "okay"; }; }; @@ -281,7 +288,6 @@ &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>; phy-mode = "rmii"; - phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; phy-supply = <®_3v3_etn>; phy-handle = <&etnphy1>; status = "disabled"; From 8647d8a7709d7619cb26467957b846989c4459d0 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 16 Jun 2025 04:11:15 +0300 Subject: [PATCH 632/931] arm64: dts: imx8mp: Add pclk clock and second power domain for the ISP The ISP HDR stitching registers are clocked by the pixel clock, which is gated by the MIPI_CSI2 power domain. Attempting to access those registers with the clock off locks up the system. Fix this by adding the pclk clock and the MIPI_CSI2 secondary power domain. Signed-off-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index bb24dba7338e..5d10de3950c3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1701,9 +1701,12 @@ isp_0: isp@32e10000 { interrupts = ; clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, - <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; - clock-names = "isp", "aclk", "hclk"; - power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>; + clock-names = "isp", "aclk", "hclk", "pclk"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>, + <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; + power-domain-names = "isp", "csi2"; fsl,blk-ctrl = <&media_blk_ctrl 0>; status = "disabled"; @@ -1723,9 +1726,12 @@ isp_1: isp@32e20000 { interrupts = ; clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, - <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; - clock-names = "isp", "aclk", "hclk"; - power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>; + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>; + clock-names = "isp", "aclk", "hclk", "pclk"; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>, + <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; + power-domain-names = "isp", "csi2"; fsl,blk-ctrl = <&media_blk_ctrl 1>; status = "disabled"; From bbe4b2f7d65336073c3ba980a2e4ea971ef7da6c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 10 Jul 2025 15:13:55 -0400 Subject: [PATCH 633/931] arm64: dts: imx95: Add msi-map for pci-ep device Add msi-map for pci-ep device. Acked-by: Manivannan Sadhasivam Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 4e5a2d40c718..ec61d27352e3 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1886,6 +1886,7 @@ pcie0_ep: pcie-ep@4c300000 { assigned-clock-rates = <3600000000>, <100000000>, <10000000>; assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; + msi-map = <0x0 &its 0x98 0x1>; power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; status = "disabled"; }; From c83b3e212da69b49e1e4a8f9f45162990b941b9e Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Thu, 21 Aug 2025 18:01:37 +0200 Subject: [PATCH 634/931] arm64: dts: imx8mp: add interconnect for lcdif-hdmi Add the missing interconnect for the lcdif-hdmi. Signed-off-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 5d10de3950c3..0c4bc3ab0555 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -2051,6 +2051,10 @@ hdmi_blk_ctrl: blk-ctrl@32fc0000 { "pai", "pvi", "trng", "hdmi-tx", "hdmi-tx-phy", "hdcp", "hrv"; + interconnects = <&noc IMX8MP_ICM_HRV &noc IMX8MP_ICN_HDMI>, + <&noc IMX8MP_ICM_LCDIF_HDMI &noc IMX8MP_ICN_HDMI>, + <&noc IMX8MP_ICM_HDCP &noc IMX8MP_ICN_HDMI>; + interconnect-names = "hrv", "lcdif-hdmi", "hdcp"; #power-domain-cells = <1>; }; From 95e882c021c8b45c9e7287aceb5637953e1414f8 Mon Sep 17 00:00:00 2001 From: Richard Hu Date: Fri, 22 Aug 2025 15:33:09 +0800 Subject: [PATCH 635/931] arm64: dts: imx8mp: Add TechNexion EDM-G-IMX8M-PLUS SOM on WB-EDM-G carrier board Add support for TechNexion EDM-G-IMX8M-PLUS SOM and WB-EDM-G carrier board. Key interfaces include: - Gigabit Ethernet - USB 3.0 - I2S, UART, SPI, I2C, PWM, GPIO Signed-off-by: Richard Hu Signed-off-by: Ray Chang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mp-edm-g-wb.dts | 359 ++++++++ .../boot/dts/freescale/imx8mp-edm-g.dtsi | 786 ++++++++++++++++++ 3 files changed, 1146 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 2be724579632..c376be23d9ff 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -203,6 +203,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-drc02.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-iota2-lumpy.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts b/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts new file mode 100644 index 000000000000..138f21e257aa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 TechNexion Ltd. + * + * Author: Ray Chang + */ + +/dts-v1/; + +#include +#include "imx8mp-edm-g.dtsi" + +/ { + compatible = "technexion,edm-g-imx8mp-wb", "technexion,edm-g-imx8mp", "fsl,imx8mp"; + model = "TechNexion EDM-G-IMX8MP SOM on WB-EDM-G"; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hs_ep: endpoint { + remote-endpoint = <&usb3_hs_ep>; + }; + }; + + port@1 { + reg = <1>; + + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "HDMI OUT"; + type = "a"; + + port { + hdmi_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led { + default-state = "on"; + gpios = <&expander2 1 GPIO_ACTIVE_HIGH>; + label = "gpio-led"; + }; + }; + + pcie0_refclk: clock-pcie-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_pwr_3v3: regulator-pwr-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "pwr-3v3"; + }; + + reg_pwr_5v: regulator-pwr-5v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "pwr-5v"; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + model = "audio-hdmi"; + }; + + sound-wm8960 { + compatible = "fsl,imx-audio-wm8960"; + audio-asrc = <&easrc>; + audio-codec = <&wm8960>; + audio-cpu = <&sai3>; + audio-routing = "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + model = "wm8960-audio"; + }; +}; + +&aud2htx { + status = "okay"; +}; + +&easrc { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&flexcan1 { + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", "", "", "DSI_RST", "", + "", "", "", "", "", "PCIE_CLKREQ_N", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + pinctrl-0 = <&pinctrl_gpio1>; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "GPIO_P249", "GPIO_P251", + "", "GPIO_P255", "", "", "", "", "", "", + "DSI_BL_EN", "DSI_VDDEN", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; + pinctrl-0 = <&pinctrl_gpio4>; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-0 = <&pinctrl_hdmi>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + wm8960: audio-codec@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + AVDD-supply = <®_pwr_3v3>; + DBVDD-supply = <®_pwr_3v3>; + DCVDD-supply = <®_pwr_3v3>; + SPKVDD1-supply = <®_pwr_5v>; + SPKVDD2-supply = <®_pwr_5v>; + wlf,gpio-cfg = <1 2>; + wlf,hp-cfg = <2 2 3>; + wlf,shared-lrclk; + }; + + expander1: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "EXPOSURE_TRIG_IN1", "FLASH_OUT1", + "INFO_TRIG_IN1", "CAM_SHUTTER1", "XVS1", + "PWR1_TIME0", "PWR1_TIME1", "PWR1_TIME2", + "EXPOSURE_TRIG_IN2", "FLASH_OUT2", + "INFO_TRIG_IN2", "CAM_SHUTTER2", "XVS2", + "PWR2_TIME0", "PWR2_TIME1", "PWR2_TIME2"; + }; + + expander2: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio4>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "M2_DISABLE_N", "LED_EN", "", "", + "", "", "", "USB_OTG_OC", + "EXT_GPIO8", "EXT_GPIO9", "", "", + "", "CSI1_PDB", "CSI2_PDB", "PD_FAULT"; + pinctrl-0 = <&pinctrl_expander2_irq>; + pinctrl-names = "default"; + }; + + usb_typec: usb-typec@67 { + compatible = "ti,hd3ss3220"; + reg = <0x67>; + interrupt-parent = <&gpio4>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_hd3ss3220_irq>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + + port@1 { + reg = <1>; + + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; + }; + }; + }; + }; +}; + +&i2c_0 { + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; +}; + +&lcdif3 { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&pcie_phy { + clocks = <&pcie0_refclk>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_0 { + /* dual role is implemented but not a full featured OTG */ + adp-disable; + dr_mode = "otg"; + hnp-disable; + role-switch-default-mode = "peripheral"; + srp-disable; + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + + port@1 { + reg = <1>; + + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; + }; + }; +}; + +&usb_dwc3_1 { + dr_mode = "host"; +}; + +&iomuxc { + pinctrl_expander2_irq: expander2-irqgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x140 /* GPIO_P247 */ + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x16 /* DSI_RST */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x16 /* GPIO_P249 */ + MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x16 /* GPIO_P251 */ + MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x16 /* GPIO_P255 */ + MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x16 /* DSI_BL_EN */ + MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x16 /* DSI_VDDEN */ + >; + }; + + pinctrl_hd3ss3220_irq: hd3ss3220-irqgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x41 /* GPIO_P253 */ + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi new file mode 100644 index 000000000000..3f1e0837f349 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi @@ -0,0 +1,786 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2024 TechNexion Ltd. + * + * Author: Ray Chang + */ + +#include "imx8mp.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; + + i2c_0: i2c { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c_brd_conf>; + pinctrl-names = "default"; + scl-gpios = <&gpio4 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + eeprom: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + }; + + memory@40000000 { + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0xc0000000>; + device_type = "memory"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + startup-delay-us = <100>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + rfkill { + compatible = "rfkill-gpio"; + name = "rfkill"; + pinctrl-0 = <&pinctrl_bt_ctrl>; + pinctrl-names = "default"; + radio-type = "bluetooth"; + shutdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; + + wl_reg_on: regulator-wl-reg-on { + compatible = "regulator-fixed"; + off-on-delay-us = <20000>; + pinctrl-0 = <&pinctrl_wifi_ctrl>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "WL_REG_ON"; + startup-delay-us = <100>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <®_arm>; +}; + +&A53_1 { + cpu-supply = <®_arm>; +}; + +&A53_2 { + cpu-supply = <®_arm>; +}; + +&A53_3 { + cpu-supply = <®_arm>; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + num-cs = <1>; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + pinctrl-names = "default"; +}; + +&eqos { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-names = "default"; + snps,force_thresh_dma_mode; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + reset-assert-us = <35000>; + reset-deassert-us = <75000>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0>; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <1>; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <2>; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <3>; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <4>; + snps,priority = <0xf0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; +}; + +&flexcan1 { + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-names = "default"; +}; + +&flexcan2 { + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-names = "default"; + status = "okay"; + + pmic: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + + regulators { + BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <720000>; + regulator-name = "BUCK1"; + regulator-ramp-delay = <3125>; + }; + + reg_arm: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1025000>; + regulator-min-microvolt = <720000>; + regulator-name = "BUCK2"; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3600000>; + regulator-min-microvolt = <3000000>; + regulator-name = "BUCK4"; + }; + + reg_buck5: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1650000>; + regulator-name = "BUCK5"; + }; + + BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1155000>; + regulator-min-microvolt = <1045000>; + regulator-name = "BUCK6"; + }; + + LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1650000>; + regulator-name = "LDO1"; + }; + + LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1890000>; + regulator-min-microvolt = <1710000>; + regulator-name = "LDO3"; + }; + + LDO5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "LDO5"; + }; + }; + }; +}; + +&i2c2 { + /* I2C_B on EDMG */ + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-names = "default"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-names = "default"; +}; + +&i2c4 { + /* I2C_A on EDMG */ + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-names = "default"; +}; + +&i2c5 { + /* I2C_C on EDMG */ + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-names = "default"; +}; + +&pcie { + pinctrl-0 = <&pinctrl_pcie>; + pinctrl-names = "default"; + reset-gpio = <&gpio1 1 GPIO_ACTIVE_LOW>; +}; + +&pwm1 { + pinctrl-0 = <&pinctrl_pwm1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm2 { + pinctrl-0 = <&pinctrl_pwm2>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm3 { + pinctrl-0 = <&pinctrl_pwm3>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm4 { + pinctrl-0 = <&pinctrl_pwm4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sai2 { + /* AUD_B on EDMG */ + assigned-clocks = <&clk IMX8MP_CLK_SAI2>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + pinctrl-0 = <&pinctrl_sai2>; + pinctrl-names = "default"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai3 { + /* AUD_A on EDMG */ + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-names = "default"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&uart1 { + /* BT */ + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + /* UART_A on EDMG, console */ + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart3 { + /* UART_C on EDMG */ + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-0 = <&pinctrl_uart3>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + /* UART_B on EDMG */ + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-0 = <&pinctrl_uart4>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc1 { + /* WIFI SDIO */ + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + keep-power-in-suspend; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <&wl_reg_on>; + status = "okay"; +}; + +&usdhc2 { + /* SD card on baseboard */ + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + /* eMMC on SOM */ + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + status = "okay"; +}; + +&wdog1 { + pinctrl-0 = <&pinctrl_wdog>; + pinctrl-names = "default"; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; + pinctrl-names = "default"; + + pinctrl_bt_ctrl: bt-ctrlgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x41 /* BT_REG_ON */ + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x41 /* BT_WAKE_HOST */ + >; + }; + + pinctrl_ecspi1_cs: ecspi1csgrp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40000 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x23 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x19 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001a3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001a3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001a3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001a3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001a3 + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001a3 + >; + }; + + pinctrl_i2c_brd_conf: i2cbrdconfgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c3 /* BRD_CONF_SCL, bitbang */ + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c3 /* BRD_CONF_SDA, bitbang */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x41 /* PCIE CLKREQ */ + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x41 /* PCIE WAKE */ + MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x41 /* PCIE RST */ + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x140 + MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140 + MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x140 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wifi_ctrl: wifi-ctrlgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x41 /* WL_REG_ON */ + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x41 /* WL_WAKE_HOST */ + >; + }; +}; From cc5717bb35c1c1eb5e8f2db37f938c329b8e530a Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Fri, 22 Aug 2025 11:20:06 +0200 Subject: [PATCH 636/931] arm64: dts: freescale: imx8mp-moduline-display-106: Use phys to replace xceiver-supply Fix the can tranceivers to actually use the new phy description instead of the regulator tweak. Signed-off-by: Maud Spierings Signed-off-by: Shawn Guo --- .../imx8mp-tx8p-ml81-moduline-display-106.dts | 46 +++++++++---------- 1 file changed, 22 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts index afd886dd590f..88ad422c2760 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts @@ -36,6 +36,24 @@ external-sensor-supply { vout-supply = <®_5v0_sensor>; }; + flexcan1_phy: can-phy0 { + compatible = "ti,tcan1051", "ti,tcan1042"; + #phy-cells = <0>; + pinctrl-0 = <&pinctrl_flexcan1_stby>; + pinctrl-names = "default"; + max-bitrate = <5000000>; + standby-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + }; + + flexcan2_phy: can-phy1 { + compatible = "ti,tcan1051", "ti,tcan1042"; + #phy-cells = <0>; + pinctrl-0 = <&pinctrl_flexcan2_stby>; + pinctrl-names = "default"; + max-bitrate = <5000000>; + standby-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + }; + reg_1v8_per: regulator-1v8-per { compatible = "regulator-fixed"; pinctrl-0 = <&pinctrl_reg_1v8>; @@ -85,26 +103,6 @@ reg_6v4: regulator-6v4 { regulator-name = "6v4"; }; - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - pinctrl-0 = <&pinctrl_flexcan1_reg>; - pinctrl-names = "default"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "can1-stby"; - gpio = <&gpio4 3 GPIO_ACTIVE_LOW>; - }; - - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - pinctrl-0 = <&pinctrl_flexcan2_reg>; - pinctrl-names = "default"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "can2-stby"; - gpio = <&gpio5 9 GPIO_ACTIVE_LOW>; - }; - sound { compatible = "simple-audio-card"; simple-audio-card,bitclock-master = <&cpudai>; @@ -180,16 +178,16 @@ adc@2 { }; &flexcan1 { + phys = <&flexcan1_phy>; pinctrl-0 = <&pinctrl_flexcan1>; pinctrl-names = "default"; - xceiver-supply = <®_can1_stby>; status = "okay"; }; &flexcan2 { + phys = <&flexcan2_phy>; pinctrl-0 = <&pinctrl_flexcan2>; pinctrl-names = "default"; - xceiver-supply = <®_can2_stby>; status = "okay"; }; @@ -278,7 +276,7 @@ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX >; }; - pinctrl_flexcan1_reg: flexcan1reggrp { + pinctrl_flexcan1_stby: flexcan1stbygrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) @@ -294,7 +292,7 @@ MX8MP_IOMUXC_UART3_RXD__CAN2_TX >; }; - pinctrl_flexcan2_reg: flexcan2reggrp { + pinctrl_flexcan2_stby: flexcan2stbygrp { fsl,pins = < MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) From da3c9dc9b439ff539a30752811610104512d20ea Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:31:10 +0200 Subject: [PATCH 637/931] arm64: dts: fsl-ls1012a: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: fsl-ls1012a.dtsi:548.4-551.32: Warning (interrupt_map): /soc/pcie@3400000:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@1400000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index dd479889658d..fc3e138077b8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -87,6 +87,7 @@ pmu { gic: interrupt-controller@1400000 { compatible = "arm,gic-400"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x1401000 0 0x1000>, /* GICD */ From 43156dff1596940c381c369ea51a45bbfaba430e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:31:11 +0200 Subject: [PATCH 638/931] arm64: dts: fsl-ls1043a: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: fsl-ls1043a.dtsi:330.5-342.26: Warning (interrupt_map): /soc/scfg@1570000/interrupt-controller@1ac:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@1400000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 26bea88cb967..73315c517039 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -289,6 +289,7 @@ pmu { gic: interrupt-controller@1400000 { compatible = "arm,gic-400"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x1401000 0 0x1000>, /* GICD */ From 46961265bdfb9c237cb03ea6b640b8e7588a982a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:31:12 +0200 Subject: [PATCH 639/931] arm64: dts: fsl-ls1046a: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: fsl-ls1046a.dtsi:334.5-346.26: Warning (interrupt_map): /soc/scfg@1570000/interrupt-controller@1ac:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@1400000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 4a22fde38bea..770d91ef0310 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -260,6 +260,7 @@ pmu { gic: interrupt-controller@1400000 { compatible = "arm,gic-400"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x1410000 0 0x10000>, /* GICD */ From e4ea1f9d4c9414b532ab541df37cdeac14ee5568 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:31:13 +0200 Subject: [PATCH 640/931] arm64: dts: imx8dxl: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: imx8dxl-ss-hsio.dtsi:45.3-48.27: Warning (interrupt_map): /bus@5f000000/pcie@5f010000:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@51a00000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index a71d8b32c192..8d60827822ed 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -92,6 +92,7 @@ gic: interrupt-controller@51a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; interrupts = ; From 78d9275da9e26f3f1b3482dbe6069b5bbcd717c8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:31:14 +0200 Subject: [PATCH 641/931] arm64: dts: imx8mm: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: imx8mm.dtsi:1355.4-1358.29: Warning (interrupt_map): /soc@0/pcie@33800000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@38800000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index ded89b046970..fc3cd639310e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1467,6 +1467,7 @@ gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; interrupts = ; From faf183a02ed6beea3d0bc5162740294497aa5e80 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:31:15 +0200 Subject: [PATCH 642/931] arm64: dts: imx8mp: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: imx8mp.dtsi:2184.4-2187.29: Warning (interrupt_map): /soc@0/pcie@33800000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@38800000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 0c4bc3ab0555..87a34e8b7266 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -2327,6 +2327,7 @@ gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, <0x38880000 0xc0000>; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; interrupts = ; From 32b387ceffa7ca9c14aa6064a8b3788d17b6ae17 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:31:16 +0200 Subject: [PATCH 643/931] arm64: dts: imx8mq: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: imx8mq.dtsi:1746.4-1749.43: Warning (interrupt_map): /soc@0/pcie@33800000:interrupt-map: Missing property '#address-cells' in node /soc@0/interrupt-controller@38800000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index c9040d1131a8..607962f807be 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1890,6 +1890,7 @@ gic: interrupt-controller@38800000 { <0x31000000 0x2000>, /* GICC */ <0x31010000 0x2000>, /* GICV */ <0x31020000 0x2000>; /* GICH */ + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; interrupts = ; From 9429445d48d59af5d3c56b5427ef1a85b4f9d291 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:31:17 +0200 Subject: [PATCH 644/931] arm64: dts: imx8qm: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: imx8qm-ss-hsio.dtsi:83.3-86.28: Warning (interrupt_map): /bus@5f000000/pcie@5f010000:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@51a00000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 827e1365b5da..5206ca82eaf6 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -245,6 +245,7 @@ gic: interrupt-controller@51a00000 { <0x0 0x52000000 0 0x2000>, /* GICC */ <0x0 0x52010000 0 0x1000>, /* GICH */ <0x0 0x52020000 0 0x20000>; /* GICV */ + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; interrupts = ; From 712a83e213ae09b6d417be81c097908c54f636cc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:31:18 +0200 Subject: [PATCH 645/931] arm64: dts: imx8qxp: Add default GIC address cells Add missing address-cells 0 to GIC interrupt node to silence W=1 warning: imx8-ss-hsio.dtsi:71.3-74.28: Warning (interrupt_map): /bus@5f000000/pcie@5f010000:interrupt-map: Missing property '#address-cells' in node /interrupt-controller@51a00000, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 9e46e16a8dc0..95edab058276 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -159,6 +159,7 @@ gic: interrupt-controller@51a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; interrupts = ; From 7a35e48fe0ec34f88a28490bb5e4d9308dec2adf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:31:19 +0200 Subject: [PATCH 646/931] arm64: dts: imx8: Use GIC_SPI for interrupt-map for readability Decoding interrupt-map is tricky, because it consists of five components. Use known GIC_SPI define in final interrupt specifier component makes easier to read. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi | 8 ++++---- .../boot/dts/freescale/imx8dxl-ss-hsio.dtsi | 8 ++++---- .../arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi | 16 ++++++++-------- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi index 9b8b1380c4c2..469de8b536b5 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi @@ -68,10 +68,10 @@ pcieb: pcie@5f010000 { clock-names = "dbi", "mstr", "slv"; bus-range = <0x00 0xff>; device_type = "pci"; - interrupt-map = <0 0 0 1 &gic 0 105 4>, - <0 0 0 2 &gic 0 106 4>, - <0 0 0 3 &gic 0 107 4>, - <0 0 0 4 &gic 0 108 4>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0 0 0 0x7>; num-lanes = <1>; num-viewport = <4>; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi index bbc6abb0fdf2..ec466e4d7df5 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi @@ -42,10 +42,10 @@ pcie0: pcie@5f010000 { #interrupt-cells = <1>; interrupts = ; interrupt-names = "msi"; - interrupt-map = <0 0 0 1 &gic 0 47 4>, - <0 0 0 2 &gic 0 48 4>, - <0 0 0 3 &gic 0 49 4>, - <0 0 0 4 &gic 0 50 4>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0 0 0 0x7>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi index 50c0f6b0f0bd..bd6e0aa27efe 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -30,10 +30,10 @@ pcie0: pciea: pcie@5f000000 { clock-names = "dbi", "mstr", "slv"; bus-range = <0x00 0xff>; device_type = "pci"; - interrupt-map = <0 0 0 1 &gic 0 73 4>, - <0 0 0 2 &gic 0 74 4>, - <0 0 0 3 &gic 0 75 4>, - <0 0 0 4 &gic 0 76 4>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0 0 0 0x7>; num-lanes = <1>; num-viewport = <4>; @@ -80,10 +80,10 @@ pcie1: pcieb: pcie@5f010000 { clock-names = "dbi", "mstr", "slv"; bus-range = <0x00 0xff>; device_type = "pci"; - interrupt-map = <0 0 0 1 &gic 0 105 4>, - <0 0 0 2 &gic 0 106 4>, - <0 0 0 3 &gic 0 107 4>, - <0 0 0 4 &gic 0 108 4>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0 0 0 0x7>; num-lanes = <1>; num-viewport = <4>; From a009c0c66ecb451200639c3ec13d806ab03795ed Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sat, 23 Aug 2025 17:28:22 +0300 Subject: [PATCH 647/931] arm64: dts: add description for solidrun imx8mp som and cubox-m Add description for the SolidRun i.MX8M Plus based System on Module, and the CuBox-M. The SoM features: - 2x 1Gbps Ethernet with PHY - eMMC - 1/2/3/8GB DDR - MIPI-CSI Camera Connector (not described without specific camera) The CuBox-M is a complete product with enclosure featuring: - 1x 1Gbps RJ45 Ethernet Port - 2x USB-3.0 Type A - HDMI connector - microSD connector - microUSB connector for console (using fdtdi chip) - IR receiver - RTC with backup battery Signed-off-by: Josua Mayer Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mp-cubox-m.dts | 223 +++++++ .../boot/dts/freescale/imx8mp-sr-som.dtsi | 591 ++++++++++++++++++ 3 files changed, 815 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index c376be23d9ff..5fd7e4b9529d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -196,6 +196,7 @@ imx8mp-aristainetos3-helios-lvds-dtbs += imx8mp-aristainetos3-helios.dtb imx8mp- dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios-lvds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-proton2s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-cubox-m.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts new file mode 100644 index 000000000000..8290f187b79f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + */ + +/dts-v1/; + +#include + +#include "imx8mp-sr-som.dtsi" + +/ { + model = "SolidRun i.MX8MP CuBox-M"; + compatible = "solidrun,imx8mp-cubox-m", + "solidrun,imx8mp-sr-som", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + /delete-property/ ethernet1; + rtc0 = &carrier_rtc; + rtc1 = &snvs_rtc; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins>; + linux,autosuspend-period = <125>; + wakeup-source; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + status { + label = "status"; + color = ; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_HEARTBEAT; + }; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; + + vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vbus_pins>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vmmc: regulator-mmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&vmmc_pins>; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + startup-delay-us = <250>; + }; +}; + +&aud2htx { + status = "okay"; +}; + +&fec { + /* this board does not use second phy / ethernet on SoM */ + status = "disabled"; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&i2c3 { + carrier_rtc: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + + hdmi_pins: pinctrl-hdmi-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154 + >; + }; + + ir_pins: pinctrl-ir-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x4f + >; + }; + + led_pins: pinctrl-led-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x0 + >; + }; + + usdhc2_pins: pinctrl-usdhc2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + vbus_pins: pinctrl-vbus-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x100 + >; + }; + + vmmc_pins: pinctrl-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0 + >; + }; +}; + +&lcdif3 { + status = "okay"; +}; + +&usb3_phy0 { + fsl,phy-tx-preemp-amp-tune-microamp = <1200>; + vbus-supply = <&vbus>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_phy1 { + fsl,phy-tx-preemp-amp-tune-microamp = <1200>; + vbus-supply = <&vbus>; + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&usdhc2_pins>; + pinctrl-1 = <&usdhc2_100mhz_pins>; + pinctrl-2 = <&usdhc2_200mhz_pins>; + vmmc-supply = <&vmmc>; + bus-width = <4>; + cap-power-off-card; + full-pwr-cycle; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi new file mode 100644 index 000000000000..4e6629f940bf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi @@ -0,0 +1,591 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + */ + +#include "imx8mp.dtsi" + +/ { + model = "SolidRun i.MX8MP SoM"; + compatible = "solidrun,imx8mp-sr-som", "fsl,imx8mp"; + + chosen { + bootargs = "earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0xc0000000>; + }; + + usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + }; + + v_1_8: regulator-1-8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + v_3_3: regulator-3-3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +/* + * Reserve all physical memory from within the first 1GB of DDR address + * space to avoid panic on low memory systems. + */ +&dsp_reserved { + reg = <0 0x6f000000 0 0x1000000>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&eqos_pins>, <&phy0_pins>; + phy-mode = "rgmii-id"; + phy = <&phy0>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&fec_pins>, <&phy1_pins>; + phy-mode = "rgmii-id"; + phy = <&phy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_gpio_pins>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-0 = <&pmic_pins>; + pinctrl-names = "default"; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + nxp,i2c-lt-enable; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + som_eeprom: eeprom@50{ + compatible = "st,24c01", "atmel,24c01"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&i2c2_gpio_pins>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c3_pins>; + pinctrl-1 = <&i2c3_gpio_pins>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { + /* routed to basler camera connector */ + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&i2c4_gpio_pins>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&iomuxc { + eqos_pins: pinctrl-eqos-grp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + >; + }; + + fec_pins: pinctrl-fec-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + >; + }; + + i2c1_pins: pinctrl-i2c1-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + i2c1_gpio_pins: pinctrl-i2c1-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c3 + >; + }; + + i2c2_pins: pinctrl-i2c2-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + i2c2_gpio_pins: pinctrl-i2c2-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3 + >; + }; + + i2c3_pins: pinctrl-i2c3-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + i2c3_gpio_pins: pinctrl-i2c3-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3 + >; + }; + + i2c4_pins: pinctrl-i2c4-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + i2c4_gpio_pins: pinctrl-i2c4-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3 + >; + }; + + phy0_pins: pinctrl-phy0-grp { + fsl,pins = < + /* RESET_N: weak i/o, open drain, external 1k pull-up */ + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x20 + /* INT_N: weak i/o, open drain, internal pull-up */ + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x160 + >; + }; + + phy1_pins: pinctrl-phy-1-grp { + fsl,pins = < + /* RESET_N: weak i/o, open drain, external 1k pull-up */ + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x20 + /* INT_N: weak i/o, open drain, internal pull-up */ + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x160 + >; + }; + + pmic_pins: pinctrl-pmic-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + uart1_pins: pinctrl-uart1-grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + /* BT_REG_ON */ + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0 + /* BT_WAKE_DEV */ + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0 + /* BT_WAKE_HOST */ + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x100 + >; + }; + + uart2_pins: pinctrl-uart2-grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + usdhc1_pins: pinctrl-usdhc1-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + /* WL_REG_ON */ + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0 + /* WL_WAKE_HOST */ + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x100 + >; + }; + + usdhc1_100mhz_pins: pinctrl-usdhc1g-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + usdhc1_200mhz_pins: pinctrl-usdhc1-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + usdhc3_pins: pinctrl-usdhc3-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + usdhc3_100mhz_pins: pinctrl-usdhc3-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + usdhc3_200mhz_pins: pinctrl-usdhc3-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + wdog1_pins: pinctrl-wdog1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x140 + >; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + uart-has-rtscts; + /* select 80MHz parent clock to support maximum baudrate 4Mbps */ + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + /* Murata 1MW module supports max. 3M baud */ + max-speed = <3000000>; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&usdhc1_pins>; + pinctrl-1 = <&usdhc1_100mhz_pins>; + pinctrl-2 = <&usdhc1_200mhz_pins>; + vmmc-supply = <&v_3_3>; + vqmmc-supply = <&v_1_8>; + bus-width = <4>; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&usdhc3_pins>; + pinctrl-1 = <&usdhc3_100mhz_pins>; + pinctrl-2 = <&usdhc3_200mhz_pins>; + vmmc-supply = <&v_3_3>; + vqmmc-supply = <&v_1_8>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&wdog1_pins>; + status = "okay"; +}; From 1335b32ba1f6a7b145410746caf5b48dcc17c85c Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Mon, 25 Aug 2025 20:00:55 +0200 Subject: [PATCH 648/931] arm64: dts: lx2160a-cex7: add interrupts for rtc and ethernet phy SolidRun LX2160A CEX-7 module has interrupts wired for both the rtc and ethernet phy. Add description for those interrupts to the rtc and phy nodes. Signed-off-by: Josua Mayer Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi index e4b727070814..eec2cd6c6d32 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi @@ -41,6 +41,7 @@ &emdio1 { rgmii_phy1: ethernet-phy@1 { reg = <1>; qca,smarteee-tw-us-1g = <24>; + interrupts-extended = <&gpio2 4 IRQ_TYPE_EDGE_FALLING>; }; }; @@ -156,6 +157,7 @@ &i2c4 { rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; + interrupts-extended = <&gpio2 8 IRQ_TYPE_LEVEL_LOW>; }; }; From 8fc7141826470cf92553f71dc7d0a3e262fad67a Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Mon, 25 Aug 2025 20:00:56 +0200 Subject: [PATCH 649/931] arm64: dts: lx2160a-clearfog-itx: enable pcie nodes for x4 and x8 slots SolidRun Clearfog CX and Honeycomb have LX2160A PEX3 and PEX5 exposed on physical connectors. Vendor U-Boot used to patch status properties such that it went undiscovered these nodes have their status set disabled. Set status okay for pcie3 and pcie5 nodes. Signed-off-by: Josua Mayer Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi index a7dcbecc1f41..af6258b2fe82 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi @@ -96,6 +96,14 @@ &esdhc0 { status = "okay"; }; +&pcie3 { + status = "okay"; +}; + +&pcie5 { + status = "okay"; +}; + &pcs_mdio7 { status = "okay"; }; From 9e7b91e00c190c0fcc7960ba40b134468b5d1bb9 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Mon, 1 Sep 2025 18:36:27 +0800 Subject: [PATCH 650/931] arm64: dts: freescale: move aliases from imx93.dtsi to board dts The aliases is board level property rather than soc property, so move these to each boards. Reviewed-by: Alexander Stein Reviewed-by: Frank Li Signed-off-by: Joy Zou Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-11x11-evk.dts | 19 +++++++++++ .../boot/dts/freescale/imx93-14x14-evk.dts | 15 ++++++++ .../boot/dts/freescale/imx93-9x9-qsb.dts | 18 ++++++++++ .../dts/freescale/imx93-kontron-bl-osm-s.dts | 21 ++++++++++++ .../dts/freescale/imx93-phyboard-nash.dts | 21 ++++++++++++ .../dts/freescale/imx93-phyboard-segin.dts | 9 +++++ .../freescale/imx93-tqma9352-mba91xxca.dts | 11 ++++++ .../freescale/imx93-tqma9352-mba93xxca.dts | 25 ++++++++++++++ .../freescale/imx93-tqma9352-mba93xxla.dts | 25 ++++++++++++++ .../dts/freescale/imx93-var-som-symphony.dts | 17 ++++++++++ arch/arm64/boot/dts/freescale/imx93.dtsi | 34 ------------------- 11 files changed, 181 insertions(+), 34 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index e24e12f04526..44566e03be65 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -12,6 +12,25 @@ / { model = "NXP i.MX93 11X11 EVK board"; compatible = "fsl,imx93-11x11-evk", "fsl,imx93"; + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + }; + chosen { stdout-path = &lpuart1; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts index 8c5769f90746..f9eebd27d640 100644 --- a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts @@ -12,6 +12,21 @@ / { model = "NXP i.MX93 14X14 EVK board"; compatible = "fsl,imx93-14x14-evk", "fsl,imx93"; + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &bbnsm_rtc; + serial0 = &lpuart1; + }; + chosen { stdout-path = &lpuart1; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts index f6f8d105b737..0852067eab2c 100644 --- a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts +++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts @@ -17,6 +17,24 @@ bt_sco_codec: bt-sco-codec { compatible = "linux,bt-sco"; }; + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + }; + chosen { stdout-path = &lpuart1; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts b/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts index c3d2ddd887fd..4620c070f4d7 100644 --- a/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts @@ -14,6 +14,27 @@ / { aliases { ethernet0 = &fec; ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + spi0 = &lpspi1; + spi1 = &lpspi2; + spi2 = &lpspi3; + spi3 = &lpspi4; + spi4 = &lpspi5; + spi5 = &lpspi6; + spi6 = &lpspi7; + spi7 = &lpspi8; }; leds { diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts index 71a0e9f270af..3f9efa32cddc 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts @@ -19,8 +19,29 @@ / { aliases { ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; rtc0 = &i2c_rtc; rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + spi0 = &lpspi1; + spi1 = &lpspi2; + spi2 = &lpspi3; + spi3 = &lpspi4; + spi4 = &lpspi5; + spi5 = &lpspi6; }; chosen { diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts index 6f1374f5757f..802d96b19e4c 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts @@ -19,8 +19,17 @@ /{ aliases { ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + mmc0 = &usdhc1; + mmc1 = &usdhc2; rtc0 = &i2c_rtc; rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; }; chosen { diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts index 9dbf41cf394b..2673d9dccbf4 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts @@ -27,8 +27,19 @@ aliases { eeprom0 = &eeprom0; ethernet0 = &eqos; ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; rtc0 = &pcf85063; rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; }; backlight: backlight { diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts index 137b8ed242a2..4760d07ea24b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts @@ -28,8 +28,33 @@ aliases { eeprom0 = &eeprom0; ethernet0 = &eqos; ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; rtc0 = &pcf85063; rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + spi0 = &lpspi1; + spi1 = &lpspi2; + spi2 = &lpspi3; + spi3 = &lpspi4; + spi4 = &lpspi5; + spi5 = &lpspi6; }; backlight_lvds: backlight { diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts index 219f49a4f87f..8a88c98ac05a 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts @@ -28,8 +28,33 @@ aliases { eeprom0 = &eeprom0; ethernet0 = &eqos; ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; rtc0 = &pcf85063; rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + spi0 = &lpspi1; + spi1 = &lpspi2; + spi2 = &lpspi3; + spi3 = &lpspi4; + spi4 = &lpspi5; + spi5 = &lpspi6; }; backlight_lvds: backlight { diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index 576d6982a4a0..c789c1f24bdc 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -17,8 +17,25 @@ /{ aliases { ethernet0 = &eqos; ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; }; + chosen { stdout-path = &lpuart1; }; diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 8a7f1cd76c76..d505f9dfd8ee 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -18,40 +18,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - i2c0 = &lpi2c1; - i2c1 = &lpi2c2; - i2c2 = &lpi2c3; - i2c3 = &lpi2c4; - i2c4 = &lpi2c5; - i2c5 = &lpi2c6; - i2c6 = &lpi2c7; - i2c7 = &lpi2c8; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &lpuart1; - serial1 = &lpuart2; - serial2 = &lpuart3; - serial3 = &lpuart4; - serial4 = &lpuart5; - serial5 = &lpuart6; - serial6 = &lpuart7; - serial7 = &lpuart8; - spi0 = &lpspi1; - spi1 = &lpspi2; - spi2 = &lpspi3; - spi3 = &lpspi4; - spi4 = &lpspi5; - spi5 = &lpspi6; - spi6 = &lpspi7; - spi7 = &lpspi8; - }; - cpus { #address-cells = <1>; #size-cells = <0>; From 80ae41949f641b79c47a1b513a58ba9a3d65ab39 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Mon, 1 Sep 2025 18:36:28 +0800 Subject: [PATCH 651/931] arm64: dts: freescale: rename imx93.dtsi to imx91_93_common.dtsi and modify them The design of i.MX91 platform is very similar to i.MX93 and only some small differences. If the imx91.dtsi include the imx93.dtsi, each add to imx93.dtsi requires an remove in imx91.dtsi for this unique to i.MX93, e.g. NPU. The i.MX91 isn't the i.MX93 subset, if the imx93.dtsi include the imx91.dtsi, the same problem will occur. Common + delta is better than common - delta, so add imx91_93_common.dtsi for i.MX91 and i.MX93, then the imx93.dtsi and imx91.dtsi will include the imx91_93_common.dtsi. Rename imx93.dtsi to imx91_93_common.dtsi and move i.MX93 specific part from imx91_93_common.dtsi to imx93.dtsi. Reviewed-by: Frank Li Signed-off-by: Joy Zou Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx91_93_common.dtsi | 1187 ++++++++++++++ arch/arm64/boot/dts/freescale/imx93.dtsi | 1396 ++--------------- 2 files changed, 1304 insertions(+), 1279 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx91_93_common.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi new file mode 100644 index 000000000000..c48f3ecb91ed --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi @@ -0,0 +1,1187 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022,2025 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "imx93-pinfunc.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <10000>; + exit-latency-us = <7000>; + min-residency-us = <27000>; + wakeup-latency-us = <15000>; + }; + }; + + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + }; + }; + + osc_32k: clock-osc-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "osc_32k"; + }; + + osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48040000 0 0xc0000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + mqs1: mqs1 { + compatible = "fsl,imx93-mqs"; + gpr = <&aonmix_ns_gpr>; + status = "disabled"; + }; + + mqs2: mqs2 { + compatible = "fsl,imx93-mqs"; + gpr = <&wakeupmix_gpr>; + status = "disabled"; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; + clock-names = "main_clk"; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x80000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + edma1: dma-controller@44000000 { + compatible = "fsl,imx93-edma3"; + reg = <0x44000000 0x200000>; + #dma-cells = <3>; + dma-channels = <31>; + interrupts = , // 0: Reserved + , // 1: CANFD1 + , // 2: Reserved + , // 3: GPIO1 CH0 + , // 4: GPIO1 CH1 + , // 5: I3C1 TO Bus + , // 6: I3C1 From Bus + , // 7: LPI2C1 M TX + , // 8: LPI2C1 S TX + , // 9: LPI2C2 M RX + , // 10: LPI2C2 S RX + , // 11: LPSPI1 TX + , // 12: LPSPI1 RX + , // 13: LPSPI2 TX + , // 14: LPSPI2 RX + , // 15: LPTMR1 + , // 16: LPUART1 TX + , // 17: LPUART1 RX + , // 18: LPUART2 TX + , // 19: LPUART2 RX + , // 20: S400 + , // 21: SAI TX + , // 22: SAI RX + , // 23: TPM1 CH0/CH2 + , // 24: TPM1 CH1/CH3 + , // 25: TPM1 Overflow + , // 26: TMP2 CH0/CH2 + , // 27: TMP2 CH1/CH3 + , // 28: TMP2 Overflow + , // 29: PDM + , // 30: ADC1 + ; // err + clocks = <&clk IMX93_CLK_EDMA1_GATE>; + clock-names = "dma"; + }; + + aonmix_ns_gpr: syscon@44210000 { + compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; + reg = <0x44210000 0x1000>; + }; + + system_counter: timer@44290000 { + compatible = "nxp,sysctr-timer"; + reg = <0x44290000 0x30000>; + interrupts = ; + clocks = <&osc_24m>; + clock-names = "per"; + nxp,no-divider; + }; + + wdog1: watchdog@442d0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x442d0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG1_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + wdog2: watchdog@442e0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x442e0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG2_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + tpm1: pwm@44310000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x44310000 0x1000>; + clocks = <&clk IMX93_CLK_TPM1_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm2: pwm@44320000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x44320000 0x10000>; + clocks = <&clk IMX93_CLK_TPM2_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i3c1: i3c@44330000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x44330000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_I3C1_SLOW>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c1: i2c@44340000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44340000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPI2C1_GATE>, + <&clk IMX93_CLK_BUS_AON>; + clock-names = "per", "ipg"; + dmas = <&edma1 7 0 0>, <&edma1 8 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c2: i2c@44350000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44350000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPI2C2_GATE>, + <&clk IMX93_CLK_BUS_AON>; + clock-names = "per", "ipg"; + dmas = <&edma1 9 0 0>, <&edma1 10 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi1: spi@44360000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x44360000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI1_GATE>, + <&clk IMX93_CLK_BUS_AON>; + clock-names = "per", "ipg"; + dmas = <&edma1 11 0 0>, <&edma1 12 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi2: spi@44370000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x44370000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI2_GATE>, + <&clk IMX93_CLK_BUS_AON>; + clock-names = "per", "ipg"; + dmas = <&edma1 13 0 0>, <&edma1 14 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpuart1: serial@44380000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x44380000 0x1000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPUART1_GATE>; + clock-names = "ipg"; + dmas = <&edma1 17 0 FSL_EDMA_RX>, <&edma1 16 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPUART2_GATE>; + clock-names = "ipg"; + dmas = <&edma1 19 0 FSL_EDMA_RX>, <&edma1 18 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + flexcan1: can@443a0000 { + compatible = "fsl,imx93-flexcan"; + reg = <0x443a0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_CAN1_GATE>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX93_CLK_CAN1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>; + status = "disabled"; + }; + + sai1: sai@443b0000 { + compatible = "fsl,imx93-sai"; + reg = <0x443b0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 22 0 FSL_EDMA_RX>, <&edma1 21 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + iomuxc: pinctrl@443c0000 { + compatible = "fsl,imx93-iomuxc"; + reg = <0x443c0000 0x10000>; + status = "okay"; + }; + + bbnsm: bbnsm@44440000 { + compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; + reg = <0x44440000 0x10000>; + + bbnsm_rtc: rtc { + compatible = "nxp,imx93-bbnsm-rtc"; + interrupts = ; + }; + + bbnsm_pwrkey: pwrkey { + compatible = "nxp,imx93-bbnsm-pwrkey"; + interrupts = ; + linux,code = ; + }; + }; + + clk: clock-controller@44450000 { + compatible = "fsl,imx93-ccm"; + reg = <0x44450000 0x10000>; + #clock-cells = <1>; + clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; + clock-names = "osc_32k", "osc_24m", "clk_ext1"; + assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <393216000>; + status = "okay"; + }; + + src: system-controller@44460000 { + compatible = "fsl,imx93-src", "syscon"; + reg = <0x44460000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mediamix: power-domain@44462400 { + compatible = "fsl,imx93-src-slice"; + reg = <0x44462400 0x400>, <0x44465800 0x400>; + #power-domain-cells = <0>; + clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>, + <&clk IMX93_CLK_MEDIA_APB>; + }; + }; + + clock-controller@44480000 { + compatible = "fsl,imx93-anatop"; + reg = <0x44480000 0x2000>; + #clock-cells = <1>; + }; + + micfil: micfil@44520000 { + compatible = "fsl,imx93-micfil"; + reg = <0x44520000 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX93_CLK_PDM_IPG>, + <&clk IMX93_CLK_PDM_GATE>, + <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "ipg_clk", "ipg_clk_app", "pll8k"; + dmas = <&edma1 29 0 5>; + dma-names = "rx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + adc1: adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = , + , + ; + clocks = <&clk IMX93_CLK_ADC1_GATE>; + clock-names = "ipg"; + #io-channel-cells = <1>; + status = "disabled"; + }; + }; + + aips2: bus@42000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + edma2: dma-controller@42000000 { + compatible = "fsl,imx93-edma4"; + reg = <0x42000000 0x210000>; + #dma-cells = <3>; + dma-channels = <64>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&clk IMX93_CLK_EDMA2_GATE>; + clock-names = "dma"; + }; + + wakeupmix_gpr: syscon@42420000 { + compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; + reg = <0x42420000 0x1000>; + }; + + wdog3: watchdog@42490000 { + compatible = "fsl,imx93-wdt"; + reg = <0x42490000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG3_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + wdog4: watchdog@424a0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x424a0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG4_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + wdog5: watchdog@424b0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x424b0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_WDOG5_GATE>; + timeout-sec = <40>; + status = "disabled"; + }; + + tpm3: pwm@424e0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424e0000 0x1000>; + clocks = <&clk IMX93_CLK_TPM3_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm4: pwm@424f0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424f0000 0x10000>; + clocks = <&clk IMX93_CLK_TPM4_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm5: pwm@42500000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42500000 0x10000>; + clocks = <&clk IMX93_CLK_TPM5_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm6: pwm@42510000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42510000 0x10000>; + clocks = <&clk IMX93_CLK_TPM6_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i3c2: i3c@42520000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x42520000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_I3C2_SLOW>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c3: i2c@42530000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42530000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPI2C3_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c4: i2c@42540000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42540000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPI2C4_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi3: spi@42550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42550000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI3_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi4: spi@42560000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42560000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI4_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpuart3: serial@42570000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42570000 0x1000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPUART3_GATE>; + clock-names = "ipg"; + dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart4: serial@42580000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42580000 0x1000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPUART4_GATE>; + clock-names = "ipg"; + dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart5: serial@42590000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42590000 0x1000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPUART5_GATE>; + clock-names = "ipg"; + dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart6: serial@425a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x425a0000 0x1000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPUART6_GATE>; + clock-names = "ipg"; + dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + flexcan2: can@425b0000 { + compatible = "fsl,imx93-flexcan"; + reg = <0x425b0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_CAN2_GATE>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX93_CLK_CAN2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>; + status = "disabled"; + }; + + flexspi1: spi@425e0000 { + compatible = "nxp,imx8mm-fspi"; + reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, + <&clk IMX93_CLK_FLEXSPI1_GATE>; + clock-names = "fspi_en", "fspi"; + assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + status = "disabled"; + }; + + sai2: sai@42650000 { + compatible = "fsl,imx93-sai"; + reg = <0x42650000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sai3: sai@42660000 { + compatible = "fsl,imx93-sai"; + reg = <0x42660000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + xcvr: xcvr@42680000 { + compatible = "fsl,imx93-xcvr"; + reg = <0x42680000 0x800>, + <0x42680800 0x400>, + <0x42680c00 0x080>, + <0x42680e00 0x080>; + reg-names = "ram", "regs", "rxfifo", "txfifo"; + interrupts = , + ; + clocks = <&clk IMX93_CLK_SPDIF_IPG>, + <&clk IMX93_CLK_SPDIF_GATE>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_AUD_XCVR_GATE>; + clock-names = "ipg", "phy", "spba", "pll_ipg"; + dmas = <&edma2 65 0 FSL_EDMA_RX>, <&edma2 66 0 0>; + dma-names = "rx", "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + lpuart7: serial@42690000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x42690000 0x1000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPUART7_GATE>; + clock-names = "ipg"; + dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart8: serial@426a0000 { + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x426a0000 0x1000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPUART8_GATE>; + clock-names = "ipg"; + dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpi2c5: i2c@426b0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPI2C5_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c6: i2c@426c0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426c0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPI2C6_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c7: i2c@426d0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426d0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPI2C7_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c8: i2c@426e0000 { + compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x426e0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPI2C8_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi5: spi@426f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x426f0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI5_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi6: spi@42700000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42700000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI6_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi7: spi@42710000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42710000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI7_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi8: spi@42720000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42720000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_LPSPI8_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x42800000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usdhc1: mmc@42850000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42850000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_USDHC1_GATE>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + + usdhc2: mmc@42860000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42860000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_USDHC2_GATE>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC2>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + + fec: ethernet@42890000 { + compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; + reg = <0x42890000 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX93_CLK_ENET1_GATE>, + <&clk IMX93_CLK_ENET1_GATE>, + <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, + <&clk IMX93_CLK_ENET_REF>, + <&clk IMX93_CLK_ENET_REF_PHY>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <100000000>, <250000000>, <50000000>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; + nvmem-cells = <ð_mac1>; + nvmem-cell-names = "mac-address"; + status = "disabled"; + }; + + eqos: ethernet@428a0000 { + compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x428a0000 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, + <&clk IMX93_CLK_ENET_QOS_GATE>, + <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>, + <&clk IMX93_CLK_ENET_QOS_GATE>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; + assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, + <&clk IMX93_CLK_ENET>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; + intf_mode = <&wakeupmix_gpr 0x28>; + snps,clk-csr = <6>; + nvmem-cells = <ð_mac2>; + nvmem-cell-names = "mac-address"; + status = "disabled"; + }; + + usdhc3: mmc@428b0000 { + compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x428b0000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_WAKEUP_AXI>, + <&clk IMX93_CLK_USDHC3_GATE>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX93_CLK_USDHC3>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + }; + + gpio2: gpio@43810000 { + compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; + reg = <0x43810000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk IMX93_CLK_GPIO2_GATE>, + <&clk IMX93_CLK_GPIO2_GATE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc 0 4 30>; + ngpios = <30>; + }; + + gpio3: gpio@43820000 { + compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; + reg = <0x43820000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk IMX93_CLK_GPIO3_GATE>, + <&clk IMX93_CLK_GPIO3_GATE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, + <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; + ngpios = <32>; + }; + + gpio4: gpio@43830000 { + compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; + reg = <0x43830000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk IMX93_CLK_GPIO4_GATE>, + <&clk IMX93_CLK_GPIO4_GATE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; + ngpios = <30>; + }; + + gpio1: gpio@47400000 { + compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; + reg = <0x47400000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk IMX93_CLK_GPIO1_GATE>, + <&clk IMX93_CLK_GPIO1_GATE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc 0 92 16>; + ngpios = <16>; + }; + + ocotp: efuse@47510000 { + compatible = "fsl,imx93-ocotp", "syscon"; + reg = <0x47510000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + eth_mac1: mac-address@4ec { + reg = <0x4ec 0x6>; + }; + + eth_mac2: mac-address@4f2 { + reg = <0x4f2 0x6>; + }; + + }; + + s4muap: mailbox@47520000 { + compatible = "fsl,imx93-mu-s4"; + reg = <0x47520000 0x10000>; + interrupts = , + ; + interrupt-names = "tx", "rx"; + #mbox-cells = <2>; + }; + + media_blk_ctrl: system-controller@4ac10000 { + compatible = "fsl,imx93-media-blk-ctrl", "syscon"; + reg = <0x4ac10000 0x10000>; + power-domains = <&mediamix>; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_NIC_MEDIA_GATE>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_PXP_GATE>, + <&clk IMX93_CLK_LCDIF_GATE>, + <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MIPI_CSI_GATE>, + <&clk IMX93_CLK_MIPI_DSI_GATE>; + clock-names = "apb", "axi", "nic", "disp", "cam", + "pxp", "lcdif", "isi", "csi", "dsi"; + #power-domain-cells = <1>; + status = "disabled"; + }; + + usbotg1: usb@4c100000 { + compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x4c100000 0x200>; + interrupts = ; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, + <&clk IMX93_CLK_HSIO_32K_GATE>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + assigned-clocks = <&clk IMX93_CLK_HSIO>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <133000000>; + phys = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@4c100200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x4c100200 0x200>; + #index-cells = <1>; + }; + + usbotg2: usb@4c200000 { + compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x4c200000 0x200>; + interrupts = ; + clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, + <&clk IMX93_CLK_HSIO_32K_GATE>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + assigned-clocks = <&clk IMX93_CLK_HSIO>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <133000000>; + phys = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@4c200200 { + compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", + "fsl,imx6q-usbmisc"; + reg = <0x4c200200 0x200>; + #index-cells = <1>; + }; + + memory-controller@4e300000 { + compatible = "nxp,imx9-memory-controller"; + reg = <0x4e300000 0x800>, <0x4e301000 0x1000>; + reg-names = "ctrl", "inject"; + interrupts = ; + little-endian; + }; + + ddr-pmu@4e300dc0 { + compatible = "fsl,imx93-ddr-pmu"; + reg = <0x4e300dc0 0x200>; + interrupts = ; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index d505f9dfd8ee..7b27012dfcb5 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -1,153 +1,15 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2022 NXP + * Copyright 2022,2025 NXP */ -#include -#include -#include -#include -#include -#include -#include +#include "imx91_93_common.dtsi" -#include "imx93-pinfunc.h" - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - idle-states { - entry-method = "psci"; - - cpu_pd_wait: cpu-pd-wait { - compatible = "arm,idle-state"; - arm,psci-suspend-param = <0x0010033>; - local-timer-stop; - entry-latency-us = <10000>; - exit-latency-us = <7000>; - min-residency-us = <27000>; - wakeup-latency-us = <15000>; - }; - }; - - A55_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0>; - enable-method = "psci"; - #cooling-cells = <2>; - cpu-idle-states = <&cpu_pd_wait>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l0>; - }; - - A55_1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x100>; - enable-method = "psci"; - #cooling-cells = <2>; - cpu-idle-states = <&cpu_pd_wait>; - i-cache-size = <32768>; - i-cache-line-size = <64>; - i-cache-sets = <128>; - d-cache-size = <32768>; - d-cache-line-size = <64>; - d-cache-sets = <128>; - next-level-cache = <&l2_cache_l1>; - }; - - l2_cache_l0: l2-cache-l0 { - compatible = "cache"; - cache-size = <65536>; - cache-line-size = <64>; - cache-sets = <256>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l2_cache_l1: l2-cache-l1 { - compatible = "cache"; - cache-size = <65536>; - cache-line-size = <64>; - cache-sets = <256>; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_cache>; - }; - - l3_cache: l3-cache { - compatible = "cache"; - cache-size = <262144>; - cache-line-size = <64>; - cache-sets = <256>; - cache-level = <3>; - cache-unified; - }; - }; - - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - pmu { - compatible = "arm,cortex-a55-pmu"; - interrupts = ; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - arm,no-tick-in-suspend; - interrupt-parent = <&gic>; - }; - - gic: interrupt-controller@48000000 { - compatible = "arm,gic-v3"; - reg = <0 0x48000000 0 0x10000>, - <0 0x48040000 0 0xc0000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; +/{ + cm33: remoteproc-cm33 { + compatible = "fsl,imx93-cm33"; + clocks = <&clk IMX93_CLK_CM33_GATE>; + status = "disabled"; }; thermal-zones { @@ -181,1143 +43,119 @@ map0 { }; }; }; +}; - cm33: remoteproc-cm33 { - compatible = "fsl,imx93-cm33"; - clocks = <&clk IMX93_CLK_CM33_GATE>; +&aips1 { + mu1: mailbox@44230000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x44230000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_MU1_B_GATE>; + #mbox-cells = <2>; status = "disabled"; }; - mqs1: mqs1 { - compatible = "fsl,imx93-mqs"; - gpr = <&aonmix_ns_gpr>; - status = "disabled"; - }; - - mqs2: mqs2 { - compatible = "fsl,imx93-mqs"; - gpr = <&wakeupmix_gpr>; - status = "disabled"; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; - clock-names = "main_clk"; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; - clock-names = "main_clk"; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x80000000>, - <0x28000000 0x0 0x28000000 0x10000000>; - - aips1: bus@44000000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x44000000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - edma1: dma-controller@44000000 { - compatible = "fsl,imx93-edma3"; - reg = <0x44000000 0x200000>; - #dma-cells = <3>; - dma-channels = <31>; - interrupts = , // 0: Reserved - , // 1: CANFD1 - , // 2: Reserved - , // 3: GPIO1 CH0 - , // 4: GPIO1 CH1 - , // 5: I3C1 TO Bus - , // 6: I3C1 From Bus - , // 7: LPI2C1 M TX - , // 8: LPI2C1 S TX - , // 9: LPI2C2 M RX - , // 10: LPI2C2 S RX - , // 11: LPSPI1 TX - , // 12: LPSPI1 RX - , // 13: LPSPI2 TX - , // 14: LPSPI2 RX - , // 15: LPTMR1 - , // 16: LPUART1 TX - , // 17: LPUART1 RX - , // 18: LPUART2 TX - , // 19: LPUART2 RX - , // 20: S400 - , // 21: SAI TX - , // 22: SAI RX - , // 23: TPM1 CH0/CH2 - , // 24: TPM1 CH1/CH3 - , // 25: TPM1 Overflow - , // 26: TMP2 CH0/CH2 - , // 27: TMP2 CH1/CH3 - , // 28: TMP2 Overflow - , // 29: PDM - , // 30: ADC1 - ; // err - clocks = <&clk IMX93_CLK_EDMA1_GATE>; - clock-names = "dma"; - }; - - aonmix_ns_gpr: syscon@44210000 { - compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; - reg = <0x44210000 0x1000>; - }; - - mu1: mailbox@44230000 { - compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; - reg = <0x44230000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_MU1_B_GATE>; - #mbox-cells = <2>; - status = "disabled"; - }; - - system_counter: timer@44290000 { - compatible = "nxp,sysctr-timer"; - reg = <0x44290000 0x30000>; - interrupts = ; - clocks = <&osc_24m>; - clock-names = "per"; - nxp,no-divider; - }; - - wdog1: watchdog@442d0000 { - compatible = "fsl,imx93-wdt"; - reg = <0x442d0000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_WDOG1_GATE>; - timeout-sec = <40>; - status = "disabled"; - }; - - wdog2: watchdog@442e0000 { - compatible = "fsl,imx93-wdt"; - reg = <0x442e0000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_WDOG2_GATE>; - timeout-sec = <40>; - status = "disabled"; - }; - - tpm1: pwm@44310000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x44310000 0x1000>; - clocks = <&clk IMX93_CLK_TPM1_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm2: pwm@44320000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x44320000 0x10000>; - clocks = <&clk IMX93_CLK_TPM2_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - i3c1: i3c@44330000 { - compatible = "silvaco,i3c-master-v1"; - reg = <0x44330000 0x10000>; - interrupts = ; - #address-cells = <3>; - #size-cells = <0>; - clocks = <&clk IMX93_CLK_BUS_AON>, - <&clk IMX93_CLK_I3C1_GATE>, - <&clk IMX93_CLK_I3C1_SLOW>; - clock-names = "pclk", "fast_clk", "slow_clk"; - status = "disabled"; - }; - - lpi2c1: i2c@44340000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x44340000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPI2C1_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - dmas = <&edma1 7 0 0>, <&edma1 8 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpi2c2: i2c@44350000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x44350000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPI2C2_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - dmas = <&edma1 9 0 0>, <&edma1 10 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi1: spi@44360000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x44360000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPSPI1_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - dmas = <&edma1 11 0 0>, <&edma1 12 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi2: spi@44370000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x44370000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPSPI2_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - dmas = <&edma1 13 0 0>, <&edma1 14 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpuart1: serial@44380000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x44380000 0x1000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPUART1_GATE>; - clock-names = "ipg"; - dmas = <&edma1 17 0 FSL_EDMA_RX>, <&edma1 16 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpuart2: serial@44390000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x44390000 0x1000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPUART2_GATE>; - clock-names = "ipg"; - dmas = <&edma1 19 0 FSL_EDMA_RX>, <&edma1 18 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - flexcan1: can@443a0000 { - compatible = "fsl,imx93-flexcan"; - reg = <0x443a0000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_BUS_AON>, - <&clk IMX93_CLK_CAN1_GATE>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX93_CLK_CAN1>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>; - status = "disabled"; - }; - - sai1: sai@443b0000 { - compatible = "fsl,imx93-sai"; - reg = <0x443b0000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_DUMMY>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma1 22 0 FSL_EDMA_RX>, <&edma1 21 0 0>; - dma-names = "rx", "tx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - iomuxc: pinctrl@443c0000 { - compatible = "fsl,imx93-iomuxc"; - reg = <0x443c0000 0x10000>; - status = "okay"; - }; - - bbnsm: bbnsm@44440000 { - compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; - reg = <0x44440000 0x10000>; - - bbnsm_rtc: rtc { - compatible = "nxp,imx93-bbnsm-rtc"; - interrupts = ; - }; - - bbnsm_pwrkey: pwrkey { - compatible = "nxp,imx93-bbnsm-pwrkey"; - interrupts = ; - linux,code = ; - }; - }; - - clk: clock-controller@44450000 { - compatible = "fsl,imx93-ccm"; - reg = <0x44450000 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; - clock-names = "osc_32k", "osc_24m", "clk_ext1"; - assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>; - assigned-clock-rates = <393216000>; - status = "okay"; - }; - - src: system-controller@44460000 { - compatible = "fsl,imx93-src", "syscon"; - reg = <0x44460000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mlmix: power-domain@44461800 { - compatible = "fsl,imx93-src-slice"; - reg = <0x44461800 0x400>, <0x44464800 0x400>; - #power-domain-cells = <0>; - clocks = <&clk IMX93_CLK_ML_APB>, - <&clk IMX93_CLK_ML>; - }; - - mediamix: power-domain@44462400 { - compatible = "fsl,imx93-src-slice"; - reg = <0x44462400 0x400>, <0x44465800 0x400>; - #power-domain-cells = <0>; - clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>, - <&clk IMX93_CLK_MEDIA_APB>; - }; - }; - - clock-controller@44480000 { - compatible = "fsl,imx93-anatop"; - reg = <0x44480000 0x2000>; - #clock-cells = <1>; - }; - - tmu: tmu@44482000 { - compatible = "fsl,qoriq-tmu"; - reg = <0x44482000 0x1000>; - interrupts = ; - clocks = <&clk IMX93_CLK_TMC_GATE>; - little-endian; - fsl,tmu-range = <0x800000da 0x800000e9 - 0x80000102 0x8000012a - 0x80000166 0x800001a7 - 0x800001b6>; - fsl,tmu-calibration = <0x00000000 0x0000000e - 0x00000001 0x00000029 - 0x00000002 0x00000056 - 0x00000003 0x000000a2 - 0x00000004 0x00000116 - 0x00000005 0x00000195 - 0x00000006 0x000001b2>; - #thermal-sensor-cells = <1>; - }; - - micfil: micfil@44520000 { - compatible = "fsl,imx93-micfil"; - reg = <0x44520000 0x10000>; - interrupts = , - , - , - ; - clocks = <&clk IMX93_CLK_PDM_IPG>, - <&clk IMX93_CLK_PDM_GATE>, - <&clk IMX93_CLK_AUDIO_PLL>; - clock-names = "ipg_clk", "ipg_clk_app", "pll8k"; - dmas = <&edma1 29 0 5>; - dma-names = "rx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - adc1: adc@44530000 { - compatible = "nxp,imx93-adc"; - reg = <0x44530000 0x10000>; - interrupts = , - , - ; - clocks = <&clk IMX93_CLK_ADC1_GATE>; - clock-names = "ipg"; - #io-channel-cells = <1>; - status = "disabled"; - }; - }; - - aips2: bus@42000000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x42000000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - edma2: dma-controller@42000000 { - compatible = "fsl,imx93-edma4"; - reg = <0x42000000 0x210000>; - #dma-cells = <3>; - dma-channels = <64>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&clk IMX93_CLK_EDMA2_GATE>; - clock-names = "dma"; - }; - - wakeupmix_gpr: syscon@42420000 { - compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; - reg = <0x42420000 0x1000>; - }; - - mu2: mailbox@42440000 { - compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; - reg = <0x42440000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_MU2_B_GATE>; - #mbox-cells = <2>; - status = "disabled"; - }; - - wdog3: watchdog@42490000 { - compatible = "fsl,imx93-wdt"; - reg = <0x42490000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_WDOG3_GATE>; - timeout-sec = <40>; - status = "disabled"; - }; - - wdog4: watchdog@424a0000 { - compatible = "fsl,imx93-wdt"; - reg = <0x424a0000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_WDOG4_GATE>; - timeout-sec = <40>; - status = "disabled"; - }; - - wdog5: watchdog@424b0000 { - compatible = "fsl,imx93-wdt"; - reg = <0x424b0000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_WDOG5_GATE>; - timeout-sec = <40>; - status = "disabled"; - }; - - tpm3: pwm@424e0000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x424e0000 0x1000>; - clocks = <&clk IMX93_CLK_TPM3_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm4: pwm@424f0000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x424f0000 0x10000>; - clocks = <&clk IMX93_CLK_TPM4_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm5: pwm@42500000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x42500000 0x10000>; - clocks = <&clk IMX93_CLK_TPM5_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm6: pwm@42510000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x42510000 0x10000>; - clocks = <&clk IMX93_CLK_TPM6_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - i3c2: i3c@42520000 { - compatible = "silvaco,i3c-master-v1"; - reg = <0x42520000 0x10000>; - interrupts = ; - #address-cells = <3>; - #size-cells = <0>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_I3C2_GATE>, - <&clk IMX93_CLK_I3C2_SLOW>; - clock-names = "pclk", "fast_clk", "slow_clk"; - status = "disabled"; - }; - - lpi2c3: i2c@42530000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x42530000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPI2C3_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpi2c4: i2c@42540000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x42540000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPI2C4_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi3: spi@42550000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42550000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPSPI3_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi4: spi@42560000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42560000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPSPI4_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpuart3: serial@42570000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42570000 0x1000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPUART3_GATE>; - clock-names = "ipg"; - dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpuart4: serial@42580000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42580000 0x1000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPUART4_GATE>; - clock-names = "ipg"; - dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpuart5: serial@42590000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42590000 0x1000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPUART5_GATE>; - clock-names = "ipg"; - dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpuart6: serial@425a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x425a0000 0x1000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPUART6_GATE>; - clock-names = "ipg"; - dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - flexcan2: can@425b0000 { - compatible = "fsl,imx93-flexcan"; - reg = <0x425b0000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_CAN2_GATE>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX93_CLK_CAN2>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>; - status = "disabled"; - }; - - flexspi1: spi@425e0000 { - compatible = "nxp,imx8mm-fspi"; - reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; - reg-names = "fspi_base", "fspi_mmap"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, - <&clk IMX93_CLK_FLEXSPI1_GATE>; - clock-names = "fspi_en", "fspi"; - assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; - status = "disabled"; - }; - - sai2: sai@42650000 { - compatible = "fsl,imx93-sai"; - reg = <0x42650000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_DUMMY>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; - dma-names = "rx", "tx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - sai3: sai@42660000 { - compatible = "fsl,imx93-sai"; - reg = <0x42660000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_DUMMY>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; - dma-names = "rx", "tx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - xcvr: xcvr@42680000 { - compatible = "fsl,imx93-xcvr"; - reg = <0x42680000 0x800>, - <0x42680800 0x400>, - <0x42680c00 0x080>, - <0x42680e00 0x080>; - reg-names = "ram", "regs", "rxfifo", "txfifo"; - interrupts = , - ; - clocks = <&clk IMX93_CLK_SPDIF_IPG>, - <&clk IMX93_CLK_SPDIF_GATE>, - <&clk IMX93_CLK_DUMMY>, - <&clk IMX93_CLK_AUD_XCVR_GATE>; - clock-names = "ipg", "phy", "spba", "pll_ipg"; - dmas = <&edma2 65 0 FSL_EDMA_RX>, <&edma2 66 0 0>; - dma-names = "rx", "tx"; - #sound-dai-cells = <0>; - status = "disabled"; - }; - - lpuart7: serial@42690000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42690000 0x1000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPUART7_GATE>; - clock-names = "ipg"; - dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpuart8: serial@426a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x426a0000 0x1000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPUART8_GATE>; - clock-names = "ipg"; - dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - lpi2c5: i2c@426b0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426b0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPI2C5_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpi2c6: i2c@426c0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426c0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPI2C6_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpi2c7: i2c@426d0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426d0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPI2C7_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpi2c8: i2c@426e0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426e0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPI2C8_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi5: spi@426f0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x426f0000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPSPI5_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi6: spi@42700000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42700000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPSPI6_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi7: spi@42710000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42710000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPSPI7_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - lpspi8: spi@42720000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42720000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_LPSPI8_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - }; - - aips3: bus@42800000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x42800000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usdhc1: mmc@42850000 { - compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x42850000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_USDHC1_GATE>; - clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX93_CLK_USDHC1>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - fsl,tuning-start-tap = <1>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - - usdhc2: mmc@42860000 { - compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x42860000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_USDHC2_GATE>; - clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX93_CLK_USDHC2>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; - assigned-clock-rates = <400000000>; - bus-width = <4>; - fsl,tuning-start-tap = <1>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - - fec: ethernet@42890000 { - compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; - reg = <0x42890000 0x10000>; - interrupts = , - , - , - ; - clocks = <&clk IMX93_CLK_ENET1_GATE>, - <&clk IMX93_CLK_ENET1_GATE>, - <&clk IMX93_CLK_ENET_TIMER1>, - <&clk IMX93_CLK_ENET_REF>, - <&clk IMX93_CLK_ENET_REF_PHY>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, - <&clk IMX93_CLK_ENET_REF>, - <&clk IMX93_CLK_ENET_REF_PHY>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <100000000>, <250000000>, <50000000>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; - nvmem-cells = <ð_mac1>; - nvmem-cell-names = "mac-address"; - status = "disabled"; - }; - - eqos: ethernet@428a0000 { - compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; - reg = <0x428a0000 0x10000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, - <&clk IMX93_CLK_ENET_QOS_GATE>, - <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>, - <&clk IMX93_CLK_ENET_QOS_GATE>; - clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; - assigned-clock-rates = <100000000>, <250000000>; - intf_mode = <&wakeupmix_gpr 0x28>; - snps,clk-csr = <6>; - nvmem-cells = <ð_mac2>; - nvmem-cell-names = "mac-address"; - status = "disabled"; - }; - - usdhc3: mmc@428b0000 { - compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x428b0000 0x10000>; - interrupts = ; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_USDHC3_GATE>; - clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX93_CLK_USDHC3>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; - assigned-clock-rates = <400000000>; - bus-width = <4>; - fsl,tuning-start-tap = <1>; - fsl,tuning-step = <2>; - status = "disabled"; - }; - }; - - gpio2: gpio@43810000 { - compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; - reg = <0x43810000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = , - ; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO2_GATE>, - <&clk IMX93_CLK_GPIO2_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 4 30>; - ngpios = <30>; - }; - - gpio3: gpio@43820000 { - compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; - reg = <0x43820000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = , - ; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO3_GATE>, - <&clk IMX93_CLK_GPIO3_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, - <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; - ngpios = <32>; - }; - - gpio4: gpio@43830000 { - compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; - reg = <0x43830000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = , - ; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO4_GATE>, - <&clk IMX93_CLK_GPIO4_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; - ngpios = <30>; - }; - - gpio1: gpio@47400000 { - compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; - reg = <0x47400000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupts = , - ; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO1_GATE>, - <&clk IMX93_CLK_GPIO1_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 92 16>; - ngpios = <16>; - }; - - ocotp: efuse@47510000 { - compatible = "fsl,imx93-ocotp", "syscon"; - reg = <0x47510000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - eth_mac1: mac-address@4ec { - reg = <0x4ec 0x6>; - }; - - eth_mac2: mac-address@4f2 { - reg = <0x4f2 0x6>; - }; - - }; - - s4muap: mailbox@47520000 { - compatible = "fsl,imx93-mu-s4"; - reg = <0x47520000 0x10000>; - interrupts = , - ; - interrupt-names = "tx", "rx"; - #mbox-cells = <2>; - }; - - media_blk_ctrl: system-controller@4ac10000 { - compatible = "fsl,imx93-media-blk-ctrl", "syscon"; - reg = <0x4ac10000 0x10000>; - power-domains = <&mediamix>; - clocks = <&clk IMX93_CLK_MEDIA_APB>, - <&clk IMX93_CLK_MEDIA_AXI>, - <&clk IMX93_CLK_NIC_MEDIA_GATE>, - <&clk IMX93_CLK_MEDIA_DISP_PIX>, - <&clk IMX93_CLK_CAM_PIX>, - <&clk IMX93_CLK_PXP_GATE>, - <&clk IMX93_CLK_LCDIF_GATE>, - <&clk IMX93_CLK_ISI_GATE>, - <&clk IMX93_CLK_MIPI_CSI_GATE>, - <&clk IMX93_CLK_MIPI_DSI_GATE>; - clock-names = "apb", "axi", "nic", "disp", "cam", - "pxp", "lcdif", "isi", "csi", "dsi"; - #power-domain-cells = <1>; - status = "disabled"; - }; - - usbotg1: usb@4c100000 { - compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x4c100000 0x200>; - interrupts = ; - clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, - <&clk IMX93_CLK_HSIO_32K_GATE>; - clock-names = "usb_ctrl_root", "usb_wakeup"; - assigned-clocks = <&clk IMX93_CLK_HSIO>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <133000000>; - phys = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; - status = "disabled"; - }; - - usbmisc1: usbmisc@4c100200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x4c100200 0x200>; - #index-cells = <1>; - }; - - usbotg2: usb@4c200000 { - compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x4c200000 0x200>; - interrupts = ; - clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, - <&clk IMX93_CLK_HSIO_32K_GATE>; - clock-names = "usb_ctrl_root", "usb_wakeup"; - assigned-clocks = <&clk IMX93_CLK_HSIO>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <133000000>; - phys = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - status = "disabled"; - }; - - usbmisc2: usbmisc@4c200200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x4c200200 0x200>; - #index-cells = <1>; - }; - - memory-controller@4e300000 { - compatible = "nxp,imx9-memory-controller"; - reg = <0x4e300000 0x800>, <0x4e301000 0x1000>; - reg-names = "ctrl", "inject"; - interrupts = ; - little-endian; - }; - - ddr-pmu@4e300dc0 { - compatible = "fsl,imx93-ddr-pmu"; - reg = <0x4e300dc0 0x200>; - interrupts = ; - }; + tmu: tmu@44482000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x44482000 0x1000>; + interrupts = ; + clocks = <&clk IMX93_CLK_TMC_GATE>; + #thermal-sensor-cells = <1>; + little-endian; + fsl,tmu-range = <0x800000da 0x800000e9 + 0x80000102 0x8000012a + 0x80000166 0x800001a7 + 0x800001b6>; + fsl,tmu-calibration = <0x00000000 0x0000000e + 0x00000001 0x00000029 + 0x00000002 0x00000056 + 0x00000003 0x000000a2 + 0x00000004 0x00000116 + 0x00000005 0x00000195 + 0x00000006 0x000001b2>; + }; +}; + +&aips2 { + mu2: mailbox@42440000 { + compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; + reg = <0x42440000 0x10000>; + interrupts = ; + clocks = <&clk IMX93_CLK_MU2_B_GATE>; + #mbox-cells = <2>; + status = "disabled"; + }; +}; + +&cpus { + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + }; + + A55_1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <262144>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <3>; + cache-unified; + }; +}; + +&src { + mlmix: power-domain@44461800 { + compatible = "fsl,imx93-src-slice"; + reg = <0x44461800 0x400>, <0x44464800 0x400>; + clocks = <&clk IMX93_CLK_ML_APB>, + <&clk IMX93_CLK_ML>; + #power-domain-cells = <0>; }; }; From b0830e7e8c8cf5e7a8d143f90d58f58eb8beed32 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Mon, 1 Sep 2025 18:36:29 +0800 Subject: [PATCH 652/931] arm64: dts: imx91: add i.MX91 dtsi support The i.MX 91 family features an Arm Cortex-A55 running at up to 1.4GHz, support for modern LPDDR4 memory to enable platform longevity, along with a rich set of peripherals targeting medical, industrial and consumer IoT market segments. The mainly difference between i.MX91 and i.MX93 is as follows: - i.MX91 removed some clocks and modified the names of some clocks. - i.MX91 only has one A core. - i.MX91 has different pinmux. Tested-by: Alexander Stein Reviewed-by: Frank Li Signed-off-by: Joy Zou Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx91-pinfunc.h | 770 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx91.dtsi | 71 ++ .../boot/dts/freescale/imx91_93_common.dtsi | 2 +- 3 files changed, 842 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/freescale/imx91-pinfunc.h create mode 100644 arch/arm64/boot/dts/freescale/imx91.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx91-pinfunc.h b/arch/arm64/boot/dts/freescale/imx91-pinfunc.h new file mode 100644 index 000000000000..3e19945f5ce3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-pinfunc.h @@ -0,0 +1,770 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright 2025 NXP + */ + +#ifndef __DTS_IMX91_PINFUNC_H +#define __DTS_IMX91_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01b0 0x03d8 0x00 0x00 +#define MX91_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01b0 0x0000 0x01 0x00 +#define MX91_PAD_DAP_TDI__CAN2_TX 0x0000 0x01b0 0x0000 0x03 0x00 +#define MX91_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01b0 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01b0 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01b0 0x0488 0x06 0x00 + +#define MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01b4 0x03dc 0x00 0x00 +#define MX91_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01b4 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01b4 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01b4 0x0000 0x06 0x00 + +#define MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01b8 0x03d4 0x00 0x00 +#define MX91_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01b8 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01b8 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01b8 0x0484 0x06 0x00 + +#define MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000c 0x01bc 0x0000 0x00 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000c 0x01bc 0x0000 0x01 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000c 0x01bc 0x0364 0x03 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000c 0x01bc 0x0000 0x04 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000c 0x01bc 0x0000 0x05 0x00 +#define MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000c 0x01bc 0x048c 0x06 0x00 + +#define MX91_PAD_GPIO_IO00__GPIO2_IO0 0x0010 0x01c0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01c0 0x03f4 0x01 0x00 +#define MX91_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01c0 0x04bc 0x02 0x00 +#define MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01c0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01c0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01c0 0x048c 0x05 0x01 +#define MX91_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01c0 0x0404 0x06 0x00 +#define MX91_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 0x0010 0x01c0 0x036c 0x07 0x00 + +#define MX91_PAD_GPIO_IO01__GPIO2_IO1 0x0014 0x01c4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01c4 0x03f0 0x01 0x00 +#define MX91_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 0x0014 0x01c4 0x0490 0x02 0x00 +#define MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01c4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01c4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01c4 0x0488 0x05 0x01 +#define MX91_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01c4 0x0400 0x06 0x00 +#define MX91_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 0x0014 0x01c4 0x0370 0x07 0x00 + +#define MX91_PAD_GPIO_IO02__GPIO2_IO2 0x0018 0x01c8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01c8 0x03fc 0x01 0x00 +#define MX91_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01c8 0x04c0 0x02 0x00 +#define MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01c8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01c8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01c8 0x0484 0x05 0x01 +#define MX91_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01c8 0x040c 0x06 0x00 +#define MX91_PAD_GPIO_IO02__FLEXIO1_FLEXIO2 0x0018 0x01c8 0x0374 0x07 0x00 + +#define MX91_PAD_GPIO_IO03__GPIO2_IO3 0x001c 0x01cc 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO03__LPI2C4_SCL 0x001c 0x01cc 0x03f8 0x01 0x00 +#define MX91_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001c 0x01cc 0x04b8 0x02 0x00 +#define MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001c 0x01cc 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x001c 0x01cc 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO03__LPUART5_RTS_B 0x001c 0x01cc 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO03__LPI2C6_SCL 0x001c 0x01cc 0x0408 0x06 0x00 +#define MX91_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 0x001c 0x01cc 0x0378 0x07 0x00 + +#define MX91_PAD_GPIO_IO04__GPIO2_IO4 0x0020 0x01d0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01d0 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01d0 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x0020 0x01d0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01d0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01d0 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01d0 0x040c 0x06 0x01 +#define MX91_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 0x0020 0x01d0 0x037c 0x07 0x00 + +#define MX91_PAD_GPIO_IO05__GPIO2_IO5 0x0024 0x01d4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01d4 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO05__PDM_BIT_STREAM0 0x0024 0x01d4 0x04c4 0x02 0x00 +#define MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x0024 0x01d4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01d4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01d4 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01d4 0x0408 0x06 0x01 +#define MX91_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 0x0024 0x01d4 0x0380 0x07 0x00 + +#define MX91_PAD_GPIO_IO06__GPIO2_IO6 0x0028 0x01d8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01d8 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO06__PDM_BIT_STREAM1 0x0028 0x01d8 0x04c8 0x02 0x00 +#define MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x0028 0x01d8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01d8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01d8 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01d8 0x0414 0x06 0x00 +#define MX91_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 0x0028 0x01d8 0x0384 0x07 0x00 + +#define MX91_PAD_GPIO_IO07__GPIO2_IO7 0x002c 0x01dc 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO07__LPSPI3_PCS1 0x002c 0x01dc 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 0x002c 0x01dc 0x0494 0x02 0x00 +#define MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x002c 0x01dc 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO07__LPSPI7_SCK 0x002c 0x01dc 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO07__LPUART6_RTS_B 0x002c 0x01dc 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO07__LPI2C7_SCL 0x002c 0x01dc 0x0410 0x06 0x00 +#define MX91_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 0x002c 0x01dc 0x0388 0x07 0x00 + +#define MX91_PAD_GPIO_IO08__GPIO2_IO8 0x0030 0x01e0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01e0 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 0x0030 0x01e0 0x0498 0x02 0x00 +#define MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x0030 0x01e0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01e0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01e0 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01e0 0x0414 0x06 0x01 +#define MX91_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 0x0030 0x01e0 0x038c 0x07 0x00 + +#define MX91_PAD_GPIO_IO09__GPIO2_IO9 0x0034 0x01e4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01e4 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 0x0034 0x01e4 0x049c 0x02 0x00 +#define MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x0034 0x01e4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01e4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01e4 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01e4 0x0410 0x06 0x01 +#define MX91_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 0x0034 0x01e4 0x0390 0x07 0x00 + +#define MX91_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01e8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01e8 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 0x0038 0x01e8 0x04a0 0x02 0x00 +#define MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x0038 0x01e8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01e8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01e8 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01e8 0x041c 0x06 0x00 +#define MX91_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01e8 0x0394 0x07 0x00 + +#define MX91_PAD_GPIO_IO11__GPIO2_IO11 0x003c 0x01ec 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x003c 0x01ec 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 0x003c 0x01ec 0x04a4 0x02 0x00 +#define MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x003c 0x01ec 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO11__TPM5_EXTCLK 0x003c 0x01ec 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO11__LPUART7_RTS_B 0x003c 0x01ec 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO11__LPI2C8_SCL 0x003c 0x01ec 0x0418 0x06 0x00 +#define MX91_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003c 0x01ec 0x0398 0x07 0x00 + +#define MX91_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01f0 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01f0 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO12__PDM_BIT_STREAM2 0x0040 0x01f0 0x04cc 0x02 0x00 +#define MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x0040 0x01f0 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01f0 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01f0 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01f0 0x041c 0x06 0x01 +#define MX91_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01f0 0x04dc 0x07 0x00 + +#define MX91_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01f4 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01f4 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO13__PDM_BIT_STREAM3 0x0044 0x01f4 0x04d0 0x02 0x00 +#define MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x0044 0x01f4 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01f4 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01f4 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01f4 0x0418 0x06 0x01 +#define MX91_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01f4 0x039c 0x07 0x00 + +#define MX91_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01f8 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01f8 0x0474 0x01 0x00 +#define MX91_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 0x0048 0x01f8 0x04a8 0x02 0x00 +#define MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01f8 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01f8 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01f8 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01f8 0x0480 0x06 0x00 +#define MX91_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01f8 0x03a0 0x07 0x00 + +#define MX91_PAD_GPIO_IO15__GPIO2_IO15 0x004c 0x01fc 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO15__LPUART3_RX 0x004c 0x01fc 0x0470 0x01 0x00 +#define MX91_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 0x004c 0x01fc 0x04ac 0x02 0x00 +#define MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004c 0x01fc 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x004c 0x01fc 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO15__LPUART8_RTS_B 0x004c 0x01fc 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO15__LPUART4_RX 0x004c 0x01fc 0x047c 0x06 0x00 +#define MX91_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004c 0x01fc 0x03a4 0x07 0x00 + +#define MX91_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO16__PDM_BIT_STREAM2 0x0050 0x0200 0x04cc 0x02 0x01 +#define MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x046c 0x04 0x00 +#define MX91_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0478 0x06 0x00 +#define MX91_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03a8 0x07 0x00 + +#define MX91_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 0x0054 0x0204 0x04b0 0x02 0x00 +#define MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03ac 0x07 0x00 + +#define MX91_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x04d8 0x01 0x00 +#define MX91_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 0x0058 0x0208 0x04b4 0x02 0x00 +#define MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03b0 0x07 0x00 + +#define MX91_PAD_GPIO_IO19__GPIO2_IO19 0x005c 0x020c 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005c 0x020c 0x04dc 0x01 0x01 +#define MX91_PAD_GPIO_IO19__PDM_BIT_STREAM3 0x005c 0x020c 0x04d0 0x02 0x01 +#define MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005c 0x020c 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO19__LPSPI5_SIN 0x005c 0x020c 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO19__LPSPI4_SIN 0x005c 0x020c 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO19__TPM6_CH2 0x005c 0x020c 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x005c 0x020c 0x0000 0x07 0x00 + +#define MX91_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x0060 0x0210 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO20__PDM_BIT_STREAM0 0x0060 0x0210 0x04c4 0x02 0x01 +#define MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03b4 0x07 0x00 + +#define MX91_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO21__SAI3_TX_DATA0 0x0064 0x0214 0x0000 0x01 0x00 +#define MX91_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x04d8 0x07 0x01 + +#define MX91_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x04e8 0x01 0x00 +#define MX91_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x04e4 0x02 0x00 +#define MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x0404 0x06 0x01 +#define MX91_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03b8 0x07 0x00 + +#define MX91_PAD_GPIO_IO23__GPIO2_IO23 0x006c 0x021c 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO23__USDHC3_CMD 0x006c 0x021c 0x04ec 0x01 0x00 +#define MX91_PAD_GPIO_IO23__SPDIF_OUT 0x006c 0x021c 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006c 0x021c 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO23__TPM6_CH1 0x006c 0x021c 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x006c 0x021c 0x0400 0x06 0x01 +#define MX91_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006c 0x021c 0x03bc 0x07 0x00 + +#define MX91_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x04f0 0x01 0x00 +#define MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x05 0x00 +#define MX91_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03c0 0x07 0x00 + +#define MX91_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x04f4 0x01 0x00 +#define MX91_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03d4 0x05 0x01 +#define MX91_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03c4 0x07 0x00 + +#define MX91_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x04f8 0x01 0x00 +#define MX91_PAD_GPIO_IO26__PDM_BIT_STREAM1 0x0078 0x0228 0x04c8 0x02 0x01 +#define MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03d8 0x05 0x01 +#define MX91_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x04e0 0x07 0x00 + +#define MX91_PAD_GPIO_IO27__GPIO2_IO27 0x007c 0x022c 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO27__USDHC3_DATA3 0x007c 0x022c 0x04fc 0x01 0x00 +#define MX91_PAD_GPIO_IO27__CAN2_RX 0x007c 0x022c 0x0364 0x02 0x01 +#define MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007c 0x022c 0x0000 0x03 0x00 +#define MX91_PAD_GPIO_IO27__TPM6_CH3 0x007c 0x022c 0x0000 0x04 0x00 +#define MX91_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007c 0x022c 0x03dc 0x05 0x01 +#define MX91_PAD_GPIO_IO27__LPSPI5_PCS1 0x007c 0x022c 0x0000 0x06 0x00 +#define MX91_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007c 0x022c 0x03c8 0x07 0x00 + +#define MX91_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03f4 0x01 0x01 +#define MX91_PAD_GPIO_IO28__CAN1_TX 0x0080 0x0230 0x0000 0x02 0x00 +#define MX91_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x07 0x00 + +#define MX91_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x00 0x00 +#define MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03f0 0x01 0x01 +#define MX91_PAD_GPIO_IO29__CAN1_RX 0x0084 0x0234 0x0360 0x02 0x00 +#define MX91_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x07 0x00 + +#define MX91_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x04 0x00 +#define MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x05 0x00 + +#define MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x008c 0x023c 0x0000 0x05 0x00 +#define MX91_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008c 0x023c 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008c 0x023c 0x03c8 0x04 0x01 + +#define MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x04 0x00 +#define MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x05 0x00 + +#define MX91_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x00 0x00 +#define MX91_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x04 0x00 +#define MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_MDC__ENET1_MDC 0x0098 0x0248 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03cc 0x02 0x00 +#define MX91_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 0x0098 0x0248 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_MDC__GPIO4_IO0 0x0098 0x0248 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_MDC__LPI2C1_SCL 0x0098 0x0248 0x03e0 0x06 0x00 + +#define MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009c 0x024c 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009c 0x024c 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_MDIO__I3C2_SDA 0x009c 0x024c 0x03d0 0x02 0x00 +#define MX91_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009c 0x024c 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 0x009c 0x024c 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x009c 0x024c 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_MDIO__LPI2C1_SDA 0x009c 0x024c 0x03e4 0x06 0x00 + +#define MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00a0 0x0250 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD3__CAN2_TX 0x00a0 0x0250 0x0000 0x02 0x00 +#define MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00a0 0x0250 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 0x00a0 0x0250 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD3__GPIO4_IO2 0x00a0 0x0250 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TD3__LPI2C2_SCL 0x00a0 0x0250 0x03e8 0x06 0x00 + +#define MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00a4 0x0254 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x00a4 0x0254 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TD2__CAN2_RX 0x00a4 0x0254 0x0364 0x02 0x02 +#define MX91_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00a4 0x0254 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 0x00a4 0x0254 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD2__GPIO4_IO3 0x00a4 0x0254 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TD2__LPI2C2_SDA 0x00a4 0x0254 0x03ec 0x06 0x00 + +#define MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x00a8 0x0258 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD1__LPUART3_RTS_B 0x00a8 0x0258 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TD1__I3C2_PUR 0x00a8 0x0258 0x0000 0x02 0x00 +#define MX91_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00a8 0x0258 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 0x00a8 0x0258 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD1__GPIO4_IO4 0x00a8 0x0258 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TD1__I3C2_PUR_B 0x00a8 0x0258 0x0000 0x06 0x00 + +#define MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00ac 0x025c 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TD0__LPUART3_TX 0x00ac 0x025c 0x0474 0x01 0x01 +#define MX91_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 0x00ac 0x025c 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TD0__GPIO4_IO5 0x00ac 0x025c 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00b0 0x0260 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00b0 0x0260 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 0x00b0 0x0260 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x00b0 0x0260 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TX_CTL__LPSPI2_SCK 0x00b0 0x0260 0x043c 0x02 0x00 + +#define MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00b4 0x0264 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00b4 0x0264 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 0x00b4 0x0264 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_TXC__GPIO4_IO7 0x00b4 0x0264 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_TXC__LPSPI2_SIN 0x00b4 0x0264 0x0440 0x02 0x00 + +#define MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00b8 0x0268 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00b8 0x0268 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00b8 0x0268 0x0000 0x03 0x00 +#define MX91_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 0x00b8 0x0268 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x00b8 0x0268 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_RX_CTL__LPSPI2_PCS0 0x00b8 0x0268 0x0434 0x02 0x00 + +#define MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x00bc 0x026c 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00bc 0x026c 0x0000 0x01 0x00 +#define MX91_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 0x00bc 0x026c 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RXC__GPIO4_IO9 0x00bc 0x026c 0x0000 0x05 0x00 +#define MX91_PAD_ENET1_RXC__LPSPI2_SOUT 0x00bc 0x026c 0x0444 0x02 0x00 + +#define MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00c0 0x0270 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD0__LPUART3_RX 0x00c0 0x0270 0x0470 0x01 0x01 +#define MX91_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00c0 0x0270 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD0__GPIO4_IO10 0x00c0 0x0270 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00c4 0x0274 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD1__LPUART3_CTS_B 0x00c4 0x0274 0x046c 0x01 0x01 +#define MX91_PAD_ENET1_RD1__LPTMR2_ALT1 0x00c4 0x0274 0x0448 0x03 0x00 +#define MX91_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00c4 0x0274 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD1__GPIO4_IO11 0x00c4 0x0274 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00c8 0x0278 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD2__LPTMR2_ALT2 0x00c8 0x0278 0x044c 0x03 0x00 +#define MX91_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00c8 0x0278 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD2__GPIO4_IO12 0x00c8 0x0278 0x0000 0x05 0x00 + +#define MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00cc 0x027c 0x0000 0x00 0x00 +#define MX91_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00cc 0x027c 0x0000 0x02 0x00 +#define MX91_PAD_ENET1_RD3__LPTMR2_ALT3 0x00cc 0x027c 0x0450 0x03 0x00 +#define MX91_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00cc 0x027c 0x0000 0x04 0x00 +#define MX91_PAD_ENET1_RD3__GPIO4_IO13 0x00cc 0x027c 0x0000 0x05 0x00 + +#define MX91_PAD_ENET2_MDC__ENET2_MDC 0x00d0 0x0280 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_MDC__LPUART4_DCB_B 0x00d0 0x0280 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00d0 0x0280 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00d0 0x0280 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_MDC__GPIO4_IO14 0x00d0 0x0280 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK 0x00d0 0x0280 0x04bc 0x06 0x01 + +#define MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x00d4 0x0284 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00d4 0x0284 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00d4 0x0284 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00d4 0x0284 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x00d4 0x0284 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 0x00d4 0x0284 0x0490 0x06 0x01 + +#define MX91_PAD_ENET2_TD3__SAI2_RX_DATA0 0x00d8 0x0288 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00d8 0x0288 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD3__GPIO4_IO16 0x00d8 0x0288 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC 0x00d8 0x0288 0x04c0 0x06 0x01 +#define MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x00d8 0x0288 0x0000 0x00 0x00 + +#define MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x00dc 0x028c 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x00dc 0x028c 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00dc 0x028c 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD2__GPIO4_IO17 0x00dc 0x028c 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC 0x00dc 0x028c 0x04b8 0x06 0x01 + +#define MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x00e0 0x0290 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TD1__LPUART4_RTS_B 0x00e0 0x0290 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00e0 0x0290 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD1__GPIO4_IO18 0x00e0 0x0290 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 0x00e0 0x0290 0x0494 0x06 0x01 + +#define MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x00e4 0x0294 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TD0__LPUART4_TX 0x00e4 0x0294 0x0480 0x01 0x01 +#define MX91_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00e4 0x0294 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TD0__GPIO4_IO19 0x00e4 0x0294 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 0x00e4 0x0294 0x0498 0x06 0x01 + +#define MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x00e8 0x0298 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00e8 0x0298 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00e8 0x0298 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00e8 0x0298 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00e8 0x0298 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 0x00e8 0x0298 0x049c 0x06 0x01 + +#define MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x00ec 0x029c 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_TXC__ENET2_TX_ER 0x00ec 0x029c 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00ec 0x029c 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00ec 0x029c 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_TXC__GPIO4_IO21 0x00ec 0x029c 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 0x00ec 0x029c 0x04a0 0x06 0x01 + +#define MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x00f0 0x02a0 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00f0 0x02a0 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 0x00f0 0x02a0 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00f0 0x02a0 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00f0 0x02a0 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 0x00f0 0x02a0 0x04a4 0x06 0x01 + +#define MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x00f4 0x02a4 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RXC__ENET2_RX_ER 0x00f4 0x02a4 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00f4 0x02a4 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RXC__GPIO4_IO23 0x00f4 0x02a4 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 0x00f4 0x02a4 0x04a8 0x06 0x01 + +#define MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x00f8 0x02a8 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD0__LPUART4_RX 0x00f8 0x02a8 0x047c 0x01 0x01 +#define MX91_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00f8 0x02a8 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD0__GPIO4_IO24 0x00f8 0x02a8 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 0x00f8 0x02a8 0x04ac 0x06 0x01 + +#define MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x00fc 0x02ac 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD1__SPDIF_IN 0x00fc 0x02ac 0x04e4 0x01 0x01 +#define MX91_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00fc 0x02ac 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD1__GPIO4_IO25 0x00fc 0x02ac 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 0x00fc 0x02ac 0x04b0 0x06 0x01 + +#define MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x0100 0x02b0 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02b0 0x0478 0x01 0x01 +#define MX91_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02b0 0x0000 0x02 0x00 +#define MX91_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02b0 0x0000 0x03 0x00 +#define MX91_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02b0 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02b0 0x0000 0x05 0x00 +#define MX91_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 0x0100 0x02b0 0x04b4 0x06 0x01 + +#define MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x0104 0x02b4 0x0000 0x00 0x00 +#define MX91_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02b4 0x0000 0x01 0x00 +#define MX91_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02b4 0x04e4 0x02 0x02 +#define MX91_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02b4 0x0000 0x03 0x00 +#define MX91_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02b4 0x0000 0x04 0x00 +#define MX91_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02b4 0x0000 0x05 0x00 + +#define MX91_PAD_SD1_CLK__FLEXIO1_FLEXIO8 0x0108 0x02b8 0x038c 0x04 0x01 +#define MX91_PAD_SD1_CLK__GPIO3_IO8 0x0108 0x02b8 0x0000 0x05 0x00 +#define MX91_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02b8 0x0000 0x00 0x00 +#define MX91_PAD_SD1_CLK__LPSPI2_SCK 0x0108 0x02b8 0x043c 0x03 0x01 + +#define MX91_PAD_SD1_CMD__USDHC1_CMD 0x010c 0x02bc 0x0000 0x00 0x00 +#define MX91_PAD_SD1_CMD__FLEXIO1_FLEXIO9 0x010c 0x02bc 0x0390 0x04 0x01 +#define MX91_PAD_SD1_CMD__GPIO3_IO9 0x010c 0x02bc 0x0000 0x05 0x00 +#define MX91_PAD_SD1_CMD__LPSPI2_SIN 0x010c 0x02bc 0x0440 0x03 0x01 + +#define MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02c0 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02c0 0x0394 0x04 0x01 +#define MX91_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02c0 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA0__LPSPI2_PCS0 0x0110 0x02c0 0x0434 0x03 0x01 + +#define MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02c4 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02c4 0x0398 0x04 0x01 +#define MX91_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02c4 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02c4 0x0000 0x06 0x00 +#define MX91_PAD_SD1_DATA1__LPSPI2_SOUT 0x0114 0x02c4 0x0444 0x03 0x01 + +#define MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02c8 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02c8 0x0000 0x04 0x00 +#define MX91_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02c8 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02c8 0x0000 0x06 0x00 +#define MX91_PAD_SD1_DATA2__LPSPI2_PCS1 0x0118 0x02c8 0x0438 0x03 0x00 + +#define MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x011c 0x02cc 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011c 0x02cc 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011c 0x02cc 0x039c 0x04 0x01 +#define MX91_PAD_SD1_DATA3__GPIO3_IO13 0x011c 0x02cc 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA3__LPSPI1_PCS1 0x011c 0x02cc 0x0424 0x03 0x00 + +#define MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02d0 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 0x0120 0x02d0 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02d0 0x03a0 0x04 0x01 +#define MX91_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02d0 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA4__LPSPI1_PCS0 0x0120 0x02d0 0x0420 0x03 0x00 + +#define MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02d4 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 0x0124 0x02d4 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02d4 0x0000 0x02 0x00 +#define MX91_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02d4 0x03a4 0x04 0x01 +#define MX91_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02d4 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA5__LPSPI1_SIN 0x0124 0x02d4 0x042c 0x03 0x00 + +#define MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02d8 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 0x0128 0x02d8 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02d8 0x0000 0x02 0x00 +#define MX91_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02d8 0x03a8 0x04 0x01 +#define MX91_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02d8 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA6__LPSPI1_SCK 0x0128 0x02d8 0x0428 0x03 0x00 + +#define MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x012c 0x02dc 0x0000 0x00 0x00 +#define MX91_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 0x012c 0x02dc 0x0000 0x01 0x00 +#define MX91_PAD_SD1_DATA7__USDHC1_WP 0x012c 0x02dc 0x0000 0x02 0x00 +#define MX91_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012c 0x02dc 0x03ac 0x04 0x01 +#define MX91_PAD_SD1_DATA7__GPIO3_IO17 0x012c 0x02dc 0x0000 0x05 0x00 +#define MX91_PAD_SD1_DATA7__LPSPI1_SOUT 0x012c 0x02dc 0x0430 0x03 0x00 + +#define MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02e0 0x0000 0x00 0x00 +#define MX91_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02e0 0x0000 0x01 0x00 +#define MX91_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02e0 0x03b0 0x04 0x01 +#define MX91_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02e0 0x0000 0x05 0x00 + +#define MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02e4 0x0000 0x00 0x00 +#define MX91_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02e4 0x0000 0x01 0x00 +#define MX91_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02e4 0x0450 0x02 0x01 +#define MX91_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02e4 0x0000 0x04 0x00 +#define MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02e4 0x0000 0x05 0x00 +#define MX91_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02e4 0x0368 0x06 0x00 + +#define MX91_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02e8 0x04e8 0x00 0x01 +#define MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02e8 0x0000 0x01 0x00 +#define MX91_PAD_SD3_CLK__LPUART1_CTS_B 0x0138 0x02e8 0x0454 0x02 0x00 +#define MX91_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02e8 0x03b4 0x04 0x01 +#define MX91_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02e8 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_CMD__USDHC3_CMD 0x013c 0x02ec 0x04ec 0x00 0x01 +#define MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013c 0x02ec 0x0000 0x01 0x00 +#define MX91_PAD_SD3_CMD__LPUART1_RTS_B 0x013c 0x02ec 0x0000 0x02 0x00 +#define MX91_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013c 0x02ec 0x0000 0x04 0x00 +#define MX91_PAD_SD3_CMD__GPIO3_IO21 0x013c 0x02ec 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02f0 0x04f0 0x00 0x01 +#define MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x0140 0x02f0 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA0__LPUART2_CTS_B 0x0140 0x02f0 0x0460 0x02 0x00 +#define MX91_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02f0 0x03b8 0x04 0x01 +#define MX91_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02f0 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02f4 0x04f4 0x00 0x01 +#define MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x0144 0x02f4 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA1__LPUART2_RTS_B 0x0144 0x02f4 0x0000 0x02 0x00 +#define MX91_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02f4 0x03bc 0x04 0x01 +#define MX91_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02f4 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02f8 0x04f8 0x00 0x01 +#define MX91_PAD_SD3_DATA2__LPI2C4_SDA 0x0148 0x02f8 0x03fc 0x02 0x01 +#define MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x0148 0x02f8 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02f8 0x03c0 0x04 0x01 +#define MX91_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02f8 0x0000 0x05 0x00 + +#define MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x014c 0x02fc 0x04fc 0x00 0x01 +#define MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x014c 0x02fc 0x0000 0x01 0x00 +#define MX91_PAD_SD3_DATA3__LPI2C4_SCL 0x014c 0x02fc 0x03f8 0x02 0x01 +#define MX91_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014c 0x02fc 0x03c4 0x04 0x01 +#define MX91_PAD_SD3_DATA3__GPIO3_IO25 0x014c 0x02fc 0x0000 0x05 0x00 + +#define MX91_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x00 0x00 +#define MX91_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x01 0x00 +#define MX91_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03cc 0x02 0x01 +#define MX91_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 0x0150 0x0300 0x036c 0x04 0x01 +#define MX91_PAD_SD2_CD_B__GPIO3_IO0 0x0150 0x0300 0x0000 0x05 0x00 +#define MX91_PAD_SD2_CD_B__LPI2C1_SCL 0x0150 0x0300 0x03e0 0x03 0x01 + +#define MX91_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x00 0x00 +#define MX91_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x01 0x00 +#define MX91_PAD_SD2_CLK__I2C1_SDA 0x0154 0x0304 0x0000 0x03 0x00 +#define MX91_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03d0 0x02 0x01 +#define MX91_PAD_SD2_CLK__FLEXIO1_FLEXIO1 0x0154 0x0304 0x0370 0x04 0x01 +#define MX91_PAD_SD2_CLK__GPIO3_IO1 0x0154 0x0304 0x0000 0x05 0x00 +#define MX91_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x06 0x00 +#define MX91_PAD_SD2_CLK__LPI2C1_SDA 0x0154 0x0304 0x03e4 0x03 0x01 + +#define MX91_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x00 0x00 +#define MX91_PAD_SD2_CMD__ENET2_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x01 0x00 +#define MX91_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x02 0x00 +#define MX91_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x03 0x00 +#define MX91_PAD_SD2_CMD__FLEXIO1_FLEXIO2 0x0158 0x0308 0x0374 0x04 0x01 +#define MX91_PAD_SD2_CMD__GPIO3_IO2 0x0158 0x0308 0x0000 0x05 0x00 +#define MX91_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x015c 0x030c 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT 0x015c 0x030c 0x0000 0x01 0x00 +#define MX91_PAD_SD2_DATA0__CAN2_TX 0x015c 0x030c 0x0000 0x02 0x00 +#define MX91_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 0x015c 0x030c 0x0378 0x04 0x01 +#define MX91_PAD_SD2_DATA0__GPIO3_IO3 0x015c 0x030c 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA0__LPUART1_TX 0x015c 0x030c 0x045c 0x03 0x00 +#define MX91_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015c 0x030c 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x01 0x00 +#define MX91_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x02 0x03 +#define MX91_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 0x0160 0x0310 0x037c 0x04 0x01 +#define MX91_PAD_SD2_DATA1__GPIO3_IO4 0x0160 0x0310 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA1__LPUART1_RX 0x0160 0x0310 0x0458 0x03 0x00 +#define MX91_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x01 0x00 +#define MX91_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x02 0x00 +#define MX91_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 0x0164 0x0314 0x0380 0x04 0x01 +#define MX91_PAD_SD2_DATA2__GPIO3_IO5 0x0164 0x0314 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA2__LPUART2_TX 0x0164 0x0314 0x0468 0x03 0x00 +#define MX91_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x00 0x00 +#define MX91_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0448 0x01 0x01 +#define MX91_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x02 0x00 +#define MX91_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 0x0168 0x0318 0x0384 0x04 0x01 +#define MX91_PAD_SD2_DATA3__GPIO3_IO6 0x0168 0x0318 0x0000 0x05 0x00 +#define MX91_PAD_SD2_DATA3__LPUART2_RX 0x0168 0x0318 0x0464 0x03 0x00 +#define MX91_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x06 0x00 + +#define MX91_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016c 0x031c 0x0000 0x00 0x00 +#define MX91_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016c 0x031c 0x044c 0x01 0x01 +#define MX91_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 0x016c 0x031c 0x0388 0x04 0x01 +#define MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x016c 0x031c 0x0000 0x05 0x00 +#define MX91_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016c 0x031c 0x0000 0x06 0x00 + +#define MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x03e0 0x00 0x02 +#define MX91_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x01 0x00 +#define MX91_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x02 0x00 +#define MX91_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x03 0x00 +#define MX91_PAD_I2C1_SCL__GPIO1_IO0 0x0170 0x0320 0x0000 0x05 0x00 + +#define MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x03e4 0x00 0x02 +#define MX91_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x01 0x00 +#define MX91_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x02 0x00 +#define MX91_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x03 0x00 +#define MX91_PAD_I2C1_SDA__GPIO1_IO1 0x0174 0x0324 0x0000 0x05 0x00 + +#define MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x03e8 0x00 0x01 +#define MX91_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x01 0x00 +#define MX91_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x02 0x00 +#define MX91_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x03 0x00 +#define MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x04 0x00 +#define MX91_PAD_I2C2_SCL__GPIO1_IO2 0x0178 0x0328 0x0000 0x05 0x00 +#define MX91_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x06 0x00 + +#define MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x017c 0x032c 0x03ec 0x00 0x01 +#define MX91_PAD_I2C2_SDA__LPUART2_RIN_B 0x017c 0x032c 0x0000 0x02 0x00 +#define MX91_PAD_I2C2_SDA__TPM2_CH3 0x017c 0x032c 0x0000 0x03 0x00 +#define MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017c 0x032c 0x0000 0x04 0x00 +#define MX91_PAD_I2C2_SDA__GPIO1_IO3 0x017c 0x032c 0x0000 0x05 0x00 + +#define MX91_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0458 0x00 0x01 +#define MX91_PAD_UART1_RXD__ELE_UART_RX 0x0180 0x0330 0x0000 0x01 0x00 +#define MX91_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0440 0x02 0x02 +#define MX91_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x03 0x00 +#define MX91_PAD_UART1_RXD__GPIO1_IO4 0x0180 0x0330 0x0000 0x05 0x00 + +#define MX91_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x045c 0x00 0x01 +#define MX91_PAD_UART1_TXD__ELE_UART_TX 0x0184 0x0334 0x0000 0x01 0x00 +#define MX91_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0434 0x02 0x02 +#define MX91_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x03 0x00 +#define MX91_PAD_UART1_TXD__GPIO1_IO5 0x0184 0x0334 0x0000 0x05 0x00 + +#define MX91_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0464 0x00 0x01 +#define MX91_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0454 0x01 0x01 +#define MX91_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0444 0x02 0x02 +#define MX91_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x03 0x00 +#define MX91_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x04d4 0x04 0x00 +#define MX91_PAD_UART2_RXD__GPIO1_IO6 0x0188 0x0338 0x0000 0x05 0x00 + +#define MX91_PAD_UART2_TXD__LPUART2_TX 0x018c 0x033c 0x0468 0x00 0x01 +#define MX91_PAD_UART2_TXD__LPUART1_RTS_B 0x018c 0x033c 0x0000 0x01 0x00 +#define MX91_PAD_UART2_TXD__LPSPI2_SCK 0x018c 0x033c 0x043c 0x02 0x02 +#define MX91_PAD_UART2_TXD__TPM1_CH3 0x018c 0x033c 0x0000 0x03 0x00 +#define MX91_PAD_UART2_TXD__GPIO1_IO7 0x018c 0x033c 0x0000 0x05 0x00 +#define MX91_PAD_UART2_TXD__SAI3_TX_SYNC 0x018c 0x033c 0x04e0 0x07 0x02 + +#define MX91_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x00 0x00 +#define MX91_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x01 0x00 +#define MX91_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x04 0x00 +#define MX91_PAD_PDM_CLK__GPIO1_IO8 0x0190 0x0340 0x0000 0x05 0x00 +#define MX91_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x06 0x00 + +#define MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x0194 0x0344 0x04c4 0x00 0x02 +#define MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x01 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0424 0x02 0x01 +#define MX91_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x03 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x04 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x0194 0x0344 0x0000 0x05 0x00 +#define MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x06 0x01 + +#define MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x0198 0x0348 0x04c8 0x00 0x02 +#define MX91_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0438 0x02 0x01 +#define MX91_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x03 0x00 +#define MX91_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x04 0x00 +#define MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x05 0x00 +#define MX91_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x06 0x01 + +#define MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019c 0x034c 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_TXFS__SAI1_TX_DATA1 0x019c 0x034c 0x0000 0x01 0x00 +#define MX91_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019c 0x034c 0x0420 0x02 0x01 +#define MX91_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019c 0x034c 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_TXFS__MQS1_LEFT 0x019c 0x034c 0x0000 0x04 0x00 +#define MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x019c 0x034c 0x0000 0x05 0x00 + +#define MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01a0 0x0350 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_TXC__LPUART2_CTS_B 0x01a0 0x0350 0x0460 0x01 0x01 +#define MX91_PAD_SAI1_TXC__LPSPI1_SIN 0x01a0 0x0350 0x042c 0x02 0x01 +#define MX91_PAD_SAI1_TXC__LPUART1_DSR_B 0x01a0 0x0350 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_TXC__CAN1_RX 0x01a0 0x0350 0x0360 0x04 0x02 +#define MX91_PAD_SAI1_TXC__GPIO1_IO12 0x01a0 0x0350 0x0000 0x05 0x00 + +#define MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x01a4 0x0354 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01a4 0x0354 0x0000 0x01 0x00 +#define MX91_PAD_SAI1_TXD0__LPSPI1_SCK 0x01a4 0x0354 0x0428 0x02 0x01 +#define MX91_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01a4 0x0354 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_TXD0__CAN1_TX 0x01a4 0x0354 0x0000 0x04 0x00 +#define MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x01a4 0x0354 0x0000 0x05 0x00 +#define MX91_PAD_SAI1_TXD0__SAI1_MCLK 0x01a4 0x0354 0x04d4 0x06 0x01 + +#define MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x01a8 0x0358 0x0000 0x00 0x00 +#define MX91_PAD_SAI1_RXD0__SAI1_MCLK 0x01a8 0x0358 0x04d4 0x01 0x02 +#define MX91_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01a8 0x0358 0x0430 0x02 0x01 +#define MX91_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01a8 0x0358 0x0000 0x03 0x00 +#define MX91_PAD_SAI1_RXD0__MQS1_RIGHT 0x01a8 0x0358 0x0000 0x04 0x00 +#define MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x01a8 0x0358 0x0000 0x05 0x00 + +#define MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01ac 0x035c 0x0000 0x00 0x00 +#define MX91_PAD_WDOG_ANY__GPIO1_IO15 0x01ac 0x035c 0x0000 0x05 0x00 +#endif /* __DTS_IMX91_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/dts/freescale/imx91.dtsi new file mode 100644 index 000000000000..4d8300b2a7bc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +#include "imx91-pinfunc.h" +#include "imx91_93_common.dtsi" + +&clk { + compatible = "fsl,imx91-ccm"; +}; + +&ddr_pmu { + compatible = "fsl,imx91-ddr-pmu", "fsl,imx93-ddr-pmu"; +}; + +&eqos { + clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, + <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET1_QOS_TSN>, + <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>; + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET1_QOS_TSN>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; +}; + +&fec { + clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>, + <&clk IMX91_CLK_ENET2_REGULAR_GATE>, + <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET2_REGULAR>, + <&clk IMX93_CLK_DUMMY>; + assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, + <&clk IMX91_CLK_ENET2_REGULAR>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; + assigned-clock-rates = <100000000>, <250000000>; +}; + +&i3c1 { + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_DUMMY>; +}; + +&i3c2 { + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_DUMMY>; +}; + +&iomuxc { + compatible = "fsl,imx91-iomuxc"; +}; + +&media_blk_ctrl { + compatible = "fsl,imx91-media-blk-ctrl", "syscon"; + clocks = <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_NIC_MEDIA_GATE>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_CAM_PIX>, + <&clk IMX93_CLK_LCDIF_GATE>, + <&clk IMX93_CLK_ISI_GATE>, + <&clk IMX93_CLK_MIPI_CSI_GATE>; + clock-names = "apb", "axi", "nic", "disp", "cam", + "lcdif", "isi", "csi"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi index c48f3ecb91ed..52da571f26c4 100644 --- a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi @@ -1178,7 +1178,7 @@ memory-controller@4e300000 { little-endian; }; - ddr-pmu@4e300dc0 { + ddr_pmu: ddr-pmu@4e300dc0 { compatible = "fsl,imx93-ddr-pmu"; reg = <0x4e300dc0 0x200>; interrupts = ; From 6772c4cffd87f44ea4ea46d159e9feaeb418c3d0 Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Mon, 1 Sep 2025 18:36:30 +0800 Subject: [PATCH 653/931] arm64: dts: freescale: add i.MX91 11x11 EVK basic support Add i.MX91 11x11 EVK board support. - Enable ADC1. - Enable lpuart1 and lpuart5. - Enable network eqos and fec. - Enable I2C bus and children nodes under I2C bus. - Enable USB and related nodes. - Enable uSDHC1 and uSDHC2. - Enable Watchdog3. Reviewed-by: Frank Li Signed-off-by: Pengfei Li Signed-off-by: Joy Zou Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx91-11x11-evk.dts | 674 ++++++++++++++++++ 2 files changed, 675 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 5fd7e4b9529d..e29bd48734d5 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -339,6 +339,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts new file mode 100644 index 000000000000..aca78768dbd4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -0,0 +1,674 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include +#include "imx91.dtsi" + +/ { + compatible = "fsl,imx91-11x11-evk", "fsl,imx91"; + model = "NXP i.MX91 11X11 EVK board"; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "audio-pwr"; + gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x40000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&eqos { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + realtek,clkout-disable; + }; + }; +}; + +&fec { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + pinctrl-names = "default", "sleep"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + realtek,clkout-disable; + }; + }; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-names = "default"; + status = "okay"; + + audio_codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + DCVDD-supply = <®_audio_pwr>; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + inertial-meter@6a { + compatible = "st,lsm6dso"; + reg = <0x6a>; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio3>; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pcal6524>; + + regulators { + buck1: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2237500>; + regulator-min-microvolt = <650000>; + regulator-name = "BUCK1"; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK2"; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK4"; + }; + + buck5: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK5"; + }; + + buck6: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK6"; + }; + + ldo1: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + regulator-name = "LDO1"; + }; + + ldo4: LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; + regulator-name = "LDO4"; + }; + + ldo5: LDO5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "LDO5"; + }; + }; + }; + + adp5585: io-expander@34 { + compatible = "adi,adp5585-00", "adi,adp5585"; + reg = <0x34>; + #gpio-cells = <2>; + gpio-controller; + #pwm-cells = <3>; + gpio-reserved-ranges = <5 1>; + + exp-sel-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-low; + }; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio3>; + + typec1_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + ptn5110_2: tcpc@51 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x51>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio3>; + status = "okay"; + + typec2_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + }; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pcal6524>; + status = "okay"; + }; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + usb2_drd_sw: endpoint { + remote-endpoint = <&typec2_dr_sw>; + }; + }; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e + MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e + MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e + MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e + MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e + MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e + MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e + MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e + MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e + MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e + MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e + MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e + MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e + MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e + MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX91_PAD_DAP_TDI__LPUART5_RX 0x31e + MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e + MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e + MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e + MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e + MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e + MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e + MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + +}; From 0f75caf42baa7cb207573b8d82eedbbce8d4016b Mon Sep 17 00:00:00 2001 From: Joy Zou Date: Mon, 1 Sep 2025 18:36:31 +0800 Subject: [PATCH 654/931] arm64: dts: imx93-11x11-evk: remove fec property eee-broken-1000t The 'eee-broken-1000t' flag disables Energy-Efficient Ethernet (EEE) on 1G links as a workaround for PTP sync issues on older i.MX6 platforms. Remove it since the i.MX93 have not such issue. Reviewed-by: Frank Li Signed-off-by: Joy Zou Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index 44566e03be65..b94a24193e19 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -291,7 +291,6 @@ mdio { ethphy2: ethernet-phy@2 { reg = <2>; - eee-broken-1000t; reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; From e71db39f0c7c0157177be12de7ae2d2495184da1 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 1 Sep 2025 12:04:30 +0200 Subject: [PATCH 655/931] arm64: dts: freescale: add initial device tree for TQMa91xx/MBa91xxCA This adds support for TQMa91xx module attached to MBa91xxCA board. TQMa91xx is a SOM series using i.MX91 SOC. The SOM features PMIC, RAM, e-MMC and some optional peripherals like SPI-NOR, RTC, EEPROM, gyroscope and secure element. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx91-tqma9131-mba91xxca.dts | 739 ++++++++++++++++++ .../boot/dts/freescale/imx91-tqma9131.dtsi | 295 +++++++ 3 files changed, 1035 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts create mode 100644 arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index e29bd48734d5..86050b50d704 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -340,6 +340,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts b/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts new file mode 100644 index 000000000000..5c430e6fca65 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts @@ -0,0 +1,739 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + * Author: Alexander Stein + */ +/dts-v1/; + +#include +#include +#include +#include +#include +#include "imx91-tqma9131.dtsi" + +/{ + model = "TQ-Systems i.MX91 TQMa91xxLA/TQMa91xxCA on MBa91xxCA starter kit"; + compatible = "tq,imx91-tqma9131-mba91xxca", "tq,imx91-tqma9131", "fsl,imx91"; + chassis-type = "embedded"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + eeprom0 = &eeprom0; + ethernet0 = &eqos; + ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + serial1 = &lpuart2; + rtc0 = &pcf85063; + rtc1 = &bbnsm_rtc; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&tpm2 2 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_12v0>; + enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + display: display { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + power-supply = <®_3v3>; + enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + status = "disabled"; + + port { + panel_in: endpoint { + }; + }; + }; + + fan0: gpio-fan { + compatible = "gpio-fan"; + gpios = <&expander2 4 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0>, <10000 1>; + fan-supply = <®_12v0>; + #cooling-cells = <2>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + switch-a { + label = "switcha"; + linux,code = ; + gpios = <&expander0 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-b { + label = "switchb"; + linux,code = ; + gpios = <&expander0 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&expander2 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&expander2 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; + }; + + lvds_encoder: lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + powerdown-gpios = <&expander2 3 GPIO_ACTIVE_LOW>; + power-supply = <®_3v3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_encoder_input: endpoint { + }; + }; + + port@1 { + reg = <1>; + + lvds_encoder_output: endpoint { + }; + }; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "V_5V0_MB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "V_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mpcie_1v5: regulator-mpcie-1v5 { + compatible = "regulator-fixed"; + regulator-name = "V_1V5_MPCIE"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mpcie_3v3: regulator-mpcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MPCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + +&adc1 { + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_eqos>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy_eqos: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_phy>; + reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_fec>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy_fec: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + /* 00 */ "", "", "", "PMIC_IRQ#", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "USB_C_ALERT#", "BM2_LCD_INT#", + /* 12 */ "PEX_INT#", "", "RTC_EVENT#", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + /* 00 */ "", "", "", "", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_jtag>; + gpio-line-names = + /* 00 */ "SD2_CD#", "", "", "", + /* 04 */ "", "", "", "SD2_RST#", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "ENET1_INT#", "ENET2_INT#", + /* 28 */ "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* 00 */ "", "", "", "", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + temperature-sensor@1c { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1c>; + }; + + ptn5110: usb-typec@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + label = "X17"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + typec-power-opmode = "default"; + pd-disable; + self-powered; + + port { + typec_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + }; + }; + + eeprom2: eeprom@54 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x54>; + pagesize = <16>; + vcc-supply = <®_3v3>; + }; + + expander0: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pexp_irq>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_3v3>; + gpio-line-names = "TEMP_EVENT_MOD#", "MPCIE_WAKE#", + "MPCIE_1V5_EN", "MPCIE_3V3_EN", + "MPCIE_PERST#", "MPCIE_WDISABLE#", + "BUTTON_A#", "BUTTON_B#"; + + temp-event-mod-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_LOW>; + input; + line-name = "TEMP_EVENT_MOD#"; + }; + + mpcie-wake-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + input; + line-name = "MPCIE_WAKE#"; + }; + + /* + * Controls the mPCIE slot reset which is low active as + * reset signal. The output-low states, the signal is + * inactive, e.g. not in reset + */ + mpcie_rst_hog: mpcie-rst-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "MPCIE_PERST#"; + }; + + /* + * Controls the mPCIE slot WDISABLE pin which is low active + * as disable signal. The output-low states, the signal is + * inactive, e.g. not disabled + */ + mpcie_wdisable_hog: mpcie-wdisable-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "MPCIE_WDISABLE#"; + }; + }; + + expander1: gpio@71 { + compatible = "nxp,pca9538"; + reg = <0x71>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "ENET1_RESET#", "ENET2_RESET#", + "USB_RESET#", "", + "WLAN_PD#", "WLAN_W_DISABLE#", + "WLAN_PERST#", "12V_EN"; + + /* + * Controls the WiFi card PD pin which is low active + * as power down signal. The output-low states, the signal + * is inactive, e.g. not power down + */ + wlan-pd-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_PD#"; + }; + + /* + * Controls the WiFi card disable pin which is low active + * as disable signal. The output-low states, the signal + * is inactive, e.g. not disabled + */ + wlan-wdisable-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_W_DISABLE#"; + }; + + /* + * Controls the WiFi card reset pin which is low active + * as reset signal. The output-low states, the signal + * is inactive, e.g. not in reset + */ + wlan-perst-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_PERST#"; + }; + }; + + expander2: gpio@72 { + compatible = "nxp,pca9538"; + reg = <0x72>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "LCD_RESET#", "LCD_PWR_EN", + "LCD_BLT_EN", "LVDS_SHDN#", + "FAN_PWR_EN", "", + "USER_LED1", "USER_LED2"; + }; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&pcf85063 { + /* RTC_EVENT# from SoM is connected on mainboard */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf85063>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; +}; + +&se97_som { + /* TEMP_EVENT# from SoM is connected on mainboard */ + interrupt-parent = <&expander0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; +}; + +&tpm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + status = "okay"; + + port { + typec_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usbotg2 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + disable-over-current; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb424,2517"; + reg = <1>; + reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + no-sdio; + no-mmc; + disable-wp; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = /* PD | FSEL_2 | DSE X4 */ + , + /* SION | HYS | FSEL_2 | DSE X4 */ + , + /* HYS | FSEL_0 | DSE no drive */ + , + , + , + , + , + /* HYS | PD | FSEL_0 | DSE no drive */ + , + /* PD | FSEL_2 | DSE X4 */ + , + , + , + , + , + /* PD | FSEL_3 | DSE X3 */ + ; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = /* HYS | FSEL_0 | DSE no drive */ + ; + }; + + pinctrl_fec: fecgrp { + fsl,pins = /* PD | FSEL_2 | DSE X4 */ + , + /* SION | HYS | FSEL_2 | DSE X4 */ + , + /* HYS | FSEL_0 | DSE no drive */ + , + , + , + , + , + /* HYS | PD | FSEL_0 | DSE no drive */ + , + /* PD | FSEL_2 | DSE X4 */ + , + , + , + , + , + /* PD | FSEL_3 | DSE X3 */ + ; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = /* HYS | FSEL_0 | DSE no drive */ + ; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */ + , + /* PU | FSEL_3 | DSE X4 */ + ; + }; + + pinctrl_jtag: jtaggrp { + fsl,pins = , + , + , + ; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */ + , + ; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins = ; + }; + + pinctrl_pexp_irq: pexpirqgrp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + ; + }; + + pinctrl_rgbdisp: rgbdispgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_touch: touchgrp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + ; + }; + + pinctrl_tpm2: tpm2grp { + fsl,pins = ; + }; + + pinctrl_typec: typecgrp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + , + /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + , + /* FSEL_2 | DSE X4 */ + , + /* FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = /* HYS | FSEL_0 | No DSE */ + ; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_hs: usdhc2hsgrp { + fsl,pins = /* PD | FSEL_3 | DSE X5 */ + , + /* HYS | PU | FSEL_3 | DSE X4 */ + , + /* HYS | PU | FSEL_3 | DSE X3 */ + , + , + , + , + /* FSEL_2 | DSE X3 */ + ; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_uhs: usdhc2uhsgrp { + fsl,pins = /* PD | FSEL_3 | DSE X6 */ + , + /* HYS | PU | FSEL_3 | DSE X4 */ + , + , + , + , + , + /* FSEL_2 | DSE X3 */ + ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi b/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi new file mode 100644 index 000000000000..5792952b7a8e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + * Author: Alexander Stein + */ + +#include "imx91.dtsi" + +/{ + model = "TQ-Systems i.MX91 TQMa91xxCA / TQMa91xxLA SOM"; + compatible = "tq,imx91-tqma9131", "fsl,imx91"; + + memory@80000000 { + device_type = "memory"; + /* our minimum RAM config will be 1024 MiB */ + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* default CMA, must not exceed assembled memory */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + + /* EdgeLock secure enclave */ + ele_reserved: ele-reserved@a4120000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4120000 0 0x100000>; + no-map; + }; + }; + + /* SD2 RST# via PMIC SW_EN */ + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&buck4>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc1 { + vref-supply = <&buck5>; +}; + +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + /* + * no DQS, RXCLKSRC internal loop back, max 66 MHz + * clk framework uses CLK_DIVIDER_ROUND_CLOSEST + * selected value together with root from + * IMX91_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to + * respect the maximum value. + */ + spi-max-frequency = <62000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + vcc-supply = <&buck5>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + se97_som: temperature-sensor@1b { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pca9451a: pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9451>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* V_0V8_SOC - hw developer guide: 0.75 .. 0.9 */ + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* V_DDRQ - 1.1 V for LPDDR4 */ + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* V_3V3 - EEPROM, RTC, ... */ + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8 - SPI NOR, eMMC, RAM VDD1... */ + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V1 - RAM VDD2*/ + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_BBSM, fix 1.8 */ + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_0V8_ANA */ + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_SD2 - 3.3/1.8V USDHC2 io Voltage */ + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + eeprom0: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + read-only; + vcc-supply = <&buck4>; + }; + + eeprom1: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <&buck4>; + }; + + /* protectable identification memory (part of M24C64-D @57) */ + eeprom@5f { + compatible = "atmel,24c64d-wl"; + reg = <0x5f>; + vcc-supply = <&buck4>; + }; + + accelerometer@6a { + compatible = "st,ism330dhcx"; + reg = <0x6a>; + vdd-supply = <&buck4>; + vddio-supply = <&buck4>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + vmmc-supply = <&buck4>; + vqmmc-supply = <&buck5>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&wdog3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi1: flexspi1grp { + fsl,pins = /* FSEL 3 | DSE X6 */ + , + , + /* HYS | PU | FSEL 3 | DSE X6 */ + , + , + /* HYS | FSEL 3 | DSE X6 (external PU) */ + , + ; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = /* SION | OD | FSEL 3 | DSE X4 */ + , + ; + }; + + pinctrl_pca9451: pca9451grp { + fsl,pins = /* HYS | PU */ + ; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = /* FSEL 2 | DSE X2 */ + ; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = /* PD | FSEL 3 | DSE X5 */ + , + /* HYS | FSEL 0 | no drive */ + , + /* HYS | FSEL 3 | X5 */ + , + /* HYS | FSEL 3 | X4 */ + , + , + , + , + , + , + , + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = /* PU | FSEL 1 | DSE X4 */ + ; + }; +}; From 53f9271ed0de355a32e4d7a08b357d43e8222e08 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:19:54 -0400 Subject: [PATCH 656/931] ARM: dts: imx6: add #address-cells for gsc@20 Add #address-cells for gsc20 to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/imx/imx6dl-gw51xx.dtb: gsc@20 (gw,gsc): '#address-cells' is a required property Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi | 1 + 12 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi index e75e1a5364b8..c61e70469b66 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi @@ -156,6 +156,7 @@ gsc: gsc@20 { interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; #size-cells = <0>; adc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi index b57f4073f881..4f66271bf4a4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi @@ -230,6 +230,7 @@ gsc: gsc@20 { interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; #size-cells = <0>; adc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi index 090c0057d117..cdb40046bd7e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi @@ -223,6 +223,7 @@ gsc: gsc@20 { interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; #size-cells = <0>; adc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi index 009a9d56757c..4db5ef4a3e56 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi @@ -179,6 +179,7 @@ gsc: gsc@20 { interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; #size-cells = <0>; adc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi index 77ae611b817a..5d5ef18a0593 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi @@ -146,6 +146,7 @@ gsc: gsc@20 { interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; #size-cells = <0>; adc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi index e3b677384a22..a9dfa7cb69ef 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi @@ -142,6 +142,7 @@ gsc: gsc@20 { interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; #size-cells = <0>; adc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi index ce1d49a9e0cd..11483daa59fc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi @@ -254,6 +254,7 @@ gsc: gsc@20 { interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; #size-cells = <0>; adc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi index 50b484998c49..c48dd7d06bce 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi @@ -195,6 +195,7 @@ gsc: gsc@20 { interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; #size-cells = <0>; adc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi index 3125cd04d4ea..2d24f9bc4106 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi @@ -260,6 +260,7 @@ gsc: gsc@20 { interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; #size-cells = <0>; adc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi index 955a51226eda..e214a5f2f191 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi @@ -156,6 +156,7 @@ gsc: gsc@20 { interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; #size-cells = <0>; adc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi index 453dee4d9227..02bfec7af9f2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi @@ -165,6 +165,7 @@ gsc: gsc@20 { interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; #size-cells = <0>; adc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi index 82f47c295b08..0dc239d4975c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi @@ -141,6 +141,7 @@ gsc: gsc@20 { interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; #size-cells = <0>; adc { From 965661c7c52e36aa497fcdadc3ed478e19222f85 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:19:55 -0400 Subject: [PATCH 657/931] ARM: dts: imx6: add key- prefix for gpio-keys Add key- prefix for gpio-keys and rename button_0 to button-0 to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/imx/imx6q-gw51xx.dtb: gpio-keys (gpio-keys): 'eeprom-wp', ... do not match any of the regexes: '^(button|...))$', 'pinctrl-[0-9]+ Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi | 4 ++-- arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi | 12 ++++++------ .../arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi | 12 ++++++------ arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi | 12 ++++++------ .../dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi | 4 ++-- arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi | 10 +++++----- arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi | 12 ++++++------ arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi | 6 +++--- arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi | 4 ++-- .../dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx7s-warp.dts | 2 +- 31 files changed, 116 insertions(+), 116 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi index 41d073f5bfe7..c504cf7e9492 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-cubox-i.dtsi @@ -118,7 +118,7 @@ gpio-keys { pinctrl-0 = <&pinctrl_gpio_key>; pinctrl-names = "default"; - button_0 { + button-0 { label = "Button 0"; gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi index 97763db3959f..6fb873c2983f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi @@ -33,7 +33,7 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emcon_wake>; - wake { + key-wake { label = "Wake"; linux,code = ; gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi index c61e70469b66..d92d26e40a1c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi @@ -24,13 +24,13 @@ chosen { gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -44,21 +44,21 @@ key-erased { interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <5>; }; - switch-hold { + key-switch-hold { label = "switch_hold"; linux,code = ; interrupt-parent = <&gsc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi index 4f66271bf4a4..c1d124ad1d66 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi @@ -33,13 +33,13 @@ backlight { gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -53,21 +53,21 @@ key-erased { interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <5>; }; - switch-hold { + key-switch-hold { label = "switch_hold"; linux,code = ; interrupt-parent = <&gsc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi index cdb40046bd7e..63e604537b06 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi @@ -33,13 +33,13 @@ backlight { gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -53,21 +53,21 @@ key-erased { interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <5>; }; - switch-hold { + key-switch-hold { label = "switch_hold"; linux,code = ; interrupt-parent = <&gsc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi index 94f1d1ae59aa..66a7b3e03fa1 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi @@ -34,13 +34,13 @@ backlight { gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -54,21 +54,21 @@ key-erased { interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <5>; }; - switch-hold { + key-switch-hold { label = "switch_hold"; linux,code = ; interrupt-parent = <&gsc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi index 4db5ef4a3e56..07cb36e65df7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi @@ -26,13 +26,13 @@ chosen { gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -46,21 +46,21 @@ key-erased { interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <5>; }; - switch-hold { + key-switch-hold { label = "switch_hold"; linux,code = ; interrupt-parent = <&gsc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi index 5d5ef18a0593..f152ebbd203d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi @@ -25,13 +25,13 @@ chosen { gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -45,21 +45,21 @@ key-erased { interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <5>; }; - switch-hold { + key-switch-hold { label = "switch_hold"; linux,code = ; interrupt-parent = <&gsc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi index a9dfa7cb69ef..aef920c192b5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi @@ -24,13 +24,13 @@ chosen { gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -44,21 +44,21 @@ key-erased { interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <5>; }; - switch-hold { + key-switch-hold { label = "switch_hold"; linux,code = ; interrupt-parent = <&gsc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi index 11483daa59fc..ea92b2b5c50d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi @@ -50,13 +50,13 @@ backlight-keypad { gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -70,21 +70,21 @@ key-erased { interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <5>; }; - switch-hold { + key-switch-hold { label = "switch_hold"; linux,code = ; interrupt-parent = <&gsc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi index c48dd7d06bce..b518bcb6b7a9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi @@ -34,13 +34,13 @@ backlight { gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -54,21 +54,21 @@ key-erased { interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <5>; }; - switch-hold { + key-switch-hold { label = "switch_hold"; linux,code = ; interrupt-parent = <&gsc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi index 2d24f9bc4106..3df4d345da98 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi @@ -36,13 +36,13 @@ backlight { gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -56,21 +56,21 @@ key-erased { interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <5>; }; - switch-hold { + key-switch-hold { label = "switch_hold"; linux,code = ; interrupt-parent = <&gsc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi index e214a5f2f191..b73a170940a0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi @@ -24,13 +24,13 @@ chosen { gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -44,21 +44,21 @@ key-erased { interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <5>; }; - switch-hold { + key-switch-hold { label = "switch_hold"; linux,code = ; interrupt-parent = <&gsc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi index 02bfec7af9f2..099ed2f94d61 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5910.dtsi @@ -27,13 +27,13 @@ memory@10000000 { gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -47,21 +47,21 @@ key-erased { interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <5>; }; - switch-hold { + key-switch-hold { label = "switch_hold"; linux,code = ; interrupt-parent = <&gsc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi index add700bc11cc..cbca5e58e812 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5912.dtsi @@ -25,13 +25,13 @@ chosen { gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -45,21 +45,21 @@ key-erased { interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <5>; }; - switch-hold { + key-switch-hold { label = "switch_hold"; linux,code = ; interrupt-parent = <&gsc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi index 0dc239d4975c..4e4dce5adc15 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5913.dtsi @@ -24,13 +24,13 @@ chosen { gpio-keys { compatible = "gpio-keys"; - user-pb { + key-user-pb { label = "user_pb"; gpios = <&gsc_gpio 2 GPIO_ACTIVE_LOW>; linux,code = ; }; - user-pb1x { + key-user-pb1x { label = "user_pb1x"; linux,code = ; interrupt-parent = <&gsc>; @@ -44,21 +44,21 @@ key-erased { interrupts = <1>; }; - eeprom-wp { + key-eeprom-wp { label = "eeprom_wp"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <2>; }; - tamper { + key-tamper { label = "tamper"; linux,code = ; interrupt-parent = <&gsc>; interrupts = <5>; }; - switch-hold { + key-switch-hold { label = "switch_hold"; linux,code = ; interrupt-parent = <&gsc>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi index 8ee65f9858c0..8d471450d5c5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi @@ -57,13 +57,13 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - home { + key-home { label = "Home"; gpios = <&gpio7 13 IRQ_TYPE_LEVEL_LOW>; linux,code = <102>; }; - back { + key-back { label = "Back"; gpios = <&gpio4 5 IRQ_TYPE_LEVEL_LOW>; linux,code = <158>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi index 43d474bbf55d..a096f4d985e7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi @@ -86,38 +86,38 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - power { + key-power { label = "Power Button"; gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; }; - menu { + key-menu { label = "Menu"; gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; linux,code = ; }; - home { + key-home { label = "Home"; gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; linux,code = ; }; - back { + key-back { label = "Back"; gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; linux,code = ; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; linux,code = ; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi index 8e64314fa8b2..806af7f60419 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi @@ -47,38 +47,38 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - power { + key-power { label = "Power Button"; gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; }; - menu { + key-menu { label = "Menu"; gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; linux,code = ; }; - home { + key-home { label = "Home"; gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; linux,code = ; }; - back { + key-back { label = "Back"; gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; linux,code = ; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; linux,code = ; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi index 8a0bfc387a59..c71aa7498acf 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi @@ -80,38 +80,38 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - power { + key-power { label = "Power Button"; gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; }; - menu { + key-menu { label = "Menu"; gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; linux,code = ; }; - home { + key-home { label = "Home"; gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; linux,code = ; }; - back { + key-back { label = "Back"; gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; linux,code = ; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; linux,code = ; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi index 037b60197598..060d2aeb1baf 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi @@ -13,14 +13,14 @@ gpio-keys { pinctrl-0 = <&pinctrl_gpio_keys>; status = "disabled"; - power { + key-power { label = "Power Button"; gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; }; - sleep { + key-sleep { label = "Sleep Button"; gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi index 2587d17c5918..b9dde0af3b99 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi @@ -32,35 +32,35 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - home { + key-home { label = "Home"; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; }; - back { + key-back { label = "Back"; gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; }; - program { + key-program { label = "Program"; gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio5 14 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi index bdef7e642d3c..f7abc17c7c93 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi @@ -108,38 +108,38 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - power { + key-power { label = "Power Button"; gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; }; - menu { + key-menu { label = "Menu"; gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; linux,code = ; }; - home { + key-home { label = "Home"; gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; linux,code = ; }; - back { + key-back { label = "Back"; gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; linux,code = ; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; linux,code = ; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi index 960e83f5e904..e8368c6b27ef 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi @@ -71,21 +71,21 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - power { + key-power { label = "Power Button"; gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; wakeup-source; linux,code = ; }; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; wakeup-source; linux,code = ; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; wakeup-source; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi index 6823a639ed2f..2daf2b6af884 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-savageboard.dtsi @@ -58,7 +58,7 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - power { + key-power { gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; label = "Power Button"; linux,code = ; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi index 2bb5b762c984..57297d6521cf 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi @@ -44,7 +44,7 @@ mclk: clock { gpio-keys { compatible = "gpio-keys"; - power { + key-power { label = "Power Button"; gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; linux,code = ; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi index 67cf09e63a63..c7aeb99d8f00 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi @@ -33,14 +33,14 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - volume-up { + key-volume-up { label = "Volume Up"; gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; }; - volume-down { + key-volume-down { label = "Volume Down"; gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi index 2f3fd32a1167..d4d6ce975639 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi @@ -13,7 +13,7 @@ gpio_keys: gpio-keys { pinctrl-0 = <&pinctrl_gpio_keys>; status = "disabled"; - power { + key-power { label = "Power Button"; gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtsi index de4dc7c1a03a..e75dad0f0e23 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtsi @@ -13,7 +13,7 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_snvs_gpiokeys>; - power { + key-power { label = "Wake-Up"; gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; linux,code = ; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dtsi index f52f8b5ad8a6..bce6fbf230b3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri-iris.dtsi @@ -13,7 +13,7 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_snvs_gpiokeys>; - power { + key-power { label = "Wake-Up"; gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; linux,code = ; diff --git a/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts b/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts index f2cd95e992e7..56dedd4fb8f0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7s-warp.dts @@ -23,7 +23,7 @@ gpio-keys { pinctrl-0 = <&pinctrl_gpio>; autorepeat; - back { + key-back { label = "Back"; gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; linux,code = ; From 5a5d4c5cc54ddb89c93c4ba612a2d7be943b1471 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:19:56 -0400 Subject: [PATCH 658/931] ARM: dts: imx6: align rtc chip node name to 'rtc' Rename node name ds1672 to rtc to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/imx/imx6dl-gw51xx.dtb: ds1672@68 (dallas,ds1672): $nodename:0: 'ds1672@68' does not match '^rtc(@.*|-([0-9]|[1-9][0-9]+))?$ Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx35-eukrea-cpuimx35.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx51-eukrea-cpuimx51.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6q-h100.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6q-novena.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/nxp/imx/imx35-eukrea-cpuimx35.dtsi index ef546525e2ec..0064b5452b54 100644 --- a/arch/arm/boot/dts/nxp/imx/imx35-eukrea-cpuimx35.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx35-eukrea-cpuimx35.dtsi @@ -26,7 +26,7 @@ &i2c1 { pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pcf8563@51 { + rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/nxp/imx/imx51-eukrea-cpuimx51.dtsi index 0a150c91d30f..244740d65b3d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-eukrea-cpuimx51.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx51-eukrea-cpuimx51.dtsi @@ -26,7 +26,7 @@ &i2c1 { pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - pcf8563@51 { + rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi index de80ca141bca..7a3b96315eaf 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi @@ -157,7 +157,7 @@ &i2c3 { sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; - rtc: m41t62@68 { + rtc: rtc@68 { compatible = "st,m41t62"; reg = <0x68>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts index c5525b2c1dbd..17fabff80e90 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts @@ -266,7 +266,7 @@ temp2: ad7414@4d { reg = <0x4d>; }; - rtc: m41t62@68 { + rtc: rtc@68 { compatible = "st,m41t62"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts index c5c144879fa6..bf8fde9cb38d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts @@ -184,7 +184,7 @@ gpio: pca9555@23 { #gpio-cells = <2>; }; - rtc: ds1672@68 { + rtc: rtc@68 { compatible = "dallas,ds1672"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-h100.dts b/arch/arm/boot/dts/nxp/imx/imx6q-h100.dts index 46e011a363e8..4c8ea4381559 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-h100.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-h100.dts @@ -171,7 +171,7 @@ eeprom: eeprom@51 { reg = <0x51>; }; - rtc: pcf8523@68 { + rtc: rtc@68 { compatible = "nxp,pcf8523"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts b/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts index 8c3a9ea8d5b3..4d25090db55f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts @@ -265,7 +265,7 @@ accel: mma8452@1c { reg = <0x1c>; }; - rtc: pcf8523@68 { + rtc: rtc@68 { compatible = "nxp,pcf8523"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi index d92d26e40a1c..beff5a0f58ab 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi @@ -271,7 +271,7 @@ eeprom4: eeprom@53 { pagesize = <16>; }; - rtc: ds1672@68 { + rtc: rtc@68 { compatible = "dallas,ds1672"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi index c1d124ad1d66..9d3ba4083216 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi @@ -351,7 +351,7 @@ eeprom4: eeprom@53 { pagesize = <16>; }; - rtc: ds1672@68 { + rtc: rtc@68 { compatible = "dallas,ds1672"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi index 63e604537b06..7e84e0a52ef3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi @@ -350,7 +350,7 @@ eeprom4: eeprom@53 { pagesize = <16>; }; - rtc: ds1672@68 { + rtc: rtc@68 { compatible = "dallas,ds1672"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi index 66a7b3e03fa1..81394d47dd68 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi @@ -376,7 +376,7 @@ eeprom4: eeprom@53 { pagesize = <16>; }; - rtc: ds1672@68 { + rtc: rtc@68 { compatible = "dallas,ds1672"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi index 07cb36e65df7..6136a95b9259 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi @@ -288,7 +288,7 @@ eeprom4: eeprom@53 { pagesize = <16>; }; - rtc: ds1672@68 { + rtc: rtc@68 { compatible = "dallas,ds1672"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi index f152ebbd203d..9c822ca23130 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi @@ -261,7 +261,7 @@ eeprom4: eeprom@53 { pagesize = <16>; }; - rtc: ds1672@68 { + rtc: rtc@68 { compatible = "dallas,ds1672"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi index aef920c192b5..552114a69f5b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi @@ -257,7 +257,7 @@ eeprom4: eeprom@53 { pagesize = <16>; }; - rtc: ds1672@68 { + rtc: rtc@68 { compatible = "dallas,ds1672"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi index b73a170940a0..87fdc9e2a727 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5907.dtsi @@ -271,7 +271,7 @@ eeprom@53 { pagesize = <16>; }; - ds1672@68 { + rtc@68 { compatible = "dallas,ds1672"; reg = <0x68>; }; From 220ee5c4c89c6964358ab889e2e4a298f1049a57 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:19:57 -0400 Subject: [PATCH 659/931] ARM: dts: imx6: add interrupt-cells for dlg,da9063 pmic Add interrupt-cells for pmic to fix below CHECK_DTBS warnings: arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dtb: pmic@58 (dlg,da9063): 'interrupt-controller' is a required property from schema $id: http://devicetree.org/schemas/mfd/dlg,da9063.yaml Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi | 2 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi | 2 ++ arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi index d77472519086..53013b12c2ec 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi @@ -222,6 +222,8 @@ pmic@58 { pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio7>; interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; onkey { compatible = "dlg,da9063-onkey"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi index 57970f29367d..828af3ac5576 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi @@ -114,6 +114,8 @@ pmic@58 { reg = <0x58>; interrupt-parent = <&gpio1>; interrupts = <04 0x8>; + #interrupt-cells = <2>; + interrupt-controller; regulators { bcore1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi index 6fb873c2983f..9f4e746beb2d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi @@ -225,6 +225,8 @@ da9063: pmic@58 { pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio2>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; onkey { compatible = "dlg,da9063-onkey"; From e2de44e6f245e03c417e5f5527a79f90be203be2 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:19:58 -0400 Subject: [PATCH 660/931] ARM: dts: imx6qdl-aristainetos2: rename ethernet-phy to ethernet-phy@0 Rename ethernet-phy to ethernet-phy@0 to fix below CHECK_DTB warnings: arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dtb: ethernet@2188000 (fsl,imx6q-fec): mdio: Unevaluated properties are not allowed ('ethernet-phy' was unexpected) Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi index 828af3ac5576..01d4ea20b13d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi @@ -290,8 +290,9 @@ mdio { #address-cells = <1>; #size-cells = <0>; - ethphy: ethernet-phy { + ethphy: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; txd0-skew-ps = <0>; txd1-skew-ps = <0>; txd2-skew-ps = <0>; From f0b73936217487c36e4c2188db6aae457142393b Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:19:59 -0400 Subject: [PATCH 661/931] ARM: dts: imx6: remove redundant pinctrl-names Remove redundant pinctrl-name because no pinctrl-0 existed to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-hummingboard.dtb: pwm@2084000 (fsl,imx6q-pwm): 'pinctrl-0' is a dependency of 'pinctrl-names' from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-consumer.yaml# Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts | 1 - arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts | 2 -- arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts | 2 -- arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi | 1 - arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi | 2 -- arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1.dtsi | 1 - arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi | 2 -- 7 files changed, 11 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts index 0b1275a8891f..2160b7177835 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-prtmvt.dts @@ -557,7 +557,6 @@ &uart5 { &usbh1 { vbus-supply = <®_h1_vbus>; - pinctrl-names = "default"; phy_type = "utmi"; dr_mode = "host"; disable-over-current; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts index e9ac4768f36c..55b7e91d2ac0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts @@ -389,8 +389,6 @@ &usdhc4 { }; &iomuxc { - pinctrl-names = "default"; - pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts index bba82126aaaa..ef5c0eda8b15 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-mccmon6.dts @@ -292,8 +292,6 @@ flash@0,0 { }; &iomuxc { - pinctrl-names = "default"; - pinctrl_backlight: dispgrp { fsl,pins = < /* BLEN_OUT */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi index 54d4bced2395..6b737360a532 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-hummingboard.dtsi @@ -332,7 +332,6 @@ &pwm1 { }; &pwm2 { - pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi index 64ded5e5559c..22d5918ee4d8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi @@ -23,7 +23,6 @@ reg_3p3v: regulator-3p3v { reg_usbh1_vbus: regulator-usbh1-vbus { compatible = "regulator-fixed"; - pinctrl-names = "default"; regulator-name = "usbh1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -33,7 +32,6 @@ reg_usbh1_vbus: regulator-usbh1-vbus { reg_usb_otg_vbus: regulator-otg-vbus { compatible = "regulator-fixed"; - pinctrl-names = "default"; regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1.dtsi index 96e4f4b0b248..de2b12dad7d8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-vicut1.dtsi @@ -429,7 +429,6 @@ &uart5 { }; &usbh1 { - pinctrl-names = "default"; phy_type = "utmi"; dr_mode = "host"; disable-over-current; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi index 911ccbd132cf..17989e6d82e6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi @@ -421,8 +421,6 @@ &wdog1 { }; &iomuxc { - pinctrl-names = "default"; - pinctrl_camera_clock: cameraclockgrp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 From 5058aa3d4d60e3033e6e3d628ea98066f3900e32 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:20:00 -0400 Subject: [PATCH 662/931] ARM: dts: imx6: rename touch screen's node name to touchscreen Rename touch to touchscreen. Rename stmpe_touchscreen to touchscreen. Rename stmpe_adc to adc. Fix below CHECK_DTBS warning: arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dtb: touch@48 (ti,tsc2004): 'wakeup-gpios' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/input/touchscreen/ti,tsc2005.yaml# Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6q-novena.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi | 4 ++-- arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-av-02.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts | 2 +- 7 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi index df543b4751e0..89b17509ad48 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi @@ -47,7 +47,7 @@ touchscreen@41 { interrupt-parent = <&gpio7>; irq-trigger = <0x1>; - stmpe_touchscreen { + touchscreen { compatible = "st,stmpe-ts"; st,sample-time = <4>; st,mod-12b = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts b/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts index 4d25090db55f..24fc3ff1c70c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts @@ -288,7 +288,7 @@ touch: stmpe811@44 { vio-supply = <®_3p3v>; vcc-supply = <®_3p3v>; - stmpe_touchscreen { + touchscreen { compatible = "st,stmpe-ts"; st,sample-time = <4>; st,mod-12b = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi index b13000a62a7b..5fcd7cdb7001 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi @@ -648,7 +648,7 @@ stmpe811@41 { /* ADC conversion time: 80 clocks */ st,sample-time = <4>; - stmpe_ts: stmpe_touchscreen { + stmpe_ts: touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ st,ave-ctrl = <3>; @@ -665,7 +665,7 @@ stmpe_ts: stmpe_touchscreen { st,touch-det-delay = <5>; }; - stmpe_adc: stmpe_adc { + stmpe_adc: adc { compatible = "st,stmpe-adc"; #io-channel-cells = <1>; /* forbid to use ADC channels 3-0 (touch) */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi index 3525cbcda57f..419d85b5a660 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi @@ -572,7 +572,7 @@ stmpe811@41 { /* ADC converstion time: 80 clocks */ st,sample-time = <4>; - stmpe_ts: stmpe_touchscreen { + stmpe_ts: touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ st,ave-ctrl = <3>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi index 0b4c09b09c03..a3c2811e9c6f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi @@ -162,7 +162,7 @@ stmpe: touchctrl@44 { interrupts = <12 IRQ_TYPE_NONE>; status = "disabled"; - stmpe_touchscreen { + touchscreen { compatible = "st,stmpe-ts"; st,sample-time = <4>; st,mod-12b = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-av-02.dtsi index ec042648bd98..c6064f4c679b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-av-02.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-av-02.dtsi @@ -61,7 +61,7 @@ stmpe: touchscreen@44 { wakeup-source; status = "disabled"; - stmpe_touchscreen { + touchscreen { compatible = "st,stmpe-ts"; st,sample-time = <4>; st,mod-12b = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts b/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts index 7ee66be8bccb..7acd28658e6f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-nitrogen7.dts @@ -270,7 +270,7 @@ &i2c3 { pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - touch@48 { + touchscreen@48 { compatible = "ti,tsc2004"; reg = <0x48>; pinctrl-names = "default"; From 68979d311a55a68c88203e21c5720203cc4111bc Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:20:01 -0400 Subject: [PATCH 663/931] ARM: dts: imx6: rename node i2c-gpio to i2c. Rename node name i2c-gpio to i2c to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-0010.dtb: / (karo,imx6ul-tx6ul): i2c-gpio: {'compatible': ['i2c-gpio'], '#address-cells': 1, '#size-cells': 0, 'pinctrl-names': ['default'], 'pinctrl-0': [[68]], 'sda-gpios': [[46, 1, 0]], 'scl-gpios': [[46, 0, 0]], 'clock-frequency': 400000, 'status': ['okay'], 'rtc@68': {'compatible': ['dallas,ds1339'], 'reg': [[104]], 'status': ['disabled']}} is not of type 'array' from schema $id: http://devicetree.org/schemas/gpio/gpio-consumer.yaml# Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi index 5c7e9556b5ce..1992dfb53b45 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi @@ -72,7 +72,7 @@ backlight: backlight { default-brightness-level = <50>; }; - i2c_gpio: i2c-gpio { + i2c_gpio: i2c { compatible = "i2c-gpio"; #address-cells = <1>; #size-cells = <0>; From 9538e88f185fbc037e54827dbec1ea3edbc0c325 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:20:02 -0400 Subject: [PATCH 664/931] ARM: dts: imx6: rename node name flash to eeprom Rename node name flash to eeprom to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6q-b450v3.dtb: flash@0 (atmel,at25): $nodename: 'anyOf' conditional failed, one must be fixed: 'flash@0' does not match '^eeprom@[0-9a-f]{1,2}$' 'flash@0' does not match '^fram@[0-9a-f]{1,2}$' Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi index aa1adcc74019..e1d0c6e123fd 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi @@ -160,7 +160,7 @@ &ecspi5 { pinctrl-0 = <&pinctrl_ecspi5>; status = "okay"; - m25_eeprom: flash@0 { + m25_eeprom: eeprom@0 { compatible = "atmel,at25"; spi-max-frequency = <10000000>; size = <0x8000>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts index d2d0a82ea178..484a60892229 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts @@ -47,7 +47,7 @@ &ecspi5 { pinctrl-0 = <&pinctrl_ecspi5>; status = "okay"; - m25_eeprom: flash@0 { + m25_eeprom: eeprom@0 { compatible = "atmel,at25256B", "atmel,at25"; spi-max-frequency = <20000000>; size = <0x8000>; From 688dc0342532464239de99197583ccc9f9d3c64c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:20:03 -0400 Subject: [PATCH 665/931] ARM: dts: imx6: rename i2cmux i2c-mux- Rename i2cmux i2c-mux- to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6q-nitrogen6_max.dtb: i2c2mux (i2c-mux-gpio): $nodename:0: 'i2c2mux' does not match '^(i2c-?)?mux' from schema $id: http://devicetree.org/schemas/i2c/i2c-mux-gpio.yaml Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts | 4 ++-- arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts index 4989e8d069a1..9bb36db131c2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-alti6p.dts @@ -25,7 +25,7 @@ clock_ksz8081: clock-ksz8081 { clock-output-names = "enet_ref_pad"; }; - i2c2-mux { + i2c-mux-2 { compatible = "i2c-mux"; i2c-parent = <&i2c2>; mux-controls = <&i2c_mux>; @@ -45,7 +45,7 @@ i2c@2 { }; }; - i2c4-mux { + i2c-mux-4 { compatible = "i2c-mux"; i2c-parent = <&i2c4>; mux-controls = <&i2c_mux>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi index a096f4d985e7..c727aac257f9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi @@ -124,7 +124,7 @@ key-volume-down { }; }; - i2c2mux { + i2c-mux-2 { compatible = "i2c-mux-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2mux>; @@ -148,7 +148,7 @@ i2c2mux@2 { }; }; - i2c3mux { + i2c-mux-3 { compatible = "i2c-mux-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3mux>; From 91c6d75db0c0fbadc70e0b423508440dcef00e6e Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:20:04 -0400 Subject: [PATCH 666/931] ARM: dts: imx6: replace gpio-key with gpio-keys compatible string Compatible string 'gpio-key' is not existed. Correct it to 'gpio-keys'. Fix below CHECK_DTBS warnings arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-ff-rdk-emmc.dtb: /gpio-keys: failed to match any schema with compatible: ['gpio-key'] Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi index d4d6ce975639..24c48cdd1797 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi @@ -8,7 +8,7 @@ / { gpio_keys: gpio-keys { - compatible = "gpio-key"; + compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; status = "disabled"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi index d12fb44aeb14..8ad09fd334f7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi @@ -15,7 +15,7 @@ aliases { }; gpio_keys: gpio-keys { - compatible = "gpio-key"; + compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; From 2039db627d348d7263ed7d507e502faf3a088525 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:20:05 -0400 Subject: [PATCH 667/931] ARM: dts: imx6: replace isl,isl12022 with isil,isl12022 for RTC The compatible string isl,isl12022 is typo, it should be isil,isl12022. Fix below CHECK_DTBS warning: arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dtb: /soc/bus@2100000/i2c@21a0000/rtc@6f: failed to match any schema with compatible: ['isl,isl12022'] Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi index 11c70431feec..2e8573dac39e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi @@ -218,7 +218,7 @@ m41t00s: rtc@68 { }; isl12022: rtc@6f { - compatible = "isl,isl12022"; + compatible = "isil,isl12022"; reg = <0x6f>; }; From ce2e4c237ddd75b689fb6a6e5fa39d514199a0e8 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:20:06 -0400 Subject: [PATCH 668/931] ARM: dts: imx6ul-14x14-evk: add regulator for ov5640 Add required power supply for ov5640. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtb: camera@3c (ovti,ov5640): 'AVDD-supply' is a required property from schema $id: http://devicetree.org/schemas/media/i2c/ovti,ov5640.yaml# Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- .../boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi index 17989e6d82e6..73c9cfbdba62 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi @@ -22,6 +22,26 @@ backlight_display: backlight-display { status = "okay"; }; + reg_1v5: regulator-1v5 { + compatible = "regulator-fixed"; + regulator-name = "1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_2v8: regulator-2v8 { + compatible = "regulator-fixed"; + regulator-name = "2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; reg_sd1_vmmc: regulator-sd1-vmmc { compatible = "regulator-fixed"; @@ -182,6 +202,9 @@ camera@3c { clock-names = "xclk"; powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>; + AVDD-supply = <®_2v8>; + DVDD-supply = <®_1v5>; + DOVDD-supply = <®_1v8>; port { ov5640_to_parallel: endpoint { From a863c9bffd00edd96610067377a648ce4eb30242 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:20:07 -0400 Subject: [PATCH 669/931] ARM: dts: imx6ul-pico: add power-supply for vxt,vl050-8048nt-c01 Add power-supply for vxt,vl050-8048nt-c01 to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dtb: panel (vxt,vl050-8048nt-c01): 'power-supply' is a required property Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi index fe307f49b9e5..9fa5225994e3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pico.dtsi @@ -76,6 +76,7 @@ reg_brcm: regulator-brcm { panel { compatible = "vxt,vl050-8048nt-c01"; backlight = <&backlight>; + power-supply = <®_3p3v>; port { panel_in: endpoint { From 25d1ef1cfbd230d782b15189963cfcc3286ece16 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:20:08 -0400 Subject: [PATCH 670/931] ARM: dts: imx6: remove undefined linux,default-trigger source Set gpio/off to none for linux,default-trigger. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-phytec-mira-rdk-nand.dtb: user-leds (gpio-leds): user-led1:linux,default-trigger: 'oneOf' conditional failed, one must be fixed: 'gpio' is not one of ['backlight', 'default-on', 'heartbeat', 'disk-activity', 'disk-read', 'disk-write', 'timer', 'pattern', 'audio-micmute', 'audio-mute', 'bluetooth-power', 'flash', 'kbd-capslock', 'mtd', 'nand-disk', 'netdev', 'none', 'rc-feedback', 'torch', 'usb-gadget', 'usb-host', 'usbport'] Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi | 4 ++-- arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi | 4 ++-- .../boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi | 6 +++--- arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts | 2 +- .../boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi | 4 ++-- arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi index ebbd4d93e460..543cf723008f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53-kp.dtsi @@ -42,14 +42,14 @@ leds { led-bus { label = "bus"; gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; + linux,default-trigger = "none"; default-state = "off"; }; led-error { label = "error"; gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; + linux,default-trigger = "none"; default-state = "off"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi index c425d427663d..d6deb8c22b8c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-kp.dtsi @@ -69,14 +69,14 @@ leds { led-green { label = "led1"; gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; + linux,default-trigger = "none"; default-state = "off"; }; led-red { label = "led0"; gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; + linux,default-trigger = "none"; default-state = "off"; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi index 060d2aeb1baf..fc78acc9f5c5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-eval-01.dtsi @@ -35,19 +35,19 @@ user_leds: user-leds { user-led1 { gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; + linux,default-trigger = "none"; default-state = "on"; }; user-led2 { gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; + linux,default-trigger = "none"; default-state = "on"; }; user-led3 { gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; + linux,default-trigger = "none"; default-state = "on"; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts index 56040da0bd25..b6c336e3079e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts @@ -84,7 +84,7 @@ led-0 { led-1 { label = "tolinoshine2hd:white:backlightboost"; gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "off"; + linux,default-trigger = "none"; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi index 24c48cdd1797..113485e3397a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-segin-peb-eval-01.dtsi @@ -29,13 +29,13 @@ user_leds: user-leds { user-led1 { gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; + linux,default-trigger = "none"; default-state = "on"; }; user-led2 { gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; + linux,default-trigger = "none"; default-state = "on"; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi index 8ad09fd334f7..7ee25b141627 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-phytec-tauri.dtsi @@ -79,13 +79,13 @@ user_leds: user-leds { user-led1 { label = "yellow"; gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "off"; + linux,default-trigger = "none"; }; user-led2 { label = "red"; gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "off"; + linux,default-trigger = "none"; }; }; }; From 419f47b88d72ba8e197707af4f41976f6508c16c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 3 Sep 2025 16:20:09 -0400 Subject: [PATCH 671/931] ARM: dts: imx6: change rtc compatible string to st,m41t00 from m41t00 m41t00 compatible is not existing. Change it to st,m41t00 to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-ts7970.dtb: /soc/bus@2100000/i2c@21a0000/rtc@68: failed to match any schema with compatible: ['m41t00'] Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi index 2e8573dac39e..17f6a568f0e8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi @@ -213,7 +213,7 @@ &i2c1 { status = "okay"; m41t00s: rtc@68 { - compatible = "m41t00"; + compatible = "st,m41t00"; reg = <0x68>; }; From cf0713875422df28f9e76b4410fede952ebad898 Mon Sep 17 00:00:00 2001 From: Wei Fang Date: Thu, 4 Sep 2025 10:00:49 +0800 Subject: [PATCH 672/931] arm64: dts: imx95: add standard PCI device compatible string to NETC Timer PCI devices should have a compatible string based on the vendor and device IDs. So add this compatible string to NETC Timer. Signed-off-by: Wei Fang Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index ec61d27352e3..d737fa6aca4b 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -2110,6 +2110,7 @@ enetc_port2: ethernet@10,0 { }; netc_timer: ethernet@18,0 { + compatible = "pci1131,ee02"; reg = <0x00c000 0 0 0 0>; status = "disabled"; }; From 463714763fd1887a6538470132ba51a1a04e8ec2 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Fri, 5 Sep 2025 08:55:03 +0200 Subject: [PATCH 673/931] arm64: dts: freescale: imx93-phyboard-nash: Current sense via iio-hwmon Commit 21179eae56de ("arm64: dts: freescale: imx93-phyboard-nash: Add current sense amplifier") added information about the current sensing circuitry found on the board. Now, lets provide current sense reading also via IIO-hwmon subsystem. This way, SoM current can be read directly via sysfs property more conveniently for the customers. No need for them to manually apply scaling factor calculations anymore. Signed-off-by: Primoz Fiser Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts index 3f9efa32cddc..5599e296919f 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts +++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts @@ -48,8 +48,9 @@ chosen { stdout-path = &lpuart1; }; - current-sense { + curr_sens: current-sense { compatible = "current-sense-amplifier"; + #io-channel-cells = <0>; io-channels = <&adc1 1>; sense-gain-div = <2>; sense-gain-mult = <50>; @@ -65,6 +66,11 @@ flexcan1_tc: can-phy0 { standby-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&curr_sens 0>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; From c56b0b3c2465aeef72348272d7bec786c27619ad Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 8 Sep 2025 13:44:31 -0300 Subject: [PATCH 674/931] ARM: dts: imx6sll: Use 'dma-names' 'dma-name' is not a valid property and causes the following dt-schema warning: dma-name: b'rx\x00tx\x00' is not of type 'object', 'integer', 'array', 'boolean', 'null' Fix it by using 'dma-names' instead. Signed-off-by: Fabio Estevam Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6sll.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi index 8c5ca4f9b87f..704870e8c10c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi @@ -309,7 +309,7 @@ uart3: serial@2034000 { reg = <0x02034000 0x4000>; interrupts = ; dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; - dma-name = "rx", "tx"; + dma-names = "rx", "tx"; clocks = <&clks IMX6SLL_CLK_UART3_IPG>, <&clks IMX6SLL_CLK_UART3_SERIAL>; clock-names = "ipg", "per"; From e0c1a76b8d5f765e6555d89964d0189156339075 Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Mon, 8 Sep 2025 13:17:05 +0200 Subject: [PATCH 675/931] arm64: dts: freescale: imx93-phycore-som: Remove "fsl,magic-packet" FEC WoL (Wake-on-Lan) functionality depends on using Ethernet PHY in IRQ mode. However, on phyCORE-i.MX93 SoM, polling mode is used instead for the FEC Ethernet PHY. Consequently, WoL is non-functional. Thus disable it by removing "fsl,magic-packet" property. This allows us to save some power during device suspend as PHY is not kept awake. Signed-off-by: Primoz Fiser Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi index 89552ae70660..3f069905cf0b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi @@ -67,7 +67,6 @@ &fec { pinctrl-0 = <&pinctrl_fec>; phy-mode = "rmii"; phy-handle = <ðphy1>; - fsl,magic-packet; assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, <&clk IMX93_CLK_ENET_REF>, <&clk IMX93_CLK_ENET_REF_PHY>; From 40ded2d12b5d999866c2bc4122683355bb17c831 Mon Sep 17 00:00:00 2001 From: Jan Remmet Date: Wed, 10 Sep 2025 08:17:39 +0200 Subject: [PATCH 676/931] arm64: dts: imx8mm-phycore-som: optimize drive strengh Reduce ENET pin drive strength from X6 to X4 to optimize signal quality and reduce potential signal integrity issues. Signed-off-by: Jan Remmet Reviewed-by: Teresa Remmet Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index 672baba4c8d0..921a7f58fd41 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -340,10 +340,10 @@ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x12 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x12 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x12 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x12 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 >; }; From 76e145f857e9dea47002f23965a21ea35caa8bbd Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Sat, 23 Aug 2025 17:28:21 +0300 Subject: [PATCH 677/931] dt-bindings: arm: fsl: Add bindings for SolidRun i.MX8MP SoM and boards Add bindings for SolidRun i.MX8M Plus System on Module based boards: - CuBox-M is a complete produc with enclosure including the SoM - HummingBoard Mate/Pro/Pulse/Ripple are evaluation boards with common design but different available interfaces. Signed-off-by: Josua Mayer Acked-by: Rob Herring (Arm) Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 8e48a34af890..b98efb7bf6ee 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1201,6 +1201,17 @@ properties: - const: polyhex,imx8mp-debix-som-a # Polyhex Debix SOM A - const: fsl,imx8mp + - description: SolidRun i.MX8MP SoM based boards + items: + - enum: + - solidrun,imx8mp-cubox-m # SolidRun i.MX8MP SoM on CuBox-M + - solidrun,imx8mp-hummingboard-mate # SolidRun i.MX8MP SoM on HummingBoard Mate + - solidrun,imx8mp-hummingboard-pro # SolidRun i.MX8MP SoM on HummingBoard Pro + - solidrun,imx8mp-hummingboard-pulse # SolidRun i.MX8MP SoM on HummingBoard Pulse + - solidrun,imx8mp-hummingboard-ripple # SolidRun i.MX8MP SoM on HummingBoard Ripple + - const: solidrun,imx8mp-sr-som + - const: fsl,imx8mp + - description: TechNexion EDM-G-IMX8M-PLUS SoM based boards items: - enum: From 0463d9d492dfc896f61fd6319688e02341fea772 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 27 Aug 2025 17:24:45 -0400 Subject: [PATCH 678/931] dt-bindings: fsl: fsl,imx7ulp-smc1: Allow clocks and clock-names Allow clocks and clock-names to match existed dts file. 'hsrun_divcore' should be 'hsrun-divcore'. But use '_' to keep old dts back compatible. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx7ulp-com.dtb: clock-controller@40410000 (fsl,imx7ulp-smc1): '#clock-cells', 'clock-names', 'clocks' do not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-pm.yaml# Signed-off-by: Frank Li Acked-by: Rob Herring (Arm) Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml index 3b26040f8f18..9d377e193c12 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml @@ -28,6 +28,14 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 2 + + clock-names: + items: + - const: divcore + - const: hsrun_divcore + required: - compatible - reg From f001225088b8736f55dd28a4616cdf1b1bdcdd2e Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 1 Sep 2025 12:04:29 +0200 Subject: [PATCH 679/931] dt-bindings: arm: fsl: add TQMa91xx SOM series TQMa91xx series is using NXP i.MX91 CPU on an LGA or socketable type board. MBa91xxCA is a starterkit base board for TQMa91xx on an adapter board. Reviewed-by: Frank Li Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b98efb7bf6ee..00cdf490b062 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1451,6 +1451,24 @@ properties: - fsl,imxrt1170-evk # i.MXRT1170 EVK Board - const: fsl,imxrt1170 + - description: + TQMa91xxLA and TQMa91xxCA are two series of feature compatible SOM + using NXP i.MX91 SOC in 11x11 mm package. + TQMa91xxLA is designed to be soldered on different carrier boards. + TQMa91xxCA is a compatible variant using board to board connectors. + All SOM and CPU variants use the same device tree hence only one + compatible is needed. Bootloader disables all features not present + in the assembled SOC. + MBa91xxCA mainboard can be used as starterkit for the SOM + soldered on an adapter board or for the connector variant + MBa91xxLA mainboard is a single board computer using the solderable + SOM variant + items: + - enum: + - tq,imx91-tqma9131-mba91xxca # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM on MBa91xxCA + - const: tq,imx91-tqma9131 # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM + - const: fsl,imx91 + - description: TQMa93xxLA and TQMa93xxCA are two series of feature compatible SOM using NXP i.MX93 SOC in 11x11 mm package. From 92f96706947e902fd9156cdcdd61c9a44b4b186c Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Wed, 3 Sep 2025 19:04:49 +0200 Subject: [PATCH 680/931] dt-bindings: soc: rockchip: add rk3588 csidphy grf syscon Add CSIDPHY GRF syscon compatible for the Rockchip RK3588. Acked-by: "Rob Herring (Arm)" Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-1-a4f340a7f0cf@collabora.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 1d0f35e26311..01641692418b 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -48,6 +48,7 @@ properties: - rockchip,rk3576-vop-grf - rockchip,rk3588-bigcore0-grf - rockchip,rk3588-bigcore1-grf + - rockchip,rk3588-csidphy-grf - rockchip,rk3588-dcphy-grf - rockchip,rk3588-hdptxphy-grf - rockchip,rk3588-ioc From 871b0391ccf3feb831e233ba3e972663c057b946 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Wed, 3 Sep 2025 19:04:55 +0200 Subject: [PATCH 681/931] arm64: dts: rockchip: add mipi csi-2 dphy nodes to rk3588 The Rockchip RK3588 features two MIPI CSI-2 DPHYs. Add the device tree nodes for them. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-7-a4f340a7f0cf@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 23a41c151c5d..e2500e31c434 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -621,6 +621,16 @@ php_grf: syscon@fd5b0000 { reg = <0x0 0xfd5b0000 0x0 0x1000>; }; + csidphy0_grf: syscon@fd5b4000 { + compatible = "rockchip,rk3588-csidphy-grf", "syscon"; + reg = <0x0 0xfd5b4000 0x0 0x1000>; + }; + + csidphy1_grf: syscon@fd5b5000 { + compatible = "rockchip,rk3588-csidphy-grf", "syscon"; + reg = <0x0 0xfd5b5000 0x0 0x1000>; + }; + pipe_phy0_grf: syscon@fd5bc000 { compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; reg = <0x0 0xfd5bc000 0x0 0x100>; @@ -3176,6 +3186,30 @@ mipidcphy1: phy@fedb0000 { status = "disabled"; }; + csi_dphy0: phy@fedc0000 { + compatible = "rockchip,rk3588-csi-dphy"; + reg = <0x0 0xfedc0000 0x0 0x8000>; + clocks = <&cru PCLK_CSIPHY0>; + clock-names = "pclk"; + #phy-cells = <0>; + resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>; + reset-names = "apb", "phy"; + rockchip,grf = <&csidphy0_grf>; + status = "disabled"; + }; + + csi_dphy1: phy@fedc8000 { + compatible = "rockchip,rk3588-csi-dphy"; + reg = <0x0 0xfedc8000 0x0 0x8000>; + clocks = <&cru PCLK_CSIPHY1>; + clock-names = "pclk"; + #phy-cells = <0>; + resets = <&cru SRST_P_CSIPHY1>, <&cru SRST_CSIPHY1>; + reset-names = "apb", "phy"; + rockchip,grf = <&csidphy1_grf>; + status = "disabled"; + }; + combphy0_ps: phy@fee00000 { compatible = "rockchip,rk3588-naneng-combphy"; reg = <0x0 0xfee00000 0x0 0x100>; From 843367c7ed196bd0806c8776cba108aaf6923b82 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Wed, 10 Sep 2025 15:54:51 +0200 Subject: [PATCH 682/931] arm64: dts: rockchip: Fix network on rk3576 evb1 board The RK3576 EVB1 has a RTL8211F PHY for each GMAC interface with a dedicated reset line and the 25MHz clock provided by the SoC. The current description results in non-working Ethernet as the clocks are only enabled by the PHY driver, but probing the right PHY driver currently requires that the PHY ID register can be read for automatic identification. This fixes up the network description to get the network functionality working reliably and cleans up usage of deprecated DT properties while at it. Fixes: f135a1a07352 ("arm64: dts: rockchip: Add rk3576 evb1 board") Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20250910-rk3576-evb-network-v1-1-68ed4df272a2@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3576-evb1-v10.dts | 38 ++++++++++++++----- 1 file changed, 28 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index 439831715cbb..db8fef7a4f1b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -275,9 +275,6 @@ ð0m0_rx_bus2 ð0m0_rgmii_clk ð0m0_rgmii_bus ðm0_clk0_25m_out>; - snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 20000 100000>; tx_delay = <0x21>; status = "okay"; }; @@ -293,9 +290,6 @@ ð1m0_rx_bus2 ð1m0_rgmii_clk ð1m0_rgmii_bus ðm0_clk1_25m_out>; - snps,reset-gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 20000 100000>; tx_delay = <0x20>; status = "okay"; }; @@ -715,18 +709,32 @@ hym8563: rtc@51 { }; &mdio0 { - rgmii_phy0: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; reg = <0x1>; clocks = <&cru REFCLKO25M_GMAC0_OUT>; + assigned-clocks = <&cru REFCLKO25M_GMAC0_OUT>; + assigned-clock-rates = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_phy0_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; }; }; &mdio1 { - rgmii_phy1: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; reg = <0x1>; clocks = <&cru REFCLKO25M_GMAC1_OUT>; + assigned-clocks = <&cru REFCLKO25M_GMAC1_OUT>; + assigned-clock-rates = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_phy1_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; }; }; @@ -786,6 +794,16 @@ rtc_int: rtc-int { }; }; + network { + rgmii_phy0_rst: rgmii-phy0-rst { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + rgmii_phy1_rst: rgmii-phy1-rst { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pcie0 { pcie0_rst: pcie0-rst { rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; From 718efbc6a773dd07047f2ac3d62bbbf3bc4b104f Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sat, 6 Sep 2025 12:08:09 +0000 Subject: [PATCH 683/931] arm64: dts: rockchip: add GPU powerdomain, opps, and cooling to rk3328 Add GPU powerdomain, opp-table, and cooling map nodes for the Mali GPU on the RK3328 SoC. Opp-table frequencies are sourced from the Rockchip Linux v4.4 vendor kernel while voltages have been derived from practical use and support work: keeping voltage above 1075mV and disabling the 500MHz opp-point avoids instability and crashes. Signed-off-by: Alex Bee Signed-off-by: Christian Hewitt Tested-by: Diederik de Haas # Rock64 Link: https://lore.kernel.org/r/20250906120810.1833016-1-christianshewitt@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 40 +++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 6438c969f9d7..283d9cbc4368 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -331,6 +331,11 @@ power: power-controller { #address-cells = <1>; #size-cells = <0>; + power-domain@RK3328_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + #power-domain-cells = <0>; + }; power-domain@RK3328_PD_HEVC { reg = ; clocks = <&cru SCLK_VENC_CORE>; @@ -570,9 +575,13 @@ map0 { <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <4096>; }; + map1 { + trip = <&target>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; }; }; - }; tsadc: tsadc@ff250000 { @@ -651,7 +660,36 @@ gpu: gpu@ff300000 { "ppmmu1"; clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; clock-names = "bus", "core"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3328_PD_GPU>; resets = <&cru SRST_GPU_A>; + #cooling-cells = <2>; + }; + + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1075000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1075000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1075000>; + }; + + opp-500000000 { + /* causes stability issues */ + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1150000>; + status = "disabled"; + }; }; h265e_mmu: iommu@ff330200 { From d81b0c3099d02f6c7a4be7a15d33145b3700b159 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sat, 6 Sep 2025 12:08:10 +0000 Subject: [PATCH 684/931] arm64: dts: rockchip: enable the Mali GPU on RK3328 boards Add a gpu node to the rock64 board to enable the Mali GPU and move the existing node from roc-pc to the shared roc dtsi to enable it also for the roc-cc board. Signed-off-by: Alex Bee Signed-off-by: Christian Hewitt Tested-by: Diederik de Haas # Rock64 Link: https://lore.kernel.org/r/20250906120810.1833016-2-christianshewitt@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts | 4 ---- arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi | 4 ++++ arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 4 ++++ 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts index 329d03172433..c0b7b98ff788 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts @@ -44,10 +44,6 @@ &codec { mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; }; -&gpu { - mali-supply = <&vdd_logic>; -}; - &pinctrl { ir { ir_int: ir-int { diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi index 2449a344f4ec..7d62a3e96b19 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc.dtsi @@ -167,6 +167,10 @@ &gmac2io { status = "okay"; }; +&gpu { + mali-supply = <&vdd_logic>; +}; + &hdmi { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts index 5367e5fa9232..592fd8ca21df 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts @@ -152,6 +152,10 @@ &gmac2io { status = "okay"; }; +&gpu { + mali-supply = <&vdd_logic>; +}; + &hdmi { avdd-0v9-supply = <&vdd_10>; avdd-1v8-supply = <&vcc_18>; From 804ebc2bdcc85f30973708835b47ee023a4be003 Mon Sep 17 00:00:00 2001 From: Kartik Rajput Date: Thu, 28 Aug 2025 11:29:29 +0530 Subject: [PATCH 685/931] dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C Tegra264 has 17 generic I2C controllers, two of which are in always-on partition of the SoC. In addition to the features supported by Tegra194 it also supports a SW mutex register to allow sharing the same I2C instance across multiple firmware. Document compatible string "nvidia,tegra264-i2c" for Tegra264 I2C. Signed-off-by: Kartik Rajput Acked-by: Conor Dooley Signed-off-by: Thierry Reding --- .../devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml index 6b6f6762d122..f0693b872cb6 100644 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml @@ -80,6 +80,12 @@ properties: support for 64 KiB transactions whereas earlier chips supported no more than 4 KiB per transactions. const: nvidia,tegra194-i2c + - description: + Tegra264 has 17 generic I2C controllers, two of which are in the AON + (always-on) partition of the SoC. In addition to the features from + Tegra194, a SW mutex register is added to support use of the same I2C + instance across multiple firmwares. + const: nvidia,tegra264-i2c reg: maxItems: 1 @@ -186,6 +192,7 @@ allOf: contains: enum: - nvidia,tegra194-i2c + - nvidia,tegra264-i2c then: required: - resets From 6b670e53ac6ecd531d90324e9ef87a029d2c98b9 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 6 Sep 2025 16:53:33 +0300 Subject: [PATCH 686/931] dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI The avdd-dsi-csi-supply is CSI power supply, it has nothing to do with VI, like same supply is used with DSI and has nothing to do with DC. Move it to correct place. Signed-off-by: Svyatoslav Ryhel Acked-by: Rob Herring (Arm) Signed-off-by: Thierry Reding --- .../devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml | 3 --- .../devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml | 3 +++ 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml index 2181855a0920..644f42b942ad 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml @@ -70,9 +70,6 @@ properties: ranges: maxItems: 1 - avdd-dsi-csi-supply: - description: DSI/CSI power supply. Must supply 1.2 V. - vip: $ref: /schemas/display/tegra/nvidia,tegra20-vip.yaml diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml index fa07a40d1004..37f6129c9c92 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml @@ -37,6 +37,9 @@ properties: - const: cile - const: csi_tpg + avdd-dsi-csi-supply: + description: DSI/CSI power supply. Must supply 1.2 V. + power-domains: maxItems: 1 From fc02f529a8dbf617f6d211cb693f56a842b6dbe5 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 6 Sep 2025 16:53:23 +0300 Subject: [PATCH 687/931] dt-bindings: clock: tegra30: Add IDs for CSI pad clocks Tegra30 has CSI pad clock enable bits embedded into PLLD/PLLD2 registers. Add ids for these clocks. Additionally, move TEGRA30_CLK_CLK_MAX into clk-tegra30 source. Signed-off-by: Svyatoslav Ryhel Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- drivers/clk/tegra/clk-tegra30.c | 1 + include/dt-bindings/clock/tegra30-car.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 82a8cb9545eb..e7ebb63970d3 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -53,6 +53,7 @@ #define SYSTEM_CLK_RATE 0x030 #define TEGRA30_CLK_PERIPH_BANKS 5 +#define TEGRA30_CLK_CLK_MAX 311 #define PLLC_BASE 0x80 #define PLLC_MISC 0x8c diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h index f193663e6f28..763b81f80908 100644 --- a/include/dt-bindings/clock/tegra30-car.h +++ b/include/dt-bindings/clock/tegra30-car.h @@ -271,6 +271,7 @@ #define TEGRA30_CLK_AUDIO3_MUX 306 #define TEGRA30_CLK_AUDIO4_MUX 307 #define TEGRA30_CLK_SPDIF_MUX 308 -#define TEGRA30_CLK_CLK_MAX 309 +#define TEGRA30_CLK_CSIA_PAD 309 +#define TEGRA30_CLK_CSIB_PAD 310 #endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ From 669c71f6c6b0034f918430a2fdcf577683d31db6 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Tue, 9 Sep 2025 10:49:57 +0300 Subject: [PATCH 688/931] dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101) Add a compatible for the Xiaomi Mi Pad (A0101) tablet. Signed-off-by: Svyatoslav Ryhel Acked-by: Rob Herring (Arm) Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 1634dab53269..5b0f03af370d 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -174,6 +174,10 @@ properties: - const: google,nyan-big - const: google,nyan - const: nvidia,tegra124 + - description: Xiaomi Mi Pad (A0101) + items: + - const: xiaomi,mocha + - const: nvidia,tegra124 - items: - enum: - nvidia,darcy From 7526e6db4703d0fe81b5397939c2aefd5fe8d9bc Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 29 Aug 2025 15:22:31 +0300 Subject: [PATCH 689/931] dt-bindings: reset: Add Tegra114 CAR header The way that resets are handled on these Tegra devices is that there is a set of peripheral clocks & resets which are paired up. This is because they are laid out in banks within the CAR (clock and reset) controller. In most cases we're referring to those resets, so you'll often see a clock ID used in conjection with the same reset ID for a given IP block. In addition to those peripheral resets, there are a number of extra resets that don't have a corresponding clock and which are exposed in registers outside of the peripheral banks, but still part of the CAR. To support those "special" registers, the TEGRA*_RESET() is used to denote resets outside of the regular peripheral resets. Essentially it defines the offset within the CAR at which special resets start. In the above case, Tegra114 has 5 banks with 32 peripheral resets each. The first special reset, TEGRA114_RESET(0), therefore gets ID 5 * 32 + 0 = 160. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- include/dt-bindings/reset/nvidia,tegra114-car.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 include/dt-bindings/reset/nvidia,tegra114-car.h diff --git a/include/dt-bindings/reset/nvidia,tegra114-car.h b/include/dt-bindings/reset/nvidia,tegra114-car.h new file mode 100644 index 000000000000..9b8c320402db --- /dev/null +++ b/include/dt-bindings/reset/nvidia,tegra114-car.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * This header provides Tegra114-specific constants for binding + * nvidia,tegra114-car. + */ + +#ifndef _DT_BINDINGS_RESET_NVIDIA_TEGRA114_CAR_H +#define _DT_BINDINGS_RESET_NVIDIA_TEGRA114_CAR_H + +#define TEGRA114_RESET(x) (5 * 32 + (x)) +#define TEGRA114_RST_DFLL_DVCO TEGRA114_RESET(0) + +#endif /* _DT_BINDINGS_RESET_NVIDIA_TEGRA114_CAR_H */ From 04f27a0fda6b6be104531eeb95d07ef1b3a72af8 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 6 Sep 2025 09:29:33 +0300 Subject: [PATCH 690/931] dt-bindings: arm: tegra: Add ASUS TF101G and SL101 Add a compatible for ASUS Eee Pad Transformer TF101G and ASUS Eee Pad Slider SL101. Signed-off-by: Svyatoslav Ryhel Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 5b0f03af370d..6139407c2cbf 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -36,8 +36,12 @@ properties: - toradex,colibri_t20-iris - const: toradex,colibri_t20 - const: nvidia,tegra20 - - items: - - const: asus,tf101 + - description: ASUS Transformers T20 Device family + items: + - enum: + - asus,sl101 + - asus,tf101 + - asus,tf101g - const: nvidia,tegra20 - items: - const: acer,picasso From b49a73a08100ab139e07cfa7ca36e9b15787d0ab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonas=20Schw=C3=B6bel?= Date: Wed, 3 Sep 2025 19:19:46 +0300 Subject: [PATCH 691/931] ARM: tegra: p880: set correct touchscreen clipping MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Existing touchscreen clipping is too small and causes problems with touchscreen accuracy. Signed-off-by: Jonas Schwöbel Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts index 2f7754fd42a1..c6ef0a20c19f 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-lg-p880.dts @@ -108,8 +108,8 @@ sub-mic-ldo { i2c@7000c400 { touchscreen@20 { rmi4-f11@11 { - syna,clip-x-high = <1110>; - syna,clip-y-high = <1973>; + syna,clip-x-high = <1440>; + syna,clip-y-high = <2560>; touchscreen-inverted-y; }; From 93ff9ffaf3434a236d5450d8a29af1433b48a049 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 29 Aug 2025 15:22:34 +0300 Subject: [PATCH 692/931] ARM: tegra: Add DFLL clock support for Tegra114 Add DFLL clock node to common Tegra114 device tree along with clocks property to cpu node. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/tegra114.dtsi | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi index 4caf2073c556..a2a50f959927 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include / { @@ -693,6 +694,29 @@ mipi: mipi@700e3000 { #nvidia,mipi-calibrate-cells = <1>; }; + dfll: clock@70110000 { + compatible = "nvidia,tegra114-dfll"; + reg = <0x70110000 0x100>, /* DFLL control */ + <0x70110000 0x100>, /* I2C output control */ + <0x70110100 0x100>, /* Integrated I2C controller */ + <0x70110200 0x100>; /* Look-up table RAM */ + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>, + <&tegra_car TEGRA114_CLK_DFLL_REF>, + <&tegra_car TEGRA114_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <10>; + nvidia,ci = <0>; + nvidia,cg = <2>; + status = "disabled"; + }; + mmc@78000000 { compatible = "nvidia,tegra114-sdhci"; reg = <0x78000000 0x200>; @@ -824,6 +848,15 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + + clocks = <&tegra_car TEGRA114_CLK_CCLK_G>, + <&tegra_car TEGRA114_CLK_CCLK_LP>, + <&tegra_car TEGRA114_CLK_PLL_X>, + <&tegra_car TEGRA114_CLK_PLL_P>, + <&dfll>; + clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; + /* FIXME: what's the actual transition time? */ + clock-latency = <300000>; }; cpu1: cpu@1 { From cca41614d15ce2bbc2c661362d3eafe53c9990af Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 6 Sep 2025 09:29:31 +0300 Subject: [PATCH 693/931] ARM: tegra: transformer-20: add missing magnetometer interrupt Add missing interrupt to magnetometer node. Tested-by: Winona Schroeer-Smith # ASUS SL101 Tested-by: Antoni Aloy Torrens # ASUS TF101 Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts index 67764afeb013..39008816fe5e 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts @@ -502,6 +502,9 @@ magnetometer@e { compatible = "asahi-kasei,ak8974"; reg = <0xe>; + interrupt-parent = <&gpio>; + interrupts = ; + avdd-supply = <&vdd_3v3_sys>; dvdd-supply = <&vdd_1v8_sys>; From 3f973d78d176768fa7456def97f0b9824235024f Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 6 Sep 2025 09:29:32 +0300 Subject: [PATCH 694/931] ARM: tegra: transformer-20: fix audio-codec interrupt Correct audio-codec interrupt should be PX3 while PX1 is used for external microphone detection. Tested-by: Winona Schroeer-Smith # ASUS SL101 Tested-by: Antoni Aloy Torrens # ASUS TF101 Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts index 39008816fe5e..efd8838f9644 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts @@ -518,7 +518,7 @@ wm8903: audio-codec@1a { reg = <0x1a>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; gpio-controller; #gpio-cells = <2>; From 73e23d3bd7220847c3b1554ebe29221f84a01e95 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 6 Sep 2025 09:29:34 +0300 Subject: [PATCH 695/931] ARM: tegra: add support for ASUS Eee Pad Slider SL101 Factor out common part from ASUS Eee Pad Transformer TF101 device tree into tegra20-asus-transformer-common.dtsi and add device tree fragment for ASUS Eee Pad Slider SL101. Tested-by: Winona Schroeer-Smith # ASUS SL101 Tested-by: Antoni Aloy Torrens # ASUS TF101 Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/Makefile | 1 + .../boot/dts/nvidia/tegra20-asus-sl101.dts | 61 + .../boot/dts/nvidia/tegra20-asus-tf101.dts | 1254 +--------------- .../tegra20-asus-transformer-common.dtsi | 1268 +++++++++++++++++ 4 files changed, 1333 insertions(+), 1251 deletions(-) create mode 100644 arch/arm/boot/dts/nvidia/tegra20-asus-sl101.dts create mode 100644 arch/arm/boot/dts/nvidia/tegra20-asus-transformer-common.dtsi diff --git a/arch/arm/boot/dts/nvidia/Makefile b/arch/arm/boot/dts/nvidia/Makefile index 7c1d3cb5dcf0..2ed2d923c8f9 100644 --- a/arch/arm/boot/dts/nvidia/Makefile +++ b/arch/arm/boot/dts/nvidia/Makefile @@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ tegra124-venice2.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-acer-a500-picasso.dtb \ + tegra20-asus-sl101.dtb \ tegra20-asus-tf101.dtb \ tegra20-harmony.dtb \ tegra20-colibri-eval-v3.dtb \ diff --git a/arch/arm/boot/dts/nvidia/tegra20-asus-sl101.dts b/arch/arm/boot/dts/nvidia/tegra20-asus-sl101.dts new file mode 100644 index 000000000000..8828129d1fa3 --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-asus-sl101.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra20-asus-transformer-common.dtsi" + +/ { + model = "ASUS Eee Pad Slider SL101"; + compatible = "asus,sl101", "nvidia,tegra20"; + + i2c@7000c000 { + magnetometer@e { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; + + /* Atmel MXT1386 Touchscreen */ + touchscreen@5a { + compatible = "atmel,maxtouch"; + reg = <0x5a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; + + vdda-supply = <&vdd_3v3_sys>; + vdd-supply = <&vdd_3v3_sys>; + + atmel,wakeup-method = ; + }; + + gyroscope@68 { + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + + i2c-gate { + accelerometer@f { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; + }; + }; + }; + + extcon-keys { + compatible = "gpio-keys"; + + switch-tablet-mode { + label = "Tablet Mode"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <500>; + wakeup-event-action = ; + wakeup-source; + }; + }; +}; diff --git a/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts index efd8838f9644..0d93820a5ad4 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts @@ -1,545 +1,19 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -#include -#include -#include -#include - -#include "tegra20.dtsi" -#include "tegra20-cpu-opp.dtsi" -#include "tegra20-cpu-opp-microvolt.dtsi" +#include "tegra20-asus-transformer-common.dtsi" / { - model = "ASUS EeePad Transformer TF101"; + model = "ASUS Eee Pad Transformer TF101"; compatible = "asus,tf101", "nvidia,tegra20"; - chassis-type = "convertible"; - - aliases { - mmc0 = &sdmmc4; /* eMMC */ - mmc1 = &sdmmc3; /* MicroSD */ - mmc2 = &sdmmc1; /* WiFi */ - - rtc0 = &pmic; - rtc1 = "/rtc@7000e000"; - - serial0 = &uartd; - serial1 = &uartc; /* Bluetooth */ - serial2 = &uartb; /* GPS */ - }; - - /* - * The decompressor and also some bootloaders rely on a - * pre-existing /chosen node to be available to insert the - * command line and merge other ATAGS info. - */ - chosen {}; - - memory@0 { - reg = <0x00000000 0x40000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - ramoops@2ffe0000 { - compatible = "ramoops"; - reg = <0x2ffe0000 0x10000>; /* 64kB */ - console-size = <0x8000>; /* 32kB */ - record-size = <0x400>; /* 1kB */ - ecc-size = <16>; - }; - - linux,cma@30000000 { - compatible = "shared-dma-pool"; - alloc-ranges = <0x30000000 0x10000000>; - size = <0x10000000>; /* 256MiB */ - linux,cma-default; - reusable; - }; - }; - - host1x@50000000 { - dc@54200000 { - rgb { - status = "okay"; - - port { - lcd_output: endpoint { - remote-endpoint = <&lvds_encoder_input>; - bus-width = <18>; - }; - }; - }; - }; - - hdmi@54280000 { - status = "okay"; - - vdd-supply = <&hdmi_vdd_reg>; - pll-supply = <&hdmi_pll_reg>; - hdmi-supply = <&vdd_hdmi_en>; - - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) - GPIO_ACTIVE_HIGH>; - }; - }; - - gpio@6000d000 { - charging-enable-hog { - gpio-hog; - gpios = ; - output-low; - }; - }; - - pinmux@70000014 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; - - state_default: pinmux { - ata { - nvidia,pins = "ata"; - nvidia,function = "ide"; - }; - - atb { - nvidia,pins = "atb", "gma", "gme"; - nvidia,function = "sdio4"; - }; - - atc { - nvidia,pins = "atc"; - nvidia,function = "nand"; - }; - - atd { - nvidia,pins = "atd", "ate", "gmb", "spia", - "spib", "spic"; - nvidia,function = "gmi"; - }; - - cdev1 { - nvidia,pins = "cdev1"; - nvidia,function = "plla_out"; - }; - - cdev2 { - nvidia,pins = "cdev2"; - nvidia,function = "pllp_out4"; - }; - - crtp { - nvidia,pins = "crtp"; - nvidia,function = "crt"; - }; - - lm1 { - nvidia,pins = "lm1"; - nvidia,function = "rsvd3"; - }; - - csus { - nvidia,pins = "csus"; - nvidia,function = "vi_sensor_clk"; - }; - - dap1 { - nvidia,pins = "dap1"; - nvidia,function = "dap1"; - }; - - dap2 { - nvidia,pins = "dap2"; - nvidia,function = "dap2"; - }; - - dap3 { - nvidia,pins = "dap3"; - nvidia,function = "dap3"; - }; - - dap4 { - nvidia,pins = "dap4"; - nvidia,function = "dap4"; - }; - - dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; - nvidia,function = "vi"; - }; - - dtf { - nvidia,pins = "dtf"; - nvidia,function = "i2c3"; - }; - - gmc { - nvidia,pins = "gmc"; - nvidia,function = "uartd"; - }; - - gmd { - nvidia,pins = "gmd"; - nvidia,function = "sflash"; - }; - - gpu { - nvidia,pins = "gpu"; - nvidia,function = "pwm"; - }; - - gpu7 { - nvidia,pins = "gpu7"; - nvidia,function = "rtck"; - }; - - gpv { - nvidia,pins = "gpv", "slxa"; - nvidia,function = "pcie"; - }; - - hdint { - nvidia,pins = "hdint"; - nvidia,function = "hdmi"; - }; - - i2cp { - nvidia,pins = "i2cp"; - nvidia,function = "i2cp"; - }; - - irrx { - nvidia,pins = "irrx", "irtx"; - nvidia,function = "uartb"; - }; - - kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf"; - nvidia,function = "kbc"; - }; - - lcsn { - nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", - "lsdi", "lvp0"; - nvidia,function = "rsvd4"; - }; - - ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lpp", "lpw0", - "lpw2", "lsc0", "lsc1", "lsck", "lsda", - "lspi", "lvp1", "lvs"; - nvidia,function = "displaya"; - }; - - owc { - nvidia,pins = "owc", "spdi", "spdo", "uac"; - nvidia,function = "rsvd2"; - }; - - pmc { - nvidia,pins = "pmc"; - nvidia,function = "pwr_on"; - }; - - rm { - nvidia,pins = "rm"; - nvidia,function = "i2c1"; - }; - - sdb { - nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; - nvidia,function = "sdio3"; - }; - - sdio1 { - nvidia,pins = "sdio1"; - nvidia,function = "sdio1"; - }; - - slxd { - nvidia,pins = "slxd"; - nvidia,function = "spdif"; - }; - - spid { - nvidia,pins = "spid", "spie", "spif"; - nvidia,function = "spi1"; - }; - - spig { - nvidia,pins = "spig", "spih"; - nvidia,function = "spi2_alt"; - }; - - uaa { - nvidia,pins = "uaa", "uab", "uda"; - nvidia,function = "ulpi"; - }; - - uad { - nvidia,pins = "uad"; - nvidia,function = "irda"; - }; - - uca { - nvidia,pins = "uca", "ucb"; - nvidia,function = "uartc"; - }; - - conf_ata { - nvidia,pins = "ata", "atb", "atc", "atd", - "cdev1", "cdev2", "dap1", "dap4", - "dte", "ddc", "dtf", "gma", "gmc", - "gme", "gpu", "gpu7", "gpv", "i2cp", - "irrx", "irtx", "pta", "rm", "sdc", - "sdd", "slxc", "slxd", "slxk", "spdi", - "spdo", "uac", "uad", - "uda", "csus"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - conf_ate { - nvidia,pins = "ate", "dap2", "dap3", "gmb", "gmd", - "owc", "spia", "spib", "spic", - "spid", "spie", "spig", "slxa"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - conf_ck32 { - nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", - "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; - nvidia,pull = ; - }; - - conf_crtp { - nvidia,pins = "crtp", "spih"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - conf_dta { - nvidia,pins = "dta", "dtb", "dtc", "dtd"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - conf_spif { - nvidia,pins = "spif"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - conf_hdint { - nvidia,pins = "hdint", "lcsn", "ldc", "lm1", - "lpw1", "lsck", "lsda", "lsdi", "lvp0"; - nvidia,tristate = ; - }; - - conf_kbca { - nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", - "kbce", "kbcf", "sdio1", "uaa", "uab", - "uca", "ucb"; - nvidia,pull = ; - nvidia,tristate = ; - }; - - conf_lc { - nvidia,pins = "lc", "ls"; - nvidia,pull = ; - }; - - conf_ld0 { - nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", - "ld5", "ld6", "ld7", "ld8", "ld9", - "ld10", "ld11", "ld12", "ld13", "ld14", - "ld15", "ld16", "ld17", "ldi", "lhp0", - "lhp1", "lhp2", "lhs", "lm0", "lpp", - "lpw0", "lpw2", "lsc0", "lsc1", "lspi", - "lvp1", "lvs", "pmc", "sdb"; - nvidia,tristate = ; - }; - - conf_ld17_0 { - nvidia,pins = "ld17_0", "ld19_18", "ld21_20", - "ld23_22"; - nvidia,pull = ; - }; - - drive_sdio1 { - nvidia,pins = "drive_sdio1", "drive_ddc", "drive_vi1"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - - drive_csus { - nvidia,pins = "drive_csus"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,low-power-mode = ; - nvidia,pull-down-strength = <31>; - nvidia,pull-up-strength = <31>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; - }; - - state_i2cmux_ddc: pinmux-i2cmux-ddc { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "i2c2"; - }; - - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_idle: pinmux-i2cmux-idle { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - - pta { - nvidia,pins = "pta"; - nvidia,function = "rsvd4"; - }; - }; - - state_i2cmux_pta: pinmux-i2cmux-pta { - ddc { - nvidia,pins = "ddc"; - nvidia,function = "rsvd4"; - }; - - pta { - nvidia,pins = "pta"; - nvidia,function = "i2c2"; - }; - }; - }; - - spdif@70002400 { - status = "okay"; - - nvidia,fixed-parent-rate; - }; - - i2s@70002800 { - status = "okay"; - - nvidia,fixed-parent-rate; - }; - - serial@70006040 { - compatible = "nvidia,tegra20-hsuart"; - reset-names = "serial"; - /delete-property/ reg-shift; - /* GPS BCM4751 */ - }; - - serial@70006200 { - compatible = "nvidia,tegra20-hsuart"; - reset-names = "serial"; - /delete-property/ reg-shift; - status = "okay"; - - /* Azurewave AW-NH615 BCM4329B1 */ - bluetooth { - compatible = "brcm,bcm4329-bt"; - - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wakeup"; - - /* PLLP 216MHz / 16 / 4 */ - max-speed = <3375000>; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "txco"; - - vbat-supply = <&vdd_3v3_sys>; - vddio-supply = <&vdd_1v8_sys>; - - device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; - }; - }; - - serial@70006300 { - /delete-property/ dmas; - /delete-property/ dma-names; - status = "okay"; - }; - - pwm@7000a000 { - status = "okay"; - }; i2c@7000c000 { - status = "okay"; - clock-frequency = <400000>; - - /* Aichi AMI306 digital compass */ magnetometer@e { - compatible = "asahi-kasei,ak8974"; - reg = <0xe>; - - interrupt-parent = <&gpio>; - interrupts = ; - - avdd-supply = <&vdd_3v3_sys>; - dvdd-supply = <&vdd_1v8_sys>; - mount-matrix = "-1", "0", "0", "0", "1", "0", "0", "0", "-1"; }; - wm8903: audio-codec@1a { - compatible = "wlf,wm8903"; - reg = <0x1a>; - - interrupt-parent = <&gpio>; - interrupts = ; - - gpio-controller; - #gpio-cells = <2>; - - micdet-cfg = <0x83>; - micdet-delay = <100>; - - gpio-cfg = < - 0x00000600 /* DMIC_LR, output */ - 0x00000680 /* DMIC_DAT, input */ - 0x00000000 /* Speaker-enable GPIO, output, low */ - 0xffffffff /* don't touch */ - 0xffffffff /* don't touch */ - >; - - AVDD-supply = <&vdd_1v8_sys>; - CPVDD-supply = <&vdd_1v8_sys>; - DBVDD-supply = <&vdd_1v8_sys>; - DCVDD-supply = <&vdd_1v8_sys>; - }; - /* Atmel MXT1386 Touchscreen */ touchscreen@5b { compatible = "atmel,maxtouch"; @@ -557,33 +31,12 @@ touchscreen@5b { }; gyroscope@68 { - compatible = "invensense,mpu3050"; - reg = <0x68>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vdd-supply = <&vdd_3v3_sys>; - vlogic-supply = <&vdd_1v8_sys>; - mount-matrix = "0", "1", "0", "-1", "0", "0", "0", "0", "1"; i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - accelerometer@f { - compatible = "kionix,kxtf9"; - reg = <0xf>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vdd-supply = <&vdd_1v8_sys>; - vddio-supply = <&vdd_1v8_sys>; - mount-matrix = "-1", "0", "0", "0", "-1", "0", "0", "0", "-1"; @@ -592,461 +45,9 @@ accelerometer@f { }; }; - i2c2: i2c@7000c400 { - status = "okay"; - clock-frequency = <100000>; - }; - - i2c@7000c500 { - status = "okay"; - clock-frequency = <400000>; - }; - - i2c@7000d000 { - status = "okay"; - clock-frequency = <400000>; - - pmic: pmic@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = ; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_5v0_sys>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - vdd_core: sm0 { - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-coupled-with = <&rtc_vdd &vdd_cpu>; - regulator-coupled-max-spread = <170000 550000>; - regulator-always-on; - regulator-boot-on; - - nvidia,tegra-core-regulator; - }; - - vdd_cpu: sm1 { - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1125000>; - regulator-coupled-with = <&vdd_core &rtc_vdd>; - regulator-coupled-max-spread = <550000 550000>; - regulator-always-on; - regulator-boot-on; - - nvidia,tegra-cpu-regulator; - }; - - sm2_reg: sm2 { - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - /* LDO0 is not connected to anything */ - - ldo1 { - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - rtc_vdd: ldo2 { - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-coupled-with = <&vdd_core &vdd_cpu>; - regulator-coupled-max-spread = <170000 550000>; - regulator-always-on; - regulator-boot-on; - - nvidia,tegra-rtc-regulator; - }; - - ldo3 { - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - ldo4 { - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vcore_emmc: ldo5 { - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo6 { - regulator-name = "vdd_ldo6,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - hdmi_vdd_reg: ldo7 { - regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - hdmi_pll_reg: ldo8 { - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo9 { - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - ldo_rtc { - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; - - nct1008: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&vdd_3v3_sys>; - - interrupt-parent = <&gpio>; - interrupts = ; - - #thermal-sensor-cells = <1>; - }; - }; - - pmc@7000e400 { - nvidia,invert-interrupt; - nvidia,suspend-mode = <1>; - nvidia,cpu-pwr-good-time = <2000>; - nvidia,cpu-pwr-off-time = <100>; - nvidia,core-pwr-good-time = <3845 3845>; - nvidia,core-pwr-off-time = <458>; - nvidia,sys-clock-req-active-high; - core-supply = <&vdd_core>; - }; - - memory-controller@7000f400 { - nvidia,use-ram-code; - - emc-tables@3 { - reg = <0x3>; - - #address-cells = <1>; - #size-cells = <0>; - - emc-table@25000 { - reg = <25000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <25000>; - nvidia,emc-registers = <0x00000002 0x00000006 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000004 - 0x00000003 0x00000008 0x0000000b 0x0000004d - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000068 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@50000 { - reg = <50000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <50000>; - nvidia,emc-registers = <0x00000003 0x00000007 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000009f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000007 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x000000d0 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000005 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@75000 { - reg = <75000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <75000>; - nvidia,emc-registers = <0x00000005 0x0000000a - 0x00000004 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x000000ff - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x0000000b - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000138 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000007 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@150000 { - reg = <150000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <150000>; - nvidia,emc-registers = <0x00000009 0x00000014 - 0x00000007 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000021f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000015 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000270 0x00000000 0x00000001 - 0x00000000 0x00000000 0x00000282 0xa07c04ae - 0x007dc010 0x00000000 0x00000000 0x0000000e - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@300000 { - reg = <300000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <300000>; - nvidia,emc-registers = <0x00000012 0x00000027 - 0x0000000d 0x00000006 0x00000007 0x00000005 - 0x00000003 0x00000009 0x00000006 0x00000006 - 0x00000003 0x00000003 0x00000002 0x00000006 - 0x00000003 0x00000009 0x0000000c 0x0000045f - 0x00000000 0x00000004 0x00000004 0x00000006 - 0x00000008 0x00000001 0x0000000e 0x0000002a - 0x00000003 0x0000000f 0x00000007 0x00000005 - 0x00000002 0x000004e0 0x00000005 0x00000002 - 0x00000000 0x00000000 0x00000282 0xe059048b - 0x007e0010 0x00000000 0x00000000 0x0000001b - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - lpddr2 { - compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; - revision-id = <1 0>; - density = <2048>; - io-width = <16>; - }; - }; - }; - - /* Peripheral USB via ASUS connector */ - usb@c5000000 { - compatible = "nvidia,tegra20-udc"; - status = "okay"; - dr_mode = "peripheral"; - }; - - usb-phy@c5000000 { - status = "okay"; - dr_mode = "peripheral"; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - vbus-supply = <&vdd_5v0_sys>; - }; - - /* Dock's USB port */ - usb@c5008000 { - status = "okay"; - }; - - usb-phy@c5008000 { - status = "okay"; - nvidia,xcvr-setup-use-fuses; - vbus-supply = <&vdd_5v0_sys>; - }; - - sdmmc1: mmc@c8000000 { - status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - - assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; - assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; - assigned-clock-rates = <40000000>; - - max-frequency = <40000000>; - keep-power-in-suspend; - bus-width = <4>; - non-removable; - - mmc-pwrseq = <&brcm_wifi_pwrseq>; - vmmc-supply = <&vdd_3v3_sys>; - vqmmc-supply = <&vdd_3v3_sys>; - - /* Azurewave AW-NH615 BCM4329B1 */ - wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wake"; - }; - }; - - sdmmc3: mmc@c8000400 { - status = "okay"; - bus-width = <4>; - cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; - power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; - vmmc-supply = <&vdd_3v3_sys>; - vqmmc-supply = <&vdd_3v3_sys>; - }; - - sdmmc4: mmc@c8000600 { - status = "okay"; - bus-width = <8>; - vmmc-supply = <&vcore_emmc>; - vqmmc-supply = <&vdd_3v3_sys>; - non-removable; - }; - - mains: ac-adapter-detect { - compatible = "gpio-charger"; - charger-type = "mains"; - gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - - enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; - power-supply = <&vdd_3v3_sys>; - pwms = <&pwm 2 4000000>; - - brightness-levels = <7 255>; - num-interpolated-steps = <248>; - default-brightness-level = <20>; - }; - - /* PMIC has a built-in 32KHz oscillator which is used by PMC */ - clk32k_in: clock-32k-in { - compatible = "fixed-clock"; - clock-frequency = <32768>; - #clock-cells = <0>; - }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - cpu-supply = <&vdd_cpu>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - - display-panel { - compatible = "auo,b101ew05", "panel-lvds"; - - /* AUO B101EW05 using custom timings */ - - backlight = <&backlight>; - ddc-i2c-bus = <&lvds_ddc>; - power-supply = <&vdd_pnl_reg>; - - width-mm = <218>; - height-mm = <135>; - - data-mapping = "jeida-18"; - - panel-timing { - clock-frequency = <71200000>; - hactive = <1280>; - vactive = <800>; - hfront-porch = <8>; - hback-porch = <18>; - hsync-len = <184>; - vsync-len = <3>; - vfront-porch = <4>; - vback-porch = <8>; - }; - - port { - panel_input: endpoint { - remote-endpoint = <&lvds_encoder_output>; - }; - }; - }; - - gpio-keys { + extcon-keys { compatible = "gpio-keys"; - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - switch-dock-hall-sensor { label = "Lid"; gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; @@ -1057,253 +58,4 @@ switch-dock-hall-sensor { wakeup-source; }; }; - - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&i2c2>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - lvds_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - smart-battery@b { - compatible = "ti,bq20z75", "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - power-supplies = <&mains>; - }; - - /* Dynaimage ambient light sensor */ - light-sensor@1c { - compatible = "dynaimage,al3000a"; - reg = <0x1c>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vdd-supply = <&vdd_1v8_sys>; - }; - }; - }; - - lvds-encoder { - compatible = "ti,sn75lvds83", "lvds-encoder"; - - powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; - power-supply = <&vdd_3v3_sys>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_encoder_input: endpoint { - remote-endpoint = <&lcd_output>; - }; - }; - - port@1 { - reg = <1>; - - lvds_encoder_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; - }; - }; - - opp-table-emc { - /delete-node/ opp-666000000; - /delete-node/ opp-760000000; - }; - - vdd_5v0_sys: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3_sys: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3_vs"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vdd_5v0_sys>; - }; - - regulator-pcie { - compatible = "regulator-fixed"; - regulator-name = "pcie_vdd"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; - regulator-always-on; - }; - - vdd_pnl_reg: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vdd_1v8_sys: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v8_vs"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_hdmi_en: regulator-hdmi { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0_hdmi_en"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - vin-supply = <&vdd_5v0_sys>; - gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - sound { - compatible = "asus,tegra-audio-wm8903-tf101", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Asus EeePad Transformer WM8903"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "ROP", - "Int Spk", "RON", - "Int Spk", "LOP", - "Int Spk", "LON", - "IN2L", "Mic Jack", - "DMICDAT", "Int Mic"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>; - nvidia,coupled-mic-hp-det; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - thermal-zones { - /* - * NCT1008 has two sensors: - * - * 0: internal that monitors ambient/skin temperature - * 1: external that is connected to the CPU's diode - * - * Ideally we should use userspace thermal governor, - * but it's a much more complex solution. The "skin" - * zone is a simpler solution which prevents TF101 from - * getting too hot from a user's tactile perspective. - * The CPU zone is intended to protect silicon from damage. - */ - - skin-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct1008 0>; - - trips { - trip0: skin-alert { - /* start throttling at 60C */ - temperature = <60000>; - hysteresis = <200>; - type = "passive"; - }; - - trip1: skin-crit { - /* shut down at 70C */ - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&trip0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct1008 1>; - - trips { - trip2: cpu-alert { - /* throttle at 85C until temperature drops to 84.8C */ - temperature = <85000>; - hysteresis = <200>; - type = "passive"; - }; - - trip3: cpu-crit { - /* shut down at 90C */ - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map1 { - trip = <&trip2>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - brcm_wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <200>; - power-off-delay-us = <200>; - }; }; diff --git a/arch/arm/boot/dts/nvidia/tegra20-asus-transformer-common.dtsi b/arch/arm/boot/dts/nvidia/tegra20-asus-transformer-common.dtsi new file mode 100644 index 000000000000..b48f53c00efa --- /dev/null +++ b/arch/arm/boot/dts/nvidia/tegra20-asus-transformer-common.dtsi @@ -0,0 +1,1268 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include + +#include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" +#include "tegra20-cpu-opp-microvolt.dtsi" + +/ { + chassis-type = "convertible"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* MicroSD */ + mmc2 = &sdmmc1; /* WiFi */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + serial0 = &uartd; + serial1 = &uartc; /* Bluetooth */ + serial2 = &uartb; /* GPS */ + }; + + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + + memory@0 { + reg = <0x00000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@2ffe0000 { + compatible = "ramoops"; + reg = <0x2ffe0000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + linux,cma@30000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x30000000 0x10000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + port { + lcd_output: endpoint { + remote-endpoint = <&lvds_encoder_input>; + bus-width = <18>; + }; + }; + }; + }; + + hdmi@54280000 { + status = "okay"; + + vdd-supply = <&hdmi_vdd_reg>; + pll-supply = <&hdmi_pll_reg>; + hdmi-supply = <&vdd_hdmi_en>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) + GPIO_ACTIVE_HIGH>; + }; + }; + + gpio@6000d000 { + charging-enable-hog { + gpio-hog; + gpios = ; + output-low; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + + atd { + nvidia,pins = "atd", "ate", "gmb", "spia", + "spib", "spic"; + nvidia,function = "gmi"; + }; + + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + + lm1 { + nvidia,pins = "lm1"; + nvidia,function = "rsvd3"; + }; + + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + + gmd { + nvidia,pins = "gmd"; + nvidia,function = "sflash"; + }; + + gpu { + nvidia,pins = "gpu"; + nvidia,function = "pwm"; + }; + + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + + gpv { + nvidia,pins = "gpv", "slxa"; + nvidia,function = "pcie"; + }; + + hdint { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uartb"; + }; + + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + + lcsn { + nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", + "lsdi", "lvp0"; + nvidia,function = "rsvd4"; + }; + + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lpp", "lpw0", + "lpw2", "lsc0", "lsc1", "lsck", "lsda", + "lspi", "lvp1", "lvs"; + nvidia,function = "displaya"; + }; + + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + + sdb { + nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; + nvidia,function = "sdio3"; + }; + + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + + slxd { + nvidia,pins = "slxd"; + nvidia,function = "spdif"; + }; + + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + + conf-ata { + nvidia,pins = "ata", "atb", "atc", "atd", + "cdev1", "cdev2", "dap1", "dap4", + "dte", "ddc", "dtf", "gma", "gmc", + "gme", "gpu", "gpu7", "gpv", "i2cp", + "irrx", "irtx", "pta", "rm", "sdc", + "sdd", "slxc", "slxd", "slxk", "spdi", + "spdo", "uac", "uad", + "uda", "csus"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf-ate { + nvidia,pins = "ate", "dap2", "dap3", "gmb", "gmd", + "owc", "spia", "spib", "spic", + "spid", "spie", "spig", "slxa"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf-ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = ; + }; + + conf-crtp { + nvidia,pins = "crtp", "spih"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf-dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf-spif { + nvidia,pins = "spif"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf-hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsck", "lsda", "lsdi", "lvp0"; + nvidia,tristate = ; + }; + + conf-kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf", "sdio1", "uaa", "uab", + "uca", "ucb"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf-lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = ; + }; + + conf-ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lsc1", "lspi", + "lvp1", "lvs", "pmc", "sdb"; + nvidia,tristate = ; + }; + + conf-ld17-0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = ; + }; + + drive-sdio1 { + nvidia,pins = "drive_sdio1", "drive_ddc", "drive_vi1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive-csus { + nvidia,pins = "drive_csus"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + + state_i2cmux_ddc: pinmux-i2cmux-ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_idle: pinmux-i2cmux-idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux-i2cmux-pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + }; + + spdif@70002400 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + + i2s@70002800 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + + serial@70006040 { + compatible = "nvidia,tegra20-hsuart"; + reset-names = "serial"; + /delete-property/ reg-shift; + /* GPS BCM4751 */ + }; + + serial@70006200 { + compatible = "nvidia,tegra20-hsuart"; + reset-names = "serial"; + /delete-property/ reg-shift; + status = "okay"; + + /* Azurewave AW-NH615 BCM4329B1 */ + bluetooth { + compatible = "brcm,bcm4329-bt"; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wakeup"; + + /* PLLP 216MHz / 16 / 4 */ + max-speed = <3375000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + vbat-supply = <&vdd_3v3_sys>; + vddio-supply = <&vdd_1v8_sys>; + + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + }; + }; + + serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; + status = "okay"; + }; + + pwm@7000a000 { + status = "okay"; + }; + + i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + /* Aichi AMI306 digital compass */ + magnetometer@e { + compatible = "asahi-kasei,ak8974"; + reg = <0xe>; + + interrupt-parent = <&gpio>; + interrupts = ; + + avdd-supply = <&vdd_3v3_sys>; + dvdd-supply = <&vdd_1v8_sys>; + }; + + wm8903: audio-codec@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + + interrupt-parent = <&gpio>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0x83>; + micdet-delay = <100>; + + gpio-cfg = < + 0x00000600 /* DMIC_LR, output */ + 0x00000680 /* DMIC_DAT, input */ + 0x00000000 /* Speaker-enable GPIO, output, low */ + 0xffffffff /* don't touch */ + 0xffffffff /* don't touch */ + >; + + AVDD-supply = <&vdd_1v8_sys>; + CPVDD-supply = <&vdd_1v8_sys>; + DBVDD-supply = <&vdd_1v8_sys>; + DCVDD-supply = <&vdd_1v8_sys>; + }; + + gyroscope@68 { + compatible = "invensense,mpu3050"; + reg = <0x68>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_3v3_sys>; + vlogic-supply = <&vdd_1v8_sys>; + + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + + accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0xf>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_sys>; + vddio-supply = <&vdd_1v8_sys>; + }; + }; + }; + }; + + i2c2: i2c@7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000c500 { + status = "okay"; + clock-frequency = <400000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = ; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + sys-supply = <&vdd_5v0_sys>; + vin-sm0-supply = <&sys_reg>; + vin-sm1-supply = <&sys_reg>; + vin-sm2-supply = <&sys_reg>; + vinldo01-supply = <&sm2_reg>; + vinldo23-supply = <&sm2_reg>; + vinldo4-supply = <&sm2_reg>; + vinldo678-supply = <&sm2_reg>; + vinldo9-supply = <&sm2_reg>; + + regulators { + sys_reg: sys { + regulator-name = "vdd_sys"; + regulator-always-on; + }; + + vdd_core: sm0 { + regulator-name = "vdd_sm0,vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&rtc_vdd &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-core-regulator; + }; + + vdd_cpu: sm1 { + regulator-name = "vdd_sm1,vdd_cpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1125000>; + regulator-coupled-with = <&vdd_core &rtc_vdd>; + regulator-coupled-max-spread = <550000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-cpu-regulator; + }; + + sm2_reg: sm2 { + regulator-name = "vdd_sm2,vin_ldo*"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + }; + + /* LDO0 is not connected to anything */ + + ldo1 { + regulator-name = "vdd_ldo1,avdd_pll*"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + rtc_vdd: ldo2 { + regulator-name = "vdd_ldo2,vdd_rtc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-coupled-with = <&vdd_core &vdd_cpu>; + regulator-coupled-max-spread = <170000 550000>; + regulator-always-on; + regulator-boot-on; + + nvidia,tegra-rtc-regulator; + }; + + ldo3 { + regulator-name = "vdd_ldo3,avdd_usb*"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcore_emmc: ldo5 { + regulator-name = "vdd_ldo5,vcore_mmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo6 { + regulator-name = "vdd_ldo6,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_vdd_reg: ldo7 { + regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_pll_reg: ldo8 { + regulator-name = "vdd_ldo8,avdd_hdmi_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9 { + regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo_rtc { + regulator-name = "vdd_rtc_out,vdd_cell"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + nct1008: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&vdd_3v3_sys>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + }; + + pmc@7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <100>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; + }; + + memory-controller@7000f400 { + nvidia,use-ram-code; + + emc-tables@3 { + reg = <0x3>; + + #address-cells = <1>; + #size-cells = <0>; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007dc010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e0 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e0010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + lpddr2 { + compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; + revision-id = <1 0>; + density = <2048>; + io-width = <16>; + }; + }; + }; + + /* Peripheral USB via ASUS connector */ + usb@c5000000 { + compatible = "nvidia,tegra20-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@c5000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&vdd_5v0_sys>; + }; + + /* Dock's USB port */ + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + vbus-supply = <&vdd_5v0_sys>; + }; + + sdmmc1: mmc@c8000000 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; + assigned-clock-rates = <40000000>; + + max-frequency = <40000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + + /* Azurewave AW-NH615 BCM4329B1 */ + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + sdmmc3: mmc@c8000400 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + sdmmc4: mmc@c8000600 { + status = "okay"; + bus-width = <8>; + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_3v3_sys>; + non-removable; + }; + + mains: ac-adapter-detect { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_3v3_sys>; + pwms = <&pwm 2 4000000>; + + brightness-levels = <7 255>; + num-interpolated-steps = <248>; + default-brightness-level = <20>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + + display-panel { + compatible = "auo,b101ew05", "panel-lvds"; + + /* AUO B101EW05 using custom timings */ + + backlight = <&backlight>; + ddc-i2c-bus = <&lvds_ddc>; + power-supply = <&vdd_pnl_reg>; + + width-mm = <218>; + height-mm = <135>; + + data-mapping = "jeida-18"; + + panel-timing { + clock-frequency = <71200000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <8>; + hback-porch = <18>; + hsync-len = <184>; + vsync-len = <3>; + vfront-porch = <4>; + vback-porch = <8>; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&lvds_encoder_output>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + }; + + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&i2c2>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + lvds_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + smart-battery@b { + compatible = "ti,bq20z75", "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + power-supplies = <&mains>; + }; + + /* Dynaimage ambient light sensor */ + light-sensor@1c { + compatible = "dynaimage,al3000a"; + reg = <0x1c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_sys>; + }; + }; + }; + + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_encoder_input: endpoint { + remote-endpoint = <&lcd_output>; + }; + }; + + port@1 { + reg = <1>; + + lvds_encoder_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + opp-table-emc { + /delete-node/ opp-666000000; + /delete-node/ opp-760000000; + }; + + vdd_5v0_sys: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_3v3_sys: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_vs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "pcie_vdd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + vdd_pnl_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_1v8_sys: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_vs"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_hdmi_en: regulator-hdmi { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_hdmi_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "asus,tegra-audio-wm8903-tf101", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Asus EeePad Transformer WM8903"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "IN2L", "Mic Jack", + "DMICDAT", "Int Mic"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>; + nvidia,coupled-mic-hp-det; + + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; + + thermal-zones { + /* + * NCT1008 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone is a simpler solution which prevents TF101 from + * getting too hot from a user's tactile perspective. + * The CPU zone is intended to protect silicon from damage. + */ + + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 0>; + + trips { + trip0: skin-alert { + /* start throttling at 60C */ + temperature = <60000>; + hysteresis = <200>; + type = "passive"; + }; + + trip1: skin-crit { + /* shut down at 70C */ + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&nct1008 1>; + + trips { + trip2: cpu-alert { + /* throttle at 85C until temperature drops to 84.8C */ + temperature = <85000>; + hysteresis = <200>; + type = "passive"; + }; + + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; + power-off-delay-us = <200>; + }; +}; From e1899da95f59240ed2d4a51d7a89c8b77c45ff06 Mon Sep 17 00:00:00 2001 From: Kartik Rajput Date: Thu, 28 Aug 2025 15:58:03 +0530 Subject: [PATCH 696/931] arm64: tegra: Add I2C nodes for Tegra264 Add I2C nodes for Tegra264. Signed-off-by: Kartik Rajput Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 225 +++++++++++++++++++++++ 1 file changed, 225 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index e02659efa233..872a69553e3c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -148,6 +148,36 @@ uart0: serial@c5f0000 { status = "disabled"; }; + i2c2: i2c@c600000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x0 0x0c600000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_AON_I2C>, + <&bpmp TEGRA264_CLK_PLLAON>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>; + resets = <&bpmp TEGRA264_RESET_I2C2>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c3: i2c@c610000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x0 0x0c610000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_AON_I2C>, + <&bpmp TEGRA264_CLK_PLLAON>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_AON_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON>; + resets = <&bpmp TEGRA264_RESET_I2C3>; + reset-names = "i2c"; + status = "disabled"; + }; + pmc: pmc@c800000 { compatible = "nvidia,tegra264-pmc"; reg = <0x0 0x0c800000 0x0 0x100000>, @@ -272,6 +302,201 @@ smmu4: iommu@b000000 { dma-coherent; }; + i2c14: i2c@c410000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c410000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C14>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c15: i2c@c420000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c420000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C15>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c16: i2c@c430000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c430000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C16>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c0: i2c@c630000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c630000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C0>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c1: i2c@c640000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c640000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C1>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c4: i2c@c650000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c650000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C4>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c6: i2c@c670000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c670000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C6>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c7: i2c@c680000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c680000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C7>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c8: i2c@c690000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c690000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C8>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c9: i2c@c6a0000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c6a0000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C9>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c10: i2c@c6b0000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c6b0000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C10>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c11: i2c@c6c0000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c6c0000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C11>; + reset-names = "i2c"; + status = "disabled"; + }; + + i2c12: i2c@c6d0000 { + compatible = "nvidia,tegra264-i2c"; + reg = <0x00 0x0c6d0000 0x0 0x10000>; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, + <&bpmp TEGRA264_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA264_CLK_TOP_I2C>; + assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA264_RESET_I2C12>; + reset-names = "i2c"; + status = "disabled"; + }; + gic: interrupt-controller@46000000 { compatible = "arm,gic-v3"; reg = <0x00 0x46000000 0x0 0x010000>, /* GICD */ From 1ed2786e9ef8f16204dc3f30c46412070cb7140e Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Wed, 10 Sep 2025 02:01:37 +0000 Subject: [PATCH 697/931] dt-bindings: soc: renesas: Document R-Car X5H Ironhide Document the compatible values for the Renesas R-Car X5H (R8A78000) SoC, as used on the Renesas Ironhide board. Signed-off-by: Kuninori Morimoto Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/87ms73vzen.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 5f9d541d177a..f4947ac65460 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -473,6 +473,12 @@ properties: - const: renesas,r8a779mb - const: renesas,r8a7795 + - description: R-Car X5H (R8A78000) + items: + - enum: + - renesas,ironhide # Ironhide (RTP8A78000ASKB0F10S) + - const: renesas,r8a78000 + - description: RZ/N1D (R9A06G032) items: - enum: From 00c8fdc2809f05422d919809106f54c23de3cba3 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Sat, 23 Aug 2025 22:01:11 +0530 Subject: [PATCH 698/931] arm64: dts: ti: k3-j742s2-mcu-wakeup: Override firmware-name for MCU R5F cores The J742S2 SoC reuses the common k3-j784s4-j742s2-mcu-wakeup-common.dtsi for its MCU domain, but it does not override the firmware-name property for its R5F cores. This causes the wrong firmware binaries to be referenced. Introduce a new k3-j742s2-mcu-wakeup.dtsi file to override the firmware-name property with correct names for J742s2. Fixes: 38fd90a3e1ac ("arm64: dts: ti: Introduce J742S2 SoC family") Signed-off-by: Beleswar Padhi Reviewed-by: Udit Kumar Link: https://patch.msgid.link/20250823163111.2237199-1-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-j742s2.dtsi | 1 + 2 files changed, 18 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi new file mode 100644 index 000000000000..61db2348d6a4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree Source for J742S2 SoC Family + * + * TRM: https://www.ti.com/lit/pdf/spruje3 + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + * + */ + +&mcu_r5fss0_core0 { + firmware-name = "j742s2-mcu-r5f0_0-fw"; +}; + +&mcu_r5fss0_core1 { + firmware-name = "j742s2-mcu-r5f0_1-fw"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j742s2.dtsi b/arch/arm64/boot/dts/ti/k3-j742s2.dtsi index 7a72f82f56d6..d265df1abade 100644 --- a/arch/arm64/boot/dts/ti/k3-j742s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j742s2.dtsi @@ -96,3 +96,4 @@ cpu3: cpu@3 { }; #include "k3-j742s2-main.dtsi" +#include "k3-j742s2-mcu-wakeup.dtsi" From 7b09167cb7cb09282200903b6371996df4d76bc4 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:57:53 +0530 Subject: [PATCH 699/931] arm64: dts: ti: k3-j7200: Enable R5F remote processors at board level Remote Processors defined in top-level J7200 SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis Link: https://patch.msgid.link/20250908142826.1828676-2-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 9 +++++++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 5ce5f0a3d6f5..628ff89dd72f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -1516,6 +1516,7 @@ main_r5fss0: r5fss@5c00000 { ranges = <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss0_core0: r5f@5c00000 { compatible = "ti,j7200-r5f"; @@ -1530,6 +1531,7 @@ main_r5fss0_core0: r5f@5c00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss0_core1: r5f@5d00000 { @@ -1545,6 +1547,7 @@ main_r5fss0_core1: r5f@5d00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 56ab144fea07..692c4745040e 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -612,6 +612,7 @@ mcu_r5fss0: r5fss@41000000 { ranges = <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; mcu_r5fss0_core0: r5f@41000000 { compatible = "ti,j7200-r5f"; @@ -626,6 +627,7 @@ mcu_r5fss0_core0: r5f@41000000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; mcu_r5fss0_core1: r5f@41400000 { @@ -641,6 +643,7 @@ mcu_r5fss0_core1: r5f@41400000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 291ab9bb414d..90befcdc8d08 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -254,20 +254,27 @@ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { }; }; +&mcu_r5fss0 { + status = "okay"; +}; + &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status = "okay"; }; &mcu_r5fss0_core1 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + status = "okay"; }; &main_r5fss0 { ti,cluster-mode = <0>; + status = "okay"; }; /* Timers are used by Remoteproc firmware */ @@ -287,12 +294,14 @@ &main_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status = "okay"; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status = "okay"; }; &main_i2c0 { From 73d0df7437364feb1a39772eccbb4f1a604cf623 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:57:54 +0530 Subject: [PATCH 700/931] arm64: dts: ti: k3-j721e: Enable remote processors at board level Remote Processors defined in top-level J721E SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis Link: https://patch.msgid.link/20250908142826.1828676-3-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 18 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 6 ++++++ .../arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 12 ++++++++++++ 5 files changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index fb899c99753e..0d1a313a7d10 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -935,37 +935,55 @@ mbox_c71_0: mbox-c71-0 { }; }; +&mcu_r5fss0 { + status = "okay"; +}; + &mcu_r5fss0_core0 { + status = "okay"; mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { + status = "okay"; mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; +&main_r5fss0 { + status = "okay"; +}; + &main_r5fss0_core0 { + status = "okay"; mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { + status = "okay"; mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; +&main_r5fss1 { + status = "okay"; +}; + &main_r5fss1_core0 { + status = "okay"; mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { + status = "okay"; mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index ab3666ff4297..e748f704e3b6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -2182,6 +2182,7 @@ main_r5fss0: r5fss@5c00000 { ranges = <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss0_core0: r5f@5c00000 { compatible = "ti,j721e-r5f"; @@ -2196,6 +2197,7 @@ main_r5fss0_core0: r5f@5c00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss0_core1: r5f@5d00000 { @@ -2211,6 +2213,7 @@ main_r5fss0_core1: r5f@5d00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; @@ -2222,6 +2225,7 @@ main_r5fss1: r5fss@5e00000 { ranges = <0x5e00000 0x00 0x5e00000 0x20000>, <0x5f00000 0x00 0x5f00000 0x20000>; power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss1_core0: r5f@5e00000 { compatible = "ti,j721e-r5f"; @@ -2236,6 +2240,7 @@ main_r5fss1_core0: r5f@5e00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss1_core1: r5f@5f00000 { @@ -2251,6 +2256,7 @@ main_r5fss1_core1: r5f@5f00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index b02142b2b460..42a21398e389 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -594,6 +594,7 @@ mcu_r5fss0: r5fss@41000000 { ranges = <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; mcu_r5fss0_core0: r5f@41000000 { compatible = "ti,j721e-r5f"; @@ -608,6 +609,7 @@ mcu_r5fss0_core0: r5f@41000000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; mcu_r5fss0_core1: r5f@41400000 { @@ -623,6 +625,7 @@ mcu_r5fss0_core1: r5f@41400000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index ffef3d1cfd55..62b9c13a91e7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -1349,13 +1349,19 @@ mbox_c71_0: mbox-c71-0 { }; }; +&mcu_r5fss0 { + status = "okay"; +}; + &mcu_r5fss0_core0 { + status = "okay"; mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { + status = "okay"; mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; @@ -1363,10 +1369,12 @@ &mcu_r5fss0_core1 { &main_r5fss0 { ti,cluster-mode = <0>; + status = "okay"; }; &main_r5fss1 { ti,cluster-mode = <0>; + status = "okay"; }; /* Timers are used by Remoteproc firmware */ @@ -1399,24 +1407,28 @@ &main_timer15 { }; &main_r5fss0_core0 { + status = "okay"; mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { + status = "okay"; mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { + status = "okay"; mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { + status = "okay"; mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 0722f6361cc8..795b041ee733 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -554,23 +554,31 @@ mbox_c71_0: mbox-c71-0 { }; }; +&mcu_r5fss0 { + status = "okay"; +}; + &mcu_r5fss0_core0 { + status = "okay"; mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { + status = "okay"; mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0 { + status = "okay"; ti,cluster-mode = <0>; }; &main_r5fss1 { + status = "okay"; ti,cluster-mode = <0>; }; @@ -604,24 +612,28 @@ &main_timer15 { }; &main_r5fss0_core0 { + status = "okay"; mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { + status = "okay"; mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { + status = "okay"; mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { + status = "okay"; mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; From 368ae64a7188ac06d3cb2ee96975d40e6504e40d Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:57:55 +0530 Subject: [PATCH 701/931] arm64: dts: ti: k3-j721s2: Enable remote processors at board level Remote Processors defined in top-level J721S2 SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis Link: https://patch.msgid.link/20250908142826.1828676-4-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 12 ++++++++++++ 5 files changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi index fd715fee8170..383594732e81 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi @@ -371,24 +371,28 @@ &main_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status = "okay"; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status = "okay"; }; &main_r5fss1_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status = "okay"; }; &main_r5fss1_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status = "okay"; }; /* eMMC */ @@ -407,10 +411,12 @@ &main_sdhci1 { &main_r5fss0 { ti,cluster-mode = <0>; + status = "okay"; }; &main_r5fss1 { ti,cluster-mode = <0>; + status = "okay"; }; /* Timers are used by Remoteproc firmware */ @@ -438,16 +444,22 @@ &main_timer5 { status = "reserved"; }; +&mcu_r5fss0 { + status = "okay"; +}; + &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status = "okay"; }; &mcu_r5fss0_core1 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + status = "okay"; }; &ospi0 { diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi index 4ca2d4e2fb9b..2d2edeeb7347 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -291,24 +291,32 @@ mbox_c71_1: mbox-c71-1 { }; }; +&mcu_r5fss0 { + status = "okay"; +}; + &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status = "okay"; }; &mcu_r5fss0_core1 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + status = "okay"; }; &main_r5fss0 { ti,cluster-mode = <0>; + status = "okay"; }; &main_r5fss1 { ti,cluster-mode = <0>; + status = "okay"; }; /* Timers are used by Remoteproc firmware */ @@ -340,24 +348,28 @@ &main_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status = "okay"; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status = "okay"; }; &main_r5fss1_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status = "okay"; }; &main_r5fss1_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status = "okay"; }; &c71_0 { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 0ad752975acd..80c51b11ac9f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1895,6 +1895,7 @@ main_r5fss0: r5fss@5c00000 { ranges = <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss0_core0: r5f@5c00000 { compatible = "ti,j721s2-r5f"; @@ -1909,6 +1910,7 @@ main_r5fss0_core0: r5f@5c00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss0_core1: r5f@5d00000 { @@ -1924,6 +1926,7 @@ main_r5fss0_core1: r5f@5d00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; @@ -1935,6 +1938,7 @@ main_r5fss1: r5fss@5e00000 { ranges = <0x5e00000 0x00 0x5e00000 0x20000>, <0x5f00000 0x00 0x5f00000 0x20000>; power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss1_core0: r5f@5e00000 { compatible = "ti,j721s2-r5f"; @@ -1949,6 +1953,7 @@ main_r5fss1_core0: r5f@5e00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss1_core1: r5f@5f00000 { @@ -1964,6 +1969,7 @@ main_r5fss1_core1: r5f@5f00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index bc31266126d0..837097751c18 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -690,6 +690,7 @@ mcu_r5fss0: r5fss@41000000 { ranges = <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; mcu_r5fss0_core0: r5f@41000000 { compatible = "ti,j721s2-r5f"; @@ -704,6 +705,7 @@ mcu_r5fss0_core0: r5f@41000000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; mcu_r5fss0_core1: r5f@41400000 { @@ -719,6 +721,7 @@ mcu_r5fss0_core1: r5f@41400000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index a9dbe14fb0c9..f252007262d3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -572,24 +572,32 @@ mbox_c71_1: mbox-c71-1 { }; }; +&mcu_r5fss0 { + status = "okay"; +}; + &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status = "okay"; }; &mcu_r5fss0_core1 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + status = "okay"; }; &main_r5fss0 { ti,cluster-mode = <0>; + status = "okay"; }; &main_r5fss1 { ti,cluster-mode = <0>; + status = "okay"; }; /* Timers are used by Remoteproc firmware */ @@ -621,24 +629,28 @@ &main_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status = "okay"; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status = "okay"; }; &main_r5fss1_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status = "okay"; }; &main_r5fss1_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status = "okay"; }; &c71_0 { From fa1b98ddfa1d44a98f70d7480c87f33f8d29c8d7 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:57:56 +0530 Subject: [PATCH 702/931] arm64: dts: ti: k3-j784s4-j742s2: Enable remote processors at board level Remote Processors defined in top-level J784S4-J742S2 common SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis Link: https://patch.msgid.link/20250908142826.1828676-5-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 15 +++++++++++++++ .../boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 7 +++++++ .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 9 +++++++++ .../ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi | 3 +++ 4 files changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index f4f7b89bf0d2..af8eafc3f54a 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -992,24 +992,32 @@ &mcu_cpsw_port1 { bootph-all; }; +&mcu_r5fss0 { + status = "okay"; +}; + &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status = "okay"; }; &mcu_r5fss0_core1 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; + status = "okay"; }; &main_r5fss0 { ti,cluster-mode = <0>; + status = "okay"; }; &main_r5fss1 { ti,cluster-mode = <0>; + status = "okay"; }; /* Timers are used by Remoteproc firmware */ @@ -1055,42 +1063,49 @@ &main_timer9 { &main_r5fss2 { ti,cluster-mode = <0>; + status = "okay"; }; &main_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status = "okay"; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status = "okay"; }; &main_r5fss1_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status = "okay"; }; &main_r5fss1_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status = "okay"; }; &main_r5fss2_core0 { mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; memory-region = <&main_r5fss2_core0_dma_memory_region>, <&main_r5fss2_core0_memory_region>; + status = "okay"; }; &main_r5fss2_core1 { mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; memory-region = <&main_r5fss2_core1_dma_memory_region>, <&main_r5fss2_core1_memory_region>; + status = "okay"; }; &c71_0 { diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index 6afa802544e9..c269e5b29b96 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -1154,6 +1154,10 @@ mbox_c71_2: mbox-c71-2 { }; }; +&mcu_r5fss0 { + status = "okay"; +}; + &mcu_r5fss0_core0 { status = "okay"; mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; @@ -1170,14 +1174,17 @@ &mcu_r5fss0_core1 { &main_r5fss0 { ti,cluster-mode = <0>; + status = "okay"; }; &main_r5fss1 { ti,cluster-mode = <0>; + status = "okay"; }; &main_r5fss2 { ti,cluster-mode = <0>; + status = "okay"; }; /* Timers are used by Remoteproc firmware */ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index fbbe768e7a30..9cc0901d58fb 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -2174,6 +2174,7 @@ main_r5fss0: r5fss@5c00000 { ranges = <0x5c00000 0x00 0x5c00000 0x20000>, <0x5d00000 0x00 0x5d00000 0x20000>; power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss0_core0: r5f@5c00000 { compatible = "ti,j721s2-r5f"; @@ -2188,6 +2189,7 @@ main_r5fss0_core0: r5f@5c00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss0_core1: r5f@5d00000 { @@ -2203,6 +2205,7 @@ main_r5fss0_core1: r5f@5d00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; @@ -2214,6 +2217,7 @@ main_r5fss1: r5fss@5e00000 { ranges = <0x5e00000 0x00 0x5e00000 0x20000>, <0x5f00000 0x00 0x5f00000 0x20000>; power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss1_core0: r5f@5e00000 { compatible = "ti,j721s2-r5f"; @@ -2228,6 +2232,7 @@ main_r5fss1_core0: r5f@5e00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss1_core1: r5f@5f00000 { @@ -2243,6 +2248,7 @@ main_r5fss1_core1: r5f@5f00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; @@ -2254,6 +2260,7 @@ main_r5fss2: r5fss@5900000 { ranges = <0x5900000 0x00 0x5900000 0x20000>, <0x5a00000 0x00 0x5a00000 0x20000>; power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss2_core0: r5f@5900000 { compatible = "ti,j721s2-r5f"; @@ -2268,6 +2275,7 @@ main_r5fss2_core0: r5f@5900000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss2_core1: r5f@5a00000 { @@ -2283,6 +2291,7 @@ main_r5fss2_core1: r5f@5a00000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi index 52e2965a3bf5..cc22bfb5f599 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi @@ -595,6 +595,7 @@ mcu_r5fss0: r5fss@41000000 { ranges = <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; mcu_r5fss0_core0: r5f@41000000 { compatible = "ti,j721s2-r5f"; @@ -609,6 +610,7 @@ mcu_r5fss0_core0: r5f@41000000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; mcu_r5fss0_core1: r5f@41400000 { @@ -624,6 +626,7 @@ mcu_r5fss0_core1: r5f@41400000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; From ec158a0883c90528bbc1ec960a9b990d49a34099 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:57:57 +0530 Subject: [PATCH 703/931] arm64: dts: ti: k3-am62p-j722s: Enable remote processors at board level Remote Processors defined in top-level AM62P-J722S common SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Tested-by: Judith Mendez Reviewed-by: Dhruva Gole Acked-by: Andrew Davis Link: https://patch.msgid.link/20250908142826.1828676-6-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 ++ arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts | 3 +++ arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 3 +++ arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 1 + 6 files changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi index bd6a00d13aea..5288c959f3c1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi @@ -205,6 +205,7 @@ mcu_r5fss0_core0: r5f@79000000 { ti,atcm-enable = <0>; ti,btcm-enable = <1>; ti,loczrama = <0>; + status = "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi index 6757b37a9de3..8612b45e665c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi @@ -136,6 +136,7 @@ wkup_r5fss0_core0: r5f@78000000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 899da7896563..2755598fd1f5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -725,6 +725,7 @@ &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status = "okay"; }; &mcu_r5fss0 { @@ -735,6 +736,7 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status = "okay"; }; &main_uart0 { diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts index bf9b23df1da2..b329e4cb0c37 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts @@ -515,6 +515,7 @@ &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status = "okay"; }; &mcu_r5fss0 { @@ -525,6 +526,7 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status = "okay"; }; &main_r5fss0 { @@ -535,6 +537,7 @@ &main_r5fss0_core0 { mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status = "okay"; }; &c7x_0 { diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 9d8abfa9afd2..2b9e007432a9 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -850,6 +850,7 @@ &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status = "okay"; }; &mcu_r5fss0 { @@ -860,6 +861,7 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status = "okay"; }; &main_r5fss0 { @@ -870,6 +872,7 @@ &main_r5fss0_core0 { mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status = "okay"; }; &c7x_0 { diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 993828872dfb..d57fdd38bdce 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -368,6 +368,7 @@ main_r5fss0_core0: r5f@78400000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; From bdc921171dbe13fdc41589d44217d560299bbd5c Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:57:58 +0530 Subject: [PATCH 704/931] arm64: dts: ti: k3-am62: Enable remote processors at board level Remote Processors defined in top-level AM62x SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Tested-by: Wadim Egorov Reviewed-by: Wadim Egorov Reviewed-by: Dhruva Gole Acked-by: Andrew Davis Link: https://patch.msgid.link/20250908142826.1828676-7-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index 10e6b5c08619..dcd22ff487ec 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -407,4 +407,5 @@ &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index 6549b7efa656..75aed3a88284 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -128,6 +128,7 @@ wkup_r5fss0_core0: r5f@78000000 { ti,sci = <&dmsc>; ti,sci-dev-id = <121>; ti,sci-proc-ids = <0x01 0xff>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 13e1d36123d5..840772060cb1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -506,6 +506,7 @@ &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status = "okay"; }; &usbss0 { From f927049553dfaa27acc099b21095ee488b199687 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:57:59 +0530 Subject: [PATCH 705/931] arm64: dts: ti: k3-am62a: Enable remote processors at board level Remote Processors defined in top-level AM62A SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Tested-by: Judith Mendez Acked-by: Andrew Davis Link: https://patch.msgid.link/20250908142826.1828676-8-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 ++ arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 1 + 5 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi index ee961ced7208..d22caa7c346b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -197,6 +197,7 @@ mcu_r5fss0_core0: r5f@79000000 { ti,sci = <&dmsc>; ti,sci-dev-id = <9>; ti,sci-proc-ids = <0x03 0xff>; + status = "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index 207ca00630d1..403adfbf7dce 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -406,6 +406,7 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status = "okay"; }; &ospi0 { @@ -444,4 +445,5 @@ &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index 9ef1c829a9df..23877dadc98d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -127,6 +127,7 @@ wkup_r5fss0_core0: r5f@78000000 { ti,sci = <&dmsc>; ti,sci-dev-id = <121>; ti,sci-proc-ids = <0x01 0xff>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index bceead5e288e..03291862f07a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -870,6 +870,7 @@ &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status = "okay"; }; &mcu_r5fss0 { @@ -880,6 +881,7 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status = "okay"; }; &c7x_0 { diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts index daea18b0bc61..d45fc42b03f3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -586,6 +586,7 @@ &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status = "okay"; bootph-pre-ram; }; From 93b4ff5b86e5bc53aeba3a0193597ba31a4e5839 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:00 +0530 Subject: [PATCH 706/931] arm64: dts: ti: k3-am64: Enable remote processors at board level Remote Processors defined in top-level AM64x SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Tested-by: Wadim Egorov # phycore-am64x Tested-by: Hari Nagalla Reviewed-by: Wadim Egorov Acked-by: Andrew Davis Link: https://patch.msgid.link/20250908142826.1828676-9-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 12 ++++++++++++ 6 files changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index c7e5da37486a..d872cc671094 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -921,6 +921,7 @@ main_r5fss0: r5fss@78000000 { <0x78200000 0x00 0x78200000 0x08000>, <0x78300000 0x00 0x78300000 0x08000>; power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss0_core0: r5f@78000000 { compatible = "ti,am64-r5f"; @@ -935,6 +936,7 @@ main_r5fss0_core0: r5f@78000000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss0_core1: r5f@78200000 { @@ -950,6 +952,7 @@ main_r5fss0_core1: r5f@78200000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; @@ -963,6 +966,7 @@ main_r5fss1: r5fss@78400000 { <0x78600000 0x00 0x78600000 0x08000>, <0x78700000 0x00 0x78700000 0x08000>; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; main_r5fss1_core0: r5f@78400000 { compatible = "ti,am64-r5f"; @@ -977,6 +981,7 @@ main_r5fss1_core0: r5f@78400000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; main_r5fss1_core1: r5f@78600000 { @@ -992,6 +997,7 @@ main_r5fss1_core1: r5f@78600000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index d9d491b12c33..03c46d74ebb5 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -349,28 +349,40 @@ &main_pktdma { bootph-all; }; +&main_r5fss0 { + status = "okay"; +}; + &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status = "okay"; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status = "okay"; +}; + +&main_r5fss1 { + status = "okay"; }; &main_r5fss1_core0 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status = "okay"; }; &main_r5fss1_core1 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status = "okay"; }; &mcu_m4fss { diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index e01866372293..a07503b192c9 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -764,28 +764,40 @@ mbox_m4_0: mbox-m4-0 { }; }; +&main_r5fss0 { + status = "okay"; +}; + &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status = "okay"; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status = "okay"; +}; + +&main_r5fss1 { + status = "okay"; }; &main_r5fss1_core0 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status = "okay"; }; &main_r5fss1_core1 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status = "okay"; }; &mcu_m4fss { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 1deaa0be0085..ae4a6552644c 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -679,28 +679,40 @@ mbox_m4_0: mbox-m4-0 { }; }; +&main_r5fss0 { + status = "okay"; +}; + &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status = "okay"; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status = "okay"; +}; + +&main_r5fss1 { + status = "okay"; }; &main_r5fss1_core0 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status = "okay"; }; &main_r5fss1_core1 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status = "okay"; }; &mcu_m4fss { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi index a5cec9a07510..d0c1e4dc1da7 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -488,28 +488,40 @@ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB0_DRVVBUS */ }; }; +&main_r5fss0 { + status = "okay"; +}; + &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status = "okay"; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status = "okay"; +}; + +&main_r5fss1 { + status = "okay"; }; &main_r5fss1_core0 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status = "okay"; }; &main_r5fss1_core1 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status = "okay"; }; /* SoC default UART console */ diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi index 828d815d6bdf..876cbb21961d 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -167,28 +167,40 @@ mbox_m4_0: mbox-m4-0 { }; }; +&main_r5fss0 { + status = "okay"; +}; + &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; + status = "okay"; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; + status = "okay"; +}; + +&main_r5fss1 { + status = "okay"; }; &main_r5fss1_core0 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; + status = "okay"; }; &main_r5fss1_core1 { mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; + status = "okay"; }; &ospi0 { From c3fc9c1c1ac8f64ef333858ea42676889448a248 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:01 +0530 Subject: [PATCH 707/931] arm64: dts: ti: k3-am65: Enable remote processors at board level Remote Processors defined in top-level AM65x SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis Link: https://patch.msgid.link/20250908142826.1828676-10-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 6 ++++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index e5136ed94765..73936994a156 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -602,16 +602,22 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { }; }; +&mcu_r5fss0 { + status = "okay"; +}; + &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + status = "okay"; }; &mcu_r5fss0_core1 { memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; + status = "okay"; }; &mcu_rti1 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 7cf1f646500a..f6d9a5779918 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -408,6 +408,7 @@ mcu_r5fss0: r5fss@41000000 { ranges = <0x41000000 0x00 0x41000000 0x20000>, <0x41400000 0x00 0x41400000 0x20000>; power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; mcu_r5fss0_core0: r5f@41000000 { compatible = "ti,am654-r5f"; @@ -422,6 +423,7 @@ mcu_r5fss0_core0: r5f@41000000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; mcu_r5fss0_core1: r5f@41400000 { @@ -437,6 +439,7 @@ mcu_r5fss0_core1: r5f@41400000 { ti,atcm-enable = <1>; ti,btcm-enable = <1>; ti,loczrama = <1>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index e589690c7c82..39c2d46801de 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -541,16 +541,22 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { }; }; +&mcu_r5fss0 { + status = "okay"; +}; + &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + status = "okay"; }; &mcu_r5fss0_core1 { memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; + status = "okay"; }; &ospi0 { From bc590db1b5fe999d056ba66dc1990288c14f1ec3 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:02 +0530 Subject: [PATCH 708/931] arm64: dts: ti: k3-am62: Enable Mailbox nodes at the board level Mailbox nodes defined in the top-level AM62x SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Beleswar Padhi Reviewed-by: Dhruva Gole Acked-by: Andrew Davis Link: https://patch.msgid.link/20250908142826.1828676-11-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts | 2 ++ arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 2 ++ 3 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 029380dc1a35..40fb3c9e674c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -808,6 +808,7 @@ mailbox0_cluster0: mailbox@29000000 { #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; ecap0: pwm@23100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts index 2e4cf65ee323..2eee5f638e0f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts @@ -293,6 +293,8 @@ &epwm2 { }; &mailbox0_cluster0 { + status = "okay"; + mbox_m4_0: mbox-m4-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index bc2289d74774..bbf2d630b305 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -1317,6 +1317,8 @@ &main_i2c3 { }; &mailbox0_cluster0 { + status = "okay"; + mbox_m4_0: mbox-m4-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; From 9ca8079eb36b71a86bb5851d9d3b7a49da8e595f Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:03 +0530 Subject: [PATCH 709/931] arm64: dts: ti: k3-am62a: Enable Mailbox nodes at the board level Mailbox nodes defined in the top-level AM62A SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Beleswar Padhi Tested-by: Judith Mendez Acked-by: Andrew Davis Link: https://patch.msgid.link/20250908142826.1828676-12-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 9cad79d7bbc1..d5f018768981 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -804,6 +804,7 @@ mailbox0_cluster0: mailbox@29000000 { #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster1: mailbox@29010000 { @@ -813,6 +814,7 @@ mailbox0_cluster1: mailbox@29010000 { #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster2: mailbox@29020000 { @@ -822,6 +824,7 @@ mailbox0_cluster2: mailbox@29020000 { #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster3: mailbox@29030000 { @@ -831,6 +834,7 @@ mailbox0_cluster3: mailbox@29030000 { #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; main_mcan0: can@20701000 { From 4f1aee4723a796a92f17b23699dc861b582ddfd2 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:04 +0530 Subject: [PATCH 710/931] arm64: dts: ti: k3-am6*-boards: Add label to reserved-memory node Add the label name 'reserved_memory' to the reserved-memory node in all K3 AM6* board level dts files. This is done so that the node can be referenced and extended to add more carveout entries as needed in future refactoring patches. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis Link: https://patch.msgid.link/20250908142826.1828676-13-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 +- arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 2 +- arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 +- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 2 +- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 2 +- arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 2 +- 13 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index bbf2d630b305..cbbcb96e2e24 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -189,7 +189,7 @@ reg_usb0_vbus: regulator-usb0-vbus { regulator-name = "USB_1_EN"; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index 403adfbf7dce..3108e9b0c804 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -45,7 +45,7 @@ memory@80000000 { bootph-all; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 03291862f07a..7ebcfe8edfe1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -39,7 +39,7 @@ memory@80000000 { bootph-all; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts index d45fc42b03f3..41860ac42f3c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -39,7 +39,7 @@ memory@80000000 { bootph-all; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi index a2fdc6741da2..6a04b370d149 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -147,7 +147,7 @@ reg_vsodimm: regulator-vsodimm { regulator-name = "+V_SODIMM"; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 2755598fd1f5..c5b5b00c42b9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -44,7 +44,7 @@ memory@80000000 { bootph-pre-ram; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 840772060cb1..03b8e246d8c2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -36,7 +36,7 @@ memory@80000000 { reg = <0x00000000 0x80000000 0x00000000 0x80000000>; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index a07503b192c9..7640c5efe9b8 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -42,7 +42,7 @@ memory@80000000 { reg = <0x00000000 0x80000000 0x00000000 0x80000000>; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index ae4a6552644c..fb8bd66f2f94 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -40,7 +40,7 @@ memory@80000000 { reg = <0x00000000 0x80000000 0x00000000 0x80000000>; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi index d0c1e4dc1da7..81adae0a8e55 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -105,7 +105,7 @@ memory@80000000 { device_type = "memory"; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi index 876cbb21961d..40b619c9a6c9 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -20,7 +20,7 @@ memory@80000000 { }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 73936994a156..6cd499ea53e7 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -36,7 +36,7 @@ chosen { stdout-path = "serial3:115200n8"; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 39c2d46801de..e532ea0a22b2 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -39,7 +39,7 @@ memory@80000000 { <0x00000008 0x80000000 0x00000000 0x80000000>; }; - reserved-memory { + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; From aee0678597c63e5427e91b2e49a6c5ed4951f277 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:05 +0530 Subject: [PATCH 711/931] arm64: dts: ti: k3: Rename rproc reserved-mem nodes to 'memory@addr' Currently, the reserved memory carveouts used by remote processors are named like 'rproc-name--memory-region@addr'. While it is descriptive, the node label already serves that purpose. Rename reserved memory nodes to generic 'memory@addr' to align with the device tree specifications. This is done for all TI K3 based boards. Signed-off-by: Beleswar Padhi Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20250908142826.1828676-14-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am62-phycore-som.dtsi | 10 ++-- .../boot/dts/ti/k3-am62-pocketbeagle2.dts | 6 +-- arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 2 +- .../arm64/boot/dts/ti/k3-am625-beagleplay.dts | 2 +- .../boot/dts/ti/k3-am62a-phycore-som.dtsi | 12 ++--- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 12 ++--- arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 14 +++--- arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 8 ++-- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 8 ++-- .../boot/dts/ti/k3-am64-phycore-som.dtsi | 22 ++++----- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 22 ++++----- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 22 ++++----- arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 16 +++---- .../arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 18 +++---- .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 10 ++-- .../arm64/boot/dts/ti/k3-am654-base-board.dts | 10 ++-- .../arm64/boot/dts/ti/k3-am67a-beagley-ai.dts | 22 ++++----- .../boot/dts/ti/k3-am68-phycore-som.dtsi | 34 ++++++------- arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 34 ++++++------- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 48 +++++++++---------- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 18 +++---- .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 38 +++++++-------- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 38 +++++++-------- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 38 +++++++-------- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 34 ++++++------- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 22 ++++----- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 4 +- .../dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 44 ++++++++--------- 29 files changed, 285 insertions(+), 285 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index dcd22ff487ec..75b7e64f6659 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -46,31 +46,31 @@ ramoops@9c700000 { pmsg-size = <0x8000>; }; - rtos_ipc_memory_region: ipc-memories@9c800000 { + rtos_ipc_memory_region: memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x00300000>; no-map; }; - mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + mcu_m4fss_dma_memory_region: memory@9cb00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9cb00000 0x00 0x100000>; no-map; }; - mcu_m4fss_memory_region: m4f-memory@9cc00000 { + mcu_m4fss_memory_region: memory@9cc00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9cc00000 0x00 0xe00000>; no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9da00000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { + wkup_r5fss0_core0_memory_region: memory@9db00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9db00000 0x00 0xc00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts index 2eee5f638e0f..2d46be298b0b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts @@ -54,13 +54,13 @@ linux,cma { linux,cma-default; }; - mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + mcu_m4fss_dma_memory_region: memory@9cb00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9cb00000 0x00 0x100000>; no-map; }; - mcu_m4fss_memory_region: m4f-memory@9cc00000 { + mcu_m4fss_memory_region: memory@9cc00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9cc00000 0x00 0xe00000>; no-map; @@ -78,7 +78,7 @@ secure_ddr: optee@9e800000 { no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9db00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9db00000 0x00 0xc00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index cbbcb96e2e24..9384c9a0232a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -206,7 +206,7 @@ secure_ddr: optee@9e800000 { no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9db00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9db00000 0x00 0xc00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index 72b09f9c69d8..7028d9835c4a 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -83,7 +83,7 @@ secure_ddr: optee@9e800000 { no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9db00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9db00000 0x00 0xc00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index 3108e9b0c804..0406a43ff704 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -59,37 +59,37 @@ linux,cma { linux,cma-default; }; - c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + c7x_0_dma_memory_region: memory@99800000 { compatible = "shared-dma-pool"; reg = <0x00 0x99800000 0x00 0x100000>; no-map; }; - c7x_0_memory_region: c7x-memory@99900000 { + c7x_0_memory_region: memory@99900000 { compatible = "shared-dma-pool"; reg = <0x00 0x99900000 0x00 0xf00000>; no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9b800000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + mcu_r5fss0_core0_memory_region: memory@9b900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9b900000 0x00 0xf00000>; no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c900000 0x00 0xf00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 7ebcfe8edfe1..312bdab28784 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -53,37 +53,37 @@ linux,cma { linux,cma-default; }; - c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + c7x_0_dma_memory_region: memory@99800000 { compatible = "shared-dma-pool"; reg = <0x00 0x99800000 0x00 0x100000>; no-map; }; - c7x_0_memory_region: c7x-memory@99900000 { + c7x_0_memory_region: memory@99900000 { compatible = "shared-dma-pool"; reg = <0x00 0x99900000 0x00 0xf00000>; no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9b800000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + mcu_r5fss0_core0_memory_region: memory@9b900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9b900000 0x00 0xf00000>; no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c900000 0x00 0xf00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts index 41860ac42f3c..289f52b3481f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -58,37 +58,37 @@ secure_tfa_ddr: tfa@80000000 { no-map; }; - c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + c7x_0_dma_memory_region: memory@99800000 { compatible = "shared-dma-pool"; reg = <0x00 0x99800000 0x00 0x100000>; no-map; }; - c7x_0_memory_region: c7x-memory@99900000 { + c7x_0_memory_region: memory@99900000 { compatible = "shared-dma-pool"; reg = <0x00 0x99900000 0x00 0xf00000>; no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9b800000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + mcu_r5fss0_core0_memory_region: memory@9b900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9b900000 0x00 0xf00000>; no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c900000 0x00 0xf00000>; no-map; @@ -100,7 +100,7 @@ secure_ddr: optee@9e800000 { no-map; }; - rtos_ipc_memory_region: ipc-memories@a0000000 { + rtos_ipc_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x01000000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi index 6a04b370d149..522d6f029c36 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -162,7 +162,7 @@ secure_ddr: optee@9e800000 { no-map; }; - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c900000 0x00 0x01e00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index c5b5b00c42b9..aa363aaf6d59 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -49,25 +49,25 @@ reserved_memory: reserved-memory { #size-cells = <2>; ranges; - mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 { + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9b800000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { + mcu_r5fss0_core0_memory_region: memory@9b900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9b900000 0x00 0xf00000>; no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c900000 0x00 0xf00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 03b8e246d8c2..05cba3cfc79e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -58,25 +58,25 @@ linux,cma { linux,cma-default; }; - mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + mcu_m4fss_dma_memory_region: memory@9cb00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9cb00000 0x00 0x100000>; no-map; }; - mcu_m4fss_memory_region: m4f-memory@9cc00000 { + mcu_m4fss_memory_region: memory@9cc00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9cc00000 0x00 0xe00000>; no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9da00000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { + wkup_r5fss0_core0_memory_region: memory@9db00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9db00000 0x00 0xc00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 03c46d74ebb5..ba425b125d63 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -41,67 +41,67 @@ secure_ddr: optee@9e800000 { no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + main_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + main_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + main_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + main_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss1_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + main_r5fss1_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss1_core1_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + main_r5fss1_core1_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + mcu_m4fss_dma_memory_region: memory@a4000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4000000 0x00 0x100000>; no-map; }; - mcu_m4fss_memory_region: m4f-memory@a4100000 { + mcu_m4fss_memory_region: memory@a4100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; - rtos_ipc_memory_region: ipc-memories@a5000000 { + rtos_ipc_memory_region: memory@a5000000 { reg = <0x00 0xa5000000 0x00 0x00800000>; alignment = <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 7640c5efe9b8..ebc9fedc4d72 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -53,67 +53,67 @@ secure_ddr: optee@9e800000 { no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + main_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + main_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + main_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + main_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss1_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + main_r5fss1_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss1_core1_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + main_r5fss1_core1_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + mcu_m4fss_dma_memory_region: memory@a4000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4000000 0x00 0x100000>; no-map; }; - mcu_m4fss_memory_region: m4f-memory@a4100000 { + mcu_m4fss_memory_region: memory@a4100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; - rtos_ipc_memory_region: ipc-memories@a5000000 { + rtos_ipc_memory_region: memory@a5000000 { reg = <0x00 0xa5000000 0x00 0x00800000>; alignment = <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index fb8bd66f2f94..d2b06e508c7f 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -51,67 +51,67 @@ secure_ddr: optee@9e800000 { no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + main_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + main_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + main_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + main_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss1_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + main_r5fss1_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss1_core1_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + main_r5fss1_core1_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + mcu_m4fss_dma_memory_region: memory@a4000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4000000 0x00 0x100000>; no-map; }; - mcu_m4fss_memory_region: m4f-memory@a4100000 { + mcu_m4fss_memory_region: memory@a4100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; - rtos_ipc_memory_region: ipc-memories@a5000000 { + rtos_ipc_memory_region: memory@a5000000 { reg = <0x00 0xa5000000 0x00 0x00800000>; alignment = <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi index 81adae0a8e55..35294a5c46d5 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -115,49 +115,49 @@ secure_ddr: optee@9e800000 { no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + main_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + main_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + main_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + main_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss1_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + main_r5fss1_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss1_core1_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + main_r5fss1_core1_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi index 40b619c9a6c9..4068d2c2b10c 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -31,55 +31,55 @@ secure_ddr: optee@9e800000 { no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + main_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + main_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + main_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + main_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss1_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + main_r5fss1_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss1_core1_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + main_r5fss1_core1_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; - rtos_ipc_memory_region: ipc-memories@a5000000 { + rtos_ipc_memory_region: memory@a5000000 { reg = <0x00 0xa5000000 0x00 0x00800000>; alignment = <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 6cd499ea53e7..df2eed0b4048 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -47,31 +47,31 @@ secure_ddr: secure-ddr@9e800000 { no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0 0xa0000000 0 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0 0xa0100000 0 0xf00000>; no-map; }; - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0 0xa1000000 0 0x100000>; no-map; }; - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0 0xa1100000 0 0xf00000>; no-map; }; - rtos_ipc_memory_region: ipc-memories@a2000000 { + rtos_ipc_memory_region: memory@a2000000 { reg = <0x00 0xa2000000 0x00 0x00200000>; alignment = <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index e532ea0a22b2..3ca771a4f9c7 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -50,31 +50,31 @@ secure_ddr: secure-ddr@9e800000 { no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0 0xa0000000 0 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0 0xa0100000 0 0xf00000>; no-map; }; - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0 0xa1000000 0 0x100000>; no-map; }; - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0 0xa1100000 0 0xf00000>; no-map; }; - rtos_ipc_memory_region: ipc-memories@a2000000 { + rtos_ipc_memory_region: memory@a2000000 { reg = <0x00 0xa2000000 0x00 0x00100000>; alignment = <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts index b329e4cb0c37..85436ea5b4e7 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts @@ -50,67 +50,67 @@ secure_ddr: optee@9e800000 { no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + wkup_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { + wkup_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { + mcu_r5fss0_core0_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { + c7x_0_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - c7x_0_memory_region: c7x-memory@a3100000 { + c7x_0_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; - c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { + c7x_1_dma_memory_region: memory@a4000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4000000 0x00 0x100000>; no-map; }; - c7x_1_memory_region: c7x-memory@a4100000 { + c7x_1_memory_region: memory@a4100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; - rtos_ipc_memory_region: ipc-memories@a5000000 { + rtos_ipc_memory_region: memory@a5000000 { reg = <0x00 0xa5000000 0x00 0x1c00000>; alignment = <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi index 383594732e81..b9c60e078d21 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi @@ -49,103 +49,103 @@ secure_ddr: optee@9e800000 { no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4000000 0x00 0x100000>; no-map; }; - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5000000 0x00 0x100000>; no-map; }; - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5100000 0x00 0xf00000>; no-map; }; - c71_0_dma_memory_region: c71-dma-memory@a6000000 { + c71_0_dma_memory_region: memory@a6000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6000000 0x00 0x100000>; no-map; }; - c71_0_memory_region: c71-memory@a6100000 { + c71_0_memory_region: memory@a6100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6100000 0x00 0xf00000>; no-map; }; - c71_1_dma_memory_region: c71-dma-memory@a7000000 { + c71_1_dma_memory_region: memory@a7000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7000000 0x00 0x100000>; no-map; }; - c71_1_memory_region: c71-memory@a7100000 { + c71_1_memory_region: memory@a7100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7100000 0x00 0xf00000>; no-map; }; - rtos_ipc_memory_region: ipc-memories@a8000000 { + rtos_ipc_memory_region: memory@a8000000 { reg = <0x00 0xa8000000 0x00 0x01c00000>; alignment = <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi index 2d2edeeb7347..c423b1443e0c 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -27,103 +27,103 @@ secure_ddr: optee@9e800000 { no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4000000 0x00 0x100000>; no-map; }; - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5000000 0x00 0x100000>; no-map; }; - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5100000 0x00 0xf00000>; no-map; }; - c71_0_dma_memory_region: c71-dma-memory@a6000000 { + c71_0_dma_memory_region: memory@a6000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6000000 0x00 0x100000>; no-map; }; - c71_0_memory_region: c71-memory@a6100000 { + c71_0_memory_region: memory@a6100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6100000 0x00 0xf00000>; no-map; }; - c71_1_dma_memory_region: c71-dma-memory@a7000000 { + c71_1_dma_memory_region: memory@a7000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7000000 0x00 0x100000>; no-map; }; - c71_1_memory_region: c71-memory@a7100000 { + c71_1_memory_region: memory@a7100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7100000 0x00 0xf00000>; no-map; }; - rtos_ipc_memory_region: ipc-memories@a8000000 { + rtos_ipc_memory_region: memory@a8000000 { reg = <0x00 0xa8000000 0x00 0x01c00000>; alignment = <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index af8eafc3f54a..60817c1f3104 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -49,145 +49,145 @@ secure_ddr: optee@9e800000 { no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4000000 0x00 0x100000>; no-map; }; - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5000000 0x00 0x100000>; no-map; }; - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5100000 0x00 0xf00000>; no-map; }; - main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { + main_r5fss2_core0_dma_memory_region: memory@a6000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6000000 0x00 0x100000>; no-map; }; - main_r5fss2_core0_memory_region: r5f-memory@a6100000 { + main_r5fss2_core0_memory_region: memory@a6100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6100000 0x00 0xf00000>; no-map; }; - main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { + main_r5fss2_core1_dma_memory_region: memory@a7000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7000000 0x00 0x100000>; no-map; }; - main_r5fss2_core1_memory_region: r5f-memory@a7100000 { + main_r5fss2_core1_memory_region: memory@a7100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7100000 0x00 0xf00000>; no-map; }; - c71_0_dma_memory_region: c71-dma-memory@a8000000 { + c71_0_dma_memory_region: memory@a8000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa8000000 0x00 0x100000>; no-map; }; - c71_0_memory_region: c71-memory@a8100000 { + c71_0_memory_region: memory@a8100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa8100000 0x00 0xf00000>; no-map; }; - c71_1_dma_memory_region: c71-dma-memory@a9000000 { + c71_1_dma_memory_region: memory@a9000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa9000000 0x00 0x100000>; no-map; }; - c71_1_memory_region: c71-memory@a9100000 { + c71_1_memory_region: memory@a9100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa9100000 0x00 0xf00000>; no-map; }; - c71_2_dma_memory_region: c71-dma-memory@aa000000 { + c71_2_dma_memory_region: memory@aa000000 { compatible = "shared-dma-pool"; reg = <0x00 0xaa000000 0x00 0x100000>; no-map; }; - c71_2_memory_region: c71-memory@aa100000 { + c71_2_memory_region: memory@aa100000 { compatible = "shared-dma-pool"; reg = <0x00 0xaa100000 0x00 0xf00000>; no-map; }; - c71_3_dma_memory_region: c71-dma-memory@ab000000 { + c71_3_dma_memory_region: memory@ab000000 { compatible = "shared-dma-pool"; reg = <0x00 0xab000000 0x00 0x100000>; no-map; }; - c71_3_memory_region: c71-memory@ab100000 { + c71_3_memory_region: memory@ab100000 { compatible = "shared-dma-pool"; reg = <0x00 0xab100000 0x00 0xf00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 90befcdc8d08..c689e417cf45 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -29,55 +29,55 @@ secure_ddr: optee@9e800000 { no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; - rtos_ipc_memory_region: ipc-memories@a4000000 { + rtos_ipc_memory_region: memory@a4000000 { reg = <0x00 0xa4000000 0x00 0x00800000>; alignment = <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 0d1a313a7d10..ac4d90e82aab 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -51,115 +51,115 @@ secure_ddr: optee@9e800000 { no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4000000 0x00 0x100000>; no-map; }; - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5000000 0x00 0x100000>; no-map; }; - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5100000 0x00 0xf00000>; no-map; }; - c66_0_dma_memory_region: c66-dma-memory@a6000000 { + c66_0_dma_memory_region: memory@a6000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6000000 0x00 0x100000>; no-map; }; - c66_0_memory_region: c66-memory@a6100000 { + c66_0_memory_region: memory@a6100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6100000 0x00 0xf00000>; no-map; }; - c66_1_dma_memory_region: c66-dma-memory@a7000000 { + c66_1_dma_memory_region: memory@a7000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7000000 0x00 0x100000>; no-map; }; - c66_1_memory_region: c66-memory@a7100000 { + c66_1_memory_region: memory@a7100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7100000 0x00 0xf00000>; no-map; }; - c71_0_dma_memory_region: c71-dma-memory@a8000000 { + c71_0_dma_memory_region: memory@a8000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa8000000 0x00 0x100000>; no-map; }; - c71_0_memory_region: c71-memory@a8100000 { + c71_0_memory_region: memory@a8100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa8100000 0x00 0xf00000>; no-map; }; - rtos_ipc_memory_region: ipc-memories@aa000000 { + rtos_ipc_memory_region: memory@aa000000 { reg = <0x00 0xaa000000 0x00 0x01c00000>; alignment = <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 62b9c13a91e7..0f05e65f7bf7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -48,115 +48,115 @@ secure_ddr: optee@9e800000 { no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4000000 0x00 0x100000>; no-map; }; - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5000000 0x00 0x100000>; no-map; }; - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5100000 0x00 0xf00000>; no-map; }; - c66_0_dma_memory_region: c66-dma-memory@a6000000 { + c66_0_dma_memory_region: memory@a6000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6000000 0x00 0x100000>; no-map; }; - c66_0_memory_region: c66-memory@a6100000 { + c66_0_memory_region: memory@a6100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6100000 0x00 0xf00000>; no-map; }; - c66_1_dma_memory_region: c66-dma-memory@a7000000 { + c66_1_dma_memory_region: memory@a7000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7000000 0x00 0x100000>; no-map; }; - c66_1_memory_region: c66-memory@a7100000 { + c66_1_memory_region: memory@a7100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7100000 0x00 0xf00000>; no-map; }; - c71_0_dma_memory_region: c71-dma-memory@a8000000 { + c71_0_dma_memory_region: memory@a8000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa8000000 0x00 0x100000>; no-map; }; - c71_0_memory_region: c71-memory@a8100000 { + c71_0_memory_region: memory@a8100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa8100000 0x00 0xf00000>; no-map; }; - rtos_ipc_memory_region: ipc-memories@aa000000 { + rtos_ipc_memory_region: memory@aa000000 { reg = <0x00 0xaa000000 0x00 0x01c00000>; alignment = <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 795b041ee733..06388f28d122 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -29,115 +29,115 @@ secure_ddr: optee@9e800000 { no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4000000 0x00 0x100000>; no-map; }; - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5000000 0x00 0x100000>; no-map; }; - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5100000 0x00 0xf00000>; no-map; }; - c66_1_dma_memory_region: c66-dma-memory@a6000000 { + c66_1_dma_memory_region: memory@a6000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6000000 0x00 0x100000>; no-map; }; - c66_0_memory_region: c66-memory@a6100000 { + c66_0_memory_region: memory@a6100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6100000 0x00 0xf00000>; no-map; }; - c66_0_dma_memory_region: c66-dma-memory@a7000000 { + c66_0_dma_memory_region: memory@a7000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7000000 0x00 0x100000>; no-map; }; - c66_1_memory_region: c66-memory@a7100000 { + c66_1_memory_region: memory@a7100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7100000 0x00 0xf00000>; no-map; }; - c71_0_dma_memory_region: c71-dma-memory@a8000000 { + c71_0_dma_memory_region: memory@a8000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa8000000 0x00 0x100000>; no-map; }; - c71_0_memory_region: c71-memory@a8100000 { + c71_0_memory_region: memory@a8100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa8100000 0x00 0xf00000>; no-map; }; - rtos_ipc_memory_region: ipc-memories@aa000000 { + rtos_ipc_memory_region: memory@aa000000 { reg = <0x00 0xaa000000 0x00 0x01c00000>; alignment = <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index f252007262d3..ff5264d4c2da 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -31,103 +31,103 @@ secure_ddr: optee@9e800000 { no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4000000 0x00 0x100000>; no-map; }; - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5000000 0x00 0x100000>; no-map; }; - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5100000 0x00 0xf00000>; no-map; }; - c71_0_dma_memory_region: c71-dma-memory@a6000000 { + c71_0_dma_memory_region: memory@a6000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6000000 0x00 0x100000>; no-map; }; - c71_0_memory_region: c71-memory@a6100000 { + c71_0_memory_region: memory@a6100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6100000 0x00 0xf00000>; no-map; }; - c71_1_dma_memory_region: c71-dma-memory@a7000000 { + c71_1_dma_memory_region: memory@a7000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7000000 0x00 0x100000>; no-map; }; - c71_1_memory_region: c71-memory@a7100000 { + c71_1_memory_region: memory@a7100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7100000 0x00 0xf00000>; no-map; }; - rtos_ipc_memory_region: ipc-memories@a8000000 { + rtos_ipc_memory_region: memory@a8000000 { reg = <0x00 0xa8000000 0x00 0x01c00000>; alignment = <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 2b9e007432a9..d323284a30ab 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -52,67 +52,67 @@ secure_ddr: optee@9e800000 { no-map; }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + wkup_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { + wkup_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@a1000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@a1100000 { + mcu_r5fss0_core0_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core0_dma_memory_region: main-r5fss-dma-memory-region@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: main-r5fss-memory-region@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - c7x_0_dma_memory_region: c7x-dma-memory@a3000000 { + c7x_0_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - c7x_0_memory_region: c7x-memory@a3100000 { + c7x_0_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; - c7x_1_dma_memory_region: c7x-dma-memory@a4000000 { + c7x_1_dma_memory_region: memory@a4000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4000000 0x00 0x100000>; no-map; }; - c7x_1_memory_region: c7x-memory@a4100000 { + c7x_1_memory_region: memory@a4100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; - rtos_ipc_memory_region: ipc-memories@a5000000 { + rtos_ipc_memory_region: memory@a5000000 { reg = <0x00 0xa5000000 0x00 0x1c00000>; alignment = <0x1000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index a84bde08f85e..2ed1ec6d53c8 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -28,13 +28,13 @@ reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; - c71_3_dma_memory_region: c71-dma-memory@ab000000 { + c71_3_dma_memory_region: memory@ab000000 { compatible = "shared-dma-pool"; reg = <0x00 0xab000000 0x00 0x100000>; no-map; }; - c71_3_memory_region: c71-memory@ab100000 { + c71_3_memory_region: memory@ab100000 { compatible = "shared-dma-pool"; reg = <0x00 0xab100000 0x00 0xf00000>; no-map; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index c269e5b29b96..fdde1bd0e831 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -35,133 +35,133 @@ secure_ddr: optee@9e800000 { no-map; }; - mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + mcu_r5fss0_core0_dma_memory_region: memory@a0000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + mcu_r5fss0_core0_memory_region: memory@a0100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1000000 0x00 0x100000>; no-map; }; - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + mcu_r5fss0_core1_memory_region: memory@a1100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa1100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + main_r5fss0_core0_dma_memory_region: memory@a2000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2000000 0x00 0x100000>; no-map; }; - main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + main_r5fss0_core0_memory_region: memory@a2100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa2100000 0x00 0xf00000>; no-map; }; - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + main_r5fss0_core1_dma_memory_region: memory@a3000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3000000 0x00 0x100000>; no-map; }; - main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + main_r5fss0_core1_memory_region: memory@a3100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + main_r5fss1_core0_dma_memory_region: memory@a4000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4000000 0x00 0x100000>; no-map; }; - main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + main_r5fss1_core0_memory_region: memory@a4100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + main_r5fss1_core1_dma_memory_region: memory@a5000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5000000 0x00 0x100000>; no-map; }; - main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + main_r5fss1_core1_memory_region: memory@a5100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa5100000 0x00 0xf00000>; no-map; }; - main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { + main_r5fss2_core0_dma_memory_region: memory@a6000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6000000 0x00 0x100000>; no-map; }; - main_r5fss2_core0_memory_region: r5f-memory@a6100000 { + main_r5fss2_core0_memory_region: memory@a6100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6100000 0x00 0xf00000>; no-map; }; - main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { + main_r5fss2_core1_dma_memory_region: memory@a7000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7000000 0x00 0x100000>; no-map; }; - main_r5fss2_core1_memory_region: r5f-memory@a7100000 { + main_r5fss2_core1_memory_region: memory@a7100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7100000 0x00 0xf00000>; no-map; }; - c71_0_dma_memory_region: c71-dma-memory@a8000000 { + c71_0_dma_memory_region: memory@a8000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa8000000 0x00 0x100000>; no-map; }; - c71_0_memory_region: c71-memory@a8100000 { + c71_0_memory_region: memory@a8100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa8100000 0x00 0xf00000>; no-map; }; - c71_1_dma_memory_region: c71-dma-memory@a9000000 { + c71_1_dma_memory_region: memory@a9000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa9000000 0x00 0x100000>; no-map; }; - c71_1_memory_region: c71-memory@a9100000 { + c71_1_memory_region: memory@a9100000 { compatible = "shared-dma-pool"; reg = <0x00 0xa9100000 0x00 0xf00000>; no-map; }; - c71_2_dma_memory_region: c71-dma-memory@aa000000 { + c71_2_dma_memory_region: memory@aa000000 { compatible = "shared-dma-pool"; reg = <0x00 0xaa000000 0x00 0x100000>; no-map; }; - c71_2_memory_region: c71-memory@aa100000 { + c71_2_memory_region: memory@aa100000 { compatible = "shared-dma-pool"; reg = <0x00 0xaa100000 0x00 0xf00000>; no-map; From a564730142d5d23c197ca4b4741fb6a89e6f0c2c Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:06 +0530 Subject: [PATCH 712/931] arm64: dts: ti: k3-j721e-beagleboneai64: Add missing cfg for TI IPC FW The TI IPC Firmwares running on J721E SoCs use certain MAIN domain timers as tick. Reserve those at board level DT to avoid remote processor crashes. This config aligns with other J721E boards and can be refactored out later. Signed-off-by: Beleswar Padhi Link: https://patch.msgid.link/20250908142826.1828676-15-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index ac4d90e82aab..66c4614f9e42 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -935,6 +935,35 @@ mbox_c71_0: mbox-c71-0 { }; }; +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&main_timer12 { + status = "reserved"; +}; + +&main_timer13 { + status = "reserved"; +}; + +&main_timer14 { + status = "reserved"; +}; + +&main_timer15 { + status = "reserved"; +}; + &mcu_r5fss0 { status = "okay"; }; From fc4f6f0146d4c778859042a76b1e932b6334bf96 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:07 +0530 Subject: [PATCH 713/931] arm64: dts: ti: k3-am62p-verdin: Add missing cfg for TI IPC Firmware The wkup_r5fss0_core0_memory_region is used to store the text/data sections of the Device Manager (DM) firmware itself and is necessary for platform boot. Whereas the wkup_r5fss0_core0_dma_memory_region is used for allocating the Virtio buffers needed for IPC with the DM core which could be optional. The labels were incorrectly used in the k3-am62p-verdin.dtsi file. Correct the firmware memory region label. Currently, only mailbox node is enabled with FIFO assignment. However, there are no users of the enabled mailboxes. Add the missing carveouts for WKUP and MCU R5F remote processors, and enable those by associating to the above carveout and mailboxes. This config aligns with other AM62P boards and can be refactored out later. Signed-off-by: Beleswar Padhi Tested-by: Hiago De Franco # Verdin AM62P Acked-by: Francesco Dolcini Link: https://patch.msgid.link/20250908142826.1828676-16-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 40 +++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi index 522d6f029c36..671d367b40d1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -162,6 +162,24 @@ secure_ddr: optee@9e800000 { no-map; }; + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: memory@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + wkup_r5fss0_core0_memory_region: memory@9c900000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c900000 0x00 0x01e00000>; @@ -848,6 +866,28 @@ mbox_mcu_r5_0: mbox-mcu-r5-0 { }; }; +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status = "okay"; +}; + &main0_alert { temperature = <95000>; }; From a49f991e740f5f3917b4023705568aeb817ee773 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:08 +0530 Subject: [PATCH 714/931] arm64: dts: ti: k3-am62-verdin: Add missing cfg for TI IPC Firmware The wkup_r5fss0_core0_memory_region is used to store the text/data sections of the Device Manager (DM) firmware itself and is necessary for platform boot. Whereas the wkup_r5fss0_core0_dma_memory_region is used for allocating the Virtio buffers needed for IPC with the DM core which could be optional. The labels were incorrectly used in the k3-am62-verdin.dtsi file. Correct the firmware memory region label. Currently, only mailbox node is enabled with FIFO assignment for a single M4F remote core. However, there are no users of the enabled mailboxes. Add the missing carveouts for WKUP R5F and MCU M4F remote processors, and enable those by associating to the above carveout and mailboxes. This config aligns with other AM62 boards and can be refactored out later. Signed-off-by: Beleswar Padhi Tested-by: Hiago De Franco # Verdin AM62 Acked-by: Francesco Dolcini Link: https://patch.msgid.link/20250908142826.1828676-17-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 43 +++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index 9384c9a0232a..5ecdd833587e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -206,7 +206,25 @@ secure_ddr: optee@9e800000 { no-map; }; - wkup_r5fss0_core0_dma_memory_region: memory@9db00000 { + mcu_m4fss_dma_memory_region: memory@9cb00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: memory@9cc00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: memory@9db00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9db00000 0x00 0xc00000>; no-map; @@ -1323,6 +1341,29 @@ mbox_m4_0: mbox-m4-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; }; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mcu_m4fss { + mboxes = <&mailbox0_cluster0 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status = "okay"; }; /* Verdin CAN_1 */ From 6104984a7d1d8c17c724e799501a1be2a2a35a52 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:09 +0530 Subject: [PATCH 715/931] arm64: dts: ti: k3-am62-pocketbeagle2: Add missing cfg for TI IPC Firmware The wkup_r5fss0_core0_memory_region is used to store the text/data sections of the Device Manager (DM) firmware itself and is necessary for platform boot. Whereas the wkup_r5fss0_core0_dma_memory_region is used for allocating the Virtio buffers needed for IPC with the DM core which could be optional. The labels were incorrectly used in the k3-am62-pocketbeagle2.dts file. Correct the firmware memory region label Currently, only mailbox node is enabled with FIFO assignment for a single M4F remote core. Add the missing carveouts for WKUP R5F remote processor, and enable that by associating to the above carveout and mailbox. This config aligns with other AM62 boards and can be refactored out later. Signed-off-by: Beleswar Padhi Reviewed-by: Dhruva Gole Link: https://patch.msgid.link/20250908142826.1828676-18-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am62-pocketbeagle2.dts | 24 ++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts index 2d46be298b0b..621fb6c52db1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts @@ -78,7 +78,13 @@ secure_ddr: optee@9e800000 { no-map; }; - wkup_r5fss0_core0_dma_memory_region: memory@9db00000 { + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: memory@9db00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9db00000 0x00 0xc00000>; no-map; @@ -299,6 +305,11 @@ mbox_m4_0: mbox-m4-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; }; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; }; &main_uart0 { @@ -358,6 +369,17 @@ &mcu_m4fss { status = "okay"; }; +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status = "okay"; +}; + &mcu_pmx0 { wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < From e85524649959c2fa2477b66a450471df6e1fb725 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:10 +0530 Subject: [PATCH 716/931] arm64: dts: ti: k3-am642-sr-som: Add missing cfg for TI IPC Firmware Currently, only R5F remote processors are enabled for k3-am642-sr SoMs, whereas the M4F in MCU domain is disabled. Enable the M4F remote processor at board level by reserving memory carveouts and assigning mailboxes. While at it, reserve the MAIN domain timers that are used by R5F remote processors for ticks to avoid rproc crashes. This config aligns with other AM64 boards and can be refactored out later. Signed-off-by: Beleswar Padhi Link: https://patch.msgid.link/20250908142826.1828676-19-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 54 +++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi index 35294a5c46d5..38feda717d7a 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -162,6 +162,24 @@ main_r5fss1_core1_memory_region: memory@a3100000 { reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; + + mcu_m4fss_dma_memory_region: memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; }; vdd_mmc0: regulator-vdd-mmc0 { @@ -291,6 +309,35 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { }; }; +&mailbox0_cluster6 { + status = "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; +}; + +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status = "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status = "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status = "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status = "reserved"; +}; + &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_default_pins>; @@ -524,6 +571,13 @@ &main_r5fss1_core1 { status = "okay"; }; +&mcu_m4fss { + mboxes = <&mailbox0_cluster6 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; + /* SoC default UART console */ &main_uart0 { pinctrl-names = "default"; From 67b98792407f41b369ecd799a4928db24dbb2058 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:11 +0530 Subject: [PATCH 717/931] arm64: dts: ti: k3-am64-phycore-som: Add missing cfg for TI IPC Firmware The k3-am64-phycore SoM enables all R5F and M4F remote processors. Reserve the MAIN domain timers that are used by R5F remote processors for ticks to avoid rproc crashes. This config aligns with other AM64 boards and can be refactored out later. Signed-off-by: Beleswar Padhi Tested-by: Wadim Egorov Link: https://patch.msgid.link/20250908142826.1828676-20-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am64-phycore-som.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index ba425b125d63..5e0c82960a6c 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -275,6 +275,30 @@ mbox_m4_0: mbox-m4-0 { }; }; +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status = "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status = "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status = "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status = "reserved"; +}; + +&main_r5fss0 { + status = "okay"; +}; + &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; From b13fb32f6bde4c0c533fab6e4bc240b75296e810 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:12 +0530 Subject: [PATCH 718/931] arm64: dts: ti: k3-am642-tqma64xxl: Add missing cfg for TI IPC Firmware Currently, only R5F remote processors are enabled for k3-am642-tqma64xxl whereas the M4F in MCU domain is disabled. Enable the M4F remote processor at board level by reserving memory carveouts and assigning mailboxes. While at it, reserve the MAIN domain timers that are used by R5F remote processors for ticks to avoid rproc crashes. This config aligns with other AM64 boards and can be refactored out later. Signed-off-by: Beleswar Padhi Link: https://patch.msgid.link/20250908142826.1828676-21-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi index 4068d2c2b10c..f6d1e980d32f 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -79,6 +79,18 @@ main_r5fss1_core1_memory_region: memory@a3100000 { no-map; }; + mcu_m4fss_dma_memory_region: memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + rtos_ipc_memory_region: memory@a5000000 { reg = <0x00 0xa5000000 0x00 0x00800000>; alignment = <0x1000>; @@ -167,6 +179,26 @@ mbox_m4_0: mbox-m4-0 { }; }; +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status = "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status = "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status = "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status = "reserved"; +}; + &main_r5fss0 { status = "okay"; }; @@ -203,6 +235,13 @@ &main_r5fss1_core1 { status = "okay"; }; +&mcu_m4fss { + mboxes = <&mailbox0_cluster6 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; + &ospi0 { status = "okay"; pinctrl-names = "default"; From 79a1778c7819c8491cdbdc1f7e46d478cb84d5cf Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:13 +0530 Subject: [PATCH 719/931] Revert "arm64: dts: ti: k3-j721e-sk: Fix reversed C6x carveout locations" This reverts commit 9f3814a7c06b7c7296cf8c1622078ad71820454b. The C6x carveouts are reversed intentionally. This is due to the requirement to keep the DMA memory region as non-cached, however the minimum granular cache region for C6x is 16MB. So, C66x_0 marks the entire C66x_1 16MB memory carveouts as non-cached, and uses the DMA memory region of C66x_1 as its own, and vice-versa. This was also called out in the original commit which introduced these reversed carveouts: "The minimum granularity on the Cache settings on C66x DSP cores is 16MB, so the DMA memory regions are chosen such that they are in separate 16MB regions for each DSP, while reserving a total of 16 MB for each DSP and not changing the overall DSP remoteproc carveouts." Fixes: 9f3814a7c06b ("arm64: dts: ti: k3-j721e-sk: Fix reversed C6x carveout locations") Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis Link: https://patch.msgid.link/20250908142826.1828676-22-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 0f05e65f7bf7..37bc33f2cc26 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -120,7 +120,8 @@ main_r5fss1_core1_memory_region: memory@a5100000 { no-map; }; - c66_0_dma_memory_region: memory@a6000000 { + /* Carveout locations are flipped due to caching */ + c66_1_dma_memory_region: memory@a6000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6000000 0x00 0x100000>; no-map; @@ -132,7 +133,8 @@ c66_0_memory_region: memory@a6100000 { no-map; }; - c66_1_dma_memory_region: memory@a7000000 { + /* Carveout locations are flipped due to caching */ + c66_0_dma_memory_region: memory@a7000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7000000 0x00 0x100000>; no-map; From 932424a925ce79cbed0a93d36c5f1b69a0128de1 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:14 +0530 Subject: [PATCH 720/931] Revert "arm64: dts: ti: k3-j721e-beagleboneai64: Fix reversed C6x carveout locations" This reverts commit 1a314099b7559690fe23cdf3300dfff6e830ecb1. The C6x carveouts are reversed intentionally. This is due to the requirement to keep the DMA memory region as non-cached, however the minimum granular cache region for C6x is 16MB. So, C66x_0 marks the entire C66x_1 16MB memory carveouts as non-cached, and uses the DMA memory region of C66x_1 as its own, and vice-versa. This was also called out in the original commit which introduced these reversed carveouts: "The minimum granularity on the Cache settings on C66x DSP cores is 16MB, so the DMA memory regions are chosen such that they are in separate 16MB regions for each DSP, while reserving a total of 16 MB for each DSP and not changing the overall DSP remoteproc carveouts." Fixes: 1a314099b755 ("arm64: dts: ti: k3-j721e-beagleboneai64: Fix reversed C6x carveout locations") Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis Link: https://patch.msgid.link/20250908142826.1828676-23-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 66c4614f9e42..92f5e4a14a49 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -123,7 +123,8 @@ main_r5fss1_core1_memory_region: memory@a5100000 { no-map; }; - c66_0_dma_memory_region: memory@a6000000 { + /* Carveout locations are flipped due to caching */ + c66_1_dma_memory_region: memory@a6000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6000000 0x00 0x100000>; no-map; @@ -135,7 +136,8 @@ c66_0_memory_region: memory@a6100000 { no-map; }; - c66_1_dma_memory_region: memory@a7000000 { + /* Carveout locations are flipped due to caching */ + c66_0_dma_memory_region: memory@a7000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa7000000 0x00 0x100000>; no-map; From 897117c6bb4b151bd9326773cd6a5acdad4c47b4 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:15 +0530 Subject: [PATCH 721/931] arm64: dts: ti: k3-j721e-beagleboneai64: Switch MAIN R5F clusters to Split-mode Switch the MAIN domain R5F clusters into split mode to maximize the number of R5F processors. The TI IPC firmware for the split processors is already available public. This config aligns with other J721E boards and can be refactored out later. Signed-off-by: Beleswar Padhi Link: https://patch.msgid.link/20250908142826.1828676-24-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 92f5e4a14a49..3a7813c8770f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -985,6 +985,7 @@ &mcu_r5fss0_core1 { }; &main_r5fss0 { + ti,cluster-mode = <0>; status = "okay"; }; @@ -1003,6 +1004,7 @@ &main_r5fss0_core1 { }; &main_r5fss1 { + ti,cluster-mode = <0>; status = "okay"; }; From c5b645dbecd6d0b2689fa44eeefe2a2648172dc7 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:16 +0530 Subject: [PATCH 722/931] arm64: dts: ti: k3-j7200-ti-ipc-firmware: Refactor IPC cfg into new dtsi The TI K3 J7200 SoCs have multiple programmable remote processors like R5Fs. The TI SDKs for J7200 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Link: https://patch.msgid.link/20250908142826.1828676-25-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 124 +---------------- .../boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi | 130 ++++++++++++++++++ 2 files changed, 132 insertions(+), 122 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index c689e417cf45..5a8c2e707fde 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -40,48 +40,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a4000000 { - reg = <0x00 0xa4000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; }; mux0: mux-controller-0 { @@ -224,86 +182,6 @@ partition@800000 { }; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - status = "okay"; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status = "okay"; -}; - &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; @@ -546,3 +424,5 @@ &main_mcan0 { pinctrl-names = "default"; phys = <&transceiver0>; }; + +#include "k3-j7200-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..9477f1efbbc6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j7200-ti-ipc-firmware.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J7200 SoCs + * + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a4000000 { + reg = <0x00 0xa4000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; + status = "okay"; +}; + +&main_r5fss0 { + ti,cluster-mode = <0>; + status = "okay"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; + status = "okay"; +}; From 20ca55168b139c78d4e604a59dbc89403781ee0a Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:17 +0530 Subject: [PATCH 723/931] arm64: dts: ti: k3-j721e-ti-ipc-firmware: Refactor IPC cfg into new dtsi The TI K3 J721E SoCs have multiple programmable remote processors like R5F, C6x, C7x etc. The TI SDKs for J721E SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Link: https://patch.msgid.link/20250908142826.1828676-26-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 280 +---------------- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 280 +---------------- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 278 +---------------- .../boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi | 288 ++++++++++++++++++ 4 files changed, 291 insertions(+), 835 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 3a7813c8770f..352fb60e6ce8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -62,110 +62,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - /* Carveout locations are flipped due to caching */ - c66_1_dma_memory_region: memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - /* Carveout locations are flipped due to caching */ - c66_0_dma_memory_region: memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@aa000000 { - reg = <0x00 0xaa000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; }; gpio_keys: gpio-keys { @@ -867,178 +763,4 @@ &ufs_wrapper { status = "disabled"; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer12 { - status = "reserved"; -}; - -&main_timer13 { - status = "reserved"; -}; - -&main_timer14 { - status = "reserved"; -}; - -&main_timer15 { - status = "reserved"; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -&main_r5fss0_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -&main_r5fss1_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; - memory-region = <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; - memory-region = <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; +#include "k3-j721e-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 37bc33f2cc26..5e5784ef6f85 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -59,110 +59,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - /* Carveout locations are flipped due to caching */ - c66_1_dma_memory_region: memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - /* Carveout locations are flipped due to caching */ - c66_0_dma_memory_region: memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@aa000000 { - reg = <0x00 0xaa000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; }; vusb_main: fixedregulator-vusb-main5v0 { @@ -1281,178 +1177,4 @@ &ufs_wrapper { status = "disabled"; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -&main_r5fss1 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer12 { - status = "reserved"; -}; - -&main_timer13 { - status = "reserved"; -}; - -&main_timer14 { - status = "reserved"; -}; - -&main_timer15 { - status = "reserved"; -}; - -&main_r5fss0_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; - memory-region = <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; - memory-region = <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; +#include "k3-j721e-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 06388f28d122..c8073ee634b7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -40,108 +40,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c66_1_dma_memory_region: memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c66_0_memory_region: memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c66_0_dma_memory_region: memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c66_1_memory_region: memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@aa000000 { - reg = <0x00 0xaa000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; }; }; @@ -484,178 +382,4 @@ partition@800000 { }; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_c66_0: mbox-c66-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c66_1: mbox-c66-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - status = "okay"; - ti,cluster-mode = <0>; -}; - -&main_r5fss1 { - status = "okay"; - ti,cluster-mode = <0>; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer12 { - status = "reserved"; -}; - -&main_timer13 { - status = "reserved"; -}; - -&main_timer14 { - status = "reserved"; -}; - -&main_timer15 { - status = "reserved"; -}; - -&main_r5fss0_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&c66_0 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; - memory-region = <&c66_0_dma_memory_region>, - <&c66_0_memory_region>; -}; - -&c66_1 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; - memory-region = <&c66_1_dma_memory_region>, - <&c66_1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; +#include "k3-j721e-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..40c6cc99c405 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-ti-ipc-firmware.dtsi @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J721E SoCs + * + * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + /* Carveout locations are flipped due to caching */ + c66_1_dma_memory_region: memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c66_0_memory_region: memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + /* Carveout locations are flipped due to caching */ + c66_0_dma_memory_region: memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c66_1_memory_region: memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@aa000000 { + reg = <0x00 0xaa000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + interrupts = <424>; + + mbox_c66_0: mbox-c66-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c66_1: mbox-c66-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&main_timer12 { + status = "reserved"; +}; + +&main_timer13 { + status = "reserved"; +}; + +&main_timer14 { + status = "reserved"; +}; + +&main_timer15 { + status = "reserved"; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0 { + status = "okay"; + ti,cluster-mode = <0>; +}; + +&main_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1 { + status = "okay"; + ti,cluster-mode = <0>; +}; + +&main_r5fss1_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&c66_0 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; + memory-region = <&c66_0_dma_memory_region>, + <&c66_0_memory_region>; +}; + +&c66_1 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; + memory-region = <&c66_1_dma_memory_region>, + <&c66_1_memory_region>; +}; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; From e2581d3e0787a42f6ede8a15a66a93ae4a3ecd6f Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:18 +0530 Subject: [PATCH 724/931] arm64: dts: ti: k3-j721s2-ti-ipc-firmware: Refactor IPC cfg into new dtsi The TI K3 J721S2 SoCs have multiple programmable remote processors like R5F, C7x etc. The TI SDKs for J721S2 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Link: https://patch.msgid.link/20250908142826.1828676-27-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am68-phycore-som.dtsi | 247 +---------------- arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 241 +---------------- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 243 +---------------- .../dts/ti/k3-j721s2-ti-ipc-firmware.dtsi | 253 ++++++++++++++++++ 4 files changed, 258 insertions(+), 726 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi index b9c60e078d21..adef02bd8040 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi @@ -60,96 +60,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a8000000 { - reg = <0x00 0xa8000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; }; vdd_sd_dv: regulator-sd { @@ -243,80 +153,6 @@ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT_PULLUP, 0) /* (H27) WKUP_I2C0_SDA */ }; }; -&c71_0 { - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; - status = "okay"; -}; - -&c71_1 { - mboxes = <&mailbox0_cluster4 &mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; - status = "okay"; -}; - -&mailbox0_cluster0 { - interrupts = <436>; - status = "okay"; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - interrupts = <432>; - status = "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - interrupts = <428>; - status = "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - interrupts = <420>; - status = "okay"; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - &main_cpsw { pinctrl-names = "default"; pinctrl-0 = <&rgmii1_pins_default>; @@ -367,34 +203,6 @@ &main_gpio0 { status = "okay"; }; -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status = "okay"; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status = "okay"; -}; - /* eMMC */ &main_sdhci0 { non-removable; @@ -409,59 +217,6 @@ &main_sdhci1 { bootph-all; }; -&main_r5fss0 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -&main_r5fss1 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer3 { - status = "reserved"; -}; - -&main_timer4 { - status = "reserved"; -}; - -&main_timer5 { - status = "reserved"; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - status = "okay"; -}; - &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; @@ -611,3 +366,5 @@ som_eeprom_opt: eeprom@51 { pagesize = <32>; }; }; + +#include "k3-j721s2-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi index c423b1443e0c..6a6dc816b658 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -38,96 +38,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a8000000 { - reg = <0x00 0xa8000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; }; }; @@ -235,153 +145,4 @@ partition@3fc0000 { }; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - status = "okay"; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -&main_r5fss1 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer3 { - status = "reserved"; -}; - -&main_timer4 { - status = "reserved"; -}; - -&main_timer5 { - status = "reserved"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status = "okay"; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status = "okay"; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; +#include "k3-j721s2-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index ff5264d4c2da..12a38dd1514b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -42,96 +42,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a8000000 { - reg = <0x00 0xa8000000 0x00 0x01c00000>; - alignment = <0x1000>; - no-map; - }; }; mux0: mux-controller-0 { @@ -516,157 +426,6 @@ partition@3fc0000 { }; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - status = "okay"; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -&main_r5fss1 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer3 { - status = "reserved"; -}; - -&main_timer4 { - status = "reserved"; -}; - -&main_timer5 { - status = "reserved"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status = "okay"; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status = "okay"; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; - &main_i2c4 { bridge_dsi_edp: bridge-dsi-edp@2c { compatible = "ti,sn65dsi86"; @@ -693,3 +452,5 @@ port@1 { }; }; }; + +#include "k3-j721s2-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..ebab0cc580bb --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-ti-ipc-firmware.dtsi @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J721S2 SoCs + * + * Copyright (C) 2021-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a8000000 { + reg = <0x00 0xa8000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&main_timer3 { + status = "reserved"; +}; + +&main_timer4 { + status = "reserved"; +}; + +&main_timer5 { + status = "reserved"; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; + status = "okay"; +}; + +&main_r5fss0 { + ti,cluster-mode = <0>; + status = "okay"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; + status = "okay"; +}; + +&main_r5fss1 { + ti,cluster-mode = <0>; + status = "okay"; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; + status = "okay"; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; + status = "okay"; +}; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; From 3dabfaa168d8b3835e210f90da3bf0f10b050fdb Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:19 +0530 Subject: [PATCH 725/931] arm64: dts: ti: k3-j784s4-j742s2-ti-ipc-firmware-common: Refactor IPC cfg into new dtsi The TI K3 J784S4/J742S2 SoCs have multiple programmable remote processors like R5F, C7x etc. The TI SDKs for J784S4/J742S2 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Link: https://patch.msgid.link/20250908142826.1828676-28-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 336 +---------------- .../dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 344 +---------------- ...-j784s4-j742s2-ti-ipc-firmware-common.dtsi | 350 ++++++++++++++++++ 3 files changed, 354 insertions(+), 676 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 60817c1f3104..3be74d828d84 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -61,126 +61,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { no-map; }; - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core0_dma_memory_region: memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core0_memory_region: memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core1_dma_memory_region: memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core1_memory_region: memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: memory@a9000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa9000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: memory@a9100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa9100000 0x00 0xf00000>; - no-map; - }; - - c71_2_dma_memory_region: memory@aa000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xaa000000 0x00 0x100000>; - no-map; - }; - - c71_2_memory_region: memory@aa100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xaa100000 0x00 0xf00000>; - no-map; - }; - c71_3_dma_memory_region: memory@ab000000 { compatible = "shared-dma-pool"; reg = <0x00 0xab000000 0x00 0x100000>; @@ -640,84 +520,7 @@ &phy_gmii_sel { bootph-all; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - &mailbox0_cluster5 { - status = "okay"; - interrupts = <416>; - mbox_c71_2: mbox-c71-2 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - mbox_c71_3: mbox-c71-3 { ti,mbox-rx = <2 0 0>; ti,mbox-tx = <3 0 0>; @@ -992,143 +795,6 @@ &mcu_cpsw_port1 { bootph-all; }; -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - status = "okay"; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -&main_r5fss1 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer3 { - status = "reserved"; -}; - -&main_timer4 { - status = "reserved"; -}; - -&main_timer5 { - status = "reserved"; -}; - -&main_timer6 { - status = "reserved"; -}; - -&main_timer7 { - status = "reserved"; -}; - -&main_timer8 { - status = "reserved"; -}; - -&main_timer9 { - status = "reserved"; -}; - -&main_r5fss2 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status = "okay"; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status = "okay"; -}; - -&main_r5fss2_core0 { - mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; - memory-region = <&main_r5fss2_core0_dma_memory_region>, - <&main_r5fss2_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss2_core1 { - mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; - memory-region = <&main_r5fss2_core1_dma_memory_region>, - <&main_r5fss2_core1_memory_region>; - status = "okay"; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; - -&c71_2 { - status = "okay"; - mboxes = <&mailbox0_cluster5 &mbox_c71_2>; - memory-region = <&c71_2_dma_memory_region>, - <&c71_2_memory_region>; -}; - &c71_3 { status = "okay"; mboxes = <&mailbox0_cluster5 &mbox_c71_3>; @@ -1418,3 +1084,5 @@ &usb0 { phys = <&serdes0_usb_link>; phy-names = "cdns3,usb3-phy"; }; + +#include "k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index fdde1bd0e831..419c1a70e028 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -46,126 +46,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core1_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a5000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a5100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa5100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core0_dma_memory_region: memory@a6000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core0_memory_region: memory@a6100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa6100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss2_core1_dma_memory_region: memory@a7000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7000000 0x00 0x100000>; - no-map; - }; - - main_r5fss2_core1_memory_region: memory@a7100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa7100000 0x00 0xf00000>; - no-map; - }; - - c71_0_dma_memory_region: memory@a8000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8000000 0x00 0x100000>; - no-map; - }; - - c71_0_memory_region: memory@a8100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa8100000 0x00 0xf00000>; - no-map; - }; - - c71_1_dma_memory_region: memory@a9000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa9000000 0x00 0x100000>; - no-map; - }; - - c71_1_memory_region: memory@a9100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa9100000 0x00 0xf00000>; - no-map; - }; - - c71_2_dma_memory_region: memory@aa000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xaa000000 0x00 0x100000>; - no-map; - }; - - c71_2_memory_region: memory@aa100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xaa100000 0x00 0xf00000>; - no-map; - }; }; evm_12v0: regulator-evm12v0 { @@ -1069,228 +949,6 @@ &main_cpsw1_port1 { status = "okay"; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - interrupts = <428>; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - interrupts = <424>; - - mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - interrupts = <420>; - - mbox_c71_0: mbox-c71-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c71_1: mbox-c71-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mailbox0_cluster5 { - status = "okay"; - interrupts = <416>; - - mbox_c71_2: mbox-c71-2 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; -}; - -&mcu_r5fss0_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; -}; - -&main_r5fss0 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -&main_r5fss1 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -&main_r5fss2 { - ti,cluster-mode = <0>; - status = "okay"; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&main_timer3 { - status = "reserved"; -}; - -&main_timer4 { - status = "reserved"; -}; - -&main_timer5 { - status = "reserved"; -}; - -&main_timer6 { - status = "reserved"; -}; - -&main_timer7 { - status = "reserved"; -}; - -&main_timer8 { - status = "reserved"; -}; - -&main_timer9 { - status = "reserved"; -}; - -&main_r5fss0_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; -}; - -&main_r5fss0_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; -}; - -&main_r5fss1_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; -}; - -&main_r5fss1_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; -}; - -&main_r5fss2_core0 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; - memory-region = <&main_r5fss2_core0_dma_memory_region>, - <&main_r5fss2_core0_memory_region>; -}; - -&main_r5fss2_core1 { - status = "okay"; - mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; - memory-region = <&main_r5fss2_core1_dma_memory_region>, - <&main_r5fss2_core1_memory_region>; -}; - -&c71_0 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; - memory-region = <&c71_0_dma_memory_region>, - <&c71_0_memory_region>; -}; - -&c71_1 { - status = "okay"; - mboxes = <&mailbox0_cluster4 &mbox_c71_1>; - memory-region = <&c71_1_dma_memory_region>, - <&c71_1_memory_region>; -}; - -&c71_2 { - status = "okay"; - mboxes = <&mailbox0_cluster5 &mbox_c71_2>; - memory-region = <&c71_2_dma_memory_region>, - <&c71_2_memory_region>; -}; - &tscadc0 { pinctrl-0 = <&mcu_adc0_pins_default>; pinctrl-names = "default"; @@ -1619,3 +1277,5 @@ &mcasp0 { 0 0 0 0 >; }; + +#include "k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi new file mode 100644 index 000000000000..455397227d4a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J784S4/J742S2 SoCs + * + * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core0_dma_memory_region: memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core0_memory_region: memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core1_dma_memory_region: memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core1_memory_region: memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: memory@a9000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: memory@a9100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9100000 0x00 0xf00000>; + no-map; + }; + + c71_2_dma_memory_region: memory@aa000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa000000 0x00 0x100000>; + no-map; + }; + + c71_2_memory_region: memory@aa100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa100000 0x00 0xf00000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + interrupts = <424>; + + mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster5 { + status = "okay"; + interrupts = <416>; + + mbox_c71_2: mbox-c71-2 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&main_timer3 { + status = "reserved"; +}; + +&main_timer4 { + status = "reserved"; +}; + +&main_timer5 { + status = "reserved"; +}; + +&main_timer6 { + status = "reserved"; +}; + +&main_timer7 { + status = "reserved"; +}; + +&main_timer8 { + status = "reserved"; +}; + +&main_timer9 { + status = "reserved"; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0 { + ti,cluster-mode = <0>; + status = "okay"; +}; + +&main_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1 { + ti,cluster-mode = <0>; + status = "okay"; +}; + +&main_r5fss1_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&main_r5fss2 { + ti,cluster-mode = <0>; + status = "okay"; +}; + +&main_r5fss2_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; + memory-region = <&main_r5fss2_core0_dma_memory_region>, + <&main_r5fss2_core0_memory_region>; +}; + +&main_r5fss2_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; + memory-region = <&main_r5fss2_core1_dma_memory_region>, + <&main_r5fss2_core1_memory_region>; +}; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; + +&c71_2 { + status = "okay"; + mboxes = <&mailbox0_cluster5 &mbox_c71_2>; + memory-region = <&c71_2_dma_memory_region>, + <&c71_2_memory_region>; +}; From 2742d963e1dd7f4a3d0505044323b091daffcddc Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:20 +0530 Subject: [PATCH 726/931] arm64: dts: ti: k3-j784s4-ti-ipc-firmware: Refactor IPC cfg into new dtsi The TI K3 J784S4 SoCs have multiple programmable remote processors like R5F, C7x etc. The TI SDKs for J784S4 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. This patch only refactors the C71_3 remote processor related nodes into the new dtsi. All other nodes have been refactored in the previous commit as part of k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi. Signed-off-by: Beleswar Padhi Link: https://patch.msgid.link/20250908142826.1828676-29-b-padhi@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 27 +------------- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 26 +------------- .../dts/ti/k3-j784s4-ti-ipc-firmware.dtsi | 35 +++++++++++++++++++ 3 files changed, 37 insertions(+), 51 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 3be74d828d84..5896e57b5b9e 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -60,18 +60,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - c71_3_dma_memory_region: memory@ab000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xab000000 0x00 0x100000>; - no-map; - }; - - c71_3_memory_region: memory@ab100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xab100000 0x00 0xf00000>; - no-map; - }; }; vusb_main: regulator-vusb-main5v0 { @@ -520,13 +508,6 @@ &phy_gmii_sel { bootph-all; }; -&mailbox0_cluster5 { - mbox_c71_3: mbox-c71-3 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - &wkup_uart0 { /* Firmware usage */ status = "reserved"; @@ -795,13 +776,6 @@ &mcu_cpsw_port1 { bootph-all; }; -&c71_3 { - status = "okay"; - mboxes = <&mailbox0_cluster5 &mbox_c71_3>; - memory-region = <&c71_3_dma_memory_region>, - <&c71_3_memory_region>; -}; - &wkup_gpio_intr { status = "okay"; }; @@ -1086,3 +1060,4 @@ &usb0 { }; #include "k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi" +#include "k3-j784s4-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 2ed1ec6d53c8..6c7458c76f53 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -27,31 +27,7 @@ memory@80000000 { reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; - - c71_3_dma_memory_region: memory@ab000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xab000000 0x00 0x100000>; - no-map; - }; - - c71_3_memory_region: memory@ab100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xab100000 0x00 0xf00000>; - no-map; - }; }; }; -&mailbox0_cluster5 { - mbox_c71_3: mbox-c71-3 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&c71_3 { - mboxes = <&mailbox0_cluster5 &mbox_c71_3>; - memory-region = <&c71_3_dma_memory_region>, - <&c71_3_memory_region>; - status = "okay"; -}; +#include "k3-j784s4-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..81b508b9b05e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J784S4 SoCs + * + * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + c71_3_dma_memory_region: memory@ab000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab000000 0x00 0x100000>; + no-map; + }; + + c71_3_memory_region: memory@ab100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab100000 0x00 0xf00000>; + no-map; + }; +}; + +&mailbox0_cluster5 { + + mbox_c71_3: mbox-c71-3 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&c71_3 { + mboxes = <&mailbox0_cluster5 &mbox_c71_3>; + memory-region = <&c71_3_dma_memory_region>, + <&c71_3_memory_region>; + status = "okay"; +}; From 3cc04e49cd5d9c5af24eb4357775f35156b19fec Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:21 +0530 Subject: [PATCH 727/931] arm64: dts: ti: k3-j722s-ti-ipc-firmware: Refactor IPC cfg into new dtsi The TI K3 J722S SoCs have multiple programmable remote processors like R5F, C7x etc. The TI SDKs for J722S SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Link: https://patch.msgid.link/20250908142826.1828676-30-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../arm64/boot/dts/ti/k3-am67a-beagley-ai.dts | 155 +---------------- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 157 +---------------- .../boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi | 163 ++++++++++++++++++ 3 files changed, 166 insertions(+), 309 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts index 85436ea5b4e7..b697035df04e 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts @@ -61,60 +61,6 @@ wkup_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core0_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - c7x_0_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - c7x_0_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - c7x_1_dma_memory_region: memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - c7x_1_memory_region: memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a5000000 { - reg = <0x00 0xa5000000 0x00 0x1c00000>; - alignment = <0x1000>; - no-map; - }; }; vsys_5v0: regulator-1 { @@ -453,103 +399,4 @@ &sdhci1 { status = "okay"; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_wkup_r5_0: mbox-wkup-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - - mbox_c7x_0: mbox-c7x-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - - mbox_main_r5_0: mbox-main-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c7x_1: mbox-c7x-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss0 { - status = "okay"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&c7x_0 { - mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; - memory-region = <&c7x_0_dma_memory_region>, - <&c7x_0_memory_region>; - status = "okay"; -}; - -&c7x_1 { - mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; - memory-region = <&c7x_1_dma_memory_region>, - <&c7x_1_memory_region>; - status = "okay"; -}; +#include "k3-j722s-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index d323284a30ab..a9b5d9a06241 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -63,60 +63,6 @@ wkup_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - mcu_r5fss0_core0_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss0_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - c7x_0_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - c7x_0_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - c7x_1_dma_memory_region: memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - c7x_1_memory_region: memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a5000000 { - reg = <0x00 0xa5000000 0x00 0x1c00000>; - alignment = <0x1000>; - no-map; - }; }; vmain_pd: regulator-0 { @@ -788,107 +734,6 @@ &sdhci1 { bootph-all; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_wkup_r5_0: mbox-wkup-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - - mbox_c7x_0: mbox-c7x-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster3 { - status = "okay"; - - mbox_main_r5_0: mbox-main-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_c7x_1: mbox-c7x-1 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -/* Timers are used by Remoteproc firmware */ -&main_timer0 { - status = "reserved"; -}; - -&main_timer1 { - status = "reserved"; -}; - -&main_timer2 { - status = "reserved"; -}; - -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss0 { - status = "okay"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&c7x_0 { - mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; - memory-region = <&c7x_0_dma_memory_region>, - <&c7x_0_memory_region>; - status = "okay"; -}; - -&c7x_1 { - mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; - memory-region = <&c7x_1_dma_memory_region>, - <&c7x_1_memory_region>; - status = "okay"; -}; - &serdes_ln_ctrl { idle-states = , ; @@ -999,3 +844,5 @@ &mcu_i2c0 { clock-frequency = <400000>; status = "okay"; }; + +#include "k3-j722s-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..cb7cd385a165 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on J722S SoCs + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_r5fss0_core0_dma_memory_region: memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + c7x_0_dma_memory_region: memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + c7x_1_dma_memory_region: memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + c7x_1_memory_region: memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a5000000 { + reg = <0x00 0xa5000000 0x00 0x1c00000>; + alignment = <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_wkup_r5_0: mbox-wkup-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + + mbox_main_r5_0: mbox-main-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c7x_1: mbox-c7x-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_wkup_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&main_r5fss0 { + status = "okay"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster3 &mbox_main_r5_0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&c7x_0 { + mboxes = <&mailbox0_cluster2 &mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status = "okay"; +}; + +&c7x_1 { + mboxes = <&mailbox0_cluster3 &mbox_c7x_1>; + memory-region = <&c7x_1_dma_memory_region>, + <&c7x_1_memory_region>; + status = "okay"; +}; From 6bd0449be319a29096f3ee7cd415f8b6b28104c7 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:22 +0530 Subject: [PATCH 728/931] arm64: dts: ti: k3-am62p-ti-ipc-firmware: Refactor IPC cfg into new dtsi The TI K3 AM62P SoCs have multiple programmable remote processors like R5Fs. The TI SDKs for AM62P SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Tested-by: Judith Mendez Reviewed-by: Dhruva Gole Link: https://patch.msgid.link/20250908142826.1828676-31-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi | 60 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 54 +---------------- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 54 +---------------- 3 files changed, 64 insertions(+), 104 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..d29a5dbe13ef --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-ti-ipc-firmware.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM62P SoCs + * + * Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: memory@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi index 671d367b40d1..99810047614e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -162,18 +162,6 @@ secure_ddr: optee@9e800000 { no-map; }; - mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@9b900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x100000>; @@ -848,46 +836,6 @@ &epwm2 { status = "disabled"; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status = "okay"; -}; - &main0_alert { temperature = <95000>; }; @@ -1466,3 +1414,5 @@ &wkup_uart0 { uart-has-rtscts; status = "disabled"; }; + +#include "k3-am62p-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index aa363aaf6d59..56f0eb11b902 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -49,18 +49,6 @@ reserved_memory: reserved-memory { #size-cells = <2>; ranges; - mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@9b900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x100000>; @@ -699,46 +687,6 @@ partition@3fc0000 { }; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status = "okay"; -}; - &main_uart0 { pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; @@ -810,3 +758,5 @@ &epwm1 { pinctrl-0 = <&main_epwm1_pins_default>; status = "okay"; }; + +#include "k3-am62p-ti-ipc-firmware.dtsi" From 1d6161617c10435e970d3bb3ef5de124b94fe719 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:23 +0530 Subject: [PATCH 729/931] arm64: dts: ti: k3-am62-ti-ipc-firmware: Refactor IPC cfg into new dtsi The TI K3 AM62 SoCs have multiple programmable remote processors like R5F, M4F etc. The TI SDKs for AM62 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Tested-by: Wadim Egorov # phycore-am62x Reviewed-by: Wadim Egorov Reviewed-by: Dhruva Gole Link: https://patch.msgid.link/20250908142826.1828676-32-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am62-phycore-som.dtsi | 44 +--------------- .../boot/dts/ti/k3-am62-pocketbeagle2.dts | 46 +--------------- .../boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi | 52 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 46 +--------------- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 46 +--------------- 5 files changed, 59 insertions(+), 175 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index 75b7e64f6659..eeca643fedbe 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -52,18 +52,6 @@ rtos_ipc_memory_region: memory@9c800000 { no-map; }; - mcu_m4fss_dma_memory_region: memory@9cb00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9cb00000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@9cc00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9cc00000 0x00 0xe00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9da00000 0x00 0x100000>; @@ -245,20 +233,6 @@ cpsw3g_phy1: ethernet-phy@1 { }; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - &main_pktdma { bootph-all; }; @@ -364,13 +338,6 @@ i2c_som_rtc: rtc@52 { }; }; -&mcu_m4fss { - mboxes = <&mailbox0_cluster0 &mbox_m4_0>; - memory-region = <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status = "okay"; -}; - &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; @@ -399,13 +366,4 @@ &sdhci0 { status = "okay"; }; -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status = "okay"; -}; +#include "k3-am62-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts index 621fb6c52db1..7a4cffc27bda 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts @@ -54,18 +54,6 @@ linux,cma { linux,cma-default; }; - mcu_m4fss_dma_memory_region: memory@9cb00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9cb00000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@9cc00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9cc00000 0x00 0xe00000>; - no-map; - }; - secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; alignment = <0x1000>; @@ -298,20 +286,6 @@ &epwm2 { pinctrl-0 = <&epwm2_pins_default>; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - &main_uart0 { pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; @@ -362,24 +336,6 @@ &main_i2c2 { status = "okay"; }; -&mcu_m4fss { - mboxes = <&mailbox0_cluster0 &mbox_m4_0>; - memory-region = <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status = "okay"; -}; - -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status = "okay"; -}; - &mcu_pmx0 { wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < @@ -543,3 +499,5 @@ ldo4_reg: ldo4 { }; }; }; + +#include "k3-am62-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..ea69fab9b52b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM62 SoCs + * + * Copyright (C) 2021-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_m4fss_dma_memory_region: memory@9cb00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: memory@9cc00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mcu_m4fss { + mboxes = <&mailbox0_cluster0 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index 5ecdd833587e..dc4b228a9fd7 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -206,18 +206,6 @@ secure_ddr: optee@9e800000 { no-map; }; - mcu_m4fss_dma_memory_region: memory@9cb00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9cb00000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@9cc00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9cc00000 0x00 0xe00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9da00000 0x00 0x100000>; @@ -1334,38 +1322,6 @@ &main_i2c3 { status = "disabled"; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_m4fss { - mboxes = <&mailbox0_cluster0 &mbox_m4_0>; - memory-region = <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status = "okay"; -}; - -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status = "okay"; -}; - /* Verdin CAN_1 */ &main_mcan0 { pinctrl-names = "default"; @@ -1549,3 +1505,5 @@ &wkup_uart0 { pinctrl-0 = <&pinctrl_wkup_uart0>; status = "disabled"; }; + +#include "k3-am62-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 05cba3cfc79e..241902fc1cf2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -58,18 +58,6 @@ linux,cma { linux,cma-default; }; - mcu_m4fss_dma_memory_region: memory@9cb00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9cb00000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@9cc00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9cc00000 0x00 0xe00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9da00000 0x00 0x100000>; @@ -477,38 +465,6 @@ cpsw3g_phy0: ethernet-phy@0 { }; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <2 0 0>; - ti,mbox-tx = <3 0 0>; - }; -}; - -&mcu_m4fss { - mboxes = <&mailbox0_cluster0 &mbox_m4_0>; - memory-region = <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status = "okay"; -}; - -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status = "okay"; -}; - &usbss0 { bootph-all; status = "okay"; @@ -601,3 +557,5 @@ &epwm1 { pinctrl-0 = <&main_epwm1_pins_default>; status = "okay"; }; + +#include "k3-am62-ti-ipc-firmware.dtsi" From d4ab4a33c8e0a8cd33c8cb70ba3c74dba770c2a4 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:24 +0530 Subject: [PATCH 730/931] arm64: dts: ti: k3-am62a-ti-ipc-firmware: Refactor IPC cfg into new dtsi The TI K3 AM62A SoCs have multiple programmable remote processors like R5F, C7x etc. The TI SDKs for AM62A SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Tested-by: Judith Mendez Reviewed-by: Dhruva Gole Link: https://patch.msgid.link/20250908142826.1828676-33-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am62a-phycore-som.dtsi | 90 +---------------- .../boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi | 98 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 92 +---------------- arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 76 +------------- 4 files changed, 102 insertions(+), 254 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index 0406a43ff704..b3d012a5a26a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -59,30 +59,6 @@ linux,cma { linux,cma-default; }; - c7x_0_dma_memory_region: memory@99800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x99800000 0x00 0x100000>; - no-map; - }; - - c7x_0_memory_region: memory@99900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x99900000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@9b900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x100000>; @@ -209,13 +185,6 @@ opp-1400000000 { }; }; -&c7x_0 { - mboxes = <&mailbox0_cluster1 &mbox_c7x_0>; - memory-region = <&c7x_0_dma_memory_region>, - <&c7x_0_memory_region>; - status = "okay"; -}; - &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>; @@ -246,33 +215,6 @@ &fss { status = "okay"; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - - mbox_c7x_0: mbox-c7x-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; @@ -388,27 +330,6 @@ &main_pktdma { bootph-all; }; -/* main_rti4 is used by C7x DSP */ -&main_rti4 { - status = "reserved"; -}; - -/* main_timer2 is used by C7x DSP */ -&main_timer2 { - status = "reserved"; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status = "okay"; -}; - &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; @@ -437,13 +358,4 @@ &sdhci0 { status = "okay"; }; -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status = "okay"; -}; +#include "k3-am62a-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..950f4f37d477 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62a-ti-ipc-firmware.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM62A SoCs + * + * Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + c7x_0_dma_memory_region: memory@99800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: memory@99900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x99900000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: memory@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&c7x_0 { + mboxes = <&mailbox0_cluster1>, <&mbox_c7x_0>; + memory-region = <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status = "okay"; +}; + +/* main_rti4 is used by C7x DSP */ +&main_rti4 { + status = "reserved"; +}; + +/* main_timer2 is used by C7x DSP */ +&main_timer2 { + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 312bdab28784..9f148b89e74d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -53,30 +53,6 @@ linux,cma { linux,cma-default; }; - c7x_0_dma_memory_region: memory@99800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x99800000 0x00 0x100000>; - no-map; - }; - - c7x_0_memory_region: memory@99900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x99900000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@9b900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x100000>; @@ -713,11 +689,6 @@ &main_uart1 { status = "reserved"; }; -/* main_timer2 is used by C7x DSP */ -&main_timer2 { - status = "reserved"; -}; - &usbss0 { status = "okay"; ti,vbus-divider; @@ -835,67 +806,6 @@ &epwm1 { status = "okay"; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - - mbox_c7x_0: mbox-c7x-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&wkup_r5fss0 { - status = "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&c7x_0 { - mboxes = <&mailbox0_cluster1>, <&mbox_c7x_0>; - memory-region = <&c7x_0_dma_memory_region>, - <&c7x_0_memory_region>; - status = "okay"; -}; - -/* main_rti4 is used by C7x DSP */ -&main_rti4 { - status = "reserved"; -}; - &fss { status = "okay"; }; @@ -937,3 +847,5 @@ AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ >; }; }; + +#include "k3-am62a-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts index 289f52b3481f..c958a1c4a657 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -58,30 +58,6 @@ secure_tfa_ddr: tfa@80000000 { no-map; }; - c7x_0_dma_memory_region: memory@99800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x99800000 0x00 0x100000>; - no-map; - }; - - c7x_0_memory_region: memory@99900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x99900000 0x00 0xf00000>; - no-map; - }; - - mcu_r5fss0_core0_dma_memory_region: memory@9b800000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b800000 0x00 0x100000>; - no-map; - }; - - mcu_r5fss0_core0_memory_region: memory@9b900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9b900000 0x00 0xf00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: memory@9c800000 { compatible = "shared-dma-pool"; reg = <0x00 0x9c800000 0x00 0x100000>; @@ -551,66 +527,16 @@ cpsw3g_phy1: ethernet-phy@3 { }; }; -&mailbox0_cluster0 { - status = "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - - mbox_c7x_0: mbox-c7x-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster2 { - status = "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&wkup_r5fss0 { - status = "okay"; -}; - &wkup_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_r5_0>; - memory-region = <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status = "okay"; bootph-pre-ram; }; -&mcu_r5fss0 { - status = "okay"; -}; - &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>; - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; firmware-name = "am62d-mcu-r5f0_0-fw"; - status = "okay"; }; &c7x_0 { - mboxes = <&mailbox0_cluster1 &mbox_c7x_0>; - memory-region = <&c7x_0_dma_memory_region>, - <&c7x_0_memory_region>; firmware-name = "am62d-c71_0-fw"; - status = "okay"; }; -/* main_rti4 is used by C7x DSP */ -&main_rti4 { - status = "reserved"; -}; +#include "k3-am62a-ti-ipc-firmware.dtsi" From 3ad3ab0bfa577d1f93e7048224c267b32ed4d6a1 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:25 +0530 Subject: [PATCH 731/931] arm64: dts: ti: k3-am64-ti-ipc-firmware: Refactor IPC cfg into new dtsi The TI K3 AM64 SoCs have multiple programmable remote processors like R5F, M4F etc. The TI SDKs for AM64 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Tested-by: Wadim Egorov # phycore-am64x Tested-by: Hari Nagalla Reviewed-by: Wadim Egorov # phycore-am64x Reviewed-by: Dhruva Gole Link: https://patch.msgid.link/20250908142826.1828676-34-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am64-phycore-som.dtsi | 160 +---------------- .../boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi | 162 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 156 +---------------- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 156 +---------------- arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 156 +---------------- .../arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 156 +---------------- 6 files changed, 172 insertions(+), 774 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 5e0c82960a6c..02ef1dd92eaa 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -52,60 +52,6 @@ main_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a5000000 { - reg = <0x00 0xa5000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; }; leds { @@ -238,67 +184,6 @@ &cpsw_port1 { status = "okay"; }; -&mailbox0_cluster2 { - status = "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status = "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status = "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status = "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status = "reserved"; -}; - -&main_r5fss0 { - status = "okay"; -}; - &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; @@ -373,49 +258,6 @@ &main_pktdma { bootph-all; }; -&main_r5fss0 { - status = "okay"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status = "okay"; -}; - -&main_r5fss1 { - status = "okay"; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status = "okay"; -}; - -&mcu_m4fss { - mboxes = <&mailbox0_cluster6 &mbox_m4_0>; - memory-region = <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status = "okay"; -}; - &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; @@ -451,3 +293,5 @@ adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..6b10646ae64a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM64 SoCs + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + main_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + mcu_m4fss_dma_memory_region: memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster6 { + status = "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; +}; + +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status = "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status = "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status = "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status = "reserved"; +}; + +&main_r5fss0 { + status = "okay"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; + status = "okay"; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; + status = "okay"; +}; + +&main_r5fss1 { + status = "okay"; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; + status = "okay"; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; + status = "okay"; +}; + +&mcu_m4fss { + mboxes = <&mailbox0_cluster6 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index ebc9fedc4d72..85dcff104936 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -64,60 +64,6 @@ main_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a5000000 { - reg = <0x00 0xa5000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; }; evm_12v0: regulator-0 { @@ -727,106 +673,6 @@ partition@3fc0000 { }; }; -&mailbox0_cluster2 { - status = "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; -}; - -&main_r5fss0 { - status = "okay"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status = "okay"; -}; - -&main_r5fss1 { - status = "okay"; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status = "okay"; -}; - -&mcu_m4fss { - mboxes = <&mailbox0_cluster6 &mbox_m4_0>; - memory-region = <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status = "okay"; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status = "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status = "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status = "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status = "reserved"; -}; - &serdes_ln_ctrl { idle-states = ; }; @@ -890,3 +736,5 @@ &icssg1_iep0 { pinctrl-names = "default"; pinctrl-0 = <&icssg1_iep0_pins_default>; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index d2b06e508c7f..1fb1b91a1bad 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -62,60 +62,6 @@ main_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a5000000 { - reg = <0x00 0xa5000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; }; vusb_main: regulator-0 { @@ -642,106 +588,6 @@ partition@3fc0000 { }; }; -&mailbox0_cluster2 { - status = "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; -}; - -&main_r5fss0 { - status = "okay"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status = "okay"; -}; - -&main_r5fss1 { - status = "okay"; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status = "okay"; -}; - -&mcu_m4fss { - mboxes = <&mailbox0_cluster6 &mbox_m4_0>; - memory-region = <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status = "okay"; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status = "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status = "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status = "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status = "reserved"; -}; - &ecap0 { status = "okay"; /* PWM is available on Pin 1 of header J3 */ @@ -755,3 +601,5 @@ &eqep0 { pinctrl-names = "default"; pinctrl-0 = <&main_eqep0_pins_default>; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi index 38feda717d7a..fcbcc04521b8 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -126,60 +126,6 @@ main_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a5000000 { - reg = <0x00 0xa5000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; }; vdd_mmc0: regulator-vdd-mmc0 { @@ -281,63 +227,6 @@ ethernet_phy2: ethernet-phy@f { }; }; -&mailbox0_cluster2 { - status = "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status = "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status = "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status = "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status = "reserved"; -}; - &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_default_pins>; @@ -535,49 +424,6 @@ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB0_DRVVBUS */ }; }; -&main_r5fss0 { - status = "okay"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status = "okay"; -}; - -&main_r5fss1 { - status = "okay"; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status = "okay"; -}; - -&mcu_m4fss { - mboxes = <&mailbox0_cluster6 &mbox_m4_0>; - memory-region = <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status = "okay"; -}; - /* SoC default UART console */ &main_uart0 { pinctrl-names = "default"; @@ -656,3 +502,5 @@ &usbss0 { ti,vbus-divider; ti,usb2-only; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi index f6d1e980d32f..ff3b2e0b8dd4 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -42,60 +42,6 @@ main_r5fss0_core0_memory_region: memory@a0100000 { reg = <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: memory@a2000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: memory@a2100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: memory@a3000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: memory@a3100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: memory@a4000000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: memory@a4100000 { - compatible = "shared-dma-pool"; - reg = <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a5000000 { - reg = <0x00 0xa5000000 0x00 0x00800000>; - alignment = <0x1000>; - no-map; - }; }; reg_1v8: regulator-1v8 { @@ -142,106 +88,6 @@ eeprom1: eeprom@54 { }; }; -&mailbox0_cluster2 { - status = "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status = "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx = <2 0 2>; - ti,mbox-tx = <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status = "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx = <0 0 2>; - ti,mbox-tx = <1 0 2>; - }; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status = "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status = "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status = "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status = "reserved"; -}; - -&main_r5fss0 { - status = "okay"; -}; - -&main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region = <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region = <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status = "okay"; -}; - -&main_r5fss1 { - status = "okay"; -}; - -&main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region = <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status = "okay"; -}; - -&main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region = <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status = "okay"; -}; - -&mcu_m4fss { - mboxes = <&mailbox0_cluster6 &mbox_m4_0>; - memory-region = <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status = "okay"; -}; - &ospi0 { status = "okay"; pinctrl-names = "default"; @@ -315,3 +161,5 @@ AM64X_IOPAD(0x0008, PIN_INPUT, 0) >; }; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" From a26bc9175f679da37ee3a52669aeb26db7f57738 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Mon, 8 Sep 2025 19:58:26 +0530 Subject: [PATCH 732/931] arm64: dts: ti: k3-am65-ti-ipc-firmware: Refactor IPC cfg into new dtsi The TI K3 AM65 SoCs have multiple programmable remote processors like R5Fs. The TI SDKs for AM65 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Link: https://patch.msgid.link/20250908142826.1828676-35-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 62 ++---------------- .../boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi | 64 +++++++++++++++++++ .../arm64/boot/dts/ti/k3-am654-base-board.dts | 58 +---------------- 3 files changed, 72 insertions(+), 112 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index df2eed0b4048..42ba3dab2fc1 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -59,24 +59,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { no-map; }; - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0 0xa1000000 0 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0 0xa1100000 0 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a2000000 { - reg = <0x00 0xa2000000 0x00 0x00200000>; - alignment = <0x1000>; - no-map; - }; - /* To reserve the power-on(PON) reason for watchdog reset */ wdt_reset_memory_region: wdt-memory@a2200000 { reg = <0x00 0xa2200000 0x00 0x1000>; @@ -582,44 +564,6 @@ &pcie1_rc { reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-tx = <1 0 0>; - ti,mbox-rx = <0 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-tx = <1 0 0>; - ti,mbox-rx = <0 0 0>; - }; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - status = "okay"; -}; - -&mcu_r5fss0_core1 { - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; - status = "okay"; -}; - &mcu_rti1 { memory-region = <&wdt_reset_memory_region>; }; @@ -692,3 +636,9 @@ &mcu_r5fss0 { /* lock-step mode not supported on iot2050 boards */ ti,cluster-mode = <0>; }; + +#include "k3-am65-ti-ipc-firmware.dtsi" + +&rtos_ipc_memory_region { + reg = <0x00 0xa2000000 0x00 0x00200000>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..61ab0357fc0d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM65 SoCs + * + * Copyright (C) 2016-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0 0xa1000000 0 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0 0xa1100000 0 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: memory@a2000000 { + reg = <0x00 0xa2000000 0x00 0x00100000>; + alignment = <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-tx = <1 0 0>; + ti,mbox-rx = <0 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-tx = <1 0 0>; + ti,mbox-rx = <0 0 0>; + }; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + status = "okay"; +}; + +&mcu_r5fss0_core1 { + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 3ca771a4f9c7..0c42c486d83a 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -61,24 +61,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 { reg = <0 0xa0100000 0 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: memory@a1000000 { - compatible = "shared-dma-pool"; - reg = <0 0xa1000000 0 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: memory@a1100000 { - compatible = "shared-dma-pool"; - reg = <0 0xa1100000 0 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: memory@a2000000 { - reg = <0x00 0xa2000000 0x00 0x00100000>; - alignment = <0x1000>; - no-map; - }; }; gpio-keys { @@ -521,44 +503,6 @@ &serdes1 { status = "disabled"; }; -&mailbox0_cluster0 { - status = "okay"; - interrupts = <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-tx = <1 0 0>; - ti,mbox-rx = <0 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - interrupts = <432>; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-tx = <1 0 0>; - ti,mbox-rx = <0 0 0>; - }; -}; - -&mcu_r5fss0 { - status = "okay"; -}; - -&mcu_r5fss0_core0 { - memory-region = <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - status = "okay"; -}; - -&mcu_r5fss0_core1 { - memory-region = <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; - status = "okay"; -}; - &ospi0 { status = "okay"; pinctrl-names = "default"; @@ -653,3 +597,5 @@ &dss { &wkup_gpio0 { bootph-all; }; + +#include "k3-am65-ti-ipc-firmware.dtsi" From bc2d616d58ab3810ce755e250885cc66dc707209 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:33:30 +0200 Subject: [PATCH 733/931] arm64: dts: marvell: armada-37xx: Add default PCI interrup controller address cells Add missing address-cells 0 to the PCI interrupt node to silence W=1 warning: armada-37xx.dtsi:518.4-521.29: Warning (interrupt_map): /soc/pcie@d0070000:interrupt-map: Missing property '#address-cells' in node /soc/pcie@d0070000/interrupt-controller, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 75b0fdc3efb2..c612317043ea 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -524,6 +524,7 @@ pcie0: pcie@d0070000 { pcie_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; + #address-cells = <0>; }; }; }; From 3668be17e5464c835544b84c7a808b7d5cf99ffc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:33:31 +0200 Subject: [PATCH 734/931] arm64: dts: marvell: armada-cp11x: Add default ICU address cells Add missing address-cells 0 to the ICU interrupt node to silence W=1 warning: armada-cp11x.dtsi:547.3-47: Warning (interrupt_map): /cp0-bus/pcie@f2600000:interrupt-map: Missing property '#address-cells' in node /cp0-bus/bus@f2000000/interrupt-controller@1e0000/interrupt-controller@10, using 0 as fallback Value '0' is correct because: 1. GIC interrupt controller does not have children, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index a057e119492f..d9d409eac259 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -202,6 +202,7 @@ CP11X_LABEL(icu): interrupt-controller@1e0000 { CP11X_LABEL(icu_nsr): interrupt-controller@10 { compatible = "marvell,cp110-icu-nsr"; reg = <0x10 0x20>; + #address-cells = <0>; #interrupt-cells = <2>; interrupt-controller; msi-parent = <&gicp>; From e0b9feca7329c495a76891d7766a781dea73787d Mon Sep 17 00:00:00 2001 From: Anshul Dalal Date: Thu, 14 Aug 2025 19:15:27 +0530 Subject: [PATCH 735/931] arm64: dts: ti: k3-am62*: remove SoC dtsi from common dtsi The k3-am62x-sk-common dtsi represents the common hardware used across am62x EVMs which can be configured with various DDR sizes or none (with DDR integrated in the package) based on the specific am62x SoC used. Therefore this patch moves the memory node and the SoC specific k3-am625 dtsi out of sk-common and into the board dts files. No functional change is intended from this patch. The device-tree inheritance is changed as follows: Before: k3-am62 ^ k3-am625 ^ k3-am62x-sk-common ^ am62x EVMs (k3-am625-sk, k3-am62-lp-sk) After: k3-am62 ^ k3-am625 k3-am62x-sk-common ^ ^ am62x EVMs (k3-am625-sk, k3-am62-lp-sk) Signed-off-by: Anshul Dalal Reviewed-by: Bryan Brattlof Link: https://patch.msgid.link/20250814134531.2743874-2-anshuld@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 8 ++++++++ arch/arm64/boot/dts/ti/k3-am625-sk.dts | 5 +++-- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 8 -------- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts index 4609f366006e..ecfba05fe5c2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -7,12 +7,20 @@ /dts-v1/; +#include "k3-am625.dtsi" #include "k3-am62x-sk-common.dtsi" / { compatible = "ti,am62-lp-sk", "ti,am625"; model = "Texas Instruments AM62x LP SK"; + memory@80000000 { + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + device_type = "memory"; + bootph-pre-ram; + }; + vmain_pd: regulator-0 { /* TPS65988 PD CONTROLLER OUTPUT */ compatible = "regulator-fixed"; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index d240165bda9c..1c6812a8ae9b 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -7,6 +7,7 @@ /dts-v1/; +#include "k3-am625.dtsi" #include "k3-am62x-sk-common.dtsi" / { @@ -23,10 +24,10 @@ opp-1400000000 { }; memory@80000000 { - device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - + device_type = "memory"; + bootph-pre-ram; }; vmain_pd: regulator-0 { diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 241902fc1cf2..af549104af47 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -8,7 +8,6 @@ #include #include #include -#include "k3-am625.dtsi" / { aliases { @@ -29,13 +28,6 @@ chosen { stdout-path = "serial2:115200n8"; }; - memory@80000000 { - bootph-pre-ram; - device_type = "memory"; - /* 2G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; - reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; From 3e915577cf0b7d3f9088c398888e5e01e10356d7 Mon Sep 17 00:00:00 2001 From: Anshul Dalal Date: Thu, 14 Aug 2025 19:15:28 +0530 Subject: [PATCH 736/931] dt-bindings: arm: ti: Add binding for AM625 SiP The AM6254atl SiP belongs to the K3 Multicore SoC architecture platform, providing AM625 SoC with 512MiB of integrated DDR in the package. For further information about the package check: https://www.ti.com/lit/ds/symlink/am625sip.pdf Signed-off-by: Anshul Dalal Reviewed-by: Bryan Brattlof Acked-by: Conor Dooley Link: https://patch.msgid.link/20250814134531.2743874-3-anshuld@ti.com Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index e80c653fa438..f98817e97d4c 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -58,6 +58,13 @@ properties: - ti,am62-lp-sk - const: ti,am625 + - description: K3 AM6254atl SiP + items: + - enum: + - ti,am6254atl-sk + - const: ti,am6254atl + - const: ti,am625 + - description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards items: - enum: From 7c1d13a14e61ab33eec330cb6cabbddb37eecaa9 Mon Sep 17 00:00:00 2001 From: Anshul Dalal Date: Thu, 14 Aug 2025 19:15:29 +0530 Subject: [PATCH 737/931] arm64: dts: ti: Introduce base support for AM6254atl SiP This patch adds the top level dtsi for AM6254atl SiP which integrates the existing AM625 SoC with 512MiB of DDR in a single package. More information about the package can be found here: https://www.ti.com/lit/ds/symlink/am625sip.pdf Signed-off-by: Anshul Dalal Reviewed-by: Bryan Brattlof Link: https://patch.msgid.link/20250814134531.2743874-4-anshuld@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am6254atl.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am6254atl.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am6254atl.dtsi b/arch/arm64/boot/dts/ti/k3-am6254atl.dtsi new file mode 100644 index 000000000000..976ad7dc1e71 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am6254atl.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * DTS for AM625 SiP SoC family in Quad core configuration and 512MiB RAM. + * + * Webpage: https://www.ti.com/product/AM625SIP + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am625.dtsi" + +/ { + model = "Texas Instruments AM6254atl SiP"; + compatible = "ti,am6254atl", "ti,am625"; + + memory@80000000 { + /* 512MiB of integrated RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x20000000>; + device_type = "memory"; + bootph-all; + }; + +}; From 2517e476b819df986fa1fe53927c099032bb72dc Mon Sep 17 00:00:00 2001 From: Anshul Dalal Date: Thu, 14 Aug 2025 19:15:30 +0530 Subject: [PATCH 738/931] arm64: dts: ti: Add support for AM6254atl SiP SK This patch adds the dt for SK-AM62-SIP, which uses the existing SK-AM62 board design with the new AM6254atl SiP. This changes the location of memory node from the board dts to SoC level dtsi (k3-am6254atl in our case). Therefore this patch introduces the new 'k3-am625-sk-common.dtsi' which represents the common hardware used for both 'am625-sk' and 'am6254atl-sk' boards with the inheritance hierarchy modified to: k3-am625-sk.dts: k3-am62 k3-am62x-sk-common | | k3-am625 k3-am625-sk-common | | +-----+------+ | k3-am625-sk k3-am6254atl-sk.dts: k3-am62 | k3-am625 k3-am62x-sk-common | | k3-am6254atl k3-am625-sk-common | | +-------+--------+ | k3-am6254atl-sk Signed-off-by: Anshul Dalal Reviewed-by: Bryan Brattlof Link: https://patch.msgid.link/20250814134531.2743874-5-anshuld@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 1 + .../arm64/boot/dts/ti/k3-am625-sk-common.dtsi | 296 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am625-sk.dts | 296 +----------------- arch/arm64/boot/dts/ti/k3-am6254atl-sk.dts | 15 + 4 files changed, 313 insertions(+), 295 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am6254atl-sk.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index aad9177930e6..72f8755a0f30 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -28,6 +28,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62x-phyboard-lyra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62-pocketbeagle2.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am6254atl-sk.dtb # Boards with AM62Ax SoC dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi new file mode 100644 index 000000000000..fe0b98e1d105 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Common dtsi for AM625 SK and derivatives + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am62x-sk-common.dtsi" + +/ { + opp-table { + /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_5v0: regulator-1 { + /* Output of LM34936 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3v3_sys: regulator-2 { + /* output of LM61460-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vdd_mmc1: regulator-3 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_sys>; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vdd_sd_dv: regulator-4 { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc_5v0>; + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + bootph-all; + }; + + vcc_1v8: regulator-5 { + /* output of TPS6282518DMQ */ + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&main_pmx0 { + main_mmc0_pins_default: main-mmc0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + main_rgmii2_pins_default: main-rgmii2-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ + AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ + AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ + AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ + AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ + AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ + AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ + AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ + AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ + AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ + >; + bootph-all; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ + >; + bootph-all; + }; +}; + +&main_gpio0 { + bootph-all; +}; + +&main_gpio1 { + bootph-all; +}; + +&main_i2c1 { + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + interrupt-parent = <&main_gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "PRU_DETECT", "MMC1_SD_EN", + "VPP_LDO_EN", "EXP_PS_3V3_En", + "EXP_PS_5V0_En", "EXP_HAT_DETECT", + "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", + "UART1_FET_BUF_EN", "WL_LT_EN", + "GPIO_HDMI_RSTn", "CSI_GPIO1", + "CSI_GPIO2", "PRU_3V3_EN", + "HDMI_INTn", "PD_I2C_IRQ", + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", + "MCASP1_FET_SEL", "UART1_FET_SEL", + "TSINT#", "IO_EXP_TEST_LED"; + bootph-all; + }; +}; + +&sdhci0 { + bootph-all; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + disable-wp; +}; + +&sdhci1 { + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; +}; + +&cpsw_port2 { + /* PCB provides an internal delay of 2ns */ + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&fss { + bootph-all; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-pre-ram; + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 1c6812a8ae9b..52954c77df80 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -8,310 +8,16 @@ /dts-v1/; #include "k3-am625.dtsi" -#include "k3-am62x-sk-common.dtsi" +#include "k3-am625-sk-common.dtsi" / { compatible = "ti,am625-sk", "ti,am625"; model = "Texas Instruments AM625 SK"; - opp-table { - /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */ - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-supported-hw = <0x01 0x0004>; - clock-latency-ns = <6000000>; - }; - }; - memory@80000000 { /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; device_type = "memory"; bootph-pre-ram; }; - - vmain_pd: regulator-0 { - /* TPS65988 PD CONTROLLER OUTPUT */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vmain_pd"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_5v0: regulator-1 { - /* Output of LM34936 */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vcc_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vmain_pd>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_3v3_sys: regulator-2 { - /* output of LM61460-Q1 */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_sys"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vmain_pd>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_mmc1: regulator-3 { - /* TPS22918DBVR */ - bootph-all; - compatible = "regulator-fixed"; - regulator-name = "vdd_mmc1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - enable-active-high; - vin-supply = <&vcc_3v3_sys>; - gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; - }; - - vdd_sd_dv: regulator-4 { - /* Output of TLV71033 */ - bootph-all; - compatible = "regulator-gpio"; - regulator-name = "tlv71033"; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_sd_dv_pins_default>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - vin-supply = <&vcc_5v0>; - gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; - states = <1800000 0x0>, - <3300000 0x1>; - }; - - vcc_1v8: regulator-5 { - /* output of TPS6282518DMQ */ - compatible = "regulator-fixed"; - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3_sys>; - regulator-always-on; - regulator-boot-on; - }; -}; - -&main_pmx0 { - main_mmc0_pins_default: main-mmc0-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ - AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ - AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ - AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ - AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ - AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ - AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ - AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ - AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ - AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ - >; - }; - - main_rgmii2_pins_default: main-rgmii2-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ - AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ - AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ - AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ - AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ - AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ - AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ - AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ - AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ - AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ - AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ - AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ - >; - }; - - ospi0_pins_default: ospi0-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ - AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ - AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ - AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ - AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ - AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ - AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ - AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ - AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ - AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ - AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ - >; - }; - - vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ - >; - }; - - main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { - bootph-all; - pinctrl-single,pins = < - AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ - >; - }; -}; - -&main_gpio0 { - bootph-all; -}; - -&main_gpio1 { - bootph-all; -}; - -&main_i2c1 { - bootph-all; - exp1: gpio@22 { - bootph-all; - compatible = "ti,tca6424"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", - "PRU_DETECT", "MMC1_SD_EN", - "VPP_LDO_EN", "EXP_PS_3V3_En", - "EXP_PS_5V0_En", "EXP_HAT_DETECT", - "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", - "UART1_FET_BUF_EN", "WL_LT_EN", - "GPIO_HDMI_RSTn", "CSI_GPIO1", - "CSI_GPIO2", "PRU_3V3_EN", - "HDMI_INTn", "PD_I2C_IRQ", - "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", - "MCASP1_FET_SEL", "UART1_FET_SEL", - "TSINT#", "IO_EXP_TEST_LED"; - - interrupt-parent = <&main_gpio1>; - interrupts = <23 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - - pinctrl-names = "default"; - pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; - }; -}; - -&sdhci0 { - bootph-all; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc0_pins_default>; - status = "okay"; -}; - -&sdhci1 { - vmmc-supply = <&vdd_mmc1>; - vqmmc-supply = <&vdd_sd_dv>; -}; - -&cpsw3g { - pinctrl-names = "default"; - pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; -}; - -&cpsw_port2 { - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy1>; -}; - -&cpsw3g_mdio { - cpsw3g_phy1: ethernet-phy@1 { - reg = <1>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - }; -}; - -&fss { - bootph-all; -}; - -&ospi0 { - bootph-all; - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&ospi0_pins_default>; - - flash@0 { - bootph-all; - compatible = "jedec,spi-nor"; - reg = <0x0>; - spi-tx-bus-width = <8>; - spi-rx-bus-width = <8>; - spi-max-frequency = <25000000>; - cdns,tshsl-ns = <60>; - cdns,tsd2d-ns = <60>; - cdns,tchsh-ns = <60>; - cdns,tslch-ns = <60>; - cdns,read-delay = <4>; - - partitions { - bootph-all; - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "ospi.tiboot3"; - reg = <0x0 0x80000>; - }; - - partition@80000 { - label = "ospi.tispl"; - reg = <0x80000 0x200000>; - }; - - partition@280000 { - label = "ospi.u-boot"; - reg = <0x280000 0x400000>; - }; - - partition@680000 { - label = "ospi.env"; - reg = <0x680000 0x40000>; - }; - - partition@6c0000 { - label = "ospi.env.backup"; - reg = <0x6c0000 0x40000>; - }; - - partition@800000 { - label = "ospi.rootfs"; - reg = <0x800000 0x37c0000>; - }; - - partition@3fc0000 { - bootph-pre-ram; - label = "ospi.phypattern"; - reg = <0x3fc0000 0x40000>; - }; - }; - }; -}; - -&tlv320aic3106 { - DVDD-supply = <&vcc_1v8>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am6254atl-sk.dts b/arch/arm64/boot/dts/ti/k3-am6254atl-sk.dts new file mode 100644 index 000000000000..055e63a3fbb1 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am6254atl-sk.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * AM6254atl SiP SK: https://www.ti.com/lit/df/sprr482b/sprr482b.zip + * Webpage: https://www.ti.com/tool/SK-AM62-SIP + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am6254atl.dtsi" +#include "k3-am625-sk-common.dtsi" + +/ { + model = "Texas Instruments AM6254atl SK"; + compatible = "ti,am6254atl-sk", "ti,am6254atl", "ti,am625"; +}; From 7efc354b7fe1ac5e874d0188b3d6be88a3fa0fe4 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Mon, 8 Sep 2025 18:52:06 -0500 Subject: [PATCH 739/931] arm64: dts: ti: k3-am62p/j722s: Remove HS400 support from common Since eMMC HS400 has been descoped for J722s due to errata i2478 [0] and is supported for AM62Px device, remove eMMC HS400 support from common-main.dtsi and include only in am62p-main.dtsi. [0] https://www.ti.com/lit/pdf/sprz575 Signed-off-by: Judith Mendez Reviewed-by: Andrew Davis Reviewed-by: Moteen Shah Link: https://patch.msgid.link/20250908235207.473628-2-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 3 --- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 6 ++++++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 4427b12058a6..0c05bcf1d776 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -576,15 +576,12 @@ sdhci0: mmc@fa10000 { bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; - mmc-hs400-1_8v; ti,clkbuf-sel = <0x7>; - ti,strobe-sel = <0x77>; ti,trm-icp = <0x8>; ti,otap-del-sel-legacy = <0x1>; ti,otap-del-sel-mmc-hs = <0x1>; ti,otap-del-sel-ddr52 = <0x6>; ti,otap-del-sel-hs200 = <0x8>; - ti,otap-del-sel-hs400 = <0x5>; ti,itap-del-sel-legacy = <0x10>; ti,itap-del-sel-mmc-hs = <0xa>; ti,itap-del-sel-ddr52 = <0x3>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index 6aea9d3f134e..020bd121a6a3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -74,3 +74,9 @@ &main_gpio1 { gpio-reserved-ranges = <32 10>; ti,ngpio = <52>; }; + +&sdhci0 { + mmc-hs400-1_8v; + ti,strobe-sel = <0x77>; + ti,otap-del-sel-hs400 = <0x5>; +}; From 9fdcc5f98141cf2f77e8778bee830190d7b71ced Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Mon, 8 Sep 2025 18:52:07 -0500 Subject: [PATCH 740/931] arm64: dts: ti: k3-am62p: Update eMMC HS400 STRB value STRB setting for eMMC HS400 have been updated in device datasheet [0], so update for am62p in k3-am62p-main. [0] https://www.ti.com/lit/gpn/am62p Signed-off-by: Judith Mendez Link: https://patch.msgid.link/20250908235207.473628-3-jm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index 020bd121a6a3..908cc0760e7d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -77,6 +77,6 @@ &main_gpio1 { &sdhci0 { mmc-hs400-1_8v; - ti,strobe-sel = <0x77>; + ti,strobe-sel = <0x66>; ti,otap-del-sel-hs400 = <0x5>; }; From 4c4e48afb6d85c1a8f9fdbae1fdf17ceef4a6f5b Mon Sep 17 00:00:00 2001 From: Vibhore Vardhan Date: Wed, 3 Sep 2025 11:55:12 +0530 Subject: [PATCH 741/931] arm64: dts: ti: k3-am62a-main: Fix main padcfg length The main pad configuration register region starts with the register MAIN_PADCFG_CTRL_MMR_CFG0_PADCONFIG0 with address 0x000f4000 and ends with the MAIN_PADCFG_CTRL_MMR_CFG0_PADCONFIG150 register with address 0x000f4258, as a result of which, total size of the region is 0x25c instead of 0x2ac. Reference Docs TRM (AM62A) - https://www.ti.com/lit/ug/spruj16b/spruj16b.pdf TRM (AM62D) - https://www.ti.com/lit/ug/sprujd4/sprujd4.pdf Fixes: 5fc6b1b62639c ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Cc: stable@vger.kernel.org Signed-off-by: Vibhore Vardhan Signed-off-by: Paresh Bhagat Reviewed-by: Siddharth Vadapalli Link: https://patch.msgid.link/20250903062513.813925-2-p-bhagat@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index d5f018768981..829f00adea6e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -267,7 +267,7 @@ secure_proxy_sa3: mailbox@43600000 { main_pmx0: pinctrl@f4000 { compatible = "pinctrl-single"; - reg = <0x00 0xf4000 0x00 0x2ac>; + reg = <0x00 0xf4000 0x00 0x25c>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; From 5cd40f33273bb41b5eec763bcfc7c9b2e9fe2e64 Mon Sep 17 00:00:00 2001 From: Paresh Bhagat Date: Wed, 3 Sep 2025 11:55:13 +0530 Subject: [PATCH 742/931] arm64: dts: ti: k3-am62d2-evm: Enable USB support Add pinmux configuration for USB1 interface and enable the node for functionality. Also enable data transfer on USB0, on existing power delivery configuration. Co-developed-by: Siddharth Vadapalli Signed-off-by: Siddharth Vadapalli Signed-off-by: Paresh Bhagat Reviewed-by: Hrushikesh Salunke Link: https://patch.msgid.link/20250903062513.813925-3-p-bhagat@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts index c958a1c4a657..6cb2339869b5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -343,6 +343,12 @@ usr_led_pins_default: usr-led-default-pins { AM62DX_IOPAD(0x0244, PIN_INPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */ >; }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (D19) USB1_DRVVBUS */ + >; + }; }; &mcu_gpio0 { @@ -475,6 +481,11 @@ &main_uart0 { status = "okay"; }; +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + &usb0 { usb-role-switch; @@ -485,6 +496,16 @@ usb0_hs_ep: endpoint { }; }; +&usbss1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; + &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>, From 1a1066f553df1777ffa5ede050457e41972f34f4 Mon Sep 17 00:00:00 2001 From: Paresh Bhagat Date: Wed, 13 Aug 2025 14:33:00 +0530 Subject: [PATCH 743/931] arm64: dts: ti: k3-am62d2-evm: Add support for OSPI flash AM62D2 EVM has S28HS512T 64 MiB Octal SPI NOR flash connected to the OSPI interface. Add support for the flash and describe the partition information as per bootloader. Signed-off-by: Paresh Bhagat Reviewed-by: Santhosh Kumar K Link: https://patch.msgid.link/20250813090300.733295-1-p-bhagat@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 86 ++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts index 6cb2339869b5..83af889e790a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -25,6 +25,7 @@ aliases { rtc0 = &wkup_rtc0; ethernet0 = &cpsw_port1; ethernet1 = &cpsw_port2; + spi0 = &ospi0; }; chosen { @@ -349,6 +350,26 @@ main_usb1_pins_default: main-usb1-default-pins { AM62DX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (D19) USB1_DRVVBUS */ >; }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (L22) OSPI0_CLK */ + AM62DX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (H21) OSPI0_CSn0 */ + AM62DX_IOPAD(0x0030, PIN_OUTPUT, 0) /* (G19) OSPI0_CSn1 */ + AM62DX_IOPAD(0x0034, PIN_OUTPUT, 0) /* (K20) OSPI0_CSn2 */ + AM62DX_IOPAD(0x0038, PIN_OUTPUT, 0) /* (G20) OSPI0_CSn3 */ + AM62DX_IOPAD(0x000c, PIN_INPUT, 0) /* (J21) OSPI0_D0 */ + AM62DX_IOPAD(0x0010, PIN_INPUT, 0) /* (J18) OSPI0_D1 */ + AM62DX_IOPAD(0x0014, PIN_INPUT, 0) /* (J19) OSPI0_D2 */ + AM62DX_IOPAD(0x0018, PIN_INPUT, 0) /* (H18) OSPI0_D3 */ + AM62DX_IOPAD(0x001c, PIN_INPUT, 0) /* (K21) OSPI0_D4 */ + AM62DX_IOPAD(0x0020, PIN_INPUT, 0) /* (H19) OSPI0_D5 */ + AM62DX_IOPAD(0x0024, PIN_INPUT, 0) /* (J20) OSPI0_D6 */ + AM62DX_IOPAD(0x0028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62DX_IOPAD(0x0008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */ + >; + bootph-all; + }; }; &mcu_gpio0 { @@ -548,6 +569,71 @@ cpsw3g_phy1: ethernet-phy@3 { }; }; +&fss { + status = "okay"; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + status = "okay"; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + bootph-all; + }; + }; + }; +}; + &wkup_r5fss0_core0 { bootph-pre-ram; }; From c881d1c37b2c159d908203dba5c4920bc776046f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 10 Jun 2025 14:34:30 +0800 Subject: [PATCH 744/931] arm64: dts: mediatek: mt8188: Change efuse fallback compatible to mt8186 The efuse block in the MT8188 contains the GPU speed bin cell, and like the MT8186 one, has the same conversion scheme to work with the GPU OPP binding. This was reflected in a corresponding change to the efuse DT binding. Change the fallback compatible of the MT8188's efuse block from the generic one to the MT8186 one. This also makes GPU DVFS work properly. Fixes: d39aacd1021a ("arm64: dts: mediatek: mt8188: add lvts definitions") Fixes: 50e7592cb696 ("arm64: dts: mediatek: mt8188: Add GPU speed bin NVMEM cells") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250610063431.2955757-3-wenst@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 202478407727..90c388f1890f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -2183,7 +2183,7 @@ imp_iic_wrap_en: clock-controller@11ec2000 { }; efuse: efuse@11f20000 { - compatible = "mediatek,mt8188-efuse", "mediatek,efuse"; + compatible = "mediatek,mt8188-efuse", "mediatek,mt8186-efuse"; reg = <0 0x11f20000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; From 0370911565869384f19b35ea9e71ee7a57b48a33 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 12 Aug 2025 17:01:34 +0800 Subject: [PATCH 745/931] arm64: dts: mediatek: mt8186-tentacruel: Fix touchscreen model The touchscreen controller used with the original Krabby design is the Elan eKTH6918, which is in the same family as eKTH6915, but supporting a larger screen size with more sense lines. OTOH, the touchscreen controller that actually shipped on the Tentacruel devices is the Elan eKTH6A12NAY. A compatible string was added for it specifically because it has different power sequencing timings. Fix up the touchscreen nodes for both these. This also includes adding a previously missing reset line. Also add "no-reset-on-power-off" since the power is always on, and putting it in reset would consume more power. Fixes: 8855d01fb81f ("arm64: dts: mediatek: Add MT8186 Krabby platform based Tentacruel / Tentacool") Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20250812090135.3310374-1-wenst@chromium.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi | 8 ++++---- .../dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts | 4 ++++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi index 7c971198fa95..72a2a2bff0a9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi @@ -71,14 +71,14 @@ &i2c1 { i2c-scl-internal-delay-ns = <10000>; touchscreen: touchscreen@10 { - compatible = "hid-over-i2c"; + compatible = "elan,ekth6915"; reg = <0x10>; interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&touchscreen_pins>; - post-power-on-delay-ms = <10>; - hid-descr-addr = <0x0001>; - vdd-supply = <&pp3300_s3>; + reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>; + vcc33-supply = <&pp3300_s3>; + no-reset-on-power-off; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts index 26d3451a5e47..24d9ede63eaa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts @@ -42,3 +42,7 @@ MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) CROS_STD_MAIN_KEYMAP >; }; + +&touchscreen { + compatible = "elan,ekth6a12nay"; +}; From e36be19823f0e666de2994bb39ab8d8495da6709 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 14 Aug 2025 17:25:08 +0800 Subject: [PATCH 746/931] arm64: dts: mediatek: mt8188-geralt: Enable first SCP core The first SCP core is used to drive the video decoder and encoders. Signed-off-by: Chen-Yu Tsai Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20250814092510.211672-1-wenst@chromium.org Signed-off-by: Matthias Brugger --- .../boot/dts/mediatek/mt8188-geralt.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi index c5254ae0bb99..7fedbacdac44 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -164,6 +164,12 @@ reserved_memory: reserved-memory { #size-cells = <2>; ranges; + scp_mem_reserved: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x800000>; + no-map; + }; + apu_mem: memory@55000000 { compatible = "shared-dma-pool"; reg = <0 0x55000000 0 0x1400000>; @@ -1077,6 +1083,13 @@ pins-bus { }; }; + scp_pins: scp-pins { + pins-scp-vreq { + pinmux = ; + bias-disable; + }; + }; + spi0_pins: spi0-pins { pins-bus { pinmux = , @@ -1146,6 +1159,18 @@ &postmask0_out { remote-endpoint = <&dither0_in>; }; +&scp_cluster { + status = "okay"; +}; + +&scp_c0 { + pinctrl-names = "default"; + pinctrl-0 = <&scp_pins>; + firmware-name = "mediatek/mt8188/scp.img"; + memory-region = <&scp_mem_reserved>; + status = "okay"; +}; + &sound { pinctrl-names = "aud_etdm_hp_on", "aud_etdm_hp_off", "aud_etdm_spk_on", "aud_etdm_spk_off", From 36d05f21da4d1879f7e81f18eae85f34e9c64aa5 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Thu, 4 Sep 2025 11:05:30 -0500 Subject: [PATCH 747/931] arm64: dts: rockchip: Add USB and charger to Gameforce Ace Add support for the BQ25703A charger manager and boost regulator to the Gameforce Ace. Add the USB-C port and PHY as well as they all depend on each other for operation. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20250904160530.66178-6-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588s-gameforce-ace.dts | 122 ++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts index 55fc7cbef58d..f5894672fcbd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts @@ -612,6 +612,56 @@ &i2c6 { pinctrl-0 = <&i2c6m3_xfer>; status = "okay"; + fusb302: typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&usbc0_int>; + pinctrl-names = "default"; + vbus-supply = <&usb_otg_vbus>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + usbc0_role_sw: endpoint { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + + port@2 { + reg = <2>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + rtc_hym8563: rtc@51 { compatible = "haoyu,hym8563"; reg = <0x51>; @@ -640,8 +690,34 @@ battery@62 { 0x2F 0x00 0x64 0xA5 0xB5 0x1C 0xF0 0x49>; cellwise,monitor-interval-ms = <5000>; monitored-battery = <&battery>; + power-supplies = <&bq25703>; status = "okay"; }; + + bq25703: charger@6b { + compatible = "ti,bq25703a"; + reg = <0x6b>; + input-current-limit-microamp = <5000000>; + interrupt-parent = <&gpio0>; + interrupts = ; + monitored-battery = <&battery>; + pinctrl-0 = <&charger_int_h>; + pinctrl-names = "default"; + power-supplies = <&fusb302>; + + regulators { + usb_otg_vbus: vbus { + enable-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&boost_enable_h>; + pinctrl-names = "default"; + regulator-max-microamp = <960000>; + regulator-max-microvolt = <5088000>; + regulator-min-microamp = <512000>; + regulator-min-microvolt = <4992000>; + regulator-name = "usb_otg_vbus"; + }; + }; + }; }; &i2c7 { @@ -853,6 +929,12 @@ usbc0_int: usbc0-int { rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; }; + + usbc_sbu_dc: usbc-sbu-dc { + rockchip,pins = + <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; vcc3v3-lcd { @@ -1286,6 +1368,46 @@ bluetooth { }; }; +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdp_phy0 { + mode-switch; + orientation-switch; + pinctrl-0 = <&usbc_sbu_dc>; + pinctrl-names = "default"; + sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + rockchip,dp-lane-mux = <2 3>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + &vop { status = "okay"; }; From fe0e018b05f118cb8e5c8cd77dd74185b2cb7177 Mon Sep 17 00:00:00 2001 From: Akashdeep Kaur Date: Tue, 9 Sep 2025 10:11:05 +0530 Subject: [PATCH 748/931] arm64: dts: ti: k3-am62p5-sk: Remove the unused cfg in USB1_DRVVBUS After the SoC has entered the DeepSleep low power mode, USB1 can be used to wakeup the SoC based on USB events triggered by USB devices. This requires that the pin corresponding to the Type-A connector remains pulled up even after the SoC has entered the DeepSleep low power mode. For that, either DeepSleep pullup configuration can be selected or the pin can have the same configuration that it had when SoC was in active mode. Remove the unnecessary DeepSleep state configuration from USB1_DRVBUS pin, as the DeepSleep control bit is not set and the active configuration is sufficient to keep the pin pulled up. This simplifies the setup and removes redundant configuration. This reverts commit 115290c112952db27009668aa7ae2f29920704f0. Tested-by: Kendall Willis Reviewed-by: Dhruva Gole Signed-off-by: Akashdeep Kaur Reviewed-by: Kendall Willis Acked-by: Siddharth Vadapalli Link: https://patch.msgid.link/20250909044108.2541534-2-a-kaur@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 56f0eb11b902..b211ec7b35b8 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -348,7 +348,7 @@ AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR.UART1_TXD */ main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < - AM62PX_IOPAD(0x0258, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (G21) USB1_DRVVBUS */ + AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ >; }; From 121babfed84a0c6d7ebee4486db4fbd9a900d9f5 Mon Sep 17 00:00:00 2001 From: Akashdeep Kaur Date: Tue, 9 Sep 2025 10:11:06 +0530 Subject: [PATCH 749/931] arm64: dts: ti: k3-am62x-sk-common: Remove the unused cfg in USB1_DRVVBUS After the SoC has entered the DeepSleep low power mode, USB1 can be used to wakeup the SoC based on USB events triggered by USB devices. This requires that the pin corresponding to the Type-A connector remains pulled up even after the SoC has entered the DeepSleep low power mode. For that, either DeepSleep pullup configuration can be selected or the pin can have the same configuration that it had when SoC was in active mode. Remove the unnecessary DeepSleep state configuration from USB1_DRVBUS pin, as the DeepSleep control bit is not set and the active configuration is sufficient to keep the pin pulled up. This simplifies the setup and removes redundant configuration. This reverts commit 527f884d2d94981016e181dcbd4c4b5bf597c0ad. Tested-by: Kendall Willis Reviewed-by: Dhruva Gole Signed-off-by: Akashdeep Kaur Reviewed-by: Kendall Willis Acked-by: Siddharth Vadapalli Link: https://patch.msgid.link/20250909044108.2541534-3-a-kaur@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index af549104af47..edf82b9a556d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -229,7 +229,7 @@ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */ main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < - AM62X_IOPAD(0x0258, PIN_OUTPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (F18/E16) USB1_DRVVBUS */ + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ >; }; From 42558822658e0ad249a8f109fd053e3bad4476e9 Mon Sep 17 00:00:00 2001 From: Akashdeep Kaur Date: Tue, 9 Sep 2025 10:11:07 +0530 Subject: [PATCH 750/931] arm64: dts: ti: k3-pinctrl: Add the remaining macros Add the drive strength, schmitt trigger enable macros to pinctrl file. Add the missing macros for DeepSleep configuration control referenced from "Table 14-8769. Description Of The Pad Configuration Register Bits" in AM62Px TRM[0]. Add some DeepSleep macros to provide combinations that can be used directly in device tree files example PIN_DS_OUTPUT_LOW that configures pin to be output and also sets its value to 0. [0] https://www.ti.com/lit/pdf/SPRUJ83 Reviewed-by: Dhruva Gole Reviewed-by: Vignesh Raghavendra Signed-off-by: Akashdeep Kaur Reviewed-by: Kendall Willis Link: https://patch.msgid.link/20250909044108.2541534-4-a-kaur@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 47 ++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h index c0f09be8d3f9..8ce37ace94c9 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -3,15 +3,20 @@ * This header provides constants for pinctrl bindings for TI's K3 SoC * family. * - * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #ifndef DTS_ARM64_TI_K3_PINCTRL_H #define DTS_ARM64_TI_K3_PINCTRL_H +#define WKUP_LVL_EN_SHIFT (7) +#define WKUP_LVL_POL_SHIFT (8) #define ST_EN_SHIFT (14) #define PULLUDEN_SHIFT (16) #define PULLTYPESEL_SHIFT (17) #define RXACTIVE_SHIFT (18) +#define DRV_STR_SHIFT (19) +#define ISO_OVERRIDE_EN_SHIFT (22) +#define ISO_BYPASS_EN_SHIFT (23) #define DEBOUNCE_SHIFT (11) #define FORCE_DS_EN_SHIFT (15) #define DS_EN_SHIFT (24) @@ -19,6 +24,7 @@ #define DS_OUT_VAL_SHIFT (26) #define DS_PULLUD_EN_SHIFT (27) #define DS_PULLTYPE_SEL_SHIFT (28) +#define WKUP_EN_SHIFT (29) /* Schmitt trigger configuration */ #define ST_DISABLE (0 << ST_EN_SHIFT) @@ -33,6 +39,29 @@ #define INPUT_EN (1 << RXACTIVE_SHIFT) #define INPUT_DISABLE (0 << RXACTIVE_SHIFT) +#define DS_PULL_DISABLE (1 << DS_PULLUD_EN_SHIFT) +#define DS_PULL_ENABLE (0 << DS_PULLUD_EN_SHIFT) + +#define DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENABLE) +#define DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT | DS_PULL_ENABLE) + +#define DS_STATE_EN (1 << DS_EN_SHIFT) +#define DS_STATE_DISABLE (0 << DS_EN_SHIFT) + +#define DS_INPUT_EN (1 << DS_OUT_DIS_SHIFT | DS_STATE_EN) +#define DS_INPUT_DISABLE (0 << DS_OUT_DIS_SHIFT | DS_STATE_EN) + +#define DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) +#define DS_OUT_VALUE_ONE (1 << DS_OUT_VAL_SHIFT) + +/* Configuration to enable wake-up on pin activity */ +#define WKUP_ENABLE (1 << WKUP_EN_SHIFT) +#define WKUP_DISABLE (0 << WKUP_EN_SHIFT) +#define WKUP_ON_LEVEL (1 << WKUP_LVL_EN_SHIFT) +#define WKUP_ON_EDGE (0 << WKUP_LVL_EN_SHIFT) +#define WKUP_LEVEL_LOW (0 << WKUP_LVL_POL_SHIFT) +#define WKUP_LEVEL_HIGH (1 << WKUP_LVL_POL_SHIFT) + /* Only these macros are expected be used directly in device tree files */ #define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) #define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) @@ -53,6 +82,10 @@ #define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) #define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) +#define PIN_DRIVE_STRENGTH_NOMINAL (0 << DRV_STR_SHIFT) +#define PIN_DRIVE_STRENGTH_SLOW (1 << DRV_STR_SHIFT) +#define PIN_DRIVE_STRENGTH_FAST (2 << DRV_STR_SHIFT) + #define PIN_DS_FORCE_DISABLE (0 << FORCE_DS_EN_SHIFT) #define PIN_DS_FORCE_ENABLE (1 << FORCE_DS_EN_SHIFT) #define PIN_DS_IO_OVERRIDE_DISABLE (0 << DS_IO_OVERRIDE_EN_SHIFT) @@ -65,6 +98,18 @@ #define PIN_DS_PULLUD_DISABLE (1 << DS_PULLUD_EN_SHIFT) #define PIN_DS_PULL_DOWN (0 << DS_PULLTYPE_SEL_SHIFT) #define PIN_DS_PULL_UP (1 << DS_PULLTYPE_SEL_SHIFT) +#define PIN_DS_ISO_BYPASS (1 << ISO_BYPASS_EN_SHIFT) +#define PIN_DS_ISO_BYPASS_DISABLE (0 << ISO_BYPASS_EN_SHIFT) + +#define PIN_DS_OUTPUT_LOW (DS_INPUT_DISABLE | DS_OUT_VALUE_ZERO) +#define PIN_DS_OUTPUT_HIGH (DS_INPUT_DISABLE | DS_OUT_VALUE_ONE) +#define PIN_DS_INPUT (DS_INPUT_EN | DS_PULL_DISABLE) +#define PIN_DS_INPUT_PULLUP (DS_INPUT_EN | DS_PULL_UP) +#define PIN_DS_INPUT_PULLDOWN (DS_INPUT_EN | DS_PULL_DOWN) + +#define PIN_WKUP_EN_LEVEL_LOW (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_LOW) +#define PIN_WKUP_EN_LEVEL_HIGH (WKUP_ENABLE | WKUP_ON_LEVEL | WKUP_LEVEL_HIGH) +#define PIN_WKUP_EN (WKUP_ENABLE | WKUP_ON_EDGE) /* Default mux configuration for gpio-ranges to use with pinctrl */ #define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7) From 2e79ee4d64e9ba4a3fc90e91dfd715407efab16d Mon Sep 17 00:00:00 2001 From: Akashdeep Kaur Date: Tue, 9 Sep 2025 10:11:08 +0530 Subject: [PATCH 751/931] arm64: dts: ti: k3-pinctrl: Fix the bug in existing macros Currently, DS_IO_OVERRIDE_EN_SHIFT macro is not defined anywhere but used for defining other macro. Replace this undefined macro with valid macro. Rename the existing macro to reflect the actual behavior. Fixes: 325aa0f6b36e ("arm64: dts: ti: k3-pinctrl: Introduce deep sleep macros") Reviewed-by: Kendall Willis Reviewed-by: Dhruva Gole Reviewed-by: Vignesh Raghavendra Signed-off-by: Akashdeep Kaur Fixes: 325aa0f6b36e ("arm64: dts: ti: k3-pinctrl: Introduce deep sleep macros") Link: https://patch.msgid.link/20250909044108.2541534-5-a-kaur@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-pinctrl.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h index 8ce37ace94c9..e46f7bf52701 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -88,8 +88,8 @@ #define PIN_DS_FORCE_DISABLE (0 << FORCE_DS_EN_SHIFT) #define PIN_DS_FORCE_ENABLE (1 << FORCE_DS_EN_SHIFT) -#define PIN_DS_IO_OVERRIDE_DISABLE (0 << DS_IO_OVERRIDE_EN_SHIFT) -#define PIN_DS_IO_OVERRIDE_ENABLE (1 << DS_IO_OVERRIDE_EN_SHIFT) +#define PIN_DS_ISO_OVERRIDE_DISABLE (0 << ISO_OVERRIDE_EN_SHIFT) +#define PIN_DS_ISO_OVERRIDE_ENABLE (1 << ISO_OVERRIDE_EN_SHIFT) #define PIN_DS_OUT_ENABLE (0 << DS_OUT_DIS_SHIFT) #define PIN_DS_OUT_DISABLE (1 << DS_OUT_DIS_SHIFT) #define PIN_DS_OUT_VALUE_ZERO (0 << DS_OUT_VAL_SHIFT) From 6fdcb1013f13f87cdebd94ab8aa2f8ea2c644a33 Mon Sep 17 00:00:00 2001 From: Rahul T R Date: Fri, 5 Sep 2025 15:13:25 +0530 Subject: [PATCH 752/931] arm64: dts: ti: k3-j721e-main: Add DSI and DPHY-TX TI's J721E SoC supports a DPI to DSI video signal conversion bridge on it's platform bus. The IP is from Cadence, and it has a custom TI wrapper around it to facilitate integration. This IP takes the DPI video signals from DSS and alongwith the DPHY IP, it transmits DSI video signals out of the SoC. Add support for DSI bridge and the DPHY-TX. Signed-off-by: Rahul T R Signed-off-by: Jayesh Choudhary Signed-off-by: Harikrishna Shenoy Link: https://patch.msgid.link/20250905094325.472473-1-h-shenoy@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 39 +++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index e748f704e3b6..d5fd30a01032 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1887,6 +1887,45 @@ port@4 { }; }; + dphy2: phy@4480000 { + compatible = "ti,j721e-dphy"; + reg = <0x00 0x04480000 0x00 0x1000>; + clocks = <&k3_clks 296 1>, <&k3_clks 296 3>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + power-domains = <&k3_pds 296 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 296 3>; + assigned-clock-parents = <&k3_clks 296 4>; + assigned-clock-rates = <19200000>; + status = "disabled"; + }; + + dsi0: dsi@4800000 { + compatible = "ti,j721e-dsi"; + reg = <0x00 0x04800000 0x00 0x100000>, <0x00 0x04710000 0x00 0x100>; + clocks = <&k3_clks 150 1>, <&k3_clks 150 5>; + clock-names = "dsi_p_clk", "dsi_sys_clk"; + power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; + interrupt-parent = <&gic500>; + interrupts = ; + phys = <&dphy2>; + phy-names = "dphy"; + status = "disabled"; + + dsi0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = From 47315d395a98a56f8854a2085f887fb18a8217d9 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Tue, 2 Sep 2025 11:00:06 +0530 Subject: [PATCH 753/931] arm64: dts: ti: k3-am62a7-sk: Add bootph-all tag to usb0_phy_ctrl node Add bootph-all property to the USB0 PHY controller node to make it available during all boot phases. This is required for USB DFU boot. Signed-off-by: Hrushikesh Salunke Reviewed-by: Siddharth Vadapalli Reviewed-by: Judith Mendez Link: https://patch.msgid.link/20250902053009.1732607-2-h-salunke@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 9f148b89e74d..af591fe6ae4f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -705,6 +705,10 @@ usb0_hs_ep: endpoint { }; }; +&usb0_phy_ctrl { + bootph-all; +}; + &usbss1 { status = "okay"; }; From 398af33bedc1a64f7045be065e1e17e292cc1c60 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Tue, 2 Sep 2025 11:00:07 +0530 Subject: [PATCH 754/931] arm64: dts: ti: k3-am62p5-sk: Add bootph-all tag to usb0_phy_ctrl node Add bootph-all property to the USB0 PHY controller node to make it available during all boot phases. This is required for USB DFU boot. Signed-off-by: Hrushikesh Salunke Reviewed-by: Siddharth Vadapalli Reviewed-by: Judith Mendez Link: https://patch.msgid.link/20250902053009.1732607-3-h-salunke@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index b211ec7b35b8..a064a632680e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -595,6 +595,10 @@ usb0_hs_ep: endpoint { }; }; +&usb0_phy_ctrl { + bootph-all; +}; + &usb1 { dr_mode = "host"; pinctrl-names = "default"; From 69cd3e0eef26edbc39dca06522f6ae289448d172 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Tue, 2 Sep 2025 11:00:08 +0530 Subject: [PATCH 755/931] arm64: dts: ti: k3-am62x-sk-common: Add bootph-all tag to usb0_phy_ctrl node Add bootph-all property to the USB0 PHY controller node to make it available during all boot phases. This is required for USB DFU boot. Signed-off-by: Hrushikesh Salunke Reviewed-by: Siddharth Vadapalli Reviewed-by: Judith Mendez Link: https://patch.msgid.link/20250902053009.1732607-4-h-salunke@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index edf82b9a556d..58f78c0de292 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -479,6 +479,10 @@ usb0_hs_ep: endpoint { }; }; +&usb0_phy_ctrl { + bootph-all; +}; + &usb1 { dr_mode = "host"; pinctrl-names = "default"; From 5cad4ce9a7b82118cfeeb764e1a555a5789c22e3 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Tue, 2 Sep 2025 11:00:09 +0530 Subject: [PATCH 756/931] arm64: dts: ti: k3-j722s-evm: Add bootph-all tag to usb0_phy_ctrl node Add bootph-all property to the USB0 PHY controller node to make it available during all boot phases. This is required for USB DFU boot. Signed-off-by: Hrushikesh Salunke Reviewed-by: Siddharth Vadapalli Reviewed-by: Judith Mendez Link: https://patch.msgid.link/20250902053009.1732607-5-h-salunke@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index a9b5d9a06241..e0e303da7e15 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -784,6 +784,10 @@ &usb0 { usb-role-switch; }; +&usb0_phy_ctrl { + bootph-all; +}; + &usbss1 { pinctrl-names = "default"; pinctrl-0 = <&main_usb1_pins_default>; From 03c7b1f0ee9f7c8d047a6ea5767ac96490d1385c Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Tue, 9 Sep 2025 23:37:39 +0200 Subject: [PATCH 757/931] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P Add devicetree bindings for Variscite VAR-SOM-AM62P System on Module and its carrier boards. Signed-off-by: Stefano Radaelli Reviewed-by: Judith Mendez Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250909213749.28098-2-stefano.radaelli21@gmail.com Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index f98817e97d4c..0105dcda6e04 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -113,6 +113,12 @@ properties: - const: toradex,verdin-am62p # Verdin AM62P Module - const: ti,am62p5 + - description: K3 AM62P5 SoC Variscite SOM and Carrier Boards + items: + - const: variscite,var-som-am62p-symphony + - const: variscite,var-som-am62p + - const: ti,am62p5 + - description: K3 AM642 SoC items: - enum: From 571562e76458682231453a561d5df0c8e91c461d Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Tue, 9 Sep 2025 23:37:40 +0200 Subject: [PATCH 758/931] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P Add device tree support for the Variscite VAR-SOM-AM62P system on module. This SOM is designed to be used with various carrier boards. The module includes: - AM62P Sitara MPU processor - Up to 8GB of DDR4-3733 memory - eMMC storage memory - PS6522430 chip as a Power Management Integrated circuit (PMIC) - Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices ADIN1300 - Resistive touch panel interface controller TI TSC2046 - I2C interfaces Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://www.variscite.it/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/ Signed-off-by: Stefano Radaelli Reviewed-by: Judith Mendez Link: https://patch.msgid.link/20250909213749.28098-3-stefano.radaelli21@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 387 ++++++++++++++++++ 1 file changed, 387 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi new file mode 100644 index 000000000000..edaa4f99295d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common dtsi for Variscite VAR-SOM-AM62P + * + * Link: https://www.variscite.com/product/system-on-module-som/cortex-a53-krait/var-som-am62p-ti-sitara-am62px/ + * + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "k3-am62p5.dtsi" + +/ { + compatible = "variscite,var-som-am62p", "ti,am62p5"; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */ + <&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + }; + + mmc_pwrseq: mmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc_pwrseq>; + reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>; + }; + + memory@80000000 { + /* 8G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type = "memory"; + bootph-pre-ram; + }; + + opp-table { + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b500000 0x00 0x00300000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b800000 0x00 0x00100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b900000 0x00 0x00f00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x00100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + no-map; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "On-module +V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "On-module +V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_3v3>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3v3_phy: regulator-3v3-phy { + compatible = "regulator-fixed"; + regulator-name = "On-module +V3.3_PHY"; + gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio1>; + status = "okay"; + + cpsw3g_phy0: ethernet-phy@4 { + compatible = "ethernet-phy-id0283.bc30"; + reg = <4>; + reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + }; +}; + +&cpsw_port1 { + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <&cpsw3g_phy0>; + status = "okay"; +}; + +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; +}; + +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; +}; + +&main_pmx0 { + pinctrl_mmc_pwrseq: main-emmc-pwrseq-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */ + >; + }; + + pinctrl_i2c2: main-i2c2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL */ + AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + pinctrl_i2c3: main-i2c3-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */ + AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */ + >; + }; + + pinctrl_mdio1: main-mdio1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */ + AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */ + >; + }; + + pinctrl_mmc2: main-mmc2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0120, PIN_INPUT_PULLUP, 0) /* (K24) MMC2_CMD */ + AM62PX_IOPAD(0x0118, PIN_INPUT_PULLDOWN, 0) /* (K21) MMC2_CLK */ + AM62PX_IOPAD(0x011c, PIN_INPUT_PULLUP, 0) /* () MMC2_CLKLB */ + AM62PX_IOPAD(0x0114, PIN_INPUT_PULLUP, 0) /* (K23) MMC2_DAT0 */ + AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */ + AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */ + AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */ + >; + }; + + pinctrl_rgmii1: main-rgmii1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */ + AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */ + AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */ + AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */ + AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */ + AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */ + AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */ + AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */ + AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */ + AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */ + AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */ + AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */ + >; + bootph-all; + }; + + pinctrl_spi0: main-spi0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (B21) SPI0_CLK */ + AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (D20) SPI0_CS0 */ + AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */ + AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */ + >; + }; + + pinctrl_uart5: main-uart5-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00ec, PIN_INPUT, 4) /* (AC21) VOUT0_DATA13.UART5_CTSn */ + AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AD21) VOUT0_DATA12.UART5_RTSn */ + AM62PX_IOPAD(0x00d0, PIN_INPUT, 4) /* (AC23) VOUT0_DATA6.UART5_RXD */ + AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AE23) VOUT0_DATA7.UART5_TXD */ + >; + }; + + pinctrl_bt: main-btgrp-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 (BT_EN) */ + >; + }; + + pinctrl_restouch: main-restouch-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (Y23) VOUT0_DATA3.GPIO0_48 */ + >; + }; + + pinctrl_wifi: main-wifi-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (AC22) VOUT0_DATA9.GPIO0_54 - WIFI_PWR_EN - */ + AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 - WIFI_EN - */ + >; + }; +}; + +&mcu_pmx0 { + pinctrl_wkup_clkout0: wkup-clkout0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */ + >; + }; +}; + +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + ti,pindir-d0-out-d1-in; + status = "okay"; +}; + +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&sdhci0 { + /* On-module eMMC */ + ti,driver-strength-ohm = <50>; + mmc-pwrseq = <&mmc_pwrseq>; + bootph-all; + status = "okay"; +}; + +&sdhci2 { + /* On-module WiFi */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc2>, <&pinctrl_wifi>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + ti,fails-without-test-cd; + status = "okay"; +}; + +&usbss0 { + ti,vbus-divider; +}; + +&usbss1 { + ti,vbus-divider; +}; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mcu_r5fss0 { + status = "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&wkup_r5fss0 { + status = "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_r5_0>; + memory-region = <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ +&mcu_gpio0 { + status = "reserved"; +}; + +&mcu_gpio_intr { + status = "reserved"; +}; + +&wkup_rtc0 { + status = "disabled"; +}; + +&wkup_rti0 { + /* WKUP RTI0 is used by DM firmware */ + status = "reserved"; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; +}; From e402a3f1d9681d4b0be4568b5f318b3c3bc804bf Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Tue, 9 Sep 2025 23:37:41 +0200 Subject: [PATCH 759/931] arm64: dts: ti: var-som-am62p: Add support for Variscite Symphony Board Add device tree support for the Variscite Symphony carrier board with the VAR-SOM-AM62P system on module. The Symphony board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart interfaces - OV5640 Camera support - GPIO Expander - CAN, I2C and general purpose interfaces Link: https://www.variscite.it/product/single-board-computers/symphony-board/ Signed-off-by: Stefano Radaelli Reviewed-by: Judith Mendez Link: https://patch.msgid.link/20250909213749.28098-4-stefano.radaelli21@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 1 + .../dts/ti/k3-am62p5-var-som-symphony.dts | 500 ++++++++++++++++++ 2 files changed, 501 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 72f8755a0f30..82ce5deb2f58 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -39,6 +39,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62d2-evm.dtb # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-var-som-symphony.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-ivy.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts new file mode 100644 index 000000000000..4bb92fde6ab8 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts @@ -0,0 +1,500 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Variscite Symphony carrier board for VAR-SOM-AM62P + * + * Link: https://www.variscite.it/product/single-board-computers/symphony-board/ + * + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "k3-am62p5-var-som.dtsi" + +/ { + model = "Variscite VAR-SOM-AM62P on Symphony-Board"; + compatible = "variscite,var-som-am62p-symphony", "variscite,var-som-am62p", "ti,am62p5"; + + aliases { + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + serial0 = &main_uart0; + serial2 = &main_uart2; + serial5 = &main_uart5; + serial6 = &main_uart6; + spi5 = &main_spi2; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clk_ov5640_fixed: clock-24000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-back { + label = "Back"; + linux,code = ; + gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; + }; + + button-home { + label = "Home"; + linux,code = ; + gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; + }; + + button-menu { + label = "Menu"; + linux,code = ; + gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-heartbeat { + label = "Heartbeat"; + linux,default-trigger = "heartbeat"; + gpios = <&pca9534 0 GPIO_ACTIVE_LOW>; + }; + }; + + reg_2p8v: regulator-2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <®_3v3>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_3v3>; + regulator-always-on; + }; + + reg_1p5v: regulator-1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + vin-supply = <®_3v3>; + regulator-always-on; + }; + + reg_sdhc1_vmmc: regulator-sdhc1 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_SD"; + vin-supply = <®_sdhc1_vmmc_int>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + reg_sdhc1_vmmc_int: regulator-sdhc1-int { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_SD_INT"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_vmmc>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&main_gpio0 53 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc { + compatible = "regulator-gpio"; + regulator-name = "+V3.3_SD_VQMMC"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_vqmmc>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpios = <&main_gpio0 56 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + bootph-all; + }; + + reg_ov5640_buf_en: regulator-camera-buf-en { + compatible = "regulator-fixed"; + regulator-name = "ov5640_buf_en"; + gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + }; + + transceiver1: can-phy { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_extcon>; + label = "USB-C"; + id-gpios = <&main_gpio1 12 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + usb_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>, + <&pinctrl_rgmii2>; + status = "okay"; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio1>; + status = "okay"; + + cpsw3g_phy1: ethernet-phy@5 { + compatible = "ethernet-phy-id0283.bc30"; + reg = <5>; + reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + }; +}; + +&cpsw_port2 { + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the Symphony PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <&cpsw3g_phy1>; + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&main_i2c0{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clock-frequency = <400000>; + status = "okay"; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p5v>; + powerdown-gpios = <&main_gpio0 10 GPIO_ACTIVE_HIGH>; + reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; + + /* GPIO expander */ + pca9534: gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + gpio-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9534>; + interrupt-parent = <&main_gpio1>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + #gpio-cells = <2>; + status = "okay"; + + usb3-sel-hog { + gpio-hog; + gpios = <4 0>; + output-low; + line-name = "usb3_sel"; + }; + + eth-som-vselect-hog { + gpio-hog; + gpios = <6 0>; + output-low; + line-name = "eth-vselect"; + }; + + eth-mdio-enable-hog { + gpio-hog; + gpios = <7 0>; + output-high; + line-name = "eth-mdio-enable"; + }; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcan0>; + phys = <&transceiver1>; + status = "okay"; +}; + +&main_pmx0 { + pinctrl_extcon: main-extcon-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01a8, PIN_INPUT, 7) /* (F25) MCASP0_AFSX.GPIO1_12 */ + >; + }; + + pinctrl_i2c0: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */ + AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */ + >; + }; + + pinctrl_i2c1: main-i2c1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */ + AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */ + >; + bootph-all; + }; + + pinctrl_mcan0: main-mcan0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01dc, PIN_INPUT, 0) /* (F20) MCAN0_RX */ + AM62PX_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (B23) MCAN0_TX */ + >; + }; + + pinctrl_mmc1: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */ + AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */ + AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */ + AM62PX_IOPAD(0x022c, PIN_INPUT, 0) /* (H23) MMC1_DAT1 */ + AM62PX_IOPAD(0x0228, PIN_INPUT, 0) /* (H22) MMC1_DAT2 */ + AM62PX_IOPAD(0x0224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */ + AM62PX_IOPAD(0x0240, PIN_INPUT, 0) /* (D23) MMC1_SDCD */ + >; + bootph-all; + }; + + pinctrl_rgmii2: main-rgmii2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */ + AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */ + AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */ + AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */ + AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */ + AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */ + AM62PX_IOPAD(0x016c, PIN_INPUT, 0) /* (B19) RGMII2_TD0 */ + AM62PX_IOPAD(0x0170, PIN_INPUT, 0) /* (A21) RGMII2_TD1 */ + AM62PX_IOPAD(0x0174, PIN_INPUT, 0) /* (D17) RGMII2_TD2 */ + AM62PX_IOPAD(0x0178, PIN_INPUT, 0) /* (A19) RGMII2_TD3 */ + AM62PX_IOPAD(0x0168, PIN_INPUT_PULLDOWN, 0) /* (D16) RGMII2_TXC */ + AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX_CTL */ + >; + }; + + pinctrl_spi2: main-spi2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01b0, PIN_INPUT, 1) /* (G20) MCASP0_ACLKR.SPI2_CLK */ + AM62PX_IOPAD(0x0194, PIN_OUTPUT, 1) /* (D25) MCASP0_AXR3.SPI2_D0 */ + AM62PX_IOPAD(0x0198, PIN_INPUT, 1) /* (E25) MCASP0_AXR2.SPI2_D1 */ + AM62PX_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (G23) MCASP0_AFSR.GPIO1_13 */ + >; + }; + + pinctrl_uart0: main-uart0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ + >; + bootph-all; + }; + + pinctrl_uart2: main-uart2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x005c, PIN_INPUT_PULLUP, 2) /* (AC25) GPMC0_AD8.UART2_RXD */ + AM62PX_IOPAD(0x0060, PIN_OUTPUT, 2) /* (AB25) GPMC0_AD9.UART2_TXD */ + >; + }; + + pinctrl_uart6: main-uart6-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x009c, PIN_INPUT_PULLUP, 3) /* (AD24) GPMC0_WAIT1.UART6_RXD */ + AM62PX_IOPAD(0x0244, PIN_OUTPUT, 1) /* (D24) MMC1_SDWP.UART6_TXD */ + >; + }; + + pinctrl_usb1: main-usb1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (G21) USB1_DRVVBUS */ + >; + }; + + pinctrl_ov5640: main-ov5640-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0028, PIN_OUTPUT, 7) /* (N20) OSPI0_D7.GPIO0_10 */ + AM62PX_IOPAD(0x0054, PIN_OUTPUT, 7) /* (V24) GPMC0_AD6.GPIO0_21 */ + AM62PX_IOPAD(0x0058, PIN_OUTPUT, 7) /* (W25) GPMC0_AD7.GPIO0_22 */ + >; + }; + + pinctrl_pca9534: main-pca9534-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01f0, PIN_INPUT, 7) /* (C25) EXT_REFCLK1.GPIO1_30 */ + >; + }; + + pinctrl_sd1_vmmc: main-sd1-vmmc-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AC24) GPMC0_AD15.GPIO0_30 */ + AM62PX_IOPAD(0x00d8, PIN_OUTPUT, 7) /* (AE22) VOUT0_DATA8.GPIO0_53 */ + >; + bootph-all; + }; + + pinctrl_sd1_vqmmc: main-sd1-vqmmc-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00e4, PIN_OUTPUT, 7) /* (AE21) VOUT0_DATA11.GPIO0_56 */ + >; + bootph-all; + }; +}; + +&main_spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + ti,pindir-d0-out-d1-in; + cs-gpios = <&main_gpio1 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&main_uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&main_uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&sdhci1 { + /* SD Card */ + vmmc-supply = <®_sdhc1_vmmc>; + vqmmc-supply = <®_sdhc1_vqmmc>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1>; + disable-wp; + bootph-all; + status="okay"; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&usb0 { + usb-role-switch; + status = "okay"; + + port { + typec_hs: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + status = "okay"; +}; + +&usbss0 { + status = "okay"; +}; + +&usbss1 { + status = "okay"; +}; From e53fbf955ea7753ef7970b866ca229abe32d5639 Mon Sep 17 00:00:00 2001 From: Garrett Giordano Date: Wed, 10 Sep 2025 16:17:16 +0200 Subject: [PATCH 760/931] arm64: dts: ti: k3-am642-phyboard-electra: Add PEB-C-010 Overlay The PEB-C-010 expansion board adds two extra 1Gbps ethernet ports to the phyBOARD-Electra-AM64x. Signed-off-by: Garrett Giordano Signed-off-by: Wadim Egorov Link: https://patch.msgid.link/20250910141716.2133707-1-w.egorov@phytec.de Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 3 + .../k3-am642-phyboard-electra-peb-c-010.dtso | 158 ++++++++++++++++++ 2 files changed, 161 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 82ce5deb2f58..28642ef98a32 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-gpio-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-pcie-usb2.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-peb-c-010.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo @@ -208,6 +209,8 @@ k3-am642-phyboard-electra-pcie-usb2-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-pcie-usb2.dtbo k3-am642-phyboard-electra-x27-gpio1-spi1-uart3-dtbs := \ k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtbo +k3-am642-phyboard-electra-peb-c-010-dtbs := \ + k3-am642-phyboard-electra-rdk.dtb k3-am642-phyboard-electra-peb-c-010.dtbo k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso new file mode 100644 index 000000000000..7fc73cfacadb --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2025 PHYTEC America LLC + * Author: Garrett Giordano + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet3 = "/icssg1-ethernet/ethernet-ports/port@0"; + ethernet4 = "/icssg1-ethernet/ethernet-ports/port@1"; + }; + + icssg1-ethernet { + compatible = "ti,am642-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_rgmii1_pins_default>, <&icssg1_rgmii2_pins_default>; + + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>, /* ingress slice 1 */ + <&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */ + <&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1", + "rxmgm0", "rxmgm1"; + + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + interrupt-parent = <&icssg1_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + sram = <&oc_sram>; + + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; + ti,mii-g-rt = <&icssg1_mii_g_rt>; + ti,mii-rt = <&icssg1_mii_rt>; + ti,pa-stats = <&icssg1_pa_stats>; + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + icssg1_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg1_phy1>; + phy-mode = "rgmii-id"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + ti,syscon-rgmii-delay = <&main_conf 0x4110>; + }; + + icssg1_emac1: port@1 { + reg = <1>; + phy-handle = <&icssg1_phy2>; + phy-mode = "rgmii-id"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + ti,syscon-rgmii-delay = <&main_conf 0x4114>; + }; + }; + }; +}; + +&main_pmx0 { + icssg1_mdio_pins_default: icssg1-mdio-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ + >; + }; + + icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ + AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ + AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ + AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ + AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + >; + }; + + icssg1_rgmii2_pins_default: icssg1-rgmii2-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x0108, PIN_INPUT, 2) /* (W11) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) /* (V11) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) /* (AA12) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) /* (Y12) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) /* (W12) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) /* (U11) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) /* (AA10) PRG1_PRU1_GPO11.PRG1_RGMII2_TD0 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) /* (V10) PRG1_PRU1_GPO12.PRG1_RGMII2_TD1 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) /* (U10) PRG1_PRU1_GPO13.PRG1_RGMII2_TD2 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) /* (AA11) PRG1_PRU1_GPO14.PRG1_RGMII2_TD3 */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) /* (Y11) PRG1_PRU1_GPO15.PRG1_RGMII2_TX_CTL */ + AM64X_IOPAD(0x0148, PIN_INPUT, 2) /* (Y10) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */ + >; + }; +}; + +&icssg1_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_mdio_pins_default>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + icssg1_phy1: ethernet-phy@1 { + reg = <0x1>; + rx-fifo-depth = ; + tx-fifo-depth = ; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; + ti,clk-output-sel = ; + ti,min-output-impedance; + }; + + icssg1_phy2: ethernet-phy@2 { + reg = <0x2>; + rx-fifo-depth = ; + tx-fifo-depth = ; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; + ti,clk-output-sel = ; + ti,min-output-impedance; + }; +}; From fcfedcb6804caaf18f22016de16d93bf18bbcfdd Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Fri, 12 Sep 2025 11:50:14 +0530 Subject: [PATCH 761/931] arm64: dts: ti: k3-j721s2-evm: Add overlay to enable USB0 Type-A The J721S2-EVM (J721S2-SOM mounted on the J7 Common Processor Board) has a single instance of USB namely USB0. On the board, USB0 can be enabled using a single USB interface at a time among the following: 1. USB3.1 Gen1 Type C interface 2. Two USB2.0 Type A interfaces via an on-board USB Hub By default, USB0 is enabled using the USB3.1 Gen1 Type C interface. Hence, add a device-tree overlay to allow using USB0 with the USB2.0 Type A interfaces by configuring the "USB2.0_MUX_SEL" mux. Also, since the Type A interfaces only connect to USB Devices with USB0 acting as the USB Host, set the Dual-Role mode for USB0 to Host. Signed-off-by: Siddharth Vadapalli Link: https://patch.msgid.link/20250912062021.2906034-1-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 4 +++ .../dts/ti/k3-j721s2-evm-usb0-type-a.dtso | 28 +++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-usb0-type-a.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 28642ef98a32..743115b849a7 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -134,6 +134,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo k3-j721s2-evm-dtbs := k3-j721s2-common-proc-board.dtb k3-j721s2-evm-gesi-exp-board.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-usb0-type-a.dtbo # Boards with J722s SoC dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai.dtb @@ -235,6 +236,8 @@ k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo +k3-j721s2-evm-usb0-type-a-dtbs := k3-j721s2-common-proc-board.dtb \ + k3-j721s2-evm-usb0-type-a.dtbo k3-j722s-evm-csi2-quad-rpi-cam-imx219-dtbs := k3-j722s-evm.dtb \ k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo k3-j722s-evm-csi2-quad-tevi-ov5640-dtbs := k3-j722s-evm.dtb \ @@ -277,6 +280,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-j721e-evm-pcie1-ep.dtb \ k3-j721e-sk-csi2-dual-imx219.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ + k3-j721s2-evm-usb0-type-a.dtb \ k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtb \ k3-j722s-evm-csi2-quad-tevi-ov5640.dtb \ k3-j742s2-evm-usb0-type-a.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-usb0-type-a.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-usb0-type-a.dtso new file mode 100644 index 000000000000..fe4a23efe708 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-usb0-type-a.dtso @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for enabling USB0 instance of USB in the Host Mode of operation + * with the Type-A Connector on the J7 common processor board. + * + * J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include + +&exp_som { + p0-hog { + /* P0 - USB2.0_MUX_SEL */ + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "USB2.0_MUX_SEL"; + }; +}; + +&usb0 { + dr_mode = "host"; +}; From 4d7624fc85a27240ce35e0acc624dd165a314fca Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 20 Aug 2025 21:06:57 +0100 Subject: [PATCH 762/931] arm64: dts: renesas: rzt2h-rzn2h-evk: Enable eMMC Enable eMMC on RZ/T2H and RZ/N2H EVKs. As SDHI0 can be connected to either eMMC0/SD0 `SD0_EMMC` macro is added. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250820200659.2048755-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 9 +++ .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 10 +++ .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 62 +++++++++++++++++++ 3 files changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index a7b91c96f311..cb659b2a4337 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -8,6 +8,15 @@ /dts-v1/; #include "r9a09g077m44.dtsi" + +/* + * SD0 can be connected to either eMMC (IC49) or SD card slot CN31 + * Lets by default enable the eMMC, note we need the below SW settings + * for eMMC. + * SW2[1] = ON; SW2[2] = ON + */ +#define SD0_EMMC 1 + #include "rzt2h-n2h-evk-common.dtsi" / { diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index a068661fc442..87e362f6f09f 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -8,6 +8,16 @@ /dts-v1/; #include "r9a09g087m44.dtsi" + +/* + * SD0 can be connected to either eMMC (U33) or SD card slot CN21 + * Lets by default enable the eMMC, note we need the below SW settings + * for eMMC. + * DSW5[1] = ON; DSW5[2] = ON + * DSW17[5] = OFF; DSW17[6] = ON + */ +#define SD0_EMMC 1 + #include "rzt2h-n2h-evk-common.dtsi" /* diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 1b7e16ffe6b6..68d493bf5e8c 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -13,12 +13,31 @@ / { aliases { i2c0 = &i2c0; i2c1 = &i2c1; + mmc0 = &sdhi0; serial0 = &sci0; }; chosen { stdout-path = "serial0:115200n8"; }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &extal_clk { @@ -46,6 +65,34 @@ sci0_pins: sci0-pins { pinmux = , ; }; + +#if SD0_EMMC + sdhi0-emmc-iovs-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "SD0_IOVS"; + }; +#endif + + sdhi0_emmc_pins: sd0-emmc-group { + data-pins { + pinmux = , /* SD0_DATA0 */ + , /* SD0_DATA1 */ + , /* SD0_DATA2 */ + , /* SD0_DATA3 */ + , /* SD0_DATA4 */ + , /* SD0_DATA5 */ + , /* SD0_DATA6 */ + ; /* SD0_DATA7 */ + }; + + ctrl-pins { + pinmux = , /* SD0_CLK */ + , /* SD0_CMD */ + ; /* SD0_RST# */ + }; + }; }; &sci0 { @@ -53,3 +100,18 @@ &sci0 { pinctrl-names = "default"; status = "okay"; }; + +#if SD0_EMMC +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + non-removable; + mmc-hs200-1_8v; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; +#endif From dba8ee27c5de15c3c347816bb189af939092aea9 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 20 Aug 2025 21:06:58 +0100 Subject: [PATCH 763/931] arm64: dts: renesas: rzt2h-rzn2h-evk: Enable MicroSD card slot Enable MicroSD card slot which is connected to SDHI1 on the RZ/T2H and RZ/N2H EVKs. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250820200659.2048755-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 9 ++++ .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 6 +++ .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 51 +++++++++++++++++++ 3 files changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index cb659b2a4337..37330c837f64 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -17,6 +17,13 @@ */ #define SD0_EMMC 1 +/* + * P17_4 = SD1_CD; SW2[3] = ON + * P08_5 = SD1_PWEN; SW2[3] = ON + * P08_6 = SD1_IOVS; SW2[3] = ON; SW5[3] = OFF; SW5[4] = ON + */ +#define SD1_MICRO_SD 1 + #include "rzt2h-n2h-evk-common.dtsi" / { @@ -49,6 +56,7 @@ led-2 { function-enumerator = <2>; }; +#if (!SD1_MICRO_SD) led-3 { /* SW2-3: OFF */ gpios = <&pinctrl RZT2H_GPIO(8, 5) GPIO_ACTIVE_HIGH>; @@ -56,6 +64,7 @@ led-3 { function = LED_FUNCTION_DEBUG; function-enumerator = <3>; }; +#endif led-4 { /* SW8-3: ON, SW8-4: OFF */ diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index 87e362f6f09f..87178933bee8 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -18,6 +18,12 @@ */ #define SD0_EMMC 1 +/* + * P17_4 = SD1_CD; DSW5[3] = ON; DSW19[1] = OFF; DSW19[2] = ON + * P08_6 = SD1_IOVS; DSW5[3] = ON + */ +#define SD1_MICRO_SD 1 + #include "rzt2h-n2h-evk-common.dtsi" /* diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 68d493bf5e8c..34572630ecbe 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -14,6 +14,7 @@ aliases { i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhi0; + mmc1 = &sdhi1; serial0 = &sci0; }; @@ -38,6 +39,18 @@ reg_3p3v: regulator-3p3v { regulator-boot-on; regulator-always-on; }; + +#if SD1_MICRO_SD + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZT2H_GPIO(8, 6) GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <3300000 0>, <1800000 1>; + }; +#endif }; &extal_clk { @@ -93,6 +106,30 @@ ctrl-pins { ; /* SD0_RST# */ }; }; + +#if SD1_MICRO_SD + sdhi1-pwen-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "SD1_PWEN"; + }; +#endif + + sdhi1_pins: sd1-group { + data-pins { + pinmux = , /* SD1_DATA0 */ + , /* SD1_DATA1 */ + , /* SD1_DATA2 */ + ; /* SD1_DATA3 */ + }; + + ctrl-pins { + pinmux = , /* SD1_CLK */ + , /* SD1_CMD */ + ; /* SD1_CD */ + }; + }; }; &sci0 { @@ -115,3 +152,17 @@ &sdhi0 { status = "okay"; }; #endif + +#if SD1_MICRO_SD +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi1>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; +#endif From d065453e5ee097193e3da3f7a8aafcdfabbaf78f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 20 Aug 2025 21:06:59 +0100 Subject: [PATCH 764/931] arm64: dts: renesas: rzt2h-rzn2h-evk: Enable SD card slot Enable SD card slot which is connected to SDHI0 on the RZ/T2H and RZ/N2H EVKs. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250820200659.2048755-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 5 ++ .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 9 ++++ .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 51 +++++++++++++++++++ 3 files changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 37330c837f64..264f7ddb8cc5 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -14,8 +14,13 @@ * Lets by default enable the eMMC, note we need the below SW settings * for eMMC. * SW2[1] = ON; SW2[2] = ON + * + * To enable SD card and disable eMMC on SDHI0 disable the below macro + * and set the below switch setting: + * SW2[1] = OFF; SW2[2] = ON */ #define SD0_EMMC 1 +#define SD0_SD (!SD0_EMMC) /* * P17_4 = SD1_CD; SW2[3] = ON diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index 87178933bee8..80f358fb2d74 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -15,8 +15,17 @@ * for eMMC. * DSW5[1] = ON; DSW5[2] = ON * DSW17[5] = OFF; DSW17[6] = ON + * + * To enable SD card and disable eMMC on SDHI0 disable the below macro + * and set the below switch setting: + * DSW5[1] = OFF; DSW5[2] = ON + * P22_6 = SD0_WP; DSW15[1] = OFF; DSW15[2] = ON + * P22_5 = SD0_CD; DSW15[3] = OFF; DSW15[4] = ON + * P02_6 = SD0_IOVS; DSW17[5] = OFF; DSW17[6] = ON + * P02_5 = SD0_PWEN; DSW17[7] = OFF; DSW17[8] = ON */ #define SD0_EMMC 1 +#define SD0_SD (!SD0_EMMC) /* * P17_4 = SD1_CD; DSW5[3] = ON; DSW19[1] = OFF; DSW19[2] = ON diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 34572630ecbe..8b9d04dce8ae 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -40,6 +40,18 @@ reg_3p3v: regulator-3p3v { regulator-always-on; }; +#if SD0_SD + vqmmc_sdhi0: regulator-vqmmc-sdhi0 { + compatible = "regulator-gpio"; + regulator-name = "SDHI0 VqmmC"; + gpios = <&pinctrl RZT2H_GPIO(2, 6) GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios-states = <0>; + states = <3300000 0>, <1800000 1>; + }; +#endif + #if SD1_MICRO_SD vccq_sdhi1: regulator-vccq-sdhi1 { compatible = "regulator-gpio"; @@ -107,6 +119,31 @@ ctrl-pins { }; }; +#if SD0_SD + sdhi0-pwen-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "SD0_PWEN"; + }; +#endif + + sdhi0_sd_pins: sd0-sd-group { + data-pins { + pinmux = , /* SD0_DATA0 */ + , /* SD0_DATA1 */ + , /* SD0_DATA2 */ + ; /* SD0_DATA3 */ + }; + + ctrl-pins { + pinmux = , /* SD0_CLK */ + , /* SD0_CMD */ + , /* SD0_CD */ + ; /* SD0_WP */ + }; + }; + #if SD1_MICRO_SD sdhi1-pwen-hog { gpio-hog; @@ -153,6 +190,20 @@ &sdhi0 { }; #endif +#if SD0_SD +&sdhi0 { + pinctrl-0 = <&sdhi0_sd_pins>; + pinctrl-1 = <&sdhi0_sd_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vqmmc_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; +#endif + #if SD1_MICRO_SD &sdhi1 { pinctrl-0 = <&sdhi1_pins>; From 19adb35f9dccd16df111f2d0ec265d572f8bb3f5 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 21 Aug 2025 17:19:41 +0100 Subject: [PATCH 765/931] arm64: dts: renesas: r9a09g077: Add WDT nodes Add WDT0-5 nodes to RZ/T2H (R9A09G077) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250821161946.1096033-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 0929ce2db05c..5291ea9fc326 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -160,6 +160,66 @@ sci5: serial@81005000 { status = "disabled"; }; + wdt0: watchdog@80082000 { + compatible = "renesas,r9a09g077-wdt"; + reg = <0 0x80082000 0 0x400>, + <0 0x81295100 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt1: watchdog@80082400 { + compatible = "renesas,r9a09g077-wdt"; + reg = <0 0x80082400 0 0x400>, + <0 0x81295104 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt2: watchdog@80082800 { + compatible = "renesas,r9a09g077-wdt"; + reg = <0 0x80082800 0 0x400>, + <0 0x81295108 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt3: watchdog@80082c00 { + compatible = "renesas,r9a09g077-wdt"; + reg = <0 0x80082c00 0 0x400>, + <0 0x8129510c 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt4: watchdog@80083000 { + compatible = "renesas,r9a09g077-wdt"; + reg = <0 0x80083000 0 0x400>, + <0 0x81295110 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt5: watchdog@80083400 { + compatible = "renesas,r9a09g077-wdt"; + reg = <0 0x80083400 0 0x400>, + <0 0x81295114 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + i2c0: i2c@80088000 { compatible = "renesas,riic-r9a09g077"; reg = <0 0x80088000 0 0x400>; From 283b465626a0fd2404a65de76a3485f09ccb32f0 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 21 Aug 2025 17:19:42 +0100 Subject: [PATCH 766/931] arm64: dts: renesas: r9a09g087: Add WDT nodes Add WDT0-5 nodes to RZ/N2H (R9A09G087) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250821161946.1096033-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index ecbb7b93aed2..b669c1a506d3 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -160,6 +160,66 @@ sci5: serial@81005000 { status = "disabled"; }; + wdt0: watchdog@80082000 { + compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; + reg = <0 0x80082000 0 0x400>, + <0 0x81295100 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt1: watchdog@80082400 { + compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; + reg = <0 0x80082400 0 0x400>, + <0 0x81295104 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt2: watchdog@80082800 { + compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; + reg = <0 0x80082800 0 0x400>, + <0 0x81295108 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt3: watchdog@80082c00 { + compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; + reg = <0 0x80082c00 0 0x400>, + <0 0x8129510c 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt4: watchdog@80083000 { + compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; + reg = <0 0x80083000 0 0x400>, + <0 0x81295110 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt5: watchdog@80083400 { + compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; + reg = <0 0x80083400 0 0x400>, + <0 0x81295114 0 0x04>; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; + clock-names = "pclk"; + power-domains = <&cpg>; + status = "disabled"; + }; + i2c0: i2c@80088000 { compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; reg = <0 0x80088000 0 0x400>; From da23f1bdce81712096601d9e5e59cfe071aa1c92 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 21 Aug 2025 17:19:43 +0100 Subject: [PATCH 767/931] arm64: dts: renesas: rzt2h-n2h-evk-common: Enable WDT2 Enable watchdog (WDT2) on RZ/T2H and RZ/N2H EVKs. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250821161946.1096033-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 8b9d04dce8ae..91068042bec0 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -217,3 +217,8 @@ &sdhi1 { status = "okay"; }; #endif + +&wdt2 { + status = "okay"; + timeout-sec = <60>; +}; From a777631037d0f5e55d50e59e5f2179381eb91fbb Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 21 Aug 2025 17:19:44 +0100 Subject: [PATCH 768/931] arm64: dts: renesas: r9a09g077: Add USB2.0 support Add EHCI, OHCI, PHY and HSUSB nodes to RZ/T2H (R9A09G077) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250821161946.1096033-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 5291ea9fc326..7f1aca218c9f 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -299,6 +299,53 @@ gic: interrupt-controller@83000000 { interrupts = ; }; + ohci: usb@92040000 { + compatible = "generic-ohci"; + reg = <0 0x92040000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + phys = <&usb2_phy 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci: usb@92040100 { + compatible = "generic-ehci"; + reg = <0 0x92040100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + phys = <&usb2_phy 2>; + phy-names = "usb"; + companion = <&ohci>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy: usb-phy@92040200 { + compatible = "renesas,usb2-phy-r9a09g077"; + reg = <0 0x92040200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>, + <&cpg CPG_CORE R9A09G077_USB_CLK>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + hsusb: usb@92041000 { + compatible = "renesas,usbhs-r9a09g077"; + reg = <0 0x92041000 0 0x1000>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 408>; + phys = <&usb2_phy 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + sdhi0: mmc@92080000 { compatible = "renesas,sdhi-r9a09g077", "renesas,sdhi-r9a09g057"; From 00998e5fe0d85798b7d1f30d2ddfd9990cf5d7ef Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 21 Aug 2025 17:19:45 +0100 Subject: [PATCH 769/931] arm64: dts: renesas: r9a09g087: Add USB2.0 support Add EHCI, OHCI, PHY and HSUSB nodes to RZ/N2H (R9A09G087) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250821161946.1096033-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index b669c1a506d3..f06c19c73adb 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -299,6 +299,53 @@ gic: interrupt-controller@83000000 { interrupts = ; }; + ohci: usb@92040000 { + compatible = "generic-ohci"; + reg = <0 0x92040000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + phys = <&usb2_phy 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci: usb@92040100 { + compatible = "generic-ehci"; + reg = <0 0x92040100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + phys = <&usb2_phy 2>; + phy-names = "usb"; + companion = <&ohci>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy: usb-phy@92040200 { + compatible = "renesas,usb2-phy-r9a09g087", "renesas,usb2-phy-r9a09g077"; + reg = <0 0x92040200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>, + <&cpg CPG_CORE R9A09G087_USB_CLK>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + hsusb: usb@92041000 { + compatible = "renesas,usbhs-r9a09g087", "renesas,usbhs-r9a09g077"; + reg = <0 0x92041000 0 0x1000>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 408>; + phys = <&usb2_phy 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + sdhi0: mmc@92080000 { compatible = "renesas,sdhi-r9a09g087", "renesas,sdhi-r9a09g057"; From da7326322d31eb60fea27be30ca013d1e9b0a86c Mon Sep 17 00:00:00 2001 From: John Madieu Date: Thu, 14 Aug 2025 17:34:55 +0200 Subject: [PATCH 770/931] arm64: dts: renesas: r9a09g047: Enable Tx coe support The GBETH IPs found on RZ/G3E SoC family are compatible with the stmmac driver. They have a MAC HW feature register used by this driver to enable respective features. While the register advertises Tx coe support, it was not enabled by the driver due to the 'snps,force_thresh_dma_mode' dtsi property. Switch from 'snps,force_thresh_dma_mode' to 'snps,force_sf_dma_mode' to enable Tx checksum offload support on both GBETH IPs. While at it, also switch from 'snps,fixed-burst' to 'snps,mixed-burst' and remove 'snps,no-pbl-x8' for optimal DMA configuration. This improvement results in a measurable TCP Tx performance gain, increasing throughput by 20Mbps. Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250814153456.268208-1-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index e5b24e46d645..47d843c79021 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -927,9 +927,8 @@ eth0: ethernet@15c30000 { snps,perfect-filter-entries = <128>; rx-fifo-depth = <8192>; tx-fifo-depth = <8192>; - snps,fixed-burst; - snps,no-pbl-x8; - snps,force_thresh_dma_mode; + snps,mixed-burst; + snps,force_sf_dma_mode; snps,axi-config = <&stmmac_axi_setup>; snps,mtl-rx-config = <&mtl_rx_setup0>; snps,mtl-tx-config = <&mtl_tx_setup0>; @@ -1028,9 +1027,8 @@ eth1: ethernet@15c40000 { snps,perfect-filter-entries = <128>; rx-fifo-depth = <8192>; tx-fifo-depth = <8192>; - snps,fixed-burst; - snps,no-pbl-x8; - snps,force_thresh_dma_mode; + snps,mixed-burst; + snps,force_sf_dma_mode; snps,axi-config = <&stmmac_axi_setup>; snps,mtl-rx-config = <&mtl_rx_setup1>; snps,mtl-tx-config = <&mtl_tx_setup1>; From 3e5df910b592d47734b6dcd03d57498d4766bf6c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 17 Aug 2025 15:51:30 +0100 Subject: [PATCH 771/931] arm64: dts: renesas: r9a09g047e57-smarc: Fix gpio key's pin control node Adding pin control node to the child won't parse the pins during driver bind. Fix the issue by moving it to parent node. This issue is observed while adding Schmitt input enable for PS0 pin on later patch. Currently the reset value of the PIN is set to NMI function and hence there is no breakage. Fixes: 9e95446b0cf9 ("arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys") Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250817145135.166591-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 1e67f0a2a945..9f6716fa1086 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -90,10 +90,10 @@ &i2c0 { }; &keys { - key-sleep { - pinctrl-0 = <&nmi_pins>; - pinctrl-names = "default"; + pinctrl-0 = <&nmi_pins>; + pinctrl-names = "default"; + key-sleep { interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>; linux,code = ; label = "SLEEP"; From 4b9e0d8aa96c92be0073825344b661afc49242aa Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 17 Aug 2025 15:51:31 +0100 Subject: [PATCH 772/931] arm64: dts: renesas: r9a09g047e57-smarc: Use Schmitt input for NMI function The latest RZ/G3E pin control document (rev 1.2) recommends using Schmitt input when PS0 pin used as NMI function. Enable Schmitt input for PS0 pin. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250817145135.166591-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 9f6716fa1086..08e814c03fa8 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -132,6 +132,7 @@ i2c0_pins: i2c0 { nmi_pins: nmi { pinmux = ; /* NMI */ + input-schmitt-enable; }; scif_pins: scif { From 7e7bac722ddbd2fc9ba5c5916929cdd2507b97af Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 4 Sep 2025 11:04:35 +0100 Subject: [PATCH 773/931] arm64: dts: renesas: rzt2h-n2h-evk: Enable USB2.0 support Enable USB2.0 support on RZ/T2H and RZ/N2H EVKs. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250904100435.4033858-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 36 ++++++++++++++++ .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 41 +++++++++++++++++++ .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 22 ++++++++++ 3 files changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 264f7ddb8cc5..2bf867273ad0 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -29,6 +29,28 @@ */ #define SD1_MICRO_SD 1 +/* + * USB Pin Configuration: + * + * This board is equipped with three USB connectors: Type-A (CN80), Mini-B + * (CN79), and Micro-AB (CN33). The RZ/T2H SoC has a single USB channel, so + * either the USB host interface or the USB function interface can be used, + * but not both simultaneously when using the CN79 and CN80 connectors. + * + * By default, the Type-A (CN80) and Mini-B (CN79) connectors are enabled. + * Configure the switches as follows: + * - P00_0 - P00_2 (control signals for USB power supply): SW1[5] = ON + * - USB_VBUSIN (used for USB function): SW7[7] = OFF; SW7[8] = ON + * - USB_VBUSEN (used for USB_HF_VBUSEN): SW7[9] = OFF; SW7[10] = ON + * + * To enable the Micro-AB (CN33) USB OTG connector, set the following macro + * to 1 and configure the switches as follows: + * - P00_0 - P00_2 (control signals for USB power supply): SW1[5] = ON + * - USB_VBUSIN (used for USB OTG): SW7[7] = ON; SW7[8] = OFF + * - USB_VBUSEN (used for USB_OTG_VBUSEN): SW7[9] = ON; SW7[10] = OFF + */ +#define USB_OTG 0 + #include "rzt2h-n2h-evk-common.dtsi" / { @@ -145,4 +167,18 @@ i2c1_pins: i2c1-pins { pinmux = , /* SDA */ ; /* SCL */ }; + +#if USB_OTG + usb-exicen-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "usb_exicen_a"; + }; +#endif + + usb_pins: usb-pins { + pinmux = , /* VBUSEN */ + ; /* OVRCUR */ + }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index 80f358fb2d74..084b3a0c8052 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -33,6 +33,33 @@ */ #define SD1_MICRO_SD 1 +/* + * USB Pin Configuration: + * + * This board is equipped with three USB connectors: Type-A (CN7), Mini-B + * (CN8), and Micro-AB (CN9). The RZ/N2H SoC has a single USB channel, so + * either the USB host interface or the USB function interface can be used, + * but not both simultaneously when using the CN7 and CN8 connectors. + * + * By default, the Type-A (CN7) and Mini-B (CN8) connectors are enabled. + * Configure the switches as follows: + * - P02_2 - P02_3 (control signals for USB power supply): DSW2[6] = OFF; + * - P02_2 (used for VBUSEN): DSW14[5] = OFF; DSW14[6] = ON + * - P02_3 (used for USB_OVRCUR): DSW14[1] = OFF; DSW14[2] = ON + * - USB_VBUSIN (used for VBUS of CN8): DSW16[1] = OFF; DSW16[2] = ON + * - USB_VBUSEN (used for USB_HF_VBUSEN): DSW16[3] = OFF; DSW16[4] = ON + * + * To enable the Micro-AB (CN9) USB OTG connector, set the following macro + * to 1 and configure the switches as follows: + * - P02_2 - P02_3 (control signals for USB power supply): DSW2[6] = OFF; + * - P02_2 (used for VBUSEN): DSW14[5] = OFF; DSW14[6] = ON + * - P02_3 (used for USB_OVRCUR): DSW14[1] = OFF; DSW14[2] = ON + * - USB_VBUSIN (used for VBUS for OTG): DSW16[1] = ON; DSW16[2] = OFF + * - USB_VBUSEN (used for USB_OTG_VBUSEN): DSW16[3] = ON; DSW16[4] = OFF + * - USB_EXICEN (used for USB OTG EXICEN): DSW14[3] = OFF; DSW14[4] = ON + */ +#define USB_OTG 0 + #include "rzt2h-n2h-evk-common.dtsi" /* @@ -185,4 +212,18 @@ i2c1_pins: i2c1-pins { pinmux = , ; }; + +#if USB_OTG + usb-exicen-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "usb_exicen_a"; + }; +#endif + + usb_pins: usb-pins { + pinmux = , /* VBUSEN */ + ; /* OVRCUR */ + }; }; diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 91068042bec0..5c91002c99c4 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -65,10 +65,20 @@ vccq_sdhi1: regulator-vccq-sdhi1 { #endif }; +&ehci { + dr_mode = "otg"; + status = "okay"; +}; + &extal_clk { clock-frequency = <25000000>; }; +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + &i2c0 { eeprom: eeprom@50 { compatible = "renesas,r1ex24016", "atmel,24c16"; @@ -77,6 +87,11 @@ eeprom: eeprom@50 { }; }; +&ohci { + dr_mode = "otg"; + status = "okay"; +}; + &pinctrl { /* * SCI0 Pin Configuration: @@ -218,6 +233,13 @@ &sdhi1 { }; #endif +&usb2_phy { + pinctrl-0 = <&usb_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &wdt2 { status = "okay"; timeout-sec = <60>; From 21fd8f45bad1c82c5fc94b372e47ad481bbad99b Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 4 Sep 2025 17:59:08 +0100 Subject: [PATCH 774/931] arm64: dts: renesas: r9a09g057: Add I3C node Add I3C node to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250904165909.281131-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index e66f5654f2ab..630f7a98df38 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -607,6 +607,39 @@ scif: serial@11c01400 { status = "disabled"; }; + i3c: i3c@12400000 { + compatible = "renesas,r9a09g057-i3c", "renesas,r9a09g047-i3c"; + reg = <0 0x12400000 0 0x10000>; + clocks = <&cpg CPG_MOD 0x91>, <&cpg CPG_MOD 0x92>, <&cpg CPG_MOD 0x90>; + clock-names = "pclk", "tclk", "pclkrw"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ierr", "terr", "abort", "resp", + "cmd", "ibi", "rx", "tx", "rcv", + "st", "sp", "tend", "nack", + "al", "tmo", "wu"; + resets = <&cpg 0x96>, <&cpg 0x97>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + rspi0: spi@12800000 { compatible = "renesas,r9a09g057-rspi"; reg = <0x0 0x12800000 0x0 0x400>; From 16e10c91ae4d4cab6fd8aa605689ebd31de98888 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 4 Sep 2025 17:59:09 +0100 Subject: [PATCH 775/931] arm64: dts: renesas: r9a09g056: Add I3C node Add I3C node to RZ/V2N ("R9A09G056") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250904165909.281131-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 50a3d42d192c..887110878906 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -369,6 +369,39 @@ scif: serial@11c01400 { status = "disabled"; }; + i3c: i3c@12400000 { + compatible = "renesas,r9a09g056-i3c", "renesas,r9a09g047-i3c"; + reg = <0 0x12400000 0 0x10000>; + clocks = <&cpg CPG_MOD 0x91>, <&cpg CPG_MOD 0x92>, <&cpg CPG_MOD 0x90>; + clock-names = "pclk", "tclk", "pclkrw"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ierr", "terr", "abort", "resp", + "cmd", "ibi", "rx", "tx", "rcv", + "st", "sp", "tend", "nack", + "al", "tmo", "wu"; + resets = <&cpg 0x96>, <&cpg 0x97>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <3>; + #size-cells = <0>; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; From 675621b20f7bd3abaa2ee47f397894d9cab90c9a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 4 Sep 2025 23:01:18 +0200 Subject: [PATCH 776/931] arm64: dts: renesas: rcar: Rename dsi-encoder to dsi Rename "dsi-encoder" nodes to "dsi" to follow node name pattern in Documentation/devicetree/bindings/display/dsi-controller.yaml. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250904210147.186728-1-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20250904210147.186728-2-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20250904210147.186728-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 95ff69339991..2c3fb34abb28 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -2949,7 +2949,7 @@ isp3vin31: endpoint { }; }; - dsi0: dsi-encoder@fed80000 { + dsi0: dsi@fed80000 { compatible = "renesas,r8a779a0-dsi-csi2-tx"; reg = <0 0xfed80000 0 0x10000>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2977,7 +2977,7 @@ port@1 { }; }; - dsi1: dsi-encoder@fed90000 { + dsi1: dsi@fed90000 { compatible = "renesas,r8a779a0-dsi-csi2-tx"; reg = <0 0xfed90000 0 0x10000>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 8d9ca30c299c..4fae063bf91b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -2476,7 +2476,7 @@ isp1vin15: endpoint { }; }; - dsi0: dsi-encoder@fed80000 { + dsi0: dsi@fed80000 { compatible = "renesas,r8a779g0-dsi-csi2-tx"; reg = <0 0xfed80000 0 0x10000>; clocks = <&cpg CPG_MOD 415>, @@ -2505,7 +2505,7 @@ port@1 { }; }; - dsi1: dsi-encoder@fed90000 { + dsi1: dsi@fed90000 { compatible = "renesas,r8a779g0-dsi-csi2-tx"; reg = <0 0xfed90000 0 0x10000>; clocks = <&cpg CPG_MOD 416>, diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index ed1eefa3515d..0f20a2d23983 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -2144,7 +2144,7 @@ isp1vin15: endpoint { }; }; - dsi0: dsi-encoder@fed80000 { + dsi0: dsi@fed80000 { compatible = "renesas,r8a779h0-dsi-csi2-tx"; reg = <0 0xfed80000 0 0x10000>; clocks = <&cpg CPG_MOD 415>, From 3ba261af4214996915970448fc308cde93cc3345 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Fri, 5 Sep 2025 10:40:47 +0200 Subject: [PATCH 777/931] arm64: dts: renesas: sparrow-hawk: Add overlay for IMX219 on J1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add an overlay to connect an IMX219 camera sensor to the J1 connector. The IMX219 utilizes 2 CSI-2 D-PHY lanes. This enables the video capture pipeline behind the CSI40 Rx to be enabled to process images from the sensor. Signed-off-by: Niklas Söderlund Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250905084050.310651-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 3 + ...8a779g3-sparrow-hawk-camera-j1-imx219.dtso | 116 ++++++++++++++++++ 2 files changed, 119 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx219.dtso diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index d8c923762466..82656bce02e9 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -96,6 +96,9 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single-ard-audio-da7212.dtb DTC_FLAGS_r8a779g3-sparrow-hawk += -Wno-spi_bus_bridge dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx219.dtbo +r8a779g3-sparrow-hawk-camera-j1-imx219-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j1-imx219.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx219.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtbo r8a779g3-sparrow-hawk-fan-pwm-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-fan-pwm.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx219.dtso b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx219.dtso new file mode 100644 index 000000000000..3acaf714cf24 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx219.dtso @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for an IMX219 camera sensor on connector J1 on R-Car V4H + * ES3.0 Sparrow Hawk board. + * + * Copyright 2025 Renesas Electronics Corp. + * Copyright 2025 Niklas Söderlund + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + clk_cam_j1: clk-cam-j1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + /* Page 29 / CSI_IF_CN / J1 */ + reg_cam_j1: reg-cam-j1 { + compatible = "regulator-fixed"; + regulator-name = "cam-J1"; + enable-active-high; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cam@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_j1>; + + VANA-supply = <®_cam_j1>; + VDIG-supply = <®_cam_j1>; + VDDL-supply = <®_cam_j1>; + + orientation = <2>; + rotation = <0>; + + port { + imx219_j1_out: endpoint { + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + data-lanes = <1 2>; + remote-endpoint = <&csi40_in>; + }; + }; + }; +}; + +/* Page 29 / CSI_IF_CN */ +&csi40 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi40_in: endpoint { + bus-type = ; + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&imx219_j1_out>; + }; + }; + }; +}; + +&isp0 { + status = "okay"; +}; + +&vin00 { + status = "okay"; +}; + +&vin01 { + status = "okay"; +}; + +&vin02 { + status = "okay"; +}; + +&vin03 { + status = "okay"; +}; + +&vin04 { + status = "okay"; +}; + +&vin05 { + status = "okay"; +}; + +&vin06 { + status = "okay"; +}; + +&vin07 { + status = "okay"; +}; From 6e7f6aa88405bc6c1fc29d4104f9040688ca5efc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Fri, 5 Sep 2025 10:40:48 +0200 Subject: [PATCH 778/931] arm64: dts: renesas: sparrow-hawk: Add overlay for IMX219 on J2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add an overlay to connect an IMX219 camera sensor to the J2 connector. The IMX219 utilizes 2 CSI-2 D-PHY lanes. This enables the video capture pipeline behind the CSI41 Rx to be enabled to process images from the sensor. Signed-off-by: Niklas Söderlund Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250905084050.310651-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 3 + ...8a779g3-sparrow-hawk-camera-j2-imx219.dtso | 116 ++++++++++++++++++ 2 files changed, 119 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx219.dtso diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 82656bce02e9..8a5302b0412e 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -99,6 +99,9 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx219.dtbo r8a779g3-sparrow-hawk-camera-j1-imx219-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j1-imx219.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx219.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx219.dtbo +r8a779g3-sparrow-hawk-camera-j2-imx219-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j2-imx219.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx219.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtbo r8a779g3-sparrow-hawk-fan-pwm-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-fan-pwm.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx219.dtso b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx219.dtso new file mode 100644 index 000000000000..512810b861aa --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx219.dtso @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for an IMX219 camera sensor on connector J2 on R-Car V4H + * ES3.0 Sparrow Hawk board. + * + * Copyright 2025 Renesas Electronics Corp. + * Copyright 2025 Niklas Söderlund + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + clk_cam_j2: clk-cam-j2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + /* Page 29 / CSI_IF_CN / J2 */ + reg_cam_j2: reg-cam-j2 { + compatible = "regulator-fixed"; + regulator-name = "cam-J2"; + enable-active-high; + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cam@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_cam_j2>; + + VANA-supply = <®_cam_j2>; + VDIG-supply = <®_cam_j2>; + VDDL-supply = <®_cam_j2>; + + orientation = <2>; + rotation = <0>; + + port { + imx219_j2_out: endpoint { + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + data-lanes = <1 2>; + remote-endpoint = <&csi41_in>; + }; + }; + }; +}; + +/* Page 29 / CSI_IF_CN */ +&csi41 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi41_in: endpoint { + bus-type = ; + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&imx219_j2_out>; + }; + }; + }; +}; + +&isp1 { + status = "okay"; +}; + +&vin08 { + status = "okay"; +}; + +&vin09 { + status = "okay"; +}; + +&vin10 { + status = "okay"; +}; + +&vin11 { + status = "okay"; +}; + +&vin12 { + status = "okay"; +}; + +&vin13 { + status = "okay"; +}; + +&vin14 { + status = "okay"; +}; + +&vin15 { + status = "okay"; +}; From de6a859c29e6624eabac0a474562290ee49850d4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Fri, 5 Sep 2025 10:40:49 +0200 Subject: [PATCH 779/931] arm64: dts: renesas: sparrow-hawk: Add overlay for IMX462 on J1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add an overlay to connect an IMX462 camera sensor to the J1 connector. The IMX462 utilizes 4 CSI-2 D-PHY lanes. This enables the video capture pipeline behind the CSI40 Rx to be enabled to process images from the sensor. Signed-off-by: Niklas Söderlund Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250905084050.310651-4-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 3 + ...8a779g3-sparrow-hawk-camera-j1-imx462.dtso | 117 ++++++++++++++++++ 2 files changed, 120 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx462.dtso diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 8a5302b0412e..0bd225a92b25 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -99,6 +99,9 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx219.dtbo r8a779g3-sparrow-hawk-camera-j1-imx219-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j1-imx219.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx219.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx462.dtbo +r8a779g3-sparrow-hawk-camera-j1-imx462-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j1-imx462.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx462.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx219.dtbo r8a779g3-sparrow-hawk-camera-j2-imx219-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j2-imx219.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx219.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx462.dtso b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx462.dtso new file mode 100644 index 000000000000..a19bc0840392 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j1-imx462.dtso @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for an IMX462 camera sensor on connector J1 on R-Car V4H + * ES3.0 Sparrow Hawk board. + * + * Copyright 2025 Renesas Electronics Corp. + * Copyright 2025 Niklas Söderlund + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + clk_cam_j1: clk-cam-j1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <37125000>; + }; + + /* Page 29 / CSI_IF_CN / J1 */ + reg_cam_j1: reg-cam-j1 { + compatible = "regulator-fixed"; + regulator-name = "cam-J1"; + enable-active-high; + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cam@1a { + compatible = "sony,imx462lqr"; + reg = <0x1a>; + + clocks = <&clk_cam_j1>; + clock-names = "xclk"; + clock-frequency = <37125000>; + + vdddo-supply = <®_cam_j1>; + vdda-supply = <®_cam_j1>; + vddd-supply = <®_cam_j1>; + + orientation = <2>; + rotation = <0>; + + port { + imx462_j1_out: endpoint { + link-frequencies = /bits/ 64 <222750000 148500000>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; +}; + +/* Page 29 / CSI_IF_CN */ +&csi40 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi40_in: endpoint { + bus-type = ; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&imx462_j1_out>; + }; + }; + }; +}; + +&isp0 { + status = "okay"; +}; + +&vin00 { + status = "okay"; +}; + +&vin01 { + status = "okay"; +}; + +&vin02 { + status = "okay"; +}; + +&vin03 { + status = "okay"; +}; + +&vin04 { + status = "okay"; +}; + +&vin05 { + status = "okay"; +}; + +&vin06 { + status = "okay"; +}; + +&vin07 { + status = "okay"; +}; From babab7f22da6ae04b87c0cded98622ea4a648910 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Fri, 5 Sep 2025 10:40:50 +0200 Subject: [PATCH 780/931] arm64: dts: renesas: sparrow-hawk: Add overlay for IMX462 on J2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add an overlay to connect an IMX462 camera sensor to the J2 connector. The IMX462 utilizes 4 CSI-2 D-PHY lanes. This enables the video capture pipeline behind the CSI41 Rx to be enabled to process images from the sensor. Signed-off-by: Niklas Söderlund Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250905084050.310651-5-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 3 + ...8a779g3-sparrow-hawk-camera-j2-imx462.dtso | 117 ++++++++++++++++++ 2 files changed, 120 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx462.dtso diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 0bd225a92b25..ccdf7aaeca13 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -105,6 +105,9 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j1-imx462.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx219.dtbo r8a779g3-sparrow-hawk-camera-j2-imx219-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j2-imx219.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx219.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx462.dtbo +r8a779g3-sparrow-hawk-camera-j2-imx462-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-camera-j2-imx462.dtbo +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-camera-j2-imx462.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtbo r8a779g3-sparrow-hawk-fan-pwm-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-fan-pwm.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-fan-pwm.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx462.dtso b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx462.dtso new file mode 100644 index 000000000000..a31524b59834 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-camera-j2-imx462.dtso @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Overlay for an IMX462 camera sensor on connector J2 on R-Car V4H + * ES3.0 Sparrow Hawk board. + * + * Copyright 2025 Renesas Electronics Corp. + * Copyright 2025 Niklas Söderlund + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + clk_cam_j2: clk-cam-j2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <37125000>; + }; + + /* Page 29 / CSI_IF_CN / J2 */ + reg_cam_j2: reg-cam-j2 { + compatible = "regulator-fixed"; + regulator-name = "cam-J2"; + enable-active-high; + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cam@1a { + compatible = "sony,imx462lqr"; + reg = <0x1a>; + + clocks = <&clk_cam_j2>; + clock-names = "xclk"; + clock-frequency = <37125000>; + + vdddo-supply = <®_cam_j2>; + vdda-supply = <®_cam_j2>; + vddd-supply = <®_cam_j2>; + + orientation = <2>; + rotation = <0>; + + port { + imx462_j2_out: endpoint { + link-frequencies = /bits/ 64 <222750000 148500000>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi41_in>; + }; + }; + }; +}; + +/* Page 29 / CSI_IF_CN */ +&csi41 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi41_in: endpoint { + bus-type = ; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&imx462_j2_out>; + }; + }; + }; +}; + +&isp1 { + status = "okay"; +}; + +&vin08 { + status = "okay"; +}; + +&vin09 { + status = "okay"; +}; + +&vin10 { + status = "okay"; +}; + +&vin11 { + status = "okay"; +}; + +&vin12 { + status = "okay"; +}; + +&vin13 { + status = "okay"; +}; + +&vin14 { + status = "okay"; +}; + +&vin15 { + status = "okay"; +}; From 5bf682d9747277a0190e82e5ae6f9e201ce002d9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 8 Sep 2025 00:53:05 +0200 Subject: [PATCH 781/931] arm64: dts: renesas: sparrow-hawk-fan-pwm: Rework hwmon comment Reword fan DT overlay hwmon comment to accurately locate the fan control sysfs hwmon node on Retronix R-Car V4H Sparrow Hawk. No functional change. Signed-off-by: Marek Vasut Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250907225338.426253-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- .../renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso index 50d53c8d76c5..fbfec57db11e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-fan-pwm.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Overlay for the PWM controlled blower fan in connector J3:FAN + * Device Tree Overlay for the PWM controlled blower fan on connector J3:FAN * on R-Car V4H ES3.0 Sparrow Hawk board * * Copyright (C) 2025 Marek Vasut @@ -9,21 +9,16 @@ * * # Localize hwmon sysfs directory that matches the PWM fan, * # enable the PWM fan, and configure the fan speed manually. - * r8a779g3-sparrow-hawk$ grep -H . /sys/class/hwmon/hwmon?/name - * /sys/class/hwmon/hwmon0/name:sensor1_thermal - * /sys/class/hwmon/hwmon1/name:sensor2_thermal - * /sys/class/hwmon/hwmon2/name:sensor3_thermal - * /sys/class/hwmon/hwmon3/name:sensor4_thermal - * /sys/class/hwmon/hwmon4/name:pwmfan - * ^ ^^^^^^ + * r8a779g3-sparrow-hawk$ ls -1 /sys/devices/platform/pwm-fan/hwmon/hwmon?/pwm?_enable + * /sys/devices/platform/pwm-fan/hwmon/hwmon4/pwm1_enable * * # Select mode 2 , enable fan PWM and regulator and keep them enabled. * # For details, see Linux Documentation/hwmon/pwm-fan.rst - * r8a779g3-sparrow-hawk$ echo 2 > /sys/class/hwmon/hwmon4/pwm1_enable + * r8a779g3-sparrow-hawk$ echo 2 > /sys/devices/platform/pwm-fan/hwmon/hwmon4/pwm1_enable * * # Configure PWM fan speed in range 0..255 , 0 is stopped , 255 is full speed . * # Fan speed 101 is about 2/5 of the PWM fan speed: - * r8a779g3-sparrow-hawk$ echo 101 > /sys/class/hwmon/hwmon4/pwm1 + * r8a779g3-sparrow-hawk$ echo 101 > /sys/devices/platform/pwm-fan/hwmon/hwmon4/pwm1 */ /dts-v1/; From 98967109c9c0e2de4140827628c63f96314099ab Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:52 +0200 Subject: [PATCH 782/931] arm64: dts: mediatek: mt6331: Fix pmic, regulators, rtc, keys node names The node names for "pmic", "regulators", "rtc", and "keys" are dictated by the PMIC MFD binding: change those to adhere to it. Fixes: aef783f3e0ca ("arm64: dts: mediatek: Add MT6331 PMIC devicetree") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20250724083914.61351-17-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6331.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6331.dtsi b/arch/arm64/boot/dts/mediatek/mt6331.dtsi index d89858c73ab1..243afbffa21f 100644 --- a/arch/arm64/boot/dts/mediatek/mt6331.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6331.dtsi @@ -6,12 +6,12 @@ #include &pwrap { - pmic: mt6331 { + pmic: pmic { compatible = "mediatek,mt6331"; interrupt-controller; #interrupt-cells = <2>; - mt6331regulator: mt6331regulator { + mt6331regulator: regulators { compatible = "mediatek,mt6331-regulator"; mt6331_vdvfs11_reg: buck-vdvfs11 { @@ -258,7 +258,7 @@ mt6331_vrtc_reg: ldo-vrtc { }; mt6331_vdig18_reg: ldo-vdig18 { - regulator-name = "dvdd18_dig"; + regulator-name = "vdig18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-ramp-delay = <0>; @@ -266,11 +266,11 @@ mt6331_vdig18_reg: ldo-vdig18 { }; }; - mt6331rtc: mt6331rtc { + mt6331rtc: rtc { compatible = "mediatek,mt6331-rtc"; }; - mt6331keys: mt6331keys { + mt6331keys: keys { compatible = "mediatek,mt6331-keys"; power { linux,keycodes = ; From e3c84c9408bbaead850daf5e5f515ea025821b57 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:53 +0200 Subject: [PATCH 783/931] arm64: dts: mediatek: mt6797: Fix pinctrl node names Change the pinctrl node names to adhere to the binding: the main nodes are now named like "uart0-pins" and the children "pins-bus". Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20250724083914.61351-18-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6797.dtsi | 40 ++++++++++++------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index 0e9d11b4585b..be401617dfd8 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -135,71 +135,71 @@ pio: pinctrl@10005000 { gpio-controller; #gpio-cells = <2>; - uart0_pins_a: uart0 { - pins0 { + uart0_pins_a: uart0-pins { + pins-bus { pinmux = , ; }; }; - uart1_pins_a: uart1 { - pins1 { + uart1_pins_a: uart1-pins { + pins-bus { pinmux = , ; }; }; - i2c0_pins_a: i2c0 { - pins0 { + i2c0_pins_a: i2c0-pins { + pins-bus { pinmux = , ; }; }; - i2c1_pins_a: i2c1 { - pins1 { + i2c1_pins_a: i2c1-pins { + pins-bus { pinmux = , ; }; }; - i2c2_pins_a: i2c2 { - pins2 { + i2c2_pins_a: i2c2-pins { + pins-bus { pinmux = , ; }; }; - i2c3_pins_a: i2c3 { - pins3 { + i2c3_pins_a: i2c3-pins { + pins-bus { pinmux = , ; }; }; - i2c4_pins_a: i2c4 { - pins4 { + i2c4_pins_a: i2c4-pins { + pins-bus { pinmux = , ; }; }; - i2c5_pins_a: i2c5 { - pins5 { + i2c5_pins_a: i2c5-pins { + pins-bus { pinmux = , ; }; }; - i2c6_pins_a: i2c6 { - pins6 { + i2c6_pins_a: i2c6-pins { + pins-bus { pinmux = , ; }; }; - i2c7_pins_a: i2c7 { - pins7 { + i2c7_pins_a: i2c7-pins { + pins-bus { pinmux = , ; }; From d1a7bf9031b9f91b86187bcd5bd7a4bfd76bcaef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Macholda?= Date: Thu, 11 Sep 2025 18:13:07 +0200 Subject: [PATCH 784/931] dt-bindings: marvell: armada-37xx: add ripe,atlas-v5 compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document compatible for RIPE Atlas Probe v5. Signed-off-by: Tomáš Macholda Acked-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml index 51e1386f0e01..b2f4fe81b97c 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml +++ b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml @@ -23,6 +23,7 @@ properties: - marvell,armada-3720-db - methode,edpu - methode,udpu + - ripe,atlas-v5 - const: marvell,armada3720 - const: marvell,armada3710 From 0b738a2901f43980fc2307a50a26457be1c8030b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Macholda?= Date: Thu, 11 Sep 2025 18:13:08 +0200 Subject: [PATCH 785/931] arm64: dts: marvell: add dts for RIPE Atlas Probe v5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit internet measurement device based on Turris MOX Signed-off-by: Tomáš Macholda Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/Makefile | 1 + .../boot/dts/marvell/armada-3720-atlas-v5.dts | 110 ++++++++++++++++++ 2 files changed, 111 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 40e5ac6cd468..a774bc74a0a0 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 # Mvebu SoC Family +dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-atlas-v5.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-eDPU.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts b/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts new file mode 100644 index 000000000000..070d10a705bb --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-3720-atlas-v5.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for RIPE Atlas Probe v5 + * 2025 by Marek Behún + */ + +/dts-v1/; + +#include +#include +#include +#include "armada-372x.dtsi" + +/ { + model = "RIPE Atlas Probe v5"; + compatible = "ripe,atlas-v5", "marvell,armada3720", + "marvell,armada3710"; + + aliases { + ethernet0 = ð0; + mmc0 = &sdhci0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + led { + gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_ACTIVITY; + color = ; + linux,default-trigger = "default-on"; + }; + }; + + vsdc_reg: vsdc-reg { + compatible = "regulator-gpio"; + regulator-name = "vsdc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1 + 3300000 0x0>; + enable-active-high; + }; + + firmware { + armada-3700-rwtm { + compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm"; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii-id"; + phy-handle = <&phy1>; + status = "okay"; +}; + +&sdhci0 { + non-removable; + bus-width = <4>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + sd-uhs-sdr104; + marvell,xenon-emmc; + marvell,xenon-tun-count = <9>; + marvell,pad-type = "fixed-1-8v"; + vqmmc-supply = <&vsdc_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pins>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + mmccard: mmccard@0 { + compatible = "mmc-card"; + reg = <0>; + }; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&smi_pins>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; From 1cc3d6c8640e4a75dab4077121b8cafd15eab8b0 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 11 Sep 2025 20:28:07 +0200 Subject: [PATCH 786/931] arm64: dts: marvell: cn9130-sr-som: add missing properties to emmc CN9130 System on Module connects an eMMC to ap_sdhci0, but the common properties indicating eMMC were not added to device-tree. Add no-sdio and non-removable as applicable to eMMC. Signed-off-by: Josua Mayer Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi index a997bbabedd8..f95202decfce 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi @@ -61,6 +61,8 @@ &ap_sdhci0 { pinctrl-0 = <&ap_mmc0_pins>; pinctrl-names = "default"; vqmmc-supply = <&v_1_8>; + no-sdio; + non-removable; status = "okay"; }; From 50dd9ea91de1c0fa23a91ac9850f01c8d4e44172 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:54 +0200 Subject: [PATCH 787/931] arm64: dts: mediatek: mt6797: Remove bogus id property in i2c nodes All of the I2C nodes in this devicetree has a bogus "id" property, which was probably specifying the I2C bus number. This property was never parsed and never used - and besides, it also gives dtbs_check warnings: remove it from all i2c nodes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20250724083914.61351-19-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6797.dtsi | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index be401617dfd8..f2d93bf6a055 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -285,7 +285,6 @@ uart3: serial@11005000 { i2c0: i2c@11007000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <0>; reg = <0 0x11007000 0 0x1000>, <0 0x11000100 0 0x80>; interrupts = ; @@ -301,7 +300,6 @@ i2c0: i2c@11007000 { i2c1: i2c@11008000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <1>; reg = <0 0x11008000 0 0x1000>, <0 0x11000180 0 0x80>; interrupts = ; @@ -317,7 +315,6 @@ i2c1: i2c@11008000 { i2c8: i2c@11009000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <8>; reg = <0 0x11009000 0 0x1000>, <0 0x11000200 0 0x80>; interrupts = ; @@ -334,7 +331,6 @@ i2c8: i2c@11009000 { i2c9: i2c@1100d000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <9>; reg = <0 0x1100d000 0 0x1000>, <0 0x11000280 0 0x80>; interrupts = ; @@ -351,7 +347,6 @@ i2c9: i2c@1100d000 { i2c6: i2c@1100e000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <6>; reg = <0 0x1100e000 0 0x1000>, <0 0x11000500 0 0x80>; interrupts = ; @@ -367,7 +362,6 @@ i2c6: i2c@1100e000 { i2c7: i2c@11010000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <7>; reg = <0 0x11010000 0 0x1000>, <0 0x11000580 0 0x80>; interrupts = ; @@ -383,7 +377,6 @@ i2c7: i2c@11010000 { i2c4: i2c@11011000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <4>; reg = <0 0x11011000 0 0x1000>, <0 0x11000300 0 0x80>; interrupts = ; @@ -399,7 +392,6 @@ i2c4: i2c@11011000 { i2c2: i2c@11013000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <2>; reg = <0 0x11013000 0 0x1000>, <0 0x11000400 0 0x80>; interrupts = ; @@ -416,7 +408,6 @@ i2c2: i2c@11013000 { i2c3: i2c@11014000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <3>; reg = <0 0x11014000 0 0x1000>, <0 0x11000480 0 0x80>; interrupts = ; @@ -433,7 +424,6 @@ i2c3: i2c@11014000 { i2c5: i2c@1101c000 { compatible = "mediatek,mt6797-i2c", "mediatek,mt6577-i2c"; - id = <5>; reg = <0 0x1101c000 0 0x1000>, <0 0x11000380 0 0x80>; interrupts = ; From 4f6a808b36eb4cb1cfde4c46be8c64653c606d00 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:55 +0200 Subject: [PATCH 788/931] arm64: dts: mediatek: mt6795: Add mediatek,infracfg to iommu node The "M4U" IOMMU requires a handle to the infracfg to switch to the 4gb/pae addressing mode: add it. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20250724083914.61351-20-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index e5e269a660b1..38f65aad2802 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -427,6 +427,7 @@ iommu: iommu@10205000 { clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; interrupts = ; + mediatek,infracfg = <&infracfg>; mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>; power-domains = <&spm MT6795_POWER_DOMAIN_MM>; #iommu-cells = <1>; From 236681fb64102f25ed11df55999e6985c1bc2f7d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:56 +0200 Subject: [PATCH 789/931] arm64: dts: mediatek: mt6795-xperia-m5: Fix mmc0 latch-ck value Change the latch-ck value from 0x14 to 4: as only bits [0-3] are actually used, the final value that gets written to the register field for DAT_LATCH_CK_SEL is just 0x4. This also fixes dtbs_check warnings. Fixes: 5a65dcccf483 ("arm64: dts: mediatek: mt6795-xperia-m5: Add eMMC, MicroSD slot, SDIO") Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250724083914.61351-21-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index 91de920c2245..03cc48321a3f 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -212,7 +212,7 @@ proximity@48 { &mmc0 { /* eMMC controller */ - mediatek,latch-ck = <0x14>; /* hs400 */ + mediatek,latch-ck = <4>; /* hs400 */ mediatek,hs200-cmd-int-delay = <1>; mediatek,hs400-cmd-int-delay = <1>; mediatek,hs400-ds-dly3 = <0x1a>; From 20be341f0b911a184934b17e9a9cf025da208974 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:57 +0200 Subject: [PATCH 790/931] arm64: dts: mediatek: mt6795-sony-xperia-m5: Add pinctrl for mmc1/mmc2 Add pinctrl nodes for the MicroSD slot on mmc1 and SDIO Controller on mmc2 and assign those to the respective controller nodes. This makes sure that all of the pins are muxed in the right state and with the right pullup/down(s) before trying to use the mmc controllers. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250724083914.61351-22-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../dts/mediatek/mt6795-sony-xperia-m5.dts | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index 03cc48321a3f..fccb948cfa45 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -227,6 +227,8 @@ &mmc0 { &mmc1 { /* MicroSD card slot */ + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; vmmc-supply = <&mt6331_vmc_reg>; vqmmc-supply = <&mt6331_vmch_reg>; status = "okay"; @@ -234,6 +236,8 @@ &mmc1 { &mmc2 { /* SDIO WiFi on MMC2 */ + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; vmmc-supply = <&mt6331_vmc_reg>; vqmmc-supply = <&mt6331_vmch_reg>; status = "okay"; @@ -311,6 +315,40 @@ pins-ds { }; }; + mmc1_pins_default: microsd-pins { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + bias-pull-down = ; + }; + }; + + mmc2_pins_default: sdio-pins { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + bias-pull-down = ; + }; + }; + nfc_pins: nfc-pins { pins-irq { pinmux = ; From 3f9f2a32ddcb18066656f793a7285ceeb4431ed7 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:58 +0200 Subject: [PATCH 791/931] arm64: dts: mediatek: Fix node name for SYSIRQ controller on all SoCs The sysirq has "intpol-controller" as node name, but being this an interrupt controller, it needs to be named "interrupt-controller" as per what the bindings (correctly) expect. This commit brings no functional changes, but fixes a dtbs_check warning. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20250724083914.61351-23-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6755.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt6779.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt6797.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6755.dtsi b/arch/arm64/boot/dts/mediatek/mt6755.dtsi index b55d3fac9bd4..8da5c0a56a02 100644 --- a/arch/arm64/boot/dts/mediatek/mt6755.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6755.dtsi @@ -98,7 +98,7 @@ timer { (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; - sysirq: intpol-controller@10200620 { + sysirq: interrupt-controller@10200620 { compatible = "mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi index 5c579e88e749..70f3375916e8 100644 --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -138,7 +138,7 @@ ppi_cluster1: interrupt-partition-1 { }; - sysirq: intpol-controller@c53a650 { + sysirq: interrupt-controller@c53a650 { compatible = "mediatek,mt6779-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 38f65aad2802..58833e5135c8 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -404,7 +404,7 @@ pwrap: pwrap@1000d000 { clock-names = "spi", "wrap"; }; - sysirq: intpol-controller@10200620 { + sysirq: interrupt-controller@10200620 { compatible = "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index f2d93bf6a055..8ac98a378fd6 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -228,7 +228,7 @@ apmixedsys: apmixed@1000c000 { #clock-cells = <1>; }; - sysirq: intpol-controller@10200620 { + sysirq: interrupt-controller@10200620 { compatible = "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; From 6b3fff78c13f1a2ba5a355a101fa1ca0a13054ad Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:38:59 +0200 Subject: [PATCH 792/931] arm64: dts: mediatek: mt7986a: Fix PCI-Express T-PHY node address The PCIe TPHY is under the soc bus, which provides MMIO, and all nodes under that must use the bus, otherwise those would clearly be out of place. Add ranges to the PCIe tphy and assign the address to the main node to silence a dtbs_check warning, and fix the children to use the MMIO range of t-phy. Fixes: 963c3b0c47ec ("arm64: dts: mediatek: fix t-phy unit name") Fixes: 918aed7abd2d ("arm64: dts: mt7986: add pcie related device nodes") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20250724083914.61351-24-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index a9e079fd42c6..a8972330a7b8 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -428,16 +428,16 @@ pcie_intc: interrupt-controller { }; }; - pcie_phy: t-phy { + pcie_phy: t-phy@11c00000 { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; - ranges; - #address-cells = <2>; - #size-cells = <2>; + ranges = <0 0 0x11c00000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; status = "disabled"; - pcie_port: pcie-phy@11c00000 { - reg = <0 0x11c00000 0 0x20000>; + pcie_port: pcie-phy@0 { + reg = <0 0x20000>; clocks = <&clk40m>; clock-names = "ref"; #phy-cells = <1>; From e11590394fc999c64a67b3a49f89e37fb839fb7d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:39:00 +0200 Subject: [PATCH 793/931] arm64: dts: mediatek: mt7986a-bpi-r3: Fix SFP I2C node names The binding wants the node to be named "i2c-number", alternatively "i2c@address", but those are named "i2c-gpio-number" instead. Rename those to i2c-0, i2c-1 to adhere to the binding and suppress dtbs_check warnings. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20250724083914.61351-25-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts index ed79ad1ae871..6d2762866a1a 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -64,23 +64,19 @@ wps-key { }; /* i2c of the left SFP cage (wan) */ - i2c_sfp1: i2c-gpio-0 { + i2c_sfp1: i2c-0 { compatible = "i2c-gpio"; sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; }; /* i2c of the right SFP cage (lan) */ - i2c_sfp2: i2c-gpio-1 { + i2c_sfp2: i2c-1 { compatible = "i2c-gpio"; sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; }; leds { From 1d0775def5e71cc8074edd85c6791b8780062737 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:39:01 +0200 Subject: [PATCH 794/931] arm64: dts: mediatek: mt7986a-bpi-r3: Set interrupt-parent to mdio switch Being this an interrupt controller, the binding forbids to use interrupts-extended and wants an `interrupts` property instead. Since this interrupt controller's parent is on the GPIO controller set it as interrupt-parent and change interrupts-extended to just interrupts to silence a dtbs_check warning. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250724083914.61351-26-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts index 6d2762866a1a..e7654dc9a1c9 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -200,8 +200,9 @@ switch: switch@31 { compatible = "mediatek,mt7531"; reg = <31>; interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; - interrupts-extended = <&pio 66 IRQ_TYPE_LEVEL_HIGH>; reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; }; }; From ca27e6078ffc1581ed5ec3ac36917d26668a4462 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:39:02 +0200 Subject: [PATCH 795/931] arm64: dts: mediatek: acelink-ew-7886cax: Remove unnecessary cells in spi-nand There is no need to specify #address-cells and #size-cells in a node that has only one non-addressable subnode, and this is the case of the flash@0 node in this devicetree, as it has only one "partitions" subnode. Remove those to suppress an avoid_unnecessary_addr_size warning. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20250724083914.61351-27-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts b/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts index 08b3b0827436..30805a610262 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-acelink-ew-7886cax.dts @@ -98,8 +98,6 @@ &spi0 { flash@0 { compatible = "spi-nand"; reg = <0>; - #address-cells = <1>; - #size-cells = <1>; spi-max-frequency = <52000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; From 510e32c27e221ed9cccded07d5f56ecd82a01e2d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:39:05 +0200 Subject: [PATCH 796/931] arm64: dts: mediatek: mt8183: Fix pinctrl node names Fix the pinctrl node names to adhere to the bindings, as the main pin node is supposed to be named like "uart0-pins" and the pinmux node named like "pins-bus". Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20250724083914.61351-30-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../mediatek/mt8183-kukui-audio-da7219.dtsi | 4 +- .../mediatek/mt8183-kukui-audio-ts3a227e.dtsi | 2 +- .../dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 22 +++--- .../dts/mediatek/mt8183-kukui-kakadu.dtsi | 16 ++-- .../dts/mediatek/mt8183-kukui-kodama.dtsi | 12 +-- .../boot/dts/mediatek/mt8183-kukui-krane.dtsi | 12 +-- .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 78 +++++++++---------- 7 files changed, 73 insertions(+), 73 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi index 586eee79c73c..f69ffcb9792a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi @@ -39,8 +39,8 @@ da7219_aad { }; &pio { - da7219_pins: da7219_pins { - pins1 { + da7219_pins: da7219-pins { + pins-intn { pinmux = ; input-enable; bias-pull-up; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi index 548e22c194a2..c4aedf8cbfcd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-ts3a227e.dtsi @@ -17,7 +17,7 @@ ts3a227e: ts3a227e@3b { }; &pio { - ts3a227e_pins: ts3a227e_pins { + ts3a227e_pins: ts3a227e-pins { pins1 { pinmux = ; input-enable; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 80888bd4ad82..f2afca63c75a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -395,14 +395,14 @@ &pio { "", ""; - pp1000_mipibrdg_en: pp1000-mipibrdg-en { + pp1000_mipibrdg_en: pp1000-mipibrdg-en-pins { pins1 { pinmux = ; output-low; }; }; - pp1800_mipibrdg_en: pp1800-mipibrdg-en { + pp1800_mipibrdg_en: pp1800-mipibrdg-en-pins { pins1 { pinmux = ; output-low; @@ -410,20 +410,20 @@ pins1 { }; pp3300_panel_pins: pp3300-panel-pins { - panel_3v3_enable: panel-3v3-enable { + panel_3v3_enable: pins-panel-en { pinmux = ; output-low; }; }; - ppvarp_lcd_en: ppvarp-lcd-en { + ppvarp_lcd_en: ppvarp-lcd-en-pins { pins1 { pinmux = ; output-low; }; }; - ppvarn_lcd_en: ppvarn-lcd-en { + ppvarn_lcd_en: ppvarn-lcd-en-pins { pins1 { pinmux = ; output-low; @@ -444,27 +444,27 @@ pins2 { }; touchscreen_pins: touchscreen-pins { - touch-int-odl { + pins-intn { pinmux = ; input-enable; bias-pull-up; }; - touch-rst-l { + pins-rst { pinmux = ; output-high; }; }; trackpad_pins: trackpad-pins { - trackpad-int { + pins-intn { pinmux = ; input-enable; bias-disable; /* pulled externally */ }; }; - pp3300_mipibrdg_en: pp3300-mipibrdg-en { + pp3300_mipibrdg_en: pp3300-mipibrdg-en-pins { pins1 { pinmux = ; output-low; @@ -472,13 +472,13 @@ pins1 { }; volume_button_pins: volume-button-pins { - voldn-btn-odl { + pins-voldn { pinmux = ; input-enable; bias-pull-up; }; - volup-btn-odl { + pins-volup { pinmux = ; input-enable; bias-pull-up; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi index ff02f63bac29..472d4987615a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi @@ -304,35 +304,35 @@ &pio { "", ""; - ppvarp_lcd_en: ppvarp-lcd-en { + ppvarp_lcd_en: ppvarp-lcd-en-pins { pins1 { pinmux = ; output-low; }; }; - ppvarn_lcd_en: ppvarn-lcd-en { + ppvarn_lcd_en: ppvarn-lcd-en-pins { pins1 { pinmux = ; output-low; }; }; - pp1800_lcd_en: pp1800-lcd-en { + pp1800_lcd_en: pp1800-lcd-en-pins { pins1 { pinmux = ; output-low; }; }; - open_touch: open_touch { - irq_pin { + open_touch: opentouch-pins { + pins-intn { pinmux = ; input-enable; bias-pull-up; }; - rst_pin { + pins-rst { pinmux = ; /* @@ -349,8 +349,8 @@ rst_pin { }; }; - pen_eject: peneject { - pen_eject { + pen_eject: pen-pins { + pins-eject { pinmux = ; input-enable; /* External pull-up. */ diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi index da6e767b4cee..1b21e3958061 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi @@ -292,35 +292,35 @@ &pio { "", ""; - ppvarp_lcd_en: ppvarp-lcd-en { + ppvarp_lcd_en: ppvarp-lcd-en-pins { pins1 { pinmux = ; output-low; }; }; - ppvarn_lcd_en: ppvarn-lcd-en { + ppvarn_lcd_en: ppvarn-lcd-en-pins { pins1 { pinmux = ; output-low; }; }; - pp1800_lcd_en: pp1800-lcd-en { + pp1800_lcd_en: pp1800-lcd-en-pins { pins1 { pinmux = ; output-low; }; }; - touch_default: touchdefault { - pin_irq { + touch_default: touch-pins { + pins-intn { pinmux = ; input-enable; bias-pull-up; }; - touch_pin_reset: pin_reset { + touch_pin_reset: pins-rst { pinmux = ; /* diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi index 8b56b8564ed7..a85c73b43195 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi @@ -296,35 +296,35 @@ &pio { "", ""; - ppvarp_lcd_en: ppvarp-lcd-en { + ppvarp_lcd_en: ppvarp-lcd-en-pins { pins1 { pinmux = ; output-low; }; }; - ppvarn_lcd_en: ppvarn-lcd-en { + ppvarn_lcd_en: ppvarn-lcd-en-pins { pins1 { pinmux = ; output-low; }; }; - pp1800_lcd_en: pp1800-lcd-en { + pp1800_lcd_en: pp1800-lcd-en-pins { pins1 { pinmux = ; output-low; }; }; - open_touch: open_touch { - irq_pin { + open_touch: opentouch-pins { + pins-intn { pinmux = ; input-enable; bias-pull-up; }; - rst_pin { + pins-rst { pinmux = ; /* diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index fff93e26eb76..350b381f780d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -435,7 +435,7 @@ &mt6358_vsram_gpu_reg { }; &pio { - aud_pins_default: audiopins { + aud_pins_default: audio-pins { pins-bus { pinmux = , , @@ -457,7 +457,7 @@ pins-bus { }; }; - aud_pins_tdm_out_on: audiotdmouton { + aud_pins_tdm_out_on: audio-tdmout-on-pins { pins-bus { pinmux = , , @@ -469,7 +469,7 @@ pins-bus { }; }; - aud_pins_tdm_out_off: audiotdmoutoff { + aud_pins_tdm_out_off: audio-tdmout-off-pins { pins-bus { pinmux = , , @@ -490,22 +490,22 @@ pins-bt-en { }; }; - ec_ap_int_odl: ec-ap-int-odl { - pins1 { + ec_ap_int_odl: ec-ap-int-odl-pins { + pins-intn { pinmux = ; input-enable; bias-pull-up; }; }; - h1_int_od_l: h1-int-od-l { - pins1 { + h1_int_od_l: h1-int-od-l-pins { + pins-intn { pinmux = ; input-enable; }; }; - i2c0_pins: i2c0 { + i2c0_pins: i2c0-pins { pins-bus { pinmux = , ; @@ -513,7 +513,7 @@ pins-bus { }; }; - i2c1_pins: i2c1 { + i2c1_pins: i2c1-pins { pins-bus { pinmux = , ; @@ -521,7 +521,7 @@ pins-bus { }; }; - i2c2_pins: i2c2 { + i2c2_pins: i2c2-pins { pins-bus { pinmux = , ; @@ -529,7 +529,7 @@ pins-bus { }; }; - i2c3_pins: i2c3 { + i2c3_pins: i2c3-pins { pins-bus { pinmux = , ; @@ -537,7 +537,7 @@ pins-bus { }; }; - i2c4_pins: i2c4 { + i2c4_pins: i2c4-pins { pins-bus { pinmux = , ; @@ -545,7 +545,7 @@ pins-bus { }; }; - i2c5_pins: i2c5 { + i2c5_pins: i2c5-pins { pins-bus { pinmux = , ; @@ -553,7 +553,7 @@ pins-bus { }; }; - i2c6_pins: i2c6 { + i2c6_pins: i2c6-pins { pins-bus { pinmux = , ; @@ -561,7 +561,7 @@ pins-bus { }; }; - mmc0_pins_default: mmc0-pins-default { + mmc0_pins_default: mmc0-default-pins { pins-cmd-dat { pinmux = , , @@ -625,7 +625,7 @@ pins-rst { }; }; - mmc1_pins_default: mmc1-pins-default { + mmc1_pins_default: mmc1-default-pins { pins-cmd-dat { pinmux = , , @@ -643,7 +643,7 @@ pins-clk { }; }; - mmc1_pins_uhs: mmc1-pins-uhs { + mmc1_pins_uhs: mmc1-uhs-pins { pins-cmd-dat { pinmux = , , @@ -663,15 +663,15 @@ pins-clk { }; }; - panel_pins_default: panel-pins-default { - panel-reset { + panel_pins_default: panel-pins { + pins-panel-reset { pinmux = ; output-low; bias-pull-up; }; }; - pwm0_pin_default: pwm0-pin-default { + pwm0_pin_default: pwm0-pins { pins1 { pinmux = ; output-high; @@ -682,15 +682,15 @@ pins2 { }; }; - scp_pins: scp { + scp_pins: scp-pins { pins-scp-uart { pinmux = , ; }; }; - spi0_pins: spi0 { - pins-spi { + spi0_pins: spi0-pins { + pins-bus { pinmux = , , , @@ -699,8 +699,8 @@ pins-spi { }; }; - spi1_pins: spi1 { - pins-spi { + spi1_pins: spi1-pins { + pins-bus { pinmux = , , , @@ -709,21 +709,21 @@ pins-spi { }; }; - spi2_pins: spi2 { - pins-spi { + spi2_pins: spi2-pins { + pins-bus { pinmux = , , ; bias-disable; }; - pins-spi-mi { + pins-miso { pinmux = ; mediatek,pull-down-adv = <00>; }; }; - spi3_pins: spi3 { - pins-spi { + spi3_pins: spi3-pins { + pins-bus { pinmux = , , , @@ -732,8 +732,8 @@ pins-spi { }; }; - spi4_pins: spi4 { - pins-spi { + spi4_pins: spi4-pins { + pins-bus { pinmux = , , , @@ -742,8 +742,8 @@ pins-spi { }; }; - spi5_pins: spi5 { - pins-spi { + spi5_pins: spi5-pins { + pins-bus { pinmux = , , , @@ -752,7 +752,7 @@ pins-spi { }; }; - uart0_pins_default: uart0-pins-default { + uart0_pins_default: uart0-pins { pins-rx { pinmux = ; input-enable; @@ -763,7 +763,7 @@ pins-tx { }; }; - uart1_pins_default: uart1-pins-default { + uart1_pins_default: uart1-pins { pins-rx { pinmux = ; input-enable; @@ -781,7 +781,7 @@ pins-cts { }; }; - uart1_pins_sleep: uart1-pins-sleep { + uart1_pins_sleep: uart1-sleep-pins { pins-rx { pinmux = ; input-enable; @@ -799,14 +799,14 @@ pins-cts { }; }; - wifi_pins_pwrseq: wifi-pins-pwrseq { + wifi_pins_pwrseq: wifi-pwr-pins { pins-wifi-enable { pinmux = ; output-low; }; }; - wifi_pins_wakeup: wifi-pins-wakeup { + wifi_pins_wakeup: wifi-wake-pins { pins-wifi-wakeup { pinmux = ; input-enable; From 181eb7d996d24a02487a627de9a47294174db7a7 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:39:06 +0200 Subject: [PATCH 797/931] arm64: dts: mediatek: pumpkin-common: Fix pinctrl node names Fix the pinctrl node names to adhere to the bindings, as the main pin node is supposed to be named like "uart0-pins" and the pinmux node named like "pins-bus". Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20250724083914.61351-31-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../boot/dts/mediatek/pumpkin-common.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index a356db5fcc5f..805fb82138a8 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -198,8 +198,8 @@ &usb_phy { }; &pio { - gpio_keys_default: gpiodefault { - pins_cmd_dat { + gpio_keys_default: gpio-keys-pins { + pins-cmd-dat { pinmux = , ; bias-pull-up; @@ -207,7 +207,7 @@ pins_cmd_dat { }; }; - i2c0_pins_a: i2c0 { + i2c0_pins_a: i2c0-pins { pins1 { pinmux = , ; @@ -215,7 +215,7 @@ pins1 { }; }; - i2c2_pins_a: i2c2 { + i2c2_pins_a: i2c2-pins { pins1 { pinmux = , ; @@ -223,21 +223,21 @@ pins1 { }; }; - tca6416_pins: pinmux_tca6416_pins { - gpio_mux_rst_n_pin { + tca6416_pins: tca6416-pins { + pins-mux-rstn { pinmux = ; output-high; }; - gpio_mux_int_n_pin { + pins-mux-intn { pinmux = ; input-enable; bias-pull-up; }; }; - ethernet_pins_default: ethernet { - pins_ethernet { + ethernet_pins_default: ethernet-pins { + pins-eth { pinmux = , , , From 3808199f034fbf3633d99a97ce42a974bbe0fbe6 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:39:07 +0200 Subject: [PATCH 798/931] arm64: dts: mediatek: mt8183-pumpkin: Add power supply for CCI Add a power supply for the Cache Coherent Interconnect node as it is required to perform CPU DVFS because both are scaling together. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250724083914.61351-32-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index 7c3010889ae7..8d88cb861a5a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -482,6 +482,10 @@ &mfg { domain-supply = <&mt6358_vgpu_reg>; }; +&cci { + proc-supply = <&mt6358_vproc12_reg>; +}; + &cpu0 { proc-supply = <&mt6358_vproc12_reg>; }; From e72d63fa0563f8a6e98c10fed3a9ce74dc0536e6 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:39:08 +0200 Subject: [PATCH 799/931] arm64: dts: mediatek: mt8183: Migrate to display controller OF graph The display related IPs in MT8183 are flexible and support being interconnected with different instances of DDP IPs forming a full Display Data Path that ends with an actual display output, which is board specific. Add a common graph in the main mt8183.dtsi devicetree, which is shared between all of the currently supported boards, and do it such that only a very minimal amount of changes are needed to each board - the only required change was done in mt8183-pumpkin, using a phandle to assign the display to DPI0. All boards featuring any display functionality will extend this common graph to hook the display controller of the SoC to their specific output port(s). Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20250724083914.61351-33-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../boot/dts/mediatek/mt8183-pumpkin.dts | 10 +- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 239 +++++++++++++++++- 2 files changed, 239 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index 8d88cb861a5a..f60ef3e53a09 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -531,10 +531,8 @@ &dpi0 { pinctrl-0 = <&dpi_func_pins>; pinctrl-1 = <&dpi_idle_pins>; status = "okay"; - - port { - dpi_out: endpoint { - remote-endpoint = <&it66121_in>; - }; - }; +}; + +&dpi_out { + remote-endpoint = <&it66121_in>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 3c1fe80e64b9..960d8955d018 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1667,6 +1667,21 @@ mmsys: syscon@14000000 { mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, <&gce 1 CMDQ_THR_PRIO_HIGHEST>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + mmsys_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + + mmsys_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <&ovl_2l1_in>; + }; + }; }; dma-controller0@14001000 { @@ -1733,6 +1748,25 @@ ovl0: ovl@14008000 { clocks = <&mmsys CLK_MM_DISP_OVL0>; iommus = <&iommu M4U_PORT_DISP_OVL0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl0_in: endpoint { + remote-endpoint = <&mmsys_ep_main>; + }; + }; + + port@1 { + reg = <1>; + ovl0_out: endpoint { + remote-endpoint = <&ovl_2l0_in>; + }; + }; + }; }; ovl_2l0: ovl@14009000 { @@ -1743,6 +1777,25 @@ ovl_2l0: ovl@14009000 { clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl_2l0_in: endpoint { + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + reg = <1>; + ovl_2l0_out: endpoint { + remote-endpoint = <&rdma0_in>; + }; + }; + }; }; ovl_2l1: ovl@1400a000 { @@ -1753,6 +1806,25 @@ ovl_2l1: ovl@1400a000 { clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl_2l1_in: endpoint { + remote-endpoint = <&mmsys_ep_ext>; + }; + }; + + port@1 { + reg = <1>; + ovl_2l1_out: endpoint { + remote-endpoint = <&rdma1_in>; + }; + }; + }; }; rdma0: rdma@1400b000 { @@ -1764,6 +1836,25 @@ rdma0: rdma@1400b000 { iommus = <&iommu M4U_PORT_DISP_RDMA0>; mediatek,rdma-fifo-size = <5120>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma0_in: endpoint { + remote-endpoint = <&ovl_2l0_out>; + }; + }; + + port@1 { + reg = <1>; + rdma0_out: endpoint { + remote-endpoint = <&color0_in>; + }; + }; + }; }; rdma1: rdma@1400c000 { @@ -1775,6 +1866,25 @@ rdma1: rdma@1400c000 { iommus = <&iommu M4U_PORT_DISP_RDMA1>; mediatek,rdma-fifo-size = <2048>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma1_in: endpoint { + remote-endpoint = <&ovl_2l1_out>; + }; + }; + + port@1 { + reg = <1>; + rdma1_out: endpoint { + remote-endpoint = <&dpi_in>; + }; + }; + }; }; color0: color@1400e000 { @@ -1785,6 +1895,25 @@ color0: color@1400e000 { power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_COLOR0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + color0_in: endpoint { + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + reg = <1>; + color0_out: endpoint { + remote-endpoint = <&ccorr0_in>; + }; + }; + }; }; ccorr0: ccorr@1400f000 { @@ -1794,6 +1923,25 @@ ccorr0: ccorr@1400f000 { power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_CCORR0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccorr0_in: endpoint { + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + reg = <1>; + ccorr0_out: endpoint { + remote-endpoint = <&aal0_in>; + }; + }; + }; }; aal0: aal@14010000 { @@ -1803,6 +1951,25 @@ aal0: aal@14010000 { power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_AAL0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aal0_in: endpoint { + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + reg = <1>; + aal0_out: endpoint { + remote-endpoint = <&gamma0_in>; + }; + }; + }; }; gamma0: gamma@14011000 { @@ -1812,6 +1979,25 @@ gamma0: gamma@14011000 { power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_GAMMA0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + gamma0_in: endpoint { + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + reg = <1>; + gamma0_out: endpoint { + remote-endpoint = <&dither0_in>; + }; + }; + }; }; dither0: dither@14012000 { @@ -1821,6 +2007,25 @@ dither0: dither@14012000 { power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_DITHER0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dither0_in: endpoint { + remote-endpoint = <&gamma0_out>; + }; + }; + + port@1 { + reg = <1>; + dither0_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; }; dsi0: dsi@14014000 { @@ -1837,8 +2042,21 @@ dsi0: dsi@14014000 { phy-names = "dphy"; status = "disabled"; - port { - dsi_out: endpoint { }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { }; + }; }; }; @@ -1853,8 +2071,21 @@ dpi0: dpi@14015000 { clock-names = "pixel", "engine", "pll"; status = "disabled"; - port { - dpi_out: endpoint { }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi_in: endpoint { + remote-endpoint = <&rdma1_out>; + }; + }; + + port@1 { + reg = <1>; + dpi_out: endpoint { }; + }; }; }; From 0f4a8198d6825d75ae42ea01680a3a532d3ccb6f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:39:09 +0200 Subject: [PATCH 800/931] arm64: dts: mediatek: mt8183-kukui: Move DSI panel node to machine dtsis Not all of the kukui machines have got a real DSI panel, infact, some of those have got a DSI to eDP bridge instead: this means that the address and size cells are necessary in the first case but unnecessary in the latter. Instead of adding a bunch of /delete-node/ which would impact on human readability, move the entire panel node declaration to each of the relevant Kukui machine dtsi: even though this introduces some duplication, the advantages in readability surclass that. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20250724083914.61351-34-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 5 ---- .../dts/mediatek/mt8183-kukui-kakadu.dtsi | 27 ++++++++++++++++++ .../dts/mediatek/mt8183-kukui-kodama.dtsi | 28 +++++++++++++++++++ .../boot/dts/mediatek/mt8183-kukui-krane.dtsi | 28 +++++++++++++++++++ .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 23 --------------- 5 files changed, 83 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index f2afca63c75a..1b74ec171c10 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -93,11 +93,6 @@ cros_ec_pwm: pwm { }; }; -&dsi0 { - status = "okay"; - /delete-node/panel@0; -}; - &dsi_out { remote-endpoint = <&anx7625_in>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi index 472d4987615a..d71972c94e42 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dtsi @@ -61,6 +61,33 @@ &bluetooth { firmware-name = "nvm_00440302_i2s_eu.bin"; }; +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + panel: panel@0 { + /* compatible will be set in board dts */ + reg = <0>; + enable-gpios = <&pio 45 0>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_pins_default>; + avdd-supply = <&ppvarn_lcd>; + avee-supply = <&ppvarp_lcd>; + pp1800-supply = <&pp1800_lcd>; + backlight = <&backlight_lcd0>; + rotation = <270>; + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_out { + remote-endpoint = <&panel_in>; +}; + &i2c0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi index 1b21e3958061..b702ff066636 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi @@ -42,6 +42,34 @@ pp1800_lcd: pp1800-lcd { }; }; +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel: panel@0 { + /* compatible will be set in board dts */ + reg = <0>; + enable-gpios = <&pio 45 0>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_pins_default>; + avdd-supply = <&ppvarn_lcd>; + avee-supply = <&ppvarp_lcd>; + pp1800-supply = <&pp1800_lcd>; + backlight = <&backlight_lcd0>; + rotation = <270>; + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_out { + remote-endpoint = <&panel_in>; +}; + &i2c0 { status = "okay"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi index a85c73b43195..b6cfcafd8b06 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane.dtsi @@ -45,6 +45,34 @@ &bluetooth { firmware-name = "nvm_00440302_i2s_eu.bin"; }; +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel: panel@0 { + /* compatible will be set in board dts */ + reg = <0>; + enable-gpios = <&pio 45 0>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_pins_default>; + avdd-supply = <&ppvarn_lcd>; + avee-supply = <&ppvarp_lcd>; + pp1800-supply = <&pp1800_lcd>; + backlight = <&backlight_lcd0>; + rotation = <270>; + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_out { + remote-endpoint = <&panel_in>; +}; + &i2c0 { status = "okay"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 350b381f780d..4b87d4940c8c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -252,29 +252,6 @@ &cpu7 { &dsi0 { status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - panel: panel@0 { - /* compatible will be set in board dts */ - reg = <0>; - enable-gpios = <&pio 45 0>; - pinctrl-names = "default"; - pinctrl-0 = <&panel_pins_default>; - avdd-supply = <&ppvarn_lcd>; - avee-supply = <&ppvarp_lcd>; - pp1800-supply = <&pp1800_lcd>; - backlight = <&backlight_lcd0>; - rotation = <270>; - port { - panel_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; - -&dsi_out { - remote-endpoint = <&panel_in>; }; &gic { From a9eac43d039f86518595a8a731064309f1088fc6 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:39:10 +0200 Subject: [PATCH 801/931] arm64: dts: mediatek: mt8195: Fix ranges for jpeg enc/decoder nodes The jpeg decoder main node is under the soc bus but currently has no ranges or reg specified, while the children do, and this is wrong in multiple aspects. The very same is also valid for the jpeg encoder node. Rename the decoder and encoder nodes to "jpeg-decoder@1a040000" and to "jpeg-encoder@1a030000" respectively, and change their children to use the newly defined ranges. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20250724083914.61351-35-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 30 +++++++++++++----------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index ab0b2f606eb4..ec452d657031 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -3036,7 +3036,7 @@ venc: video-codec@1a020000 { #size-cells = <2>; }; - jpgdec-master { + jpeg-decoder@1a040000 { compatible = "mediatek,mt8195-jpgdec"; power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, @@ -3047,11 +3047,12 @@ jpgdec-master { <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0 0 0 0x1a040000 0 0x20000>, + <1 0 0 0x1b040000 0 0x10000>; - jpgdec@1a040000 { + jpgdec@0,0 { compatible = "mediatek,mt8195-jpgdec-hw"; - reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ + reg = <0 0 0 0x10000>;/* JPGDEC_C0 */ iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, @@ -3064,9 +3065,9 @@ jpgdec@1a040000 { power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; }; - jpgdec@1a050000 { + jpgdec@0,10000 { compatible = "mediatek,mt8195-jpgdec-hw"; - reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ + reg = <0 0 0x10000 0x10000>;/* JPGDEC_C1 */ iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, @@ -3079,9 +3080,9 @@ jpgdec@1a050000 { power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; }; - jpgdec@1b040000 { + jpgdec@1,0 { compatible = "mediatek,mt8195-jpgdec-hw"; - reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ + reg = <1 0 0 0x10000>;/* JPGDEC_C2 */ iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, @@ -3110,7 +3111,7 @@ vdosys0: syscon@1c01a000 { }; - jpgenc-master { + jpeg-encoder@1a030000 { compatible = "mediatek,mt8195-jpgenc"; power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, @@ -3119,11 +3120,12 @@ jpgenc-master { <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; #address-cells = <2>; #size-cells = <2>; - ranges; + ranges = <0 0 0 0x1a030000 0 0x10000>, + <1 0 0 0x1b030000 0 0x10000>; - jpgenc@1a030000 { + jpgenc@0,0 { compatible = "mediatek,mt8195-jpgenc-hw"; - reg = <0 0x1a030000 0 0x10000>; + reg = <0 0 0 0x10000>; iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, @@ -3134,9 +3136,9 @@ jpgenc@1a030000 { power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; }; - jpgenc@1b030000 { + jpgenc@1,0 { compatible = "mediatek,mt8195-jpgenc-hw"; - reg = <0 0x1b030000 0 0x10000>; + reg = <1 0 0 0x10000>; iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, From d0c8ecd9ec6d5222aade05dd63ab5dd36d52ab27 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:39:11 +0200 Subject: [PATCH 802/931] arm64: dts: mediatek: mt8195-cherry: Move VBAT-supply to Tomato R1/R2 Move the VBAT supply to mt8195-cherry-tomato-{r1,r2} as this power supply is named like that only for the Realtek RT5682i codec. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20250724083914.61351-36-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts | 1 + arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts | 1 + arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 1 - 3 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts index a82d716f10d4..a50b4e8efaba 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r1.dts @@ -13,6 +13,7 @@ / { &audio_codec { compatible = "realtek,rt5682i"; realtek,btndet-delay = <16>; + VBAT-supply = <&pp3300_z5>; }; &sound { diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts index 2d6522c144b7..a8657c0068d5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-tomato-r2.dts @@ -13,6 +13,7 @@ / { &audio_codec { compatible = "realtek,rt5682i"; realtek,btndet-delay = <16>; + VBAT-supply = <&pp3300_z5>; }; &pio_default { diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index e70599807bb1..d40f4c1b9766 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -535,7 +535,6 @@ audio_codec: codec@1a { AVDD-supply = <&mt6359_vio18_ldo_reg>; MICVDD-supply = <&pp3300_z2>; - VBAT-supply = <&pp3300_z5>; }; }; From 45049abe5bcda5b049d22423f10f74e38041a435 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:39:12 +0200 Subject: [PATCH 803/931] arm64: dts: mediatek: mt8195-cherry: Add missing regulators to rt5682 Add the missing DBVDD and LDO1-IN power supplies to the codec node as both RT5682i and RT5682s require those. This commit only fixes a dtbs_check warning but doesn't produce any functional changes because the VIO18 LDO is already powered on because it's assigned as AVDD supply anyway. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20250724083914.61351-37-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index d40f4c1b9766..b3761b80cac7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -534,7 +534,9 @@ audio_codec: codec@1a { realtek,jd-src = <1>; AVDD-supply = <&mt6359_vio18_ldo_reg>; + DBVDD-supply = <&mt6359_vio18_ldo_reg>; MICVDD-supply = <&pp3300_z2>; + LDO1-IN-supply = <&mt6359_vio18_ldo_reg>; }; }; From 09a1e9c973973aff26e66a5673c19442d91b9e3d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:39:13 +0200 Subject: [PATCH 804/931] arm64: dts: mediatek: mt8395-kontron-i1200: Fix MT6360 regulator nodes All of the MT6360 regulator nodes were wrong and would not probe because the regulator names are supposed to be lower case, but they are upper case in this devicetree. Change all nodes to be lower case to get working regulators. Fixes: 94aaf79a6af5 ("arm64: dts: mediatek: add Kontron 3.5"-SBC-i1200") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20250724083914.61351-38-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../mediatek/mt8395-kontron-3-5-sbc-i1200.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts index 4985b65925a9..d16f545cbbb2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts @@ -352,7 +352,7 @@ regulator { LDO_VIN2-supply = <&vsys>; LDO_VIN3-supply = <&vsys>; - mt6360_buck1: BUCK1 { + mt6360_buck1: buck1 { regulator-name = "emi_vdd2"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <1800000>; @@ -362,7 +362,7 @@ MT6360_OPMODE_LP regulator-always-on; }; - mt6360_buck2: BUCK2 { + mt6360_buck2: buck2 { regulator-name = "emi_vddq"; regulator-min-microvolt = <300000>; regulator-max-microvolt = <1300000>; @@ -372,7 +372,7 @@ MT6360_OPMODE_LP regulator-always-on; }; - mt6360_ldo1: LDO1 { + mt6360_ldo1: ldo1 { regulator-name = "mt6360_ldo1"; /* Test point */ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <3600000>; @@ -380,7 +380,7 @@ mt6360_ldo1: LDO1 { MT6360_OPMODE_LP>; }; - mt6360_ldo2: LDO2 { + mt6360_ldo2: ldo2 { regulator-name = "panel1_p1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -388,7 +388,7 @@ mt6360_ldo2: LDO2 { MT6360_OPMODE_LP>; }; - mt6360_ldo3: LDO3 { + mt6360_ldo3: ldo3 { regulator-name = "vmc_pmu"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; @@ -396,7 +396,7 @@ mt6360_ldo3: LDO3 { MT6360_OPMODE_LP>; }; - mt6360_ldo5: LDO5 { + mt6360_ldo5: ldo5 { regulator-name = "vmch_pmu"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -404,7 +404,7 @@ mt6360_ldo5: LDO5 { MT6360_OPMODE_LP>; }; - mt6360_ldo6: LDO6 { + mt6360_ldo6: ldo6 { regulator-name = "mt6360_ldo6"; /* Test point */ regulator-min-microvolt = <500000>; regulator-max-microvolt = <2100000>; @@ -412,7 +412,7 @@ mt6360_ldo6: LDO6 { MT6360_OPMODE_LP>; }; - mt6360_ldo7: LDO7 { + mt6360_ldo7: ldo7 { regulator-name = "emi_vmddr_en"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; From ffe6a5d1dd4d4d8af0779526cf4e40522647b25f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 24 Jul 2025 10:39:14 +0200 Subject: [PATCH 805/931] arm64: dts: mediatek: mt8516-pumpkin: Fix machine compatible This devicetree contained only the SoC compatible but lacked the machine specific one: add a "mediatek,mt8516-pumpkin" compatible to the list to fix dtbs_check warnings. Fixes: 9983822c8cf9 ("arm64: dts: mediatek: add pumpkin board dts") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Fei Shao Link: https://lore.kernel.org/r/20250724083914.61351-39-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts index cce642c53812..3d3db33a64dc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8516-pumpkin.dts @@ -11,7 +11,7 @@ / { model = "Pumpkin MT8516"; - compatible = "mediatek,mt8516"; + compatible = "mediatek,mt8516-pumpkin", "mediatek,mt8516"; memory@40000000 { device_type = "memory"; From 129d617c60c9101963f0af07dd8edfbe9d346056 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Mon, 8 Sep 2025 09:21:25 +0200 Subject: [PATCH 806/931] ARM: dts: sti: remove dangling stih407-clock file Following the removal of B2120 board support, the st/stih407-clock.dtsi file has been left unused. Remove it. Fixes: dee546e1adef ("ARM: sti: drop B2120 board support") Signed-off-by: Raphael Gallais-Pou Reviewed-by: Patrice Chotard Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/st/stih407-clock.dtsi | 210 ------------------------ 1 file changed, 210 deletions(-) delete mode 100644 arch/arm/boot/dts/st/stih407-clock.dtsi diff --git a/arch/arm/boot/dts/st/stih407-clock.dtsi b/arch/arm/boot/dts/st/stih407-clock.dtsi deleted file mode 100644 index 350bcfcf498b..000000000000 --- a/arch/arm/boot/dts/st/stih407-clock.dtsi +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2014 STMicroelectronics R&D Limited - */ -#include -/ { - /* - * Fixed 30MHz oscillator inputs to SoC - */ - clk_sysin: clk-sysin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - clk_tmdsout_hdmi: clk-tmdsout-hdmi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* - * A9 PLL. - */ - clockgen-a9@92b0000 { - compatible = "st,clkgen-c32"; - reg = <0x92b0000 0x10000>; - - clockgen_a9_pll: clockgen-a9-pll { - #clock-cells = <1>; - compatible = "st,stih407-clkgen-plla9"; - - clocks = <&clk_sysin>; - }; - - clk_m_a9: clk-m-a9 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux"; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; - }; - }; - }; - - clockgen-a@90ff000 { - compatible = "st,clkgen-c32"; - reg = <0x90ff000 0x1000>; - - clk_s_a0_pll: clk-s-a0-pll { - #clock-cells = <1>; - compatible = "st,clkgen-pll0-a0"; - - clocks = <&clk_sysin>; - }; - - clk_s_a0_flexgen: clk-s-a0-flexgen { - compatible = "st,flexgen", "st,flexgen-stih407-a0"; - - #clock-cells = <1>; - - clocks = <&clk_s_a0_pll 0>, - <&clk_sysin>; - }; - }; - - clk_s_c0: clockgen-c@9103000 { - compatible = "st,clkgen-c32"; - reg = <0x9103000 0x1000>; - - clk_s_c0_pll0: clk-s-c0-pll0 { - #clock-cells = <1>; - compatible = "st,clkgen-pll0-c0"; - - clocks = <&clk_sysin>; - }; - - clk_s_c0_pll1: clk-s-c0-pll1 { - #clock-cells = <1>; - compatible = "st,clkgen-pll1-c0"; - - clocks = <&clk_sysin>; - }; - - clk_s_c0_quadfs: clk-s-c0-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - - clocks = <&clk_sysin>; - }; - - clk_s_c0_flexgen: clk-s-c0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih407-c0"; - - clocks = <&clk_s_c0_pll0 0>, - <&clk_s_c0_pll1 0>, - <&clk_s_c0_quadfs 0>, - <&clk_s_c0_quadfs 1>, - <&clk_s_c0_quadfs 2>, - <&clk_s_c0_quadfs 3>, - <&clk_sysin>; - - /* - * ARM Peripheral clock for timers - */ - clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - - clocks = <&clk_s_c0_flexgen 13>; - - clock-output-names = "clk-m-a9-ext2f-div2"; - - clock-div = <2>; - clock-mult = <1>; - }; - }; - }; - - clockgen-d0@9104000 { - compatible = "st,clkgen-c32"; - reg = <0x9104000 0x1000>; - - clk_s_d0_quadfs: clk-s-d0-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-d0"; - - clocks = <&clk_sysin>; - }; - - clk_s_d0_flexgen: clk-s-d0-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih407-d0"; - - clocks = <&clk_s_d0_quadfs 0>, - <&clk_s_d0_quadfs 1>, - <&clk_s_d0_quadfs 2>, - <&clk_s_d0_quadfs 3>, - <&clk_sysin>; - }; - }; - - clockgen-d2@9106000 { - compatible = "st,clkgen-c32"; - reg = <0x9106000 0x1000>; - - clk_s_d2_quadfs: clk-s-d2-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-d2"; - - clocks = <&clk_sysin>; - }; - - clk_s_d2_flexgen: clk-s-d2-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih407-d2"; - - clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 1>, - <&clk_s_d2_quadfs 2>, - <&clk_s_d2_quadfs 3>, - <&clk_sysin>, - <&clk_sysin>, - <&clk_tmdsout_hdmi>; - }; - }; - - clockgen-d3@9107000 { - compatible = "st,clkgen-c32"; - reg = <0x9107000 0x1000>; - - clk_s_d3_quadfs: clk-s-d3-quadfs { - #clock-cells = <1>; - compatible = "st,quadfs-d3"; - - clocks = <&clk_sysin>; - }; - - clk_s_d3_flexgen: clk-s-d3-flexgen { - #clock-cells = <1>; - compatible = "st,flexgen", "st,flexgen-stih407-d3"; - - clocks = <&clk_s_d3_quadfs 0>, - <&clk_s_d3_quadfs 1>, - <&clk_s_d3_quadfs 2>, - <&clk_s_d3_quadfs 3>, - <&clk_sysin>; - }; - }; - }; -}; From e9671ddd82eee96146a7359431a4e1f04ac2b076 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 12 Sep 2025 01:47:04 +0800 Subject: [PATCH 807/931] dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock The main clock controller on the A523/T527 has the NPU's module clock. It was missing from the original submission, likely because that was based on the A523 user manual; the A523 is marketed without the NPU. Reviewed-by: Andre Przywara Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250911174710.3149589-2-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- include/dt-bindings/clock/sun55i-a523-ccu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/sun55i-a523-ccu.h b/include/dt-bindings/clock/sun55i-a523-ccu.h index c8259ac5ada7..54808fcfd556 100644 --- a/include/dt-bindings/clock/sun55i-a523-ccu.h +++ b/include/dt-bindings/clock/sun55i-a523-ccu.h @@ -185,5 +185,6 @@ #define CLK_FANOUT0 176 #define CLK_FANOUT1 177 #define CLK_FANOUT2 178 +#define CLK_NPU 179 #endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */ From 0f610e650d4e979490ccfa4c22ca29ca547f41e7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 12 Sep 2025 01:47:05 +0800 Subject: [PATCH 808/931] dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller There are four clock controllers in the A523 SoC. The existing binding already covers two of them that are critical for basic operation. The remaining ones are the MCU clock controller and CPU PLL clock controller. Add a description for the MCU CCU. This unit controls and provides clocks to the MCU (RISC-V) subsystem and peripherals meant to operate under low power conditions. Reviewed-by: Rob Herring (Arm) Link: https://patch.msgid.link/20250911174710.3149589-3-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- .../clock/allwinner,sun55i-a523-ccu.yaml | 37 ++++++++++++- .../dt-bindings/clock/sun55i-a523-mcu-ccu.h | 54 +++++++++++++++++++ .../dt-bindings/reset/sun55i-a523-mcu-ccu.h | 30 +++++++++++ 3 files changed, 119 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/clock/sun55i-a523-mcu-ccu.h create mode 100644 include/dt-bindings/reset/sun55i-a523-mcu-ccu.h diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml index f5f62e9a10a1..58be701a720e 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml @@ -19,6 +19,7 @@ properties: compatible: enum: - allwinner,sun55i-a523-ccu + - allwinner,sun55i-a523-mcu-ccu - allwinner,sun55i-a523-r-ccu reg: @@ -26,11 +27,11 @@ properties: clocks: minItems: 4 - maxItems: 5 + maxItems: 9 clock-names: minItems: 4 - maxItems: 5 + maxItems: 9 required: - "#clock-cells" @@ -63,6 +64,38 @@ allOf: - const: iosc - const: losc-fanout + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-mcu-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (usually at 24MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Audio PLL (4x) + - description: Peripherals PLL 0 (300 MHz output) + - description: DSP module clock + - description: MBUS clock + - description: PRCM AHB clock + - description: PRCM APB0 clock + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: pll-audio0-4x + - const: pll-periph0-300m + - const: dsp + - const: mbus + - const: r-ahb + - const: r-apb0 + - if: properties: compatible: diff --git a/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h b/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h new file mode 100644 index 000000000000..6efc6bc7e11a --- /dev/null +++ b/include/dt-bindings/clock/sun55i-a523-mcu-ccu.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Chen-Yu Tsai + */ + +#ifndef _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ +#define _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ + +#define CLK_MCU_PLL_AUDIO1 0 +#define CLK_MCU_PLL_AUDIO1_DIV2 1 +#define CLK_MCU_PLL_AUDIO1_DIV5 2 +#define CLK_MCU_AUDIO_OUT 3 +#define CLK_MCU_DSP 4 +#define CLK_MCU_I2S0 5 +#define CLK_MCU_I2S1 6 +#define CLK_MCU_I2S2 7 +#define CLK_MCU_I2S3 8 +#define CLK_MCU_I2S3_ASRC 9 +#define CLK_BUS_MCU_I2S0 10 +#define CLK_BUS_MCU_I2S1 11 +#define CLK_BUS_MCU_I2S2 12 +#define CLK_BUS_MCU_I2S3 13 +#define CLK_MCU_SPDIF_TX 14 +#define CLK_MCU_SPDIF_RX 15 +#define CLK_BUS_MCU_SPDIF 16 +#define CLK_MCU_DMIC 17 +#define CLK_BUS_MCU_DMIC 18 +#define CLK_MCU_AUDIO_CODEC_DAC 19 +#define CLK_MCU_AUDIO_CODEC_ADC 20 +#define CLK_BUS_MCU_AUDIO_CODEC 21 +#define CLK_BUS_MCU_DSP_MSGBOX 22 +#define CLK_BUS_MCU_DSP_CFG 23 +#define CLK_BUS_MCU_NPU_HCLK 24 +#define CLK_BUS_MCU_NPU_ACLK 25 +#define CLK_MCU_TIMER0 26 +#define CLK_MCU_TIMER1 27 +#define CLK_MCU_TIMER2 28 +#define CLK_MCU_TIMER3 29 +#define CLK_MCU_TIMER4 30 +#define CLK_MCU_TIMER5 31 +#define CLK_BUS_MCU_TIMER 32 +#define CLK_BUS_MCU_DMA 33 +#define CLK_MCU_TZMA0 34 +#define CLK_MCU_TZMA1 35 +#define CLK_BUS_MCU_PUBSRAM 36 +#define CLK_MCU_MBUS_DMA 37 +#define CLK_MCU_MBUS 38 +#define CLK_MCU_RISCV 39 +#define CLK_BUS_MCU_RISCV_CFG 40 +#define CLK_BUS_MCU_RISCV_MSGBOX 41 +#define CLK_MCU_PWM0 42 +#define CLK_BUS_MCU_PWM0 43 + +#endif /* _DT_BINDINGS_CLK_SUN55I_A523_MCU_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h b/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h new file mode 100644 index 000000000000..a89a0b44f08b --- /dev/null +++ b/include/dt-bindings/reset/sun55i-a523-mcu-ccu.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2025 Chen-Yu Tsai + */ + +#ifndef _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ +#define _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ + +#define RST_BUS_MCU_I2S0 0 +#define RST_BUS_MCU_I2S1 1 +#define RST_BUS_MCU_I2S2 2 +#define RST_BUS_MCU_I2S3 3 +#define RST_BUS_MCU_SPDIF 4 +#define RST_BUS_MCU_DMIC 5 +#define RST_BUS_MCU_AUDIO_CODEC 6 +#define RST_BUS_MCU_DSP_MSGBOX 7 +#define RST_BUS_MCU_DSP_CFG 8 +#define RST_BUS_MCU_NPU 9 +#define RST_BUS_MCU_TIMER 10 +#define RST_BUS_MCU_DSP_DEBUG 11 +#define RST_BUS_MCU_DSP 12 +#define RST_BUS_MCU_DMA 13 +#define RST_BUS_MCU_PUBSRAM 14 +#define RST_BUS_MCU_RISCV_CFG 15 +#define RST_BUS_MCU_RISCV_DEBUG 16 +#define RST_BUS_MCU_RISCV_CORE 17 +#define RST_BUS_MCU_RISCV_MSGBOX 18 +#define RST_BUS_MCU_PWM0 19 + +#endif /* _DT_BINDINGS_RST_SUN55I_A523_MCU_CCU_H_ */ From edd63e54e516b54c0b7071463d6e839445efab68 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 12 Sep 2025 01:47:09 +0800 Subject: [PATCH 809/931] arm64: dts: allwinner: a523: Add MCU PRCM CCU node Add a device node for the third supported clock controller found in the A523 / T527 SoCs. This controller has clocks and resets for the RISC-V MCU, and others peripherals possibly meant to operate in low power mode driven by the MCU, such as audio interfaces, an audio DSP, and the NPU. Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec Link: https://patch.msgid.link/20250911174710.3149589-7-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index 6b6f2296bdff..a5100e5d19aa 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -4,8 +4,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -690,5 +692,30 @@ rtc: rtc@7090000 { clock-names = "bus", "hosc", "ahb"; #clock-cells = <1>; }; + + mcu_ccu: clock-controller@7102000 { + compatible = "allwinner,sun55i-a523-mcu-ccu"; + reg = <0x7102000 0x200>; + clocks = <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, + <&ccu CLK_PLL_AUDIO0_4X>, + <&ccu CLK_PLL_PERIPH0_300M>, + <&ccu CLK_DSP>, + <&ccu CLK_MBUS>, + <&r_ccu CLK_R_AHB>, + <&r_ccu CLK_R_APB0>; + clock-names = "hosc", + "losc", + "iosc", + "pll-audio0-4x", + "pll-periph0-300m", + "dsp", + "mbus", + "r-ahb", + "r-apb0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; }; From a1845487afd06899502714a3500b60f815d98203 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 12 Sep 2025 01:47:10 +0800 Subject: [PATCH 810/931] arm64: dts: allwinner: a523: Add NPU device node The Allwinner T527 SoC has an NPU built in. Based on identifiers found in the BSP, it is a Vivante IP block. After enabling it, the etnaviv driver reports it as a GC9000 revision 9003. The standard bindings are used as everything matches directly. There is no option for DVFS at the moment. That might require some more work, perhaps on the efuse side to map speed bins. It is unclear whether the NPU block is fused out at the hardware level or the BSP limits use of the NPU through software, as the author only has boards with the T527. Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec Link: https://patch.msgid.link/20250911174710.3149589-8-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index a5100e5d19aa..d00da1cd744e 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -717,5 +717,17 @@ mcu_ccu: clock-controller@7102000 { #clock-cells = <1>; #reset-cells = <1>; }; + + npu: npu@7122000 { + compatible = "vivante,gc"; + reg = <0x07122000 0x1000>; + interrupts = ; + clocks = <&mcu_ccu CLK_BUS_MCU_NPU_ACLK>, + <&ccu CLK_NPU>, + <&mcu_ccu CLK_BUS_MCU_NPU_HCLK>; + clock-names = "bus", "core", "reg"; + resets = <&mcu_ccu RST_BUS_MCU_NPU>; + power-domains = <&ppu PD_NPU>; + }; }; }; From 3173a760021b9340923831aa5edc5530d61a6b9b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=2E=20Neusch=C3=A4fer?= Date: Thu, 11 Sep 2025 22:23:55 +0200 Subject: [PATCH 811/931] ARM: dts: allwinner: orangepi-zero: Add default audio routing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Line out playback and microphone capture work, after enabling the corresponding ALSA controls. Tested with the Orange Pi Zero interface board. Signed-off-by: J. Neuschäfer Link: https://patch.msgid.link/20250911-opz-audio-v3-1-9dfd317a8163@posteo.net Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun8i-h2-plus-orangepi-zero.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts index 1b001f2ad0ef..b23cec5b89eb 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts @@ -112,6 +112,20 @@ wifi_pwrseq: pwrseq { }; }; +/* + * Audio input/output is exposed on the 13-pin header and can't be used for + * anything else. However, adapter boards may use different audio routing. + * - https://linux-sunxi.org/Xunlong_Orange_Pi_Zero#Expansion_Port + * - Allwinner H3 Datasheet, section 3.1. Pin Characteristics + */ +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "disabled"; +}; + &cpu0 { cpu-supply = <®_vdd_cpux>; }; From fd5c7bf8ddb51373a6c9456865b3af99f53642a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=2E=20Neusch=C3=A4fer?= Date: Thu, 11 Sep 2025 22:23:56 +0200 Subject: [PATCH 812/931] ARM: dts: allwinner: orangepi-zero-plus2: Add default audio routing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Orange Pi Zero Plus 2 has the same pinout[1] as the Orange Pi Zero[2] (with the possible exception of line-out left/right being swapped), and the Orange Pi Zero Interface Board is sold[3] as compatible with both of them. We can thus use the same audio routing. [1]: http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-Zero-Plus-2.html [2]: https://linux-sunxi.org/Xunlong_Orange_Pi_Zero#Expansion_Port [3]: https://orangepi.com/index.php?route=product/product&product_id=871 Signed-off-by: J. Neuschäfer Link: https://patch.msgid.link/20250911-opz-audio-v3-2-9dfd317a8163@posteo.net Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts index 7a6444a10e25..97a3565ac7a8 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts @@ -99,6 +99,20 @@ wifi_pwrseq: pwrseq { }; }; +/* + * Audio input/output is exposed on the 13-pin header and can't be used for + * anything else. However, adapter boards may use different audio routing. + * - http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-Zero-Plus-2.html + * - Allwinner H3 Datasheet, section 3.1. Pin Characteristics + */ +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "disabled"; +}; + &de { status = "okay"; }; From b65ee02e77cb14486cf30709e978430e91f74d2e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=2E=20Neusch=C3=A4fer?= Date: Thu, 11 Sep 2025 22:23:57 +0200 Subject: [PATCH 813/931] ARM: dts: allwinner: Add Orange Pi Zero Interface Board overlay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Orange Pi Zero interface board is a (mostly) passive adapter from the 13-pin header of the Orange Pi Zero and Orange Pi Zero Plus2 to standard connectors (2x USB A, 1x Audio/Video output, 1x built-in microphone, 1x infrared input). Headphones, microphone, infrared (CIR) input, and USB have been tested with the Orange Pi Zero. CVBS output is currently not supported. https://orangepi.com/index.php?route=product/product&product_id=871 Signed-off-by: J. Neuschäfer Link: https://patch.msgid.link/20250911-opz-audio-v3-3-9dfd317a8163@posteo.net Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/Makefile | 7 +++ .../sun8i-orangepi-zero-interface-board.dtso | 46 +++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-orangepi-zero-interface-board.dtso diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index d799ad153b37..97d0a205493f 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -182,6 +182,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-wits-pro-a20-dkt.dtb # Enables support for device-tree overlays for all pis +DTC_FLAGS_sun8i-h2-plus-orangepi-zero := -@ DTC_FLAGS_sun8i-h3-orangepi-lite := -@ DTC_FLAGS_sun8i-h3-bananapi-m2-plus := -@ DTC_FLAGS_sun8i-h3-nanopi-m1-plus := -@ @@ -225,6 +226,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h2-plus-libretech-all-h3-cc.dtb \ sun8i-h2-plus-orangepi-r1.dtb \ sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h2-plus-orangepi-zero-interface-board.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ sun8i-h3-bananapi-m2-plus-v1.2.dtb \ sun8i-h3-beelink-x2.dtb \ @@ -244,6 +246,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-plus.dtb \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-h3-orangepi-zero-plus2.dtb \ + sun8i-h3-orangepi-zero-plus2-interface-board.dtb \ sun8i-h3-rervision-dvk.dtb \ sun8i-h3-zeropi.dtb \ sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ @@ -264,6 +267,10 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-v3s-licheepi-zero-dock.dtb \ sun8i-v3s-netcube-kumquat.dtb \ sun8i-v40-bananapi-m2-berry.dtb +sun8i-h2-plus-orangepi-zero-interface-board-dtbs += \ + sun8i-h2-plus-orangepi-zero.dtb sun8i-orangepi-zero-interface-board.dtbo +sun8i-h3-orangepi-zero-plus2-interface-board-dtbs += \ + sun8i-h3-orangepi-zero-plus2.dtb sun8i-orangepi-zero-interface-board.dtbo dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/boot/dts/allwinner/sun8i-orangepi-zero-interface-board.dtso b/arch/arm/boot/dts/allwinner/sun8i-orangepi-zero-interface-board.dtso new file mode 100644 index 000000000000..e137eefee341 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-orangepi-zero-interface-board.dtso @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright (C) 2025 J. Neuschäfer + * + * Devicetree overlay for the Orange Pi Zero Interface board (OP0014). + * + * https://orangepi.com/index.php?route=product/product&product_id=871 + * + * This overlay applies to the following base files: + * + * - arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts + * - arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts + */ + +/dts-v1/; +/plugin/; + +&codec { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; From db5796c5c5c6db72339e818b54e6a2e043f7032c Mon Sep 17 00:00:00 2001 From: Lukas Schmid Date: Sun, 31 Aug 2025 18:25:30 +0200 Subject: [PATCH 814/931] dt-bindings: arm: sunxi: Add NetCube Systems Nagami SoM and carrier board bindings The NetCube Systems Nagami is an System on Module base on the Allwinner T113s SoC. It is intended to be used in low cost devices which require simple layouts and low BOM cost. The NetCube Systems Nagami Basic Carrier Board is a simple carrier for the Nagami SoM. It is intended to serve as a simple reference design for a custom implementation or just evaluating the module with other peripherals The NetCube Systems Nagami Keypad Carrier is a custom board intended to fit a standard Ritto Intercom enclosure and provides a Keypad, NFC-Reader and Status-LED all controllable over Ethernet with PoE support. Signed-off-by: Lukas Schmid Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250831162536.2380589-2-lukas.schmid@netcube.li Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/sunxi.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index c25a22fe4d25..72ef861a0b68 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -595,6 +595,14 @@ properties: - const: netcube,kumquat - const: allwinner,sun8i-v3s + - description: NetCube Systems Nagami SoM based boards + items: + - enum: + - netcube,nagami-basic-carrier + - netcube,nagami-keypad-carrier + - const: netcube,nagami + - const: allwinner,sun8i-t113s + - description: NextThing Co. CHIP items: - const: nextthing,chip From cbce6d5326b116f55dc29f7fc0a7d56a9a03d9e5 Mon Sep 17 00:00:00 2001 From: Lukas Schmid Date: Sun, 31 Aug 2025 18:25:31 +0200 Subject: [PATCH 815/931] riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM Added the following pinctrl's used by the NetCube Systems Nagami SoM * i2c2_pins * i2c3_pins * i2s1_pins, i2s1_din_pins, i2s1_dout_pins * spi1_pins, spi1_hold_pin, spi1_wp_pin Signed-off-by: Lukas Schmid Link: https://patch.msgid.link/20250831162536.2380589-3-lukas.schmid@netcube.li [wens@csie.org: Fix up node names and labels for i2c* and i2s1_d* pins] Signed-off-by: Chen-Yu Tsai --- .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index e4175adb028d..63e252b44973 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -78,6 +78,36 @@ dsi_4lane_pins: dsi-4lane-pins { function = "dsi"; }; + /omit-if-no-ref/ + i2c2_pd_pins: i2c2-pd-pins { + pins = "PD20", "PD21"; + function = "i2c2"; + }; + + /omit-if-no-ref/ + i2c3_pg_pins: i2c3-pg-pins { + pins = "PG10", "PG11"; + function = "i2c3"; + }; + + /omit-if-no-ref/ + i2s1_pins: i2s1-pins { + pins = "PG12", "PG13"; + function = "i2s1"; + }; + + /omit-if-no-ref/ + i2s1_din0_pin: i2s1-din0-pin { + pins = "PG14"; + function = "i2s1_din"; + }; + + /omit-if-no-ref/ + i2s1_dout0_pin: i2s1-dout0-pin { + pins = "PG15"; + function = "i2s1_dout"; + }; + /omit-if-no-ref/ lcd_rgb666_pins: lcd-rgb666-pins { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", @@ -126,6 +156,24 @@ spi0_pins: spi0-pins { function = "spi0"; }; + /omit-if-no-ref/ + spi1_pins: spi1-pins { + pins = "PD10", "PD11", "PD12", "PD13"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_hold_pin: spi1-hold-pin { + pins = "PD14"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_wp_pin: spi1-wp-pin { + pins = "PD15"; + function = "spi1"; + }; + /omit-if-no-ref/ uart1_pg6_pins: uart1-pg6-pins { pins = "PG6", "PG7"; From cba2febbd6465aabdff157fb95b1c07d090af1f0 Mon Sep 17 00:00:00 2001 From: Lukas Schmid Date: Sun, 31 Aug 2025 18:25:32 +0200 Subject: [PATCH 816/931] ARM: dts: sunxi: add support for NetCube Systems Nagami SoM NetCube Systems Nagami SoM is a module based around the Allwinner T113s SoC. It includes the following features and interfaces: - 128MB DDR3 included in SoC - 10/100 Mbps Ethernet using LAN8720A phy - One USB-OTG interface - One USB-Host interface - One I2S interface with in and output support - Two CAN interfaces - ESP32 over SDIO - One SPI interface - I2C EEPROM for MAC address - One QWIIC I2C Interface with dedicated interrupt pin shared with EEPROM - One external I2C interface - SD interface for external SD-Card Signed-off-by: Lukas Schmid Link: https://patch.msgid.link/20250831162536.2380589-4-lukas.schmid@netcube.li [wens@csie.org: fix up pinctrl names for i2c* and i2s_d*; fix indentation for gpio-line-names and rmii_pe_pins; fix "pre-magnetics" typo in comment] Signed-off-by: Chen-Yu Tsai --- .../allwinner/sun8i-t113s-netcube-nagami.dtsi | 250 ++++++++++++++++++ 1 file changed, 250 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi new file mode 100644 index 000000000000..544d60cfc32e --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Lukas Schmid + */ + +/dts-v1/; +#include "sun8i-t113s.dtsi" + +#include +#include + +/ { + model = "NetCube Systems Nagami SoM"; + compatible = "netcube,nagami", "allwinner,sun8i-t113s"; + + aliases { + serial1 = &uart1; // ESP32 Bootloader UART + serial3 = &uart3; // Console UART on Card Edge + ethernet0 = &emac; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + /* module wide 3.3V supply directly from the card edge */ + reg_vcc3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */ + reg_vcc_core: regulator-core { + compatible = "regulator-fixed"; + regulator-name = "vcc-core"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + vin-supply = <®_vcc3v3>; + }; + + /* USB0 MUX to switch connect to Card-Edge only after BootROM */ + usb0_sec_mux: mux-controller{ + compatible = "gpio-mux"; + #mux-control-cells = <0>; + mux-gpios = <&pio 3 9 GPIO_ACTIVE_HIGH>; /* PD9 */ + idle-state = <1>; /* USB connected to Card-Edge by default */ + }; + + /* Reset of ESP32 */ + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>; /* PG9 */ + post-power-on-delay-ms = <1500>; + power-off-delay-us = <200>; + }; +}; + +&cpu0 { + cpu-supply = <®_vcc_core>; +}; + +&cpu1 { + cpu-supply = <®_vcc_core>; +}; + +&dcxo { + clock-frequency = <24000000>; +}; + +&emac { + nvmem-cells = <ð0_macaddress>; + nvmem-cell-names = "mac-address"; + phy-handle = <&lan8720a>; + phy-mode = "rmii"; + pinctrl-0 = <&rmii_pe_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Default I2C Interface on Card-Edge */ +&i2c2 { + pinctrl-0 = <&i2c2_pd_pins>; + pinctrl-names = "default"; + status = "disabled"; +}; + +/* Exposed as the QWIIC connector and used by the internal EEPROM */ +&i2c3 { + pinctrl-0 = <&i2c3_pg_pins>; + pinctrl-names = "default"; + status = "okay"; + + eeprom0: eeprom@50 { + compatible = "atmel,24c02"; /* actually it's a 24AA02E48 */ + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <®_vcc3v3>; + + #address-cells = <1>; + #size-cells = <1>; + + eth0_macaddress: macaddress@fa { + reg = <0xfa 0x06>; + }; + }; +}; + +/* Default I2S Interface on Card-Edge */ +&i2s1 { + pinctrl-0 = <&i2s1_pins>, <&i2s1_din0_pin>, <&i2s1_dout0_pin>; + pinctrl-names = "default"; + status = "disabled"; +}; + +/* Phy is on SoM. MDI signals pre-magnetics are on the card edge */ +&mdio { + lan8720a: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +/* Default SD Interface on Card-Edge */ +&mmc0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + status = "disabled"; +}; + +/* Connected to the on-board ESP32 */ +&mmc1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&wifi_pwrseq>; + status = "okay"; +}; + +/* Connected to the on-board eMMC */ +&mmc2 { + pinctrl-0 = <&mmc2_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pd-supply = <®_vcc3v3>; + vcc-pe-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + + gpio-line-names = "", "", "", "", // PA + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "CAN0_TX", "CAN0_RX", // PB + "CAN1_TX", "CAN1_RX", "UART3_TX", "UART3_RX", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "eMMC_CLK", "eMMC_CMD", // PC + "eMMC_D2", "eMMC_D1", "eMMC_D0", "eMMC_D3", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", // PD + "", "", "", "", + "", "USB_SEC_EN", "SPI1_CS", "SPI1_CLK", + "SPI1_MOSI", "SPI1_MISO", "SPI1_HOLD", "SPI1_WP", + "PD16", "", "", "", + "I2C2_SCL", "I2C2_SDA", "PD22", "", + "", "", "", "", + "", "", "", "", + "ETH_CRSDV", "ETH_RXD0", "ETH_RXD1", "ETH_TXCK", // PE + "ETH_TXD0", "ETH_TXD1", "ETH_TXEN", "", + "ETH_MDC", "ETH_MDIO", "QWIIC_nINT", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "SD_D1", "SD_D0", "SD_CLK", "SD_CLK", // PF + "SD_D3", "SD_D2", "PF6", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "ESP_CLK", "ESP_CMD", "ESP_D0", "ESP_D1", // PG + "ESP_D2", "ESP_D3", "UART1_TXD", "UART1_RXD", + "ESP_nBOOT", "ESP_nRST", "I2C3_SCL", "I2C3_SDA", + "I2S1_WS", "I2S1_CLK", "I2S1_DIN0", "I2S1_DOUT0", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* Remove the unused CK pin from the pinctl as it is unconnected */ +&rmii_pe_pins { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE8", "PE9"; +}; + +/* Default SPI Interface on Card-Edge */ +&spi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&spi1_pins>, <&spi1_hold_pin>, <&spi1_wp_pin>; + pinctrl-names = "default"; + cs-gpios = <0>; + status = "disabled"; +}; + +/* Connected to the Bootloader/Console of the ESP32 */ +&uart1 { + pinctrl-0 = <&uart1_pg6_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Console/Debug UART on Card-Edge */ +&uart3 { + pinctrl-0 = <&uart3_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; From e36d4d54eefb60144666b27754007e1c0dd0a581 Mon Sep 17 00:00:00 2001 From: Lukas Schmid Date: Sun, 31 Aug 2025 18:25:33 +0200 Subject: [PATCH 817/931] ARM: dts: sunxi: add support for NetCube Systems Nagami Basic Carrier The NetCube Systems Nagami Basic Carrier is a Carrier for the Nagami SoM It provides an ethernet port for the phy on the SoM and some USB-Ports. All other interfaces and gpios are available on pinheader, except for the SD-Interface which is available on a micro-sd slot. Signed-off-by: Lukas Schmid Link: https://patch.msgid.link/20250831162536.2380589-5-lukas.schmid@netcube.li [wens@csie.org: fix indentation for board level compatible string fallback] Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/Makefile | 2 + ...n8i-t113s-netcube-nagami-basic-carrier.dts | 67 +++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-basic-carrier.dts diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index 97d0a205493f..865fd8c9d137 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -200,6 +200,7 @@ DTC_FLAGS_sun8i-h3-nanopi-r1 := -@ DTC_FLAGS_sun8i-h3-orangepi-pc := -@ DTC_FLAGS_sun8i-h3-bananapi-m2-plus-v1.2 := -@ DTC_FLAGS_sun8i-h3-orangepi-pc-plus := -@ +DTC_FLAGS_sun8i-t113s-netcube-nagami-basic-carrier := -@ DTC_FLAGS_sun8i-v3s-netcube-kumquat := -@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a23-evb.dtb \ @@ -260,6 +261,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-s3-lichee-zero-plus.dtb \ sun8i-s3-pinecube.dtb \ sun8i-t113s-mangopi-mq-r-t113.dtb \ + sun8i-t113s-netcube-nagami-basic-carrier.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ sun8i-v3s-anbernic-rg-nano.dtb \ diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-basic-carrier.dts b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-basic-carrier.dts new file mode 100644 index 000000000000..5262102a85f6 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-basic-carrier.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Lukas Schmid + */ + +/dts-v1/; +#include "sun8i-t113s-netcube-nagami.dtsi" + +/ { + model = "NetCube Systems Nagami Basic Carrier Board"; + compatible = "netcube,nagami-basic-carrier", "netcube,nagami", + "allwinner,sun8i-t113s"; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2s1 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + broken-cd; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + status = "okay"; +}; From caffed0800ef4dd29cc29ee17a89d015e867e03a Mon Sep 17 00:00:00 2001 From: Lukas Schmid Date: Sun, 31 Aug 2025 18:25:34 +0200 Subject: [PATCH 818/931] ARM: dts: sunxi: add support for NetCube Systems Nagami Keypad Carrier The NetCube Systems Nagami Keypad Carrier uses the Nagami SoM and contains a TCA8418 connected to a 4x4 matrix keypad. The I2C2 interface is connected to said TCA8418 and also a header for an PN532 NFC-Module. It also provides a pin-header for a bi-color status led. Ethernet with PoE support is available on a screwterminal after magnetics. Signed-off-by: Lukas Schmid Link: https://patch.msgid.link/20250831162536.2380589-6-lukas.schmid@netcube.li [wens@csie.org: fix indentation for board level compatible fallback, gpio-line-names and keypad matrix.] Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/Makefile | 1 + ...8i-t113s-netcube-nagami-keypad-carrier.dts | 129 ++++++++++++++++++ 2 files changed, 130 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-keypad-carrier.dts diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index 865fd8c9d137..f71392a55df8 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -262,6 +262,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-s3-pinecube.dtb \ sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t113s-netcube-nagami-basic-carrier.dtb \ + sun8i-t113s-netcube-nagami-keypad-carrier.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ sun8i-v3s-anbernic-rg-nano.dtb \ diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-keypad-carrier.dts b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-keypad-carrier.dts new file mode 100644 index 000000000000..4ffa6a0216d8 --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami-keypad-carrier.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Lukas Schmid + */ + +/dts-v1/; +#include "sun8i-t113s-netcube-nagami.dtsi" + +#include +#include + +/ { + model = "NetCube Systems Nagami Keypad Carrier Board"; + compatible = "netcube,nagami-keypad-carrier", "netcube,nagami", + "allwinner,sun8i-t113s"; + + leds { + compatible = "gpio-leds"; + + led_status_red: led-status-red { + gpios = <&pio 3 16 GPIO_ACTIVE_HIGH>; /* PD16 */ + color = ; + function = LED_FUNCTION_STATUS; + }; + + led_status_green: led-status-green { + gpios = <&pio 3 22 GPIO_ACTIVE_HIGH>; /* PD22 */ + color = ; + function = LED_FUNCTION_STATUS; + }; + }; +}; + +&i2c2 { + status = "okay"; + + tca8418: keypad@34 { + compatible = "ti,tca8418"; + reg = <0x34>; + interrupts-extended = <&pio 5 6 IRQ_TYPE_EDGE_FALLING>; /* PF6 */ + linux,keymap = ; + keypad,num-rows = <4>; + keypad,num-columns = <4>; + }; +}; + +&pio { + gpio-line-names = "", "", "", "", // PA + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", // PB + "", "", "UART3_TX", "UART3_RX", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "eMMC_CLK", "eMMC_CMD", // PC + "eMMC_D2", "eMMC_D1", "eMMC_D0", "eMMC_D3", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", // PD + "", "", "", "", + "", "USB_SEC_EN", "", "", + "", "", "", "", + "LED_STATUS_RED", "", "", "", + "I2C2_SCL", "I2C2_SDA", "LED_STATUS_GREEN", "", + "", "", "", "", + "", "", "", "", + "ETH_CRSDV", "ETH_RXD0", "ETH_RXD1", "ETH_TXCK", // PE + "ETH_TXD0", "ETH_TXD1", "ETH_TXEN", "", + "ETH_MDC", "ETH_MDIO", "QWIIC_nINT", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", // PF + "", "", "KEY_nINT", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "ESP_CLK", "ESP_CMD", "ESP_D0", "ESP_D1", // PG + "ESP_D2", "ESP_D3", "UART1_TXD", "UART1_RXD", + "ESP_nBOOT", "ESP_nRST", "I2C3_SCL", "I2C3_SDA", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; From 2a222aa2bee9e56fc1082c2fad1a92138b5bea4c Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Thu, 11 Sep 2025 12:20:04 +0300 Subject: [PATCH 819/931] arm64: dts: add description for solidrun imx8mp hummingboard variants Add descriptions for the SolidRun i.MX8M Plus System on Module based HummingBoard product-line. They share a common designed based on the "Pulse" version, defined by various assembly options. The HummingBoard Pulse features: - 2x RJ45 Ethernet - 2x USB-3.0 Type A - HDMI connector - mini-HDMI connector - microSD connector - mini-PCI-E connector with SIM slot supporting USB-2.0/3.0 interfaces - M.2 connector with SIM slot supporting USB-2.0/3.0 interfaces - MIPI-CSI Camera Connector (not described without specific camera) - 3.5mm Analog Stereo Out / Microphone In Headphone Jack - RTC with backup battery The variants Mate and Ripple are reduced versions of Pulse. The HummingBoard Pro extends Pulse with PCI-E on M.2 connector. Signed-off-by: Josua Mayer Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 4 + .../freescale/imx8mp-hummingboard-mate.dts | 31 ++ .../dts/freescale/imx8mp-hummingboard-pro.dts | 76 ++++ .../imx8mp-hummingboard-pulse-codec.dtsi | 59 +++ .../imx8mp-hummingboard-pulse-common.dtsi | 384 ++++++++++++++++++ .../imx8mp-hummingboard-pulse-hdmi.dtsi | 44 ++ .../imx8mp-hummingboard-pulse-m2con.dtsi | 60 +++ .../imx8mp-hummingboard-pulse-mini-hdmi.dtsi | 81 ++++ .../freescale/imx8mp-hummingboard-pulse.dts | 83 ++++ .../freescale/imx8mp-hummingboard-ripple.dts | 31 ++ 10 files changed, 853 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 86050b50d704..525ef180481d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -206,6 +206,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-ripple.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-iota2-lumpy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-bl-osm-s.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts new file mode 100644 index 000000000000..00614f5d58ea --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + */ + +/dts-v1/; + +#include "imx8mp-sr-som.dtsi" +#include "imx8mp-hummingboard-pulse-common.dtsi" +#include "imx8mp-hummingboard-pulse-hdmi.dtsi" + +/ { + model = "SolidRun i.MX8MP HummingBoard Mate"; + compatible = "solidrun,imx8mp-hummingboard-mate", + "solidrun,imx8mp-sr-som", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + /delete-property/ ethernet1; + }; +}; + +&fec { + /* this board does not use second phy / ethernet on SoM */ + status = "disabled"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&mikro_rst_pins>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts new file mode 100644 index 000000000000..36cd452f1583 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + */ + +/dts-v1/; + +#include + +#include "imx8mp-sr-som.dtsi" +#include "imx8mp-hummingboard-pulse-codec.dtsi" +#include "imx8mp-hummingboard-pulse-common.dtsi" +#include "imx8mp-hummingboard-pulse-hdmi.dtsi" +#include "imx8mp-hummingboard-pulse-m2con.dtsi" +#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi" + +/ { + model = "SolidRun i.MX8MP HummingBoard Pro"; + compatible = "solidrun,imx8mp-hummingboard-pro", + "solidrun,imx8mp-sr-som", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&hdmi_pins>, + <&m2_wwan_wake_pins>; +}; + +&pcie { + pinctrl-0 = <&m2_reset_pins>; + pinctrl-names = "default"; + reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_phy { + clocks = <&hsio_blk_ctrl>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&phy0 { + leds { + /* ADIN1300 LED_0 pin */ + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + /delete-node/ led@1; + }; +}; + +&phy1 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + /* ADIN1300 LED_0 pin */ + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi new file mode 100644 index 000000000000..77402a3db9ef --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + */ + +/ { + sound-wm8904 { + compatible = "fsl,imx-audio-wm8904"; + model = "audio-wm8904"; + audio-cpu = <&sai3>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "AMIC", "MICBIAS", + "IN2R", "AMIC"; + }; +}; + +&i2c2 { + codec: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + clock-names = "mclk"; + AVDD-supply = <&v_1_8>; + CPVDD-supply = <&v_1_8>; + DBVDD-supply = <&v_3_3>; + DCVDD-supply = <&v_1_8>; + MICVDD-supply = <&v_3_3>; + }; +}; + +&iomuxc { + sai3_pins: pinctrl-sai3-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + >; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&sai3_pins>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi new file mode 100644 index 000000000000..825ad6a2ba14 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + */ + +#include + +/ { + aliases { + rtc0 = &carrier_rtc; + rtc1 = &snvs_rtc; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led-0 { + label = "D30"; + color = ; + gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-1 { + label = "D31"; + color = ; + gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-2 { + label = "D32"; + color = ; + gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-3 { + label = "D33"; + color = ; + gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-4 { + label = "D34"; + color = ; + gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + rfkill-mpcie-wifi { + /* + * The mpcie connector only has USB, + * therefore this rfkill is for cellular radios only. + */ + compatible = "rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&mpcie_rfkill_pins>; + label = "mpcie radio"; + radio-type = "wwan"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; + + vmmc: regulator-mmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&vmmc_pins>; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + startup-delay-us = <250>; + }; + + vbus1: regulator-vbus-1 { + compatible = "regulator-fixed"; + regulator-name = "vbus1"; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vbus1_pins>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vbus2: regulator-vbus-2 { + compatible = "regulator-fixed"; + regulator-name = "vbus2"; + gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vbus2_pins>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + v_1_2: regulator-1-2 { + compatible = "regulator-fixed"; + regulator-name = "1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vmpcie { + /* supplies mpcie and m2 connectors */ + compatible = "regulator-fixed"; + regulator-name = "vmpcie"; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vmpcie_pins>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +/* mikrobus spi */ +&ecspi2 { + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&mikro_spi_pins>; + status = "okay"; +}; + +&gpio1 { + pinctrl-0 = <&mpcie_reset_pins>; + pinctrl-names = "default"; + + mpcie-reset-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + output-low; + line-name = "mpcie-reset"; + }; +}; + +&i2c3 { + carrier_eeprom: eeprom@57{ + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; + + carrier_rtc: rtc@69 { + compatible = "abracon,ab1805"; + reg = <0x69>; + abracon,tc-diode = "schottky"; + abracon,tc-resistor = <3>; + }; +}; + +&iomuxc { + csi_pins: pinctrl-csi-grp { + fsl,pins = < + /* Pin 24: STROBE */ + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x0 + >; + }; + + led_pins: pinctrl-led-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x0 + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0 + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x0 + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x0 + MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x0 + >; + }; + + mikro_int_pins: pinctrl-mikro-int-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x0 + >; + }; + + mikro_pwm_pins: pinctrl-mikro-pwm-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x0 + >; + }; + + mikro_rst_pins: pinctrl-mikro-rst-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x0 + >; + }; + + mikro_spi_pins: pinctrl-mikro-spi-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x40000 + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + >; + }; + + mikro_uart_pins: pinctrl-mikro-uart-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + >; + }; + + mpcie_reset_pins: pinctrl-mpcie-reset-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x0 + >; + }; + + mpcie_rfkill_pins: pinctrl-pcie-rfkill-grp { + fsl,pins = < + /* weak i/o, open drain */ + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x20 + >; + }; + + usb_hub_pins: pinctrl-usb-hub-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x0 + >; + }; + + usdhc2_pins: pinctrl-usdhc2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140 + MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140 + >; + }; + + vbus1_pins: pinctrl-vbus-1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x20 + >; + }; + + vbus2_pins: pinctrl-vbus-2-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x20 + >; + }; + + vmmc_pins: pinctrl-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + vmpcie_pins: pinctrl-vmpcie-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x0 + >; + }; +}; + +&phy0 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + /* ADIN1300 LED_0 pin */ + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + /* ADIN1300 LINK_ST pin */ + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* mikrobus uart */ +&uart3 { + status = "okay"; +}; + +&usb3_phy0 { + fsl,phy-tx-preemp-amp-tune-microamp = <1200>; + vbus-supply = <&vbus2>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <&vbus1>; + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_hub_pins>; + + hub_2_0: hub@1 { + compatible = "usb4b4,6502", "usb4b4,6506"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + vdd-supply = <&v_1_2>; + vdd2-supply = <&v_3_3>; + }; + + hub_3_0: hub@2 { + compatible = "usb4b4,6500", "usb4b4,6504"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + vdd-supply = <&v_1_2>; + vdd2-supply = <&v_3_3>; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&usdhc2_pins>; + pinctrl-1 = <&usdhc2_100mhz_pins>; + pinctrl-2 = <&usdhc2_200mhz_pins>; + vmmc-supply = <&vmmc>; + bus-width = <4>; + cap-power-off-card; + full-pwr-cycle; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi new file mode 100644 index 000000000000..d7a999c0d7e0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + */ + +/ { + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; +}; + +&aud2htx { + status = "okay"; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&iomuxc { + hdmi_pins: pinctrl-hdmi-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154 + >; + }; +}; + +&lcdif3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi new file mode 100644 index 000000000000..8d8d8d2e3da8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + */ + +/ { + rfkill-m2-gnss { + compatible = "rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&m2_gnss_rfkill_pins>; + label = "m.2 GNSS"; + radio-type = "gps"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + + /* M.2 is B-keyed, so w-disable is for WWAN */ + rfkill-m2-wwan { + compatible = "rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&m2_wwan_rfkill_pins>; + label = "m.2 WWAN"; + radio-type = "wwan"; + /* rfkill-gpio inverts internally */ + shutdown-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&iomuxc { + m2_gnss_rfkill_pins: pinctrl-m2-gnss-rfkill-grp { + fsl,pins = < + /* weak i/o, open drain */ + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x20 + >; + }; + + m2_reset_pins: pinctrl-m2-reset-grp { + fsl,pins = < + /* + * 3.3V domain on SoC, set open-drain to ensure + * 1.8V logic on connector + */ + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x20 + >; + }; + + m2_wwan_rfkill_pins: pinctrl-m2-wwan-rfkill-grp { + fsl,pins = < + /* weak i/o, open drain */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x20 + >; + }; + + m2_wwan_wake_pins: pinctrl-m2-wwan-wake-grp { + fsl,pins = < + /* weak i/o, open drain */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x20 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi new file mode 100644 index 000000000000..46916ddc0533 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + */ + +/ { + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "c"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; +}; + +&i2c3 { + hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3f>, <0x3c>, <0x38>; + reg-names = "main", "edid", "cec", "packet"; + adi,dsi-lanes = <4>; + avdd-supply = <&v_1_8>; + dvdd-supply = <&v_1_8>; + pvdd-supply = <&v_1_8>; + a2vdd-supply = <&v_1_8>; + v3p3-supply = <&v_3_3>; + pinctrl-names = "default"; + pinctrl-0 = <&mini_hdmi_pins>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + + port@1 { + reg = <1>; + + adv7535_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&iomuxc { + mini_hdmi_pins: pinctrl-mini-hdmi-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x0 + >; + }; +}; + +&lcdif1 { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + attach-bridge; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts new file mode 100644 index 000000000000..d32844c3af05 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + */ + +/dts-v1/; + +#include + +#include "imx8mp-sr-som.dtsi" +#include "imx8mp-hummingboard-pulse-codec.dtsi" +#include "imx8mp-hummingboard-pulse-common.dtsi" +#include "imx8mp-hummingboard-pulse-hdmi.dtsi" +#include "imx8mp-hummingboard-pulse-m2con.dtsi" +#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi" + +/ { + model = "SolidRun i.MX8MP HummingBoard Pulse"; + compatible = "solidrun,imx8mp-hummingboard-pulse", + "solidrun,imx8mp-sr-som", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &pcie_eth; + }; +}; + +&fec { + /* this board does not use second phy / ethernet on SoM */ + status = "disabled"; +}; + +&gpio1 { + pinctrl-0 = <&mpcie_reset_pins>, <&m2_reset_pins>; + pinctrl-names = "default"; + + m2-reset-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "m2-reset"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&hdmi_pins>, + <&m2_wwan_wake_pins>; + + pcie_eth_pins: pinctrl-pcie-eth-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x0 + >; + }; +}; + +&pcie { + pinctrl-0 = <&pcie_eth_pins>; + pinctrl-names = "default"; + reset-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>; + status = "okay"; + + root@0,0 { + compatible = "pci16c3,abcd"; + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + /* Intel i210 */ + pcie_eth: ethernet@1,0 { + compatible = "pci8086,157b"; + reg = <0x00010000 0 0 0 0>; + }; + }; +}; + +&pcie_phy { + clocks = <&hsio_blk_ctrl>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts new file mode 100644 index 000000000000..4ce5b799b6ab --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 Josua Mayer + */ + +/dts-v1/; + +#include "imx8mp-sr-som.dtsi" +#include "imx8mp-hummingboard-pulse-common.dtsi" +#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi" + +/ { + model = "SolidRun i.MX8MP HummingBoard Ripple"; + compatible = "solidrun,imx8mp-hummingboard-ripple", + "solidrun,imx8mp-sr-som", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + /delete-property/ ethernet1; + }; +}; + +&fec { + /* this board does not use second phy / ethernet on SoM */ + status = "disabled"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&mikro_rst_pins>; +}; From dc8662956496d2bfeee95eca3cf57d7b9a8f2ba4 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 12 Sep 2025 18:03:22 +0300 Subject: [PATCH 820/931] arm64: dts: s32g: Add device tree information for the OCOTP driver Add the device tree information for the S32G On Chip One-Time Programmable Controller (OCOTP) chip. Signed-off-by: Dan Carpenter Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 3ff3b2ff09be..d167624d1f0c 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -325,6 +325,13 @@ usdhc0-200mhz-grp4 { }; }; + ocotp: nvmem@400a4000 { + compatible = "nxp,s32g2-ocotp"; + reg = <0x400a4000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; + swt0: watchdog@40100000 { compatible = "nxp,s32g2-swt"; reg = <0x40100000 0x1000>; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 6292ae99883a..be3a582ebc1b 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -383,6 +383,13 @@ usdhc0-200mhz-grp4 { }; }; + ocotp: nvmem@400a4000 { + compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp"; + reg = <0x400a4000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + }; + swt0: watchdog@40100000 { compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; reg = <0x40100000 0x1000>; From e6fad4960fc67b7225255b10b080765b451a7bc7 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 13 Sep 2025 18:16:00 +0800 Subject: [PATCH 821/931] arm64: dts: sun55i: a523: Assign standard clock rates to PRCM bus clocks At least in the initial version of U-boot support landed upstream, the PRCM bus clocks were not configured, and left at their reset default 24 MHz clock rate. This is quite slow for the peripherals on them. The recommended rates from the manual are: - AHBS: 200 MHz - APBS0: 100 MHz - APBS1: 24 MHz Since 24 MHz is the hardware default, just assign rates for the first two. Reviewed-by: Jernej Skrabec Link: https://patch.msgid.link/20250913101600.3932762-1-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index d00da1cd744e..7b36c47a3a13 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -626,6 +626,8 @@ r_ccu: clock-controller@7010000 { "pll-audio"; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&r_ccu CLK_R_AHB>, <&r_ccu CLK_R_APB0>; + assigned-clock-rates = <200000000>, <100000000>; }; nmi_intc: interrupt-controller@7010320 { From 9f01e1e14e71defefcb4d6823b8476a15f3cf04a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 13 Sep 2025 18:24:48 +0800 Subject: [PATCH 822/931] arm64: dts: allwinner: a527: cubie-a5e: Drop external 32.768 KHz crystal The Radxa Cubie A5E has empty pads for a 32.768 KHz crystal, but it is left unpopulated, as per the schematics and seen on board images. A dead give away is the RTC's LOSC auto switch register showing the external OSC to be abnormal. Drop the external crystal from the device tree. It was not referenced anyway. Fixes: c2520cd032ae ("arm64: dts: allwinner: a523: add Radxa A5E support") Reviewed-by: Jernej Skrabec Link: https://patch.msgid.link/20250913102450.3935943-1-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index d4cee2222104..514c221a7a86 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -21,13 +21,6 @@ chosen { stdout-path = "serial0:115200n8"; }; - ext_osc32k: ext-osc32k-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "ext_osc32k"; - }; - leds { compatible = "gpio-leds"; From 3d5e1ba00af8dd34ae1e573c2c07e00b5ec65267 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 13 Sep 2025 18:24:49 +0800 Subject: [PATCH 823/931] arm64: dts: allwinner: t527: avaota-a1: hook up external 32k crystal When the board was added, its external 32.768 KHz crystal was described but not hooked up correctly. This meant the device had to fall back to the SoC's internal oscillator or divide a 32 KHz clock from the main oscillator, neither of which are accurate for the RTC. As a result the RTC clock will drift badly. Hook the crystal up to the RTC block and request the correct clock rate. Fixes: dbe54efa32af ("arm64: dts: allwinner: a523: add Avaota-A1 router support") Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250913102450.3935943-2-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index e7713678208d..4e71055fbd15 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -309,6 +309,14 @@ &r_pio { vcc-pm-supply = <®_aldo3>; }; +&rtc { + clocks = <&r_ccu CLK_BUS_R_RTC>, <&osc24M>, + <&r_ccu CLK_R_AHB>, <&ext_osc32k>; + clock-names = "bus", "hosc", "ahb", "ext-osc32k"; + assigned-clocks = <&rtc CLK_OSC32K>; + assigned-clock-rates = <32768>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; From bd1ce7ef6aef4ee7349eb3124166e712693650ce Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 13 Sep 2025 18:24:50 +0800 Subject: [PATCH 824/931] arm64: dts: allwinner: t527: orangepi-4a: hook up external 32k crystal When the board was added, its external 32.768 KHz crystal was described but not hooked up correctly. This meant the device had to fall back to the SoC's internal oscillator or divide a 32 KHz clock from the main oscillator, neither of which are accurate for the RTC. As a result the RTC clock will drift badly. Hook the crystal up to the RTC block and request the correct clock rate. Fixes: de713ccb9934 ("arm64: dts: allwinner: t527: Add OrangePi 4A board") Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250913102450.3935943-3-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index d07bb9193b43..b5483bd7b8d5 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -346,6 +346,14 @@ &r_pio { vcc-pm-supply = <®_bldo2>; }; +&rtc { + clocks = <&r_ccu CLK_BUS_R_RTC>, <&osc24M>, + <&r_ccu CLK_R_AHB>, <&ext_osc32k>; + clock-names = "bus", "hosc", "ahb", "ext-osc32k"; + assigned-clocks = <&rtc CLK_OSC32K>; + assigned-clock-rates = <32768>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; From cca07ac2b5f7838b8ff612b53b9f82ac8cb58312 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 14 Sep 2025 01:35:11 +0800 Subject: [PATCH 825/931] arm64: dts: allwinner: sun55i: Complete AXP717A sub-functions When the AXP717A PMIC is missing nodes for the sub-functions, the kernel complains about not found nodes. Add all the remaining nodes corresponding to the defined functions for the dev boards, which have publicly available schematics to base this change on. The battery charger on all of them are disabled. Also add an "iio-hwmon" node to express some of the ADC channels as hwmon sensors. Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20250913173511.4064176-1-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun55i-a527-cubie-a5e.dts | 21 +++++++++++++++++ .../dts/allwinner/sun55i-t527-avaota-a1.dts | 23 +++++++++++++++++++ .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 23 +++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 514c221a7a86..f82a8d121697 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -39,6 +39,12 @@ use-led { }; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&axp717_adc 3>, /* vsys_v */ + <&axp717_adc 4>; /* pmic_temp */ + }; + reg_vcc5v: vcc5v { /* board wide 5V supply from the USB-C connector */ compatible = "regulator-fixed"; @@ -140,6 +146,17 @@ axp717: pmic@34 { bldoin-supply = <®_vcc5v>; cldoin-supply = <®_vcc5v>; + axp717_adc: adc { + compatible = "x-powers,axp717-adc"; + #io-channel-cells = <1>; + }; + + battery-power { + compatible = "x-powers,axp717-battery-power-supply"; + /* charger mode design but has no battery terminal */ + status = "disabled"; + }; + regulators { /* Supplies the "little" cluster (1.4 GHz cores) */ reg_dcdc1: dcdc1 { @@ -243,6 +260,10 @@ reg_cpusldo: cpusldo { regulator-name = "vdd-cpus"; }; }; + + usb-power { + compatible = "x-powers,axp717-usb-power-supply"; + }; }; axp323: pmic@36 { diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index 4e71055fbd15..1b054fa8ef74 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -27,6 +27,12 @@ ext_osc32k: ext-osc32k-clk { clock-output-names = "ext_osc32k"; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&axp717_adc 3>, /* vsys_v */ + <&axp717_adc 4>; /* pmic_temp */ + }; + reg_vcc12v: vcc12v { /* DC input jack */ compatible = "regulator-fixed"; @@ -149,6 +155,17 @@ axp717: pmic@35 { bldoin-supply = <®_vcc5v>; cldoin-supply = <®_vcc5v>; + axp717_adc: adc { + compatible = "x-powers,axp717-adc"; + #io-channel-cells = <1>; + }; + + battery-power { + compatible = "x-powers,axp717-battery-power-supply"; + /* no battery; output used for dcdc4 instead */ + status = "disabled"; + }; + regulators { /* Supplies the "little" cluster (1.4 GHz cores) */ reg_dcdc1: dcdc1 { @@ -255,6 +272,12 @@ reg_cpusldo: cpusldo { regulator-name = "vdd-cpus"; }; }; + + usb-power { + compatible = "x-powers,axp717-usb-power-supply"; + /* 12V-5V buck converter can supply up to 5A */ + input-current-limit-microamp = <3250000>; + }; }; axp323: pmic@36 { diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index b5483bd7b8d5..39a4e194712a 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -40,6 +40,13 @@ led { }; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&axp717_adc 3>, /* vsys_v */ + <&axp717_adc 4>, /* pmic_temp */ + <&axp717_adc 7>; /* bkup_batt_v */ + }; + wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 1 1 GPIO_ACTIVE_LOW>; /* PM1 */ @@ -174,6 +181,17 @@ axp717: pmic@35 { bldoin-supply = <®_vcc5v>; cldoin-supply = <®_vcc5v>; + axp717_adc: adc { + compatible = "x-powers,axp717-adc"; + #io-channel-cells = <1>; + }; + + battery-power { + compatible = "x-powers,axp717-battery-power-supply"; + /* no battery; output used for dcdc4 instead */ + status = "disabled"; + }; + regulators { /* Supplies the "little" cluster (1.4 GHz cores) */ reg_dcdc1: dcdc1 { @@ -288,6 +306,11 @@ reg_cpusldo: cpusldo { regulator-name = "vdd-cpus-usb-0v9"; }; }; + + usb-power { + compatible = "x-powers,axp717-usb-power-supply"; + input-current-limit-microamp = <3000000>; + }; }; axp323: pmic@36 { From 7a0e28e5b2aa25919b9f32f7ef9d1e425aefabca Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 10 Sep 2025 16:48:23 -0500 Subject: [PATCH 826/931] arm64: dts: apm: Move slimpro nodes out of "simple-bus" node The slimpro nodes are not MMIO devices, so they don't belong under a "simple-bus" node. Move them to the top level. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250910214822.508317-2-robh@kernel.org Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/apm/apm-storm.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 1b9588f7536c..36214918190d 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -134,6 +134,16 @@ pmu { interrupts = <1 12 0xff04>; }; + i2cslimpro { + compatible = "apm,xgene-slimpro-i2c"; + mboxes = <&mailbox 0>; + }; + + hwmonslimpro { + compatible = "apm,xgene-slimpro-hwmon"; + mboxes = <&mailbox 7>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -761,16 +771,6 @@ mailbox: mailbox@10540000 { <0x0 0x7 0x4>; }; - i2cslimpro { - compatible = "apm,xgene-slimpro-i2c"; - mboxes = <&mailbox 0>; - }; - - hwmonslimpro { - compatible = "apm,xgene-slimpro-hwmon"; - mboxes = <&mailbox 7>; - }; - serial0: serial@1c020000 { status = "disabled"; compatible = "ns16550a"; From 668cf076552dd820914484e10cc48600dafd7e71 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 10 Sep 2025 17:30:19 -0500 Subject: [PATCH 827/931] arm64: dts: apm: Clean-up clock bindings Clean-up a couple of clock binding related issues in the the X-Gene DTS. CPU and I2C nodes aren't clock providers and shouldn't have "#clock-cells" properties. A fixed-clock only provides 1 clock, so "#clock-cells" must be 0. The preferred node name is "clock-" as well. The "type" property is undocumented and unused, so drop it. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250910223020.612244-2-robh@kernel.org Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 16 ++----- arch/arm64/boot/dts/apm/apm-storm.dtsi | 54 ++++++++++------------ 2 files changed, 29 insertions(+), 41 deletions(-) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 5a64239b4708..b98fd434b7d6 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -22,7 +22,6 @@ cpu@0 { enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_0>; - #clock-cells = <1>; clocks = <&pmd0clk 0>; }; cpu@1 { @@ -32,7 +31,6 @@ cpu@1 { enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_0>; - #clock-cells = <1>; clocks = <&pmd0clk 0>; }; cpu@100 { @@ -42,7 +40,6 @@ cpu@100 { enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_1>; - #clock-cells = <1>; clocks = <&pmd1clk 0>; }; cpu@101 { @@ -52,7 +49,6 @@ cpu@101 { enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_1>; - #clock-cells = <1>; clocks = <&pmd1clk 0>; }; cpu@200 { @@ -62,7 +58,6 @@ cpu@200 { enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_2>; - #clock-cells = <1>; clocks = <&pmd2clk 0>; }; cpu@201 { @@ -72,7 +67,6 @@ cpu@201 { enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_2>; - #clock-cells = <1>; clocks = <&pmd2clk 0>; }; cpu@300 { @@ -82,7 +76,6 @@ cpu@300 { enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_3>; - #clock-cells = <1>; clocks = <&pmd3clk 0>; }; cpu@301 { @@ -92,7 +85,6 @@ cpu@301 { enable-method = "spin-table"; cpu-release-addr = <0x1 0x0000fff8>; next-level-cache = <&xgene_L2_3>; - #clock-cells = <1>; clocks = <&pmd3clk 0>; }; xgene_L2_0: l2-cache-0 { @@ -211,9 +203,9 @@ v2m15: v2m@f0000 { }; }; - refclk: refclk { + refclk: clock-100000000 { compatible = "fixed-clock"; - #clock-cells = <1>; + #clock-cells = <0>; clock-frequency = <100000000>; clock-output-names = "refclk"; }; @@ -246,7 +238,7 @@ clocks { pmdpll: pmdpll@170000f0 { compatible = "apm,xgene-pcppll-v2-clock"; #clock-cells = <1>; - clocks = <&refclk 0>; + clocks = <&refclk>; reg = <0x0 0x170000f0 0x0 0x10>; clock-output-names = "pmdpll"; }; @@ -286,7 +278,7 @@ pmd3clk: pmd3clk@7e200230 { socpll: socpll@17000120 { compatible = "apm,xgene-socpll-v2-clock"; #clock-cells = <1>; - clocks = <&refclk 0>; + clocks = <&refclk>; reg = <0x0 0x17000120 0x0 0x1000>; clock-output-names = "socpll"; }; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 36214918190d..4ca0ead120c1 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -113,9 +113,9 @@ gic: interrupt-controller@78010000 { interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ }; - refclk: refclk { + refclk: clock-100000000 { compatible = "fixed-clock"; - #clock-cells = <1>; + #clock-cells = <0>; clock-frequency = <100000000>; clock-output-names = "refclk"; }; @@ -159,28 +159,25 @@ clocks { pcppll: pcppll@17000100 { compatible = "apm,xgene-pcppll-clock"; #clock-cells = <1>; - clocks = <&refclk 0>; + clocks = <&refclk>; clock-names = "pcppll"; reg = <0x0 0x17000100 0x0 0x1000>; clock-output-names = "pcppll"; - type = <0>; }; socpll: socpll@17000120 { compatible = "apm,xgene-socpll-clock"; #clock-cells = <1>; - clocks = <&refclk 0>; + clocks = <&refclk>; clock-names = "socpll"; reg = <0x0 0x17000120 0x0 0x1000>; clock-output-names = "socpll"; - type = <1>; }; socplldiv2: socplldiv2 { compatible = "fixed-factor-clock"; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&socpll 0>; - clock-names = "socplldiv2"; clock-mult = <1>; clock-div = <2>; clock-output-names = "socplldiv2"; @@ -189,7 +186,7 @@ socplldiv2: socplldiv2 { ahbclk: ahbclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x17000000 0x0 0x2000>; reg-names = "div-reg"; divider-offset = <0x164>; @@ -201,7 +198,7 @@ ahbclk: ahbclk@17000000 { sdioclk: sdioclk@1f2ac000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f2ac000 0x0 0x1000 0x0 0x17000000 0x0 0x2000>; reg-names = "csr-reg", "div-reg"; @@ -218,7 +215,7 @@ sdioclk: sdioclk@1f2ac000 { ethclk: ethclk { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; clock-names = "ethclk"; reg = <0x0 0x17000000 0x0 0x1000>; reg-names = "div-reg"; @@ -240,7 +237,7 @@ menetclk: menetclk { sge0clk: sge0clk@1f21c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f21c000 0x0 0x1000>; reg-names = "csr-reg"; csr-mask = <0xa>; @@ -251,7 +248,7 @@ sge0clk: sge0clk@1f21c000 { xge0clk: xge0clk@1f61c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f61c000 0x0 0x1000>; reg-names = "csr-reg"; csr-mask = <0x3>; @@ -262,7 +259,7 @@ xge1clk: xge1clk@1f62c000 { compatible = "apm,xgene-device-clock"; status = "disabled"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f62c000 0x0 0x1000>; reg-names = "csr-reg"; csr-mask = <0x3>; @@ -272,7 +269,7 @@ xge1clk: xge1clk@1f62c000 { sataphy1clk: sataphy1clk@1f21c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f21c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sataphy1clk"; @@ -286,7 +283,7 @@ sataphy1clk: sataphy1clk@1f21c000 { sataphy2clk: sataphy1clk@1f22c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f22c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sataphy2clk"; @@ -300,7 +297,7 @@ sataphy2clk: sataphy1clk@1f22c000 { sataphy3clk: sataphy1clk@1f23c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f23c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sataphy3clk"; @@ -314,7 +311,7 @@ sataphy3clk: sataphy1clk@1f23c000 { sata01clk: sata01clk@1f21c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f21c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sata01clk"; @@ -327,7 +324,7 @@ sata01clk: sata01clk@1f21c000 { sata23clk: sata23clk@1f22c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f22c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sata23clk"; @@ -340,7 +337,7 @@ sata23clk: sata23clk@1f22c000 { sata45clk: sata45clk@1f23c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f23c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "sata45clk"; @@ -353,7 +350,7 @@ sata45clk: sata45clk@1f23c000 { rtcclk: rtcclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x17000000 0x0 0x2000>; reg-names = "csr-reg"; csr-offset = <0xc>; @@ -366,7 +363,7 @@ rtcclk: rtcclk@17000000 { rngpkaclk: rngpkaclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x17000000 0x0 0x2000>; reg-names = "csr-reg"; csr-offset = <0xc>; @@ -380,7 +377,7 @@ pcie0clk: pcie0clk@1f2bc000 { status = "disabled"; compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f2bc000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "pcie0clk"; @@ -390,7 +387,7 @@ pcie1clk: pcie1clk@1f2cc000 { status = "disabled"; compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f2cc000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "pcie1clk"; @@ -400,7 +397,7 @@ pcie2clk: pcie2clk@1f2dc000 { status = "disabled"; compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f2dc000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "pcie2clk"; @@ -410,7 +407,7 @@ pcie3clk: pcie3clk@1f50c000 { status = "disabled"; compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f50c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "pcie3clk"; @@ -420,7 +417,7 @@ pcie4clk: pcie4clk@1f51c000 { status = "disabled"; compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f51c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "pcie4clk"; @@ -429,7 +426,7 @@ pcie4clk: pcie4clk@1f51c000 { dmaclk: dmaclk@1f27c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f27c000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "dmaclk"; @@ -850,7 +847,6 @@ i2c0: i2c@10512000 { compatible = "snps,designware-i2c"; reg = <0x0 0x10512000 0x0 0x1000>; interrupts = <0 0x44 0x4>; - #clock-cells = <1>; clocks = <&ahbclk 0>; }; From 58760bd7219d9d0318720049117d27ee90c96f4f Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 10 Sep 2025 18:39:23 -0500 Subject: [PATCH 828/931] arm64: dts: socionext: Drop "linux,spdif-dit" port node unit-address A single graph port node without an address (i.e. "reg") should not have a unit-address, drop it from the "linux,spdif-dit" port node. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250910233923.778992-2-robh@kernel.org Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts | 4 ++-- arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts | 4 ++-- arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts index de219570bbc9..fc105d420db4 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-global.dts @@ -68,7 +68,7 @@ spdif-out { compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; - port@0 { + port { spdif_tx: endpoint { remote-endpoint = <&spdif_hiecout1>; }; @@ -79,7 +79,7 @@ comp-spdif-out { compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; - port@0 { + port { comp_spdif_tx: endpoint { remote-endpoint = <&comp_spdif_hiecout1>; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts index fba454adae7d..10efa747ed8b 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts @@ -74,7 +74,7 @@ spdif-out { compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; - port@0 { + port { spdif_tx: endpoint { remote-endpoint = <&spdif_hiecout1>; }; @@ -85,7 +85,7 @@ comp-spdif-out { compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; - port@0 { + port { comp_spdif_tx: endpoint { remote-endpoint = <&comp_spdif_hiecout1>; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts index 20e5fb724fae..3c4dcfb82ddf 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts @@ -68,7 +68,7 @@ spdif-out { compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; - port@0 { + port { spdif_tx: endpoint { remote-endpoint = <&spdif_hiecout1>; }; @@ -79,7 +79,7 @@ comp-spdif-out { compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; - port@0 { + port { comp_spdif_tx: endpoint { remote-endpoint = <&comp_spdif_hiecout1>; }; From a409fac1f74bae095605fda86d8f7083aa5b35a6 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Wed, 10 Sep 2025 18:37:40 -0500 Subject: [PATCH 829/931] ARM: dts: socionext: Drop "linux,spdif-dit" port node unit-address A single graph port node without an address (i.e. "reg") should not have a unit-address, drop it from the "linux,spdif-dit" port node. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250910233740.777077-2-robh@kernel.org Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/socionext/uniphier-pxs2-vodka.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/socionext/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/socionext/uniphier-pxs2-vodka.dts index 7e08a459f7d8..ab910e1b5e6a 100644 --- a/arch/arm/boot/dts/socionext/uniphier-pxs2-vodka.dts +++ b/arch/arm/boot/dts/socionext/uniphier-pxs2-vodka.dts @@ -43,7 +43,7 @@ spdif-out { compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; - port@0 { + port { spdif_tx: endpoint { remote-endpoint = <&spdif_hiecout1>; }; @@ -54,7 +54,7 @@ comp-spdif-out { compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; - port@0 { + port { comp_spdif_tx: endpoint { remote-endpoint = <&comp_spdif_hiecout1>; }; From f398bb61833500bceb81c2445f2a9e6e8cbc3551 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= Date: Fri, 11 Jul 2025 09:41:24 +0200 Subject: [PATCH 830/931] arm64: dts: st: add Hardware debug port (HDP) on stm32mp25 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the hdp devicetree node for stm32mp25 SoC family Keep the node disabled as HDP needs the pinctrl SoC configuration to be able to output its mux output signal outside of the SoC, on the SoC pad. This configuration is provided in the board dtsi file through 'pinctrl-*' properties as well as HDP mux configuration. Thus, if needed, HDP should be enabled in board dtsi file. Signed-off-by: Clément Le Goffic Link: https://lore.kernel.org/r/20250711-hdp-upstream-v7-6-faeecf7aaee1@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 303abf915b8e..9372bc3c3a4b 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1672,6 +1672,13 @@ package_otp@1e8 { }; }; + hdp: pinctrl@44090000 { + compatible = "st,stm32mp251-hdp"; + reg = <0x44090000 0x400>; + clocks = <&rcc CK_BUS_HDP>; + status = "disabled"; + }; + rcc: clock-controller@44200000 { compatible = "st,stm32mp25-rcc"; reg = <0x44200000 0x10000>; From 3d42567279e1328ba90e51b47b80539b9dae007e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= Date: Fri, 11 Jul 2025 09:41:25 +0200 Subject: [PATCH 831/931] ARM: dts: stm32: add alternate pinmux for HDP pin and add HDP pinctrl node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce hdp node to output a user defined value on port hdp2. Add pinctrl nodes to be able to output this signal on one SoC pin. Signed-off-by: Clément Le Goffic Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20250711-hdp-upstream-v7-7-faeecf7aaee1@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 25 +++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi index 835b034d0aa7..8613a6a17ee9 100644 --- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -5,6 +5,14 @@ */ #include +&hdp { + /omit-if-no-ref/ + hdp2_gpo: hdp2-pins { + function = "gpoval2"; + pins = "HDP2"; + }; +}; + &pinctrl { /omit-if-no-ref/ adc1_ain_pins_a: adc1-ain-0 { @@ -731,6 +739,23 @@ pins { }; }; + /omit-if-no-ref/ + hdp2_pins_a: hdp2-0 { + pins { + pinmux = ; /* HDP2 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + /omit-if-no-ref/ + hdp2_sleep_pins_a: hdp2-sleep-0 { + pins { + pinmux = ; /* HDP2 */ + }; + }; + /omit-if-no-ref/ i2c1_pins_a: i2c1-0 { pins { From d0647b20d1e19a6d8dc44e57d2d453610c0f29f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= Date: Fri, 11 Jul 2025 09:41:26 +0200 Subject: [PATCH 832/931] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp157c-dk2 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On the stm32mp157fc-dk2 board, we can observe the hdp GPOVAL function on SoC pin E13 accessible on the pin 5 on the Arduino connector CN13. Add the relevant configuration but keep it disabled as it's used for debug only. Signed-off-by: Clément Le Goffic Link: https://lore.kernel.org/r/20250711-hdp-upstream-v7-8-faeecf7aaee1@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts index 78165c7865e1..1ec3b8f2faa9 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -62,6 +62,12 @@ &dsi_out { remote-endpoint = <&panel_in>; }; +&hdp { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hdp2_gpo &hdp2_pins_a>; + pinctrl-1 = <&hdp2_sleep_pins_a>; +}; + &i2c1 { touchscreen@38 { compatible = "focaltech,ft6236"; From 27cd5cd8bd332d9d09fe5af6b1b0ed9c02ccdf24 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 21 Aug 2025 11:14:02 +0200 Subject: [PATCH 833/931] arm64: defconfig: Enable STMicroelectronics STM32 DMA3 support Enable STMicroelectronics STM32 DMA3 support as module. STM32 DMA3 is used among others by STM32 Octo SPI driver on STM32MP257F-EV1 board. Signed-off-by: Patrice Chotard Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250821-upstream_defconfig_enable_stm32_dma3-v1-1-d9c1b71883d9@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 58f87d09366c..cce17e8701e0 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1300,6 +1300,7 @@ CONFIG_RENESAS_USB_DMAC=m CONFIG_RZ_DMAC=y CONFIG_TI_K3_UDMA=y CONFIG_TI_K3_UDMA_GLUE_LAYER=y +CONFIG_STM32_DMA3=m CONFIG_VFIO=y CONFIG_VFIO_PCI=y CONFIG_VIRTIO_PCI=y From 7e4479c9243d1b5d1e3deb7fb9efae64a399a3e3 Mon Sep 17 00:00:00 2001 From: Christian Bruel Date: Wed, 20 Aug 2025 09:54:08 +0200 Subject: [PATCH 834/931] arm64: dts: st: add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi Add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi init: forces GPIO to low while probing so CLKREQ is low for phy_init default: restore the AFMUX after controller probe Add Analog pins of PCIe to perform power cycle Signed-off-by: Christian Bruel Link: https://lore.kernel.org/r/20250820075411.1178729-9-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 5ac9e72478dd..04e1606df126 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -133,6 +133,26 @@ pins { }; }; + pcie_pins_a: pcie-0 { + pins { + pinmux = ; + bias-disable; + }; + }; + + pcie_init_pins_a: pcie-init-0 { + pins { + pinmux = ; + output-low; + }; + }; + + pcie_sleep_pins_a: pcie-sleep-0 { + pins { + pinmux = ; + }; + }; + pwm3_pins_a: pwm3-0 { pins { pinmux = ; /* TIM3_CH2 */ From 0ecdf6d2f55044487e7c1ceeed70b6356b670aa4 Mon Sep 17 00:00:00 2001 From: Christian Bruel Date: Wed, 20 Aug 2025 09:54:09 +0200 Subject: [PATCH 835/931] arm64: dts: st: Add PCIe Root Complex mode on stm32mp251 Add pcie_rc node to support STM32 MP25 PCIe driver based on the DesignWare PCIe core configured as Root Complex mode Supports Gen1/Gen2, single lane, MSI interrupts using the ARM GICv2m Signed-off-by: Christian Bruel Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20250820075411.1178729-10-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 44 ++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 9372bc3c3a4b..235a57a31df6 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -122,6 +122,15 @@ intc: interrupt-controller@4ac00000 { <0x0 0x4ac20000 0x0 0x20000>, <0x0 0x4ac40000 0x0 0x20000>, <0x0 0x4ac60000 0x0 0x20000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + v2m0: v2m@48090000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x0 0x48090000 0x0 0x1000>; + msi-controller; + }; }; psci { @@ -1654,6 +1663,41 @@ stmmac_axi_config_1: stmmac-axi-config { snps,wr_osr_lmt = <0x7>; }; }; + + pcie_rc: pcie@48400000 { + compatible = "st,stm32mp25-pcie-rc"; + device_type = "pci"; + reg = <0x48400000 0x400000>, + <0x10000000 0x10000>; + reg-names = "dbi", "config"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>, + <0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>, + <0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>; + dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>; + clocks = <&rcc CK_BUS_PCIE>; + resets = <&rcc PCIE_R>; + msi-parent = <&v2m0>; + access-controllers = <&rifsc 68>; + power-domains = <&CLUSTER_PD>; + status = "disabled"; + + pcie@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + phys = <&combophy PHY_TYPE_PCIE>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; }; bsec: efuse@44000000 { From 73d536ae1a43015dd184e5ced6879f61c8907bca Mon Sep 17 00:00:00 2001 From: Christian Bruel Date: Wed, 20 Aug 2025 09:54:10 +0200 Subject: [PATCH 836/931] arm64: dts: st: Add PCIe Endpoint mode on stm32mp251 Add pcie_ep node to support STM32 MP25 PCIe driver based on the DesignWare PCIe core configured as Endpoint mode Signed-off-by: Christian Bruel Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20250820075411.1178729-11-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 235a57a31df6..605b6a5d39a6 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1664,6 +1664,21 @@ stmmac_axi_config_1: stmmac-axi-config { }; }; + pcie_ep: pcie-ep@48400000 { + compatible = "st,stm32mp25-pcie-ep"; + reg = <0x48400000 0x100000>, + <0x48500000 0x100000>, + <0x48700000 0x80000>, + <0x10000000 0x10000000>; + reg-names = "dbi", "dbi2", "atu", "addr_space"; + clocks = <&rcc CK_BUS_PCIE>; + resets = <&rcc PCIE_R>; + phys = <&combophy PHY_TYPE_PCIE>; + access-controllers = <&rifsc 68>; + power-domains = <&CLUSTER_PD>; + status = "disabled"; + }; + pcie_rc: pcie@48400000 { compatible = "st,stm32mp25-pcie-rc"; device_type = "pci"; From 30793e0108942cb086ae9febfa5bf736453013e7 Mon Sep 17 00:00:00 2001 From: Christian Bruel Date: Wed, 20 Aug 2025 09:54:11 +0200 Subject: [PATCH 837/931] arm64: dts: st: Enable PCIe on the stm32mp257f-ev1 board Add PCIe RC and EP support on stm32mp257f-ev1 board. Default to RC mode. Signed-off-by: Christian Bruel Link: https://lore.kernel.org/r/20250820075411.1178729-12-christian.bruel@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 4ff334563599..d25d16c3681f 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -230,6 +230,27 @@ timer { }; }; +&pcie_ep { + pinctrl-names = "default", "init"; + pinctrl-0 = <&pcie_pins_a>; + pinctrl-1 = <&pcie_init_pins_a>; + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +&pcie_rc { + pinctrl-names = "default", "init", "sleep"; + pinctrl-0 = <&pcie_pins_a>; + pinctrl-1 = <&pcie_init_pins_a>; + pinctrl-2 = <&pcie_sleep_pins_a>; + status = "okay"; + + pcie@0,0 { + reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; +}; + &rtc { status = "okay"; }; From dd1704a50738605997e0aff71981c33241c3df67 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Thu, 7 Aug 2025 08:09:30 +0200 Subject: [PATCH 838/931] dt-binding: can: m_can: add optional resets property The m_can IP core has an external reset line. Add it to the bindings documentation. Signed-off-by: Marc Kleine-Budde Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20250807-stm32mp15-m_can-add-reset-v2-1-f69ebbfced1f@pengutronix.de Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/net/can/bosch,m_can.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml index c4887522e8fe..61ef60d8f1c7 100644 --- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -50,6 +50,9 @@ properties: - const: hclk - const: cclk + resets: + maxItems: 1 + bosch,mram-cfg: description: | Message RAM configuration data. From 6bb200f11aedd1c3c5579e5b37c13144d1e49ac8 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Thu, 7 Aug 2025 08:09:31 +0200 Subject: [PATCH 839/931] ARM: dts: stm32: add resets property to m_can nodes in the stm32mp153 On the STM32MP153 the m_cam IP cores (a.k.a. FDCAN) have an external shared reset in the RCC. Add the reset to both m_can nodes. Signed-off-by: Marc Kleine-Budde Link: https://lore.kernel.org/r/20250807-stm32mp15-m_can-add-reset-v2-2-f69ebbfced1f@pengutronix.de Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp153.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi index 4640dafb1598..92794b942ab2 100644 --- a/arch/arm/boot/dts/st/stm32mp153.dtsi +++ b/arch/arm/boot/dts/st/stm32mp153.dtsi @@ -40,6 +40,7 @@ m_can1: can@4400e000 { interrupt-names = "int0", "int1"; clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; + resets = <&rcc FDCAN_R>; bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; access-controllers = <&etzpc 62>; status = "disabled"; @@ -54,6 +55,7 @@ m_can2: can@4400f000 { interrupt-names = "int0", "int1"; clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; + resets = <&rcc FDCAN_R>; bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; access-controllers = <&etzpc 62>; status = "disabled"; From 114e282d51ea87dab368397d525be96e57d084ff Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:18 +0200 Subject: [PATCH 840/931] arm64: dts: st: add ltdc support on stm32mp251 The LCD-TFT Display Controller (LTDC) handles display composition, scaling and rotation. It provides a parallel digital RGB flow to be used by display interfaces. Add the LTDC node. Signed-off-by: Raphael Gallais-Pou Acked-by: Yannick Fertre Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-9-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 605b6a5d39a6..aecbdea07385 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1562,6 +1562,18 @@ trigger@4 { }; }; + ltdc: display-controller@48010000 { + compatible = "st,stm32mp251-ltdc"; + reg = <0x48010000 0x400>; + interrupts = , + ; + clocks = <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>; + clock-names = "lcd", "bus"; + resets = <&rcc LTDC_R>; + access-controllers = <&rifsc 80>; + status = "disabled"; + }; + csi: csi@48020000 { compatible = "st,stm32mp25-csi"; reg = <0x48020000 0x2000>; From 84b78bc2cb144ea0945320c5d1c4ad2085a704e6 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:19 +0200 Subject: [PATCH 841/931] arm64: dts: st: add ltdc support on stm32mp255 Add the LTDC node for stm32mp255 SoC and handle its loopback clocks. ck_ker_ltdc has the CLK_SET_RATE_PARENT flag. While having this flag is semantically correct, it for now leads to an improper setting of the clock rate. The ck_ker_ltdc parent clock is the flexgen 27, which does not support changing rates yet. To overcome this issue, a fixed clock can be used for the kernel clock. Signed-off-by: Raphael Gallais-Pou Acked-by: Yannick Fertre Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-10-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index aecbdea07385..e2a2fc9070f0 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -52,6 +52,12 @@ clk_rcbsec: clk-rcbsec { compatible = "fixed-clock"; clock-frequency = <64000000>; }; + + clk_flexgen_27_fixed: clk-54000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <54000000>; + }; }; firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index f689b47c5010..48a95af1741c 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -5,6 +5,12 @@ */ #include "stm32mp253.dtsi" +<dc { + compatible = "st,stm32mp255-ltdc"; + clocks = <&clk_flexgen_27_fixed>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds>; + clock-names = "lcd", "bus", "ref", "lvds"; +}; + &rifsc { vdec: vdec@480d0000 { compatible = "st,stm32mp25-vdec"; From c067119b07369a2d27eb2575f050afb271ec01e7 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:20 +0200 Subject: [PATCH 842/931] arm64: dts: st: add lvds support on stm32mp255 The LVDS is used on STM32MP2 as a display interface. Add the LVDS node. Signed-off-by: Raphael Gallais-Pou Acked-by: Yannick Fertre Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-11-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp255.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index 48a95af1741c..7a598f53a2a0 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -12,6 +12,18 @@ <dc { }; &rifsc { + lvds: lvds@48060000 { + compatible = "st,stm32mp255-lvds", "st,stm32mp25-lvds"; + reg = <0x48060000 0x2000>; + #clock-cells = <0>; + clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>; + clock-names = "pclk", "ref"; + resets = <&rcc LVDS_R>; + access-controllers = <&rifsc 84>; + power-domains = <&CLUSTER_PD>; + status = "disabled"; + }; + vdec: vdec@480d0000 { compatible = "st,stm32mp25-vdec"; reg = <0x480d0000 0x3c8>; From 092f7634fffa66c7dfc5c452e0c8818040ff77b8 Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:21 +0200 Subject: [PATCH 843/931] arm64: dts: st: add clock-cells to syscfg node on stm32mp251 Make the syscfg node a clock provider so clock consumers can reach child clocks through device-tree. Signed-off-by: Raphael Gallais-Pou Acked-by: Yannick Fertre Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-12-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index e2a2fc9070f0..a8e6e0f77b83 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1940,6 +1940,7 @@ exti1: interrupt-controller@44220000 { syscfg: syscon@44230000 { compatible = "st,stm32mp25-syscfg", "syscon"; reg = <0x44230000 0x10000>; + #clock-cells = <0>; }; pinctrl: pinctrl@44240000 { From 86803282a11801fb15360e52e6f2a7d7c7afdbec Mon Sep 17 00:00:00 2001 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:22 +0200 Subject: [PATCH 844/931] arm64: dts: st: enable display support on stm32mp257f-ev1 board Enable the following IPs on stm32mp257f-ev1 in order to get display: * LTDC * LVDS * WSVGA LVDS panel (1024x600) * Panel LVDS backlight as GPIO backlight * ILI2511 i2c touchscreen Signed-off-by: Raphael Gallais-Pou Acked-by: Yannick Fertre Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-13-9c825e28f733@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 76 ++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index d25d16c3681f..9e0e4da17b39 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -70,6 +70,42 @@ memory@80000000 { reg = <0x0 0x80000000 0x1 0x0>; }; + panel_lvds: display { + compatible = "edt,etml0700z9ndha", "panel-lvds"; + enable-gpios = <&gpiog 15 GPIO_ACTIVE_HIGH>; + backlight = <&panel_lvds_backlight>; + power-supply = <&scmi_v3v3>; + width-mm = <156>; + height-mm = <92>; + data-mapping = "vesa-24"; + status = "okay"; + + panel-timing { + clock-frequency = <54000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <150>; + hback-porch = <150>; + hsync-len = <21>; + vfront-porch = <24>; + vback-porch = <24>; + vsync-len = <21>; + }; + + port { + lvds_panel_in: endpoint { + remote-endpoint = <&lvds_out0>; + }; + }; + }; + + panel_lvds_backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + default-on; + status = "okay"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -183,6 +219,15 @@ imx335_ep: endpoint { }; }; }; + + ili2511: ili2511@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpioi>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpiog 14 GPIO_ACTIVE_LOW>; + status = "okay"; + }; }; &i2c8 { @@ -230,6 +275,37 @@ timer { }; }; +<dc { + status = "okay"; + port { + ltdc_ep0_out: endpoint { + remote-endpoint = <&lvds_in>; + }; + }; +}; + +&lvds { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + lvds_out0: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; +}; + &pcie_ep { pinctrl-names = "default", "init"; pinctrl-0 = <&pcie_pins_a>; From bd0c7718ae1877e2e4eeb903096e905754d5df78 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Mon, 1 Sep 2025 11:16:29 +0200 Subject: [PATCH 845/931] ARM: dts: stm32: add missing PTP reference clocks on stm32mp13x SoCs ETH1/2 miss their PTP reference clock in the SoC device tree. Add them as the fallback is not correctly handled for PPS generation and it seems there's no reason to not add them. Signed-off-by: Gatien Chevallier Link: https://lore.kernel.org/r/20250901-relative_flex_pps-v4-3-b874971dfe85@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp131.dtsi | 2 ++ arch/arm/boot/dts/st/stm32mp133.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 151ffd0bdef9..fd730aa37c22 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -1609,11 +1609,13 @@ ethernet1: ethernet@5800a000 { "mac-clk-tx", "mac-clk-rx", "ethstp", + "ptp_ref", "eth-ck"; clocks = <&rcc ETH1MAC>, <&rcc ETH1TX>, <&rcc ETH1RX>, <&rcc ETH1STP>, + <&rcc ETH1PTP_K>, <&rcc ETH1CK_K>; st,syscon = <&syscfg 0x4 0xff0000>; snps,mixed-burst; diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index 49583137b597..053fc6691205 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -81,11 +81,13 @@ ethernet2: ethernet@5800e000 { "mac-clk-tx", "mac-clk-rx", "ethstp", + "ptp_ref", "eth-ck"; clocks = <&rcc ETH2MAC>, <&rcc ETH2TX>, <&rcc ETH2RX>, <&rcc ETH2STP>, + <&rcc ETH2PTP_K>, <&rcc ETH2CK_K>; st,syscon = <&syscfg 0x4 0xff000000>; snps,mixed-burst; From 4c2ac7b9abc8d7d3407cca3677835d137a748492 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Thu, 4 Sep 2025 09:40:56 +0200 Subject: [PATCH 846/931] arm64: dts: st: add eth1 pins for stm32mp2x platforms Eth1 ethernet controller is present on every stm32mp2x vendor boards. Describe the pinctrl of eth1 for each of them. Signed-off-by: Gatien Chevallier Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-1-05a060157fb7@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 126 ++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 04e1606df126..e0d102eb6176 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -6,6 +6,132 @@ #include &pinctrl { + eth1_mdio_pins_a: eth1-mdio-0 { + pins1 { + pinmux = ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + eth1_mdio_sleep_pins_a: eth1-mdio-sleep-0 { + pins1 { + pinmux = , /* ETH_MDC */ + ; /* ETH_MDIO */ + }; + }; + + eth1_rgmii_pins_a: eth1-rgmii-0 { + pins1 { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + ; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = , /* ETH_RGMII_CLK125 */ + ; /* ETH_RGMII_GTX_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + pins4 { + pinmux = ; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { + pins { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CTL */ + ; /* ETH_RGMII_RX_CLK */ + }; + }; + + eth1_rgmii_pins_b: eth1-rgmii-1 { + pins1 { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + ; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_MDC */ + ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + pins4 { + pinmux = ; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth1_rgmii_sleep_pins_b: eth1-rgmii-sleep-1 { + pins { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_MDC */ + , /* ETH_MDIO */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CTL */ + ; /* ETH_RGMII_RX_CLK */ + }; + }; + eth2_rgmii_pins_a: eth2-rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ From 74e42b3c5938a643a32106e2921a6f3b0fc75872 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Thu, 4 Sep 2025 09:40:57 +0200 Subject: [PATCH 847/931] arm64: dts: st: enable ethernet1 controller on stm32mp257f-dk ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. Enable this peripheral on the stm32mp257f-dk board. Signed-off-by: Gatien Chevallier Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-2-05a060157fb7@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts index a278a1e3ce03..e718d888ce21 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -19,6 +19,7 @@ / { compatible = "st,stm32mp257f-dk", "st,stm32mp257"; aliases { + ethernet0 = ðernet1; serial0 = &usart2; }; @@ -77,6 +78,28 @@ &arm_wdt { status = "okay"; }; +ðernet1 { + pinctrl-0 = <ð1_rgmii_pins_b>; + pinctrl-1 = <ð1_rgmii_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + phy-handle = <&phy1_eth1>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1_eth1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <1>; + reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt = <1800000>; From 58f29beb1ff5515a8423599a6422eb3e3790da75 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Thu, 4 Sep 2025 09:40:58 +0200 Subject: [PATCH 848/931] arm64: dts: st: enable ethernet1 controller on stm32mp257f-ev1 ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. It can either be used as a standalone Ethernet controller or be connected to the internal TSN capable switch. For this board, keep the standalone setup. Also enable this peripheral on the stm32mp257f-ev1 board. Signed-off-by: Gatien Chevallier Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-3-05a060157fb7@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 9e0e4da17b39..6e165073f732 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -19,6 +19,7 @@ / { aliases { ethernet0 = ðernet2; + ethernet1 = ðernet1; serial0 = &usart2; serial1 = &usart6; }; @@ -169,6 +170,29 @@ dcmipp_0: endpoint { }; }; +ðernet1 { + pinctrl-0 = <ð1_rgmii_pins_a ð1_mdio_pins_a>; + pinctrl-1 = <ð1_rgmii_sleep_pins_a ð1_mdio_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-handle = <&phy1_eth1>; + phy-mode = "rgmii-id"; + st,ext-phyclk; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1_eth1: ethernet-phy@4 { + compatible = "ethernet-phy-id001c.c916"; + reg = <4>; + reset-gpios = <&gpioj 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; +}; + ðernet2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <ð2_rgmii_pins_a>; From df4eb8bbdd13e504f545d803e2e3cb3673efa5c8 Mon Sep 17 00:00:00 2001 From: Gatien Chevallier Date: Thu, 4 Sep 2025 09:40:59 +0200 Subject: [PATCH 849/931] arm64: dts: st: enable ethernet1 controller on stm32mp235f-dk ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. Enable this peripheral on the stm32mp235f-dk board. Signed-off-by: Gatien Chevallier Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-4-05a060157fb7@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts index 04d1b434c433..29ccf8dab35e 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -19,6 +19,7 @@ / { compatible = "st,stm32mp235f-dk", "st,stm32mp235"; aliases { + ethernet0 = ðernet1; serial0 = &usart2; }; @@ -77,6 +78,28 @@ &arm_wdt { status = "okay"; }; +ðernet1 { + pinctrl-0 = <ð1_rgmii_pins_b>; + pinctrl-1 = <ð1_rgmii_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + phy-handle = <&phy1_eth1>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1_eth1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <1>; + reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt = <1800000>; From 7bfa81d4b299d236ddecbf9dc2fc097e585d5b36 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Wed, 10 Sep 2025 10:24:37 +0200 Subject: [PATCH 850/931] arm64: dts: st: remove gpioj and gpiok banks from stm32mp231 STM32MP23x supports AJ, AK and AL packages, where PI12 to PI15, PJ0 to PJ15 (whole J bank) and PK0 to PK7 (whole K bank) pins are not available. It means gpioj and gpiok nodes are useless in stm32mp231. Remove them. Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20250910-stm32mp231_gpio_update-v2-1-8510efa2c5cf@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp231.dtsi | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi index 75697acd1345..88e214d395ab 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -1064,28 +1064,6 @@ gpioi: gpio@442c0000 { st,bank-name = "GPIOI"; status = "disabled"; }; - - gpioj: gpio@442d0000 { - reg = <0x90000 0x400>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&scmi_clk CK_SCMI_GPIOJ>; - st,bank-name = "GPIOJ"; - status = "disabled"; - }; - - gpiok: gpio@442e0000 { - reg = <0xa0000 0x400>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&scmi_clk CK_SCMI_GPIOK>; - st,bank-name = "GPIOK"; - status = "disabled"; - }; }; rtc: rtc@46000000 { From 53c18dc078bb6d9e9dfe2cc0671ab78588c44723 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Wed, 10 Sep 2025 10:24:38 +0200 Subject: [PATCH 851/931] arm64: dts: st: fix memory region size on stm32mp235f-dk STM32MP23x SoCs provide a DDR controller supporting up to 4GB/16-bit. The control pin to properly configure 4GB/16-bit is not routed on stm32mp235f-dk, that's why the board only supports 2GB. Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20250910-stm32mp231_gpio_update-v2-2-8510efa2c5cf@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts index 29ccf8dab35e..c3e688068223 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -57,7 +57,7 @@ led-blue { memory@80000000 { device_type = "memory"; - reg = <0x0 0x80000000 0x1 0x0>; + reg = <0x0 0x80000000 0x0 0x80000000>; }; reserved-memory { From dfdbe4bf6ff386d96c1dc8c7407201d882fc4113 Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Tue, 16 Sep 2025 16:16:49 +0530 Subject: [PATCH 852/931] arm64: dts: qcom: lemans: Add SDHC controller and SDC pin configuration Introduce the SDHC v5 controller node for the Lemans platform. This controller supports either eMMC or SD-card, but only one can be active at a time. SD-card is the preferred configuration on Lemans targets, so describe this controller. Define the SDC interface pins including clk, cmd, and data lines to enable proper communication with the SDHC controller. Signed-off-by: Monish Chunara Reviewed-by: Konrad Dybcio Co-developed-by: Wasim Nazir Signed-off-by: Wasim Nazir Link: https://lore.kernel.org/r/20250916-lemans-evk-bu-v5-1-53d7d206669d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 92 ++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index fd6eb6fbe29a..b7e727f01cec 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -3835,6 +3835,58 @@ apss_tpdm2_out: endpoint { }; }; + sdhc: mmc@87c4000 { + compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x087c4000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>; + clock-names = "iface", + "core"; + + interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + iommus = <&apps_smmu 0x0 0x0>; + dma-coherent; + + operating-points-v2 = <&sdhc_opp_table>; + power-domains = <&rpmhpd SA8775P_CX>; + resets = <&gcc GCC_SDCC1_BCR>; + + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + + status = "disabled"; + + sdhc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1800000 400000>; + opp-avg-kBps = <100000 0>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <5400000 1600000>; + opp-avg-kBps = <390000 0>; + }; + }; + }; + usb_0_hsphy: phy@88e4000 { compatible = "qcom,sa8775p-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; @@ -5658,6 +5710,46 @@ qup_uart21_rx: qup-uart21-rx-pins { function = "qup3_se0"; }; }; + + sdc_default: sdc-default-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc_sleep: sdc-sleep-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-bus-hold; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-bus-hold; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-bus-hold; + }; + }; }; sram: sram@146d8000 { From 5bc646aa0c7a444d4e81d8e3cae4baf463e1a018 Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Tue, 16 Sep 2025 16:16:50 +0530 Subject: [PATCH 853/931] arm64: dts: qcom: lemans-evk: Enable GPI DMA and QUPv3 controllers Enable GPI DMA controllers (gpi_dma0, gpi_dma1, gpi_dma2) and QUPv3 interfaces (qupv3_id_0, qupv3_id_2) in the device tree to support DMA and peripheral communication on the Lemans EVK platform. qupv3_id_0 provides access to I2C/SPI/UART instances 0-5. qupv3_id_2 provides access to I2C/SPI/UART instances 14-20. Signed-off-by: Viken Dadhaniya Signed-off-by: Wasim Nazir Link: https://lore.kernel.org/r/20250916-lemans-evk-bu-v5-2-53d7d206669d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index f79e826bd5d4..4da2c5a12c1f 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -329,6 +329,18 @@ vreg_l8e: ldo8 { }; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + &mdss0 { status = "okay"; }; @@ -375,10 +387,18 @@ &mdss0_dp1_phy { status = "okay"; }; +&qupv3_id_0 { + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &sleep_clk { clock-frequency = <32768>; }; From 6ae6381f871803246e9f655537999f163656de33 Mon Sep 17 00:00:00 2001 From: Nirmesh Kumar Singh Date: Tue, 16 Sep 2025 16:16:51 +0530 Subject: [PATCH 854/931] arm64: dts: qcom: lemans-evk: Add TCA9534 I/O expander Integrate the TCA9534 I/O expander via I2C to provide 8 additional GPIO lines for extended I/O functionality. Signed-off-by: Nirmesh Kumar Singh Reviewed-by: Konrad Dybcio Reviewed-by: Bartosz Golaszewski Signed-off-by: Wasim Nazir Link: https://lore.kernel.org/r/20250916-lemans-evk-bu-v5-3-53d7d206669d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 32 +++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 4da2c5a12c1f..d1118818e2fd 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -341,6 +341,38 @@ &gpi_dma2 { status = "okay"; }; +&i2c18 { + status = "okay"; + + expander0: gpio@38 { + compatible = "ti,tca9538"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander1: gpio@39 { + compatible = "ti,tca9538"; + reg = <0x39>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander2: gpio@3a { + compatible = "ti,tca9538"; + reg = <0x3a>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander3: gpio@3b { + compatible = "ti,tca9538"; + reg = <0x3b>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + &mdss0 { status = "okay"; }; From 81618ba3fe33017be5e1fce99891abd220a775b8 Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Tue, 16 Sep 2025 16:16:52 +0530 Subject: [PATCH 855/931] arm64: dts: qcom: lemans-evk: Add EEPROM and nvmem layout Integrate the GT24C256C EEPROM via I2C to enable access to board-specific non-volatile data. Also, define an nvmem-layout to expose structured regions within the EEPROM, allowing consumers to retrieve configuration data such as Ethernet MAC addresses via the nvmem subsystem. Signed-off-by: Monish Chunara Reviewed-by: Konrad Dybcio Reviewed-by: Bartosz Golaszewski Signed-off-by: Wasim Nazir Link: https://lore.kernel.org/r/20250916-lemans-evk-bu-v5-4-53d7d206669d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index d1118818e2fd..97428d9e3e41 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -371,6 +371,18 @@ expander3: gpio@3b { #gpio-cells = <2>; gpio-controller; }; + + eeprom@50 { + compatible = "giantec,gt24c256c", "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; }; &mdss0 { From 94d7d37f6ac34bd683a93fbf1013736616fc3677 Mon Sep 17 00:00:00 2001 From: Sushrut Shree Trivedi Date: Tue, 16 Sep 2025 16:16:53 +0530 Subject: [PATCH 856/931] arm64: dts: qcom: lemans-evk: Enable PCIe support Enable PCIe0 and PCIe1 along with the respective phy-nodes. PCIe0 is routed to an m.2 E key connector on the mainboard for wifi attaches while PCIe1 routes to a standard PCIe x4 expansion slot. Signed-off-by: Sushrut Shree Trivedi Signed-off-by: Wasim Nazir Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250916-lemans-evk-bu-v5-5-53d7d206669d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 82 +++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 97428d9e3e41..99400ff12cfd 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -431,6 +431,40 @@ &mdss0_dp1_phy { status = "okay"; }; +&pcie0 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -447,6 +481,54 @@ &sleep_clk { clock-frequency = <32768>; }; +&tlmm { + pcie0_default_state: pcie0-default-state { + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + clkreq-pins { + pins = "gpio3"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio4"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + &uart10 { compatible = "qcom,geni-debug-uart"; pinctrl-0 = <&qup_uart10_default>; From cac44c46970adb4553bab5c5aa528462a5fe98d0 Mon Sep 17 00:00:00 2001 From: Wasim Nazir Date: Tue, 16 Sep 2025 16:16:54 +0530 Subject: [PATCH 857/931] arm64: dts: qcom: lemans-evk: Enable remoteproc subsystems Enable remoteproc subsystems for supported DSPs such as Audio DSP, Compute DSP-0/1 and Generic DSP-0/1, along with their corresponding firmware. Signed-off-by: Wasim Nazir Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250916-lemans-evk-bu-v5-6-53d7d206669d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 99400ff12cfd..d92c089eff39 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -477,6 +477,36 @@ &qupv3_id_2 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/sa8775p/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp0 { + firmware-name = "qcom/sa8775p/cdsp0.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp1 { + firmware-name = "qcom/sa8775p/cdsp1.mbn"; + + status = "okay"; +}; + +&remoteproc_gpdsp0 { + firmware-name = "qcom/sa8775p/gpdsp0.mbn"; + + status = "okay"; +}; + +&remoteproc_gpdsp1 { + firmware-name = "qcom/sa8775p/gpdsp1.mbn"; + + status = "okay"; +}; + &sleep_clk { clock-frequency = <32768>; }; From fd32b5d586ac650ce1c6f58535ec79cd2632be09 Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Tue, 16 Sep 2025 16:16:55 +0530 Subject: [PATCH 858/931] arm64: dts: qcom: lemans-evk: Enable Iris video codec support Enable the Iris video codec accelerator on the Lemans EVK board and reference the appropriate firmware required for its operation. This allows hardware-accelerated video encoding and decoding using the Iris codec engine. Signed-off-by: Vikash Garodia Reviewed-by: Konrad Dybcio Signed-off-by: Wasim Nazir Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250916-lemans-evk-bu-v5-7-53d7d206669d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index d92c089eff39..5e720074d48f 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -385,6 +385,12 @@ nvmem-layout { }; }; +&iris { + firmware-name = "qcom/vpu/vpu30_p4_s6_16mb.mbn"; + + status = "okay"; +}; + &mdss0 { status = "okay"; }; From 7bd68ef80661a9436120702e1300b56904fdd022 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Tue, 16 Sep 2025 16:16:56 +0530 Subject: [PATCH 859/931] arm64: dts: qcom: lemans-evk: Enable first USB controller in device mode Enable the first USB controller in device mode on the Lemans EVK board and configure the associated LDO regulators to power the PHYs accordingly. The USB port is a Type-C port controlled by HD3SS3320 port controller. The role switch notifications would need to be routed to glue driver by adding an appropriate usb-c-connector node in DT. However in the design, the vbus supply that is to be provided to connected peripherals when port is configured as an DFP, is controlled by a GPIO. There is also one ID line going from Port controller chip to GPIO-50 of the SoC. As per the datasheet of HD3SS3320: "Upon detecting a UFP device, HD3SS3220 will keep ID pin high if VBUS is not at VSafe0V. Once VBUS is at VSafe0V, the HD3SS3220 will assert ID pin low. This is done to enforce Type-C requirement that VBUS must be at VSafe0V before re-enabling VBUS." The current HD3SS3220 driver doesn't have this functionality present. So, putting the first USB controller in device mode for now. Once the vbus control based on ID pin is implemented in hd3ss3220.c, the usb-c-connector will be implemented and dr mode would be made OTG. Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Signed-off-by: Wasim Nazir Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250916-lemans-evk-bu-v5-8-53d7d206669d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 5e720074d48f..3a0376f399e0 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -590,6 +590,29 @@ &ufs_mem_phy { status = "okay"; }; +&usb_0 { + status = "okay"; +}; + +&usb_0_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_0_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l7a>; + + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; }; From c3f107b514c357cbc08ae70a69700222e7d1192d Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Tue, 16 Sep 2025 16:16:57 +0530 Subject: [PATCH 860/931] arm64: dts: qcom: lemans-evk: Enable SDHCI for SD Card Enable the SD Host Controller Interface (SDHCI) on the lemans EVK board to support SD card for storage. Also add the corresponding regulators. Signed-off-by: Monish Chunara Reviewed-by: Konrad Dybcio Signed-off-by: Wasim Nazir Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250916-lemans-evk-bu-v5-9-53d7d206669d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 45 +++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 3a0376f399e0..0170da9362ae 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -17,6 +17,7 @@ / { compatible = "qcom,lemans-evk", "qcom,qcs9100", "qcom,sa8775p"; aliases { + mmc1 = &sdhc; serial0 = &uart10; }; @@ -98,6 +99,28 @@ platform { }; }; }; + + vmmc_sdc: regulator-vmmc-sdc { + compatible = "regulator-fixed"; + + regulator-name = "vmmc_sdc"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + vreg_sdc: regulator-vreg-sdc { + compatible = "regulator-gpio"; + + regulator-name = "vreg_sdc"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + + gpios = <&expander1 7 GPIO_ACTIVE_HIGH>; + states = <1800000 1>, <2950000 0>; + + startup-delay-us = <100>; + }; }; &apps_rsc { @@ -513,6 +536,22 @@ &remoteproc_gpdsp1 { status = "okay"; }; +&sdhc { + vmmc-supply = <&vmmc_sdc>; + vqmmc-supply = <&vreg_sdc>; + + pinctrl-0 = <&sdc_default>, <&sd_cd>; + pinctrl-1 = <&sdc_sleep>, <&sd_cd>; + pinctrl-names = "default", "sleep"; + + bus-width = <4>; + cd-gpios = <&tlmm 36 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + + status = "okay"; +}; + &sleep_clk { clock-frequency = <32768>; }; @@ -563,6 +602,12 @@ wake-pins { bias-pull-up; }; }; + + sd_cd: sd-cd-state { + pins = "gpio36"; + function = "gpio"; + bias-pull-up; + }; }; &uart10 { From 71ee90ed1756724d62cb55873555e006372792c7 Mon Sep 17 00:00:00 2001 From: Mohd Ayaan Anwar Date: Tue, 16 Sep 2025 16:16:58 +0530 Subject: [PATCH 861/931] arm64: dts: qcom: lemans-evk: Enable 2.5G Ethernet interface Enable the QCA8081 2.5G Ethernet PHY on port 0. Add MDC and MDIO pin functions for ethernet0, and enable the internal SGMII/SerDes PHY node. Additionally, support fetching the MAC address from EEPROM via an nvmem cell. Signed-off-by: Mohd Ayaan Anwar Reviewed-by: Konrad Dybcio Signed-off-by: Wasim Nazir Link: https://lore.kernel.org/r/20250916-lemans-evk-bu-v5-10-53d7d206669d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 115 ++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 0170da9362ae..d5dbcbd86171 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -17,6 +17,7 @@ / { compatible = "qcom,lemans-evk", "qcom,qcs9100", "qcom,sa8775p"; aliases { + ethernet0 = ðernet0; mmc1 = &sdhc; serial0 = &uart10; }; @@ -352,6 +353,94 @@ vreg_l8e: ldo8 { }; }; +ðernet0 { + phy-handle = <&hsgmii_phy0>; + phy-mode = "2500base-x"; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + nvmem-cells = <&mac_addr0>; + nvmem-cell-names = "mac-address"; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + hsgmii_phy0: ethernet-phy@1c { + compatible = "ethernet-phy-id004d.d101"; + reg = <0x1c>; + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + &gpi_dma0 { status = "okay"; }; @@ -404,6 +493,10 @@ nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; #size-cells = <1>; + + mac_addr0: mac-addr@0 { + reg = <0x0 0x6>; + }; }; }; }; @@ -552,11 +645,33 @@ &sdhc { status = "okay"; }; +&serdes0 { + phy-supply = <&vreg_l5a>; + + status = "okay"; +}; + &sleep_clk { clock-frequency = <32768>; }; &tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio8"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio9"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + pcie0_default_state: pcie0-default-state { clkreq-pins { pins = "gpio1"; From 3bc3ff8fd2fe5886043b38d3d3c9d6ecb12d0a83 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 15 Sep 2025 23:24:15 -0500 Subject: [PATCH 862/931] dt-bindings: vendor-prefixes: Add Particle Industries Particle is a San Francisco-based company providing an integrated IoT Platform-as-a-Service. https://www.particle.io/ Acked-by: Rob Herring (Arm) Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20250915-tachyon-v2-1-4f8b02a17512@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b60957808e5f..50850df73187 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1181,6 +1181,8 @@ patternProperties: description: Parade Technologies Inc. "^parallax,.*": description: Parallax Inc. + "^particle,.*": + description: Particle Industries, Inc. "^pda,.*": description: Precision Design Associates, Inc. "^pegatron,.*": From b727cf24feb56a93f7bafbcdce7ea99b9ccb16cd Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 15 Sep 2025 23:24:16 -0500 Subject: [PATCH 863/931] dt-bindings: arm: qcom: Add Particle Tachyon The Particle Tachyon is a single board computer with 5G connectivity with AI accelerator, based on the Qualcomm QCM6490 platform. Document the top-level compatible for this board. Acked-by: Rob Herring (Arm) Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20250915-tachyon-v2-2-4f8b02a17512@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index cf49dd0000e0..0a05426acb6a 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -331,6 +331,7 @@ properties: - items: - enum: - fairphone,fp5 + - particle,tachyon - qcom,qcm6490-idp - qcom,qcs6490-rb3gen2 - shift,otter From a319cf4a4b09a1dd3b2652fc96f4f08c0647ae64 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 15 Sep 2025 23:24:17 -0500 Subject: [PATCH 864/931] arm64: dts: qcom: qcm6490: Introduce the Particle Tachyon The Particle Tachyon is a single board computer with 5G connectivity with AI accelerator, based on the Qualcomm QCM6490 platform. Introduce the board, with support for UFS, USB, USB Type-C PD and altmode (DisplayPort), GPU, charger/battery status, PCIe shield, SD-card, and remoteprocs. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20250915-tachyon-v2-3-4f8b02a17512@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/qcm6490-particle-tachyon.dts | 864 ++++++++++++++++++ 2 files changed, 865 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 5b52f9e4e5f3..76d275991e83 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -116,6 +116,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-fairphone-fp5.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcm6490-particle-tachyon.dtb dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts new file mode 100644 index 000000000000..251e72f11428 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -0,0 +1,864 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Copyright (c) 2023, Luca Weiss + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "sc7280.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" + +/delete-node/ &ipa_fw_mem; +/delete-node/ &rmtfs_mem; +/delete-node/ &xbl_mem; +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &wpss_mem; + +/ { + model = "Particle Tachyon"; + compatible = "particle,tachyon", "qcom,qcm6490"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart5; + serial1 = &uart12; + serial2 = &uart7; + serial3 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&activity_led_state>; + pinctrl-names = "default"; + + led-activity { + function = LED_FUNCTION_ACTIVITY; + color = ; + gpios = <&tlmm 14 GPIO_ACTIVE_HIGH>; + default-state = "on"; + panic-indicator; + }; + }; + + pmic-glink { + compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu_in: endpoint { + remote-endpoint = <&usbdp_sbu_mux>; + }; + }; + }; + }; + }; + + vreg_power_5v: regulator-power-5v { + compatible = "regulator-fixed"; + regulator-name = "power_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&tlmm 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + reserved-memory { + xbl_mem: xbl@80700000 { + reg = <0x0 0x80700000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat@c0000000 { + reg = <0x0 0xc0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@c0100000 { + reg = <0x0 0xc0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@c1300000 { + reg = <0x0 0xc1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@c1800000 { + reg = <0x0 0xc1800000 0x0 0x1c00000>; + no-map; + }; + + debug_vm_mem: debug-vm@d0600000 { + reg = <0x0 0xd0600000 0x0 0x100000>; + no-map; + }; + + adsp_mem: adsp@86100000 { + reg = <0x0 0x86700000 0x0 0x2800000>; + no-map; + }; + + cdsp_mem: cdsp@88900000 { + reg = <0x0 0x88f00000 0x0 0x1e00000>; + no-map; + }; + + wpss_mem: wpss@9ae00000 { + reg = <0x0 0x9ae00000 0x0 0x1900000>; + no-map; + }; + + mpss_mem: mpss@8b800000 { + reg = <0x0 0x8b800000 0x0 0xf600000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@8b300000 { + reg = <0x0 0x8b700000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@8b310000 { + reg = <0x0 0x8b710000 0x0 0xa000>; + no-map; + }; + + rmtfs_mem: memory@f8500000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xf8500000 0x0 0x600000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = , ; + }; + }; + + + usbdp-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 108 GPIO_ACTIVE_HIGH>; + select-gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usbdp_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usbdp_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu_in>; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>; + vdd-l2-l7-supply = <&vreg_bob_3p296>; + vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>; + vdd-l8-supply = <&vreg_s7b_0p972>; + vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>; + vdd-l13-supply = <&vreg_s7b_0p972>; + vdd-l14-l16-supply = <&vreg_s8b_1p272>; + + vreg_s1b_1p872: smps1 { + regulator-name = "vreg_s1b_1p872"; + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7b_0p972: smps7 { + regulator-name = "vreg_s7b_0p972"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s8b_1p272: smps8 { + regulator-name = "vreg_s8b_1p272"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = ; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p504: ldo3 { + regulator-name = "vreg_l3b_0p504"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <910000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p952: ldo7 { + regulator-name = "vreg_l7b_2p952"; + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = ; + }; + + vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11b_1p504: ldo11 { + regulator-name = "vreg_l11b_1p504"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l12b_0p751: ldo12 { + regulator-name = "vreg_l12b_0p751"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l13b_0p53: ldo13 { + regulator-name = "vreg_l13b_0p53"; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l14b_1p08: ldo14 { + regulator-name = "vreg_l14b_1p08"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l15b_0p765: ldo15 { + regulator-name = "vreg_l15b_0p765"; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + regulator-initial-mode = ; + }; + + vreg_l16b_1p1: ldo16 { + regulator-name = "vreg_l16b_1p1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_l17b_1p7: ldo17 { + regulator-name = "vreg_l17b_1p7"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l12-supply = <&vreg_s1b_1p872>; + vdd-l2-l8-supply = <&vreg_s1b_1p872>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>; + vdd-l6-l9-l11-supply = <&vreg_bob_3p296>; + vdd-l10-supply = <&vreg_s7b_0p972>; + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_2p19: smps1 { + regulator-name = "vreg_s1c_2p19"; + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + }; + + vreg_s9c_1p084: smps9 { + regulator-name = "vreg_s9c_1p084"; + regulator-min-microvolt = <1084000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p62: ldo2 { + regulator-name = "vreg_l2c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l3c_2p8: ldo3 { + regulator-name = "vreg_l3c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3540000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p62: ldo4 { + regulator-name = "vreg_l4c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p62: ldo5 { + regulator-name = "vreg_l5c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p62: ldo8 { + regulator-name = "vreg_l8c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + }; + + vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p65: ldo12 { + regulator-name = "vreg_l12c_1p65"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l13c_2p7: ldo13 { + regulator-name = "vreg_l13c_2p7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + + status = "okay"; +}; + +&ipa { + firmware-name = "qcom/qcm6490/particle/tachyon/ipa_fws.mbn"; + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + + status = "okay"; +}; + +&gcc { + protected-clocks = , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcm6490/particle/tachyon/a660_zap.mbn"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp { + status = "okay"; +}; + +&mdss_dp_out { + data-lanes = <0 1>; +}; + +&pcie0 { + perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; + pinctrl-names = "default"; + + vddpe-3v3-supply = <&vreg_power_5v>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pmk8350_vadc { + status = "okay"; + + channel@44 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pmk8350_xo_therm"; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcm6490/particle/tachyon/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcm6490/particle/tachyon/cdsp.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/qcm6490/particle/tachyon/modem.mbn"; + status = "okay"; +}; + +&sdc2_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc2_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc2_data { + bias-pull-up; + drive-strength = <10>; +}; + +&sdhc_2 { + vmmc-supply = <&vreg_l9c_2p96>; + vqmmc-supply = <&vreg_l6c_2p96>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&tlmm { + activity_led_state: activity-led-state { + pins = "gpio14"; + function = "gpio"; + bias-disable; + }; + + bt_en_state: bt-default-state { + pins = "gpio84"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-pull-up; + }; + + pcie0_reset_n: pcie0-reset-n-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-disable; + }; + + pcie0_wake_n: pcie0-wake-n-state { + pins = "gpio89"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie1_reset_n: pcie1-reset-n-state { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-disable; + }; + + pcie1_wake_n: pcie1-wake-n-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; + }; + + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + usbdp_sbu_default: usbdp-sbu-state { + oe-n-pins { + pins = "gpio108"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + output-high; + }; + + sel-pins { + pins = "gpio42"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + }; + + wlan_en_state: wlan-default-state { + pins = "gpio85"; + function = "gpio"; + drive-strength = <16>; + output-low; + bias-pull-up; + }; +}; + +&uart5 { + status = "okay"; +}; + +&uart7 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-1 = <&qup_uart7_sleep_cts>, + <&qup_uart7_sleep_rts>, + <&qup_uart7_sleep_tx>, + <&qup_uart7_sleep_rx>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&uart8 { + status = "okay"; +}; + +&uart12 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l7b_2p952>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; + vccq2-supply = <&vreg_l9b_1p2>; + vccq2-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&usb_1 { + dr_mode = "otg"; + usb-role-switch; + + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda33-supply = <&vreg_l2b_3p072>; + vdda18-supply = <&vreg_l1c_1p8>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p912>; + + status = "okay"; +}; + +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p072>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; From 9feef33b3f18eb370364a5838ed14baba10f3368 Mon Sep 17 00:00:00 2001 From: Alok Tiwari Date: Mon, 15 Sep 2025 13:01:26 -0700 Subject: [PATCH 865/931] arm64: dts: qcom: sm8150: Fix reg base of frame@17c27000 The frame@17c27000 node uses the wrong base address 0x17c26000. This does not match the node name. Update the reg property to use the correct base address 0x17c27000, which matches the node name and avoids the overlap. Fixes: e13c6d144fa0 ("arm64: dts: qcom: sm8150: Add base dts file") Signed-off-by: Alok Tiwari Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250915200132.774377-1-alok.a.tiwari@oracle.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 6860816db6d2..37478c76acee 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -4420,7 +4420,7 @@ frame@17c25000 { frame@17c27000 { frame-number = <3>; interrupts = ; - reg = <0x17c26000 0x1000>; + reg = <0x17c27000 0x1000>; status = "disabled"; }; From 99b78773c2ae55dcc01025f94eae8ce9700ae985 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 15 Sep 2025 15:28:30 +0200 Subject: [PATCH 866/931] arm64: dts: qcom: msm8916: Add missing MDSS reset On most MSM8916 devices (aside from the DragonBoard 410c), the bootloader already initializes the display to show the boot splash screen. In this situation, MDSS is already configured and left running when starting Linux. To avoid side effects from the bootloader configuration, the MDSS reset can be specified in the device tree to start again with a clean hardware state. The reset for MDSS is currently missing in msm8916.dtsi, which causes errors when the MDSS driver tries to re-initialize the registers: dsi_err_worker: status=6 dsi_err_worker: status=6 dsi_err_worker: status=6 ... It turns out that we have always indirectly worked around this by building the MDSS driver as a module. Before v6.17, the power domain was temporarily turned off until the module was loaded, long enough to clear the register contents. In v6.17, power domains are not turned off during boot until sync_state() happens, so this is no longer working. Even before v6.17 this resulted in broken behavior, but notably only when the MDSS driver was built-in instead of a module. Cc: stable@vger.kernel.org Fixes: 305410ffd1b2 ("arm64: dts: msm8916: Add display support") Signed-off-by: Stephan Gerhold Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250915-msm8916-resets-v1-1-a5c705df0c45@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index b50c7e6e0bfc..de0c10b54c86 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1562,6 +1562,8 @@ mdss: display-subsystem@1a00000 { interrupts = ; + resets = <&gcc GCC_MDSS_BCR>; + interrupt-controller; #interrupt-cells = <1>; From f73c82c855e186e9b67125e3eee743960320e43c Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 15 Sep 2025 15:28:31 +0200 Subject: [PATCH 867/931] arm64: dts: qcom: msm8939: Add missing MDSS reset On most MSM8939 devices, the bootloader already initializes the display to show the boot splash screen. In this situation, MDSS is already configured and left running when starting Linux. To avoid side effects from the bootloader configuration, the MDSS reset can be specified in the device tree to start again with a clean hardware state. The reset for MDSS is currently missing in msm8939.dtsi, which causes errors when the MDSS driver tries to re-initialize the registers: dsi_err_worker: status=6 dsi_err_worker: status=6 dsi_err_worker: status=6 ... It turns out that we have always indirectly worked around this by building the MDSS driver as a module. Before v6.17, the power domain was temporarily turned off until the module was loaded, long enough to clear the register contents. In v6.17, power domains are not turned off during boot until sync_state() happens, so this is no longer working. Even before v6.17 this resulted in broken behavior, but notably only when the MDSS driver was built-in instead of a module. Cc: stable@vger.kernel.org Fixes: 61550c6c156c ("arm64: dts: qcom: Add msm8939 SoC") Signed-off-by: Stephan Gerhold Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250915-msm8916-resets-v1-2-a5c705df0c45@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 68b92fdb996c..eb64ec35e7f0 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -1249,6 +1249,8 @@ mdss: display-subsystem@1a00000 { power-domains = <&gcc MDSS_GDSC>; + resets = <&gcc GCC_MDSS_BCR>; + #address-cells = <1>; #size-cells = <1>; #interrupt-cells = <1>; From 456dcaf570043e60978352da9b2a55d067fd290b Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 15 Sep 2025 15:28:32 +0200 Subject: [PATCH 868/931] arm64: dts: qcom: msm8916: Add SDCC resets Add the missing resets for the two SDCC controllers to allow fully resetting previous hardware state from the bootloader. Signed-off-by: Stephan Gerhold Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250915-msm8916-resets-v1-3-a5c705df0c45@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index de0c10b54c86..d3a25a837488 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -2127,6 +2127,7 @@ sdhc_1: mmc@7824900 { <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC1_BCR>; pinctrl-0 = <&sdc1_default>; pinctrl-1 = <&sdc1_sleep>; pinctrl-names = "default", "sleep"; @@ -2148,6 +2149,7 @@ sdhc_2: mmc@7864900 { <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; pinctrl-0 = <&sdc2_default>; pinctrl-1 = <&sdc2_sleep>; pinctrl-names = "default", "sleep"; From 893e2abc1ae35f67f29909cd062cff978bf26b44 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 15 Sep 2025 12:06:12 +0200 Subject: [PATCH 869/931] arm64: dts: qcom: sm8550/sm8650: Fix typo in IRIS comment It should be "enable on boards", not "enable in boards". Reported-by: Alexey Klimov Closes: https://lore.kernel.org/r/DCQ8G73ISXHC.3V03MOGB6NDZE@linaro.org/ Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250915-x1e-iris-dt-v2-1-1f928de08fd4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 2df6ba05e0cd..ec67efd64b78 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3262,7 +3262,7 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, /* * IRIS firmware is signed by vendors, only - * enable in boards where the proper signed firmware + * enable on boards where the proper signed firmware * is available. */ status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 367f448a743a..e7582a19184b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5186,7 +5186,7 @@ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, /* * IRIS firmware is signed by vendors, only - * enable in boards where the proper signed firmware + * enable on boards where the proper signed firmware * is available. */ status = "disabled"; From 9065340ac04dd8a1b07da0f024aa3a1e4dd2cffb Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 15 Sep 2025 12:06:13 +0200 Subject: [PATCH 870/931] arm64: dts: qcom: x1e80100: Add IRIS video codec Add the IRIS video codec to accelerate video decoding/encoding. Copied mostly from sm8550.dtsi, only the opp-table is slightly different for X1E. For opp-240000000, we need to vote for a higher OPP on one of the power domains, because the voltage requirements for the PLL and the derived clocks differ (sm8550.dtsi has the same). Reviewed-by: Bryan O'Donoghue Tested-by: Bryan O'Donoghue # x1e Inspiron 14p Tested-by: Neil Armstrong # on Thinkpad T14S OLED Tested-by: Anthony Ruhier # Lenovo Slim 7x Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20250915-x1e-iris-dt-v2-2-1f928de08fd4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 87 ++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index ba602eddfb54..a6305077f150 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5234,6 +5234,93 @@ usb_1_ss1_dwc3_ss: endpoint { }; }; + iris: video-codec@aa00000 { + compatible = "qcom,x1e80100-iris", "qcom,sm8550-iris"; + + reg = <0 0x0aa00000 0 0xf0000>; + interrupts = ; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", + "vcodec0", + "mxc", + "mmcx"; + operating-points-v2 = <&iris_opp_table>; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names = "iface", + "core", + "vcodec0_core"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + memory-region = <&video_mem>; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; + reset-names = "bus"; + + iommus = <&apps_smmu 0x1940 0>, + <&apps_smmu 0x1947 0>; + dma-coherent; + + /* + * IRIS firmware is signed by vendors, only + * enable on boards where the proper signed firmware + * is available. + */ + status = "disabled"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_nom>; + }; + + opp-481000000 { + opp-hz = /bits/ 64 <481000000>; + required-opps = <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + }; + }; + videocc: clock-controller@aaf0000 { compatible = "qcom,x1e80100-videocc"; reg = <0 0x0aaf0000 0 0x10000>; From c0f045e303e014cec5d883edf82fe5de74769944 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 15 Sep 2025 12:06:14 +0200 Subject: [PATCH 871/931] arm64: dts: qcom: x1-el2: Disable IRIS for now The reset and IOMMU management for remoteprocs like IRIS is implemented in the hypervisor for older targets such as X1E [1]. When booting Linux/KVM directly in EL2, this functionality is missing and the PAS interface normally used by IRIS to boot the video firmware is not working. The Venus driver supports starting the video firmware without using the PAS interface. The same code also works for X1E when using KVM. However, for the new IRIS dt-bindings it was decided to avoid using the dummy "video-firmware" node in the device tree to describe the IOMMU [2]. Discussion is still ongoing how to describe this properly [3]. To avoid regressions when running using KVM, add a TODO in x1-el2.dtso for now and disable IRIS even when it was enabled by the board. [1]: https://resources.linaro.org/en/resource/sF8jXifdb9V1mUefdbfafa [2]: https://lore.kernel.org/r/20250823155349.22344-2-krzysztof.kozlowski@linaro.org/ [3]: https://lore.kernel.org/r/20250819165447.4149674-12-mukesh.ojha@oss.qualcomm.com/ Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250915-x1e-iris-dt-v2-3-1f928de08fd4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-el2.dtso | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-el2.dtso b/arch/arm64/boot/dts/qcom/x1-el2.dtso index 380441deca65..2d1c9151cf1b 100644 --- a/arch/arm64/boot/dts/qcom/x1-el2.dtso +++ b/arch/arm64/boot/dts/qcom/x1-el2.dtso @@ -12,6 +12,11 @@ &gpu_zap_shader { status = "disabled"; }; +&iris { + /* TODO: Add video-firmware iommus to start IRIS from EL2 */ + status = "disabled"; +}; + /* * When running under Gunyah, this IOMMU is controlled by the firmware, * however when we take ownership of it in EL2, we need to configure From e2367a67b3de64e1972cd6fdb8029c974fc3b2fc Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 15 Sep 2025 12:06:15 +0200 Subject: [PATCH 872/931] arm64: dts: qcom: x1e80100-crd: Enable IRIS video codec IRIS firmware for x1e80100-crd is already upstream in linux-firmware in the default path, so enable IRIS for the CRD to accelerate video decoding. It looks like the X1P CRD might need a different IRIS firmware (possibly even changes in the Linux kernel driver), so keep it local to the X1E CRD for now. Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Tested-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250915-x1e-iris-dt-v2-4-1f928de08fd4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index 976b8e44b576..dfc378e1a056 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -16,3 +16,7 @@ / { &gpu_zap_shader { firmware-name = "qcom/x1e80100/gen70500_zap.mbn"; }; + +&iris { + status = "okay"; +}; From ee2d56bb33d5fe17155e933326fb0f9b7ff1d034 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 15 Sep 2025 12:06:16 +0200 Subject: [PATCH 873/931] arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: Enable IRIS IRIS firmware for the Lenovo ThinkPad T14s is already upstream in linux-firmware at qcom/x1e80100/LENOVO/21N1/qcvss8380.mbn, so enable IRIS for the T14s with the corresponding firmware-name property. Tested-by: Neil Armstrong # on Thinkpad T14S OLED Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250915-x1e-iris-dt-v2-5-1f928de08fd4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 23213b0d9582..0a989e9d3d23 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -967,6 +967,11 @@ touchscreen@10 { /* TODO: second-sourced touchscreen @ 0x41 */ }; +&iris { + firmware-name = "qcom/x1e80100/LENOVO/21N1/qcvss8380.mbn"; + status = "okay"; +}; + &lpass_tlmm { spkr_01_sd_n_active: spkr-01-sd-n-active-state { pins = "gpio12"; From 98180f6796925abdfce26e44671048fd05387190 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 15 Sep 2025 12:06:17 +0200 Subject: [PATCH 874/931] arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Enable IRIS IRIS firmware for the Lenovo Yoga Slim 7x is already upstream in linux-firmware at qcom/x1e80100/LENOVO/83ED/qcvss8380.mbn, so enable IRIS for the Slim 7x with the corresponding firmware-name property. Tested-by: Anthony Ruhier Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250915-x1e-iris-dt-v2-6-1f928de08fd4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index dae616cd93bd..e0642fe8343f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -1026,6 +1026,11 @@ touchscreen@14 { }; }; +&iris { + firmware-name = "qcom/x1e80100/LENOVO/83ED/qcvss8380.mbn"; + status = "okay"; +}; + &lpass_tlmm { spkr_01_sd_n_active: spkr-01-sd-n-active-state { pins = "gpio12"; From 647198bd7101cd399b3dbae96630d72db68b8752 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 15 Sep 2025 12:06:18 +0200 Subject: [PATCH 875/931] arm64: dts: qcom: x1e80100-dell-inspiron-14-plus-7441: Enable IRIS Enable IRIS to allow using the hardware-accelerated video codecs. The firmware is not upstream in linux-firmware yet, so users need to copy it from Windows to qcom/x1e80100/dell/inspiron-14-plus-7441/qcvss8380.mbn (just like GPU/ADSP/CDSP firmware). Signed-off-by: Stephan Gerhold Tested-by: Bryan O'Donoghue Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250915-x1e-iris-dt-v2-7-1f928de08fd4@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts index f728d298c72f..cf2a7c262888 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-inspiron-14-plus-7441.dts @@ -37,6 +37,11 @@ touchscreen@10 { }; }; +&iris { + firmware-name = "qcom/x1e80100/dell/inspiron-14-plus-7441/qcvss8380.mbn"; + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/x1e80100/dell/inspiron-14-plus-7441/qcadsp8380.mbn", "qcom/x1e80100/dell/inspiron-14-plus-7441/adsp_dtbs.elf"; From a80ead38c51e93ed6f19733f2cbdb93abab4dbf8 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 15 Sep 2025 12:06:19 +0200 Subject: [PATCH 876/931] arm64: dts: qcom: x1e80100-dell-latitude-7455: Enable IRIS Enable IRIS to allow using the hardware-accelerated video codecs. The firmware is not upstream in linux-firmware yet, so users need to copy it from Windows to qcom/x1e80100/dell/latitude-7455/qcvss8380.mbn (just like GPU/ADSP/CDSP firmware). Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250915-x1e-iris-dt-v2-8-1f928de08fd4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts index ace2a905e443..32ad9679550e 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-latitude-7455.dts @@ -38,6 +38,11 @@ touchscreen@9 { }; }; +&iris { + firmware-name = "qcom/x1e80100/dell/latitude-7455/qcvss8380.mbn"; + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/x1e80100/dell/latitude-7455/qcadsp8380.mbn", "qcom/x1e80100/dell/latitude-7455/adsp_dtbs.elf"; From c4376ad753566e44f8e9198b7f05f79145419cd3 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 15 Sep 2025 12:06:20 +0200 Subject: [PATCH 877/931] arm64: dts: qcom: x1e80100-dell-xps13-9345: Enable IRIS Enable IRIS to allow using the hardware-accelerated video codecs. The firmware is not upstream in linux-firmware yet, so users need to copy it from Windows to qcom/x1e80100/dell/xps13-9345/qcvss8380.mbn (just like GPU/ADSP/CDSP firmware). Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250915-x1e-iris-dt-v2-9-1f928de08fd4@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index 19a2604038a8..58f8caaa7258 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -875,6 +875,11 @@ touchpad@2c { }; }; +&iris { + firmware-name = "qcom/x1e80100/dell/xps13-9345/qcvss8380.mbn"; + status = "okay"; +}; + &mdss { status = "okay"; }; From 435712ac13a58ba006af741b8d759034a69b808d Mon Sep 17 00:00:00 2001 From: Vandhiadevan Karunamoorthy Date: Mon, 15 Sep 2025 13:24:18 +0400 Subject: [PATCH 878/931] arm64: dts: qcom: ipq5018: add QUP3 I2C node Add node to support I2C bus inside of IPQ5018. Signed-off-by: Vandhiadevan Karunamoorthy Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20250915-ipq5018-i2c-v1-1-46bbf27396d6@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index e88b52006566..5ba33255659e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -504,6 +504,21 @@ blsp1_spi1: spi@78b5000 { status = "disabled"; }; + blsp1_i2c3: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + dmas = <&blsp_dma 9>, <&blsp_dma 8>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + qpic_bam: dma-controller@7984000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x07984000 0x1c000>; From a58d6100ee2c4a732fb4e1520885958480a82110 Mon Sep 17 00:00:00 2001 From: Jens Glathe Date: Mon, 15 Sep 2025 09:35:04 +0200 Subject: [PATCH 879/931] dt-bindings: arm: qcom: Add HP Omnibook X14 AI X1P4200 variant The HP Omnibook X14 AI PC is available in fe0 (Hamoa, x1e80100) and fe1 (Purwa, x1p42100) SKUs. Since they are not completely dtb-compatible, add another variant: hp,omnibook-x14-fe1 compatible to cqom,x1p42100 Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jens Glathe Link: https://lore.kernel.org/r/20250915-hp-x14-x1p-v9-1-fa457ca30ffe@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 0a05426acb6a..68cc458ca6bf 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1072,6 +1072,7 @@ properties: - items: - enum: - asus,zenbook-a14-ux3407qa + - hp,omnibook-x14-fe1 - lenovo,thinkbook-16 - qcom,x1p42100-crd - const: qcom,x1p42100 From 72b50c2fd887f632501ce69e03d8e6bb35c8a1e8 Mon Sep 17 00:00:00 2001 From: Jens Glathe Date: Mon, 15 Sep 2025 09:35:05 +0200 Subject: [PATCH 880/931] arm64: dts: qcom: x1-hp-x14: Unify HP Omnibook X14 device tree structure Extract common elements into a shared .dtsi file for HP Omnibook X14 to support both Hamoa (x1e*/x1p6*) and Purwa (x1p4*/x1*) variants. Required because the device trees are not compatible. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Jens Glathe Link: https://lore.kernel.org/r/20250915-hp-x14-x1p-v9-2-fa457ca30ffe@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/x1-hp-omnibook-x14.dtsi | 1544 +++++++++++++++++ .../dts/qcom/x1e80100-hp-omnibook-x14.dts | 1544 +---------------- 2 files changed, 1548 insertions(+), 1540 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi diff --git a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi new file mode 100644 index 000000000000..a4075434162a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi @@ -0,0 +1,1544 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Xilin Wu + */ + +#include +#include +#include +#include +#include + +/ { + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 5000000>; + + brightness-levels = <0 2048 4096 8192 16384 65535>; + num-interpolated-steps = <20>; + default-brightness-level = <80>; + + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_bl>; + + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; + pinctrl-names = "default"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + /* Left-side port, closer to the screen */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + /* Left-side port, farther from the screen */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_sbu: endpoint { + remote-endpoint = <&usb_1_ss1_sbu_mux>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound: sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-HP-OMNIBOOK-X14"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VBL9"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_reg_en>; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&misc_3p3_reg_en>; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vreg_vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the CRD mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + wcn6855-pmu { + compatible = "qcom,wcn6855-pmu"; + + vddaon-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_wcn_1p9>; + vddpcie1p3-supply = <&vreg_wcn_1p9>; + vddpcie1p9-supply = <&vreg_wcn_1p9>; + vddpmu-supply = <&vreg_wcn_0p95>; + vddpmumx-supply = <&vreg_wcn_0p95>; + vddpmucx-supply = <&vreg_wcn_0p95>; + vddrfa0p95-supply = <&vreg_wcn_0p95>; + vddrfa1p3-supply = <&vreg_wcn_1p9>; + vddrfa1p9-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn_0p8: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn_0p8"; + }; + + vreg_pmu_aon_0p8: ldo1 { + regulator-name = "vreg_pmu_aon_0p8"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p8: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p8"; + }; + + vreg_pmu_btcmx_0p8: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p8"; + }; + + vreg_pmu_pcie_1p8: ldo5 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo6 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_rfa_0p8: ldo7 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo8 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo9 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + }; + }; + + usb-1-ss1-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss1_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss1_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss1_sbu>; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vreg_vph_pwr>; + vdd-bob2-supply = <&vreg_vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name = "vreg_l5b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name = "vreg_l16b_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vreg_vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vreg_vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vreg_vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1f_1p0: ldo1 { + regulator-name = "vreg_l1f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l2f_1p0: ldo2 { + regulator-name = "vreg_l2f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l3f_1p0: ldo3 { + regulator-name = "vreg_l3f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vreg_vph_pwr>; + vdd-s2-supply = <&vreg_vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vreg_vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_1p8>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + backlight = <&backlight>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; + }; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_8_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + drive-push-pull; + input-disable; + output-enable; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; /* 1.8V */ + input-disable; + output-enable; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio10"; + function = "normal"; + }; + +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmk8550_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio5"; + function = "func3"; + }; +}; + +&pmk8550_pwm { + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&swr0 { + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + status = "okay"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>, /* SPI (TPM) */ + <72 2>, /* Secure EC I2C connection (?) */ + <238 1>; /* UFS Reset */ + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-pull-up; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-pull-up; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-pull-up; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; + + usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { + mode-pins { + pins = "gpio177"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-high; + }; + + oe-n-pins { + pins = "gpio179"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio178"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn6855-bt"; + max-speed = <3200000>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; + vddaon-supply = <&vreg_pmu_aon_0p8>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_dwc3 { + phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>; + phy-names = "usb2-0", "usb3-0"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts index 716205b437df..e5a839d45840 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-hp-omnibook-x14.dts @@ -6,1222 +6,18 @@ /dts-v1/; -#include -#include -#include -#include -#include - #include "x1e80100.dtsi" #include "x1e80100-pmics.dtsi" +#include "x1-hp-omnibook-x14.dtsi" / { - model = "HP Omnibook X 14"; + model = "HP Omnibook X 14-fe0"; compatible = "hp,omnibook-x14", "qcom,x1e80100"; chassis-type = "laptop"; - - aliases { - serial0 = &uart21; - serial1 = &uart14; - }; - - wcd938x: audio-codec { - compatible = "qcom,wcd9385-codec"; - - pinctrl-names = "default"; - pinctrl-0 = <&wcd_default>; - - qcom,micbias1-microvolt = <1800000>; - qcom,micbias2-microvolt = <1800000>; - qcom,micbias3-microvolt = <1800000>; - qcom,micbias4-microvolt = <1800000>; - qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; - qcom,mbhc-headset-vthreshold-microvolt = <1700000>; - qcom,mbhc-headphone-vthreshold-microvolt = <50000>; - qcom,rx-device = <&wcd_rx>; - qcom,tx-device = <&wcd_tx>; - - reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; - - vdd-buck-supply = <&vreg_l15b_1p8>; - vdd-rxtx-supply = <&vreg_l15b_1p8>; - vdd-io-supply = <&vreg_l15b_1p8>; - vdd-mic-bias-supply = <&vreg_bob1>; - - #sound-dai-cells = <1>; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pmk8550_pwm 0 5000000>; - - brightness-levels = <0 2048 4096 8192 16384 65535>; - num-interpolated-steps = <20>; - default-brightness-level = <80>; - - enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; - power-supply = <&vreg_edp_bl>; - - pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; - pinctrl-names = "default"; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&hall_int_n_default>; - pinctrl-names = "default"; - - switch-lid { - gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - wakeup-source; - wakeup-event-action = ; - }; - }; - - pmic-glink { - compatible = "qcom,x1e80100-pmic-glink", - "qcom,sm8550-pmic-glink", - "qcom,pmic-glink"; - orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, - <&tlmm 123 GPIO_ACTIVE_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - - /* Left-side port, closer to the screen */ - connector@0 { - compatible = "usb-c-connector"; - reg = <0>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_ss0_hs_in: endpoint { - remote-endpoint = <&usb_1_ss0_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss0_ss_in: endpoint { - remote-endpoint = <&retimer_ss0_ss_out>; - }; - }; - - port@2 { - reg = <2>; - - pmic_glink_ss0_con_sbu_in: endpoint { - remote-endpoint = <&retimer_ss0_con_sbu_out>; - }; - }; - }; - }; - - /* Left-side port, farther from the screen */ - connector@1 { - compatible = "usb-c-connector"; - reg = <1>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_ss1_hs_in: endpoint { - remote-endpoint = <&usb_1_ss1_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss1_ss_in: endpoint { - remote-endpoint = <&usb_1_ss1_qmpphy_out>; - }; - }; - - port@2 { - reg = <2>; - - pmic_glink_ss1_sbu: endpoint { - remote-endpoint = <&usb_1_ss1_sbu_mux>; - }; - }; - }; - }; - }; - - reserved-memory { - linux,cma { - compatible = "shared-dma-pool"; - size = <0x0 0x8000000>; - reusable; - linux,cma-default; - }; - }; - - sound: sound { - compatible = "qcom,x1e80100-sndcard"; - model = "X1E80100-HP-OMNIBOOK-X14"; - audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", - "SpkrRight IN", "WSA WSA_SPK2 OUT", - "IN1_HPHL", "HPHL_OUT", - "IN2_HPHR", "HPHR_OUT", - "AMIC2", "MIC BIAS2", - "VA DMIC0", "MIC BIAS3", - "VA DMIC1", "MIC BIAS3", - "VA DMIC2", "MIC BIAS1", - "VA DMIC3", "MIC BIAS1", - "VA DMIC0", "VA MIC BIAS3", - "VA DMIC1", "VA MIC BIAS3", - "VA DMIC2", "VA MIC BIAS1", - "VA DMIC3", "VA MIC BIAS1", - "TX SWR_INPUT1", "ADC2_OUTPUT"; - - wcd-playback-dai-link { - link-name = "WCD Playback"; - - cpu { - sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; - }; - - codec { - sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - - wcd-capture-dai-link { - link-name = "WCD Capture"; - - cpu { - sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; - }; - - codec { - sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - - wsa-dai-link { - link-name = "WSA Playback"; - - cpu { - sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; - }; - - codec { - sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&lpass_wsamacro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - - va-dai-link { - link-name = "VA Capture"; - - cpu { - sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; - }; - - codec { - sound-dai = <&lpass_vamacro 0>; - }; - - platform { - sound-dai = <&q6apm>; - }; - }; - }; - - vreg_edp_3p3: regulator-edp-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_EDP_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&edp_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_edp_bl: regulator-edp-bl { - compatible = "regulator-fixed"; - - regulator-name = "VBL9"; - regulator-min-microvolt = <3600000>; - regulator-max-microvolt = <3600000>; - - gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&edp_bl_reg_en>; - - regulator-boot-on; - }; - - vreg_misc_3p3: regulator-misc-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_MISC_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&misc_3p3_reg_en>; - - regulator-boot-on; - regulator-always-on; - }; - - vreg_nvme: regulator-nvme { - compatible = "regulator-fixed"; - - regulator-name = "VREG_NVME_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&nvme_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr0_1p15: regulator-rtmr0-1p15 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR0_1P15"; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1150000>; - - gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb0_pwr_1p15_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr0_1p8: regulator-rtmr0-1p8 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR0_1P8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb0_1p8_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_rtmr0_3p3: regulator-rtmr0-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_RTMR0_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&usb0_3p3_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_vph_pwr: regulator-vph-pwr { - compatible = "regulator-fixed"; - - regulator-name = "vreg_vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - - regulator-always-on; - regulator-boot-on; - }; - - vreg_wcn_3p3: regulator-wcn-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&wcn_sw_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - /* - * TODO: These two regulators are actually part of the removable M.2 - * card and not the CRD mainboard. Need to describe this differently. - * Functionally it works correctly, because all we need to do is to - * turn on the actual 3.3V supply above. - */ - vreg_wcn_0p95: regulator-wcn-0p95 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_0P95"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - - vin-supply = <&vreg_wcn_3p3>; - }; - - vreg_wcn_1p9: regulator-wcn-1p9 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_1P9"; - regulator-min-microvolt = <1900000>; - regulator-max-microvolt = <1900000>; - - vin-supply = <&vreg_wcn_3p3>; - }; - - wcn6855-pmu { - compatible = "qcom,wcn6855-pmu"; - - vddaon-supply = <&vreg_wcn_0p95>; - vddio-supply = <&vreg_wcn_1p9>; - vddpcie1p3-supply = <&vreg_wcn_1p9>; - vddpcie1p9-supply = <&vreg_wcn_1p9>; - vddpmu-supply = <&vreg_wcn_0p95>; - vddpmumx-supply = <&vreg_wcn_0p95>; - vddpmucx-supply = <&vreg_wcn_0p95>; - vddrfa0p95-supply = <&vreg_wcn_0p95>; - vddrfa1p3-supply = <&vreg_wcn_1p9>; - vddrfa1p9-supply = <&vreg_wcn_1p9>; - - wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; - bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; - - pinctrl-0 = <&wcn_wlan_bt_en>; - pinctrl-names = "default"; - - regulators { - vreg_pmu_rfa_cmn_0p8: ldo0 { - regulator-name = "vreg_pmu_rfa_cmn_0p8"; - }; - - vreg_pmu_aon_0p8: ldo1 { - regulator-name = "vreg_pmu_aon_0p8"; - }; - - vreg_pmu_wlcx_0p8: ldo2 { - regulator-name = "vreg_pmu_wlcx_0p8"; - }; - - vreg_pmu_wlmx_0p8: ldo3 { - regulator-name = "vreg_pmu_wlmx_0p8"; - }; - - vreg_pmu_btcmx_0p8: ldo4 { - regulator-name = "vreg_pmu_btcmx_0p8"; - }; - - vreg_pmu_pcie_1p8: ldo5 { - regulator-name = "vreg_pmu_pcie_1p8"; - }; - - vreg_pmu_pcie_0p9: ldo6 { - regulator-name = "vreg_pmu_pcie_0p9"; - }; - - vreg_pmu_rfa_0p8: ldo7 { - regulator-name = "vreg_pmu_rfa_0p8"; - }; - - vreg_pmu_rfa_1p2: ldo8 { - regulator-name = "vreg_pmu_rfa_1p2"; - }; - - vreg_pmu_rfa_1p7: ldo9 { - regulator-name = "vreg_pmu_rfa_1p7"; - }; - }; - }; - - usb-1-ss1-sbu-mux { - compatible = "onnn,fsusb42", "gpio-sbu-mux"; - - enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>; - select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>; - - pinctrl-0 = <&usb_1_ss1_sbu_default>; - pinctrl-names = "default"; - - mode-switch; - orientation-switch; - - port { - usb_1_ss1_sbu_mux: endpoint { - remote-endpoint = <&pmic_glink_ss1_sbu>; - }; - }; - }; }; -&apps_rsc { - regulators-0 { - compatible = "qcom,pm8550-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd-bob1-supply = <&vreg_vph_pwr>; - vdd-bob2-supply = <&vreg_vph_pwr>; - vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; - vdd-l2-l13-l14-supply = <&vreg_bob1>; - vdd-l5-l16-supply = <&vreg_bob1>; - vdd-l6-l7-supply = <&vreg_bob2>; - vdd-l8-l9-supply = <&vreg_bob1>; - vdd-l12-supply = <&vreg_s5j_1p2>; - vdd-l15-supply = <&vreg_s4c_1p8>; - vdd-l17-supply = <&vreg_bob2>; - - vreg_bob1: bob1 { - regulator-name = "vreg_bob1"; - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3960000>; - regulator-initial-mode = ; - }; - - vreg_bob2: bob2 { - regulator-name = "vreg_bob2"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <3008000>; - regulator-initial-mode = ; - }; - - vreg_l1b_1p8: ldo1 { - regulator-name = "vreg_l1b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l2b_3p0: ldo2 { - regulator-name = "vreg_l2b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3100000>; - regulator-initial-mode = ; - }; - - vreg_l4b_1p8: ldo4 { - regulator-name = "vreg_l4b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l5b_3p0: ldo5 { - regulator-name = "vreg_l5b_3p0"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-initial-mode = ; - }; - - vreg_l6b_1p8: ldo6 { - regulator-name = "vreg_l6b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l7b_2p8: ldo7 { - regulator-name = "vreg_l7b_2p8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-initial-mode = ; - }; - - vreg_l8b_3p0: ldo8 { - regulator-name = "vreg_l8b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l9b_2p9: ldo9 { - regulator-name = "vreg_l9b_2p9"; - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vreg_l10b_1p8: ldo10 { - regulator-name = "vreg_l10b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l12b_1p2: ldo12 { - regulator-name = "vreg_l12b_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vreg_l13b_3p0: ldo13 { - regulator-name = "vreg_l13b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3100000>; - regulator-initial-mode = ; - }; - - vreg_l14b_3p0: ldo14 { - regulator-name = "vreg_l14b_3p0"; - regulator-min-microvolt = <3072000>; - regulator-max-microvolt = <3072000>; - regulator-initial-mode = ; - }; - - vreg_l15b_1p8: ldo15 { - regulator-name = "vreg_l15b_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - regulator-always-on; - }; - - vreg_l16b_2p9: ldo16 { - regulator-name = "vreg_l16b_2p9"; - regulator-min-microvolt = <2912000>; - regulator-max-microvolt = <2912000>; - regulator-initial-mode = ; - }; - - vreg_l17b_2p5: ldo17 { - regulator-name = "vreg_l17b_2p5"; - regulator-min-microvolt = <2504000>; - regulator-max-microvolt = <2504000>; - regulator-initial-mode = ; - }; - }; - - regulators-1 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "c"; - - vdd-l1-supply = <&vreg_s5j_1p2>; - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s4-supply = <&vreg_vph_pwr>; - - vreg_s4c_1p8: smps4 { - regulator-name = "vreg_s4c_1p8"; - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - vreg_l1c_1p2: ldo1 { - regulator-name = "vreg_l1c_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l2c_0p8: ldo2 { - regulator-name = "vreg_l2c_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l3c_0p8: ldo3 { - regulator-name = "vreg_l3c_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - }; - - regulators-2 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "d"; - - vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s4c_1p8>; - vdd-s1-supply = <&vreg_vph_pwr>; - - vreg_l1d_0p8: ldo1 { - regulator-name = "vreg_l1d_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l2d_0p9: ldo2 { - regulator-name = "vreg_l2d_0p9"; - regulator-min-microvolt = <912000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l3d_1p8: ldo3 { - regulator-name = "vreg_l3d_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; - - regulators-3 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "e"; - - vdd-l2-supply = <&vreg_s1f_0p7>; - vdd-l3-supply = <&vreg_s5j_1p2>; - - vreg_l2e_0p8: ldo2 { - regulator-name = "vreg_l2e_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l3e_1p2: ldo3 { - regulator-name = "vreg_l3e_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - }; - - regulators-4 { - compatible = "qcom,pmc8380-rpmh-regulators"; - qcom,pmic-id = "f"; - - vdd-l1-supply = <&vreg_s5j_1p2>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s5j_1p2>; - vdd-s1-supply = <&vreg_vph_pwr>; - - vreg_s1f_0p7: smps1 { - regulator-name = "vreg_s1f_0p7"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1100000>; - regulator-initial-mode = ; - }; - - vreg_l1f_1p0: ldo1 { - regulator-name = "vreg_l1f_1p0"; - regulator-min-microvolt = <1024000>; - regulator-max-microvolt = <1024000>; - regulator-initial-mode = ; - }; - - vreg_l2f_1p0: ldo2 { - regulator-name = "vreg_l2f_1p0"; - regulator-min-microvolt = <1024000>; - regulator-max-microvolt = <1024000>; - regulator-initial-mode = ; - }; - - vreg_l3f_1p0: ldo3 { - regulator-name = "vreg_l3f_1p0"; - regulator-min-microvolt = <1024000>; - regulator-max-microvolt = <1024000>; - regulator-initial-mode = ; - }; - }; - - regulators-6 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "i"; - - vdd-l1-supply = <&vreg_s4c_1p8>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s1-supply = <&vreg_vph_pwr>; - vdd-s2-supply = <&vreg_vph_pwr>; - - vreg_s1i_0p9: smps1 { - regulator-name = "vreg_s1i_0p9"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_s2i_1p0: smps2 { - regulator-name = "vreg_s2i_1p0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1100000>; - regulator-initial-mode = ; - }; - - vreg_l1i_1p8: ldo1 { - regulator-name = "vreg_l1i_1p8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - - vreg_l2i_1p2: ldo2 { - regulator-name = "vreg_l2i_1p2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-initial-mode = ; - }; - - vreg_l3i_0p8: ldo3 { - regulator-name = "vreg_l3i_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - }; - - regulators-7 { - compatible = "qcom,pm8550ve-rpmh-regulators"; - qcom,pmic-id = "j"; - - vdd-l1-supply = <&vreg_s1f_0p7>; - vdd-l2-supply = <&vreg_s5j_1p2>; - vdd-l3-supply = <&vreg_s1f_0p7>; - vdd-s5-supply = <&vreg_vph_pwr>; - - vreg_s5j_1p2: smps5 { - regulator-name = "vreg_s5j_1p2"; - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1304000>; - regulator-initial-mode = ; - }; - - vreg_l1j_0p8: ldo1 { - regulator-name = "vreg_l1j_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - - vreg_l2j_1p2: ldo2 { - regulator-name = "vreg_l2j_1p2"; - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1256000>; - regulator-initial-mode = ; - }; - - vreg_l3j_0p8: ldo3 { - regulator-name = "vreg_l3j_0p8"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <920000>; - regulator-initial-mode = ; - }; - }; -}; - -&gpu { - status = "okay"; - - zap-shader { - firmware-name = "qcom/x1e80100/hp/omnibook-x14/qcdxkmsuc8380.mbn"; - }; -}; - -&i2c0 { - clock-frequency = <400000>; - - status = "okay"; - - keyboard@3a { - compatible = "hid-over-i2c"; - reg = <0x3a>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l12b_1p2>; - - pinctrl-0 = <&kybd_default>; - pinctrl-names = "default"; - - wakeup-source; - }; - - touchpad@15 { - compatible = "hid-over-i2c"; - reg = <0x15>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l12b_1p2>; - - pinctrl-0 = <&tpad_default>; - pinctrl-names = "default"; - - wakeup-source; - }; -}; - -&i2c3 { - clock-frequency = <400000>; - - status = "okay"; - - typec-mux@8 { - compatible = "parade,ps8830"; - reg = <0x08>; - - clocks = <&rpmhcc RPMH_RF_CLK3>; - - vdd-supply = <&vreg_rtmr0_1p15>; - vdd33-supply = <&vreg_rtmr0_3p3>; - vdd33-cap-supply = <&vreg_rtmr0_3p3>; - vddar-supply = <&vreg_rtmr0_1p15>; - vddat-supply = <&vreg_rtmr0_1p15>; - vddio-supply = <&vreg_rtmr0_1p8>; - - reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&rtmr0_default>; - pinctrl-names = "default"; - - orientation-switch; - retimer-switch; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - retimer_ss0_ss_out: endpoint { - remote-endpoint = <&pmic_glink_ss0_ss_in>; - }; - }; - - port@1 { - reg = <1>; - - retimer_ss0_ss_in: endpoint { - remote-endpoint = <&usb_1_ss0_qmpphy_out>; - }; - }; - - port@2 { - reg = <2>; - - retimer_ss0_con_sbu_out: endpoint { - remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; - }; - }; - }; - }; -}; - -&i2c5 { - clock-frequency = <400000>; - status = "okay"; - - eusb3_repeater: redriver@47 { - compatible = "nxp,ptn3222"; - reg = <0x47>; - #phy-cells = <0>; - - vdd3v3-supply = <&vreg_l13b_3p0>; - vdd1v8-supply = <&vreg_l4b_1p8>; - - reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&eusb3_reset_n>; - pinctrl-names = "default"; - - }; -}; - -&i2c8 { - clock-frequency = <400000>; - - status = "okay"; - - touchscreen@10 { - compatible = "hid-over-i2c"; - reg = <0x10>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l15b_1p8>; - - pinctrl-0 = <&ts0_default>; - pinctrl-names = "default"; - }; -}; - -&lpass_tlmm { - spkr_01_sd_n_active: spkr-01-sd-n-active-state { - pins = "gpio12"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-low; - }; -}; - -&lpass_vamacro { - pinctrl-0 = <&dmic01_default>, <&dmic23_default>; - pinctrl-names = "default"; - - vdd-micb-supply = <&vreg_l1b_1p8>; - qcom,dmic-sample-rate = <4800000>; -}; - -&mdss { - status = "okay"; -}; - -&mdss_dp0 { - status = "okay"; -}; - -&mdss_dp0_out { - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; -}; - -&mdss_dp1 { - status = "okay"; -}; - -&mdss_dp1_out { - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; -}; - -&mdss_dp3 { - /delete-property/ #sound-dai-cells; - - pinctrl-0 = <&edp0_hpd_default>; - pinctrl-names = "default"; - - status = "okay"; - - aux-bus { - panel { - compatible = "edp-panel"; - power-supply = <&vreg_edp_3p3>; - - backlight = <&backlight>; - - port { - edp_panel_in: endpoint { - remote-endpoint = <&mdss_dp3_out>; - }; - }; - }; - }; -}; - -&mdss_dp3_out { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; -}; - -&mdss_dp3_phy { - vdda-phy-supply = <&vreg_l3j_0p8>; - vdda-pll-supply = <&vreg_l2j_1p2>; - - status = "okay"; -}; - -&pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&pcie4_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie4_phy { - vdda-phy-supply = <&vreg_l3i_0p8>; - vdda-pll-supply = <&vreg_l3e_1p2>; - - status = "okay"; -}; - -&pcie4_port0 { - wifi@0 { - compatible = "pci17cb,1107"; - reg = <0x10000 0x0 0x0 0x0 0x0>; - - vddaon-supply = <&vreg_pmu_aon_0p8>; - vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; - vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; - vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; - }; -}; - -&pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; - - vddpe-3v3-supply = <&vreg_nvme>; - - pinctrl-0 = <&pcie6a_default>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&pcie6a_phy { - vdda-phy-supply = <&vreg_l1d_0p8>; - vdda-pll-supply = <&vreg_l2j_1p2>; - - status = "okay"; -}; - -&pm8550_gpios { - rtmr0_default: rtmr0-reset-n-active-state { - pins = "gpio10"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; - - usb0_3p3_reg_en: usb0-3p3-reg-en-state { - pins = "gpio11"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; -}; - -&pm8550ve_8_gpios { - misc_3p3_reg_en: misc-3p3-reg-en-state { - pins = "gpio6"; - function = "normal"; - bias-disable; - drive-push-pull; - input-disable; - output-enable; - power-source = <1>; /* 1.8 V */ - qcom,drive-strength = ; - }; -}; - -&pm8550ve_9_gpios { - usb0_1p8_reg_en: usb0-1p8-reg-en-state { - pins = "gpio8"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; -}; - -&pmc8380_3_gpios { - edp_bl_en: edp-bl-en-state { - pins = "gpio4"; - function = "normal"; - power-source = <1>; /* 1.8V */ - input-disable; - output-enable; - }; - - edp_bl_reg_en: edp-bl-reg-en-state { - pins = "gpio10"; - function = "normal"; - }; - -}; - -&pmc8380_5_gpios { - usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { - pins = "gpio8"; - function = "normal"; - power-source = <1>; /* 1.8V */ - bias-disable; - input-disable; - output-enable; - }; -}; - -&pmk8550_gpios { - edp_bl_pwm: edp-bl-pwm-state { - pins = "gpio5"; - function = "func3"; - }; -}; - -&pmk8550_pwm { - status = "okay"; -}; - -&qupv3_0 { - status = "okay"; -}; - -&qupv3_1 { - status = "okay"; -}; - -&qupv3_2 { - status = "okay"; +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/hp/omnibook-x14/qcdxkmsuc8380.mbn"; }; &remoteproc_adsp { @@ -1237,335 +33,3 @@ &remoteproc_cdsp { status = "okay"; }; - -&smb2360_0 { - status = "okay"; -}; - -&smb2360_0_eusb2_repeater { - vdd18-supply = <&vreg_l3d_1p8>; - vdd3-supply = <&vreg_l2b_3p0>; -}; - -&smb2360_1 { - status = "okay"; -}; - -&smb2360_1_eusb2_repeater { - vdd18-supply = <&vreg_l3d_1p8>; - vdd3-supply = <&vreg_l14b_3p0>; -}; - -&swr0 { - pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; - pinctrl-names = "default"; - - status = "okay"; - - /* WSA8845, Left Speaker */ - left_spkr: speaker@0,0 { - compatible = "sdw20217020400"; - reg = <0 0>; - reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - sound-name-prefix = "SpkrLeft"; - vdd-1p8-supply = <&vreg_l15b_1p8>; - vdd-io-supply = <&vreg_l12b_1p2>; - qcom,port-mapping = <1 2 3 7 10 13>; - }; - - /* WSA8845, Right Speaker */ - right_spkr: speaker@0,1 { - compatible = "sdw20217020400"; - reg = <0 1>; - reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <0>; - sound-name-prefix = "SpkrRight"; - vdd-1p8-supply = <&vreg_l15b_1p8>; - vdd-io-supply = <&vreg_l12b_1p2>; - qcom,port-mapping = <4 5 6 7 11 13>; - }; -}; - -&swr1 { - status = "okay"; - - /* WCD9385 RX */ - wcd_rx: codec@0,4 { - compatible = "sdw20217010d00"; - reg = <0 4>; - qcom,rx-port-mapping = <1 2 3 4 5>; - }; -}; - -&swr2 { - status = "okay"; - - /* WCD9385 TX */ - wcd_tx: codec@0,3 { - compatible = "sdw20217010d00"; - reg = <0 3>; - qcom,tx-port-mapping = <2 2 3 4>; - }; -}; - -&tlmm { - gpio-reserved-ranges = <34 2>, /* Unused */ - <44 4>, /* SPI (TPM) */ - <72 2>, /* Secure EC I2C connection (?) */ - <238 1>; /* UFS Reset */ - - edp_reg_en: edp-reg-en-state { - pins = "gpio70"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - eusb3_reset_n: eusb3-reset-n-state { - pins = "gpio6"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - output-low; - }; - - hall_int_n_default: hall-int-n-state { - pins = "gpio92"; - function = "gpio"; - bias-disable; - }; - - kybd_default: kybd-default-state { - pins = "gpio67"; - function = "gpio"; - bias-pull-up; - }; - - nvme_reg_en: nvme-reg-en-state { - pins = "gpio18"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - pcie4_default: pcie4-default-state { - clkreq-n-pins { - pins = "gpio147"; - function = "pcie4_clk"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio146"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio148"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie6a_default: pcie6a-default-state { - clkreq-n-pins { - pins = "gpio153"; - function = "pcie6a_clk"; - drive-strength = <2>; - bias-pull-up; - }; - - perst-n-pins { - pins = "gpio152"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wake-n-pins { - pins = "gpio154"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - tpad_default: tpad-default-state { - pins = "gpio3"; - function = "gpio"; - bias-pull-up; - }; - - ts0_default: ts0-default-state { - int-n-pins { - pins = "gpio51"; - function = "gpio"; - bias-pull-up; - }; - - reset-n-pins { - pins = "gpio48"; - function = "gpio"; - output-high; - drive-strength = <16>; - }; - }; - - usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { - mode-pins { - pins = "gpio177"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - output-high; - }; - - oe-n-pins { - pins = "gpio179"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - }; - - sel-pins { - pins = "gpio178"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - }; - }; - - wcd_default: wcd-reset-n-active-state { - pins = "gpio191"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - output-low; - }; - - wcn_sw_en: wcn-sw-en-state { - pins = "gpio214"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wcn_wlan_bt_en: wcn-wlan-bt-en-state { - pins = "gpio116", "gpio117"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; -}; - -&uart14 { - status = "okay"; - - bluetooth { - compatible = "qcom,wcn6855-bt"; - max-speed = <3200000>; - - vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; - vddaon-supply = <&vreg_pmu_aon_0p8>; - vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; - vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; - vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; - vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; - vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; - }; -}; - -&usb_1_ss0_hsphy { - vdd-supply = <&vreg_l3j_0p8>; - vdda12-supply = <&vreg_l2j_1p2>; - - phys = <&smb2360_0_eusb2_repeater>; - - status = "okay"; -}; - -&usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; - - status = "okay"; -}; - -&usb_1_ss0 { - status = "okay"; -}; - -&usb_1_ss0_dwc3 { - dr_mode = "host"; -}; - -&usb_1_ss0_dwc3_hs { - remote-endpoint = <&pmic_glink_ss0_hs_in>; -}; - -&usb_1_ss0_qmpphy_out { - remote-endpoint = <&retimer_ss0_ss_in>; -}; - -&usb_1_ss1_hsphy { - vdd-supply = <&vreg_l3j_0p8>; - vdda12-supply = <&vreg_l2j_1p2>; - - phys = <&smb2360_1_eusb2_repeater>; - - status = "okay"; -}; - -&usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; - - status = "okay"; -}; - -&usb_1_ss1 { - status = "okay"; -}; - -&usb_1_ss1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_ss1_dwc3_hs { - remote-endpoint = <&pmic_glink_ss1_hs_in>; -}; - -&usb_1_ss1_qmpphy_out { - remote-endpoint = <&pmic_glink_ss1_ss_in>; -}; - -&usb_mp { - status = "okay"; -}; - -&usb_mp_dwc3 { - phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>; - phy-names = "usb2-0", "usb3-0"; -}; - -&usb_mp_hsphy0 { - vdd-supply = <&vreg_l2e_0p8>; - vdda12-supply = <&vreg_l3e_1p2>; - - phys = <&eusb3_repeater>; - - status = "okay"; -}; - -&usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; - - status = "okay"; -}; From f8f7cc59dcd234f0dcc4964ff2188a7a2ae09fd6 Mon Sep 17 00:00:00 2001 From: Jens Glathe Date: Mon, 15 Sep 2025 09:35:06 +0200 Subject: [PATCH 881/931] arm64: dts: qcom: x1-hp-x14: Add support for X1P42100 HP Omnibook X14 These laptops are the same as the already known 14-fe0xxx models, but with a Purwa SoC, SKU number 14-fe1xxx. [1] The supported features are the same as for the original Omnibook X14: - Keyboard (no function keys though) - Display - PWM brightness control - Touchpad - Touchscreen - PCIe ports (pcie4, pcie6a) - USB type-c, type-a - WCN6855 Wifi-6E - WCN6855 Bluetooth - ADSP and CDSP - X1 GPU - GPIO Keys (Lid switch) - Audio definition (works via USB and with internal speakers) [1]: https://www.hp.com/us-en/shop/pdp/hp-omnibook-x-laptop-next-gen-ai-pc-14-fe100-14-a4nd1av-1#techSpecs Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Jens Glathe Link: https://lore.kernel.org/r/20250915-hp-x14-x1p-v9-3-fa457ca30ffe@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 ++ .../dts/qcom/x1p42100-hp-omnibook-x14.dts | 33 +++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 76d275991e83..cd0ab971278e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -340,5 +340,7 @@ x1p42100-asus-zenbook-a14-el2-dtbs := x1p42100-asus-zenbook-a14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-asus-zenbook-a14.dtb x1p42100-asus-zenbook-a14-el2.dtb x1p42100-crd-el2-dtbs := x1p42100-crd.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-crd.dtb x1p42100-crd-el2.dtb +x1p42100-hp-omnibook-x14-el2-dtbs := x1p42100-hp-omnibook-x14.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-hp-omnibook-x14.dtb x1p42100-hp-omnibook-x14-el2.dtb x1p42100-lenovo-thinkbook-16-el2-dtbs := x1p42100-lenovo-thinkbook-16.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-thinkbook-16.dtb x1p42100-lenovo-thinkbook-16-el2.dtb diff --git a/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts new file mode 100644 index 000000000000..6696cab2de3e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/dts-v1/; + +#include "x1p42100.dtsi" +#include "x1e80100-pmics.dtsi" +#include "x1-hp-omnibook-x14.dtsi" +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "HP Omnibook X 14-fe1"; + compatible = "hp,omnibook-x14-fe1", "qcom,x1p42100"; + chassis-type = "laptop"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/hp/omnibook-x14/qcdxkmsucpurwa.mbn"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/hp/omnibook-x14/qcadsp8380.mbn", + "qcom/x1p42100/hp/omnibook-x14/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/hp/omnibook-x14/qccdsp8380.mbn", + "qcom/x1p42100/hp/omnibook-x14/cdsp_dtbs.elf"; + + status = "okay"; +}; From ed32443efe2c044bad53309670e5b58473a620d1 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Sat, 13 Sep 2025 23:53:18 +0530 Subject: [PATCH 882/931] arm64: dts: qcom: qcs8300: Flatten usb controller nodes Flatten usb controller nodes and update to using latest bindings and flattened driver approach. Enumeration of ADB has been tested on EVK Platform. Signed-off-by: Krishna Kurapati Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250913182318.3547789-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 6 +- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 12 ++-- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 85 ++++++++++------------- 3 files changed, 41 insertions(+), 62 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index f3c5d363921e..116378d4ce7a 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -478,11 +478,9 @@ &ufs_mem_phy { }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "peripheral"; + + status = "okay"; }; &usb_1_hsphy { diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 9c37a0f5ba25..f8ed510477cf 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -414,17 +414,13 @@ &usb_qmpphy { }; &usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { dr_mode = "peripheral"; + + status = "okay"; }; &usb_2 { + dr_mode = "host"; + status = "okay"; }; - -&usb_2_dwc3 { - dr_mode = "host"; -}; diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 8afd77a2d737..d35bfece60d1 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -4467,9 +4467,9 @@ llcc: system-cache-controller@9200000 { interrupts = ; }; - usb_1: usb@a6f8800 { - compatible = "qcom,qcs8300-dwc3", "qcom,dwc3"; - reg = <0x0 0x0a6f8800 0x0 0x400>; + usb_1: usb@a600000 { + compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -4486,12 +4486,14 @@ usb_1: usb@a6f8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", @@ -4507,32 +4509,23 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "usb-ddr", "apps-usb"; + iommus = <&apps_smmu 0x80 0x0>; + phys = <&usb_1_hsphy>, <&usb_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + wakeup-source; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0x0 0x0a600000 0x0 0xe000>; - interrupts = ; - iommus = <&apps_smmu 0x80 0x0>; - phys = <&usb_1_hsphy>, <&usb_qmpphy>; - phy-names = "usb2-phy", "usb3-phy"; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - }; }; - usb_2: usb@a4f8800 { - compatible = "qcom,qcs8300-dwc3", "qcom,dwc3"; - reg = <0x0 0x0a4f8800 0x0 0x400>; + usb_2: usb@a400000 { + compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a400000 0x0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, <&gcc GCC_USB20_MASTER_CLK>, @@ -4549,11 +4542,13 @@ usb_2: usb@a4f8800 { <&gcc GCC_USB20_MASTER_CLK>; assigned-clock-rates = <19200000>, <120000000>; - interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; @@ -4569,32 +4564,22 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "usb-ddr", "apps-usb"; + iommus = <&apps_smmu 0x20 0x0>; + + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + qcom,select-utmi-as-pipe-clk; wakeup-source; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - usb_2_dwc3: usb@a400000 { - compatible = "snps,dwc3"; - reg = <0x0 0x0a400000 0x0 0xe000>; - - interrupts = ; - iommus = <&apps_smmu 0x20 0x0>; - - phys = <&usb_2_hsphy>; - phy-names = "usb2-phy"; - maximum-speed = "high-speed"; - - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - snps,dis_enblslpm_quirk; - }; }; iris: video-codec@aa00000 { From 11cf389c103f69d1170fbd70acbcc282cf03b748 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20Gon=C3=A7alves?= Date: Fri, 12 Sep 2025 20:25:57 +0000 Subject: [PATCH 883/931] arm64: dts: qcom: add initial support for Samsung Galaxy S22 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add new device support for the Samsung Galaxy S22 (SM-S901E) phone What works: - SimpleFB - USB Signed-off-by: Eric Gonçalves Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250912202603.7312-2-ghatto404@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm8450-samsung-r0q.dts | 145 ++++++++++++++++++ 2 files changed, 146 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index cd0ab971278e..85af93331ba4 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -290,6 +290,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8450-samsung-r0q.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-hdk.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts b/arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts new file mode 100644 index 000000000000..880d74ae6032 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8450-samsung-r0q.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include + +#include "sm8450.dtsi" +#include "pm8350.dtsi" +#include "pm8350c.dtsi" + +/ { + model = "Samsung Galaxy S22 5G"; + compatible = "samsung,r0q", "qcom,sm8450"; + chassis-type = "handset"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@b8000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0xb8000000 0x0 0x2b00000>; + width = <1080>; + height = <2340>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + /* + * The bootloader will only keep display hardware enabled + * if this memory region is named exactly 'splash_region' + */ + splash-region@b8000000 { + reg = <0x0 0xb8000000 0x0 0x2b00000>; + no-map; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_bob>; + + vreg_l2b_3p07: ldo2 { + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l5b_0p88: ldo5 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_bob>; + vdd-l2-l8-supply = <&vreg_bob>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <36 4>; /* SPI (not linked to anything) */ +}; + +&usb_1 { + /* Keep USB 2.0 only for now */ + qcom,select-utmi-as-pipe-clk; + + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + /* Remove USB3 phy */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + + status = "okay"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l5b_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p07>; + + status = "okay"; +}; From 171e12ff755812dcf98b3ed98f15f54bf264fae3 Mon Sep 17 00:00:00 2001 From: Dzmitry Sankouski Date: Fri, 12 Sep 2025 21:56:35 +0300 Subject: [PATCH 884/931] arm64: dts: qcom: sdm845-starqltechn: fix slpi reserved mem When adding adsp reserved mem, slpi reserved memory was shrunk according to vendor kernel log: `Removed memory: created DMA memory pool at 0x0000000096700000, size 15 M` However, kernel failed to load firmware with 15MiB reserved region: `[ 14.885885] qcom_q6v5_pas 5c00000.remoteproc: segment outside memory range` Increase slpi reserved region to 16MiB. Fixes: 58782c229e3e ("arm64: dts: qcom: sdm845-starqltechn: add initial sound support") Signed-off-by: Dzmitry Sankouski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250912-starqltechn_slpi-v2-1-5ca5ddbbe7b4@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 9eeb4b807465..32ce666fc57e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -118,7 +118,7 @@ removed_region: removed-region@88f00000 { }; slpi_mem: slpi@96700000 { - reg = <0 0x96700000 0 0xf00000>; + reg = <0 0x96700000 0 0x1000000>; no-map; }; From 50ced16fe5bfe76cf1cb7f0ff5371b0c141ea6c3 Mon Sep 17 00:00:00 2001 From: Dzmitry Sankouski Date: Fri, 12 Sep 2025 21:56:36 +0300 Subject: [PATCH 885/931] arm64: dts: qcom: sdm845-starqltechn: add slpi support Add support for Qualcomm sensor low power island. Signed-off-by: Dzmitry Sankouski Link: https://lore.kernel.org/r/20250912-starqltechn_slpi-v2-2-5ca5ddbbe7b4@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sdm845-samsung-starqltechn.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 32ce666fc57e..75a53f0bbebd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -56,6 +56,21 @@ framebuffer: framebuffer@9d400000 { }; }; + slpi_regulator: slpi-regulator { + compatible = "regulator-fixed"; + pinctrl-0 = <&slpi_ldo_active_state>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "slpi"; + + enable-active-high; + gpio = <&tlmm 8 GPIO_ACTIVE_HIGH>; + }; + vib_regulator: gpio-regulator { compatible = "regulator-fixed"; @@ -902,6 +917,13 @@ &ipa { status = "okay"; }; +&slpi_pas { + firmware-name = "qcom/sdm845/starqltechn/slpi.mbn"; + cx-supply = <&slpi_regulator>; + + status = "okay"; +}; + &usb_1 { status = "okay"; }; @@ -1028,6 +1050,13 @@ sd_card_det_n_state: sd-card-det-n-state { bias-pull-up; }; + slpi_ldo_active_state: slpi-ldo-active-state { + pins = "gpio8"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + touch_irq_state: touch-irq-state { pins = "gpio120"; function = "gpio"; From a19c879b69b12cc31ed59b50e743a1ef2e5b08b1 Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Thu, 14 Aug 2025 15:46:15 +0530 Subject: [PATCH 886/931] arm64: dts: qcom: lemans: Add support for camss Add changes to support the camera subsystem on the lemans. Co-developed-by: Suresh Vankadara Signed-off-by: Suresh Vankadara Signed-off-by: Vikram Sharma Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20250814101615.1102795-10-quic_vikramsa@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 185 +++++++++++++++++++++++++++ 1 file changed, 185 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index b7e727f01cec..45c81e581af3 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -4410,6 +4411,190 @@ videocc: clock-controller@abf0000 { #power-domain-cells = <1>; }; + camss: isp@ac78000 { + compatible = "qcom,sa8775p-camss"; + + reg = <0x0 0xac78000 0x0 0x1000>, + <0x0 0xac7a000 0x0 0x0f00>, + <0x0 0xac7c000 0x0 0x0f00>, + <0x0 0xac84000 0x0 0x0f00>, + <0x0 0xac88000 0x0 0x0f00>, + <0x0 0xac8c000 0x0 0x0f00>, + <0x0 0xac90000 0x0 0x0f00>, + <0x0 0xac94000 0x0 0x0f00>, + <0x0 0xac9c000 0x0 0x2000>, + <0x0 0xac9e000 0x0 0x2000>, + <0x0 0xaca0000 0x0 0x2000>, + <0x0 0xaca2000 0x0 0x2000>, + <0x0 0xacac000 0x0 0x0400>, + <0x0 0xacad000 0x0 0x0400>, + <0x0 0xacae000 0x0 0x0400>, + <0x0 0xac4d000 0x0 0xd000>, + <0x0 0xac5a000 0x0 0xd000>, + <0x0 0xac85000 0x0 0x0d00>, + <0x0 0xac89000 0x0 0x0d00>, + <0x0 0xac8d000 0x0 0x0d00>, + <0x0 0xac91000 0x0 0x0d00>, + <0x0 0xac95000 0x0 0x0d00>; + reg-names = "csid_wrapper", + "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb_clk", + "cpas_vfe_lite", + "cpas_vfe0", + "cpas_vfe1", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy_rx", + "gcc_axi_hf", + "gcc_axi_sf", + "icp_ahb", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_0"; + + iommus = <&apps_smmu 0x3400 0x20>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,sa8775p-camcc"; reg = <0x0 0x0ade0000 0x0 0x20000>; From 3964a91e552880c356ec4d3f09eed927f48e9c66 Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Fri, 12 Sep 2025 23:19:26 +0800 Subject: [PATCH 887/931] arm64: dts: qcom: lemans: Add CCI definitions Qualcomm SA8775P SoC contains 4 Camera Control Interface controllers. Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Wenmeng Liu Link: https://lore.kernel.org/r/20250912-camss_rb8-v6-2-c9a6c3d67392@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 268 +++++++++++++++++++++++++++ 1 file changed, 268 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 45c81e581af3..7e40f59e4aa3 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4411,6 +4411,162 @@ videocc: clock-controller@abf0000 { #power-domain-cells = <1>; }; + cci0: cci@ac13000 { + compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac13000 0x0 0x1000>; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 = <&cci0_0_default &cci0_1_default>; + pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac14000 { + compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac14000 0x0 0x1000>; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 = <&cci1_0_default &cci1_1_default>; + pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci2: cci@ac15000 { + compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac15000 0x0 0x1000>; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 = <&cci2_0_default &cci2_1_default>; + pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci2_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci3: cci@ac16000 { + compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; + reg = <0x0 0x0ac16000 0x0 0x1000>; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_3_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cci"; + + pinctrl-0 = <&cci3_0_default &cci3_1_default>; + pinctrl-1 = <&cci3_0_sleep &cci3_1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci3_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci3_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camss: isp@ac78000 { compatible = "qcom,sa8775p-camss"; @@ -5268,6 +5424,118 @@ hs2_mi2s_active: hs2-mi2s-active-state { bias-disable; }; + cci0_0_default: cci0-0-default-state { + pins = "gpio60", "gpio61"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci0_0_sleep: cci0-0-sleep-state { + pins = "gpio60", "gpio61"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci0_1_default: cci0-1-default-state { + pins = "gpio52", "gpio53"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci0_1_sleep: cci0-1-sleep-state { + pins = "gpio52", "gpio53"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_0_default: cci1-0-default-state { + pins = "gpio62", "gpio63"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci1_0_sleep: cci1-0-sleep-state { + pins = "gpio62", "gpio63"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_1_default: cci1-1-default-state { + pins = "gpio54", "gpio55"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci1_1_sleep: cci1-1-sleep-state { + pins = "gpio54", "gpio55"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci2_0_default: cci2-0-default-state { + pins = "gpio64", "gpio65"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci2_0_sleep: cci2-0-sleep-state { + pins = "gpio64", "gpio65"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci2_1_default: cci2-1-default-state { + pins = "gpio56", "gpio57"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci2_1_sleep: cci2-1-sleep-state { + pins = "gpio56", "gpio57"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci3_0_default: cci3-0-default-state { + pins = "gpio66", "gpio67"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci3_0_sleep: cci3-0-sleep-state { + pins = "gpio66", "gpio67"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci3_1_default: cci3-1-default-state { + pins = "gpio58", "gpio59"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + cci3_1_sleep: cci3-1-sleep-state { + pins = "gpio58", "gpio59"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + qup_i2c0_default: qup-i2c0-state { pins = "gpio20", "gpio21"; function = "qup0_se0"; From b68fc45910d4eb1b3bb7e160282fba5a4bdd8409 Mon Sep 17 00:00:00 2001 From: Wenmeng Liu Date: Fri, 12 Sep 2025 23:19:27 +0800 Subject: [PATCH 888/931] arm64: dts: qcom: lemans-evk: Add IMX577-based camera overlay Enable IMX577 via CCI1 on LeMans EVK Core Kit. The LeMans EVK board does not include a camera sensor by default, this overlay reflects the possibility of attaching an optional camera sensor. For this reason, the camera sensor configuration is placed in lemans-evk-camera.dtso, rather than modifying the base lemans-evk.dts. Reviewed-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Signed-off-by: Wenmeng Liu Link: https://lore.kernel.org/r/20250912-camss_rb8-v6-3-c9a6c3d67392@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../qcom/lemans-evk-camera-csi1-imx577.dtso | 97 +++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/lemans-evk-camera-csi1-imx577.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 85af93331ba4..d7f22476d510 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -30,6 +30,10 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb + +lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera-csi1-imx577.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-camera-csi1-imx577.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-camera-csi1-imx577.dtso new file mode 100644 index 000000000000..769befadd4e4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-evk-camera-csi1-imx577.dtso @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + vreg_cam1_1p8: regulator-cam1 { + compatible = "regulator-fixed"; + regulator-name = "vreg_cam1"; + startup-delay-us = <10000>; + enable-active-high; + gpio = <&pmm8654au_0_gpios 8 GPIO_ACTIVE_HIGH>; + }; +}; + +&camss { + vdda-pll-supply = <&vreg_l1c>; + vdda-phy-supply = <&vreg_l4a>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csiphy1_ep: endpoint { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx577_ep1>; + }; + }; + }; +}; + +&cci1 { + pinctrl-0 = <&cci1_0_default>; + pinctrl-1 = <&cci1_0_sleep>; + + status = "okay"; +}; + +&cci1_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + camera@1a { + compatible = "sony,imx577"; + reg = <0x1a>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam1_default>; + pinctrl-names = "default"; + + clocks = <&camcc CAM_CC_MCLK1_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK1_CLK>; + assigned-clock-rates = <24000000>; + + dovdd-supply = <&vreg_s4a>; + avdd-supply = <&vreg_cam1_1p8>; + + port { + imx577_ep1: endpoint { + clock-lanes = <7>; + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy1_ep>; + }; + }; + }; +}; + +&tlmm { + cam1_default: cam1-default-state { + mclk-pins { + pins = "gpio73"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + rst-pins { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; +}; From e645096d1f6dadcead09c722a3fbc6c44a45fece Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Thu, 11 Sep 2025 23:21:02 +0200 Subject: [PATCH 889/931] arm64: dts: qcom: qcm2290: Add CCI node Add Camera Control Interface (CCI), supporting two I2C masters. Signed-off-by: Loic Poulain Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250911212102.470886-2-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 50 +++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 527705c7d212..08141b41de24 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -566,6 +566,20 @@ qup_uart4_default: qup-uart4-default-state { bias-disable; }; + cci0_default: cci0-default-state { + pins = "gpio22", "gpio23"; + function = "cci_i2c"; + drive-strength = <2>; + bias-disable; + }; + + cci1_default: cci1-default-state { + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + drive-strength = <2>; + bias-disable; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; @@ -1635,6 +1649,42 @@ adreno_smmu: iommu@59a0000 { #iommu-cells = <2>; }; + cci: cci@5c1b000 { + compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci"; + reg = <0x0 0x5c1b000 0x0 0x1000>; + + interrupts = ; + + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>; + clock-names = "ahb", "cci"; + assigned-clocks = <&gcc GCC_CAMSS_CCI_0_CLK>; + assigned-clock-rates = <37500000>; + + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; + + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camss: camss@5c6e000 { compatible = "qcom,qcm2290-camss"; From 520f9fec5d6f5a23e7985140dc4dd9986f0ed140 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 10 Sep 2025 02:55:47 +0300 Subject: [PATCH 890/931] arm64: dts: qcom: sm8450: enable camera clock controller by default Enable camera clock controller on Qualcomm SM8450 boards by default due to a reasonable agreement of having all clock controllers enabled. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250909235547.787396-1-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 9ebf2b8700d2..e9ffa0af3cb3 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3300,7 +3300,6 @@ camcc: clock-controller@ade0000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - status = "disabled"; }; mdss: display-subsystem@ae00000 { From b4f745f1d8adad62ba8c2065873c8a857ed4c3da Mon Sep 17 00:00:00 2001 From: Ziyue Zhang Date: Thu, 4 Sep 2025 14:52:25 +0800 Subject: [PATCH 891/931] arm64: dts: qcom: lemans: Add PCIe lane equalization preset properties Add PCIe lane equalization preset properties with all values set to 5 for 8.0 GT/s and 16.0 GT/s data rates to enhance link stability. Co-developed-by: Qiang Yu Signed-off-by: Qiang Yu Signed-off-by: Ziyue Zhang Reviewed-by: Konrad Dybcio Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20250904065225.1762793-4-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 7e40f59e4aa3..4e6b42731d64 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -8327,6 +8327,9 @@ pcie0: pcie@1c00000 { phys = <&pcie0_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + status = "disabled"; pcieport0: pcie@0 { @@ -8497,6 +8500,9 @@ pcie1: pcie@1c10000 { phys = <&pcie1_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + status = "disabled"; pcie@0 { From 651b30c58775e334c79aa3ecd44a3d98ac201db2 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 5 Sep 2025 07:39:39 -0700 Subject: [PATCH 892/931] riscv: dts: starfive: add common board dtsi for Milk-V Mars CM variants Add a common board dtsi for use by Milk-V Mars CM and Milk-V Mars CM Lite. Signed-off-by: E Shattow Signed-off-by: Conor Dooley --- .../dts/starfive/jh7110-milkv-marscm.dtsi | 159 ++++++++++++++++++ 1 file changed, 159 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi new file mode 100644 index 000000000000..25b70af564ee --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 E Shattow + */ + +/dts-v1/; +#include +#include "jh7110-common.dtsi" + +/ { + aliases { + i2c1 = &i2c1; + i2c3 = &i2c3; + i2c4 = &i2c4; + serial3 = &uart3; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&sysgpio 33 GPIO_ACTIVE_LOW>; + }; +}; + +&gmac0 { + assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; + assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; + starfive,tx-use-rgmii-clk; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c6 { + status = "disabled"; +}; + +&mmc1 { + #address-cells = <1>; + #size-cells = <0>; + + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + status = "okay"; + + ap6256: wifi@1 { + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&sysgpio>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-0 = <&wifi_host_wake_irq>; + pinctrl-names = "default"; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&phy0 { + rx-internal-delay-ps = <1500>; + tx-internal-delay-ps = <1500>; + motorcomm,rx-clk-drv-microamp = <3970>; + motorcomm,rx-data-drv-microamp = <2910>; + motorcomm,tx-clk-10-inverted; + motorcomm,tx-clk-100-inverted; + motorcomm,tx-clk-1000-inverted; + motorcomm,tx-clk-adj-enabled; +}; + +&pwm { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&sysgpio { + uart1_pins: uart1-0 { + tx-pins { + pinmux = ; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + }; + + rx-pins { + pinmux = ; + bias-pull-up; + input-enable; + input-schmitt-enable; + }; + + cts-pins { + pinmux = ; + bias-disable; + input-enable; + input-schmitt-enable; + }; + + rts-pins { + pinmux = ; + bias-disable; + input-disable; + input-schmitt-disable; + }; + }; + + usb0_pins: usb0-0 { + vbus-pins { + pinmux = ; + bias-disable; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + wifi_host_wake_irq: wifi-host-wake-irq-0 { + wake-pins { + pinmux = ; + input-enable; + }; + }; +}; + +&uart1 { + uart-has-rtscts; + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins>; + status = "okay"; +}; From d1829e0b2f0619c39b0ce0b84fcbf67569108376 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 5 Sep 2025 07:39:40 -0700 Subject: [PATCH 893/931] dt-bindings: riscv: starfive: add milkv,marscm-emmc Add "milkv,marscm-emmc" as a StarFive JH7110 SoC-based system-on-module. Signed-off-by: E Shattow Acked-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/starfive.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index 7ef85174353d..0713edb687fe 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -28,6 +28,7 @@ properties: - enum: - deepcomputing,fml13v01 - milkv,mars + - milkv,marscm-emmc - pine64,star64 - starfive,visionfive-2-v1.2a - starfive,visionfive-2-v1.3b From 8d193bc0aa2e802be30de331317639482735d738 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 5 Sep 2025 07:39:41 -0700 Subject: [PATCH 894/931] riscv: dts: starfive: add Milk-V Mars CM system-on-module Milk-V Mars CM is a System-on-Module based on the StarFive VisionFive 2 board and Radxa CM3 System-on-Module compatible with the Raspberry Pi CM4IO Classic IO Board. Mars CM SoM features: - StarFive JH7110 System on Chip with RV64GC up to 1.5GHz - AXP15060 Power Management Unit - LPDDR4 2GB / 4GB / 8GB DRAM memory - BL24C04F 4K bits (512 x 8) EEPROM - GigaDevice 25LQ128EWIG QSPI NOR Flash 16M or SoC ROM UART loader for boot (selectable by GPIO) - eMMC5.0 8GB / 16GB / 32GB flash storage onboard - AP6256 via SDIO 2.0 onboard wireless connectivity WiFi 5 + Bluetooth 5.2 (optional, present in models with WiFi feature) - 1x Motorcomm YT8531C Gigabit Ethernet PHY - IMG BXE-4-32 Integrated GPU with 3D Acceleration: - H.264 & H.265 4K@60fps Decoding - H.265 1080p@30fps Encoding - JPEG encoder / decoder Additional features available via 2x 100-pin connectors for CM4IO Board: - 1x HDMI 2.0 - 1x MIPI DSI (4-lanes) - 1x 2CH Audio out (via GPIO) - 1x MIPI CSI (2x2-lanes or 1x4-lanes) - 1x USB 2.0 - 1x PCIe 1-lane Host, Gen 2 (5Gbps) - Up to 28x GPIO, supporting 3.3V - UART x6 - PWM x8 - I2C x7 - SPI - I2S Link to Milk-V Mars CM schematics: https://github.com/milkv-mars/mars-files/tree/main/Mars-CM_Hardware_Schematices Link to StarFive JH7110 Technical Reference Manual: https://doc-en.rvspace.org/JH7110/TRM/index.html Link to Raspberry Pi CM4IO datasheet: https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf Add the devicetree file to make use of StarFive JH7110 common supported features PMIC, EEPROM, UART, I2C, GPIO, eMMC, PCIe, QSPI Flash, PWM, and Ethernet. Also configure the common SD Card interface mmc1 for onboard SDIO BT+WiFi. Signed-off-by: E Shattow Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/Makefile | 1 + .../boot/dts/starfive/jh7110-milkv-marscm-emmc.dts | 12 ++++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-emmc.dts diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile index b3bb12f78e7d..79742617ddab 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-deepcomputing-fml13v01.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb +dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-emmc.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-emmc.dts b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-emmc.dts new file mode 100644 index 000000000000..e568537af2c4 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-emmc.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 E Shattow + */ + +/dts-v1/; +#include "jh7110-milkv-marscm.dtsi" + +/ { + model = "Milk-V Mars CM"; + compatible = "milkv,marscm-emmc", "starfive,jh7110"; +}; From 12a29108384cfe073a4de778d5207d53b492f85e Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 5 Sep 2025 07:39:42 -0700 Subject: [PATCH 895/931] dt-bindings: riscv: starfive: add milkv,marscm-lite Add "milkv,marscm-lite" as a StarFive JH7110 SoC-based system-on-module. Signed-off-by: E Shattow Acked-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/starfive.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index 0713edb687fe..04510341a71e 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -29,6 +29,7 @@ properties: - deepcomputing,fml13v01 - milkv,mars - milkv,marscm-emmc + - milkv,marscm-lite - pine64,star64 - starfive,visionfive-2-v1.2a - starfive,visionfive-2-v1.3b From 4cce8b2503ab50f75a2dbc3eef2e55722836588e Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 5 Sep 2025 07:39:43 -0700 Subject: [PATCH 896/931] riscv: dts: starfive: add Milk-V Mars CM Lite system-on-module Milk-V Mars CM Lite is a System-on-Module based on the Milk-V Mars CM without the onboard eMMC storage component populated and configured instead for SD3.0 Card Slot on that interface via 100-pin connector. Link to Milk-V Mars CM Lite schematics: https://github.com/milkv-mars/mars-files/tree/main/Mars-CM_Hardware_Schematices Link to StarFive JH7110 Technical Reference Manual: https://doc-en.rvspace.org/JH7110/TRM/index.html Link to Raspberry Pi CM4IO datasheet: https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf Add the devicetree file to make use of StarFive JH7110 common supported features PMIC, EEPROM, UART, I2C, GPIO, PCIe, QSPI Flash, PWM, and Ethernet. Also configure the eMMC interface mmc0 for SD Card use and configure the common SD Card interface mmc1 for onboard SDIO BT+WiFi. Signed-off-by: E Shattow Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/Makefile | 1 + .../dts/starfive/jh7110-milkv-marscm-lite.dts | 25 +++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile index 79742617ddab..62b659f89ba7 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-deepcomputing-fml13v01.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-emmc.dtb +dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-lite.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts new file mode 100644 index 000000000000..6c40d0ec4011 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 E Shattow + */ + +/dts-v1/; +#include "jh7110-milkv-marscm.dtsi" + +/ { + model = "Milk-V Mars CM Lite"; + compatible = "milkv,marscm-lite", "starfive,jh7110"; +}; + +&mmc0 { + bus-width = <4>; + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; +}; + +&mmc0_pins { + pwren-pins { + pinmux = ; + }; +}; From e36b9782fafa4502bd2d3e2aaf4fbf425e9ca908 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 4 Sep 2025 10:44:22 +0200 Subject: [PATCH 897/931] arm64: dts: qcom: apq8016-sbc: Correct HDMI bridge #sound-dai-cells HDMI bridge has only one sound DAI and bindings already expect that (dtbs_check): apq8016-sbc.dtb: bridge@39 (adi,adv7533): #sound-dai-cells: 0 was expected Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Tested-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250904084421.82985-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index b0c594c5f236..9c71de589749 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -181,7 +181,7 @@ adv_bridge: bridge@39 { pinctrl-names = "default","sleep"; pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; - #sound-dai-cells = <1>; + #sound-dai-cells = <0>; ports { #address-cells = <1>; @@ -346,7 +346,7 @@ cpu { sound-dai = <&lpass MI2S_QUATERNARY>; }; codec { - sound-dai = <&adv_bridge 0>; + sound-dai = <&adv_bridge>; }; }; From 24f8b8ef130b7249684948a2a82318476f7ab11c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 4 Sep 2025 10:44:23 +0200 Subject: [PATCH 898/931] arm64: dts: qcom: apq8016-sbc: Drop redundant HDMI bridge status New device nodes are enabled by default, so status is redundant. No functional impact, verified with dtx_diff. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250904084421.82985-4-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 9c71de589749..ba6ccf0db16a 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -157,8 +157,6 @@ &blsp_i2c4 { status = "okay"; adv_bridge: bridge@39 { - status = "okay"; - compatible = "adi,adv7533"; reg = <0x39>; From 8b9b2af6de97e2d2cfcfb5d92178c198f01e1559 Mon Sep 17 00:00:00 2001 From: Antonio Rische Date: Thu, 4 Sep 2025 15:54:54 +0200 Subject: [PATCH 899/931] arm64: dts: qcom: sdm845-enchilada: Add notification LED Add the notification LED for the device. The R/G/B channels are controlled by the PMI8998 LPG. Signed-off-by: Antonio Rische Signed-off-by: David Heidelberg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250904-enchilada-led-v1-1-dcf936ea7795@ixit.cz Signed-off-by: Bjorn Andersson --- .../dts/qcom/sdm845-oneplus-enchilada.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index bfbc3e6e71bb..a259eb9d45ae 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -5,6 +5,7 @@ * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ +#include #include "sdm845-oneplus-common.dtsi" / { @@ -61,6 +62,33 @@ &pmi8998_charger { monitored-battery = <&battery>; }; +&pmi8998_lpg { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@3 { + reg = <3>; + color = ; + }; + + led@4 { + reg = <4>; + color = ; + }; + + led@5 { + reg = <5>; + color = ; + }; + }; +}; + &sound { model = "OnePlus 6"; audio-routing = "RX_BIAS", "MCLK", From 4e26b0f4f1a965e366795c100bd7a8ee1635ed14 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Wed, 2 Jul 2025 13:53:11 +0530 Subject: [PATCH 900/931] arm64: dts: qcom: qcs615: Enable TSENS support for QCS615 SoC Add TSENS and thermal devicetree node for QCS615 SoC. Signed-off-by: Gaurav Kohli Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250702082311.4123461-3-quic_gkohli@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6150.dtsi | 206 ++++++++++++++++++++++++++- 1 file changed, 205 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi index 8757e0501591..3d2a1cb02b62 100644 --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi @@ -4163,6 +4163,17 @@ usb_2_dwc3: usb@a800000 { }; }; + tsens0: thermal-sensor@c263000 { + compatible = "qcom,qcs615-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c263000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + remoteproc_adsp: remoteproc@62400000 { compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas"; reg = <0x0 0x62400000 0x0 0x4040>; @@ -4249,7 +4260,6 @@ cpufreq_hw: cpufreq@18323000 { #freq-domain-cells = <1>; #clock-cells = <1>; }; - }; arch_timer: timer { @@ -4259,4 +4269,198 @@ arch_timer: timer { , ; }; + + thermal-zones { + aoss-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + aoss-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-0-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + cpuss0-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-1-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + cpuss1-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-2-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + cpuss2-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-3-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + cpuss3-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-0-thermal { + thermal-sensors = <&tsens0 5>; + + trips { + cpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-1-thermal { + thermal-sensors = <&tsens0 6>; + + trips { + cpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-2-thermal { + thermal-sensors = <&tsens0 7>; + + trips { + cpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-3-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + cpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + gpu-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + q6-hvx-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + q6-hvx-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mdm-core-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + mdm-core-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camera-thermal { + thermal-sensors = <&tsens0 12>; + + trips { + camera-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + wlan-thermal { + thermal-sensors = <&tsens0 13>; + + trips { + wlan-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + display-thermal { + thermal-sensors = <&tsens0 14>; + + trips { + display-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens0 15>; + + trips { + video-critical { + temperature = <115000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; }; From 4d94abded400a5194b929c26b3aa07fb9485fe35 Mon Sep 17 00:00:00 2001 From: Han Gao Date: Wed, 10 Sep 2025 18:55:31 +0800 Subject: [PATCH 901/931] dts: sophgo: sg2042: added numa id description According to the description of [1], sg2042 is divided into 4 numa. STREAM test performance will improve. Before: Function Best Rate MB/s Avg time Min time Max time Copy: 10739.7 0.015687 0.014898 0.016385 Scale: 10865.9 0.015628 0.014725 0.016757 Add: 10622.3 0.023276 0.022594 0.023899 Triad: 10583.4 0.023653 0.022677 0.024761 After: Function Best Rate MB/s Avg time Min time Max time Copy: 34254.9 0.005142 0.004671 0.005995 Scale: 37735.5 0.004752 0.004240 0.005407 Add: 44206.8 0.005983 0.005429 0.006461 Triad: 43040.6 0.006320 0.005576 0.006996 [1] https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/pic/mesh.png Signed-off-by: Han Gao Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/20250910105531.519897-1-rabenda.cn@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 64 +++++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 20 +++++++ 2 files changed, 84 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index 77ded5304272..94a4b71acad3 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -272,6 +272,7 @@ cpu0: cpu@0 { d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -299,6 +300,7 @@ cpu1: cpu@1 { d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -326,6 +328,7 @@ cpu2: cpu@2 { d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -353,6 +356,7 @@ cpu3: cpu@3 { d-cache-sets = <512>; next-level-cache = <&l2_cache0>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -380,6 +384,7 @@ cpu4: cpu@4 { d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -407,6 +412,7 @@ cpu5: cpu@5 { d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu5_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -434,6 +440,7 @@ cpu6: cpu@6 { d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu6_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -461,6 +468,7 @@ cpu7: cpu@7 { d-cache-sets = <512>; next-level-cache = <&l2_cache1>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu7_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -488,6 +496,7 @@ cpu8: cpu@8 { d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu8_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -515,6 +524,7 @@ cpu9: cpu@9 { d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu9_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -542,6 +552,7 @@ cpu10: cpu@10 { d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu10_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -569,6 +580,7 @@ cpu11: cpu@11 { d-cache-sets = <512>; next-level-cache = <&l2_cache4>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu11_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -596,6 +608,7 @@ cpu12: cpu@12 { d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu12_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -623,6 +636,7 @@ cpu13: cpu@13 { d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu13_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -650,6 +664,7 @@ cpu14: cpu@14 { d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu14_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -677,6 +692,7 @@ cpu15: cpu@15 { d-cache-sets = <512>; next-level-cache = <&l2_cache5>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu15_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -704,6 +720,7 @@ cpu16: cpu@16 { d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu16_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -731,6 +748,7 @@ cpu17: cpu@17 { d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu17_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -758,6 +776,7 @@ cpu18: cpu@18 { d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu18_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -785,6 +804,7 @@ cpu19: cpu@19 { d-cache-sets = <512>; next-level-cache = <&l2_cache2>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu19_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -812,6 +832,7 @@ cpu20: cpu@20 { d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu20_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -839,6 +860,7 @@ cpu21: cpu@21 { d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu21_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -866,6 +888,7 @@ cpu22: cpu@22 { d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu22_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -893,6 +916,7 @@ cpu23: cpu@23 { d-cache-sets = <512>; next-level-cache = <&l2_cache3>; mmu-type = "riscv,sv39"; + numa-node-id = <0>; cpu23_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -920,6 +944,7 @@ cpu24: cpu@24 { d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu24_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -947,6 +972,7 @@ cpu25: cpu@25 { d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu25_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -974,6 +1000,7 @@ cpu26: cpu@26 { d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu26_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1001,6 +1028,7 @@ cpu27: cpu@27 { d-cache-sets = <512>; next-level-cache = <&l2_cache6>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu27_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1028,6 +1056,7 @@ cpu28: cpu@28 { d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu28_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1055,6 +1084,7 @@ cpu29: cpu@29 { d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu29_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1082,6 +1112,7 @@ cpu30: cpu@30 { d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu30_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1109,6 +1140,7 @@ cpu31: cpu@31 { d-cache-sets = <512>; next-level-cache = <&l2_cache7>; mmu-type = "riscv,sv39"; + numa-node-id = <1>; cpu31_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1136,6 +1168,7 @@ cpu32: cpu@32 { d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu32_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1163,6 +1196,7 @@ cpu33: cpu@33 { d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu33_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1190,6 +1224,7 @@ cpu34: cpu@34 { d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu34_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1217,6 +1252,7 @@ cpu35: cpu@35 { d-cache-sets = <512>; next-level-cache = <&l2_cache8>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu35_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1244,6 +1280,7 @@ cpu36: cpu@36 { d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu36_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1271,6 +1308,7 @@ cpu37: cpu@37 { d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu37_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1298,6 +1336,7 @@ cpu38: cpu@38 { d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu38_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1325,6 +1364,7 @@ cpu39: cpu@39 { d-cache-sets = <512>; next-level-cache = <&l2_cache9>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu39_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1352,6 +1392,7 @@ cpu40: cpu@40 { d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu40_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1379,6 +1420,7 @@ cpu41: cpu@41 { d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu41_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1406,6 +1448,7 @@ cpu42: cpu@42 { d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu42_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1433,6 +1476,7 @@ cpu43: cpu@43 { d-cache-sets = <512>; next-level-cache = <&l2_cache12>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu43_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1460,6 +1504,7 @@ cpu44: cpu@44 { d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu44_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1487,6 +1532,7 @@ cpu45: cpu@45 { d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu45_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1514,6 +1560,7 @@ cpu46: cpu@46 { d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu46_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1541,6 +1588,7 @@ cpu47: cpu@47 { d-cache-sets = <512>; next-level-cache = <&l2_cache13>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu47_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1568,6 +1616,7 @@ cpu48: cpu@48 { d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu48_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1595,6 +1644,7 @@ cpu49: cpu@49 { d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu49_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1622,6 +1672,7 @@ cpu50: cpu@50 { d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu50_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1649,6 +1700,7 @@ cpu51: cpu@51 { d-cache-sets = <512>; next-level-cache = <&l2_cache10>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu51_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1676,6 +1728,7 @@ cpu52: cpu@52 { d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu52_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1703,6 +1756,7 @@ cpu53: cpu@53 { d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu53_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1730,6 +1784,7 @@ cpu54: cpu@54 { d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu54_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1757,6 +1812,7 @@ cpu55: cpu@55 { d-cache-sets = <512>; next-level-cache = <&l2_cache11>; mmu-type = "riscv,sv39"; + numa-node-id = <2>; cpu55_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1784,6 +1840,7 @@ cpu56: cpu@56 { d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu56_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1811,6 +1868,7 @@ cpu57: cpu@57 { d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu57_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1838,6 +1896,7 @@ cpu58: cpu@58 { d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu58_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1865,6 +1924,7 @@ cpu59: cpu@59 { d-cache-sets = <512>; next-level-cache = <&l2_cache14>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu59_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1892,6 +1952,7 @@ cpu60: cpu@60 { d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu60_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1919,6 +1980,7 @@ cpu61: cpu@61 { d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu61_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1946,6 +2008,7 @@ cpu62: cpu@62 { d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu62_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -1973,6 +2036,7 @@ cpu63: cpu@63 { d-cache-sets = <512>; next-level-cache = <&l2_cache15>; mmu-type = "riscv,sv39"; + numa-node-id = <3>; cpu63_intc: interrupt-controller { compatible = "riscv,cpu-intc"; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index b3e4d3c18fdc..029561b6ad81 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -19,6 +19,26 @@ / { #size-cells = <2>; dma-noncoherent; + distance-map { + compatible = "numa-distance-map-v1"; + distance-matrix = <0 0 10>, + <0 1 15>, + <0 2 25>, + <0 3 30>, + <1 0 15>, + <1 1 10>, + <1 2 30>, + <1 3 25>, + <2 0 25>, + <2 1 30>, + <2 2 10>, + <2 3 15>, + <3 0 30>, + <3 1 25>, + <3 2 15>, + <3 3 10>; + }; + aliases { serial0 = &uart0; }; From 6e5c4c093c7215198ea9fa83dcbc47d3f961de7a Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Wed, 17 Sep 2025 18:08:27 +0530 Subject: [PATCH 902/931] arm64: dts: qcom: lemans: Flatten usb controller nodes Flatten usb controller nodes and update to using latest bindings and flattened driver approach. Enumeration of ADB has been tested on EVK Platform. Signed-off-by: Krishna Kurapati Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250917123827.671966-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 6 +- .../boot/dts/qcom/lemans-ride-common.dtsi | 15 +-- arch/arm64/boot/dts/qcom/lemans.dtsi | 96 ++++++++----------- 3 files changed, 44 insertions(+), 73 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index d5dbcbd86171..c7dc9b8f4457 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -751,11 +751,9 @@ &ufs_mem_phy { }; &usb_0 { - status = "okay"; -}; - -&usb_0_dwc3 { dr_mode = "peripheral"; + + status = "okay"; }; &usb_0_hsphy { diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index 25e756c14160..c69aa2f41ce2 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -997,14 +997,11 @@ &ufs_mem_phy { &usb_0 { pinctrl-names = "default"; pinctrl-0 = <&usb0_en_state>; + dr_mode = "peripheral"; status = "okay"; }; -&usb_0_dwc3 { - dr_mode = "peripheral"; -}; - &usb_0_hsphy { vdda-pll-supply = <&vreg_l7a>; vdda18-supply = <&vreg_l6c>; @@ -1023,14 +1020,11 @@ &usb_0_qmpphy { &usb_1 { pinctrl-names = "default"; pinctrl-0 = <&usb1_en_state>; + dr_mode = "host"; status = "okay"; }; -&usb_1_dwc3 { - dr_mode = "host"; -}; - &usb_1_hsphy { vdda-pll-supply = <&vreg_l7a>; vdda18-supply = <&vreg_l6c>; @@ -1049,14 +1043,11 @@ &usb_1_qmpphy { &usb_2 { pinctrl-names = "default"; pinctrl-0 = <&usb2_en_state>; + dr_mode = "host"; status = "okay"; }; -&usb_2_dwc3 { - dr_mode = "host"; -}; - &usb_2_hsphy { vdda-pll-supply = <&vreg_l7a>; vdda18-supply = <&vreg_l6c>; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 4e6b42731d64..48f753002fc4 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -3925,12 +3925,9 @@ usb_0_qmpphy: phy@88e8000 { status = "disabled"; }; - usb_0: usb@a6f8800 { - compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_0: usb@a600000 { + compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a600000 0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>, @@ -3943,12 +3940,14 @@ usb_0: usb@a6f8800 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", @@ -3965,18 +3964,13 @@ usb_0: usb@a6f8800 { wakeup-source; - status = "disabled"; + iommus = <&apps_smmu 0x080 0x0>; + phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; - usb_0_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xe000>; - interrupts = ; - iommus = <&apps_smmu 0x080 0x0>; - phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; - phy-names = "usb2-phy", "usb3-phy"; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - }; + status = "disabled"; }; usb_1_hsphy: phy@88e6000 { @@ -4016,12 +4010,9 @@ usb_1_qmpphy: phy@88ea000 { status = "disabled"; }; - usb_1: usb@a8f8800 { - compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; - reg = <0 0x0a8f8800 0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_1: usb@a800000 { + compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a800000 0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&gcc GCC_USB30_SEC_MASTER_CLK>, @@ -4034,12 +4025,14 @@ usb_1: usb@a8f8800 { <&gcc GCC_USB30_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc 7 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", @@ -4056,18 +4049,13 @@ usb_1: usb@a8f8800 { wakeup-source; - status = "disabled"; + iommus = <&apps_smmu 0x0a0 0x0>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; - usb_1_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0 0x0a800000 0 0xe000>; - interrupts = ; - iommus = <&apps_smmu 0x0a0 0x0>; - phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; - phy-names = "usb2-phy", "usb3-phy"; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - }; + status = "disabled"; }; usb_2_hsphy: phy@88e7000 { @@ -4083,12 +4071,9 @@ usb_2_hsphy: phy@88e7000 { status = "disabled"; }; - usb_2: usb@a4f8800 { - compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; - reg = <0 0x0a4f8800 0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_2: usb@a400000 { + compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; + reg = <0 0x0a400000 0 0xfc100>; clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, <&gcc GCC_USB20_MASTER_CLK>, @@ -4101,11 +4086,13 @@ usb_2: usb@a4f8800 { <&gcc GCC_USB20_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "pwr_event", + interrupt-names = "dwc_usb3", + "pwr_event", "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; @@ -4121,18 +4108,13 @@ usb_2: usb@a4f8800 { wakeup-source; - status = "disabled"; + iommus = <&apps_smmu 0x020 0x0>; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; - usb_2_dwc3: usb@a400000 { - compatible = "snps,dwc3"; - reg = <0 0x0a400000 0 0xe000>; - interrupts = ; - iommus = <&apps_smmu 0x020 0x0>; - phys = <&usb_2_hsphy>; - phy-names = "usb2-phy"; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - }; + status = "disabled"; }; tcsr_mutex: hwlock@1f40000 { From b410d25fb349bc32132749bd2cb17aa17054287d Mon Sep 17 00:00:00 2001 From: Manikanta Mylavarapu Date: Wed, 17 Sep 2025 15:49:00 +0400 Subject: [PATCH 903/931] arm64: dts: qcom: ipq5018: add QUP1 UART2 node Add node to support the second UART node controller in IPQ5018. Signed-off-by: Manikanta Mylavarapu Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20250917-ipq5018-uart2-v1-1-f8680bbf947f@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 5ba33255659e..f024b3cba33f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -490,6 +490,16 @@ blsp1_uart1: serial@78af000 { status = "disabled"; }; + blsp1_uart2: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + blsp1_spi1: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; From 48e7e8996cf78101da5aa8292647ed960506da03 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Barnab=C3=A1s=20Cz=C3=A9m=C3=A1n?= Date: Wed, 3 Sep 2025 23:27:33 +0200 Subject: [PATCH 904/931] arm64: dts: qcom: msm8953-xiaomi-daisy: fix cd-gpios MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SD detection was not working because cd-gpios flag was wrongly configured, according to downstream sources device is using GPIO_ACTIVE_HIGH. Fix SD detection with change cd-gpios from GPIO_ACTIVE_LOW to GPIO_ACTIVE_HIGH. Fixes: 38d779c26395 ("arm64: dts: qcom: msm8953: Add device tree for Xiaomi Mi A2 Lite") Signed-off-by: Barnabás Czémán Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250903-daisy-sd-fix-v2-1-e08c50f3be57@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts index 336b916729e4..ddd7af616794 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts @@ -296,7 +296,7 @@ &sdhc_2 { vmmc-supply = <&pm8953_l11>; vqmmc-supply = <&pm8953_l12>; - cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + cd-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; From 141714e163bbb7620d538af48fce4024a4f239e1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 2 Sep 2025 16:00:19 +0200 Subject: [PATCH 905/931] arm64: dts: qcom: sm8750-mtp: Add WiFi and Bluetooth MTP8750 rev 2.0 (power grid v8) boards come as two different variants with different WiFi chips: WCN7850 and WCN786x. WCN7850 is already supported by the kernel, but WCN786x is not. Both of the board variants are considered newest revisions and the difference is only in MCN numbers and internal codenames. Add WCN7850 WiFi and Bluetooth to the MTP8750, stating that this DTS represents the WCN7850 variant. The S4D and S5F regulators should operate at 0.85 V, thus adjust lower constraint and regulator name. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250902140018.247209-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 147 +++++++++++++++++++++++- 1 file changed, 143 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 946ba53fe63a..3bbb53b7c71f 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -201,6 +201,74 @@ vph_pwr: vph-pwr-regulator { regulator-always-on; regulator-boot-on; }; + + /* + * MTPs rev 2.0 (power grid v8) come with two different WiFi chips: + * WCN7850 and WCN786x. + * Device nodes here for the PMU, WiFi and Bluetooth describe the MTP + * variant with WCN7850. + */ + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en>, <&bt_default>; + + wlan-enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&pm8550ve_f_gpios 3 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vreg_s5f_0p85>; + vddio-supply = <&vreg_l3f_1p8>; + vddio1p2-supply = <&vreg_l2f_1p2>; + vddaon-supply = <&vreg_s4d_0p85>; + vdddig-supply = <&vreg_s1d_0p97>; + vddrfa1p2-supply = <&vreg_s7i_1p2>; + vddrfa1p8-supply = <&vreg_s3g_1p8>; + + clocks = <&rpmhcc RPMH_RF_CLK1>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; }; &apps_rsc { @@ -426,7 +494,7 @@ vreg_s3d_1p2: smps3 { vreg_s4d_0p85: smps4 { regulator-name = "vreg_s4d_0p85"; - regulator-min-microvolt = <500000>; + regulator-min-microvolt = <852000>; regulator-max-microvolt = <1036000>; regulator-initial-mode = ; }; @@ -472,9 +540,9 @@ regulators-2 { qcom,pmic-id = "f"; - vreg_s5f_0p5: smps5 { - regulator-name = "vreg_s5f_0p5"; - regulator-min-microvolt = <500000>; + vreg_s5f_0p85: smps5 { + regulator-name = "vreg_s5f_0p85"; + regulator-min-microvolt = <852000>; regulator-max-microvolt = <1000000>; regulator-initial-mode = ; }; @@ -891,6 +959,40 @@ &pon_resin { status = "okay"; }; +&pcie0 { + wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1f_0p88>; + vdda-pll-supply = <&vreg_l3g_1p2>; + + status = "okay"; +}; + +&pcieport0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pmih0108_eusb2_repeater { status = "okay"; @@ -902,6 +1004,10 @@ &qupv3_1 { status = "okay"; }; +&qupv3_2 { + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/sm8750/adsp.mbn", "qcom/sm8750/adsp_dtb.mbn"; @@ -1035,6 +1141,14 @@ spkr_1_sd_n_active: spkr-1-sd-n-active-state { }; &tlmm { + bt_default: bt-default-state { + sw-ctrl-pins { + pins = "gpio18"; + function = "gpio"; + bias-pull-down; + }; + }; + wcd_default: wcd-reset-n-active-state { pins = "gpio101"; function = "gpio"; @@ -1042,6 +1156,31 @@ wcd_default: wcd-reset-n-active-state { bias-disable; output-low; }; + + wlan_en: wlan-en-state { + pins = "gpio16"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + + max-speed = <3200000>; + }; }; &ufs_mem_phy { From 458bb855f274e227618acfa8c098b8e4894d9cd9 Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Wed, 17 Sep 2025 10:58:58 +0800 Subject: [PATCH 906/931] dt-bindings: arm: qcom: Document HAMOA-IOT-EVK board Document the device tree binding for the HAMOA-IOT-EVK board, which uses the Qualcomm X1E80100 SoC. The EVK consists of a carrier board and a modular System-on-Module (SoM). The SoM integrates the SoC, PMICs, and essential GPIOs, while the EVK carrier board provides additional peripherals such as UART and USB interfaces. Acked-by: Krzysztof Kozlowski Signed-off-by: Yijie Yang Link: https://lore.kernel.org/r/20250917-hamoa_initial-v12-1-4ed39d17dfc5@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 68cc458ca6bf..4f403b99c3fd 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1069,6 +1069,12 @@ properties: - qcom,x1e80100-qcp - const: qcom,x1e80100 + - items: + - enum: + - qcom,hamoa-iot-evk + - const: qcom,hamoa-iot-som + - const: qcom,x1e80100 + - items: - enum: - asus,zenbook-a14-ux3407qa From 5098ae93ce44110a4d86574819b254fd126243af Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Wed, 17 Sep 2025 10:58:59 +0800 Subject: [PATCH 907/931] arm64: dts: qcom: Add HAMOA-IOT-SOM platform MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The HAMOA-IOT-SOM is a compact computing module that integrates a System on Chip (SoC) — specifically the x1e80100 — along with essential components optimized for IoT applications. It is designed to be mounted on carrier boards, enabling the development of complete embedded systems. Make the following peripherals on the SOM enabled: - Regulators on the SOM - Reserved memory regions - PCIe6a and its PHY - PCIe4 and its PHY - USB0 through USB6 and their PHYs - ADSP, CDSP - Graphic - Video Written in collaboration with Yingying Tang (PCIe4) and Wangao Wang (Video) . Reviewed-by: Konrad Dybcio Signed-off-by: Yijie Yang Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250917-hamoa_initial-v12-2-4ed39d17dfc5@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 619 ++++++++++++++++++++ 1 file changed, 619 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi new file mode 100644 index 000000000000..1aead50b8920 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -0,0 +1,619 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "x1e80100.dtsi" +#include "x1e80100-pmics.dtsi" +#include +#include + +/ { + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; +}; + +&apps_rsc { + /* PMC8380C_B */ + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name = "vreg_l5b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name = "vreg_l16b_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380VE_C */ + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380_D */ + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380_E */ + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380_F */ + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1f_1p0: ldo1 { + regulator-name = "vreg_l1f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l2f_1p0: ldo2 { + regulator-name = "vreg_l2f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l3f_1p0: ldo3 { + regulator-name = "vreg_l3f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380VE_I */ + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + /* PMC8380VE_J */ + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; +}; + +&iris { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1e80100/gen70500_zap.mbn"; +}; + +&pcie4 { + perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/adsp.mbn", + "qcom/x1e80100/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/cdsp.mbn", + "qcom/x1e80100/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* TPM LP & INT */ + <44 4>; /* SPI (TPM) */ + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + + }; + }; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss2 { + status = "okay"; +}; + +&usb_1_ss2_dwc3 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_ss2_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; From c11645afb0e228546279ad1b74826fffbfebbc7f Mon Sep 17 00:00:00 2001 From: Yijie Yang Date: Wed, 17 Sep 2025 10:59:00 +0800 Subject: [PATCH 908/931] arm64: dts: qcom: Add base HAMOA-IOT-EVK board The HAMOA-IOT-EVK is an evaluation platform for IoT products, composed of the Hamoa IoT SoM and a carrier board. Together, they form a complete embedded system capable of booting to UART. Make the following peripherals on the carrier board enabled: - UART - On-board regulators - USB Type-C mux - Pinctrl - Embedded USB (EUSB) repeaters - NVMe - pmic-glink - USB DisplayPorts - Bluetooth - WLAN - Audio Written in collaboration with Quill Qi (Audio) , Jie Zhang (Graphics) , Shuai Zhang (Bluetooth) , Yingying Tang (WLAN) , and Yongxing Mou (USB DisplayPorts) . Signed-off-by: Yijie Yang Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250917-hamoa_initial-v12-3-4ed39d17dfc5@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 1222 ++++++++++++++++++++ 2 files changed, 1223 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d7f22476d510..296688f7cb26 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5018-tplink-archer-ax55-v1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts new file mode 100644 index 000000000000..df8d6e5c1f45 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -0,0 +1,1222 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "hamoa-iot-som.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Hamoa IoT EVK"; + compatible = "qcom,hamoa-iot-evk", "qcom,hamoa-iot-som", "qcom,x1e80100"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 + 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 125 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_sbu: endpoint { + remote-endpoint = <&usb_1_ss0_sbu_mux>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + + connector@2 { + compatible = "usb-c-connector"; + reg = <2>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss2_hs_in: endpoint { + remote-endpoint = <&usb_1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss2_ss_in: endpoint { + remote-endpoint = <&retimer_ss2_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss2_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss2_con_sbu_out>; + }; + }; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + /* Left unused as the retimer is not used on this board. */ + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p15: regulator-rtmr2-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 189 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p8: regulator-rtmr2-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 126 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_3p3: regulator-rtmr2-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR2_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 187 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb2_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the EVK mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wwan: regulator-wwan { + compatible = "regulator-fixed"; + + regulator-name = "SDX_VPH_PWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 221 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wwan_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-EVK"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK2 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_woofer>, + <&left_tweeter>, + <&swr0 0>, + <&lpass_wsamacro 0>, + <&right_woofer>, + <&right_tweeter>, + <&swr3 0>, + <&lpass_wsa2macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + usb-1-ss0-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 168 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 167 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss0_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss0_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss0_sbu>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK5>; + + vdd-supply = <&vreg_rtmr2_1p15>; + vdd33-supply = <&vreg_rtmr2_3p3>; + vdd33-cap-supply = <&vreg_rtmr2_3p3>; + vddar-supply = <&vreg_rtmr2_1p15>; + vddat-supply = <&vreg_rtmr2_1p15>; + vddio-supply = <&vreg_rtmr2_1p8>; + + reset-gpios = <&tlmm 185 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr2_default>; + pinctrl-names = "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss2_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss2_ss_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss2_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss2_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr1_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie6a { + vddpe-3v3-supply = <&vreg_nvme>; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2 { + status = "okay"; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-low; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_default: rtmr1-reset-n-active-state { + pins = "gpio176"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr2_default: rtmr2-reset-n-active-state { + pins = "gpio185"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_1p15_reg_en: usb2-pwr-1p15-reg-en-state { + pins = "gpio189"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_1p8_reg_en: usb2-pwr-1p8-reg-en-state { + pins = "gpio126"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_pwr_3p3_reg_en: usb2-pwr-3p3-reg-en-state { + pins = "gpio187"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb_1_ss0_sbu_default: usb-1-ss0-sbu-state { + mode-pins { + pins = "gpio166"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-high; + }; + + oe-n-pins { + pins = "gpio168"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio167"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + wcn_bt_en: wcn-bt-en-state { + pins = "gpio116"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wwan_sw_en: wwan-sw-en-state { + pins = "gpio221"; + function = "gpio"; + drive-strength = <4>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + /* Switches USB signal routing between the USB connector and the Wi-Fi card. */ + wcn_usb_sw_n: wcn-usb-sw-n-state { + pins = "gpio225"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&uart21 { + compatible = "qcom,geni-debug-uart"; + + status = "okay"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_hsphy { + phys = <&smb2360_0_eusb2_repeater>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_hsphy { + phys = <&smb2360_1_eusb2_repeater>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&retimer_ss1_ss_in>; +}; + +&usb_1_ss2_dwc3_hs { + remote-endpoint = <&pmic_glink_ss2_hs_in>; +}; + +&usb_1_ss2_hsphy { + phys = <&smb2360_2_eusb2_repeater>; +}; + +&usb_1_ss2_qmpphy_out { + remote-endpoint = <&retimer_ss2_ss_in>; +}; + +&usb_2_hsphy { + phys = <&eusb5_repeater>; + + pinctrl-0 = <&wcn_usb_sw_n>; + pinctrl-names = "default"; +}; + +&usb_mp_hsphy0 { + phys = <&eusb3_repeater>; +}; + +&usb_mp_hsphy1 { + phys = <&eusb6_repeater>; +}; From 1081eafa1bca16d3610bf44f515550d060526dd4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eric=20Gon=C3=A7alves?= Date: Tue, 16 Sep 2025 18:04:08 +0000 Subject: [PATCH 909/931] dt-bindings: arm: qcom: sort sm8450 boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The bindings had samsung,r0q before sony,pdx*, which is out of alphabetical order, solve this issue by moving samsung,r0q before the pdx boards. Signed-off-by: Eric Gonçalves Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250916180409.157115-1-ghatto404@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 4f403b99c3fd..d89d1093cd15 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1005,9 +1005,9 @@ properties: - enum: - qcom,sm8450-hdk - qcom,sm8450-qrd + - samsung,r0q - sony,pdx223 - sony,pdx224 - - samsung,r0q - const: qcom,sm8450 - items: From 28f94ed138c347504c1b1b94291da8a9a398e0d7 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Sun, 14 Sep 2025 21:38:44 +0200 Subject: [PATCH 910/931] dt-bindings: arm: apple: Add t6020x compatibles This adds the following apple,t6020/t6021/t6022 platforms: - apple,j414s - MacBook Pro (14-inch, M2 Pro, 2023) - apple,j414c - MacBook Pro (14-inch, M2 Nax, 2023) - apple,j416s - MacBook Pro (16-inch, M2 Pro, 2023) - apple,j416c - MacBook Pro (16-inch, M2 Max, 2023) - apple,j474s - Mac mini (M2 Pro, 2023) - apple,j475c - Mac Studio (M2 Max, 2023) - apple,j475d - Mac Studio (M2 Ultra, 2023) - apple,j475d - Mac Pro (M2 Ultra, 2023) Acked-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau Reviewed-by: Sven Peter Signed-off-by: Sven Peter --- .../devicetree/bindings/arm/apple.yaml | 39 ++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index 7073535b7c5b..5c2629ec3d4c 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -96,7 +96,7 @@ description: | - MacBook Pro (13-inch, M2, 2022) - Mac mini (M2, 2023) - And devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs: + Devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs: - MacBook Pro (14-inch, M1 Pro, 2021) - MacBook Pro (14-inch, M1 Max, 2021) @@ -105,6 +105,17 @@ description: | - Mac Studio (M1 Max, 2022) - Mac Studio (M1 Ultra, 2022) + Devices based on the "M2 Pro", "M2 Max" and "M2 Ultra" SoCs: + + - MacBook Pro (14-inch, M2 Pro, 2023) + - MacBook Pro (14-inch, M2 Max, 2023) + - MacBook Pro (16-inch, M2 Pro, 2023) + - MacBook Pro (16-inch, M2 Max, 2023) + - Mac mini (M2 Pro, 2023) + - Mac Studio (M2 Max, 2023) + - Mac Studio (M2 Ultra, 2023) + - Mac Pro (M2 Ultra, 2023) + The compatible property should follow this format: compatible = "apple,", "apple,", "apple,arm-platform"; @@ -310,6 +321,32 @@ properties: - const: apple,t6002 - const: apple,arm-platform + - description: Apple M2 Pro SoC based platforms + items: + - enum: + - apple,j414s # MacBook Pro (14-inch, M2 Pro, 2023) + - apple,j416s # MacBook Pro (16-inch, M2 Pro, 2023) + - apple,j474s # Mac mini (M2 Pro, 2023) + - const: apple,t6020 + - const: apple,arm-platform + + - description: Apple M2 Max SoC based platforms + items: + - enum: + - apple,j414c # MacBook Pro (14-inch, M2 Max, 2023) + - apple,j416c # MacBook Pro (16-inch, M2 Max, 2023) + - apple,j475c # Mac Studio (M2 Max, 2023) + - const: apple,t6021 + - const: apple,arm-platform + + - description: Apple M2 Ultra SoC based platforms + items: + - enum: + - apple,j180d # Mac Pro (M2 Ultra, 2023) + - apple,j475d # Mac Studio (M2 Ultra, 2023) + - const: apple,t6022 + - const: apple,arm-platform + additionalProperties: true ... From 6313115c55f44f7bee3f469c91d3de60d724eabd Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Sun, 14 Sep 2025 21:38:45 +0200 Subject: [PATCH 911/931] arm64: dts: apple: Add ethernet0 alias for J375 template The alias is used by the boot loader to fill the MAC address. Fixes: aaa1d42a4ce3 ("arm64: dts: apple: Add J375 devicetrees") Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau Reviewed-by: Sven Peter Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t600x-j375.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dts/apple/t600x-j375.dtsi index ed38acc0dfc3..c0fb93ae72f4 100644 --- a/arch/arm64/boot/dts/apple/t600x-j375.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi @@ -12,6 +12,7 @@ / { aliases { bluetooth0 = &bluetooth0; + ethernet0 = ðernet0; serial0 = &serial0; wifi0 = &wifi0; }; From a8f20eb60788ab2dcf311b83e875c77c89dd298b Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Sun, 14 Sep 2025 21:38:46 +0200 Subject: [PATCH 912/931] arm64: dts: apple: Add initial t6020/t6021/t6022 DTs These SoCs are found in Apple devices with M2 Pro (t6020), M2 Max (t6021) and M2 Ultra (t6022) and follow the pattern of their M1 counterparts. t6020 is a cut-down version of t6021, so the former just includes the latter and disables the missing bits (This is currently just one PMGR node and all of its domains). t6022 is two connected t6021 dies. The implementation seems to use t6021 with blocks disabled (mostly on the second die). MMIO addresses on the second die have a constant offset. The interrupt controller is multi-die aware. This setup can be represented in the device tree with two top level "soc" nodes. The MMIO offset is applied via "ranges" and devices are included with preproceesor macros to make the node labels unique and to specify the die number for the interrupt definition. Device nodes are distributed over dtsi files based on whether they are present on both dies or just on the first die. The only exception is the NVMe controller which resides on the second die. Its nodes are in a separate file. Signed-off-by: Hector Martin Reviewed-by: Neal Gompa Co-developed-by: Janne Grunau Signed-off-by: Janne Grunau Reviewed-by: Sven Peter Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t6020.dtsi | 22 + arch/arm64/boot/dts/apple/t6021.dtsi | 69 + arch/arm64/boot/dts/apple/t6022.dtsi | 349 +++ arch/arm64/boot/dts/apple/t602x-common.dtsi | 465 ++++ arch/arm64/boot/dts/apple/t602x-die0.dtsi | 575 +++++ arch/arm64/boot/dts/apple/t602x-dieX.dtsi | 128 + .../arm64/boot/dts/apple/t602x-gpio-pins.dtsi | 81 + arch/arm64/boot/dts/apple/t602x-nvme.dtsi | 42 + arch/arm64/boot/dts/apple/t602x-pmgr.dtsi | 2265 +++++++++++++++++ 9 files changed, 3996 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t6020.dtsi create mode 100644 arch/arm64/boot/dts/apple/t6021.dtsi create mode 100644 arch/arm64/boot/dts/apple/t6022.dtsi create mode 100644 arch/arm64/boot/dts/apple/t602x-common.dtsi create mode 100644 arch/arm64/boot/dts/apple/t602x-die0.dtsi create mode 100644 arch/arm64/boot/dts/apple/t602x-dieX.dtsi create mode 100644 arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi create mode 100644 arch/arm64/boot/dts/apple/t602x-nvme.dtsi create mode 100644 arch/arm64/boot/dts/apple/t602x-pmgr.dtsi diff --git a/arch/arm64/boot/dts/apple/t6020.dtsi b/arch/arm64/boot/dts/apple/t6020.dtsi new file mode 100644 index 000000000000..bffa66a3ffff --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6020.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6020 "M2 Pro" SoC + * + * Other names: H14J, "Rhodes Chop" + * + * Copyright The Asahi Linux Contributors + */ + +/* This chip is just a cut down version of t6021, so include it and disable the missing parts */ + +#include "t6021.dtsi" + +/ { + compatible = "apple,t6020", "apple,arm-platform"; +}; + +/delete-node/ &pmgr_south; + +&gpu { + compatible = "apple,agx-g14s"; +}; diff --git a/arch/arm64/boot/dts/apple/t6021.dtsi b/arch/arm64/boot/dts/apple/t6021.dtsi new file mode 100644 index 000000000000..62907ad6a546 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6021.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6021 "M2 Max" SoC + * + * Other names: H14J, "Rhodes" + * + * Copyright The Asahi Linux Contributors + */ + +#include +#include +#include +#include +#include +#include + +#include "multi-die-cpp.h" + +#include "t602x-common.dtsi" + +/ { + compatible = "apple,t6021", "apple,arm-platform"; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges; + nonposted-mmio; + + // filled via templated includes at the end of the file + }; +}; + +#define DIE +#define DIE_NO 0 + +&{/soc} { + #include "t602x-die0.dtsi" + #include "t602x-dieX.dtsi" + #include "t602x-nvme.dtsi" +}; + +#include "t602x-gpio-pins.dtsi" +#include "t602x-pmgr.dtsi" + +#undef DIE +#undef DIE_NO + + +&aic { + affinities { + e-core-pmu-affinity { + apple,fiq-index = ; + cpus = <&cpu_e00 &cpu_e01 &cpu_e02 &cpu_e03>; + }; + + p-core-pmu-affinity { + apple,fiq-index = ; + cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03 + &cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13>; + }; + }; +}; + +&gpu { + compatible = "apple,agx-g14c", "apple,agx-g14s"; +}; diff --git a/arch/arm64/boot/dts/apple/t6022.dtsi b/arch/arm64/boot/dts/apple/t6022.dtsi new file mode 100644 index 000000000000..e73bf2f7510a --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6022.dtsi @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6022 "M2 Ultra" SoC + * + * Other names: H14J, "Rhodes 2C" + * + * Copyright The Asahi Linux Contributors + */ + +#include +#include +#include +#include +#include +#include + +#include "multi-die-cpp.h" + +#include "t602x-common.dtsi" + +/ { + compatible = "apple,t6022", "apple,arm-platform"; + + #address-cells = <2>; + #size-cells = <2>; + + cpus { + cpu-map { + cluster3 { + core0 { + cpu = <&cpu_e10>; + }; + core1 { + cpu = <&cpu_e11>; + }; + core2 { + cpu = <&cpu_e12>; + }; + core3 { + cpu = <&cpu_e13>; + }; + }; + + cluster4 { + core0 { + cpu = <&cpu_p20>; + }; + core1 { + cpu = <&cpu_p21>; + }; + core2 { + cpu = <&cpu_p22>; + }; + core3 { + cpu = <&cpu_p23>; + }; + }; + + cluster5 { + core0 { + cpu = <&cpu_p30>; + }; + core1 { + cpu = <&cpu_p31>; + }; + core2 { + cpu = <&cpu_p32>; + }; + core3 { + cpu = <&cpu_p33>; + }; + }; + }; + + cpu_e10: cpu@800 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x800>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e_die1>; + }; + + cpu_e11: cpu@801 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x801>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e_die1>; + }; + + cpu_e12: cpu@802 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x802>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e_die1>; + }; + + cpu_e13: cpu@803 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x803>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e_die1>; + }; + + cpu_p20: cpu@10900 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10900>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; + }; + + cpu_p21: cpu@10901 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10901>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; + }; + + cpu_p22: cpu@10902 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10902>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; + }; + + cpu_p23: cpu@10903 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10903>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; + }; + + cpu_p30: cpu@10a00 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10a00>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; + }; + + cpu_p31: cpu@10a01 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10a01>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; + }; + + cpu_p32: cpu@10a02 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10a02>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; + }; + + cpu_p33: cpu@10a03 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10a03>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; + }; + + l2_cache_3: l2-cache-3 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x400000>; + }; + + l2_cache_4: l2-cache-4 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x1000000>; + }; + + l2_cache_5: l2-cache-5 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x1000000>; + }; + }; + + die0: soc@200000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x02 0x00000000 0x02 0x00000000 0x4 0x00000000>, + <0x05 0x80000000 0x05 0x80000000 0x1 0x80000000>, + <0x07 0x00000000 0x07 0x00000000 0xf 0x80000000>, + <0x16 0x80000000 0x16 0x80000000 0x5 0x80000000>; + nonposted-mmio; + /* Required to get >32-bit DMA via DARTs */ + dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; + + // filled via templated includes at the end of the file + }; + + die1: soc@2200000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x02 0x00000000 0x22 0x00000000 0x4 0x00000000>, + <0x07 0x00000000 0x27 0x00000000 0xf 0x80000000>, + <0x16 0x80000000 0x36 0x80000000 0x5 0x80000000>; + nonposted-mmio; + /* Required to get >32-bit DMA via DARTs */ + dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; + + // filled via templated includes at the end of the file + }; +}; + +#define DIE +#define DIE_NO 0 + +&die0 { + #include "t602x-die0.dtsi" + #include "t602x-dieX.dtsi" +}; + +#include "t602x-pmgr.dtsi" +#include "t602x-gpio-pins.dtsi" + +#undef DIE +#undef DIE_NO + +#define DIE _die1 +#define DIE_NO 1 + +&die1 { + #include "t602x-dieX.dtsi" + #include "t602x-nvme.dtsi" +}; + +#include "t602x-pmgr.dtsi" + +/delete-node/ &ps_pmp_die1; + +#undef DIE +#undef DIE_NO + +&aic { + affinities { + e-core-pmu-affinity { + apple,fiq-index = ; + cpus = <&cpu_e00 &cpu_e01 &cpu_e02 &cpu_e03 + &cpu_e10 &cpu_e11 &cpu_e12 &cpu_e13>; + }; + + p-core-pmu-affinity { + apple,fiq-index = ; + cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03 + &cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13 + &cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23 + &cpu_p30 &cpu_p31 &cpu_p32 &cpu_p33>; + }; + }; +}; + +&ps_gfx { + // On t6022, the die0 GPU power domain needs both AFR power domains + power-domains = <&ps_afr>, <&ps_afr_die1>; +}; + +&gpu { + compatible = "apple,agx-g14d", "apple,agx-g14s"; +}; diff --git a/arch/arm64/boot/dts/apple/t602x-common.dtsi b/arch/arm64/boot/dts/apple/t602x-common.dtsi new file mode 100644 index 000000000000..9c800a391e7e --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-common.dtsi @@ -0,0 +1,465 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Nodes common to all T602x family SoCs (M2 Pro/Max/Ultra) + * + * Other names: H14J, "Rhodes Chop", "Rhodes", "Rhodes 2C" + * + * Copyright The Asahi Linux Contributors + */ + +/ { + #address-cells = <2>; + #size-cells = <2>; + + aliases { + gpu = &gpu; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_e00>; + }; + core1 { + cpu = <&cpu_e01>; + }; + core2 { + cpu = <&cpu_e02>; + }; + core3 { + cpu = <&cpu_e03>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_p00>; + }; + core1 { + cpu = <&cpu_p01>; + }; + core2 { + cpu = <&cpu_p02>; + }; + core3 { + cpu = <&cpu_p03>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu_p10>; + }; + core1 { + cpu = <&cpu_p11>; + }; + core2 { + cpu = <&cpu_p12>; + }; + core3 { + cpu = <&cpu_p13>; + }; + }; + }; + + cpu_e00: cpu@0 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; + }; + + cpu_e01: cpu@1 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; + }; + + cpu_e02: cpu@2 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; + }; + + cpu_e03: cpu@3 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&blizzard_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; + }; + + cpu_p00: cpu@10100 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0>; + }; + + cpu_p01: cpu@10101 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0>; + }; + + cpu_p02: cpu@10102 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10102>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0>; + }; + + cpu_p03: cpu@10103 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10103>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0>; + }; + + cpu_p10: cpu@10200 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10200>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1>; + }; + + cpu_p11: cpu@10201 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10201>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1>; + }; + + cpu_p12: cpu@10202 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10202>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1>; + }; + + cpu_p13: cpu@10203 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10203>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&avalanche_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1>; + }; + + l2_cache_0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x400000>; + }; + + l2_cache_1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x1000000>; + }; + + l2_cache_2: l2-cache-2 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x1000000>; + }; + }; + + blizzard_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + /* pstate #1 is a dummy clone of #2 */ + opp02 { + opp-hz = /bits/ 64 <912000000>; + opp-level = <2>; + clock-latency-ns = <7700>; + }; + opp03 { + opp-hz = /bits/ 64 <1284000000>; + opp-level = <3>; + clock-latency-ns = <25000>; + }; + opp04 { + opp-hz = /bits/ 64 <1752000000>; + opp-level = <4>; + clock-latency-ns = <33000>; + }; + opp05 { + opp-hz = /bits/ 64 <2004000000>; + opp-level = <5>; + clock-latency-ns = <38000>; + }; + opp06 { + opp-hz = /bits/ 64 <2256000000>; + opp-level = <6>; + clock-latency-ns = <44000>; + }; + opp07 { + opp-hz = /bits/ 64 <2424000000>; + opp-level = <7>; + clock-latency-ns = <48000>; + }; + }; + + avalanche_opp: opp-table-1 { + compatible = "operating-points-v2"; + opp-shared; + + opp01 { + opp-hz = /bits/ 64 <702000000>; + opp-level = <1>; + clock-latency-ns = <7400>; + }; + opp02 { + opp-hz = /bits/ 64 <948000000>; + opp-level = <2>; + clock-latency-ns = <18000>; + }; + opp03 { + opp-hz = /bits/ 64 <1188000000>; + opp-level = <3>; + clock-latency-ns = <21000>; + }; + opp04 { + opp-hz = /bits/ 64 <1452000000>; + opp-level = <4>; + clock-latency-ns = <24000>; + }; + opp05 { + opp-hz = /bits/ 64 <1704000000>; + opp-level = <5>; + clock-latency-ns = <28000>; + }; + opp06 { + opp-hz = /bits/ 64 <1968000000>; + opp-level = <6>; + clock-latency-ns = <31000>; + }; + opp07 { + opp-hz = /bits/ 64 <2208000000>; + opp-level = <7>; + clock-latency-ns = <33000>; + }; + opp08 { + opp-hz = /bits/ 64 <2400000000>; + opp-level = <8>; + clock-latency-ns = <45000>; + }; + opp09 { + opp-hz = /bits/ 64 <2568000000>; + opp-level = <9>; + clock-latency-ns = <47000>; + }; + opp10 { + opp-hz = /bits/ 64 <2724000000>; + opp-level = <10>; + clock-latency-ns = <50000>; + }; + opp11 { + opp-hz = /bits/ 64 <2868000000>; + opp-level = <11>; + clock-latency-ns = <52000>; + }; + opp12 { + opp-hz = /bits/ 64 <3000000000>; + opp-level = <12>; + clock-latency-ns = <57000>; + }; + opp13 { + opp-hz = /bits/ 64 <3132000000>; + opp-level = <13>; + clock-latency-ns = <60000>; + }; + opp14 { + opp-hz = /bits/ 64 <3264000000>; + opp-level = <14>; + clock-latency-ns = <64000>; + }; + opp15 { + opp-hz = /bits/ 64 <3360000000>; + opp-level = <15>; + clock-latency-ns = <64000>; + turbo-mode; + }; + opp16 { + opp-hz = /bits/ 64 <3408000000>; + opp-level = <16>; + clock-latency-ns = <64000>; + turbo-mode; + }; + opp17 { + opp-hz = /bits/ 64 <3504000000>; + opp-level = <17>; + clock-latency-ns = <64000>; + turbo-mode; + }; + }; + + pmu-e { + compatible = "apple,blizzard-pmu"; + interrupt-parent = <&aic>; + interrupts = ; + }; + + pmu-p { + compatible = "apple,avalanche-pmu"; + interrupt-parent = <&aic>; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; + interrupts = , + , + , + ; + }; + + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + clk_200m: clock-200m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "clk_200m"; + }; + + /* + * This is a fabulated representation of the input clock + * to NCO since we don't know the true clock tree. + */ + nco_clkref: clock-ref-nco { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "nco_ref"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpu_globals: globals { + status = "disabled"; + }; + + gpu_hw_cal_a: hw-cal-a { + status = "disabled"; + }; + + gpu_hw_cal_b: hw-cal-b { + status = "disabled"; + }; + + uat_handoff: uat-handoff { + status = "disabled"; + }; + + uat_pagetables: uat-pagetables { + status = "disabled"; + }; + + uat_ttbs: uat-ttbs { + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t602x-die0.dtsi b/arch/arm64/boot/dts/apple/t602x-die0.dtsi new file mode 100644 index 000000000000..2e7d2bf08ddc --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-die0.dtsi @@ -0,0 +1,575 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Devices used on die 0 on the Apple T6022 "M2 Ultra" SoC and present on + * Apple T6020 / T6021 "M2 Pro" / "M2 Max". + * + * Copyright The Asahi Linux Contributors + */ + + nco: clock-controller@28e03c000 { + compatible = "apple,t6020-nco", "apple,t8103-nco"; + reg = <0x2 0x8e03c000 0x0 0x14000>; + clocks = <&nco_clkref>; + #clock-cells = <1>; + }; + + aic: interrupt-controller@28e100000 { + compatible = "apple,t6020-aic", "apple,aic2"; + #interrupt-cells = <4>; + interrupt-controller; + reg = <0x2 0x8e100000 0x0 0xc000>, + <0x2 0x8e10c000 0x0 0x1000>; + reg-names = "core", "event"; + power-domains = <&ps_aic>; + }; + + nub_spmi0: spmi@29e114000 { + compatible = "apple,t6020-spmi", "apple,t8103-spmi"; + reg = <0x2 0x9e114000 0x0 0x100>; + #address-cells = <2>; + #size-cells = <0>; + + pmic1: pmic@f { + compatible = "apple,maverick-pmic", "apple,spmi-nvmem"; + reg = <0xb SPMI_USID>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + pm_setting: pm-setting@1405 { + reg = <0x1405 0x1>; + }; + + rtc_offset: rtc-offset@1411 { + reg = <0x1411 0x6>; + }; + + boot_stage: boot-stage@6001 { + reg = <0x6001 0x1>; + }; + + boot_error_count: boot-error-count@6002,0 { + reg = <0x6002 0x1>; + bits = <0 4>; + }; + + panic_count: panic-count@6002,4 { + reg = <0x6002 0x1>; + bits = <4 4>; + }; + + boot_error_stage: boot-error-stage@6003 { + reg = <0x6003 0x1>; + }; + + shutdown_flag: shutdown-flag@600f,3 { + reg = <0x600f 0x1>; + bits = <3 1>; + }; + + fault_shadow: fault-shadow@867b { + reg = <0x867b 0x10>; + }; + + socd: socd@8b00 { + reg = <0x8b00 0x400>; + }; + }; + }; + }; + + wdt: watchdog@29e2c4000 { + compatible = "apple,t6020-wdt", "apple,t8103-wdt"; + reg = <0x2 0x9e2c4000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + }; + + smc_mbox: mbox@2a2408000 { + compatible = "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x2 0xa2408000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + }; + + smc: smc@2a2400000 { + compatible = "apple,t6020-smc", "apple,t8103-smc"; + reg = <0x2 0xa2400000 0x0 0x4000>, + <0x2 0xa3e00000 0x0 0x100000>; + reg-names = "smc", "sram"; + mboxes = <&smc_mbox>; + + smc_gpio: gpio { + compatible = "apple,smc-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + smc_reboot: reboot { + compatible = "apple,smc-reboot"; + nvmem-cells = <&shutdown_flag>, <&boot_stage>, + <&boot_error_count>, <&panic_count>; + nvmem-cell-names = "shutdown_flag", "boot_stage", + "boot_error_count", "panic_count"; + }; + }; + + pinctrl_smc: pinctrl@2a2820000 { + compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl"; + reg = <0x2 0xa2820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_smc 0 0 30>; + apple,npins = <30>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + sio_dart: iommu@39b008000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x3 0x9b008000 0x0 0x8000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_sio_cpu>; + }; + + fpwm0: pwm@39b030000 { + compatible = "apple,t6020-fpwm", "apple,s5l-fpwm"; + reg = <0x3 0x9b030000 0x0 0x4000>; + power-domains = <&ps_fpwm0>; + clocks = <&clkref>; + #pwm-cells = <2>; + status = "disabled"; + }; + + i2c0: i2c@39b040000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b040000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + i2c1: i2c@39b044000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b044000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c2: i2c@39b048000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b048000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c3: i2c@39b04c000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b04c000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c4: i2c@39b050000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b050000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c5: i2c@39b054000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b054000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c5_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c5>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c6: i2c@39b054000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b054000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c6>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c7: i2c@39b054000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b054000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c7_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c7>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c8: i2c@39b054000 { + compatible = "apple,t6020-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9b054000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c8_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c8>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + spi1: spi@39b104000 { + compatible = "apple,t6020-spi", "apple,t8103-spi"; + reg = <0x3 0x9b104000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_200m>; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi1>; + status = "disabled"; + }; + + spi2: spi@39b108000 { + compatible = "apple,t6020-spi", "apple,t8103-spi"; + reg = <0x3 0x9b108000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkref>; + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi2>; + status = "disabled"; + }; + + spi4: spi@39b110000 { + compatible = "apple,t6020-spi", "apple,t8103-spi"; + reg = <0x3 0x9b110000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkref>; + pinctrl-0 = <&spi4_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi4>; + status = "disabled"; + }; + + serial0: serial@39b200000 { + compatible = "apple,s5l-uart"; + reg = <0x3 0x9b200000 0x0 0x4000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = ; + /* + * TODO: figure out the clocking properly, there may + * be a third selectable clock. + */ + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; + status = "disabled"; + }; + + admac: dma-controller@39b400000 { + compatible = "apple,t6020-admac", "apple,t8103-admac"; + reg = <0x3 0x9b400000 0x0 0x34000>; + #dma-cells = <1>; + dma-channels = <16>; + interrupts-extended = <0>, + <&aic AIC_IRQ 0 1218 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>; + iommus = <&sio_dart 2>; + power-domains = <&ps_sio_adma>; + resets = <&ps_audio_p>; + }; + + mca: mca@39b600000 { + compatible = "apple,t6020-mca", "apple,t8103-mca"; + reg = <0x3 0x9b600000 0x0 0x10000>, + <0x3 0x9b500000 0x0 0x20000>; + clocks = <&nco 0>, <&nco 1>, <&nco 2>, <&nco 3>; + dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, + <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, + <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, + <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>; + dma-names = "tx0a", "rx0a", "tx0b", "rx0b", + "tx1a", "rx1a", "tx1b", "rx1b", + "tx2a", "rx2a", "tx2b", "rx2b", + "tx3a", "rx3a", "tx3b", "rx3b"; + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, + <&ps_mca2>, <&ps_mca3>; + resets = <&ps_audio_p>; + #sound-dai-cells = <1>; + }; + + gpu: gpu@406400000 { + compatible = "apple,agx-g14s"; + reg = <0x4 0x6400000 0 0x40000>, + <0x4 0x4000000 0 0x1000000>; + reg-names = "asc", "sgx"; + mboxes = <&agx_mbox>; + power-domains = <&ps_gfx>; + memory-region = <&uat_ttbs>, <&uat_pagetables>, <&uat_handoff>, + <&gpu_hw_cal_a>, <&gpu_hw_cal_b>, <&gpu_globals>; + memory-region-names = "ttbs", "pagetables", "handoff", + "hw-cal-a", "hw-cal-b", "globals"; + + apple,firmware-abi = <0 0 0>; + }; + + agx_mbox: mbox@406408000 { + compatible = "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x4 0x6408000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + }; + + pcie0: pcie@580000000 { + compatible = "apple,t6020-pcie"; + device_type = "pci"; + + reg = <0x5 0x80000000 0x0 0x1000000>, /* config */ + <0x5 0x91000000 0x0 0x4000>, /* rc */ + <0x5 0x94008000 0x0 0x4000>, /* port0 */ + <0x5 0x95008000 0x0 0x4000>, /* port1 */ + <0x5 0x96008000 0x0 0x4000>, /* port2 */ + <0x5 0x97008000 0x0 0x4000>, /* port3 */ + <0x5 0x9e00c000 0x0 0x4000>, /* phy0 */ + <0x5 0x9e010000 0x0 0x4000>, /* phy1 */ + <0x5 0x9e014000 0x0 0x4000>, /* phy2 */ + <0x5 0x9e018000 0x0 0x4000>; /* phy3 */ + reg-names = "config", "rc", + "port0", "port1", "port2", "port3", + "phy0", "phy1", "phy2", "phy3"; + + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <&aic AIC_IRQ 0 1672 IRQ_TYPE_EDGE_RISING 32>; + + iommu-map = <0x100 &pcie0_dart_0 1 1>, + <0x200 &pcie0_dart_1 1 1>, + <0x300 &pcie0_dart_2 1 1>, + <0x400 &pcie0_dart_3 1 1>; + iommu-map-mask = <0xff00>; + + bus-range = <0 4>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000>; + + power-domains = <&ps_apcie_gp_sys>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + + port00: pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 4 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port00 0 0 0 0>, + <0 0 0 2 &port00 0 0 0 1>, + <0 0 0 3 &port00 0 0 0 2>, + <0 0 0 4 &port00 0 0 0 3>; + }; + + port01: pci@1,0 { + device_type = "pci"; + reg = <0x800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 5 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port01 0 0 0 0>, + <0 0 0 2 &port01 0 0 0 1>, + <0 0 0 3 &port01 0 0 0 2>, + <0 0 0 4 &port01 0 0 0 3>; + status = "disabled"; + }; + + port02: pci@2,0 { + device_type = "pci"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 6 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port02 0 0 0 0>, + <0 0 0 2 &port02 0 0 0 1>, + <0 0 0 3 &port02 0 0 0 2>, + <0 0 0 4 &port02 0 0 0 3>; + status = "disabled"; + }; + + port03: pci@3,0 { + device_type = "pci"; + reg = <0x1800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 7 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port03 0 0 0 0>, + <0 0 0 2 &port03 0 0 0 1>, + <0 0 0 3 &port03 0 0 0 2>, + <0 0 0 4 &port03 0 0 0 3>; + status = "disabled"; + }; + }; + + pcie0_dart_0: iommu@594000000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x5 0x94000000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&ps_apcie_gp_sys>; + }; + + pcie0_dart_1: iommu@595000000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x5 0x95000000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&ps_apcie_gp_sys>; + status = "disabled"; + }; + + pcie0_dart_2: iommu@596000000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x5 0x96000000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&ps_apcie_gp_sys>; + status = "disabled"; + }; + + pcie0_dart_3: iommu@597000000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x5 0x97000000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&ps_apcie_gp_sys>; + status = "disabled"; + }; diff --git a/arch/arm64/boot/dts/apple/t602x-dieX.dtsi b/arch/arm64/boot/dts/apple/t602x-dieX.dtsi new file mode 100644 index 000000000000..cb07fd82b32e --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-dieX.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Nodes present on both dies of T6022 (M2 Ultra) and present on M2 Pro/Max. + * + * Copyright The Asahi Linux Contributors + */ + + DIE_NODE(cpufreq_e): cpufreq@210e20000 { + compatible = "apple,t6020-cluster-cpufreq", "apple,t8112-cluster-cpufreq"; + reg = <0x2 0x10e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + DIE_NODE(cpufreq_p0): cpufreq@211e20000 { + compatible = "apple,t6020-cluster-cpufreq", "apple,t8112-cluster-cpufreq"; + reg = <0x2 0x11e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + DIE_NODE(cpufreq_p1): cpufreq@212e20000 { + compatible = "apple,t6020-cluster-cpufreq", "apple,t8112-cluster-cpufreq"; + reg = <0x2 0x12e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + DIE_NODE(pmgr): power-management@28e080000 { + compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x8e080000 0 0x8000>; + }; + + DIE_NODE(pmgr_south): power-management@28e680000 { + compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x8e680000 0 0x8000>; + }; + + DIE_NODE(pmgr_east): power-management@290280000 { + compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x90280000 0 0xc000>; + }; + + DIE_NODE(pinctrl_nub): pinctrl@29e1f0000 { + compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl"; + reg = <0x2 0x9e1f0000 0x0 0x4000>; + power-domains = <&DIE_NODE(ps_nub_gpio)>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&DIE_NODE(pinctrl_nub) 0 0 30>; + apple,npins = <30>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + DIE_NODE(pmgr_mini): power-management@29e280000 { + compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x9e280000 0 0x4000>; + }; + + DIE_NODE(pinctrl_aop): pinctrl@2a6820000 { + compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl"; + reg = <0x2 0xa6820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&DIE_NODE(pinctrl_aop) 0 0 72>; + apple,npins = <72>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + DIE_NODE(pinctrl_ap): pinctrl@39b028000 { + compatible = "apple,t6020-pinctrl", "apple,t8103-pinctrl"; + reg = <0x3 0x9b028000 0x0 0x4000>; + + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + + clocks = <&clkref>; + power-domains = <&DIE_NODE(ps_gpio)>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&DIE_NODE(pinctrl_ap) 0 0 255>; + apple,npins = <255>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + DIE_NODE(pmgr_gfx): power-management@404e80000 { + compatible = "apple,t6020-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x4 0x4e80000 0 0x4000>; + }; diff --git a/arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi b/arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi new file mode 100644 index 000000000000..e41b6475f792 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-gpio-pins.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * GPIO pin mappings for Apple T602x SoCs. + * + * Copyright The Asahi Linux Contributors + */ + +&pinctrl_ap { + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux = , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux = , + ; + }; + + i2c4_pins: i2c4-pins { + pinmux = , + ; + }; + + i2c5_pins: i2c5-pins { + pinmux = , + ; + }; + + i2c6_pins: i2c6-pins { + pinmux = , + ; + }; + + i2c7_pins: i2c7-pins { + pinmux = , + ; + }; + + i2c8_pins: i2c8-pins { + pinmux = , + ; + }; + + spi1_pins: spi1-pins { + pinmux = , /* SDI */ + , /* SDO */ + , /* SCK */ + ; /* CS */ + }; + + spi2_pins: spi2-pins { + pinmux = , /* SDI */ + , /* SDO */ + , /* SCK */ + ; /* CS */ + }; + + spi4_pins: spi4-pins { + pinmux = , /* SDI */ + , /* SDO */ + , /* SCK */ + ; /* CS */ + }; + + pcie_pins: pcie-pins { + pinmux = , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t602x-nvme.dtsi b/arch/arm64/boot/dts/apple/t602x-nvme.dtsi new file mode 100644 index 000000000000..590cec8ac804 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-nvme.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * NVMe related devices for Apple T602x SoCs. + * + * Copyright The Asahi Linux Contributors + */ + + DIE_NODE(ans_mbox): mbox@347408000 { + compatible = "apple,t6020-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x3 0x47408000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + power-domains = <&DIE_NODE(ps_ans2)>; + #mbox-cells = <0>; + }; + + DIE_NODE(sart): sart@34bc50000 { + compatible = "apple,t6020-sart", "apple,t6000-sart"; + reg = <0x3 0x4bc50000 0x0 0x10000>; + power-domains = <&DIE_NODE(ps_ans2)>; + }; + + DIE_NODE(nvme): nvme@34bcc0000 { + compatible = "apple,t6020-nvme-ans2", "apple,t8103-nvme-ans2"; + reg = <0x3 0x4bcc0000 0x0 0x40000>, <0x3 0x47400000 0x0 0x4000>; + reg-names = "nvme", "ans"; + interrupt-parent = <&aic>; + /* The NVME interrupt is always routed to die 0 */ + interrupts = ; + mboxes = <&DIE_NODE(ans_mbox)>; + apple,sart = <&DIE_NODE(sart)>; + power-domains = <&DIE_NODE(ps_ans2)>, + <&DIE_NODE(ps_apcie_st_sys)>, + <&DIE_NODE(ps_apcie_st1_sys)>; + power-domain-names = "ans", "apcie0", "apcie1"; + resets = <&DIE_NODE(ps_ans2)>; + }; diff --git a/arch/arm64/boot/dts/apple/t602x-pmgr.dtsi b/arch/arm64/boot/dts/apple/t602x-pmgr.dtsi new file mode 100644 index 000000000000..f5382a2faf0b --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-pmgr.dtsi @@ -0,0 +1,2265 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for Apple T602x "M2 Pro/Max/Ultra" SoC + * + * Copyright The Asahi Linux Contributors + */ + +&DIE_NODE(pmgr) { + DIE_NODE(ps_afi): power-controller@100 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afi); + apple,always-on; /* Apple Fabric, CPU interface is here */ + }; + + DIE_NODE(ps_aic): power-controller@108 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(aic); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_dwi): power-controller@110 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dwi); + }; + + DIE_NODE(ps_pms): power-controller@118 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_gpio): power-controller@120 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(gpio); + power-domains = <&DIE_NODE(ps_sio)>, <&DIE_NODE(ps_pms)>; + }; + + DIE_NODE(ps_soc_dpe): power-controller@128 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(soc_dpe); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_pms_c1ppt): power-controller@130 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms_c1ppt); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_pmgr_soc_ocla): power-controller@138 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pmgr_soc_ocla); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_amcc0): power-controller@168 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc0); + apple,always-on; /* Memory controller */ + }; + + DIE_NODE(ps_amcc2): power-controller@170 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc2); + apple,always-on; /* Memory controller */ + }; + + DIE_NODE(ps_dcs_00): power-controller@178 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_00); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_01): power-controller@180 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_01); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_02): power-controller@188 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_02); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_03): power-controller@190 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_03); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_08): power-controller@198 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_08); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_09): power-controller@1a0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_09); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_10): power-controller@1a8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_10); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_11): power-controller@1b0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_11); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_afnc1_ioa): power-controller@1b8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_ioa); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afc): power-controller@1d0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afc); + apple,always-on; /* Apple Fabric, CPU interface is here */ + }; + + DIE_NODE(ps_afnc0_ioa): power-controller@1e8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc0_ioa); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc1_ls): power-controller@1f0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_ls); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc1_ioa)>; + }; + + DIE_NODE(ps_afnc0_ls): power-controller@1f8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc0_ls); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc0_ioa)>; + }; + + DIE_NODE(ps_afnc1_lw0): power-controller@200 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_lw0); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc1_ls)>; + }; + + DIE_NODE(ps_afnc1_lw1): power-controller@208 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_lw1); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc1_ls)>; + }; + + DIE_NODE(ps_afnc1_lw2): power-controller@210 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_lw2); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc1_ls)>; + }; + + DIE_NODE(ps_afnc0_lw0): power-controller@218 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc0_lw0); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc0_ls)>; + }; + + DIE_NODE(ps_scodec): power-controller@220 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(scodec); + power-domains = <&DIE_NODE(ps_afnc1_lw0)>; + }; + + DIE_NODE(ps_atc0_common): power-controller@228 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_common); + power-domains = <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_atc1_common): power-controller@230 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_common); + power-domains = <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_atc2_common): power-controller@238 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_common); + power-domains = <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_atc3_common): power-controller@240 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_common); + power-domains = <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_dispext1_sys): power-controller@248 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext1_sys); + power-domains = <&DIE_NODE(ps_afnc1_lw2)>; + }; + + DIE_NODE(ps_pms_bridge): power-controller@250 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms_bridge); + apple,always-on; /* Core device */ + power-domains = <&DIE_NODE(ps_afnc0_lw0)>; + }; + + DIE_NODE(ps_dispext0_sys): power-controller@258 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext0_sys); + power-domains = <&DIE_NODE(ps_afnc0_lw0)>, <&DIE_NODE(ps_afr)>; + }; + + DIE_NODE(ps_ane_sys): power-controller@260 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_sys); + power-domains = <&DIE_NODE(ps_afnc0_lw0)>; + }; + + DIE_NODE(ps_avd_sys): power-controller@268 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(avd_sys); + power-domains = <&DIE_NODE(ps_afnc0_lw0)>; + }; + + DIE_NODE(ps_atc0_cio): power-controller@270 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_cio); + power-domains = <&DIE_NODE(ps_atc0_common)>; + }; + + DIE_NODE(ps_atc0_pcie): power-controller@278 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_pcie); + power-domains = <&DIE_NODE(ps_atc0_common)>; + }; + + DIE_NODE(ps_atc1_cio): power-controller@280 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_cio); + power-domains = <&DIE_NODE(ps_atc1_common)>; + }; + + DIE_NODE(ps_atc1_pcie): power-controller@288 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_pcie); + power-domains = <&DIE_NODE(ps_atc1_common)>; + }; + + DIE_NODE(ps_atc2_cio): power-controller@290 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_cio); + power-domains = <&DIE_NODE(ps_atc2_common)>; + }; + + DIE_NODE(ps_atc2_pcie): power-controller@298 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_pcie); + power-domains = <&DIE_NODE(ps_atc2_common)>; + }; + + DIE_NODE(ps_atc3_cio): power-controller@2a0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_cio); + power-domains = <&DIE_NODE(ps_atc3_common)>; + }; + + DIE_NODE(ps_atc3_pcie): power-controller@2a8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_pcie); + power-domains = <&DIE_NODE(ps_atc3_common)>; + }; + + DIE_NODE(ps_dispext1_fe): power-controller@2b0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext1_fe); + power-domains = <&DIE_NODE(ps_dispext1_sys)>; + }; + + DIE_NODE(ps_dispext1_cpu0): power-controller@2b8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext1_cpu0); + power-domains = <&DIE_NODE(ps_dispext1_fe)>; + apple,min-state = <4>; + }; + + DIE_NODE(ps_dispext0_fe): power-controller@2c0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext0_fe); + power-domains = <&DIE_NODE(ps_dispext0_sys)>; + }; + + DIE_NODE(ps_pmp): power-controller@2c8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pmp); + }; + + DIE_NODE(ps_pms_sram): power-controller@2d0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms_sram); + }; + + DIE_NODE(ps_dispext0_cpu0): power-controller@2d8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext0_cpu0); + power-domains = <&DIE_NODE(ps_dispext0_fe)>; + apple,min-state = <4>; + }; + + DIE_NODE(ps_ane_cpu): power-controller@2e0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_cpu); + power-domains = <&DIE_NODE(ps_ane_sys)>; + }; + + DIE_NODE(ps_atc0_cio_pcie): power-controller@2e8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_cio_pcie); + power-domains = <&DIE_NODE(ps_atc0_cio)>; + }; + + DIE_NODE(ps_atc0_cio_usb): power-controller@2f0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_cio_usb); + power-domains = <&DIE_NODE(ps_atc0_cio)>; + }; + + DIE_NODE(ps_atc1_cio_pcie): power-controller@2f8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_cio_pcie); + power-domains = <&DIE_NODE(ps_atc1_cio)>; + }; + + DIE_NODE(ps_atc1_cio_usb): power-controller@300 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_cio_usb); + power-domains = <&DIE_NODE(ps_atc1_cio)>; + }; + + DIE_NODE(ps_atc2_cio_pcie): power-controller@308 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_cio_pcie); + power-domains = <&DIE_NODE(ps_atc2_cio)>; + }; + + DIE_NODE(ps_atc2_cio_usb): power-controller@310 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_cio_usb); + power-domains = <&DIE_NODE(ps_atc2_cio)>; + }; + + DIE_NODE(ps_atc3_cio_pcie): power-controller@318 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_cio_pcie); + power-domains = <&DIE_NODE(ps_atc3_cio)>; + }; + + DIE_NODE(ps_atc3_cio_usb): power-controller@320 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_cio_usb); + power-domains = <&DIE_NODE(ps_atc3_cio)>; + }; + + DIE_NODE(ps_trace_fab): power-controller@390 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x390 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(trace_fab); + }; + + DIE_NODE(ps_ane_sys_mpm): power-controller@4000 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_sys_mpm); + power-domains = <&DIE_NODE(ps_ane_sys)>; + }; + + DIE_NODE(ps_ane_td): power-controller@4008 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_td); + power-domains = <&DIE_NODE(ps_ane_sys)>; + }; + + DIE_NODE(ps_ane_base): power-controller@4010 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_base); + power-domains = <&DIE_NODE(ps_ane_td)>; + }; + + DIE_NODE(ps_ane_set1): power-controller@4018 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_set1); + power-domains = <&DIE_NODE(ps_ane_base)>; + }; + + DIE_NODE(ps_ane_set2): power-controller@4020 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_set2); + power-domains = <&DIE_NODE(ps_ane_set1)>; + }; + + DIE_NODE(ps_ane_set3): power-controller@4028 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_set3); + power-domains = <&DIE_NODE(ps_ane_set2)>; + }; + + DIE_NODE(ps_ane_set4): power-controller@4030 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4030 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_set4); + power-domains = <&DIE_NODE(ps_ane_set3)>; + }; +}; + +&DIE_NODE(pmgr_south) { + DIE_NODE(ps_amcc4): power-controller@100 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc4); + apple,always-on; + }; + + DIE_NODE(ps_amcc5): power-controller@108 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc5); + apple,always-on; + }; + + DIE_NODE(ps_amcc6): power-controller@110 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc6); + apple,always-on; + }; + + DIE_NODE(ps_amcc7): power-controller@118 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc7); + apple,always-on; + }; + + DIE_NODE(ps_dcs_16): power-controller@120 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_16); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_17): power-controller@128 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_17); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_18): power-controller@130 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_18); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_19): power-controller@138 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_19); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_20): power-controller@140 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_20); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_21): power-controller@148 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_21); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_22): power-controller@150 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_22); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_23): power-controller@158 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_23); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_24): power-controller@160 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_24); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_25): power-controller@168 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_25); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_26): power-controller@170 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_26); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_27): power-controller@178 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_27); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_28): power-controller@180 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_28); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_29): power-controller@188 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_29); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_30): power-controller@190 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_30); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_31): power-controller@198 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_31); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_afnc4_ioa): power-controller@1a0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc4_ioa); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc4_ls): power-controller@1a8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc4_ls); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc4_ioa)>; + }; + + DIE_NODE(ps_afnc4_lw0): power-controller@1b0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc4_lw0); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc4_ls)>; + }; + + DIE_NODE(ps_afnc5_ioa): power-controller@1b8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc5_ioa); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc5_ls): power-controller@1c0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc5_ls); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc5_ioa)>; + }; + + DIE_NODE(ps_afnc5_lw0): power-controller@1c8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc5_lw0); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc5_ls)>; + }; + + DIE_NODE(ps_dispext2_sys): power-controller@1d0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext2_sys); + }; + + DIE_NODE(ps_msr1): power-controller@1d8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr1); + }; + + DIE_NODE(ps_dispext2_fe): power-controller@1e0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext2_fe); + power-domains = <&DIE_NODE(ps_dispext2_sys)>; + }; + + DIE_NODE(ps_dispext2_cpu0): power-controller@1e8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext2_cpu0); + power-domains = <&DIE_NODE(ps_dispext2_fe)>; + apple,min-state = <4>; + }; + + DIE_NODE(ps_msr1_ase_core): power-controller@1f0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr1_ase_core); + power-domains = <&DIE_NODE(ps_msr1)>; + }; + + DIE_NODE(ps_dispext3_sys): power-controller@220 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext3_sys); + }; + + DIE_NODE(ps_venc1_sys): power-controller@228 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_sys); + }; + + DIE_NODE(ps_dispext3_fe): power-controller@230 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext3_fe); + power-domains = <&DIE_NODE(ps_dispext3_sys)>; + }; + + DIE_NODE(ps_dispext3_cpu0): power-controller@238 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext3_cpu0); + power-domains = <&DIE_NODE(ps_dispext3_fe)>; + apple,min-state = <4>; + }; + + DIE_NODE(ps_venc1_dma): power-controller@4000 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_dma); + power-domains = <&DIE_NODE(ps_venc1_sys)>; + }; + + DIE_NODE(ps_venc1_pipe4): power-controller@4008 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_pipe4); + power-domains = <&DIE_NODE(ps_venc1_dma)>; + }; + + DIE_NODE(ps_venc1_pipe5): power-controller@4010 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_pipe5); + power-domains = <&DIE_NODE(ps_venc1_dma)>; + }; + + DIE_NODE(ps_venc1_me0): power-controller@4018 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_me0); + power-domains = <&DIE_NODE(ps_venc1_pipe5)>, <&DIE_NODE(ps_venc1_pipe4)>; + }; + + DIE_NODE(ps_venc1_me1): power-controller@4020 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_me1); + power-domains = <&DIE_NODE(ps_venc1_me0)>; + }; +}; + +&DIE_NODE(pmgr_east) { + DIE_NODE(ps_clvr_spmi0): power-controller@100 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(clvr_spmi0); + apple,always-on; /* PCPU voltage regulator interface (used by SMC) */ + }; + + DIE_NODE(ps_clvr_spmi1): power-controller@108 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(clvr_spmi1); + apple,always-on; /* GPU voltage regulator interface (used by SMC) */ + }; + + DIE_NODE(ps_clvr_spmi2): power-controller@110 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(clvr_spmi2); + apple,always-on; /* ANE, fabric, AFR voltage regulator interface (used by SMC) */ + }; + + DIE_NODE(ps_clvr_spmi3): power-controller@118 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(clvr_spmi3); + apple,always-on; /* Additional voltage regulator, probably used on T6021 (SMC) */ + }; + + DIE_NODE(ps_clvr_spmi4): power-controller@120 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(clvr_spmi4); + apple,always-on; /* Additional voltage regulator, probably used on T6021 (SMC) */ + }; + + DIE_NODE(ps_ispsens0): power-controller@128 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ispsens0); + }; + + DIE_NODE(ps_ispsens1): power-controller@130 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ispsens1); + }; + + DIE_NODE(ps_ispsens2): power-controller@138 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ispsens2); + }; + + DIE_NODE(ps_ispsens3): power-controller@140 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ispsens3); + }; + + DIE_NODE(ps_afnc6_ioa): power-controller@148 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc6_ioa); + apple,always-on; + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc6_ls): power-controller@150 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc6_ls); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc6_ioa)>; + }; + + DIE_NODE(ps_afnc6_lw0): power-controller@158 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc6_lw0); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc6_ls)>; + }; + + DIE_NODE(ps_afnc2_ioa): power-controller@160 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_ioa); + apple,always-on; + power-domains = <&DIE_NODE(ps_dcs_10)>; + }; + + DIE_NODE(ps_afnc2_ls): power-controller@168 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_ls); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc2_ioa)>; + }; + + DIE_NODE(ps_afnc2_lw0): power-controller@170 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_lw0); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc2_ls)>; + }; + + DIE_NODE(ps_afnc2_lw1): power-controller@178 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_lw1); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc2_ls)>; + }; + + DIE_NODE(ps_afnc3_ioa): power-controller@180 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc3_ioa); + apple,always-on; + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc3_ls): power-controller@188 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc3_ls); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc3_ioa)>; + }; + + DIE_NODE(ps_afnc3_lw0): power-controller@190 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc3_lw0); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc3_ls)>; + }; + + DIE_NODE(ps_apcie_gp): power-controller@198 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_gp); + power-domains = <&DIE_NODE(ps_afnc6_lw0)>; + }; + + DIE_NODE(ps_apcie_st): power-controller@1a0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_st); + power-domains = <&DIE_NODE(ps_afnc6_lw0)>; + }; + + DIE_NODE(ps_ans2): power-controller@1a8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ans2); + power-domains = <&DIE_NODE(ps_afnc6_lw0)>; + }; + + DIE_NODE(ps_disp0_sys): power-controller@1b0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(disp0_sys); + power-domains = <&DIE_NODE(ps_afnc2_lw0)>; + }; + + DIE_NODE(ps_jpg): power-controller@1b8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(jpg); + power-domains = <&DIE_NODE(ps_afnc2_lw0)>; + }; + + DIE_NODE(ps_sio): power-controller@1c0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio); + power-domains = <&DIE_NODE(ps_afnc2_lw1)>; + }; + + DIE_NODE(ps_isp_sys): power-controller@1c8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_sys); + power-domains = <&DIE_NODE(ps_afnc2_lw1)>; + status = "disabled"; + }; + + DIE_NODE(ps_disp0_fe): power-controller@1d0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(disp0_fe); + power-domains = <&DIE_NODE(ps_disp0_sys)>; + }; + + DIE_NODE(ps_disp0_cpu0): power-controller@1d8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(disp0_cpu0); + power-domains = <&DIE_NODE(ps_disp0_fe)>; + apple,min-state = <4>; + }; + + DIE_NODE(ps_sio_cpu): power-controller@1e0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_cpu); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_fpwm0): power-controller@1e8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(fpwm0); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_fpwm1): power-controller@1f0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(fpwm1); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_fpwm2): power-controller@1f8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(fpwm2); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c0): power-controller@200 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c0); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c1): power-controller@208 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c1); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c2): power-controller@210 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c2); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c3): power-controller@218 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c3); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c4): power-controller@220 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c4); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c5): power-controller@228 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c5); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c6): power-controller@230 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c6); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c7): power-controller@238 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c7); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c8): power-controller@240 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c8); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_spi_p): power-controller@248 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi_p); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_sio_spmi0): power-controller@250 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_spmi0); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_sio_spmi1): power-controller@258 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_spmi1); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_sio_spmi2): power-controller@260 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_spmi2); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_uart_p): power-controller@268 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart_p); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_audio_p): power-controller@270 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(audio_p); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_sio_adma): power-controller@278 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_adma); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_aes): power-controller@280 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(aes); + apple,always-on; + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_dptx_phy_ps): power-controller@288 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dptx_phy_ps); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_spi0): power-controller@2d8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi0); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi1): power-controller@2e0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi1); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi2): power-controller@2e8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi2); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi3): power-controller@2f0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi3); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi4): power-controller@2f8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi4); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi5): power-controller@300 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi5); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_uart_n): power-controller@308 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart_n); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart0): power-controller@310 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart0); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_amcc1): power-controller@318 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc1); + apple,always-on; + }; + + DIE_NODE(ps_amcc3): power-controller@320 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc3); + apple,always-on; + }; + + DIE_NODE(ps_dcs_04): power-controller@328 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_04); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_05): power-controller@330 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_05); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_06): power-controller@338 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_06); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_07): power-controller@340 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_07); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_12): power-controller@348 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x348 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_12); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_13): power-controller@350 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x350 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_13); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_14): power-controller@358 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x358 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_14); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_15): power-controller@360 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x360 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_15); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_uart1): power-controller@368 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x368 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart1); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart2): power-controller@370 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x370 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart2); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart3): power-controller@378 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x378 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart3); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart4): power-controller@380 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x380 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart4); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart5): power-controller@388 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x388 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart5); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart6): power-controller@390 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x390 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart6); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_mca0): power-controller@398 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x398 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca0); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_mca1): power-controller@3a0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca1); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_mca2): power-controller@3a8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca2); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_mca3): power-controller@3b0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca3); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_dpa0): power-controller@3b8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa0); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa1): power-controller@3c0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa1); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa2): power-controller@3c8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa2); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa3): power-controller@3d0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa3); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_msr0): power-controller@3d8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr0); + }; + + DIE_NODE(ps_venc_sys): power-controller@3e0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_sys); + }; + + DIE_NODE(ps_dpa4): power-controller@3e8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa4); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_msr0_ase_core): power-controller@3f0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr0_ase_core); + power-domains = <&DIE_NODE(ps_msr0)>; + }; + + DIE_NODE(ps_apcie_gpshr_sys): power-controller@3f8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_gpshr_sys); + power-domains = <&DIE_NODE(ps_apcie_gp)>; + }; + + DIE_NODE(ps_apcie_st_sys): power-controller@408 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x408 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_st_sys); + power-domains = <&DIE_NODE(ps_apcie_st)>, <&DIE_NODE(ps_ans2)>; + }; + + DIE_NODE(ps_apcie_st1_sys): power-controller@410 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x410 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_st1_sys); + power-domains = <&DIE_NODE(ps_apcie_st_sys)>; + }; + + DIE_NODE(ps_apcie_gp_sys): power-controller@418 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x418 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_gp_sys); + power-domains = <&DIE_NODE(ps_apcie_gpshr_sys)>; + apple,always-on; /* Breaks things if shut down */ + }; + + DIE_NODE(ps_apcie_ge_sys): power-controller@420 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x420 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_ge_sys); + power-domains = <&DIE_NODE(ps_apcie_gpshr_sys)>; + }; + + DIE_NODE(ps_apcie_phy_sw): power-controller@428 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x428 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_phy_sw); + apple,always-on; /* macOS does not turn this off */ + }; + + DIE_NODE(ps_sep): power-controller@c00 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc00 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sep); + apple,always-on; /* Locked on */ + }; + + /* There is a dependency tree involved with these PDs, + * but we do not express it here since the ISP driver + * is supposed to sequence them in the right order anyway. + * + * This also works around spurious parent PD activation + * on machines with ISP disabled (desktops), so we don't + * have to enable/disable everything in the per-model DTs. + */ + DIE_NODE(ps_isp_cpu): power-controller@4000 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_cpu); + /* power-domains = <&DIE_NODE(ps_isp_sys)>; */ + }; + + DIE_NODE(ps_isp_fe): power-controller@4008 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_fe); + /* power-domains = <&DIE_NODE(ps_isp_sys)>; */ + }; + + DIE_NODE(ps_dprx): power-controller@4010 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dprx); + /* power-domains = <&DIE_NODE(ps_isp_sys)>; */ + }; + + DIE_NODE(ps_isp_vis): power-controller@4018 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_vis); + /* power-domains = <&DIE_NODE(ps_isp_fe)>; */ + }; + + DIE_NODE(ps_isp_be): power-controller@4020 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_be); + /* power-domains = <&DIE_NODE(ps_isp_fe)>; */ + }; + + DIE_NODE(ps_isp_raw): power-controller@4028 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_raw); + /* power-domains = <&DIE_NODE(ps_isp_fe)>; */ + }; + + DIE_NODE(ps_isp_clr): power-controller@4030 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4030 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_clr); + /* power-domains = <&DIE_NODE(ps_isp_be)>; */ + }; + + DIE_NODE(ps_venc_dma): power-controller@8000 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_dma); + power-domains = <&DIE_NODE(ps_venc_sys)>; + }; + + DIE_NODE(ps_venc_pipe4): power-controller@8008 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_pipe4); + power-domains = <&DIE_NODE(ps_venc_dma)>; + }; + + DIE_NODE(ps_venc_pipe5): power-controller@8010 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_pipe5); + power-domains = <&DIE_NODE(ps_venc_dma)>; + }; + + DIE_NODE(ps_venc_me0): power-controller@8018 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_me0); + power-domains = <&DIE_NODE(ps_venc_pipe5)>, <&DIE_NODE(ps_venc_pipe4)>; + }; + + DIE_NODE(ps_venc_me1): power-controller@8020 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_me1); + power-domains = <&DIE_NODE(ps_venc_me0)>; + }; + + DIE_NODE(ps_prores): power-controller@c000 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(prores); + power-domains = <&DIE_NODE(ps_afnc3_lw0)>; + }; +}; + +&DIE_NODE(pmgr_mini) { + DIE_NODE(ps_debug): power-controller@58 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x58 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(debug); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_spmi0): power-controller@60 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x60 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi0); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_spmi1): power-controller@68 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x68 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi1); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_aon): power-controller@70 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x70 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_aon); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_msg): power-controller@78 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x78 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msg); + apple,always-on; /* Core AON device? */ + }; + + DIE_NODE(ps_nub_gpio): power-controller@80 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x80 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_gpio); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_fabric): power-controller@88 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x88 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_fabric); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_atc0_usb_aon): power-controller@90 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x90 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_atc1_usb_aon): power-controller@98 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x98 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_atc2_usb_aon): power-controller@a0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xa0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_atc3_usb_aon): power-controller@a8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xa8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_mtp_fabric): power-controller@b0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xb0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_fabric); + apple,always-on; + power-domains = <&DIE_NODE(ps_nub_fabric)>; + status = "disabled"; + }; + + DIE_NODE(ps_nub_sram): power-controller@b8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xb8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_sram); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_debug_switch): power-controller@c0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(debug_switch); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_atc0_usb): power-controller@c8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_usb); + power-domains = <&DIE_NODE(ps_atc0_common)>; + }; + + DIE_NODE(ps_atc1_usb): power-controller@d0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xd0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_usb); + power-domains = <&DIE_NODE(ps_atc1_common)>; + }; + + DIE_NODE(ps_atc2_usb): power-controller@d8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xd8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_usb); + power-domains = <&DIE_NODE(ps_atc2_common)>; + }; + + DIE_NODE(ps_atc3_usb): power-controller@e0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xe0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_usb); + power-domains = <&DIE_NODE(ps_atc3_common)>; + }; + +#if 0 + /* MTP stuff is self-managed */ + DIE_NODE(ps_mtp_gpio): power-controller@e8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xe8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_gpio); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_base): power-controller@f0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xf0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_base); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_periph): power-controller@f8 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xf8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_periph); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_spi0): power-controller@100 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_spi0); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_i2cm0): power-controller@108 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_i2cm0); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_uart0): power-controller@110 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_uart0); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_cpu): power-controller@118 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_cpu); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_scm_fabric): power-controller@120 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_scm_fabric); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_periph)>; + }; + + DIE_NODE(ps_mtp_sram): power-controller@128 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_sram); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_scm_fabric)>, <&DIE_NODE(ps_mtp_cpu)>; + }; + + DIE_NODE(ps_mtp_dma): power-controller@130 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_dma); + apple,always-on; /* MTP always stays on */ + power-domains = <&DIE_NODE(ps_mtp_sram)>; + }; +#endif +}; + +&DIE_NODE(pmgr_gfx) { + DIE_NODE(ps_gpx): power-controller@0 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(gpx); + apple,min-state = <4>; + apple,always-on; + }; + + DIE_NODE(ps_afr): power-controller@100 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afr); + /* Apple Fabric, media stuff: this can power down */ + apple,min-state = <4>; + }; + + DIE_NODE(ps_gfx): power-controller@108 { + compatible = "apple,t6020-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(gfx); + power-domains = <&DIE_NODE(ps_afr)>, <&DIE_NODE(ps_gpx)>; + }; +}; From 44a952585b4b530099f60fa076e35f29619f3e78 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Sun, 14 Sep 2025 21:38:47 +0200 Subject: [PATCH 913/931] arm64: dts: apple: Add J414 and J416 Macbook Pro device trees Add device trees for the T6020 and T6021 based Macbook Pros (M2 Pro/Max, 14/16-inch). The devices are very similar to the T6000/T6001 based ones so reuse the device templates, include the new SoCs and correct for the minimal differences. Signed-off-by: Hector Martin Reviewed-by: Neal Gompa Co-developed-by: Janne Grunau Signed-off-by: Janne Grunau Reviewed-by: Sven Peter Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/Makefile | 4 ++ arch/arm64/boot/dts/apple/t6020-j414s.dts | 26 +++++++++++ arch/arm64/boot/dts/apple/t6020-j416s.dts | 26 +++++++++++ arch/arm64/boot/dts/apple/t6021-j414c.dts | 26 +++++++++++ arch/arm64/boot/dts/apple/t6021-j416c.dts | 26 +++++++++++ .../arm64/boot/dts/apple/t602x-j414-j416.dtsi | 45 +++++++++++++++++++ 6 files changed, 153 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t6020-j414s.dts create mode 100644 arch/arm64/boot/dts/apple/t6020-j416s.dts create mode 100644 arch/arm64/boot/dts/apple/t6021-j414c.dts create mode 100644 arch/arm64/boot/dts/apple/t6021-j416c.dts create mode 100644 arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index df4ba8ef6213..e97a6676387c 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -79,6 +79,10 @@ dtb-$(CONFIG_ARCH_APPLE) += t6000-j316s.dtb dtb-$(CONFIG_ARCH_APPLE) += t6001-j316c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6001-j375c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6002-j375d.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6020-j414s.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6021-j414c.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6020-j416s.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6021-j416c.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j413.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j415.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j473.dtb diff --git a/arch/arm64/boot/dts/apple/t6020-j414s.dts b/arch/arm64/boot/dts/apple/t6020-j414s.dts new file mode 100644 index 000000000000..631c54c5f03d --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6020-j414s.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14-inch, M2 Pro, 2023) + * + * target-type: J414s + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6020.dtsi" +#include "t602x-j414-j416.dtsi" + +/ { + compatible = "apple,j414s", "apple,t6020", "apple,arm-platform"; + model = "Apple MacBook Pro (14-inch, M2 Pro, 2023)"; +}; + +&wifi0 { + brcm,board-type = "apple,tokara"; +}; + +&bluetooth0 { + brcm,board-type = "apple,tokara"; +}; diff --git a/arch/arm64/boot/dts/apple/t6020-j416s.dts b/arch/arm64/boot/dts/apple/t6020-j416s.dts new file mode 100644 index 000000000000..c277ed5889a2 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6020-j416s.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (16-inch, M2 Pro, 2023) + * + * target-type: J416s + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6020.dtsi" +#include "t602x-j414-j416.dtsi" + +/ { + compatible = "apple,j416s", "apple,t6020", "apple,arm-platform"; + model = "Apple MacBook Pro (16-inch, M2 Pro, 2023)"; +}; + +&wifi0 { + brcm,board-type = "apple,amami"; +}; + +&bluetooth0 { + brcm,board-type = "apple,amami"; +}; diff --git a/arch/arm64/boot/dts/apple/t6021-j414c.dts b/arch/arm64/boot/dts/apple/t6021-j414c.dts new file mode 100644 index 000000000000..cdcf0740714d --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6021-j414c.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14-inch, M2 Max, 2023) + * + * target-type: J414c + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6021.dtsi" +#include "t602x-j414-j416.dtsi" + +/ { + compatible = "apple,j414c", "apple,t6021", "apple,arm-platform"; + model = "Apple MacBook Pro (14-inch, M2 Max, 2023)"; +}; + +&wifi0 { + brcm,board-type = "apple,tokara"; +}; + +&bluetooth0 { + brcm,board-type = "apple,tokara"; +}; diff --git a/arch/arm64/boot/dts/apple/t6021-j416c.dts b/arch/arm64/boot/dts/apple/t6021-j416c.dts new file mode 100644 index 000000000000..6d8146b94170 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6021-j416c.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (16-inch, M2 Max, 2022) + * + * target-type: J416c + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6021.dtsi" +#include "t602x-j414-j416.dtsi" + +/ { + compatible = "apple,j416c", "apple,t6021", "apple,arm-platform"; + model = "Apple MacBook Pro (16-inch, M2 Max, 2023)"; +}; + +&wifi0 { + brcm,board-type = "apple,amami"; +}; + +&bluetooth0 { + brcm,board-type = "apple,amami"; +}; diff --git a/arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi b/arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi new file mode 100644 index 000000000000..0e806d8ddf81 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-j414-j416.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14/16-inch, 2022) + * + * This file contains the parts common to J414 and J416 devices with both t6020 and t6021. + * + * target-type: J414s / J414c / J416s / J416c + * + * Copyright The Asahi Linux Contributors + */ + +/* + * These models are essentially identical to the previous generation, other than + * the GPIO indices. + */ + +#include "t600x-j314-j316.dtsi" + +&framebuffer0 { + power-domains = <&ps_disp0_cpu0>, <&ps_dptx_phy_ps>; +}; + +&hpm0 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; + +&hpm1 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; + +&hpm2 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; + +&hpm5 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; + +&wifi0 { + compatible = "pci14e4,4434"; +}; + +&bluetooth0 { + compatible = "pci14e4,5f72"; +}; From 9da45d978ccbe00e967093a0c0dc962c28c65734 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Sun, 14 Sep 2025 21:38:48 +0200 Subject: [PATCH 914/931] arm64: dts: apple: Add J474s, J475c and J475d device trees Add device trees for the M2 Pro Mac mini and the M2 Max and Ultra Mac Studio. These devices are very similar to the M1 Max and Ultra Mac Studio so reuse the device template, include the .dtsi for the new SoCs and correct for the minimal differences. Co-developed-by: Hector Martin Signed-off-by: Hector Martin Reviewed-by: Neal Gompa Signed-off-by: Janne Grunau Reviewed-by: Sven Peter Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/Makefile | 3 ++ arch/arm64/boot/dts/apple/t6020-j474s.dts | 47 +++++++++++++++++++ arch/arm64/boot/dts/apple/t6021-j475c.dts | 37 +++++++++++++++ arch/arm64/boot/dts/apple/t6022-j475d.dts | 42 +++++++++++++++++ arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi | 38 +++++++++++++++ .../arm64/boot/dts/apple/t602x-j474-j475.dtsi | 38 +++++++++++++++ 6 files changed, 205 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t6020-j474s.dts create mode 100644 arch/arm64/boot/dts/apple/t6021-j475c.dts create mode 100644 arch/arm64/boot/dts/apple/t6022-j475d.dts create mode 100644 arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi create mode 100644 arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index e97a6676387c..21c4e02a4429 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -83,6 +83,9 @@ dtb-$(CONFIG_ARCH_APPLE) += t6020-j414s.dtb dtb-$(CONFIG_ARCH_APPLE) += t6021-j414c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6020-j416s.dtb dtb-$(CONFIG_ARCH_APPLE) += t6021-j416c.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6020-j474s.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6021-j475c.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6022-j475d.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j413.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j415.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j473.dtb diff --git a/arch/arm64/boot/dts/apple/t6020-j474s.dts b/arch/arm64/boot/dts/apple/t6020-j474s.dts new file mode 100644 index 000000000000..7c7ad5b8ad18 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6020-j474s.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac mini (M2 Pro, 2023) + * + * target-type: J474s + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6020.dtsi" + +/* + * This model is very similar to M1 and M2 Mac Studio models so base it on those + * and remove the missing SDHCI controller. + */ + +#include "t602x-j474-j475.dtsi" + +/ { + compatible = "apple,j474s", "apple,t6020", "apple,arm-platform"; + model = "Apple Mac mini (M2 Pro, 2023)"; +}; + +/* PCIe devices */ +&wifi0 { + compatible = "pci14e4,4434"; + brcm,board-type = "apple,tasmania"; +}; + +&bluetooth0 { + compatible = "pci14e4,5f72"; + brcm,board-type = "apple,tasmania"; +}; + +/* + * port01 is unused, remove the PCIe sdhci0 node from t600x-j375.dtsi and adjust + * the iommu-map. + */ +/delete-node/ &sdhci0; + +&pcie0 { + iommu-map = <0x100 &pcie0_dart_0 1 1>, + <0x200 &pcie0_dart_2 1 1>, + <0x300 &pcie0_dart_3 1 1>; +}; diff --git a/arch/arm64/boot/dts/apple/t6021-j475c.dts b/arch/arm64/boot/dts/apple/t6021-j475c.dts new file mode 100644 index 000000000000..533e35774874 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6021-j475c.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Studio (M2 Max, 2023) + * + * target-type: J475c + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6021.dtsi" +#include "t602x-j474-j475.dtsi" + +/ { + compatible = "apple,j475c", "apple,t6021", "apple,arm-platform"; + model = "Apple Mac Studio (M2 Max, 2023)"; +}; + +&wifi0 { + compatible = "pci14e4,4434"; + brcm,board-type = "apple,canary"; +}; + +&bluetooth0 { + compatible = "pci14e4,5f72"; + brcm,board-type = "apple,canary"; +}; + +/* enable PCIe port01 with SDHCI */ +&port01 { + status = "okay"; +}; + +&pcie0_dart_1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t6022-j475d.dts b/arch/arm64/boot/dts/apple/t6022-j475d.dts new file mode 100644 index 000000000000..736594544f79 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6022-j475d.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Studio (M2 Ultra, 2023) + * + * target-type: J475d + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6022.dtsi" +#include "t602x-j474-j475.dtsi" +#include "t6022-jxxxd.dtsi" + +/ { + compatible = "apple,j475d", "apple,t6022", "apple,arm-platform"; + model = "Apple Mac Studio (M2 Ultra, 2023)"; +}; + +&framebuffer0 { + power-domains = <&ps_dispext0_cpu0_die1>, <&ps_dptx_phy_ps_die1>; +}; + +/* enable PCIe port01 with SDHCI */ +&port01 { + status = "okay"; +}; + +&pcie0_dart_1 { + status = "okay"; +}; + +&wifi0 { + compatible = "pci14e4,4434"; + brcm,board-type = "apple,canary"; +}; + +&bluetooth0 { + compatible = "pci14e4,5f72"; + brcm,board-type = "apple,canary"; +}; diff --git a/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi b/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi new file mode 100644 index 000000000000..4f7bf2ebfe39 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Pro (M2 Ultra, 2023) and Mac Studio (M2 Ultra, 2023) + * + * This file contains the parts common to J180 and J475 devices with t6022. + * + * target-type: J180d / J475d + * + * Copyright The Asahi Linux Contributors + */ + +/* delete power-domains for missing disp0 / disp0_die1 */ +/delete-node/ &ps_disp0_cpu0; +/delete-node/ &ps_disp0_fe; + +/delete-node/ &ps_disp0_cpu0_die1; +/delete-node/ &ps_disp0_fe_die1; + +/* USB Type C */ +&i2c0 { + /* front-right */ + hpm4: usb-pd@39 { + compatible = "apple,cd321x"; + reg = <0x39>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + /* front-left */ + hpm5: usb-pd@3a { + compatible = "apple,cd321x"; + reg = <0x3a>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi b/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi new file mode 100644 index 000000000000..ee12fea5b12c --- /dev/null +++ b/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac mini (M2 Pro, 2023) and Mac Studio (2023) + * + * This file contains the parts common to J474 and J475 devices with t6020, + * t6021 and t6022. + * + * target-type: J474s / J475c / J475d + * + * Copyright The Asahi Linux Contributors + */ + +/* + * These models are very similar to the previous generation Mac Studio, other + * than GPIO indices. + */ + +#include "t600x-j375.dtsi" + +&framebuffer0 { + power-domains = <&ps_dispext0_cpu0>, <&ps_dptx_phy_ps>; +}; + +&hpm0 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; + +&hpm1 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; + +&hpm2 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; + +&hpm3 { + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; +}; From 3edb9c95ffa60c029074804c39b35103a9fb4bfd Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 1 Sep 2025 18:00:26 +0800 Subject: [PATCH 915/931] arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C According to Radxa E52C Schematic V1.2 [1] page 5, vcc_3v3_pmu is directly connected to vcc_3v3_s3 via a 0 ohm resistor. The vcc_3v3_pmu is not a new regulator, so remove it. [1] https://dl.radxa.com/e/e52c/hw/radxa_e52c_v1.2_schematic.pdf Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20250901100027.164594-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts b/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts index 63e5dfb77ab1..5ae09e8ecbb1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts @@ -98,16 +98,6 @@ vcc_1v1_nldo_s3: regulator-1v1 { vin-supply = <&vcc_sysin>; }; - vcc_3v3_pmu: regulator-3v3-0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; - vcc_3v3_s0: regulator-3v3-1 { compatible = "regulator-fixed"; regulator-name = "vcc_3v3_s0"; @@ -537,7 +527,7 @@ regulator-state-mem { }; }; - vcc_3v3_s3: dcdc-reg8 { + vcc_3v3_s3: vcc_3v3_pmu: dcdc-reg8 { regulator-name = "vcc_3v3_s3"; regulator-always-on; regulator-boot-on; From cf311ff5e7b27c267c05279e26546fe74f46e5da Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Mon, 1 Sep 2025 18:00:27 +0800 Subject: [PATCH 916/931] arm64: dts: rockchip: update pinctrl names for Radxa E52C Updated the pinctrl names of the user key and power LED according to the schematic. Also updated the nodenames of other pinctrls. Signed-off-by: Chukun Pan Link: https://lore.kernel.org/r/20250901100027.164594-4-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts b/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts index 5ae09e8ecbb1..5bdcaa650988 100644 --- a/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts @@ -42,7 +42,7 @@ button-0 { keys-1 { compatible = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <&btn_0>; + pinctrl-0 = <&pwm15_ir_m1>; button-1 { label = "User"; @@ -55,7 +55,7 @@ button-1 { leds-0 { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&led_0>; + pinctrl-0 = <&power_led>; led-0 { color = ; @@ -301,13 +301,13 @@ &pcie2x1l2 { &pinctrl { keys { - btn_0: button-0 { + pwm15_ir_m1: pwm15-ir-m1 { rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; leds { - led_0: led-0 { + power_led: power-led { rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -323,19 +323,19 @@ pcie20x1_2_perstn_m0: pcie-2 { }; regulators { - vcc_5v0_pwren_h: regulator-5v0-1 { + vcc_5v0_pwren_h: vcc-5v0-pwren-h { rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; rtc { - rtc_int_l: rtc-0 { + rtc_int_l: rtc-int-l { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb { - usb_otg_pwren_h: regulator-5v0-0 { + usb_otg_pwren_h: usb-otg-pwren-h { rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; From 0bb8d67611b59740f47ad57658a8d2986c43f8c1 Mon Sep 17 00:00:00 2001 From: Kaison Deng Date: Mon, 15 Sep 2025 10:22:04 +0800 Subject: [PATCH 917/931] dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT This documents Firefly ROC-RK3588-RT which is a SBC based on RK3588 SoC. Link: https://en.t-firefly.com/product/industry/rocrk3588rt Signed-off-by: Kaison Deng Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/27b2ce7950fdbf28c6c8404c3f8be3c1c35d6b3c.1757902513.git.dkx@t-chip.com.cn Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index f9ee77f17ad7..6aceaa8acbb2 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -258,6 +258,11 @@ properties: - const: firefly,roc-rk3576-pc - const: rockchip,rk3576 + - description: Firefly ROC-RK3588-RT + items: + - const: firefly,roc-rk3588-rt + - const: rockchip,rk3588 + - description: Firefly Station M2 items: - const: firefly,rk3566-roc-pc From 93781211e9ad9578787355147c2f28b7289a8ec6 Mon Sep 17 00:00:00 2001 From: Kaison Deng Date: Mon, 15 Sep 2025 10:22:05 +0800 Subject: [PATCH 918/931] arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT Link: https://en.t-firefly.com/product/industry/rocrk3588rt The Firefly ROC-RK3588-RT is RK3588 based SBC featuring: - TF card slot - SATA 2242 socket - 1x USB 3.0 Port, 1x USB 2.0 Port, 1x Typec Port - 1x HDMI 2.1 out, 1x HDMI 2.0 out - 2x Gigabit Ethernet, 1x 2.5G Ethernet - M.2 E-KEY for Extended WiFI and Bluetoolh - ES8388 on-board sound codec - jack in/out - RTC - LED: WORK, DIY Signed-off-by: Kaison Deng Reviewed-by: Andrew Lunn #gmac0, gmac1, mdio0, mdio1 nodes Link: https://lore.kernel.org/r/349c4226824efa52ceb14e3d8518c8bb5c7465fc.1757902513.git.dkx@t-chip.com.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../arm64/boot/dts/rockchip/rk3588-roc-rt.dts | 1132 +++++++++++++++++ 2 files changed, 1133 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 9d56d4146b20..ad684e3831bc 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -181,6 +181,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-max.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-ultra.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-roc-rt.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5-itx.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts b/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts new file mode 100644 index 000000000000..2d6fed2a84a3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts @@ -0,0 +1,1132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Firefly Technology Co. Ltd + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model = "Firefly ROC-RK3588-RT"; + compatible = "firefly,roc-rk3588-rt", "rockchip,rk3588"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + adc-keys-0 { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + analog-sound { + compatible = "simple-audio-card"; + pinctrl-0 = <&hp_detect>; + pinctrl-names = "default"; + simple-audio-card,aux-devs = <&_headphones>; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <384>; + simple-audio-card,name = "rockchip-es8388"; + simple-audio-card,pin-switches = "Headphones"; + simple-audio-card,routing = + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphones Amplifier INL", "LOUT1", + "Headphones Amplifier INR", "ROUT1", + "Headphones", "Headphones Amplifier OUTL", + "Headphones", "Headphones Amplifier OUTR", + "LINPUT1", "Microphone Jack", + "RINPUT1", "Microphone Jack", + "LINPUT2", "Onboard Microphone", + "RINPUT2", "Onboard Microphone"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Microphone", "Onboard Microphone", + "Headphone", "Headphones", + "Speaker", "Speaker"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&es8388>; + system-clock-frequency = <12288000>; + }; + }; + + amp_headphones: headphones-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&headphone_amplifier_en>; + sound-name-prefix = "Headphones Amplifier"; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 70 75 80 100>; + #cooling-cells = <2>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm15 0 50000 1>; + }; + + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + power_led { + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + user_led { + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; + + vbus5v0_typec: regulator-vbus5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc12v_dcin"; + }; + + vcc3v3_sata2: vcc3v3-sata2 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_sata2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sd_s0: regulator-vcc3v3-sd-s0 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_wlan: regulator-vcc3v3-wlan { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwren>; + regulator-name = "vcc3v3_wlan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host3: regulator-vcc5v0-host3 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host3_en>; + regulator-name = "vcc5v0_host3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + status = "okay"; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + /* pc9202 watchdog@3c with enable-gpio gpio0-c3 */ + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + fcs,suspend-voltage-selector = <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + fcs,suspend-voltage-selector = <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + status = "okay"; + + es8388: audio-codec@11 { + compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + AVDD-supply = <&vcc_1v8_s0>; + DVDD-supply = <&vcc_1v8_s0>; + HPVDD-supply = <&vcc_3v3_s0>; + PVDD-supply = <&vcc_1v8_s0>; + #sound-dai-cells = <0>; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + sink-pdos = + ; + source-pdos = + ; + try-power-role = "source"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_role_sw: endpoint { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + + port@2 { + reg = <2>; + + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_0_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_1_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>, <&pcie2_0_wake>, <&pcie2_0_clkreq>; + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_wlan>; + status = "okay"; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_rst>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + +&pinctrl { + audio { + hp_detect: headphone-detect { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + headphone_amplifier_en: headphone-amplifier-en { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-leds { + led_pins: led-pins { + rockchip,pins = + <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_0_wake: pcie2-0-wake { + rockchip,pins = <4 RK_PA4 4 &pcfg_pull_none>; + }; + + pcie2_0_clkreq: pcie2-0-clkreq { + rockchip,pins = <4 RK_PA3 4 &pcfg_pull_none>; + }; + + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8211f { + rtl8211f_0_rst: rtl8211f-0-rst { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + rtl8211f_1_rst: rtl8211f-1-rst { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_host3_en: vcc5v0-host3-en { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wlan { + wifi_pwren: wifi-pwren { + rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm15 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm15m2_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + avdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "avdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: nldo-reg4 { + regulator-name = "avdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&sata2 { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host3>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host3>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = ; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; From 637f7d2c731f1e5aa974bb572981a7a80834e6bb Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Sun, 14 Sep 2025 21:38:49 +0200 Subject: [PATCH 919/931] arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree The M2 Ultra in the Mac Pro differs from the M2 Ultra Mac Studio in its PCIe setup. It uses all available 16 PCIe Gen4 on the first die and 8 PCIe Gen4 lanes on the second die to connect to a 100 lane Microchip Switchtec PCIe switch. All internal PCIe devices and the PCIe slots are connected to the PCIe switch. Each die implements a PCIe controller with a single 16 or 8 lane port. The PCIe controller is mostly compatible with existing implementation in pcie-apple.c. The resources for other 8 lanes on the second die are used to connect the NVMe flash with the controller in the SoC. This initial device tree does not include PCIe support. Signed-off-by: Hector Martin Reviewed-by: Neal Gompa Co-developed-by: Janne Grunau Signed-off-by: Janne Grunau Reviewed-by: Sven Peter Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/Makefile | 1 + arch/arm64/boot/dts/apple/t6022-j180d.dts | 121 ++++++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t6022-j180d.dts diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index 21c4e02a4429..4eebcd85c90f 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -79,6 +79,7 @@ dtb-$(CONFIG_ARCH_APPLE) += t6000-j316s.dtb dtb-$(CONFIG_ARCH_APPLE) += t6001-j316c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6001-j375c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6002-j375d.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6022-j180d.dtb dtb-$(CONFIG_ARCH_APPLE) += t6020-j414s.dtb dtb-$(CONFIG_ARCH_APPLE) += t6021-j414c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6020-j416s.dtb diff --git a/arch/arm64/boot/dts/apple/t6022-j180d.dts b/arch/arm64/boot/dts/apple/t6022-j180d.dts new file mode 100644 index 000000000000..dca6bd167c22 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6022-j180d.dts @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Pro (M2 Ultra, 2023) + * + * target-type: J180d + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6022.dtsi" +#include "t6022-jxxxd.dtsi" + +/ { + compatible = "apple,j180d", "apple,t6022", "apple,arm-platform"; + model = "Apple Mac Pro (M2 Ultra, 2023)"; + aliases { + nvram = &nvram; + serial0 = &serial0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status = "disabled"; + power-domains = <&ps_dispext0_cpu0_die1>, <&ps_dptx_phy_ps_die1>; + }; + }; + + memory@10000000000 { + device_type = "memory"; + reg = <0x100 0 0x2 0>; /* To be filled by loader */ + }; +}; + +&serial0 { + status = "okay"; +}; + +/* USB Type C Rear */ +&i2c0 { + hpm2: usb-pd@3b { + compatible = "apple,cd321x"; + reg = <0x3b>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm3: usb-pd@3c { + compatible = "apple,cd321x"; + reg = <0x3c>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + /* hpm4 and hpm5 included from t6022-jxxxd.dtsi */ + + hpm6: usb-pd@3d { + compatible = "apple,cd321x"; + reg = <0x3d>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm7: usb-pd@3e { + compatible = "apple,cd321x"; + reg = <0x3e>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; + +/* USB Type C Front */ +&i2c3 { + status = "okay"; + + hpm0: usb-pd@38 { + compatible = "apple,cd321x"; + reg = <0x38>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <60 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm1: usb-pd@3f { + compatible = "apple,cd321x"; + reg = <0x3f>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <60 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; + +/* + * Delete unused PCIe nodes, the Mac Pro uses slightly different PCIe + * controllers with a single port connected to a PM40100 PCIe switch + */ +/delete-node/ &pcie0; +/delete-node/ &pcie0_dart_0; +/delete-node/ &pcie0_dart_1; +/delete-node/ &pcie0_dart_2; +/delete-node/ &pcie0_dart_3; + +&nco_clkref { + clock-frequency = <1068000000>; +}; + +#include "spi1-nvram.dtsi" From 8f6e6934e33ed95273b2a5467d244ab280beaeed Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Mon, 15 Sep 2025 09:52:25 +0800 Subject: [PATCH 920/931] arm64: dts: apple: t8012: Add SPMI node Add SPMI node for Apple T2 SoC. Signed-off-by: Nick Chan Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8012.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8012.dtsi b/arch/arm64/boot/dts/apple/t8012.dtsi index a259e5735d93..e7923814169b 100644 --- a/arch/arm64/boot/dts/apple/t8012.dtsi +++ b/arch/arm64/boot/dts/apple/t8012.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { interrupt-parent = <&aic>; @@ -220,6 +221,13 @@ pinctrl_aop: pinctrl@2100f0000 { ; }; + spmi: spmi@211180700 { + compatible = "apple,t8012-spmi", "apple,t8103-spmi"; + reg = <0x2 0x11180700 0x0 0x100>; + #address-cells = <2>; + #size-cells = <0>; + }; + pinctrl_nub: pinctrl@2111f0000 { compatible = "apple,t8010-pinctrl", "apple,pinctrl"; reg = <0x2 0x111f0000 0x0 0x1000>; From 70fa521f4d55127c85d7c2defe8c20be75e29efd Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Mon, 15 Sep 2025 09:52:26 +0800 Subject: [PATCH 921/931] arm64: dts: apple: t8015: Add SPMI node Add SPMI node for Apple A11 SoC. Signed-off-by: Nick Chan Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8015.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/apple/t8015.dtsi index 794140eb7650..586d3cf1f375 100644 --- a/arch/arm64/boot/dts/apple/t8015.dtsi +++ b/arch/arm64/boot/dts/apple/t8015.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { interrupt-parent = <&aic>; @@ -420,6 +421,13 @@ pinctrl_aop: pinctrl@2340f0000 { ; }; + spmi: spmi@235180700 { + compatible = "apple,t8015-spmi", "apple,t8103-spmi"; + reg = <0x2 0x35180700 0x0 0x100>; + #address-cells = <2>; + #size-cells = <0>; + }; + pinctrl_nub: pinctrl@2351f0000 { compatible = "apple,t8015-pinctrl", "apple,pinctrl"; reg = <0x2 0x351f0000 0x0 0x4000>; From f9d3206506b4db2711eca0f6b3d9dc621cc1e650 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=2E=20Neusch=C3=A4fer?= Date: Thu, 18 Sep 2025 12:58:43 +0200 Subject: [PATCH 922/931] dt-bindings: arm: sunxi: Add Amediatech X96Q MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The X96Q is a set-top box with an H313 SoC, AXP305 PMIC, 1 or 2 GiB RAM, 8 or 16 GiB eMMC flash, 2x USB A, Micro-SD, HDMI, Ethernet, audio/video output, and infrared input. https://x96mini.com/products/x96q-tv-box-android-10-set-top-box Reviewed-by: Andre Przywara Acked-by: Rob Herring (Arm) Signed-off-by: J. Neuschäfer Link: https://patch.msgid.link/20250918-x96q-v2-1-51bd39928806@posteo.net Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 72ef861a0b68..9e4627f97d7e 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -971,6 +971,11 @@ properties: - const: hechuang,x96-mate - const: allwinner,sun50i-h616 + - description: X96Q + items: + - const: amediatech,x96q + - const: allwinner,sun50i-h616 + - description: X96Q Pro+ items: - const: amediatech,x96q-pro-plus From 07c7f4f4e9504da240ef68adfd95a1150d3a6fd4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=2E=20Neusch=C3=A4fer?= Date: Thu, 18 Sep 2025 12:58:44 +0200 Subject: [PATCH 923/931] arm64: dts: allwinner: h313: Add Amediatech X96Q MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The X96Q is a set-top box with an H313 SoC, AXP305 PMIC, 1 or 2 GiB RAM, 8 or 16 GiB eMMC flash, 2x USB A, Micro-SD, HDMI, Ethernet, audio/video output, and infrared input. https://x96mini.com/products/x96q-tv-box-android-10-set-top-box Tested, works: - debug UART - status LED - USB ports in host mode - MicroSD - eMMC - recovery button hidden behind audio/video port - analog audio (line out) Does not work: - Ethernet (requires AC200 MFD/EPHY driver) - WLAN (requires out-of-tree XRadio driver) - analog video output (requires AC200 driver) - HDMI audio/video output Untested: - "OTG" USB port in device mode - built-in IR receiver - external IR receiver Table of regulators on the downstream kernel, for reference: vcc-5v 1 15 0 unknown 5000mV 0mA 5000mV 5000mV dcdca 0 0 0 unknown 900mV 0mA 0mV 0mV dcdcb 0 0 0 unknown 1350mV 0mA 0mV 0mV dcdcc 0 0 0 unknown 900mV 0mA 0mV 0mV dcdcd 0 0 0 unknown 1500mV 0mA 0mV 0mV dcdce 0 0 0 unknown 3300mV 0mA 0mV 0mV aldo1 0 0 0 unknown 3300mV 0mA 0mV 0mV aldo2 0 0 0 unknown 700mV 0mA 0mV 0mV aldo3 0 0 0 unknown 700mV 0mA 0mV 0mV bldo1 0 0 0 unknown 1800mV 0mA 0mV 0mV bldo2 0 0 0 unknown 1800mV 0mA 0mV 0mV bldo3 0 0 0 unknown 700mV 0mA 0mV 0mV bldo4 0 0 0 unknown 700mV 0mA 0mV 0mV cldo1 0 0 0 unknown 2500mV 0mA 0mV 0mV cldo2 0 0 0 unknown 700mV 0mA 0mV 0mV cldo3 0 0 0 unknown 700mV 0mA 0mV 0mV Signed-off-by: J. Neuschäfer Reviewed-by: Andre Przywara Link: https://patch.msgid.link/20250918-x96q-v2-2-51bd39928806@posteo.net Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../boot/dts/allwinner/sun50i-h313-x96q.dts | 230 ++++++++++++++++++ 2 files changed, 231 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h313-x96q.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 780aeba0f3a4..2edfa7bf4ab3 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-tanix-tx1.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-x96q.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-manta.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-pi.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q.dts b/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q.dts new file mode 100644 index 000000000000..b2275eb3d55b --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 J. Neuschäfer + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" + +#include +#include +#include +#include + +/ { + model = "X96Q"; + compatible = "amediatech,x96q", "allwinner,sun50i-h616"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC input */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-recovery { + label = "Recovery"; + linux,code = ; + gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + gpios = <&pio 7 6 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; +}; + +&codec { + allwinner,audio-routing = "Line Out", "LINEOUT"; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdca>; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +/* TODO: EMAC1 connected to AC200 PHY */ + +&gpu { + mali-supply = <®_dcdcc>; + status = "okay"; +}; + +&ir { + status = "okay"; +}; + +&mmc0 { + /* microSD */ + vmmc-supply = <®_aldo1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +/* TODO: XRadio XR819 WLAN @ mmc1 */ + +&mmc2 { + /* eMMC */ + vmmc-supply = <®_aldo1>; + vqmmc-supply = <®_bldo1>; + non-removable; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <100000000>; /* required for stable operation */ + bus-width = <8>; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&r_i2c { + status = "okay"; + + axp305: pmic@36 { + compatible = "x-powers,axp305", "x-powers,axp805", + "x-powers,axp806"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x36>; + + x-powers,self-working-mode; + vina-supply = <®_vcc5v>; + vinb-supply = <®_vcc5v>; + vinc-supply = <®_vcc5v>; + vind-supply = <®_vcc5v>; + vine-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + dcdcb { + /* unused */ + }; + + reg_dcdcc: dcdcc { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + dcdcd { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd-dram"; + }; + + dcdce { + /* unused */ + }; + + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3"; + }; + + aldo2 { + /* unused */ + }; + + aldo3 { + /* unused */ + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + bldo2 { + /* unused */ + }; + + bldo3 { + /* unused */ + }; + + bldo4 { + /* unused */ + }; + + cldo1 { + /* unused */ + }; + + cldo2 { + /* unused */ + }; + + cldo3 { + /* unused */ + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbotg { + dr_mode = "host"; /* USB A type receptacle */ + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; From 0099675695aab4356f7d05c507edb60fe72a4973 Mon Sep 17 00:00:00 2001 From: Jie Zhang Date: Wed, 3 Sep 2025 12:49:54 +0530 Subject: [PATCH 924/931] arm64: dts: qcom: qcs8300: Add gpu and gmu nodes Add gpu and gmu nodes for qcs8300 chipset. Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250903-a623-gpu-support-v5-3-5398585e2981@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 105 +++++++++++++++++++++++++- 1 file changed, 104 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index d35bfece60d1..8d78ccac411e 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -924,9 +924,14 @@ ipcc: mailbox@408000 { qfprom: efuse@784000 { compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; - reg = <0x0 0x00784000 0x0 0x1200>; + reg = <0x0 0x00784000 0x0 0x2410>; #address-cells = <1>; #size-cells = <1>; + + gpu_speed_bin: gpu_speed_bin@240c { + reg = <0x240c 0x1>; + bits = <0 8>; + }; }; gpi_dma0: dma-controller@900000 { @@ -4289,6 +4294,104 @@ serdes0: phy@8909000 { status = "disabled"; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-623.0", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts = ; + iommus = <&adreno_smmu 0 0xc00>, + <&adreno_smmu 1 0xc00>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + #cooling-cells = <2>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + status = "disabled"; + + gpu_zap_shader: zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-877000000 { + opp-hz = /bits/ 64 <877000000>; + opp-level = ; + opp-peak-kBps = <12484375>; + opp-supported-hw = <0x1>; + }; + + opp-780000000 { + opp-hz = /bits/ 64 <780000000>; + opp-level = ; + opp-peak-kBps = <10687500>; + opp-supported-hw = <0x1>; + }; + + opp-599000000 { + opp-hz = /bits/ 64 <599000000>; + opp-level = ; + opp-peak-kBps = <8171875>; + opp-supported-hw = <0x3>; + }; + + opp-479000000 { + opp-hz = /bits/ 64 <479000000>; + opp-level = ; + opp-peak-kBps = <5285156>; + opp-supported-hw = <0x3>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x34000>, + <0x0 0x03de0000 0x0 0x10000>, + <0x0 0x0b290000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub"; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + iommus = <&adreno_smmu 5 0xc00>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,qcs8300-gpucc"; reg = <0x0 0x03d90000 0x0 0xa000>; From 9da690f1b649c9900dd97b9bcd78e4a5ec61f2ff Mon Sep 17 00:00:00 2001 From: Jie Zhang Date: Wed, 3 Sep 2025 12:49:56 +0530 Subject: [PATCH 925/931] arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU Enable GPU for qcs8300-ride platform and provide path for zap shader. Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250903-a623-gpu-support-v5-5-5398585e2981@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index f8ed510477cf..cabb3f508704 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -296,6 +296,14 @@ queue3 { }; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs8300/a623_zap.mbn"; +}; + &pmm8650au_1_gpios { usb2_en: usb2-en-state { pins = "gpio7"; From ed7e440531601ba558fb81856352ef260ecb153f Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Tue, 9 Sep 2025 21:16:59 +0530 Subject: [PATCH 926/931] arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU Enable GPU for monaco-evk platform and provide path for zap shader. Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250909-monaco-evk-gpu-v1-1-e14938780411@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index 116378d4ce7a..e72cf6725a52 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -309,6 +309,14 @@ &gpi_dma1 { status = "okay"; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs8300/a623_zap.mbn"; +}; + &i2c1 { pinctrl-0 = <&qup_i2c1_default>; pinctrl-names = "default"; From f2983d8a1ea2812a4ccf6693dcd59118ac3f0a8e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 16 Sep 2025 20:18:28 +0300 Subject: [PATCH 927/931] arm64: dts: qcom: sm6350: correct DP compatibility strings SM6350 doesn't have MST support, as such in DT schema it has been switched to use SC7180 as a fallback compatible. Make DT file implement this change. DisplayPort on SC7180 has been supported long ago (and long before we added support for DP on SM8350). The driver will continue to work with the old DTS (having qcom,sm8350-dp fallback compatible) as even after adding MST support the driver will have to support old SM8350 DTS which didn't have MST clocks. Fixes: 62f87a3cac4e ("arm64: dts: qcom: sm6350: Add DisplayPort controller") Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250916-dp_mst_bindings-v9-1-68c674b39d8e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 2493b9611dcb..8459b27cacc7 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2249,7 +2249,7 @@ opp-560000000 { }; mdss_dp: displayport-controller@ae90000 { - compatible = "qcom,sm6350-dp", "qcom,sm8350-dp"; + compatible = "qcom,sm6350-dp", "qcom,sc7180-dp"; reg = <0x0 0xae90000 0x0 0x200>, <0x0 0xae90200 0x0 0x200>, <0x0 0xae90400 0x0 0x600>, From 2f695d3eac36601d383155e3bba189f06a0f750c Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Tue, 16 Sep 2025 20:18:29 +0300 Subject: [PATCH 928/931] arm64: dts: qcom: Add MST pixel streams for displayport Update Qualcomm DT files in order to declare extra stream pixel clocks and extra register resources used on these platforms to support DisplayPort MST. The driver will continue to work with the old DTS files as even after adding MST support the driver will have to support old DTS files which didn't have MST clocks. Signed-off-by: Jessica Zhang Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250916-dp_mst_bindings-v9-2-68c674b39d8e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 46 ++++++++++++---- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 10 ++-- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 23 +++++--- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 ++++++++++++++++++-------- arch/arm64/boot/dts/qcom/sdm845.dtsi | 15 ++++-- arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++-- arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 ++-- arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 ++-- arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 ++-- arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 ++-- arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++-- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 +++++++---- 13 files changed, 185 insertions(+), 74 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 48f753002fc4..cf685cb186ed 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -5070,7 +5070,11 @@ mdss0_dp0: displayport-controller@af54000 { <0x0 0x0af54200 0x0 0x0c0>, <0x0 0x0af55000 0x0 0x770>, <0x0 0x0af56000 0x0 0x09c>, - <0x0 0x0af57000 0x0 0x09c>; + <0x0 0x0af57000 0x0 0x09c>, + <0x0 0x0af58000 0x0 0x09c>, + <0x0 0x0af59000 0x0 0x09c>, + <0x0 0x0af5a000 0x0 0x23c>, + <0x0 0x0af5b000 0x0 0x23c>; interrupt-parent = <&mdss0>; interrupts = <12>; @@ -5079,15 +5083,28 @@ mdss0_dp0: displayport-controller@af54000 { <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents = <&mdss0_dp0_phy 0>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>; phys = <&mdss0_dp0_phy>; phy-names = "dp"; @@ -5149,7 +5166,11 @@ mdss0_dp1: displayport-controller@af5c000 { <0x0 0x0af5c200 0x0 0x0c0>, <0x0 0x0af5d000 0x0 0x770>, <0x0 0x0af5e000 0x0 0x09c>, - <0x0 0x0af5f000 0x0 0x09c>; + <0x0 0x0af5f000 0x0 0x09c>, + <0x0 0x0af60000 0x0 0x09c>, + <0x0 0x0af61000 0x0 0x09c>, + <0x0 0x0af62000 0x0 0x23c>, + <0x0 0x0af63000 0x0 0x23c>; interrupt-parent = <&mdss0>; interrupts = <13>; @@ -5158,15 +5179,20 @@ mdss0_dp1: displayport-controller@af5c000 { <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>; + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss0_dp1_phy 0>, + <&mdss0_dp1_phy 1>, + <&mdss0_dp1_phy 1>; phys = <&mdss0_dp1_phy>; phy-names = "dp"; diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index 96c4d2e06d9a..d65ad0df6865 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -2144,16 +2144,20 @@ mdss_dp0: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 4ac909214a86..4b04dea57ec8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -5144,7 +5144,8 @@ mdss_edp: edp@aea0000 { reg = <0 0x0aea0000 0 0x200>, <0 0x0aea0200 0 0x200>, <0 0x0aea0400 0 0xc00>, - <0 0x0aea1000 0 0x400>; + <0 0x0aea1000 0 0x400>, + <0 0x0aea1400 0 0x400>; interrupt-parent = <&mdss>; interrupts = <14>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 815095c2f8c7..85c2afcb417d 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3256,16 +3256,20 @@ mdss_dp0: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>; @@ -3334,16 +3338,20 @@ mdss_dp1: displayport-controller@ae98000 { <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>; @@ -3404,7 +3412,8 @@ mdss_edp: displayport-controller@ae9a000 { reg = <0 0xae9a000 0 0x200>, <0 0xae9a200 0 0x200>, <0 0xae9a400 0 0x600>, - <0 0xae9aa00 0 0x400>; + <0 0xae9aa00 0 0x400>, + <0 0xae9b000 0 0x400>; interrupt-parent = <&mdss>; interrupts = <14>; clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 225233a37a4f..279e5e6beae2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4706,15 +4706,19 @@ mdss0_dp0: displayport-controller@ae90000 { <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; @@ -4785,14 +4789,18 @@ mdss0_dp1: displayport-controller@ae98000 { <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; @@ -4862,10 +4870,12 @@ mdss0_dp2: displayport-controller@ae9a000 { <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, - <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent = <&mdss0>; interrupts = <14>; phys = <&mdss0_dp2_phy>; @@ -4873,8 +4883,11 @@ mdss0_dp2: displayport-controller@ae9a000 { power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, - <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss0_dp2_phy 0>, + <&mdss0_dp2_phy 1>, + <&mdss0_dp2_phy 1>; operating-points-v2 = <&mdss0_dp2_opp_table>; #sound-dai-cells = <0>; @@ -6043,10 +6056,12 @@ mdss1_dp0: displayport-controller@22090000 { <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent = <&mdss1>; interrupts = <12>; phys = <&mdss1_dp0_phy>; @@ -6054,8 +6069,11 @@ mdss1_dp0: displayport-controller@22090000 { power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp0_phy 0>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp0_phy 1>; operating-points-v2 = <&mdss1_dp0_opp_table>; #sound-dai-cells = <0>; @@ -6118,10 +6136,12 @@ mdss1_dp1: displayport-controller@22098000 { <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent = <&mdss1>; interrupts = <13>; phys = <&mdss1_dp1_phy>; @@ -6129,8 +6149,11 @@ mdss1_dp1: displayport-controller@22098000 { power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp1_phy 0>, + <&mdss1_dp1_phy 1>, + <&mdss1_dp1_phy 1>; operating-points-v2 = <&mdss1_dp1_opp_table>; #sound-dai-cells = <0>; @@ -6193,10 +6216,12 @@ mdss1_dp2: displayport-controller@2209a000 { <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, - <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + "ctrl_link_iface", "stream_pixel", + "stream_1_pixel"; interrupt-parent = <&mdss1>; interrupts = <14>; phys = <&mdss1_dp2_phy>; @@ -6204,8 +6229,11 @@ mdss1_dp2: displayport-controller@2209a000 { power-domains = <&rpmhpd SC8280XP_MMCX>; assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, - <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; - assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp2_phy 0>, + <&mdss1_dp2_phy 1>, + <&mdss1_dp2_phy 1>; operating-points-v2 = <&mdss1_dp2_opp_table>; #sound-dai-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index f322ebf3b4c2..13c9515260ef 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4656,12 +4656,19 @@ mdss_dp: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; - clock-names = "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; phy-names = "dp"; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 37478c76acee..acdba79612aa 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3890,16 +3890,20 @@ mdss_dp: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 6591b8172e08..50dd11432bb2 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4771,16 +4771,20 @@ mdss_dp: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index de1fae97ce44..fc4ce9d4977e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2876,16 +2876,20 @@ mdss_dp: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index e9ffa0af3cb3..23420e692472 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3434,16 +3434,20 @@ mdss_dp0: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ec67efd64b78..7724dba75db7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3759,16 +3759,20 @@ mdss_dp0: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index e7582a19184b..ebf1971b1bfb 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5660,16 +5660,20 @@ mdss_dp0: displayport-controller@af54000 { <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; operating-points-v2 = <&dp_opp_table>; diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index a6305077f150..51576d9c935d 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5476,16 +5476,20 @@ mdss_dp0: displayport-controller@ae90000 { <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; operating-points-v2 = <&mdss_dp0_opp_table>; @@ -5560,16 +5564,20 @@ mdss_dp1: displayport-controller@ae98000 { <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; operating-points-v2 = <&mdss_dp1_opp_table>; @@ -5644,16 +5652,20 @@ mdss_dp2: displayport-controller@ae9a000 { <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; operating-points-v2 = <&mdss_dp2_opp_table>; From c656932c3ece3eebe6240bb20e5c1d8aa0d7ecb0 Mon Sep 17 00:00:00 2001 From: Dharma Balasubiramani Date: Mon, 15 Sep 2025 14:43:57 +0530 Subject: [PATCH 929/931] ARM: dts: microchip: sam9x7: Add qspi controller Add support for QSPI controller. Signed-off-by: Dharma Balasubiramani Link: https://lore.kernel.org/r/20250915-sam9x7-qspi-dtsi-v1-1-1cc9adba7573@microchip.com Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/microchip/sam9x7.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/microchip/sam9x7.dtsi index 66c07e642c3e..46dacbbd201d 100644 --- a/arch/arm/boot/dts/microchip/sam9x7.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi @@ -271,6 +271,27 @@ AT91_XDMAC_DT_PERID(38))>, status = "disabled"; }; + qspi: spi@f0014000 { + compatible = "microchip,sam9x7-ospi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf0014000 0x100>, <0x60000000 0x20000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(26))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(27))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>; + clock-names = "pclk", "gclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 35>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_PLLADIV2>; + status = "disabled"; + }; + i2s: i2s@f001c000 { compatible = "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc"; reg = <0xf001c000 0x100>; From 676af08386e44fd6ea42b43db4c130bf04f36d92 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 19 Sep 2025 11:15:08 -0500 Subject: [PATCH 930/931] arm64: dts: apm-shadowcat: Move slimpro nodes out of "simple-bus" node The slimpro nodes are not MMIO devices, so they don't belong under a "simple-bus" node. Move them to the top level. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250919161509.1292227-1-robh@kernel.org Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index b98fd434b7d6..235ada884d27 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -224,6 +224,16 @@ timer { clock-frequency = <50000000>; }; + i2cslimpro { + compatible = "apm,xgene-slimpro-i2c"; + mboxes = <&mailbox 0>; + }; + + hwmonslimpro { + compatible = "apm,xgene-slimpro-hwmon"; + mboxes = <&mailbox 7>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -577,16 +587,6 @@ mailbox: mailbox@10540000 { 0x0 0x7 0x4>; }; - i2cslimpro { - compatible = "apm,xgene-slimpro-i2c"; - mboxes = <&mailbox 0>; - }; - - hwmonslimpro { - compatible = "apm,xgene-slimpro-hwmon"; - mboxes = <&mailbox 7>; - }; - serial0: serial@10600000 { compatible = "ns16550"; reg = <0 0x10600000 0x0 0x1000>; From 345518c00ba6bc90c8c557157bc0a6e081e7b2a4 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 19 Sep 2025 11:15:28 -0500 Subject: [PATCH 931/931] arm64: dts: apm-shadowcat: Drop "apm,xgene2-pcie" compatible The "apm,xgene2-pcie" compatible is unused, undocumented, and in the wrong position in the compatible list. Given this is a mature and little used platform, just remove the compatible rather than fix the order and document it. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250919161529.1293151-1-robh@kernel.org Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 235ada884d27..5bbedb0a7107 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -609,7 +609,7 @@ usb0: usb@19000000 { pcie0: pcie@1f2b0000 { status = "disabled"; device_type = "pci"; - compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; + compatible = "apm,xgene-pcie"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; @@ -635,7 +635,7 @@ pcie0: pcie@1f2b0000 { pcie1: pcie@1f2c0000 { status = "disabled"; device_type = "pci"; - compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; + compatible = "apm,xgene-pcie"; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>;