From e099febc8e2eb9f6a2454b2b433af23b5ddd5c03 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Thu, 4 May 2017 17:23:58 +0530 Subject: [PATCH 1/6] dt-bindings: qcom: Add IPQ8074 bindings This patch adds the IPQ8074 and related boards to the QCOM bindings. Signed-off-by: Varadarajan Narayanan Acked-by: Rob Herring Signed-off-by: Andy Gross --- Documentation/devicetree/bindings/arm/qcom.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt index 028d16e72186..0ed4d39d7fe1 100644 --- a/Documentation/devicetree/bindings/arm/qcom.txt +++ b/Documentation/devicetree/bindings/arm/qcom.txt @@ -25,6 +25,7 @@ The 'SoC' element must be one of the following strings: msm8994 msm8996 mdm9615 + ipq8074 The 'board' element must be one of the following strings: @@ -33,6 +34,7 @@ The 'board' element must be one of the following strings: dragonboard mtp sbc + hk01 The 'soc_version' and 'board_version' elements take the form of v. where the minor number may be omitted when it's zero, i.e. v1.0 is the same From ba4ca27ba9a03d0adf3949ba5033edcb3bb3c53b Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Mon, 3 Jul 2017 13:17:12 +0530 Subject: [PATCH 2/6] ARM: dts: ipq4019: Fix pinctrl node name This patch fixes the pinctrl node addresses to be the correct format. Signed-off-by: Varadarajan Narayanan Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi index b9457dd21a69..1ce253d0f72f 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -40,7 +40,7 @@ timer { clock-frequency = <48000000>; }; - pinctrl@0x01000000 { + pinctrl@1000000 { serial_pins: serial_pinmux { mux { pins = "gpio60", "gpio61"; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 4b7d97275c62..0eeff09856ba 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -119,7 +119,7 @@ gcc: clock-controller@1800000 { reg = <0x1800000 0x60000>; }; - tlmm: pinctrl@0x01000000 { + tlmm: pinctrl@1000000 { compatible = "qcom,ipq4019-pinctrl"; reg = <0x01000000 0x300000>; gpio-controller; From 75ea98acf7c62bf9dbe81eb5dd331ff670a649e5 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Mon, 3 Jul 2017 13:17:13 +0530 Subject: [PATCH 3/6] ARM: dts: ipq4019: Move xo and timer nodes to SoC dtsi The node for xo and timer belong to the SoC DTS file. Else, new board DT files may not inherit these nodes. Signed-off-by: Varadarajan Narayanan Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 19 ------------------- arch/arm/boot/dts/qcom-ipq4019.dtsi | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi index 1ce253d0f72f..c055a5785769 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -20,26 +20,7 @@ / { model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1"; compatible = "qcom,ipq4019"; - clocks { - xo: xo { - compatible = "fixed-clock"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; - }; - soc { - - - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 2 0xf08>, - <1 3 0xf08>, - <1 4 0xf08>, - <1 1 0xf08>; - clock-frequency = <48000000>; - }; - pinctrl@1000000 { serial_pins: serial_pinmux { mux { diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 0eeff09856ba..bd4b3c52d868 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -96,6 +96,21 @@ sleep_clk: sleep_clk { clock-frequency = <32768>; #clock-cells = <0>; }; + + xo: xo { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0xf08>, + <1 3 0xf08>, + <1 4 0xf08>, + <1 1 0xf08>; + clock-frequency = <48000000>; }; soc { From 6bfe03ddcd670e34a3fd8d3e573fd70580645ee1 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Fri, 7 Jul 2017 16:57:10 +0200 Subject: [PATCH 4/6] ARM: dts: qcom: add pseudo random number generator on the IPQ4019 This architecture has a pseudo random number generator supported by the existing "qcom,prng" binding. rngtest: bits received from input: 5795960032 rngtest: FIPS 140-2 successes: 289591 rngtest: FIPS 140-2 failures: 207 rngtest: FIPS 140-2(2001-10-10) Monobit: 25 rngtest: FIPS 140-2(2001-10-10) Poker: 28 rngtest: FIPS 140-2(2001-10-10) Runs: 91 rngtest: FIPS 140-2(2001-10-10) Long run: 67 rngtest: FIPS 140-2(2001-10-10) Continuous run: 0 rngtest: input channel speed: (min=244; avg=46122; max=3906250)Kibits/s rngtest: FIPS tests speed: (min=1.327; avg=20.966; max=26.345)Mibits/s rngtest: Program run time: 386965827 microseconds Signed-off-by: Christian Lamparter Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 4 ++++ arch/arm/boot/dts/qcom-ipq4019.dtsi | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi index c055a5785769..10a0c28cbab9 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -21,6 +21,10 @@ / { compatible = "qcom,ipq4019"; soc { + rng@22000 { + status = "ok"; + }; + pinctrl@1000000 { serial_pins: serial_pinmux { mux { diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index bd4b3c52d868..069243bc161c 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -134,6 +134,14 @@ gcc: clock-controller@1800000 { reg = <0x1800000 0x60000>; }; + rng@22000 { + compatible = "qcom,prng"; + reg = <0x22000 0x140>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + status = "disabled"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq4019-pinctrl"; reg = <0x01000000 0x300000>; From 8d4c75fbb0ef84b9148d9b5e0b4cadf40ce26b98 Mon Sep 17 00:00:00 2001 From: "Suzuki K. Poulose" Date: Thu, 20 Jul 2017 11:17:13 +0100 Subject: [PATCH 5/6] ARM: dts: qcom-msm8974: dts: Update coresight replicator Replace the obsolete compatible string for Coresight programmable replicator with the new one. Cc: Andy Gross Cc: David Brown Cc: linux-arm-msm@vger.kernel.org Cc: Mathieu Poirier Reviewed-by: Mathieu Poirier Signed-off-by: Suzuki K Poulose Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index c5ee68a3f7f5..a39207625354 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -779,7 +779,7 @@ tpiu_in: endpoint { }; replicator@fc31c000 { - compatible = "qcom,coresight-replicator1x", "arm,primecell"; + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; reg = <0xfc31c000 0x1000>; clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; From 0d363594c5287390310fa91be28d0efccb334779 Mon Sep 17 00:00:00 2001 From: Christian Lamparter Date: Sat, 22 Jul 2017 23:27:11 +0200 Subject: [PATCH 6/6] ARM: dts: qcom: add and enable both wifi blocks on the IPQ4019 This patch adds and enables the device-tree definitions for both qcom,ipq4019-wifi blocks for the IPQ4019. Support for these have been added into the ath10k driver since: commit 280e762e9c72 ("ath10k: enable ipq4019 device probe in ahb module") The binding documentation was added in: commit a47aaa69de88 ("dt: bindings: add new dt entry for pre calibration in qcom, ath10k.txt") This has been tested on an ASUS RT-AC58U (IPQ4019), an AVM Fritz!Box 4040 (IPQ4018), a Compex WPJ428 (IPQ4028) and a Cisco Meraki MR33 (IPQ4029). | a000000.wifi: qca4019 hw1.0 target 0x01000000 chip_id 0x003b00ff [...] | a000000.wifi: kconfig debug 0 debugfs 1 tracing 0 dfs 1 testmode 1 | a000000.wifi: firmware ver 10.4-3.4-00082 api 5 features no-p2p,mfp,[...] | a000000.wifi: board_file api 2 bmi_id 0:16 crc32 5773b188 | a000000.wifi: htt-ver 2.2 wmi-op 6 htt-op 4 cal pre-cal-file [...] ... | a800000.wifi: qca4019 hw1.0 target 0x01000000 chip_id 0x003b00ff sub 0000:0000 | a800000.wifi: kconfig debug 0 debugfs 1 tracing 0 dfs 1 testmode 1 | a800000.wifi: firmware ver 10.4-3.4-00082 api 5 features no-p2p, [...] | a800000.wifi: board_file api 2 bmi_id 0:17 crc32 5773b188 | a800000.wifi: htt-ver 2.2 wmi-op 6 htt-op 4 cal pre-cal-file [...] Signed-off-by: Christian Lamparter Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 8 ++ arch/arm/boot/dts/qcom-ipq4019.dtsi | 84 +++++++++++++++++++ 2 files changed, 92 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi index 10a0c28cbab9..e413b21ee331 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -93,5 +93,13 @@ crypto@8e3a000 { watchdog@b017000 { status = "ok"; }; + + wifi@a000000 { + status = "ok"; + }; + + wifi@a800000 { + status = "ok"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 069243bc161c..10d112a4078e 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -292,5 +292,89 @@ restart@4ab000 { compatible = "qcom,pshold"; reg = <0x4ab000 0x4>; }; + + wifi0: wifi@a000000 { + compatible = "qcom,ipq4019-wifi"; + reg = <0xa000000 0x200000>; + resets = <&gcc WIFI0_CPU_INIT_RESET>, + <&gcc WIFI0_RADIO_SRIF_RESET>, + <&gcc WIFI0_RADIO_WARM_RESET>, + <&gcc WIFI0_RADIO_COLD_RESET>, + <&gcc WIFI0_CORE_WARM_RESET>, + <&gcc WIFI0_CORE_COLD_RESET>; + reset-names = "wifi_cpu_init", "wifi_radio_srif", + "wifi_radio_warm", "wifi_radio_cold", + "wifi_core_warm", "wifi_core_cold"; + clocks = <&gcc GCC_WCSS2G_CLK>, + <&gcc GCC_WCSS2G_REF_CLK>, + <&gcc GCC_WCSS2G_RTC_CLK>; + clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", + "wifi_wcss_rtc"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", + "msi8", "msi9", "msi10", "msi11", + "msi12", "msi13", "msi14", "msi15", + "legacy"; + status = "disabled"; + }; + + wifi1: wifi@a800000 { + compatible = "qcom,ipq4019-wifi"; + reg = <0xa800000 0x200000>; + resets = <&gcc WIFI1_CPU_INIT_RESET>, + <&gcc WIFI1_RADIO_SRIF_RESET>, + <&gcc WIFI1_RADIO_WARM_RESET>, + <&gcc WIFI1_RADIO_COLD_RESET>, + <&gcc WIFI1_CORE_WARM_RESET>, + <&gcc WIFI1_CORE_COLD_RESET>; + reset-names = "wifi_cpu_init", "wifi_radio_srif", + "wifi_radio_warm", "wifi_radio_cold", + "wifi_core_warm", "wifi_core_cold"; + clocks = <&gcc GCC_WCSS5G_CLK>, + <&gcc GCC_WCSS5G_REF_CLK>, + <&gcc GCC_WCSS5G_RTC_CLK>; + clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", + "wifi_wcss_rtc"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", + "msi8", "msi9", "msi10", "msi11", + "msi12", "msi13", "msi14", "msi15", + "legacy"; + status = "disabled"; + }; }; };