mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-07-16 13:19:56 -04:00
Merge tag 'nand/for-6.14' into mtd/next
* Raw NAND changes A new controller driver, from Nuvoton, has been merged. Bastien Curutchet has contributed a series improving the Davinci controller driver, both on the organization of the code, but also on the performance side. The binding has also been converted to yaml, received a new OOB layout and now supports on-die ECC engines. The Qualcomm controller driver has been deeply cleaned to extract some parts of the code into a shared file with the Qualcomm SPI memory controller. Aside from these main changes, the Cadence binding has been converted to yaml, the brcmnand controller driver has received a small fix, otherwise some more minor changes have also made their way in. * SPI NAND changes The SPI NAND subsystem has seen a great improvement, with the advent of DTR operations (DDR operations, which may be extended to the address cycles). The first vendor driver to benefit from these improvements is the Winbond driver. A new manufacturer driver is added SkyHigh, with a new constraint for the core, it is impossible to disable the on-die ECC engine. A Foresee device is also now supported.
This commit is contained in:
Miquel Raynal
@@ -114,8 +114,9 @@ patternProperties:
|
||||
table that specifies the PPID to LIODN mapping. Needed if the PAMU is
|
||||
used. Value is a 12 bit value where value is a LIODN ID for this JR.
|
||||
This property is normally set by boot firmware.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 0xfff
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- maximum: 0xfff
|
||||
|
||||
'^rtic@[0-9a-f]+$':
|
||||
type: object
|
||||
@@ -186,8 +187,9 @@ patternProperties:
|
||||
Needed if the PAMU is used. Value is a 12 bit value where value
|
||||
is a LIODN ID for this JR. This property is normally set by boot
|
||||
firmware.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 0xfff
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- maximum: 0xfff
|
||||
|
||||
fsl,rtic-region:
|
||||
description:
|
||||
|
||||
@@ -90,7 +90,7 @@ properties:
|
||||
adi,dsi-lanes:
|
||||
description: Number of DSI data lanes connected to the DSI host.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 1, 2, 3, 4 ]
|
||||
enum: [ 2, 3, 4 ]
|
||||
|
||||
"#sound-dai-cells":
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||||
const: 0
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||||
|
||||
@@ -1,53 +0,0 @@
|
||||
* Cadence NAND controller
|
||||
|
||||
Required properties:
|
||||
- compatible : "cdns,hp-nfc"
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||||
- reg : Contains two entries, each of which is a tuple consisting of a
|
||||
physical address and length. The first entry is the address and
|
||||
length of the controller register set. The second entry is the
|
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address and length of the Slave DMA data port.
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- reg-names: should contain "reg" and "sdma"
|
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- #address-cells: should be 1. The cell encodes the chip select connection.
|
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- #size-cells : should be 0.
|
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- interrupts : The interrupt number.
|
||||
- clocks: phandle of the controller core clock (nf_clk).
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||||
|
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Optional properties:
|
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- dmas: shall reference DMA channel associated to the NAND controller
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- cdns,board-delay-ps : Estimated Board delay. The value includes the total
|
||||
round trip delay for the signals and is used for deciding on values
|
||||
associated with data read capture. The example formula for SDR mode is
|
||||
the following:
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board delay = RE#PAD delay + PCB trace to device + PCB trace from device
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||||
+ DQ PAD delay
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||||
|
||||
Child nodes represent the available NAND chips.
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||||
|
||||
Required properties of NAND chips:
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- reg: shall contain the native Chip Select ids from 0 to max supported by
|
||||
the cadence nand flash controller
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||||
|
||||
See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
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generic bindings.
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||||
|
||||
Example:
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||||
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nand_controller: nand-controller@60000000 {
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compatible = "cdns,hp-nfc";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
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reg-names = "reg", "sdma";
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clocks = <&nf_clk>;
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cdns,board-delay-ps = <4830>;
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interrupts = <2 0>;
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nand@0 {
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reg = <0>;
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label = "nand-1";
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||||
};
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nand@1 {
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reg = <1>;
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label = "nand-2";
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};
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||||
|
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};
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75
Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
Normal file
75
Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
Normal file
@@ -0,0 +1,75 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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||||
%YAML 1.2
|
||||
---
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||||
$id: http://devicetree.org/schemas/mtd/cdns,hp-nfc.yaml#
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||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cadence NAND controller
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||||
|
||||
maintainers:
|
||||
- Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
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||||
|
||||
allOf:
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- $ref: nand-controller.yaml
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||||
|
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properties:
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compatible:
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items:
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||||
- const: cdns,hp-nfc
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||||
|
||||
reg:
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items:
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||||
- description: Controller register set
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||||
- description: Slave DMA data port register set
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||||
|
||||
reg-names:
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||||
items:
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||||
- const: reg
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||||
- const: sdma
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||||
|
||||
interrupts:
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||||
maxItems: 1
|
||||
|
||||
clocks:
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||||
maxItems: 1
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||||
|
||||
dmas:
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||||
maxItems: 1
|
||||
|
||||
cdns,board-delay-ps:
|
||||
description: |
|
||||
Estimated Board delay. The value includes the total round trip
|
||||
delay for the signals and is used for deciding on values associated
|
||||
with data read capture. The example formula for SDR mode is the
|
||||
following.
|
||||
board delay = RE#PAD delay + PCB trace to device + PCB trace from device
|
||||
+ DQ PAD delay
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
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||||
|
||||
nand-controller@10b80000 {
|
||||
compatible = "cdns,hp-nfc";
|
||||
reg = <0x10b80000 0x10000>,
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||||
<0x10840000 0x10000>;
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||||
reg-names = "reg", "sdma";
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||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
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||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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||||
clocks = <&nf_clk>;
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||||
cdns,board-delay-ps = <4830>;
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
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||||
@@ -1,94 +0,0 @@
|
||||
Device tree bindings for Texas instruments Davinci/Keystone NAND controller
|
||||
|
||||
This file provides information, what the device node for the davinci/keystone
|
||||
NAND interface contains.
|
||||
|
||||
Documentation:
|
||||
Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
|
||||
Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "ti,davinci-nand"
|
||||
"ti,keystone-nand"
|
||||
|
||||
- reg: Contains 2 offset/length values:
|
||||
- offset and length for the access window.
|
||||
- offset and length for accessing the AEMIF
|
||||
control registers.
|
||||
|
||||
- ti,davinci-chipselect: number of chipselect. Indicates on the
|
||||
davinci_nand driver which chipselect is used
|
||||
for accessing the nand.
|
||||
Can be in the range [0-3].
|
||||
|
||||
Recommended properties :
|
||||
|
||||
- ti,davinci-mask-ale: mask for ALE. Needed for executing address
|
||||
phase. These offset will be added to the base
|
||||
address for the chip select space the NAND Flash
|
||||
device is connected to.
|
||||
If not set equal to 0x08.
|
||||
|
||||
- ti,davinci-mask-cle: mask for CLE. Needed for executing command
|
||||
phase. These offset will be added to the base
|
||||
address for the chip select space the NAND Flash
|
||||
device is connected to.
|
||||
If not set equal to 0x10.
|
||||
|
||||
- ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask
|
||||
addresses for given chipselect.
|
||||
|
||||
- nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
|
||||
valid values for davinci driver:
|
||||
- "none"
|
||||
- "soft"
|
||||
- "hw"
|
||||
|
||||
- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
|
||||
|
||||
- nand-bus-width: buswidth 8 or 16. If not present 8.
|
||||
|
||||
- nand-on-flash-bbt: use flash based bad block table support. OOB
|
||||
identifier is saved in OOB area. If not present
|
||||
false.
|
||||
|
||||
Deprecated properties:
|
||||
|
||||
- ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
|
||||
valid values for davinci driver:
|
||||
- "none"
|
||||
- "soft"
|
||||
- "hw"
|
||||
|
||||
- ti,davinci-nand-buswidth: buswidth 8 or 16. If not present 8.
|
||||
|
||||
- ti,davinci-nand-use-bbt: use flash based bad block table support. OOB
|
||||
identifier is saved in OOB area. If not present
|
||||
false.
|
||||
|
||||
Nand device bindings may contain additional sub-nodes describing partitions of
|
||||
the address space. See mtd.yaml for more detail. The NAND Flash timing
|
||||
values must be programmed in the chip select’s node of AEMIF
|
||||
memory-controller (see Documentation/devicetree/bindings/memory-controllers/
|
||||
davinci-aemif.txt).
|
||||
|
||||
Example(da850 EVM ):
|
||||
|
||||
nand_cs3@62000000 {
|
||||
compatible = "ti,davinci-nand";
|
||||
reg = <0x62000000 0x807ff
|
||||
0x68000000 0x8000>;
|
||||
ti,davinci-chipselect = <1>;
|
||||
ti,davinci-mask-ale = <0>;
|
||||
ti,davinci-mask-cle = <0>;
|
||||
ti,davinci-mask-chipsel = <0>;
|
||||
nand-ecc-mode = "hw";
|
||||
ti,davinci-ecc-bits = <4>;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
partition@180000 {
|
||||
label = "ubifs";
|
||||
reg = <0x180000 0x7e80000>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,95 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mtd/nuvoton,ma35d1-nand.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Nuvoton MA35D1 NAND Flash Interface (NFI) Controller
|
||||
|
||||
maintainers:
|
||||
- Hui-Ping Chen <hpchen0nvt@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: nand-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nuvoton,ma35d1-nand-controller
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
"^nand@[a-f0-9]$":
|
||||
type: object
|
||||
$ref: raw-nand-chip.yaml
|
||||
properties:
|
||||
reg:
|
||||
minimum: 0
|
||||
maximum: 1
|
||||
|
||||
nand-ecc-step-size:
|
||||
enum: [512, 1024]
|
||||
|
||||
nand-ecc-strength:
|
||||
enum: [8, 12, 24]
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
nand-controller@401A0000 {
|
||||
compatible = "nuvoton,ma35d1-nand-controller";
|
||||
reg = <0x0 0x401A0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk NAND_GATE>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
nand-on-flash-bbt;
|
||||
nand-ecc-step-size = <512>;
|
||||
nand-ecc-strength = <8>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
uboot@0 {
|
||||
label = "nand-uboot";
|
||||
read-only;
|
||||
reg = <0x0 0x300000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@@ -82,7 +82,7 @@ examples:
|
||||
|
||||
uimage@100000 {
|
||||
reg = <0x0100000 0x200000>;
|
||||
compress = "lzma";
|
||||
compression = "lzma";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
124
Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
Normal file
124
Documentation/devicetree/bindings/mtd/ti,davinci-nand.yaml
Normal file
@@ -0,0 +1,124 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI DaVinci NAND controller
|
||||
|
||||
maintainers:
|
||||
- Marcus Folkesson <marcus.folkesson@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: nand-controller.yaml
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,davinci-nand
|
||||
- ti,keystone-nand
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Access window.
|
||||
- description: AEMIF control registers.
|
||||
|
||||
partitions:
|
||||
$ref: /schemas/mtd/partitions/partitions.yaml
|
||||
|
||||
ti,davinci-chipselect:
|
||||
description:
|
||||
Number of chipselect. Indicate on the davinci_nand driver which
|
||||
chipselect is used for accessing the nand.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
|
||||
ti,davinci-mask-ale:
|
||||
description:
|
||||
Mask for ALE. Needed for executing address phase. These offset will be
|
||||
added to the base address for the chip select space the NAND Flash
|
||||
device is connected to.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0x08
|
||||
|
||||
ti,davinci-mask-cle:
|
||||
description:
|
||||
Mask for CLE. Needed for executing command phase. These offset will be
|
||||
added to the base address for the chip select space the NAND Flash device
|
||||
is connected to.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0x10
|
||||
|
||||
ti,davinci-mask-chipsel:
|
||||
description:
|
||||
Mask for chipselect address. Needed to mask addresses for given
|
||||
chipselect.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0
|
||||
|
||||
ti,davinci-ecc-bits:
|
||||
description: Used ECC bits.
|
||||
enum: [1, 4]
|
||||
|
||||
ti,davinci-ecc-mode:
|
||||
description: Operation mode of the NAND ECC mode.
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
enum: [none, soft, hw, on-die]
|
||||
deprecated: true
|
||||
|
||||
ti,davinci-nand-buswidth:
|
||||
description: Bus width to the NAND chip.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [8, 16]
|
||||
default: 8
|
||||
deprecated: true
|
||||
|
||||
ti,davinci-nand-use-bbt:
|
||||
type: boolean
|
||||
description:
|
||||
Use flash based bad block table support. OOB identifier is saved in OOB
|
||||
area.
|
||||
deprecated: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ti,davinci-chipselect
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
nand-controller@2000000,0 {
|
||||
compatible = "ti,davinci-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0 0x02000000 0x02000000>,
|
||||
<1 0x00000000 0x00008000>;
|
||||
|
||||
ti,davinci-chipselect = <1>;
|
||||
ti,davinci-mask-ale = <0>;
|
||||
ti,davinci-mask-cle = <0>;
|
||||
ti,davinci-mask-chipsel = <0>;
|
||||
|
||||
ti,davinci-nand-buswidth = <16>;
|
||||
ti,davinci-ecc-mode = "hw";
|
||||
ti,davinci-ecc-bits = <4>;
|
||||
ti,davinci-nand-use-bbt;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot env";
|
||||
reg = <0 0x020000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -113,11 +113,8 @@ allOf:
|
||||
maxItems: 1
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx95-usb-phy
|
||||
required:
|
||||
- orientation-switch
|
||||
then:
|
||||
$ref: /schemas/usb/usb-switch.yaml#
|
||||
|
||||
|
||||
@@ -55,6 +55,10 @@ patternProperties:
|
||||
patternProperties:
|
||||
"^power-domain@[0-9a-f]+$":
|
||||
$ref: "#/$defs/power-domain-node"
|
||||
patternProperties:
|
||||
"^power-domain@[0-9a-f]+$":
|
||||
$ref: "#/$defs/power-domain-node"
|
||||
unevaluatedProperties: false
|
||||
unevaluatedProperties: false
|
||||
unevaluatedProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
@@ -18,6 +18,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,qca6390-pmu
|
||||
- qcom,wcn6750-pmu
|
||||
- qcom,wcn6855-pmu
|
||||
- qcom,wcn7850-pmu
|
||||
|
||||
@@ -27,6 +28,9 @@ properties:
|
||||
vddaon-supply:
|
||||
description: VDD_AON supply regulator handle
|
||||
|
||||
vddasd-supply:
|
||||
description: VDD_ASD supply regulator handle
|
||||
|
||||
vdddig-supply:
|
||||
description: VDD_DIG supply regulator handle
|
||||
|
||||
@@ -42,6 +46,9 @@ properties:
|
||||
vddio1p2-supply:
|
||||
description: VDD_IO_1P2 supply regulator handle
|
||||
|
||||
vddrfa0p8-supply:
|
||||
description: VDD_RFA_0P8 supply regulator handle
|
||||
|
||||
vddrfa0p95-supply:
|
||||
description: VDD_RFA_0P95 supply regulator handle
|
||||
|
||||
@@ -51,12 +58,18 @@ properties:
|
||||
vddrfa1p3-supply:
|
||||
description: VDD_RFA_1P3 supply regulator handle
|
||||
|
||||
vddrfa1p7-supply:
|
||||
description: VDD_RFA_1P7 supply regulator handle
|
||||
|
||||
vddrfa1p8-supply:
|
||||
description: VDD_RFA_1P8 supply regulator handle
|
||||
|
||||
vddrfa1p9-supply:
|
||||
description: VDD_RFA_1P9 supply regulator handle
|
||||
|
||||
vddrfa2p2-supply:
|
||||
description: VDD_RFA_2P2 supply regulator handle
|
||||
|
||||
vddpcie1p3-supply:
|
||||
description: VDD_PCIE_1P3 supply regulator handle
|
||||
|
||||
@@ -119,6 +132,20 @@ allOf:
|
||||
- vddpcie1p3-supply
|
||||
- vddpcie1p9-supply
|
||||
- vddio-supply
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: qcom,wcn6750-pmu
|
||||
then:
|
||||
required:
|
||||
- vddaon-supply
|
||||
- vddasd-supply
|
||||
- vddpmu-supply
|
||||
- vddrfa0p8-supply
|
||||
- vddrfa1p2-supply
|
||||
- vddrfa1p7-supply
|
||||
- vddrfa2p2-supply
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -35,6 +35,7 @@ properties:
|
||||
|
||||
fsl,liodn:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
maxItems: 2
|
||||
description: See pamu.txt. Two LIODN(s). DQRR LIODN (DLIODN) and Frame LIODN
|
||||
(FLIODN)
|
||||
|
||||
@@ -69,6 +70,7 @@ patternProperties:
|
||||
type: object
|
||||
properties:
|
||||
fsl,liodn:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description: See pamu.txt, PAMU property used for static LIODN assignment
|
||||
|
||||
fsl,iommu-parent:
|
||||
|
||||
@@ -51,7 +51,7 @@ properties:
|
||||
description: Power supply for AVDD, providing 1.8V.
|
||||
|
||||
cpvdd-supply:
|
||||
description: Power supply for CPVDD, providing 3.5V.
|
||||
description: Power supply for CPVDD, providing 1.8V.
|
||||
|
||||
hp-detect-gpios:
|
||||
description:
|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/watchdog/airoha,en7581-wdt.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Airoha EN7581 Watchdog Timer
|
||||
|
||||
maintainers:
|
||||
- Christian Marangi <ansuelsmth@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: watchdog.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: airoha,en7581-wdt
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
description: BUS clock (timer ticks at half the BUS clock)
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: bus
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/en7523-clk.h>
|
||||
|
||||
watchdog@1fbf0100 {
|
||||
compatible = "airoha,en7581-wdt";
|
||||
reg = <0x1fbf0100 0x3c>;
|
||||
|
||||
clocks = <&scuclk EN7523_CLK_BUS>;
|
||||
clock-names = "bus";
|
||||
};
|
||||
@@ -48,6 +48,8 @@ properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
big-endian: true
|
||||
|
||||
fsl,ext-reset-output:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: |
|
||||
@@ -93,6 +95,18 @@ allOf:
|
||||
properties:
|
||||
fsl,suspend-in-wait: false
|
||||
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,ls1012a-wdt
|
||||
- fsl,ls1043a-wdt
|
||||
then:
|
||||
properties:
|
||||
big-endian: false
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@@ -26,6 +26,8 @@ properties:
|
||||
- qcom,apss-wdt-msm8994
|
||||
- qcom,apss-wdt-qcm2290
|
||||
- qcom,apss-wdt-qcs404
|
||||
- qcom,apss-wdt-qcs615
|
||||
- qcom,apss-wdt-qcs8300
|
||||
- qcom,apss-wdt-sa8255p
|
||||
- qcom,apss-wdt-sa8775p
|
||||
- qcom,apss-wdt-sc7180
|
||||
|
||||
@@ -26,6 +26,7 @@ properties:
|
||||
- samsung,exynos7-wdt # for Exynos7
|
||||
- samsung,exynos850-wdt # for Exynos850
|
||||
- samsung,exynosautov9-wdt # for Exynosautov9
|
||||
- samsung,exynosautov920-wdt # for Exynosautov920
|
||||
- items:
|
||||
- enum:
|
||||
- tesla,fsd-wdt
|
||||
@@ -77,6 +78,7 @@ allOf:
|
||||
- samsung,exynos7-wdt
|
||||
- samsung,exynos850-wdt
|
||||
- samsung,exynosautov9-wdt
|
||||
- samsung,exynosautov920-wdt
|
||||
then:
|
||||
required:
|
||||
- samsung,syscon-phandle
|
||||
@@ -88,6 +90,7 @@ allOf:
|
||||
- google,gs101-wdt
|
||||
- samsung,exynos850-wdt
|
||||
- samsung,exynosautov9-wdt
|
||||
- samsung,exynosautov920-wdt
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
|
||||
Reference in New Issue
Block a user