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Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux

Browse Source 
Saeed Mahameed says:

====================
updates from mlx5-next 2022-09-24

Updates form mlx5-next including[1]:

1) HW definitions and support for NPPS clock settings.

2) various cleanups

3) Enable hash mode by default for all NICs

4) page tracker and advanced virtualization HW definitions for vfio

[1] https://lore.kernel.org/netdev/20220907233636.388475-1-saeed@kernel.org/

* 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux:
  net/mlx5: Remove from FPGA IFC file not-needed definitions
  net/mlx5: Remove unused structs
  net/mlx5: Remove unused functions
  net/mlx5: detect and enable bypass port select flow table
  net/mlx5: Lag, enable hash mode by default for all NICs
  net/mlx5: Lag, set active ports if support bypass port select flow table
  RDMA/mlx5: Don't set tx affinity when lag is in hash mode
  net/mlx5: add IFC bits for bypassing port select flow table
  net/mlx5: Add support for NPPS with real time mode
  net/mlx5: Expose NPPS related registers
  net/mlx5: Query ADV_VIRTUALIZATION capabilities
  net/mlx5: Introduce ifc bits for page tracker
  RDMA/mlx5: Move function mlx5_core_query_ib_ppcnt() to mlx5_ib
====================

Link: https://lore.kernel.org/all/20220927201906.234015-1-saeed@kernel.org/
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
2022-09-28 19:20:49 -07:00
parent d4ddeefa64 9175d81037
commit 0d5bfebf74
16 changed files with 406 additions and 184 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
include/linux/mlx5/device.h
View File

@@ -882,12 +882,6 @@ static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
return cqe->op_own >> 4;
}
static inline u8 get_cqe_enhanced_num_mini_cqes(struct mlx5_cqe64 *cqe)
{
/* num_of_mini_cqes is zero based */
return get_cqe_opcode(cqe) + 1;
}
static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
{
return (cqe->lro.tcppsh_abort_dupack >> 6) & 1;
@@ -898,11 +892,6 @@ static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
return (cqe->l4_l3_hdr_type >> 4) & 0x7;
}
static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
{
return (cqe->l4_l3_hdr_type >> 2) & 0x3;
}
static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
{
return cqe->tls_outer_l3_tunneled & 0x1;
@@ -1209,6 +1198,7 @@ enum mlx5_cap_type {
MLX5_CAP_MACSEC = 0x1f,
MLX5_CAP_GENERAL_2 = 0x20,
MLX5_CAP_PORT_SELECTION = 0x25,
MLX5_CAP_ADV_VIRTUALIZATION = 0x26,
/* NUM OF CAP Types */
MLX5_CAP_NUM
};
@@ -1374,6 +1364,14 @@ enum mlx5_qcam_feature_groups {
MLX5_GET(port_selection_cap, \
mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap)
#define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \
MLX5_GET(adv_virtualization_cap, \
mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
#define MLX5_CAP_ADV_VIRTUALIZATION_MAX(mdev, cap) \
MLX5_GET(adv_virtualization_cap, \
mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->max, cap)
#define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \
MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)

11
include/linux/mlx5/driver.h
View File

@@ -698,6 +698,8 @@ struct mlx5_pps {
struct work_struct out_work;
u64 start[MAX_PIN_NUM];
u8 enabled;
u64 min_npps_period;
u64 min_out_pulse_duration_ns;
};
struct mlx5_timer {
@@ -855,11 +857,6 @@ struct mlx5_cmd_work_ent {
refcount_t refcnt;
};
struct mlx5_pas {
u64 pa;
u8 log_sz;
};
enum phy_port_state {
MLX5_AAA_111
};
@@ -1016,7 +1013,6 @@ int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
void mlx5_health_flush(struct mlx5_core_dev *dev);
void mlx5_health_cleanup(struct mlx5_core_dev *dev);
int mlx5_health_init(struct mlx5_core_dev *dev);
void mlx5_start_health_poll(struct mlx5_core_dev *dev);
@@ -1085,8 +1081,6 @@ int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
struct mlx5_odp_caps *odp_caps);
int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
u8 port_num, void *out, size_t sz);
int mlx5_init_rl_table(struct mlx5_core_dev *dev);
void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
@@ -1153,6 +1147,7 @@ int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);

48
include/linux/mlx5/fs_helpers.h
View File

@@ -38,46 +38,6 @@
#define MLX5_FS_IPV4_VERSION 4
#define MLX5_FS_IPV6_VERSION 6
static inline bool mlx5_fs_is_ipsec_flow(const u32 *match_c)
{
void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
misc_parameters);
return MLX5_GET(fte_match_set_misc, misc_params_c, outer_esp_spi);
}
static inline bool _mlx5_fs_is_outer_ipproto_flow(const u32 *match_c,
const u32 *match_v, u8 match)
{
const void *headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
outer_headers);
const void *headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
outer_headers);
return MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_protocol) == 0xff &&
MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol) == match;
}
static inline bool mlx5_fs_is_outer_tcp_flow(const u32 *match_c,
const u32 *match_v)
{
return _mlx5_fs_is_outer_ipproto_flow(match_c, match_v, IPPROTO_TCP);
}
static inline bool mlx5_fs_is_outer_udp_flow(const u32 *match_c,
const u32 *match_v)
{
return _mlx5_fs_is_outer_ipproto_flow(match_c, match_v, IPPROTO_UDP);
}
static inline bool mlx5_fs_is_vxlan_flow(const u32 *match_c)
{
void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
misc_parameters);
return MLX5_GET(fte_match_set_misc, misc_params_c, vxlan_vni);
}
static inline bool _mlx5_fs_is_outer_ipv_flow(struct mlx5_core_dev *mdev,
const u32 *match_c,
const u32 *match_v, int version)
@@ -131,12 +91,4 @@ mlx5_fs_is_outer_ipv6_flow(struct mlx5_core_dev *mdev, const u32 *match_c,
MLX5_FS_IPV6_VERSION);
}
static inline bool mlx5_fs_is_outer_ipsec_flow(const u32 *match_c)
{
void *misc_params_c =
MLX5_ADDR_OF(fte_match_param, match_c, misc_parameters);
return MLX5_GET(fte_match_set_misc, misc_params_c, outer_esp_spi);
}
#endif

126
include/linux/mlx5/mlx5_ifc.h
View File

@@ -68,6 +68,7 @@ enum {
MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION = 0x25,
};
enum {
@@ -90,6 +91,7 @@ enum {
MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
MLX5_OBJ_TYPE_MKEY = 0xff01,
MLX5_OBJ_TYPE_QP = 0xff02,
MLX5_OBJ_TYPE_PSV = 0xff03,
@@ -482,6 +484,22 @@ struct mlx5_ifc_odp_per_transport_service_cap_bits {
u8 reserved_at_6[0x1a];
};
struct mlx5_ifc_ipv4_layout_bits {
u8 reserved_at_0[0x60];
u8 ipv4[0x20];
};
struct mlx5_ifc_ipv6_layout_bits {
u8 ipv6[16][0x8];
};
union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
u8 reserved_at_0[0x80];
};
struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
u8 smac_47_16[0x20];
@@ -823,7 +841,9 @@ struct mlx5_ifc_flow_table_nic_cap_bits {
struct mlx5_ifc_port_selection_cap_bits {
u8 reserved_at_0[0x10];
u8 port_select_flow_table[0x1];
u8 reserved_at_11[0xf];
u8 reserved_at_11[0x1];
u8 port_select_flow_table_bypass[0x1];
u8 reserved_at_13[0xd];
u8 reserved_at_20[0x1e0];
@@ -1761,7 +1781,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 max_geneve_tlv_options[0x8];
u8 reserved_at_568[0x3];
u8 max_geneve_tlv_option_data_len[0x5];
u8 reserved_at_570[0x10];
u8 reserved_at_570[0x9];
u8 adv_virtualization[0x1];
u8 reserved_at_57a[0x6];
u8 reserved_at_580[0xb];
u8 log_max_dci_stream_channels[0x5];
@@ -9825,7 +9847,9 @@ struct mlx5_ifc_pcam_reg_bits {
struct mlx5_ifc_mcam_enhanced_features_bits {
u8 reserved_at_0[0x5d];
u8 mcia_32dwords[0x1];
u8 reserved_at_5e[0xc];
u8 out_pulse_duration_ns[0x1];
u8 npps_period[0x1];
u8 reserved_at_60[0xa];
u8 reset_state[0x1];
u8 ptpcyc2realtime_modify[0x1];
u8 reserved_at_6c[0x2];
@@ -10325,7 +10349,12 @@ struct mlx5_ifc_mtpps_reg_bits {
u8 reserved_at_18[0x4];
u8 cap_max_num_of_pps_out_pins[0x4];
u8 reserved_at_20[0x24];
u8 reserved_at_20[0x13];
u8 cap_log_min_npps_period[0x5];
u8 reserved_at_38[0x3];
u8 cap_log_min_out_pulse_duration_ns[0x5];
u8 reserved_at_40[0x4];
u8 cap_pin_3_mode[0x4];
u8 reserved_at_48[0x4];
u8 cap_pin_2_mode[0x4];
@@ -10344,7 +10373,9 @@ struct mlx5_ifc_mtpps_reg_bits {
u8 cap_pin_4_mode[0x4];
u8 field_select[0x20];
u8 reserved_at_a0[0x60];
u8 reserved_at_a0[0x20];
u8 npps_period[0x40];
u8 enable[0x1];
u8 reserved_at_101[0xb];
@@ -10353,7 +10384,8 @@ struct mlx5_ifc_mtpps_reg_bits {
u8 pin_mode[0x4];
u8 pin[0x8];
u8 reserved_at_120[0x20];
u8 reserved_at_120[0x2];
u8 out_pulse_duration_ns[0x1e];
u8 time_stamp[0x40];
@@ -10956,7 +10988,9 @@ struct mlx5_ifc_lagc_bits {
u8 reserved_at_18[0x5];
u8 lag_state[0x3];
u8 reserved_at_20[0x14];
u8 reserved_at_20[0xc];
u8 active_port[0x4];
u8 reserved_at_30[0x4];
u8 tx_remap_affinity_2[0x4];
u8 reserved_at_38[0x4];
u8 tx_remap_affinity_1[0x4];
@@ -11946,4 +11980,82 @@ struct mlx5_ifc_load_vhca_state_out_bits {
u8 reserved_at_40[0x40];
};
struct mlx5_ifc_adv_virtualization_cap_bits {
u8 reserved_at_0[0x3];
u8 pg_track_log_max_num[0x5];
u8 pg_track_max_num_range[0x8];
u8 pg_track_log_min_addr_space[0x8];
u8 pg_track_log_max_addr_space[0x8];
u8 reserved_at_20[0x3];
u8 pg_track_log_min_msg_size[0x5];
u8 reserved_at_28[0x3];
u8 pg_track_log_max_msg_size[0x5];
u8 reserved_at_30[0x3];
u8 pg_track_log_min_page_size[0x5];
u8 reserved_at_38[0x3];
u8 pg_track_log_max_page_size[0x5];
u8 reserved_at_40[0x7c0];
};
struct mlx5_ifc_page_track_report_entry_bits {
u8 dirty_address_high[0x20];
u8 dirty_address_low[0x20];
};
enum {
MLX5_PAGE_TRACK_STATE_TRACKING,
MLX5_PAGE_TRACK_STATE_REPORTING,
MLX5_PAGE_TRACK_STATE_ERROR,
};
struct mlx5_ifc_page_track_range_bits {
u8 start_address[0x40];
u8 length[0x40];
};
struct mlx5_ifc_page_track_bits {
u8 modify_field_select[0x40];
u8 reserved_at_40[0x10];
u8 vhca_id[0x10];
u8 reserved_at_60[0x20];
u8 state[0x4];
u8 track_type[0x4];
u8 log_addr_space_size[0x8];
u8 reserved_at_90[0x3];
u8 log_page_size[0x5];
u8 reserved_at_98[0x3];
u8 log_msg_size[0x5];
u8 reserved_at_a0[0x8];
u8 reporting_qpn[0x18];
u8 reserved_at_c0[0x18];
u8 num_ranges[0x8];
u8 reserved_at_e0[0x20];
u8 range_start_address[0x40];
u8 length[0x40];
struct mlx5_ifc_page_track_range_bits track_range[0];
};
struct mlx5_ifc_create_page_track_obj_in_bits {
struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
struct mlx5_ifc_page_track_bits obj_context;
};
struct mlx5_ifc_modify_page_track_obj_in_bits {
struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
struct mlx5_ifc_page_track_bits obj_context;
};
#endif /* MLX5_IFC_H */

24
include/linux/mlx5/mlx5_ifc_fpga.h
View File

@@ -32,30 +32,6 @@
#ifndef MLX5_IFC_FPGA_H
#define MLX5_IFC_FPGA_H
struct mlx5_ifc_ipv4_layout_bits {
u8 reserved_at_0[0x60];
u8 ipv4[0x20];
};
struct mlx5_ifc_ipv6_layout_bits {
u8 ipv6[16][0x8];
};
union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
u8 reserved_at_0[0x80];
};
enum {
MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX = 0x2c9,
};
enum {
MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC = 0x2,
};
struct mlx5_ifc_fpga_shell_caps_bits {
u8 max_num_qps[0x10];
u8 reserved_at_10[0x8];