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Merge tag 'v3.19-rc4' into next

Browse Source 
Merge with mainline to bring in the latest thermal and other changes.
This commit is contained in:
Dmitry Torokhov
2015-01-15 09:46:14 -08:00
parent 0c3e99437a eaa27f34e9
commit 0c49cd295d
15497 changed files with 878449 additions and 621464 deletions
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14
include/acpi/acbuffer.h
View File

@@ -111,7 +111,9 @@ struct acpi_gtm_info {
struct acpi_pld_info {
u8 revision;
u8 ignore_color;
u32 color;
u8 red;
u8 green;
u8 blue;
u16 width;
u16 height;
u8 user_visible;
@@ -155,8 +157,14 @@ struct acpi_pld_info {
#define ACPI_PLD_GET_IGNORE_COLOR(dword) ACPI_GET_BITS (dword, 7, ACPI_1BIT_MASK)
#define ACPI_PLD_SET_IGNORE_COLOR(dword,value) ACPI_SET_BITS (dword, 7, ACPI_1BIT_MASK, value) /* Offset 7, Len 1 */
#define ACPI_PLD_GET_COLOR(dword) ACPI_GET_BITS (dword, 8, ACPI_24BIT_MASK)
#define ACPI_PLD_SET_COLOR(dword,value) ACPI_SET_BITS (dword, 8, ACPI_24BIT_MASK, value) /* Offset 8, Len 24 */
#define ACPI_PLD_GET_RED(dword) ACPI_GET_BITS (dword, 8, ACPI_8BIT_MASK)
#define ACPI_PLD_SET_RED(dword,value) ACPI_SET_BITS (dword, 8, ACPI_8BIT_MASK, value) /* Offset 8, Len 8 */
#define ACPI_PLD_GET_GREEN(dword) ACPI_GET_BITS (dword, 16, ACPI_8BIT_MASK)
#define ACPI_PLD_SET_GREEN(dword,value) ACPI_SET_BITS (dword, 16, ACPI_8BIT_MASK, value) /* Offset 16, Len 8 */
#define ACPI_PLD_GET_BLUE(dword) ACPI_GET_BITS (dword, 24, ACPI_8BIT_MASK)
#define ACPI_PLD_SET_BLUE(dword,value) ACPI_SET_BITS (dword, 24, ACPI_8BIT_MASK, value) /* Offset 24, Len 8 */
/* Second 32-bit dword, bits 33:63 */

5
include/acpi/acnames.h
View File

@@ -52,6 +52,7 @@
#define METHOD_NAME__CBA "_CBA"
#define METHOD_NAME__CID "_CID"
#define METHOD_NAME__CRS "_CRS"
#define METHOD_NAME__DDN "_DDN"
#define METHOD_NAME__HID "_HID"
#define METHOD_NAME__INI "_INI"
#define METHOD_NAME__PLD "_PLD"
@@ -59,6 +60,10 @@
#define METHOD_NAME__PRS "_PRS"
#define METHOD_NAME__PRT "_PRT"
#define METHOD_NAME__PRW "_PRW"
#define METHOD_NAME__PS0 "_PS0"
#define METHOD_NAME__PS1 "_PS1"
#define METHOD_NAME__PS2 "_PS2"
#define METHOD_NAME__PS3 "_PS3"
#define METHOD_NAME__REG "_REG"
#define METHOD_NAME__SB_ "_SB_"
#define METHOD_NAME__SEG "_SEG"

37
include/acpi/acpi_bus.h
View File

@@ -27,6 +27,7 @@
#define __ACPI_BUS_H__
#include <linux/device.h>
#include <linux/property.h>
/* TBD: Make dynamic */
#define ACPI_MAX_HANDLES 10
@@ -312,6 +313,7 @@ struct acpi_device_wakeup_flags {
u8 valid:1; /* Can successfully enable wakeup? */
u8 run_wake:1; /* Run-Wake GPE devices */
u8 notifier_present:1; /* Wake-up notify handler has been installed */
u8 enabled:1; /* Enabled for wakeup */
};
struct acpi_device_wakeup_context {
@@ -337,10 +339,20 @@ struct acpi_device_physical_node {
bool put_online:1;
};
/* ACPI Device Specific Data (_DSD) */
struct acpi_device_data {
const union acpi_object *pointer;
const union acpi_object *properties;
const union acpi_object *of_compatible;
};
struct acpi_gpio_mapping;
/* Device */
struct acpi_device {
int device_type;
acpi_handle handle; /* no handle for fixed hardware */
struct fwnode_handle fwnode;
struct acpi_device *parent;
struct list_head children;
struct list_head node;
@@ -353,17 +365,35 @@ struct acpi_device {
struct acpi_device_wakeup wakeup;
struct acpi_device_perf performance;
struct acpi_device_dir dir;
struct acpi_device_data data;
struct acpi_scan_handler *handler;
struct acpi_hotplug_context *hp;
struct acpi_driver *driver;
const struct acpi_gpio_mapping *driver_gpios;
void *driver_data;
struct device dev;
unsigned int physical_node_count;
unsigned int dep_unmet;
struct list_head physical_node_list;
struct mutex physical_node_lock;
void (*remove)(struct acpi_device *);
};
static inline bool is_acpi_node(struct fwnode_handle *fwnode)
{
return fwnode && fwnode->type == FWNODE_ACPI;
}
static inline struct acpi_device *acpi_node(struct fwnode_handle *fwnode)
{
return fwnode ? container_of(fwnode, struct acpi_device, fwnode) : NULL;
}
static inline struct fwnode_handle *acpi_fwnode_handle(struct acpi_device *adev)
{
return &adev->fwnode;
}
static inline void *acpi_driver_data(struct acpi_device *d)
{
return d->driver_data;
@@ -433,6 +463,7 @@ int acpi_device_set_power(struct acpi_device *device, int state);
int acpi_bus_init_power(struct acpi_device *device);
int acpi_device_fix_up_power(struct acpi_device *device);
int acpi_bus_update_power(acpi_handle handle, int *state_p);
int acpi_device_update_power(struct acpi_device *device, int *state_p);
bool acpi_bus_power_manageable(acpi_handle handle);
#ifdef CONFIG_PM
@@ -515,6 +546,7 @@ acpi_status acpi_add_pm_notifier(struct acpi_device *adev, struct device *dev,
void (*work_func)(struct work_struct *work));
acpi_status acpi_remove_pm_notifier(struct acpi_device *adev);
int acpi_pm_device_sleep_state(struct device *, int *, int);
int acpi_pm_device_run_wake(struct device *, bool);
#else
static inline acpi_status acpi_add_pm_notifier(struct acpi_device *adev,
struct device *dev,
@@ -534,11 +566,6 @@ static inline int acpi_pm_device_sleep_state(struct device *d, int *p, int m)
return (m >= ACPI_STATE_D0 && m <= ACPI_STATE_D3_COLD) ?
m : ACPI_STATE_D0;
}
#endif
#ifdef CONFIG_PM_RUNTIME
int acpi_pm_device_run_wake(struct device *, bool);
#else
static inline int acpi_pm_device_run_wake(struct device *dev, bool enable)
{
return -ENODEV;

3
include/acpi/acpixf.h
View File

@@ -46,7 +46,7 @@
/* Current ACPICA subsystem version in YYYYMMDD format */
#define ACPI_CA_VERSION 0x20140724
#define ACPI_CA_VERSION 0x20141107
#include <acpi/acconfig.h>
#include <acpi/actypes.h>
@@ -692,6 +692,7 @@ ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status
*event_status))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_disable_all_gpes(void))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_enable_all_runtime_gpes(void))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status acpi_enable_all_wakeup_gpes(void))
ACPI_HW_DEPENDENT_RETURN_STATUS(acpi_status
acpi_get_gpe_device(u32 gpe_index,

19
include/acpi/actbl1.h
View File

@@ -952,7 +952,8 @@ enum acpi_srat_type {
ACPI_SRAT_TYPE_CPU_AFFINITY = 0,
ACPI_SRAT_TYPE_MEMORY_AFFINITY = 1,
ACPI_SRAT_TYPE_X2APIC_CPU_AFFINITY = 2,
ACPI_SRAT_TYPE_RESERVED = 3 /* 3 and greater are reserved */
ACPI_SRAT_TYPE_GICC_AFFINITY = 3,
ACPI_SRAT_TYPE_RESERVED = 4 /* 4 and greater are reserved */
};
/*
@@ -968,7 +969,7 @@ struct acpi_srat_cpu_affinity {
u32 flags;
u8 local_sapic_eid;
u8 proximity_domain_hi[3];
u32 reserved; /* Reserved, must be zero */
u32 clock_domain;
};
/* Flags */
@@ -1010,6 +1011,20 @@ struct acpi_srat_x2apic_cpu_affinity {
#define ACPI_SRAT_CPU_ENABLED (1) /* 00: Use affinity structure */
/* 3: GICC Affinity (ACPI 5.1) */
struct acpi_srat_gicc_affinity {
struct acpi_subtable_header header;
u32 proximity_domain;
u32 acpi_processor_uid;
u32 flags;
u32 clock_domain;
};
/* Flags for struct acpi_srat_gicc_affinity */
#define ACPI_SRAT_GICC_ENABLED (1) /* 00: Use affinity structure */
/* Reset to default packing */
#pragma pack()

9
include/acpi/actbl3.h
View File

@@ -310,10 +310,15 @@ struct acpi_gtdt_timer_entry {
u32 common_flags;
};
/* Flag Definitions: timer_flags and virtual_timer_flags above */
#define ACPI_GTDT_GT_IRQ_MODE (1)
#define ACPI_GTDT_GT_IRQ_POLARITY (1<<1)
/* Flag Definitions: common_flags above */
#define ACPI_GTDT_GT_IS_SECURE_TIMER (1)
#define ACPI_GTDT_GT_ALWAYS_ON (1<<1)
#define ACPI_GTDT_GT_IS_SECURE_TIMER (1)
#define ACPI_GTDT_GT_ALWAYS_ON (1<<1)
/* 1: SBSA Generic Watchdog Structure */

8
include/acpi/actypes.h
View File

@@ -721,7 +721,7 @@ typedef u32 acpi_event_type;
* | | | +--- Enabled for wake?
* | | +----- Set?
* | +------- Has a handler?
* +----------- <Reserved>
* +------------- <Reserved>
*/
typedef u32 acpi_event_status;
@@ -729,13 +729,17 @@ typedef u32 acpi_event_status;
#define ACPI_EVENT_FLAG_ENABLED (acpi_event_status) 0x01
#define ACPI_EVENT_FLAG_WAKE_ENABLED (acpi_event_status) 0x02
#define ACPI_EVENT_FLAG_SET (acpi_event_status) 0x04
#define ACPI_EVENT_FLAG_HANDLE (acpi_event_status) 0x08
#define ACPI_EVENT_FLAG_HAS_HANDLER (acpi_event_status) 0x08
/* Actions for acpi_set_gpe, acpi_gpe_wakeup, acpi_hw_low_set_gpe */
#define ACPI_GPE_ENABLE 0
#define ACPI_GPE_DISABLE 1
#define ACPI_GPE_CONDITIONAL_ENABLE 2
#define ACPI_GPE_SAVE_MASK 4
#define ACPI_GPE_ENABLE_SAVE (ACPI_GPE_ENABLE | ACPI_GPE_SAVE_MASK)
#define ACPI_GPE_DISABLE_SAVE (ACPI_GPE_DISABLE | ACPI_GPE_SAVE_MASK)
/*
* GPE info flags - Per GPE

15
include/acpi/processor.h
View File

@@ -67,9 +67,6 @@ struct acpi_processor_cx {
};
struct acpi_processor_power {
struct acpi_processor_cx *state;
unsigned long bm_check_timestamp;
u32 default_state;
int count;
struct acpi_processor_cx states[ACPI_PROCESSOR_MAX_POWER];
int timer_broadcast_on_state;
@@ -199,8 +196,8 @@ struct acpi_processor_flags {
struct acpi_processor {
acpi_handle handle;
u32 acpi_id;
u32 apic_id;
u32 id;
u32 phys_id; /* CPU hardware ID such as APIC ID for x86 */
u32 id; /* CPU logical ID allocated by OS */
u32 pblk;
int performance_platform_limit;
int throttling_platform_limit;
@@ -313,11 +310,13 @@ static inline int acpi_processor_get_bios_limit(int cpu, unsigned int *limit)
#endif /* CONFIG_CPU_FREQ */
/* in processor_core.c */
void acpi_processor_set_pdc(acpi_handle handle);
int acpi_get_apicid(acpi_handle, int type, u32 acpi_id);
int acpi_map_cpuid(int apic_id, u32 acpi_id);
int acpi_get_phys_id(acpi_handle, int type, u32 acpi_id);
int acpi_map_cpuid(int phys_id, u32 acpi_id);
int acpi_get_cpuid(acpi_handle, int type, u32 acpi_id);
/* in processor_pdc.c */
void acpi_processor_set_pdc(acpi_handle handle);
/* in processor_throttling.c */
int acpi_processor_tstate_has_changed(struct acpi_processor *pr);
int acpi_processor_get_throttling_info(struct acpi_processor *pr);

194
include/asm-generic/atomic.h
View File

@@ -18,14 +18,100 @@
#include <asm/cmpxchg.h>
#include <asm/barrier.h>
/*
* atomic_$op() - $op integer to atomic variable
* @i: integer value to $op
* @v: pointer to the atomic variable
*
* Atomically $ops @i to @v. Does not strictly guarantee a memory-barrier, use
* smp_mb__{before,after}_atomic().
*/
/*
* atomic_$op_return() - $op interer to atomic variable and returns the result
* @i: integer value to $op
* @v: pointer to the atomic variable
*
* Atomically $ops @i to @v. Does imply a full memory barrier.
*/
#ifdef CONFIG_SMP
/* Force people to define core atomics */
# if !defined(atomic_add_return) || !defined(atomic_sub_return) || \
!defined(atomic_clear_mask) || !defined(atomic_set_mask)
# error "SMP requires a little arch-specific magic"
# endif
/* we can build all atomic primitives from cmpxchg */
#define ATOMIC_OP(op, c_op) \
static inline void atomic_##op(int i, atomic_t *v) \
{ \
int c, old; \
\
c = v->counter; \
while ((old = cmpxchg(&v->counter, c, c c_op i)) != c) \
c = old; \
}
#define ATOMIC_OP_RETURN(op, c_op) \
static inline int atomic_##op##_return(int i, atomic_t *v) \
{ \
int c, old; \
\
c = v->counter; \
while ((old = cmpxchg(&v->counter, c, c c_op i)) != c) \
c = old; \
\
return c c_op i; \
}
#else
#include <linux/irqflags.h>
#define ATOMIC_OP(op, c_op) \
static inline void atomic_##op(int i, atomic_t *v) \
{ \
unsigned long flags; \
\
raw_local_irq_save(flags); \
v->counter = v->counter c_op i; \
raw_local_irq_restore(flags); \
}
#define ATOMIC_OP_RETURN(op, c_op) \
static inline int atomic_##op##_return(int i, atomic_t *v) \
{ \
unsigned long flags; \
int ret; \
\
raw_local_irq_save(flags); \
ret = (v->counter = v->counter c_op i); \
raw_local_irq_restore(flags); \
\
return ret; \
}
#endif /* CONFIG_SMP */
#ifndef atomic_add_return
ATOMIC_OP_RETURN(add, +)
#endif
#ifndef atomic_sub_return
ATOMIC_OP_RETURN(sub, -)
#endif
#ifndef atomic_clear_mask
ATOMIC_OP(and, &)
#define atomic_clear_mask(i, v) atomic_and(~(i), (v))
#endif
#ifndef atomic_set_mask
#define CONFIG_ARCH_HAS_ATOMIC_OR
ATOMIC_OP(or, |)
#define atomic_set_mask(i, v) atomic_or((i), (v))
#endif
#undef ATOMIC_OP_RETURN
#undef ATOMIC_OP
/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc..
@@ -33,8 +119,6 @@
#define ATOMIC_INIT(i) { (i) }
#ifdef __KERNEL__
/**
* atomic_read - read atomic variable
* @v: pointer of type atomic_t
@@ -42,7 +126,7 @@
* Atomically reads the value of @v.
*/
#ifndef atomic_read
#define atomic_read(v) (*(volatile int *)&(v)->counter)
#define atomic_read(v) ACCESS_ONCE((v)->counter)
#endif
/**
@@ -56,52 +140,6 @@
#include <linux/irqflags.h>
/**
* atomic_add_return - add integer to atomic variable
* @i: integer value to add
* @v: pointer of type atomic_t
*
* Atomically adds @i to @v and returns the result
*/
#ifndef atomic_add_return
static inline int atomic_add_return(int i, atomic_t *v)
{
unsigned long flags;
int temp;
raw_local_irq_save(flags); /* Don't trace it in an irqsoff handler */
temp = v->counter;
temp += i;
v->counter = temp;
raw_local_irq_restore(flags);
return temp;
}
#endif
/**
* atomic_sub_return - subtract integer from atomic variable
* @i: integer value to subtract
* @v: pointer of type atomic_t
*
* Atomically subtracts @i from @v and returns the result
*/
#ifndef atomic_sub_return
static inline int atomic_sub_return(int i, atomic_t *v)
{
unsigned long flags;
int temp;
raw_local_irq_save(flags); /* Don't trace it in an irqsoff handler */
temp = v->counter;
temp -= i;
v->counter = temp;
raw_local_irq_restore(flags);
return temp;
}
#endif
static inline int atomic_add_negative(int i, atomic_t *v)
{
return atomic_add_return(i, v) < 0;
@@ -139,49 +177,11 @@ static inline void atomic_dec(atomic_t *v)
static inline int __atomic_add_unless(atomic_t *v, int a, int u)
{
int c, old;
c = atomic_read(v);
while (c != u && (old = atomic_cmpxchg(v, c, c + a)) != c)
c = old;
return c;
int c, old;
c = atomic_read(v);
while (c != u && (old = atomic_cmpxchg(v, c, c + a)) != c)
c = old;
return c;
}
/**
* atomic_clear_mask - Atomically clear bits in atomic variable
* @mask: Mask of the bits to be cleared
* @v: pointer of type atomic_t
*
* Atomically clears the bits set in @mask from @v
*/
#ifndef atomic_clear_mask
static inline void atomic_clear_mask(unsigned long mask, atomic_t *v)
{
unsigned long flags;
mask = ~mask;
raw_local_irq_save(flags); /* Don't trace it in a irqsoff handler */
v->counter &= mask;
raw_local_irq_restore(flags);
}
#endif
/**
* atomic_set_mask - Atomically set bits in atomic variable
* @mask: Mask of the bits to be set
* @v: pointer of type atomic_t
*
* Atomically sets the bits set in @mask in @v
*/
#ifndef atomic_set_mask
static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
{
unsigned long flags;
raw_local_irq_save(flags); /* Don't trace it in a irqsoff handler */
v->counter |= mask;
raw_local_irq_restore(flags);
}
#endif
#endif /* __KERNEL__ */
#endif /* __ASM_GENERIC_ATOMIC_H */

20
include/asm-generic/atomic64.h
View File

@@ -20,10 +20,22 @@ typedef struct {
extern long long atomic64_read(const atomic64_t *v);
extern void atomic64_set(atomic64_t *v, long long i);
extern void atomic64_add(long long a, atomic64_t *v);
extern long long atomic64_add_return(long long a, atomic64_t *v);
extern void atomic64_sub(long long a, atomic64_t *v);
extern long long atomic64_sub_return(long long a, atomic64_t *v);
#define ATOMIC64_OP(op) \
extern void atomic64_##op(long long a, atomic64_t *v);
#define ATOMIC64_OP_RETURN(op) \
extern long long atomic64_##op##_return(long long a, atomic64_t *v);
#define ATOMIC64_OPS(op) ATOMIC64_OP(op) ATOMIC64_OP_RETURN(op)
ATOMIC64_OPS(add)
ATOMIC64_OPS(sub)
#undef ATOMIC64_OPS
#undef ATOMIC64_OP_RETURN
#undef ATOMIC64_OP
extern long long atomic64_dec_if_positive(atomic64_t *v);
extern long long atomic64_cmpxchg(atomic64_t *v, long long o, long long n);
extern long long atomic64_xchg(atomic64_t *v, long long new);

8
include/asm-generic/barrier.h
View File

@@ -42,6 +42,14 @@
#define wmb() mb()
#endif
#ifndef dma_rmb
#define dma_rmb() rmb()
#endif
#ifndef dma_wmb
#define dma_wmb() wmb()
#endif
#ifndef read_barrier_depends
#define read_barrier_depends() do { } while (0)
#endif

2
include/asm-generic/clkdev.h
View File

@@ -15,10 +15,12 @@
#include <linux/slab.h>
#ifndef CONFIG_COMMON_CLK
struct clk;
static inline int __clk_get(struct clk *clk) { return 1; }
static inline void __clk_put(struct clk *clk) { }
#endif
static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
{

2
include/asm-generic/cputime_jiffies.h
View File

@@ -3,6 +3,8 @@
typedef unsigned long __nocast cputime_t;
#define cmpxchg_cputime(ptr, old, new) cmpxchg(ptr, old, new)
#define cputime_one_jiffy jiffies_to_cputime(1)
#define cputime_to_jiffies(__ct) (__force unsigned long)(__ct)
#define cputime_to_scaled(__ct) (__ct)

2
include/asm-generic/cputime_nsecs.h
View File

@@ -21,6 +21,8 @@
typedef u64 __nocast cputime_t;
typedef u64 __nocast cputime64_t;
#define cmpxchg_cputime(ptr, old, new) cmpxchg64(ptr, old, new)
#define cputime_one_jiffy jiffies_to_cputime(1)
#define cputime_div(__ct, divisor) div_u64((__force u64)__ct, divisor)

9
include/asm-generic/dma-contiguous.h Normal file
View File

@@ -0,0 +1,9 @@
#ifndef _ASM_GENERIC_DMA_CONTIGUOUS_H
#define _ASM_GENERIC_DMA_CONTIGUOUS_H
#include <linux/types.h>
static inline void
dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) { }
#endif

17
include/asm-generic/dma-mapping-common.h
View File

@@ -179,6 +179,15 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
extern int dma_common_mmap(struct device *dev, struct vm_area_struct *vma,
void *cpu_addr, dma_addr_t dma_addr, size_t size);
void *dma_common_contiguous_remap(struct page *page, size_t size,
unsigned long vm_flags,
pgprot_t prot, const void *caller);
void *dma_common_pages_remap(struct page **pages, size_t size,
unsigned long vm_flags, pgprot_t prot,
const void *caller);
void dma_common_free_remap(void *cpu_addr, size_t size, unsigned long vm_flags);
/**
* dma_mmap_attrs - map a coherent DMA allocation into user space
* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
@@ -205,14 +214,6 @@ dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma, void *cpu_addr,
#define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, NULL)
static inline int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma,
void *cpu_addr, dma_addr_t dma_addr, size_t size)
{
DEFINE_DMA_ATTRS(attrs);
dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, &attrs);
}
int
dma_common_get_sgtable(struct device *dev, struct sg_table *sgt,
void *cpu_addr, dma_addr_t dma_addr, size_t size);

114
include/asm-generic/futex.h
View File

@@ -5,6 +5,119 @@
#include <linux/uaccess.h>
#include <asm/errno.h>
#ifndef CONFIG_SMP
/*
* The following implementation only for uniprocessor machines.
* For UP, it's relies on the fact that pagefault_disable() also disables
* preemption to ensure mutual exclusion.
*
*/
/**
* futex_atomic_op_inuser() - Atomic arithmetic operation with constant
* argument and comparison of the previous
* futex value with another constant.
*
* @encoded_op: encoded operation to execute
* @uaddr: pointer to user space address
*
* Return:
* 0 - On success
* <0 - On error
*/
static inline int
futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
{
int op = (encoded_op >> 28) & 7;
int cmp = (encoded_op >> 24) & 15;
int oparg = (encoded_op << 8) >> 20;
int cmparg = (encoded_op << 20) >> 20;
int oldval, ret;
u32 tmp;
if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
oparg = 1 << oparg;
pagefault_disable();
ret = -EFAULT;
if (unlikely(get_user(oldval, uaddr) != 0))
goto out_pagefault_enable;
ret = 0;
tmp = oldval;
switch (op) {
case FUTEX_OP_SET:
tmp = oparg;
break;
case FUTEX_OP_ADD:
tmp += oparg;
break;
case FUTEX_OP_OR:
tmp |= oparg;
break;
case FUTEX_OP_ANDN:
tmp &= ~oparg;
break;
case FUTEX_OP_XOR:
tmp ^= oparg;
break;
default:
ret = -ENOSYS;
}
if (ret == 0 && unlikely(put_user(tmp, uaddr) != 0))
ret = -EFAULT;
out_pagefault_enable:
pagefault_enable();
if (ret == 0) {
switch (cmp) {
case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
default: ret = -ENOSYS;
}
}
return ret;
}
/**
* futex_atomic_cmpxchg_inatomic() - Compare and exchange the content of the
* uaddr with newval if the current value is
* oldval.
* @uval: pointer to store content of @uaddr
* @uaddr: pointer to user space address
* @oldval: old value
* @newval: new value to store to @uaddr
*
* Return:
* 0 - On success
* <0 - On error
*/
static inline int
futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
u32 oldval, u32 newval)
{
u32 val;
if (unlikely(get_user(val, uaddr) != 0))
return -EFAULT;
if (val == oldval && unlikely(put_user(newval, uaddr) != 0))
return -EFAULT;
*uval = val;
return 0;
}
#else
static inline int
futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
{
@@ -54,4 +167,5 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
return -ENOSYS;
}
#endif /* CONFIG_SMP */
#endif

2
include/asm-generic/gpio.h
View File

@@ -27,7 +27,7 @@
*/
#ifndef ARCH_NR_GPIOS
#define ARCH_NR_GPIOS 256
#define ARCH_NR_GPIOS 512
#endif
/*

9
include/asm-generic/hash.h
View File

@@ -1,9 +0,0 @@
#ifndef __ASM_GENERIC_HASH_H
#define __ASM_GENERIC_HASH_H
struct fast_hash_ops;
static inline void setup_arch_fast_hash(struct fast_hash_ops *ops)
{
}
#endif /* __ASM_GENERIC_HASH_H */

783
include/asm-generic/io.h
View File

@@ -12,6 +12,7 @@
#define __ASM_GENERIC_IO_H
#include <asm/page.h> /* I/O is all done through memory accesses */
#include <linux/string.h> /* for memset() and memcpy() */
#include <linux/types.h>
#ifdef CONFIG_GENERIC_IOMAP
@@ -24,260 +25,691 @@
#define mmiowb() do {} while (0)
#endif
/*****************************************************************************/
/*
* readX/writeX() are used to access memory mapped devices. On some
* architectures the memory mapped IO stuff needs to be accessed
* differently. On the simple architectures, we just read/write the
* memory location directly.
* __raw_{read,write}{b,w,l,q}() access memory in native endianness.
*
* On some architectures memory mapped IO needs to be accessed differently.
* On the simple architectures, we just read/write the memory location
* directly.
*/
#ifndef __raw_readb
#define __raw_readb __raw_readb
static inline u8 __raw_readb(const volatile void __iomem *addr)
{
return *(const volatile u8 __force *) addr;
return *(const volatile u8 __force *)addr;
}
#endif
#ifndef __raw_readw
#define __raw_readw __raw_readw
static inline u16 __raw_readw(const volatile void __iomem *addr)
{
return *(const volatile u16 __force *) addr;
return *(const volatile u16 __force *)addr;
}
#endif
#ifndef __raw_readl
#define __raw_readl __raw_readl
static inline u32 __raw_readl(const volatile void __iomem *addr)
{
return *(const volatile u32 __force *) addr;
return *(const volatile u32 __force *)addr;
}
#endif
#define readb __raw_readb
#ifdef CONFIG_64BIT
#ifndef __raw_readq
#define __raw_readq __raw_readq
static inline u64 __raw_readq(const volatile void __iomem *addr)
{
return *(const volatile u64 __force *)addr;
}
#endif
#endif /* CONFIG_64BIT */
#ifndef __raw_writeb
#define __raw_writeb __raw_writeb
static inline void __raw_writeb(u8 value, volatile void __iomem *addr)
{
*(volatile u8 __force *)addr = value;
}
#endif
#ifndef __raw_writew
#define __raw_writew __raw_writew
static inline void __raw_writew(u16 value, volatile void __iomem *addr)
{
*(volatile u16 __force *)addr = value;
}
#endif
#ifndef __raw_writel
#define __raw_writel __raw_writel
static inline void __raw_writel(u32 value, volatile void __iomem *addr)
{
*(volatile u32 __force *)addr = value;
}
#endif
#ifdef CONFIG_64BIT
#ifndef __raw_writeq
#define __raw_writeq __raw_writeq
static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
{
*(volatile u64 __force *)addr = value;
}
#endif
#endif /* CONFIG_64BIT */
/*
* {read,write}{b,w,l,q}() access little endian memory and return result in
* native endianness.
*/
#ifndef readb
#define readb readb
static inline u8 readb(const volatile void __iomem *addr)
{
return __raw_readb(addr);
}
#endif
#ifndef readw
#define readw readw
static inline u16 readw(const volatile void __iomem *addr)
{
return __le16_to_cpu(__raw_readw(addr));
}
#endif
#ifndef readl
#define readl readl
static inline u32 readl(const volatile void __iomem *addr)
{
return __le32_to_cpu(__raw_readl(addr));
}
#ifndef __raw_writeb
static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
{
*(volatile u8 __force *) addr = b;
}
#endif
#ifndef __raw_writew
static inline void __raw_writew(u16 b, volatile void __iomem *addr)
{
*(volatile u16 __force *) addr = b;
}
#endif
#ifndef __raw_writel
static inline void __raw_writel(u32 b, volatile void __iomem *addr)
{
*(volatile u32 __force *) addr = b;
}
#endif
#define writeb __raw_writeb
#define writew(b,addr) __raw_writew(__cpu_to_le16(b),addr)
#define writel(b,addr) __raw_writel(__cpu_to_le32(b),addr)
#ifdef CONFIG_64BIT
#ifndef __raw_readq
static inline u64 __raw_readq(const volatile void __iomem *addr)
{
return *(const volatile u64 __force *) addr;
}
#endif
#ifndef readq
#define readq readq
static inline u64 readq(const volatile void __iomem *addr)
{
return __le64_to_cpu(__raw_readq(addr));
}
#ifndef __raw_writeq
static inline void __raw_writeq(u64 b, volatile void __iomem *addr)
{
*(volatile u64 __force *) addr = b;
}
#endif
#define writeq(b, addr) __raw_writeq(__cpu_to_le64(b), addr)
#endif /* CONFIG_64BIT */
#ifndef PCI_IOBASE
#define PCI_IOBASE ((void __iomem *) 0)
#ifndef writeb
#define writeb writeb
static inline void writeb(u8 value, volatile void __iomem *addr)
{
__raw_writeb(value, addr);
}
#endif
/*****************************************************************************/
#ifndef writew
#define writew writew
static inline void writew(u16 value, volatile void __iomem *addr)
{
__raw_writew(cpu_to_le16(value), addr);
}
#endif
#ifndef writel
#define writel writel
static inline void writel(u32 value, volatile void __iomem *addr)
{
__raw_writel(__cpu_to_le32(value), addr);
}
#endif
#ifdef CONFIG_64BIT
#ifndef writeq
#define writeq writeq
static inline void writeq(u64 value, volatile void __iomem *addr)
{
__raw_writeq(__cpu_to_le64(value), addr);
}
#endif
#endif /* CONFIG_64BIT */
/*
* traditional input/output functions
* {read,write}{b,w,l,q}_relaxed() are like the regular version, but
* are not guaranteed to provide ordering against spinlocks or memory
* accesses.
*/
#ifndef readb_relaxed
#define readb_relaxed readb
#endif
static inline u8 inb(unsigned long addr)
{
return readb(addr + PCI_IOBASE);
}
#ifndef readw_relaxed
#define readw_relaxed readw
#endif
static inline u16 inw(unsigned long addr)
{
return readw(addr + PCI_IOBASE);
}
#ifndef readl_relaxed
#define readl_relaxed readl
#endif
static inline u32 inl(unsigned long addr)
{
return readl(addr + PCI_IOBASE);
}
#ifndef readq_relaxed
#define readq_relaxed readq
#endif
static inline void outb(u8 b, unsigned long addr)
{
writeb(b, addr + PCI_IOBASE);
}
#ifndef writeb_relaxed
#define writeb_relaxed writeb
#endif
static inline void outw(u16 b, unsigned long addr)
{
writew(b, addr + PCI_IOBASE);
}
#ifndef writew_relaxed
#define writew_relaxed writew
#endif
static inline void outl(u32 b, unsigned long addr)
{
writel(b, addr + PCI_IOBASE);
}
#ifndef writel_relaxed
#define writel_relaxed writel
#endif
#define inb_p(addr) inb(addr)
#define inw_p(addr) inw(addr)
#define inl_p(addr) inl(addr)
#define outb_p(x, addr) outb((x), (addr))
#define outw_p(x, addr) outw((x), (addr))
#define outl_p(x, addr) outl((x), (addr))
#ifndef writeq_relaxed
#define writeq_relaxed writeq
#endif
#ifndef insb
static inline void insb(unsigned long addr, void *buffer, int count)
/*
* {read,write}s{b,w,l,q}() repeatedly access the same memory address in
* native endianness in 8-, 16-, 32- or 64-bit chunks (@count times).
*/
#ifndef readsb
#define readsb readsb
static inline void readsb(const volatile void __iomem *addr, void *buffer,
unsigned int count)
{
if (count) {
u8 *buf = buffer;
do {
u8 x = __raw_readb(addr + PCI_IOBASE);
u8 x = __raw_readb(addr);
*buf++ = x;
} while (--count);
}
}
#endif
#ifndef insw
static inline void insw(unsigned long addr, void *buffer, int count)
#ifndef readsw
#define readsw readsw
static inline void readsw(const volatile void __iomem *addr, void *buffer,
unsigned int count)
{
if (count) {
u16 *buf = buffer;
do {
u16 x = __raw_readw(addr + PCI_IOBASE);
u16 x = __raw_readw(addr);
*buf++ = x;
} while (--count);
}
}
#endif
#ifndef insl
static inline void insl(unsigned long addr, void *buffer, int count)
#ifndef readsl
#define readsl readsl
static inline void readsl(const volatile void __iomem *addr, void *buffer,
unsigned int count)
{
if (count) {
u32 *buf = buffer;
do {
u32 x = __raw_readl(addr + PCI_IOBASE);
u32 x = __raw_readl(addr);
*buf++ = x;
} while (--count);
}
}
#endif
#ifndef outsb
static inline void outsb(unsigned long addr, const void *buffer, int count)
#ifdef CONFIG_64BIT
#ifndef readsq
#define readsq readsq
static inline void readsq(const volatile void __iomem *addr, void *buffer,
unsigned int count)
{
if (count) {
u64 *buf = buffer;
do {
u64 x = __raw_readq(addr);
*buf++ = x;
} while (--count);
}
}
#endif
#endif /* CONFIG_64BIT */
#ifndef writesb
#define writesb writesb
static inline void writesb(volatile void __iomem *addr, const void *buffer,
unsigned int count)
{
if (count) {
const u8 *buf = buffer;
do {
__raw_writeb(*buf++, addr + PCI_IOBASE);
__raw_writeb(*buf++, addr);
} while (--count);
}
}
#endif
#ifndef outsw
static inline void outsw(unsigned long addr, const void *buffer, int count)
#ifndef writesw
#define writesw writesw
static inline void writesw(volatile void __iomem *addr, const void *buffer,
unsigned int count)
{
if (count) {
const u16 *buf = buffer;
do {
__raw_writew(*buf++, addr + PCI_IOBASE);
__raw_writew(*buf++, addr);
} while (--count);
}
}
#endif
#ifndef outsl
static inline void outsl(unsigned long addr, const void *buffer, int count)
#ifndef writesl
#define writesl writesl
static inline void writesl(volatile void __iomem *addr, const void *buffer,
unsigned int count)
{
if (count) {
const u32 *buf = buffer;
do {
__raw_writel(*buf++, addr + PCI_IOBASE);
__raw_writel(*buf++, addr);
} while (--count);
}
}
#endif
#ifndef CONFIG_GENERIC_IOMAP
#define ioread8(addr) readb(addr)
#define ioread16(addr) readw(addr)
#define ioread16be(addr) __be16_to_cpu(__raw_readw(addr))
#define ioread32(addr) readl(addr)
#define ioread32be(addr) __be32_to_cpu(__raw_readl(addr))
#ifdef CONFIG_64BIT
#ifndef writesq
#define writesq writesq
static inline void writesq(volatile void __iomem *addr, const void *buffer,
unsigned int count)
{
if (count) {
const u64 *buf = buffer;
#define iowrite8(v, addr) writeb((v), (addr))
#define iowrite16(v, addr) writew((v), (addr))
#define iowrite16be(v, addr) __raw_writew(__cpu_to_be16(v), addr)
#define iowrite32(v, addr) writel((v), (addr))
#define iowrite32be(v, addr) __raw_writel(__cpu_to_be32(v), addr)
do {
__raw_writeq(*buf++, addr);
} while (--count);
}
}
#endif
#endif /* CONFIG_64BIT */
#define ioread8_rep(p, dst, count) \
insb((unsigned long) (p), (dst), (count))
#define ioread16_rep(p, dst, count) \
insw((unsigned long) (p), (dst), (count))
#define ioread32_rep(p, dst, count) \
insl((unsigned long) (p), (dst), (count))
#define iowrite8_rep(p, src, count) \
outsb((unsigned long) (p), (src), (count))
#define iowrite16_rep(p, src, count) \
outsw((unsigned long) (p), (src), (count))
#define iowrite32_rep(p, src, count) \
outsl((unsigned long) (p), (src), (count))
#endif /* CONFIG_GENERIC_IOMAP */
#ifndef PCI_IOBASE
#define PCI_IOBASE ((void __iomem *)0)
#endif
#ifndef IO_SPACE_LIMIT
#define IO_SPACE_LIMIT 0xffff
#endif
/*
* {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be
* implemented on hardware that needs an additional delay for I/O accesses to
* take effect.
*/
#ifndef inb
#define inb inb
static inline u8 inb(unsigned long addr)
{
return readb(PCI_IOBASE + addr);
}
#endif
#ifndef inw
#define inw inw
static inline u16 inw(unsigned long addr)
{
return readw(PCI_IOBASE + addr);
}
#endif
#ifndef inl
#define inl inl
static inline u32 inl(unsigned long addr)
{
return readl(PCI_IOBASE + addr);
}
#endif
#ifndef outb
#define outb outb
static inline void outb(u8 value, unsigned long addr)
{
writeb(value, PCI_IOBASE + addr);
}
#endif
#ifndef outw
#define outw outw
static inline void outw(u16 value, unsigned long addr)
{
writew(value, PCI_IOBASE + addr);
}
#endif
#ifndef outl
#define outl outl
static inline void outl(u32 value, unsigned long addr)
{
writel(value, PCI_IOBASE + addr);
}
#endif
#ifndef inb_p
#define inb_p inb_p
static inline u8 inb_p(unsigned long addr)
{
return inb(addr);
}
#endif
#ifndef inw_p
#define inw_p inw_p
static inline u16 inw_p(unsigned long addr)
{
return inw(addr);
}
#endif
#ifndef inl_p
#define inl_p inl_p
static inline u32 inl_p(unsigned long addr)
{
return inl(addr);
}
#endif
#ifndef outb_p
#define outb_p outb_p
static inline void outb_p(u8 value, unsigned long addr)
{
outb(value, addr);
}
#endif
#ifndef outw_p
#define outw_p outw_p
static inline void outw_p(u16 value, unsigned long addr)
{
outw(value, addr);
}
#endif
#ifndef outl_p
#define outl_p outl_p
static inline void outl_p(u32 value, unsigned long addr)
{
outl(value, addr);
}
#endif
/*
* {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a
* single I/O port multiple times.
*/
#ifndef insb
#define insb insb
static inline void insb(unsigned long addr, void *buffer, unsigned int count)
{
readsb(PCI_IOBASE + addr, buffer, count);
}
#endif
#ifndef insw
#define insw insw
static inline void insw(unsigned long addr, void *buffer, unsigned int count)
{
readsw(PCI_IOBASE + addr, buffer, count);
}
#endif
#ifndef insl
#define insl insl
static inline void insl(unsigned long addr, void *buffer, unsigned int count)
{
readsl(PCI_IOBASE + addr, buffer, count);
}
#endif
#ifndef outsb
#define outsb outsb
static inline void outsb(unsigned long addr, const void *buffer,
unsigned int count)
{
writesb(PCI_IOBASE + addr, buffer, count);
}
#endif
#ifndef outsw
#define outsw outsw
static inline void outsw(unsigned long addr, const void *buffer,
unsigned int count)
{
writesw(PCI_IOBASE + addr, buffer, count);
}
#endif
#ifndef outsl
#define outsl outsl
static inline void outsl(unsigned long addr, const void *buffer,
unsigned int count)
{
writesl(PCI_IOBASE + addr, buffer, count);
}
#endif
#ifndef insb_p
#define insb_p insb_p
static inline void insb_p(unsigned long addr, void *buffer, unsigned int count)
{
insb(addr, buffer, count);
}
#endif
#ifndef insw_p
#define insw_p insw_p
static inline void insw_p(unsigned long addr, void *buffer, unsigned int count)
{
insw(addr, buffer, count);
}
#endif
#ifndef insl_p
#define insl_p insl_p
static inline void insl_p(unsigned long addr, void *buffer, unsigned int count)
{
insl(addr, buffer, count);
}
#endif
#ifndef outsb_p
#define outsb_p outsb_p
static inline void outsb_p(unsigned long addr, const void *buffer,
unsigned int count)
{
outsb(addr, buffer, count);
}
#endif
#ifndef outsw_p
#define outsw_p outsw_p
static inline void outsw_p(unsigned long addr, const void *buffer,
unsigned int count)
{
outsw(addr, buffer, count);
}
#endif
#ifndef outsl_p
#define outsl_p outsl_p
static inline void outsl_p(unsigned long addr, const void *buffer,
unsigned int count)
{
outsl(addr, buffer, count);
}
#endif
#ifndef CONFIG_GENERIC_IOMAP
#ifndef ioread8
#define ioread8 ioread8
static inline u8 ioread8(const volatile void __iomem *addr)
{
return readb(addr);
}
#endif
#ifndef ioread16
#define ioread16 ioread16
static inline u16 ioread16(const volatile void __iomem *addr)
{
return readw(addr);
}
#endif
#ifndef ioread32
#define ioread32 ioread32
static inline u32 ioread32(const volatile void __iomem *addr)
{
return readl(addr);
}
#endif
#ifndef iowrite8
#define iowrite8 iowrite8
static inline void iowrite8(u8 value, volatile void __iomem *addr)
{
writeb(value, addr);
}
#endif
#ifndef iowrite16
#define iowrite16 iowrite16
static inline void iowrite16(u16 value, volatile void __iomem *addr)
{
writew(value, addr);
}
#endif
#ifndef iowrite32
#define iowrite32 iowrite32
static inline void iowrite32(u32 value, volatile void __iomem *addr)
{
writel(value, addr);
}
#endif
#ifndef ioread16be
#define ioread16be ioread16be
static inline u16 ioread16be(const volatile void __iomem *addr)
{
return __be16_to_cpu(__raw_readw(addr));
}
#endif
#ifndef ioread32be
#define ioread32be ioread32be
static inline u32 ioread32be(const volatile void __iomem *addr)
{
return __be32_to_cpu(__raw_readl(addr));
}
#endif
#ifndef iowrite16be
#define iowrite16be iowrite16be
static inline void iowrite16be(u16 value, void volatile __iomem *addr)
{
__raw_writew(__cpu_to_be16(value), addr);
}
#endif
#ifndef iowrite32be
#define iowrite32be iowrite32be
static inline void iowrite32be(u32 value, volatile void __iomem *addr)
{
__raw_writel(__cpu_to_be32(value), addr);
}
#endif
#ifndef ioread8_rep
#define ioread8_rep ioread8_rep
static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer,
unsigned int count)
{
readsb(addr, buffer, count);
}
#endif
#ifndef ioread16_rep
#define ioread16_rep ioread16_rep
static inline void ioread16_rep(const volatile void __iomem *addr,
void *buffer, unsigned int count)
{
readsw(addr, buffer, count);
}
#endif
#ifndef ioread32_rep
#define ioread32_rep ioread32_rep
static inline void ioread32_rep(const volatile void __iomem *addr,
void *buffer, unsigned int count)
{
readsl(addr, buffer, count);
}
#endif
#ifndef iowrite8_rep
#define iowrite8_rep iowrite8_rep
static inline void iowrite8_rep(volatile void __iomem *addr,
const void *buffer,
unsigned int count)
{
writesb(addr, buffer, count);
}
#endif
#ifndef iowrite16_rep
#define iowrite16_rep iowrite16_rep
static inline void iowrite16_rep(volatile void __iomem *addr,
const void *buffer,
unsigned int count)
{
writesw(addr, buffer, count);
}
#endif
#ifndef iowrite32_rep
#define iowrite32_rep iowrite32_rep
static inline void iowrite32_rep(volatile void __iomem *addr,
const void *buffer,
unsigned int count)
{
writesl(addr, buffer, count);
}
#endif
#endif /* CONFIG_GENERIC_IOMAP */
#ifdef __KERNEL__
#include <linux/vmalloc.h>
#define __io_virt(x) ((void __force *) (x))
#define __io_virt(x) ((void __force *)(x))
#ifndef CONFIG_GENERIC_IOMAP
struct pci_dev;
extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
#ifndef pci_iounmap
#define pci_iounmap pci_iounmap
static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
{
}
@@ -289,11 +721,15 @@ static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
* These are pretty trivial
*/
#ifndef virt_to_phys
#define virt_to_phys virt_to_phys
static inline unsigned long virt_to_phys(volatile void *address)
{
return __pa((unsigned long)address);
}
#endif
#ifndef phys_to_virt
#define phys_to_virt phys_to_virt
static inline void *phys_to_virt(unsigned long address)
{
return __va(address);
@@ -306,37 +742,65 @@ static inline void *phys_to_virt(unsigned long address)
* This implementation is for the no-MMU case only... if you have an MMU
* you'll need to provide your own definitions.
*/
#ifndef CONFIG_MMU
static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
{
return (void __iomem*) (unsigned long)offset;
}
#define __ioremap(offset, size, flags) ioremap(offset, size)
#ifndef CONFIG_MMU
#ifndef ioremap
#define ioremap ioremap
static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
{
return (void __iomem *)(unsigned long)offset;
}
#endif
#ifndef __ioremap
#define __ioremap __ioremap
static inline void __iomem *__ioremap(phys_addr_t offset, size_t size,
unsigned long flags)
{
return ioremap(offset, size);
}
#endif
#ifndef ioremap_nocache
#define ioremap_nocache ioremap
#define ioremap_nocache ioremap_nocache
static inline void __iomem *ioremap_nocache(phys_addr_t offset, size_t size)
{
return ioremap(offset, size);
}
#endif
#ifndef ioremap_wc
#define ioremap_wc ioremap_nocache
#define ioremap_wc ioremap_wc
static inline void __iomem *ioremap_wc(phys_addr_t offset, size_t size)
{
return ioremap_nocache(offset, size);
}
#endif
#ifndef iounmap
#define iounmap iounmap
static inline void iounmap(void __iomem *addr)
{
}
#endif
#endif /* CONFIG_MMU */
#ifdef CONFIG_HAS_IOPORT_MAP
#ifndef CONFIG_GENERIC_IOMAP
#ifndef ioport_map
#define ioport_map ioport_map
static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
return (void __iomem *) port;
return PCI_IOBASE + (port & IO_SPACE_LIMIT);
}
#endif
#ifndef ioport_unmap
#define ioport_unmap ioport_unmap
static inline void ioport_unmap(void __iomem *p)
{
}
#endif
#else /* CONFIG_GENERIC_IOMAP */
extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
extern void ioport_unmap(void __iomem *p);
@@ -344,35 +808,68 @@ extern void ioport_unmap(void __iomem *p);
#endif /* CONFIG_HAS_IOPORT_MAP */
#ifndef xlate_dev_kmem_ptr
#define xlate_dev_kmem_ptr(p) p
#define xlate_dev_kmem_ptr xlate_dev_kmem_ptr
static inline void *xlate_dev_kmem_ptr(void *addr)
{
return addr;
}
#endif
#ifndef xlate_dev_mem_ptr
#define xlate_dev_mem_ptr(p) __va(p)
#define xlate_dev_mem_ptr xlate_dev_mem_ptr
static inline void *xlate_dev_mem_ptr(phys_addr_t addr)
{
return __va(addr);
}
#endif
#ifndef unxlate_dev_mem_ptr
#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
static inline void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)
{
}
#endif
#ifdef CONFIG_VIRT_TO_BUS
#ifndef virt_to_bus
static inline unsigned long virt_to_bus(volatile void *address)
static inline unsigned long virt_to_bus(void *address)
{
return ((unsigned long) address);
return (unsigned long)address;
}
static inline void *bus_to_virt(unsigned long address)
{
return (void *) address;
return (void *)address;
}
#endif
#endif
#ifndef memset_io
#define memset_io(a, b, c) memset(__io_virt(a), (b), (c))
#define memset_io memset_io
static inline void memset_io(volatile void __iomem *addr, int value,
size_t size)
{
memset(__io_virt(addr), value, size);
}
#endif
#ifndef memcpy_fromio
#define memcpy_fromio(a, b, c) memcpy((a), __io_virt(b), (c))
#define memcpy_fromio memcpy_fromio
static inline void memcpy_fromio(void *buffer,
const volatile void __iomem *addr,
size_t size)
{
memcpy(buffer, __io_virt(addr), size);
}
#endif
#ifndef memcpy_toio
#define memcpy_toio(a, b, c) memcpy(__io_virt(a), (b), (c))
#define memcpy_toio memcpy_toio
static inline void memcpy_toio(volatile void __iomem *addr, const void *buffer,
size_t size)
{
memcpy(__io_virt(addr), buffer, size);
}
#endif
#endif /* __KERNEL__ */

10
include/asm-generic/irq_work.h Normal file
View File

@@ -0,0 +1,10 @@
#ifndef __ASM_IRQ_WORK_H
#define __ASM_IRQ_WORK_H
static inline bool arch_irq_work_has_interrupt(void)
{
return false;
}
#endif /* __ASM_IRQ_WORK_H */

17
include/asm-generic/mm_hooks.h
View File

@@ -1,7 +1,7 @@
/*
* Define generic no-op hooks for arch_dup_mmap and arch_exit_mmap, to
* be included in asm-FOO/mmu_context.h for any arch FOO which doesn't
* need to hook these.
* Define generic no-op hooks for arch_dup_mmap, arch_exit_mmap
* and arch_unmap to be included in asm-FOO/mmu_context.h for any
* arch FOO which doesn't need to hook these.
*/
#ifndef _ASM_GENERIC_MM_HOOKS_H
#define _ASM_GENERIC_MM_HOOKS_H
@@ -15,4 +15,15 @@ static inline void arch_exit_mmap(struct mm_struct *mm)
{
}
static inline void arch_unmap(struct mm_struct *mm,
struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
}
static inline void arch_bprm_mm_init(struct mm_struct *mm,
struct vm_area_struct *vma)
{
}
#endif /* _ASM_GENERIC_MM_HOOKS_H */

32
include/asm-generic/msi.h Normal file
View File

@@ -0,0 +1,32 @@
#ifndef __ASM_GENERIC_MSI_H
#define __ASM_GENERIC_MSI_H
#include <linux/types.h>
#ifndef NUM_MSI_ALLOC_SCRATCHPAD_REGS
# define NUM_MSI_ALLOC_SCRATCHPAD_REGS 2
#endif
struct msi_desc;
/**
* struct msi_alloc_info - Default structure for MSI interrupt allocation.
* @desc: Pointer to msi descriptor
* @hwirq: Associated hw interrupt number in the domain
* @scratchpad: Storage for implementation specific scratch data
*
* Architectures can provide their own implementation by not including
* asm-generic/msi.h into their arch specific header file.
*/
typedef struct msi_alloc_info {
struct msi_desc *desc;
irq_hw_number_t hwirq;
union {
unsigned long ul;
void *ptr;
} scratchpad[NUM_MSI_ALLOC_SCRATCHPAD_REGS];
} msi_alloc_info_t;
#define GENERIC_MSI_DOMAIN_OPS 1
#endif

56
include/asm-generic/pgtable.h
View File

@@ -103,6 +103,17 @@ static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
#endif
#ifndef __HAVE_ARCH_PMDP_GET_AND_CLEAR_FULL
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
static inline pmd_t pmdp_get_and_clear_full(struct mm_struct *mm,
unsigned long address, pmd_t *pmdp,
int full)
{
return pmdp_get_and_clear(mm, address, pmdp);
}
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
#endif
#ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
unsigned long address, pte_t *ptep,
@@ -249,6 +260,24 @@ static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
#define pgprot_writecombine pgprot_noncached
#endif
#ifndef pgprot_device
#define pgprot_device pgprot_noncached
#endif
#ifndef pgprot_modify
#define pgprot_modify pgprot_modify
static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
{
if (pgprot_val(oldprot) == pgprot_val(pgprot_noncached(oldprot)))
newprot = pgprot_noncached(newprot);
if (pgprot_val(oldprot) == pgprot_val(pgprot_writecombine(oldprot)))
newprot = pgprot_writecombine(newprot);
if (pgprot_val(oldprot) == pgprot_val(pgprot_device(oldprot)))
newprot = pgprot_device(newprot);
return newprot;
}
#endif
/*
* When walking page tables, get the address of the next boundary,
* or the end address of the range if that comes earlier. Although no
@@ -660,11 +689,12 @@ static inline int pmd_trans_unstable(pmd_t *pmd)
}
#ifdef CONFIG_NUMA_BALANCING
#ifdef CONFIG_ARCH_USES_NUMA_PROT_NONE
/*
* _PAGE_NUMA works identical to _PAGE_PROTNONE (it's actually the
* same bit too). It's set only when _PAGE_PRESET is not set and it's
* never set if _PAGE_PRESENT is set.
* _PAGE_NUMA distinguishes between an unmapped page table entry, an entry that
* is protected for PROT_NONE and a NUMA hinting fault entry. If the
* architecture defines __PAGE_PROTNONE then it should take that into account
* but those that do not can rely on the fact that the NUMA hinting scanner
* skips inaccessible VMAs.
*
* pte/pmd_present() returns true if pte/pmd_numa returns true. Page
* fault triggers on those regions if pte/pmd_numa returns true
@@ -673,16 +703,14 @@ static inline int pmd_trans_unstable(pmd_t *pmd)
#ifndef pte_numa
static inline int pte_numa(pte_t pte)
{
return (pte_flags(pte) &
(_PAGE_NUMA|_PAGE_PROTNONE|_PAGE_PRESENT)) == _PAGE_NUMA;
return ptenuma_flags(pte) == _PAGE_NUMA;
}
#endif
#ifndef pmd_numa
static inline int pmd_numa(pmd_t pmd)
{
return (pmd_flags(pmd) &
(_PAGE_NUMA|_PAGE_PROTNONE|_PAGE_PRESENT)) == _PAGE_NUMA;
return pmdnuma_flags(pmd) == _PAGE_NUMA;
}
#endif
@@ -722,6 +750,8 @@ static inline pte_t pte_mknuma(pte_t pte)
{
pteval_t val = pte_val(pte);
VM_BUG_ON(!(val & _PAGE_PRESENT));
val &= ~_PAGE_PRESENT;
val |= _PAGE_NUMA;
@@ -765,16 +795,6 @@ static inline void pmdp_set_numa(struct mm_struct *mm, unsigned long addr,
}
#endif
#else
extern int pte_numa(pte_t pte);
extern int pmd_numa(pmd_t pmd);
extern pte_t pte_mknonnuma(pte_t pte);
extern pmd_t pmd_mknonnuma(pmd_t pmd);
extern pte_t pte_mknuma(pte_t pte);
extern pmd_t pmd_mknuma(pmd_t pmd);
extern void ptep_set_numa(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
extern void pmdp_set_numa(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp);
#endif /* CONFIG_ARCH_USES_NUMA_PROT_NONE */
#else
static inline int pmd_numa(pmd_t pmd)
{
return 0;

3
include/asm-generic/preempt.h
View File

@@ -23,9 +23,6 @@ static __always_inline void preempt_count_set(int pc)
/*
* must be macros to avoid header recursion hell
*/
#define task_preempt_count(p) \
(task_thread_info(p)->preempt_count & ~PREEMPT_NEED_RESCHED)
#define init_task_preempt_count(p) do { \
task_thread_info(p)->preempt_count = PREEMPT_DISABLED; \
} while (0)

30
include/asm-generic/seccomp.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* include/asm-generic/seccomp.h
*
* Copyright (C) 2014 Linaro Limited
* Author: AKASHI Takahiro <takahiro.akashi@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _ASM_GENERIC_SECCOMP_H
#define _ASM_GENERIC_SECCOMP_H
#include <linux/unistd.h>
#if defined(CONFIG_COMPAT) && !defined(__NR_seccomp_read_32)
#define __NR_seccomp_read_32 __NR_read
#define __NR_seccomp_write_32 __NR_write
#define __NR_seccomp_exit_32 __NR_exit
#define __NR_seccomp_sigreturn_32 __NR_rt_sigreturn
#endif /* CONFIG_COMPAT && ! already defined */
#define __NR_seccomp_read __NR_read
#define __NR_seccomp_write __NR_write
#define __NR_seccomp_exit __NR_exit
#ifndef __NR_seccomp_sigreturn
#define __NR_seccomp_sigreturn __NR_rt_sigreturn
#endif
#endif /* _ASM_GENERIC_SECCOMP_H */

4
include/asm-generic/sections.h
View File

@@ -3,6 +3,8 @@
/* References to section boundaries */
#include <linux/compiler.h>
/*
* Usage guidelines:
* _text, _data: architecture specific, don't use them in arch-independent code
@@ -37,6 +39,8 @@ extern char __start_rodata[], __end_rodata[];
/* Start and end of .ctors section - used for constructor calls. */
extern char __ctors_start[], __ctors_end[];
extern __visible const void __nosave_begin, __nosave_end;
/* function descriptor handling (if any). Override
* in asm/sections.h */
#ifndef dereference_function_descriptor

2
include/asm-generic/syscall.h
View File

@@ -147,7 +147,7 @@ void syscall_set_arguments(struct task_struct *task, struct pt_regs *regs,
*
* Returns the AUDIT_ARCH_* based on the system call convention in use.
*
* It's only valid to call this when @task is stopped on entry to a system
* It's only valid to call this when current is stopped on entry to a system
* call, due to %TIF_SYSCALL_TRACE, %TIF_SYSCALL_AUDIT, or %TIF_SECCOMP.
*
* Architectures which permit CONFIG_HAVE_ARCH_SECCOMP_FILTER must

57
include/asm-generic/tlb.h
View File

@@ -96,10 +96,9 @@ struct mmu_gather {
#endif
unsigned long start;
unsigned long end;
unsigned int need_flush : 1, /* Did free PTEs */
/* we are in the middle of an operation to clear
* a full mm and can make some optimizations */
fullmm : 1,
unsigned int fullmm : 1,
/* we have performed an operation which
* requires a complete flush of the tlb */
need_flush_all : 1;
@@ -128,16 +127,54 @@ static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
tlb_flush_mmu(tlb);
}
static inline void __tlb_adjust_range(struct mmu_gather *tlb,
unsigned long address)
{
tlb->start = min(tlb->start, address);
tlb->end = max(tlb->end, address + PAGE_SIZE);
}
static inline void __tlb_reset_range(struct mmu_gather *tlb)
{
tlb->start = TASK_SIZE;
tlb->end = 0;
}
/*
* In the case of tlb vma handling, we can optimise these away in the
* case where we're doing a full MM flush. When we're doing a munmap,
* the vmas are adjusted to only cover the region to be torn down.
*/
#ifndef tlb_start_vma
#define tlb_start_vma(tlb, vma) do { } while (0)
#endif
#define __tlb_end_vma(tlb, vma) \
do { \
if (!tlb->fullmm && tlb->end) { \
tlb_flush(tlb); \
__tlb_reset_range(tlb); \
} \
} while (0)
#ifndef tlb_end_vma
#define tlb_end_vma __tlb_end_vma
#endif
#ifndef __tlb_remove_tlb_entry
#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
#endif
/**
* tlb_remove_tlb_entry - remember a pte unmapping for later tlb invalidation.
*
* Record the fact that pte's were really umapped in ->need_flush, so we can
* later optimise away the tlb invalidate. This helps when userspace is
* unmapping already-unmapped pages, which happens quite a lot.
* Record the fact that pte's were really unmapped by updating the range,
* so we can later optimise away the tlb invalidate. This helps when
* userspace is unmapping already-unmapped pages, which happens quite a lot.
*/
#define tlb_remove_tlb_entry(tlb, ptep, address) \
do { \
tlb->need_flush = 1; \
__tlb_adjust_range(tlb, address); \
__tlb_remove_tlb_entry(tlb, ptep, address); \
} while (0)
@@ -151,27 +188,27 @@ static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
#define tlb_remove_pmd_tlb_entry(tlb, pmdp, address) \
do { \
tlb->need_flush = 1; \
__tlb_adjust_range(tlb, address); \
__tlb_remove_pmd_tlb_entry(tlb, pmdp, address); \
} while (0)
#define pte_free_tlb(tlb, ptep, address) \
do { \
tlb->need_flush = 1; \
__tlb_adjust_range(tlb, address); \
__pte_free_tlb(tlb, ptep, address); \
} while (0)
#ifndef __ARCH_HAS_4LEVEL_HACK
#define pud_free_tlb(tlb, pudp, address) \
do { \
tlb->need_flush = 1; \
__tlb_adjust_range(tlb, address); \
__pud_free_tlb(tlb, pudp, address); \
} while (0)
#endif
#define pmd_free_tlb(tlb, pmdp, address) \
do { \
tlb->need_flush = 1; \
__tlb_adjust_range(tlb, address); \
__pmd_free_tlb(tlb, pmdp, address); \
} while (0)

4
include/asm-generic/vmlinux.lds.h
View File

@@ -40,6 +40,8 @@
* }
*
* [__init_begin, __init_end] is the init section that may be freed after init
* // __init_begin and __init_end should be page aligned, so that we can
* // free the whole .init memory
* [_stext, _etext] is the text section
* [_sdata, _edata] is the data section
*
@@ -162,6 +164,7 @@
#define CLKSRC_OF_TABLES() OF_TABLE(CONFIG_CLKSRC_OF, clksrc)
#define IRQCHIP_OF_MATCH_TABLE() OF_TABLE(CONFIG_IRQCHIP, irqchip)
#define CLK_OF_TABLES() OF_TABLE(CONFIG_COMMON_CLK, clk)
#define IOMMU_OF_TABLES() OF_TABLE(CONFIG_OF_IOMMU, iommu)
#define RESERVEDMEM_OF_TABLES() OF_TABLE(CONFIG_OF_RESERVED_MEM, reservedmem)
#define CPU_METHOD_OF_TABLES() OF_TABLE(CONFIG_SMP, cpu_method)
#define EARLYCON_OF_TABLES() OF_TABLE(CONFIG_SERIAL_EARLYCON, earlycon)
@@ -495,6 +498,7 @@
CLK_OF_TABLES() \
RESERVEDMEM_OF_TABLES() \
CLKSRC_OF_TABLES() \
IOMMU_OF_TABLES() \
CPU_METHOD_OF_TABLES() \
KERNEL_DTB() \
IRQCHIP_OF_MATCH_TABLE() \

19
include/crypto/drbg.h
View File

@@ -82,15 +82,6 @@ typedef uint32_t drbg_flag_t;
struct drbg_core {
drbg_flag_t flags; /* flags for the cipher */
__u8 statelen; /* maximum state length */
/*
* maximum length of personalization string or additional input
* string -- exponent for base 2
*/
__u8 max_addtllen;
/* maximum bits per RNG request -- exponent for base 2*/
__u8 max_bits;
/* maximum number of requests -- exponent for base 2 */
__u8 max_req;
__u8 blocklen_bytes; /* block size of output in bytes */
char cra_name[CRYPTO_MAX_ALG_NAME]; /* mapping to kernel crypto API */
/* kernel crypto API backend cipher name */
@@ -156,12 +147,13 @@ static inline __u8 drbg_keylen(struct drbg_state *drbg)
static inline size_t drbg_max_request_bytes(struct drbg_state *drbg)
{
/* max_bits is in bits, but buflen is in bytes */
return (1 << (drbg->core->max_bits - 3));
/* SP800-90A requires the limit 2**19 bits, but we return bytes */
return (1 << 16);
}
static inline size_t drbg_max_addtl(struct drbg_state *drbg)
{
/* SP800-90A requires 2**35 bytes additional info str / pers str */
#if (__BITS_PER_LONG == 32)
/*
* SP800-90A allows smaller maximum numbers to be returned -- we
@@ -170,16 +162,17 @@ static inline size_t drbg_max_addtl(struct drbg_state *drbg)
*/
return (SIZE_MAX - 1);
#else
return (1UL<<(drbg->core->max_addtllen));
return (1UL<<35);
#endif
}
static inline size_t drbg_max_requests(struct drbg_state *drbg)
{
/* SP800-90A requires 2**48 maximum requests before reseeding */
#if (__BITS_PER_LONG == 32)
return SIZE_MAX;
#else
return (1UL<<(drbg->core->max_req));
return (1UL<<48);
#endif
}

497
include/crypto/hash.h
View File

@@ -17,6 +17,32 @@
struct crypto_ahash;
/**
* DOC: Message Digest Algorithm Definitions
*
* These data structures define modular message digest algorithm
* implementations, managed via crypto_register_ahash(),
* crypto_register_shash(), crypto_unregister_ahash() and
* crypto_unregister_shash().
*/
/**
* struct hash_alg_common - define properties of message digest
* @digestsize: Size of the result of the transformation. A buffer of this size
* must be available to the @final and @finup calls, so they can
* store the resulting hash into it. For various predefined sizes,
* search include/crypto/ using
* git grep _DIGEST_SIZE include/crypto.
* @statesize: Size of the block for partial state of the transformation. A
* buffer of this size must be passed to the @export function as it
* will save the partial state of the transformation into it. On the
* other side, the @import function will load the state from a
* buffer of this size as well.
* @base: Start of data structure of cipher algorithm. The common data
* structure of crypto_alg contains information common to all ciphers.
* The hash_alg_common data structure now adds the hash-specific
* information.
*/
struct hash_alg_common {
unsigned int digestsize;
unsigned int statesize;
@@ -37,6 +63,63 @@ struct ahash_request {
void *__ctx[] CRYPTO_MINALIGN_ATTR;
};
/**
* struct ahash_alg - asynchronous message digest definition
* @init: Initialize the transformation context. Intended only to initialize the
* state of the HASH transformation at the begining. This shall fill in
* the internal structures used during the entire duration of the whole
* transformation. No data processing happens at this point.
* @update: Push a chunk of data into the driver for transformation. This
* function actually pushes blocks of data from upper layers into the
* driver, which then passes those to the hardware as seen fit. This
* function must not finalize the HASH transformation by calculating the
* final message digest as this only adds more data into the
* transformation. This function shall not modify the transformation
* context, as this function may be called in parallel with the same
* transformation object. Data processing can happen synchronously
* [SHASH] or asynchronously [AHASH] at this point.
* @final: Retrieve result from the driver. This function finalizes the
* transformation and retrieves the resulting hash from the driver and
* pushes it back to upper layers. No data processing happens at this
* point.
* @finup: Combination of @update and @final. This function is effectively a
* combination of @update and @final calls issued in sequence. As some
* hardware cannot do @update and @final separately, this callback was
* added to allow such hardware to be used at least by IPsec. Data
* processing can happen synchronously [SHASH] or asynchronously [AHASH]
* at this point.
* @digest: Combination of @init and @update and @final. This function
* effectively behaves as the entire chain of operations, @init,
* @update and @final issued in sequence. Just like @finup, this was
* added for hardware which cannot do even the @finup, but can only do
* the whole transformation in one run. Data processing can happen
* synchronously [SHASH] or asynchronously [AHASH] at this point.
* @setkey: Set optional key used by the hashing algorithm. Intended to push
* optional key used by the hashing algorithm from upper layers into
* the driver. This function can store the key in the transformation
* context or can outright program it into the hardware. In the former
* case, one must be careful to program the key into the hardware at
* appropriate time and one must be careful that .setkey() can be
* called multiple times during the existence of the transformation
* object. Not all hashing algorithms do implement this function as it
* is only needed for keyed message digests. SHAx/MDx/CRCx do NOT
* implement this function. HMAC(MDx)/HMAC(SHAx)/CMAC(AES) do implement
* this function. This function must be called before any other of the
* @init, @update, @final, @finup, @digest is called. No data
* processing happens at this point.
* @export: Export partial state of the transformation. This function dumps the
* entire state of the ongoing transformation into a provided block of
* data so it can be @import 'ed back later on. This is useful in case
* you want to save partial result of the transformation after
* processing certain amount of data and reload this partial result
* multiple times later on for multiple re-use. No data processing
* happens at this point.
* @import: Import partial state of the transformation. This function loads the
* entire state of the ongoing transformation from a provided block of
* data so the transformation can continue from this point onward. No
* data processing happens at this point.
* @halg: see struct hash_alg_common
*/
struct ahash_alg {
int (*init)(struct ahash_request *req);
int (*update)(struct ahash_request *req);
@@ -58,6 +141,28 @@ struct shash_desc {
void *__ctx[] CRYPTO_MINALIGN_ATTR;
};
#define SHASH_DESC_ON_STACK(shash, ctx) \
char __##shash##_desc[sizeof(struct shash_desc) + \
crypto_shash_descsize(ctx)] CRYPTO_MINALIGN_ATTR; \
struct shash_desc *shash = (struct shash_desc *)__##shash##_desc
/**
* struct shash_alg - synchronous message digest definition
* @init: see struct ahash_alg
* @update: see struct ahash_alg
* @final: see struct ahash_alg
* @finup: see struct ahash_alg
* @digest: see struct ahash_alg
* @export: see struct ahash_alg
* @import: see struct ahash_alg
* @setkey: see struct ahash_alg
* @digestsize: see struct ahash_alg
* @statesize: see struct ahash_alg
* @descsize: Size of the operational state for the message digest. This state
* size is the memory size that needs to be allocated for
* shash_desc.__ctx
* @base: internally used
*/
struct shash_alg {
int (*init)(struct shash_desc *desc);
int (*update)(struct shash_desc *desc, const u8 *data,
@@ -102,11 +207,35 @@ struct crypto_shash {
struct crypto_tfm base;
};
/**
* DOC: Asynchronous Message Digest API
*
* The asynchronous message digest API is used with the ciphers of type
* CRYPTO_ALG_TYPE_AHASH (listed as type "ahash" in /proc/crypto)
*
* The asynchronous cipher operation discussion provided for the
* CRYPTO_ALG_TYPE_ABLKCIPHER API applies here as well.
*/
static inline struct crypto_ahash *__crypto_ahash_cast(struct crypto_tfm *tfm)
{
return container_of(tfm, struct crypto_ahash, base);
}
/**
* crypto_alloc_ahash() - allocate ahash cipher handle
* @alg_name: is the cra_name / name or cra_driver_name / driver name of the
* ahash cipher
* @type: specifies the type of the cipher
* @mask: specifies the mask for the cipher
*
* Allocate a cipher handle for an ahash. The returned struct
* crypto_ahash is the cipher handle that is required for any subsequent
* API invocation for that ahash.
*
* Return: allocated cipher handle in case of success; IS_ERR() is true in case
* of an error, PTR_ERR() returns the error code.
*/
struct crypto_ahash *crypto_alloc_ahash(const char *alg_name, u32 type,
u32 mask);
@@ -115,6 +244,10 @@ static inline struct crypto_tfm *crypto_ahash_tfm(struct crypto_ahash *tfm)
return &tfm->base;
}
/**
* crypto_free_ahash() - zeroize and free the ahash handle
* @tfm: cipher handle to be freed
*/
static inline void crypto_free_ahash(struct crypto_ahash *tfm)
{
crypto_destroy_tfm(tfm, crypto_ahash_tfm(tfm));
@@ -138,6 +271,16 @@ static inline struct hash_alg_common *crypto_hash_alg_common(
return __crypto_hash_alg_common(crypto_ahash_tfm(tfm)->__crt_alg);
}
/**
* crypto_ahash_digestsize() - obtain message digest size
* @tfm: cipher handle
*
* The size for the message digest created by the message digest cipher
* referenced with the cipher handle is returned.
*
*
* Return: message digest size of cipher
*/
static inline unsigned int crypto_ahash_digestsize(struct crypto_ahash *tfm)
{
return crypto_hash_alg_common(tfm)->digestsize;
@@ -163,12 +306,32 @@ static inline void crypto_ahash_clear_flags(struct crypto_ahash *tfm, u32 flags)
crypto_tfm_clear_flags(crypto_ahash_tfm(tfm), flags);
}
/**
* crypto_ahash_reqtfm() - obtain cipher handle from request
* @req: asynchronous request handle that contains the reference to the ahash
* cipher handle
*
* Return the ahash cipher handle that is registered with the asynchronous
* request handle ahash_request.
*
* Return: ahash cipher handle
*/
static inline struct crypto_ahash *crypto_ahash_reqtfm(
struct ahash_request *req)
{
return __crypto_ahash_cast(req->base.tfm);
}
/**
* crypto_ahash_reqsize() - obtain size of the request data structure
* @tfm: cipher handle
*
* Return the size of the ahash state size. With the crypto_ahash_export
* function, the caller can export the state into a buffer whose size is
* defined with this function.
*
* Return: size of the ahash state
*/
static inline unsigned int crypto_ahash_reqsize(struct crypto_ahash *tfm)
{
return tfm->reqsize;
@@ -179,38 +342,166 @@ static inline void *ahash_request_ctx(struct ahash_request *req)
return req->__ctx;
}
/**
* crypto_ahash_setkey - set key for cipher handle
* @tfm: cipher handle
* @key: buffer holding the key
* @keylen: length of the key in bytes
*
* The caller provided key is set for the ahash cipher. The cipher
* handle must point to a keyed hash in order for this function to succeed.
*
* Return: 0 if the setting of the key was successful; < 0 if an error occurred
*/
int crypto_ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
unsigned int keylen);
/**
* crypto_ahash_finup() - update and finalize message digest
* @req: reference to the ahash_request handle that holds all information
* needed to perform the cipher operation
*
* This function is a "short-hand" for the function calls of
* crypto_ahash_update and crypto_shash_final. The parameters have the same
* meaning as discussed for those separate functions.
*
* Return: 0 if the message digest creation was successful; < 0 if an error
* occurred
*/
int crypto_ahash_finup(struct ahash_request *req);
/**
* crypto_ahash_final() - calculate message digest
* @req: reference to the ahash_request handle that holds all information
* needed to perform the cipher operation
*
* Finalize the message digest operation and create the message digest
* based on all data added to the cipher handle. The message digest is placed
* into the output buffer registered with the ahash_request handle.
*
* Return: 0 if the message digest creation was successful; < 0 if an error
* occurred
*/
int crypto_ahash_final(struct ahash_request *req);
/**
* crypto_ahash_digest() - calculate message digest for a buffer
* @req: reference to the ahash_request handle that holds all information
* needed to perform the cipher operation
*
* This function is a "short-hand" for the function calls of crypto_ahash_init,
* crypto_ahash_update and crypto_ahash_final. The parameters have the same
* meaning as discussed for those separate three functions.
*
* Return: 0 if the message digest creation was successful; < 0 if an error
* occurred
*/
int crypto_ahash_digest(struct ahash_request *req);
/**
* crypto_ahash_export() - extract current message digest state
* @req: reference to the ahash_request handle whose state is exported
* @out: output buffer of sufficient size that can hold the hash state
*
* This function exports the hash state of the ahash_request handle into the
* caller-allocated output buffer out which must have sufficient size (e.g. by
* calling crypto_ahash_reqsize).
*
* Return: 0 if the export was successful; < 0 if an error occurred
*/
static inline int crypto_ahash_export(struct ahash_request *req, void *out)
{
return crypto_ahash_reqtfm(req)->export(req, out);
}
/**
* crypto_ahash_import() - import message digest state
* @req: reference to ahash_request handle the state is imported into
* @in: buffer holding the state
*
* This function imports the hash state into the ahash_request handle from the
* input buffer. That buffer should have been generated with the
* crypto_ahash_export function.
*
* Return: 0 if the import was successful; < 0 if an error occurred
*/
static inline int crypto_ahash_import(struct ahash_request *req, const void *in)
{
return crypto_ahash_reqtfm(req)->import(req, in);
}
/**
* crypto_ahash_init() - (re)initialize message digest handle
* @req: ahash_request handle that already is initialized with all necessary
* data using the ahash_request_* API functions
*
* The call (re-)initializes the message digest referenced by the ahash_request
* handle. Any potentially existing state created by previous operations is
* discarded.
*
* Return: 0 if the message digest initialization was successful; < 0 if an
* error occurred
*/
static inline int crypto_ahash_init(struct ahash_request *req)
{
return crypto_ahash_reqtfm(req)->init(req);
}
/**
* crypto_ahash_update() - add data to message digest for processing
* @req: ahash_request handle that was previously initialized with the
* crypto_ahash_init call.
*
* Updates the message digest state of the &ahash_request handle. The input data
* is pointed to by the scatter/gather list registered in the &ahash_request
* handle
*
* Return: 0 if the message digest update was successful; < 0 if an error
* occurred
*/
static inline int crypto_ahash_update(struct ahash_request *req)
{
return crypto_ahash_reqtfm(req)->update(req);
}
/**
* DOC: Asynchronous Hash Request Handle
*
* The &ahash_request data structure contains all pointers to data
* required for the asynchronous cipher operation. This includes the cipher
* handle (which can be used by multiple &ahash_request instances), pointer
* to plaintext and the message digest output buffer, asynchronous callback
* function, etc. It acts as a handle to the ahash_request_* API calls in a
* similar way as ahash handle to the crypto_ahash_* API calls.
*/
/**
* ahash_request_set_tfm() - update cipher handle reference in request
* @req: request handle to be modified
* @tfm: cipher handle that shall be added to the request handle
*
* Allow the caller to replace the existing ahash handle in the request
* data structure with a different one.
*/
static inline void ahash_request_set_tfm(struct ahash_request *req,
struct crypto_ahash *tfm)
{
req->base.tfm = crypto_ahash_tfm(tfm);
}
/**
* ahash_request_alloc() - allocate request data structure
* @tfm: cipher handle to be registered with the request
* @gfp: memory allocation flag that is handed to kmalloc by the API call.
*
* Allocate the request data structure that must be used with the ahash
* message digest API calls. During
* the allocation, the provided ahash handle
* is registered in the request data structure.
*
* Return: allocated request handle in case of success; IS_ERR() is true in case
* of an error, PTR_ERR() returns the error code.
*/
static inline struct ahash_request *ahash_request_alloc(
struct crypto_ahash *tfm, gfp_t gfp)
{
@@ -225,6 +516,10 @@ static inline struct ahash_request *ahash_request_alloc(
return req;
}
/**
* ahash_request_free() - zeroize and free the request data structure
* @req: request data structure cipher handle to be freed
*/
static inline void ahash_request_free(struct ahash_request *req)
{
kzfree(req);
@@ -236,6 +531,31 @@ static inline struct ahash_request *ahash_request_cast(
return container_of(req, struct ahash_request, base);
}
/**
* ahash_request_set_callback() - set asynchronous callback function
* @req: request handle
* @flags: specify zero or an ORing of the flags
* CRYPTO_TFM_REQ_MAY_BACKLOG the request queue may back log and
* increase the wait queue beyond the initial maximum size;
* CRYPTO_TFM_REQ_MAY_SLEEP the request processing may sleep
* @compl: callback function pointer to be registered with the request handle
* @data: The data pointer refers to memory that is not used by the kernel
* crypto API, but provided to the callback function for it to use. Here,
* the caller can provide a reference to memory the callback function can
* operate on. As the callback function is invoked asynchronously to the
* related functionality, it may need to access data structures of the
* related functionality which can be referenced using this pointer. The
* callback function can access the memory via the "data" field in the
* &crypto_async_request data structure provided to the callback function.
*
* This function allows setting the callback function that is triggered once
* the cipher operation completes.
*
* The callback function is registered with the &ahash_request handle and
* must comply with the following template
*
* void callback_function(struct crypto_async_request *req, int error)
*/
static inline void ahash_request_set_callback(struct ahash_request *req,
u32 flags,
crypto_completion_t compl,
@@ -246,6 +566,19 @@ static inline void ahash_request_set_callback(struct ahash_request *req,
req->base.flags = flags;
}
/**
* ahash_request_set_crypt() - set data buffers
* @req: ahash_request handle to be updated
* @src: source scatter/gather list
* @result: buffer that is filled with the message digest -- the caller must
* ensure that the buffer has sufficient space by, for example, calling
* crypto_ahash_digestsize()
* @nbytes: number of bytes to process from the source scatter/gather list
*
* By using this call, the caller references the source scatter/gather list.
* The source scatter/gather list points to the data the message digest is to
* be calculated for.
*/
static inline void ahash_request_set_crypt(struct ahash_request *req,
struct scatterlist *src, u8 *result,
unsigned int nbytes)
@@ -255,6 +588,33 @@ static inline void ahash_request_set_crypt(struct ahash_request *req,
req->result = result;
}
/**
* DOC: Synchronous Message Digest API
*
* The synchronous message digest API is used with the ciphers of type
* CRYPTO_ALG_TYPE_SHASH (listed as type "shash" in /proc/crypto)
*
* The message digest API is able to maintain state information for the
* caller.
*
* The synchronous message digest API can store user-related context in in its
* shash_desc request data structure.
*/
/**
* crypto_alloc_shash() - allocate message digest handle
* @alg_name: is the cra_name / name or cra_driver_name / driver name of the
* message digest cipher
* @type: specifies the type of the cipher
* @mask: specifies the mask for the cipher
*
* Allocate a cipher handle for a message digest. The returned &struct
* crypto_shash is the cipher handle that is required for any subsequent
* API invocation for that message digest.
*
* Return: allocated cipher handle in case of success; IS_ERR() is true in case
* of an error, PTR_ERR() returns the error code.
*/
struct crypto_shash *crypto_alloc_shash(const char *alg_name, u32 type,
u32 mask);
@@ -263,6 +623,10 @@ static inline struct crypto_tfm *crypto_shash_tfm(struct crypto_shash *tfm)
return &tfm->base;
}
/**
* crypto_free_shash() - zeroize and free the message digest handle
* @tfm: cipher handle to be freed
*/
static inline void crypto_free_shash(struct crypto_shash *tfm)
{
crypto_destroy_tfm(tfm, crypto_shash_tfm(tfm));
@@ -274,6 +638,15 @@ static inline unsigned int crypto_shash_alignmask(
return crypto_tfm_alg_alignmask(crypto_shash_tfm(tfm));
}
/**
* crypto_shash_blocksize() - obtain block size for cipher
* @tfm: cipher handle
*
* The block size for the message digest cipher referenced with the cipher
* handle is returned.
*
* Return: block size of cipher
*/
static inline unsigned int crypto_shash_blocksize(struct crypto_shash *tfm)
{
return crypto_tfm_alg_blocksize(crypto_shash_tfm(tfm));
@@ -289,6 +662,15 @@ static inline struct shash_alg *crypto_shash_alg(struct crypto_shash *tfm)
return __crypto_shash_alg(crypto_shash_tfm(tfm)->__crt_alg);
}
/**
* crypto_shash_digestsize() - obtain message digest size
* @tfm: cipher handle
*
* The size for the message digest created by the message digest cipher
* referenced with the cipher handle is returned.
*
* Return: digest size of cipher
*/
static inline unsigned int crypto_shash_digestsize(struct crypto_shash *tfm)
{
return crypto_shash_alg(tfm)->digestsize;
@@ -314,6 +696,21 @@ static inline void crypto_shash_clear_flags(struct crypto_shash *tfm, u32 flags)
crypto_tfm_clear_flags(crypto_shash_tfm(tfm), flags);
}
/**
* crypto_shash_descsize() - obtain the operational state size
* @tfm: cipher handle
*
* The size of the operational state the cipher needs during operation is
* returned for the hash referenced with the cipher handle. This size is
* required to calculate the memory requirements to allow the caller allocating
* sufficient memory for operational state.
*
* The operational state is defined with struct shash_desc where the size of
* that data structure is to be calculated as
* sizeof(struct shash_desc) + crypto_shash_descsize(alg)
*
* Return: size of the operational state
*/
static inline unsigned int crypto_shash_descsize(struct crypto_shash *tfm)
{
return tfm->descsize;
@@ -324,29 +721,129 @@ static inline void *shash_desc_ctx(struct shash_desc *desc)
return desc->__ctx;
}
/**
* crypto_shash_setkey() - set key for message digest
* @tfm: cipher handle
* @key: buffer holding the key
* @keylen: length of the key in bytes
*
* The caller provided key is set for the keyed message digest cipher. The
* cipher handle must point to a keyed message digest cipher in order for this
* function to succeed.
*
* Return: 0 if the setting of the key was successful; < 0 if an error occurred
*/
int crypto_shash_setkey(struct crypto_shash *tfm, const u8 *key,
unsigned int keylen);
/**
* crypto_shash_digest() - calculate message digest for buffer
* @desc: see crypto_shash_final()
* @data: see crypto_shash_update()
* @len: see crypto_shash_update()
* @out: see crypto_shash_final()
*
* This function is a "short-hand" for the function calls of crypto_shash_init,
* crypto_shash_update and crypto_shash_final. The parameters have the same
* meaning as discussed for those separate three functions.
*
* Return: 0 if the message digest creation was successful; < 0 if an error
* occurred
*/
int crypto_shash_digest(struct shash_desc *desc, const u8 *data,
unsigned int len, u8 *out);
/**
* crypto_shash_export() - extract operational state for message digest
* @desc: reference to the operational state handle whose state is exported
* @out: output buffer of sufficient size that can hold the hash state
*
* This function exports the hash state of the operational state handle into the
* caller-allocated output buffer out which must have sufficient size (e.g. by
* calling crypto_shash_descsize).
*
* Return: 0 if the export creation was successful; < 0 if an error occurred
*/
static inline int crypto_shash_export(struct shash_desc *desc, void *out)
{
return crypto_shash_alg(desc->tfm)->export(desc, out);
}
/**
* crypto_shash_import() - import operational state
* @desc: reference to the operational state handle the state imported into
* @in: buffer holding the state
*
* This function imports the hash state into the operational state handle from
* the input buffer. That buffer should have been generated with the
* crypto_ahash_export function.
*
* Return: 0 if the import was successful; < 0 if an error occurred
*/
static inline int crypto_shash_import(struct shash_desc *desc, const void *in)
{
return crypto_shash_alg(desc->tfm)->import(desc, in);
}
/**
* crypto_shash_init() - (re)initialize message digest
* @desc: operational state handle that is already filled
*
* The call (re-)initializes the message digest referenced by the
* operational state handle. Any potentially existing state created by
* previous operations is discarded.
*
* Return: 0 if the message digest initialization was successful; < 0 if an
* error occurred
*/
static inline int crypto_shash_init(struct shash_desc *desc)
{
return crypto_shash_alg(desc->tfm)->init(desc);
}
/**
* crypto_shash_update() - add data to message digest for processing
* @desc: operational state handle that is already initialized
* @data: input data to be added to the message digest
* @len: length of the input data
*
* Updates the message digest state of the operational state handle.
*
* Return: 0 if the message digest update was successful; < 0 if an error
* occurred
*/
int crypto_shash_update(struct shash_desc *desc, const u8 *data,
unsigned int len);
/**
* crypto_shash_final() - calculate message digest
* @desc: operational state handle that is already filled with data
* @out: output buffer filled with the message digest
*
* Finalize the message digest operation and create the message digest
* based on all data added to the cipher handle. The message digest is placed
* into the output buffer. The caller must ensure that the output buffer is
* large enough by using crypto_shash_digestsize.
*
* Return: 0 if the message digest creation was successful; < 0 if an error
* occurred
*/
int crypto_shash_final(struct shash_desc *desc, u8 *out);
/**
* crypto_shash_finup() - calculate message digest of buffer
* @desc: see crypto_shash_final()
* @data: see crypto_shash_update()
* @len: see crypto_shash_update()
* @out: see crypto_shash_final()
*
* This function is a "short-hand" for the function calls of
* crypto_shash_update and crypto_shash_final. The parameters have the same
* meaning as discussed for those separate functions.
*
* Return: 0 if the message digest creation was successful; < 0 if an error
* occurred
*/
int crypto_shash_finup(struct shash_desc *desc, const u8 *data,
unsigned int len, u8 *out);

1
include/crypto/if_alg.h
View File

@@ -42,6 +42,7 @@ struct af_alg_completion {
struct af_alg_control {
struct af_alg_iv *iv;
int op;
unsigned int aead_assoclen;
};
struct af_alg_type {

9
include/crypto/internal/hash.h
View File

@@ -117,6 +117,15 @@ int shash_ahash_update(struct ahash_request *req, struct shash_desc *desc);
int shash_ahash_finup(struct ahash_request *req, struct shash_desc *desc);
int shash_ahash_digest(struct ahash_request *req, struct shash_desc *desc);
int shash_ahash_mcryptd_update(struct ahash_request *req,
struct shash_desc *desc);
int shash_ahash_mcryptd_final(struct ahash_request *req,
struct shash_desc *desc);
int shash_ahash_mcryptd_finup(struct ahash_request *req,
struct shash_desc *desc);
int shash_ahash_mcryptd_digest(struct ahash_request *req,
struct shash_desc *desc);
int crypto_init_shash_ops_async(struct crypto_tfm *tfm);
static inline void *crypto_ahash_ctx(struct crypto_ahash *tfm)

112
include/crypto/mcryptd.h Normal file
View File

@@ -0,0 +1,112 @@
/*
* Software async multibuffer crypto daemon headers
*
* Author:
* Tim Chen <tim.c.chen@linux.intel.com>
*
* Copyright (c) 2014, Intel Corporation.
*/
#ifndef _CRYPTO_MCRYPT_H
#define _CRYPTO_MCRYPT_H
#include <linux/crypto.h>
#include <linux/kernel.h>
#include <crypto/hash.h>
struct mcryptd_ahash {
struct crypto_ahash base;
};
static inline struct mcryptd_ahash *__mcryptd_ahash_cast(
struct crypto_ahash *tfm)
{
return (struct mcryptd_ahash *)tfm;
}
struct mcryptd_cpu_queue {
struct crypto_queue queue;
struct work_struct work;
};
struct mcryptd_queue {
struct mcryptd_cpu_queue __percpu *cpu_queue;
};
struct mcryptd_instance_ctx {
struct crypto_spawn spawn;
struct mcryptd_queue *queue;
};
struct mcryptd_hash_ctx {
struct crypto_shash *child;
struct mcryptd_alg_state *alg_state;
};
struct mcryptd_tag {
/* seq number of request */
unsigned seq_num;
/* arrival time of request */
unsigned long arrival;
unsigned long expire;
int cpu;
};
struct mcryptd_hash_request_ctx {
struct list_head waiter;
crypto_completion_t complete;
struct mcryptd_tag tag;
struct crypto_hash_walk walk;
u8 *out;
int flag;
struct shash_desc desc;
};
struct mcryptd_ahash *mcryptd_alloc_ahash(const char *alg_name,
u32 type, u32 mask);
struct crypto_shash *mcryptd_ahash_child(struct mcryptd_ahash *tfm);
struct shash_desc *mcryptd_shash_desc(struct ahash_request *req);
void mcryptd_free_ahash(struct mcryptd_ahash *tfm);
void mcryptd_flusher(struct work_struct *work);
enum mcryptd_req_type {
MCRYPTD_NONE,
MCRYPTD_UPDATE,
MCRYPTD_FINUP,
MCRYPTD_DIGEST,
MCRYPTD_FINAL
};
struct mcryptd_alg_cstate {
unsigned long next_flush;
unsigned next_seq_num;
bool flusher_engaged;
struct delayed_work flush;
int cpu;
struct mcryptd_alg_state *alg_state;
void *mgr;
spinlock_t work_lock;
struct list_head work_list;
struct list_head flush_list;
};
struct mcryptd_alg_state {
struct mcryptd_alg_cstate __percpu *alg_cstate;
unsigned long (*flusher)(struct mcryptd_alg_cstate *cstate);
};
/* return delay in jiffies from current time */
static inline unsigned long get_delay(unsigned long t)
{
long delay;
delay = (long) t - (long) jiffies;
if (delay <= 0)
return 0;
else
return (unsigned long) delay;
}
void mcryptd_arm_flusher(struct mcryptd_alg_cstate *cstate, unsigned long delay);
#endif

6
include/crypto/public_key.h
View File

@@ -15,6 +15,7 @@
#define _LINUX_PUBLIC_KEY_H
#include <linux/mpi.h>
#include <keys/asymmetric-type.h>
#include <crypto/hash_info.h>
enum pkey_algo {
@@ -98,8 +99,9 @@ struct key;
extern int verify_signature(const struct key *key,
const struct public_key_signature *sig);
struct asymmetric_key_id;
extern struct key *x509_request_asymmetric_key(struct key *keyring,
const char *issuer,
const char *key_id);
const struct asymmetric_key_id *kid,
bool partial);
#endif /* _LINUX_PUBLIC_KEY_H */

80
include/crypto/rng.h
View File

@@ -20,11 +20,38 @@ extern struct crypto_rng *crypto_default_rng;
int crypto_get_default_rng(void);
void crypto_put_default_rng(void);
/**
* DOC: Random number generator API
*
* The random number generator API is used with the ciphers of type
* CRYPTO_ALG_TYPE_RNG (listed as type "rng" in /proc/crypto)
*/
static inline struct crypto_rng *__crypto_rng_cast(struct crypto_tfm *tfm)
{
return (struct crypto_rng *)tfm;
}
/**
* crypto_alloc_rng() -- allocate RNG handle
* @alg_name: is the cra_name / name or cra_driver_name / driver name of the
* message digest cipher
* @type: specifies the type of the cipher
* @mask: specifies the mask for the cipher
*
* Allocate a cipher handle for a random number generator. The returned struct
* crypto_rng is the cipher handle that is required for any subsequent
* API invocation for that random number generator.
*
* For all random number generators, this call creates a new private copy of
* the random number generator that does not share a state with other
* instances. The only exception is the "krng" random number generator which
* is a kernel crypto API use case for the get_random_bytes() function of the
* /dev/random driver.
*
* Return: allocated cipher handle in case of success; IS_ERR() is true in case
* of an error, PTR_ERR() returns the error code.
*/
static inline struct crypto_rng *crypto_alloc_rng(const char *alg_name,
u32 type, u32 mask)
{
@@ -40,6 +67,14 @@ static inline struct crypto_tfm *crypto_rng_tfm(struct crypto_rng *tfm)
return &tfm->base;
}
/**
* crypto_rng_alg - obtain name of RNG
* @tfm: cipher handle
*
* Return the generic name (cra_name) of the initialized random number generator
*
* Return: generic name string
*/
static inline struct rng_alg *crypto_rng_alg(struct crypto_rng *tfm)
{
return &crypto_rng_tfm(tfm)->__crt_alg->cra_rng;
@@ -50,23 +85,68 @@ static inline struct rng_tfm *crypto_rng_crt(struct crypto_rng *tfm)
return &crypto_rng_tfm(tfm)->crt_rng;
}
/**
* crypto_free_rng() - zeroize and free RNG handle
* @tfm: cipher handle to be freed
*/
static inline void crypto_free_rng(struct crypto_rng *tfm)
{
crypto_free_tfm(crypto_rng_tfm(tfm));
}
/**
* crypto_rng_get_bytes() - get random number
* @tfm: cipher handle
* @rdata: output buffer holding the random numbers
* @dlen: length of the output buffer
*
* This function fills the caller-allocated buffer with random numbers using the
* random number generator referenced by the cipher handle.
*
* Return: > 0 function was successful and returns the number of generated
* bytes; < 0 if an error occurred
*/
static inline int crypto_rng_get_bytes(struct crypto_rng *tfm,
u8 *rdata, unsigned int dlen)
{
return crypto_rng_crt(tfm)->rng_gen_random(tfm, rdata, dlen);
}
/**
* crypto_rng_reset() - re-initialize the RNG
* @tfm: cipher handle
* @seed: seed input data
* @slen: length of the seed input data
*
* The reset function completely re-initializes the random number generator
* referenced by the cipher handle by clearing the current state. The new state
* is initialized with the caller provided seed or automatically, depending
* on the random number generator type (the ANSI X9.31 RNG requires
* caller-provided seed, the SP800-90A DRBGs perform an automatic seeding).
* The seed is provided as a parameter to this function call. The provided seed
* should have the length of the seed size defined for the random number
* generator as defined by crypto_rng_seedsize.
*
* Return: 0 if the setting of the key was successful; < 0 if an error occurred
*/
static inline int crypto_rng_reset(struct crypto_rng *tfm,
u8 *seed, unsigned int slen)
{
return crypto_rng_crt(tfm)->rng_reset(tfm, seed, slen);
}
/**
* crypto_rng_seedsize() - obtain seed size of RNG
* @tfm: cipher handle
*
* The function returns the seed size for the random number generator
* referenced by the cipher handle. This value may be zero if the random
* number generator does not implement or require a reseeding. For example,
* the SP800-90A DRBGs implement an automated reseeding after reaching a
* pre-defined threshold.
*
* Return: seed size for the random number generator
*/
static inline int crypto_rng_seedsize(struct crypto_rng *tfm)
{
return crypto_rng_alg(tfm)->seedsize;

30
include/drm/ati_pcigart.h Normal file
View File

@@ -0,0 +1,30 @@
#ifndef DRM_ATI_PCIGART_H
#define DRM_ATI_PCIGART_H
#include <drm/drm_legacy.h>
/* location of GART table */
#define DRM_ATI_GART_MAIN 1
#define DRM_ATI_GART_FB 2
#define DRM_ATI_GART_PCI 1
#define DRM_ATI_GART_PCIE 2
#define DRM_ATI_GART_IGP 3
struct drm_ati_pcigart_info {
int gart_table_location;
int gart_reg_if;
void *addr;
dma_addr_t bus_addr;
dma_addr_t table_mask;
struct drm_dma_handle *table_handle;
struct drm_local_map mapping;
int table_size;
};
extern int drm_ati_pcigart_init(struct drm_device *dev,
struct drm_ati_pcigart_info * gart_info);
extern int drm_ati_pcigart_cleanup(struct drm_device *dev,
struct drm_ati_pcigart_info * gart_info);
#endif

754
include/drm/drmP.h
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File diff suppressed because it is too large Load Diff

26
include/drm/drm_agpsupport.h
View File

@@ -1,12 +1,32 @@
#ifndef _DRM_AGPSUPPORT_H_
#define _DRM_AGPSUPPORT_H_
#include <linux/agp_backend.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/mm.h>
#include <linux/mutex.h>
#include <linux/types.h>
#include <linux/agp_backend.h>
#include <drm/drmP.h>
#include <uapi/drm/drm.h>
struct drm_device;
struct drm_file;
#define __OS_HAS_AGP (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && \
defined(MODULE)))
struct drm_agp_head {
struct agp_kern_info agp_info;
struct list_head memory;
unsigned long mode;
struct agp_bridge_data *bridge;
int enabled;
int acquired;
unsigned long base;
int agp_mtrr;
int cant_use_aperture;
unsigned long page_mask;
};
#if __OS_HAS_AGP
@@ -45,6 +65,7 @@ int drm_agp_unbind_ioctl(struct drm_device *dev, void *data,
int drm_agp_bind(struct drm_device *dev, struct drm_agp_binding *request);
int drm_agp_bind_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
#else /* __OS_HAS_AGP */
static inline void drm_free_agp(struct agp_memory * handle, int pages)
@@ -172,6 +193,7 @@ static inline int drm_agp_bind_ioctl(struct drm_device *dev, void *data,
{
return -ENODEV;
}
#endif /* __OS_HAS_AGP */
#endif /* _DRM_AGPSUPPORT_H_ */

69
include/drm/drm_atomic.h Normal file
View File

@@ -0,0 +1,69 @@
/*
* Copyright (C) 2014 Red Hat
* Copyright (C) 2014 Intel Corp.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors:
* Rob Clark <robdclark@gmail.com>
* Daniel Vetter <daniel.vetter@ffwll.ch>
*/
#ifndef DRM_ATOMIC_H_
#define DRM_ATOMIC_H_
#include <drm/drm_crtc.h>
struct drm_atomic_state * __must_check
drm_atomic_state_alloc(struct drm_device *dev);
void drm_atomic_state_clear(struct drm_atomic_state *state);
void drm_atomic_state_free(struct drm_atomic_state *state);
struct drm_crtc_state * __must_check
drm_atomic_get_crtc_state(struct drm_atomic_state *state,
struct drm_crtc *crtc);
struct drm_plane_state * __must_check
drm_atomic_get_plane_state(struct drm_atomic_state *state,
struct drm_plane *plane);
struct drm_connector_state * __must_check
drm_atomic_get_connector_state(struct drm_atomic_state *state,
struct drm_connector *connector);
int __must_check
drm_atomic_set_crtc_for_plane(struct drm_atomic_state *state,
struct drm_plane *plane, struct drm_crtc *crtc);
void drm_atomic_set_fb_for_plane(struct drm_plane_state *plane_state,
struct drm_framebuffer *fb);
int __must_check
drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state,
struct drm_crtc *crtc);
int __must_check
drm_atomic_add_affected_connectors(struct drm_atomic_state *state,
struct drm_crtc *crtc);
int
drm_atomic_connectors_for_crtc(struct drm_atomic_state *state,
struct drm_crtc *crtc);
void drm_atomic_legacy_backoff(struct drm_atomic_state *state);
int __must_check drm_atomic_check_only(struct drm_atomic_state *state);
int __must_check drm_atomic_commit(struct drm_atomic_state *state);
int __must_check drm_atomic_async_commit(struct drm_atomic_state *state);
#endif /* DRM_ATOMIC_H_ */

126
include/drm/drm_atomic_helper.h Normal file
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@@ -0,0 +1,126 @@
/*
* Copyright (C) 2014 Red Hat
* Copyright (C) 2014 Intel Corp.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors:
* Rob Clark <robdclark@gmail.com>
* Daniel Vetter <daniel.vetter@ffwll.ch>
*/
#ifndef DRM_ATOMIC_HELPER_H_
#define DRM_ATOMIC_HELPER_H_
#include <drm/drm_crtc.h>
int drm_atomic_helper_check(struct drm_device *dev,
struct drm_atomic_state *state);
int drm_atomic_helper_commit(struct drm_device *dev,
struct drm_atomic_state *state,
bool async);
void drm_atomic_helper_wait_for_vblanks(struct drm_device *dev,
struct drm_atomic_state *old_state);
void drm_atomic_helper_commit_pre_planes(struct drm_device *dev,
struct drm_atomic_state *state);
void drm_atomic_helper_commit_post_planes(struct drm_device *dev,
struct drm_atomic_state *old_state);
int drm_atomic_helper_prepare_planes(struct drm_device *dev,
struct drm_atomic_state *state);
void drm_atomic_helper_commit_planes(struct drm_device *dev,
struct drm_atomic_state *state);
void drm_atomic_helper_cleanup_planes(struct drm_device *dev,
struct drm_atomic_state *old_state);
void drm_atomic_helper_swap_state(struct drm_device *dev,
struct drm_atomic_state *state);
/* implementations for legacy interfaces */
int drm_atomic_helper_update_plane(struct drm_plane *plane,
struct drm_crtc *crtc,
struct drm_framebuffer *fb,
int crtc_x, int crtc_y,
unsigned int crtc_w, unsigned int crtc_h,
uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h);
int drm_atomic_helper_disable_plane(struct drm_plane *plane);
int drm_atomic_helper_set_config(struct drm_mode_set *set);
int drm_atomic_helper_crtc_set_property(struct drm_crtc *crtc,
struct drm_property *property,
uint64_t val);
int drm_atomic_helper_plane_set_property(struct drm_plane *plane,
struct drm_property *property,
uint64_t val);
int drm_atomic_helper_connector_set_property(struct drm_connector *connector,
struct drm_property *property,
uint64_t val);
int drm_atomic_helper_page_flip(struct drm_crtc *crtc,
struct drm_framebuffer *fb,
struct drm_pending_vblank_event *event,
uint32_t flags);
/* default implementations for state handling */
void drm_atomic_helper_crtc_reset(struct drm_crtc *crtc);
struct drm_crtc_state *
drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc);
void drm_atomic_helper_crtc_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
void drm_atomic_helper_plane_reset(struct drm_plane *plane);
struct drm_plane_state *
drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane);
void drm_atomic_helper_plane_destroy_state(struct drm_plane *plane,
struct drm_plane_state *state);
void drm_atomic_helper_connector_reset(struct drm_connector *connector);
struct drm_connector_state *
drm_atomic_helper_connector_duplicate_state(struct drm_connector *connector);
void drm_atomic_helper_connector_destroy_state(struct drm_connector *connector,
struct drm_connector_state *state);
/**
* drm_atomic_crtc_for_each_plane - iterate over planes currently attached to CRTC
* @plane: the loop cursor
* @crtc: the crtc whose planes are iterated
*
* This iterates over the current state, useful (for example) when applying
* atomic state after it has been checked and swapped. To iterate over the
* planes which *will* be attached (for ->atomic_check()) see
* drm_crtc_for_each_pending_plane()
*/
#define drm_atomic_crtc_for_each_plane(plane, crtc) \
drm_for_each_plane_mask(plane, (crtc)->dev, (crtc)->state->plane_mask)
/**
* drm_crtc_atomic_state_for_each_plane - iterate over attached planes in new state
* @plane: the loop cursor
* @crtc_state: the incoming crtc-state
*
* Similar to drm_crtc_for_each_plane(), but iterates the planes that will be
* attached if the specified state is applied. Useful during (for example)
* ->atomic_check() operations, to validate the incoming state
*/
#define drm_atomic_crtc_state_for_each_plane(plane, crtc_state) \
drm_for_each_plane_mask(plane, (crtc_state)->state->dev, (crtc_state)->plane_mask)
#endif /* DRM_ATOMIC_HELPER_H_ */

148
include/drm/drm_buffer.h
View File

@@ -1,148 +0,0 @@
/**************************************************************************
*
* Copyright 2010 Pauli Nieminen.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*
**************************************************************************/
/*
* Multipart buffer for coping data which is larger than the page size.
*
* Authors:
* Pauli Nieminen <suokkos-at-gmail-dot-com>
*/
#ifndef _DRM_BUFFER_H_
#define _DRM_BUFFER_H_
#include <drm/drmP.h>
struct drm_buffer {
int iterator;
int size;
char *data[];
};
/**
* Return the index of page that buffer is currently pointing at.
*/
static inline int drm_buffer_page(struct drm_buffer *buf)
{
return buf->iterator / PAGE_SIZE;
}
/**
* Return the index of the current byte in the page
*/
static inline int drm_buffer_index(struct drm_buffer *buf)
{
return buf->iterator & (PAGE_SIZE - 1);
}
/**
* Return number of bytes that is left to process
*/
static inline int drm_buffer_unprocessed(struct drm_buffer *buf)
{
return buf->size - buf->iterator;
}
/**
* Advance the buffer iterator number of bytes that is given.
*/
static inline void drm_buffer_advance(struct drm_buffer *buf, int bytes)
{
buf->iterator += bytes;
}
/**
* Allocate the drm buffer object.
*
* buf: A pointer to a pointer where the object is stored.
* size: The number of bytes to allocate.
*/
extern int drm_buffer_alloc(struct drm_buffer **buf, int size);
/**
* Copy the user data to the begin of the buffer and reset the processing
* iterator.
*
* user_data: A pointer the data that is copied to the buffer.
* size: The Number of bytes to copy.
*/
extern int drm_buffer_copy_from_user(struct drm_buffer *buf,
void __user *user_data, int size);
/**
* Free the drm buffer object
*/
extern void drm_buffer_free(struct drm_buffer *buf);
/**
* Read an object from buffer that may be split to multiple parts. If object
* is not split function just returns the pointer to object in buffer. But in
* case of split object data is copied to given stack object that is suplied
* by caller.
*
* The processing location of the buffer is also advanced to the next byte
* after the object.
*
* objsize: The size of the objet in bytes.
* stack_obj: A pointer to a memory location where object can be copied.
*/
extern void *drm_buffer_read_object(struct drm_buffer *buf,
int objsize, void *stack_obj);
/**
* Returns the pointer to the dword which is offset number of elements from the
* current processing location.
*
* Caller must make sure that dword is not split in the buffer. This
* requirement is easily met if all the sizes of objects in buffer are
* multiples of dword and PAGE_SIZE is multiple dword.
*
* Call to this function doesn't change the processing location.
*
* offset: The index of the dword relative to the internat iterator.
*/
static inline void *drm_buffer_pointer_to_dword(struct drm_buffer *buffer,
int offset)
{
int iter = buffer->iterator + offset * 4;
return &buffer->data[iter / PAGE_SIZE][iter & (PAGE_SIZE - 1)];
}
/**
* Returns the pointer to the dword which is offset number of elements from
* the current processing location.
*
* Call to this function doesn't change the processing location.
*
* offset: The index of the byte relative to the internat iterator.
*/
static inline void *drm_buffer_pointer_to_byte(struct drm_buffer *buffer,
int offset)
{
int iter = buffer->iterator + offset;
return &buffer->data[iter / PAGE_SIZE][iter & (PAGE_SIZE - 1)];
}
#endif

353
include/drm/drm_crtc.h
View File

@@ -31,8 +31,8 @@
#include <linux/idr.h>
#include <linux/fb.h>
#include <linux/hdmi.h>
#include <drm/drm_mode.h>
#include <drm/drm_fourcc.h>
#include <uapi/drm/drm_mode.h>
#include <uapi/drm/drm_fourcc.h>
#include <drm/drm_modeset_lock.h>
struct drm_device;
@@ -42,6 +42,7 @@ struct drm_object_properties;
struct drm_file;
struct drm_clip_rect;
struct device_node;
struct fence;
#define DRM_MODE_OBJECT_CRTC 0xcccccccc
#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
@@ -136,14 +137,22 @@ struct drm_display_info {
u8 cea_rev;
};
/* data corresponds to displayid vend/prod/serial */
struct drm_tile_group {
struct kref refcount;
struct drm_device *dev;
int id;
u8 group_data[8];
};
struct drm_framebuffer_funcs {
/* note: use drm_framebuffer_remove() */
void (*destroy)(struct drm_framebuffer *framebuffer);
int (*create_handle)(struct drm_framebuffer *fb,
struct drm_file *file_priv,
unsigned int *handle);
/**
* Optinal callback for the dirty fb ioctl.
/*
* Optional callback for the dirty fb ioctl.
*
* Userspace can notify the driver via this callback
* that a area of the framebuffer has changed and should
@@ -196,7 +205,7 @@ struct drm_framebuffer {
struct drm_property_blob {
struct drm_mode_object base;
struct list_head head;
unsigned int length;
size_t length;
unsigned char data[];
};
@@ -215,32 +224,74 @@ struct drm_property {
uint64_t *values;
struct drm_device *dev;
struct list_head enum_blob_list;
struct list_head enum_list;
};
void drm_modeset_lock_all(struct drm_device *dev);
void drm_modeset_unlock_all(struct drm_device *dev);
void drm_warn_on_modeset_not_all_locked(struct drm_device *dev);
struct drm_crtc;
struct drm_connector;
struct drm_encoder;
struct drm_pending_vblank_event;
struct drm_plane;
struct drm_bridge;
struct drm_atomic_state;
/**
* drm_crtc_funcs - control CRTCs for a given device
* struct drm_crtc_state - mutable CRTC state
* @enable: whether the CRTC should be enabled, gates all other state
* @mode_changed: for use by helpers and drivers when computing state updates
* @plane_mask: bitmask of (1 << drm_plane_index(plane)) of attached planes
* @last_vblank_count: for helpers and drivers to capture the vblank of the
* update to ensure framebuffer cleanup isn't done too early
* @planes_changed: for use by helpers and drivers when computing state updates
* @adjusted_mode: for use by helpers and drivers to compute adjusted mode timings
* @mode: current mode timings
* @event: optional pointer to a DRM event to signal upon completion of the
* state update
* @state: backpointer to global drm_atomic_state
*/
struct drm_crtc_state {
bool enable;
/* computed state bits used by helpers and drivers */
bool planes_changed : 1;
bool mode_changed : 1;
/* attached planes bitmask:
* WARNING: transitional helpers do not maintain plane_mask so
* drivers not converted over to atomic helpers should not rely
* on plane_mask being accurate!
*/
u32 plane_mask;
/* last_vblank_count: for vblank waits before cleanup */
u32 last_vblank_count;
/* adjusted_mode: for use by helpers and drivers */
struct drm_display_mode adjusted_mode;
struct drm_display_mode mode;
struct drm_pending_vblank_event *event;
struct drm_atomic_state *state;
};
/**
* struct drm_crtc_funcs - control CRTCs for a given device
* @save: save CRTC state
* @restore: restore CRTC state
* @reset: reset CRTC after state has been invalidated (e.g. resume)
* @cursor_set: setup the cursor
* @cursor_set2: setup the cursor with hotspot, superseeds @cursor_set if set
* @cursor_move: move the cursor
* @gamma_set: specify color ramp for CRTC
* @destroy: deinit and free object
* @set_property: called when a property is changed
* @set_config: apply a new CRTC configuration
* @page_flip: initiate a page flip
* @atomic_duplicate_state: duplicate the atomic state for this CRTC
* @atomic_destroy_state: destroy an atomic state for this CRTC
* @atomic_set_property: set a property on an atomic state for this CRTC
*
* The drm_crtc_funcs structure is the central CRTC management structure
* in the DRM. Each CRTC controls one or more connectors (note that the name
@@ -291,16 +342,28 @@ struct drm_crtc_funcs {
int (*set_property)(struct drm_crtc *crtc,
struct drm_property *property, uint64_t val);
/* atomic update handling */
struct drm_crtc_state *(*atomic_duplicate_state)(struct drm_crtc *crtc);
void (*atomic_destroy_state)(struct drm_crtc *crtc,
struct drm_crtc_state *state);
int (*atomic_set_property)(struct drm_crtc *crtc,
struct drm_crtc_state *state,
struct drm_property *property,
uint64_t val);
};
/**
* drm_crtc - central CRTC control structure
* struct drm_crtc - central CRTC control structure
* @dev: parent DRM device
* @port: OF node used by drm_of_find_possible_crtcs()
* @head: list management
* @mutex: per-CRTC locking
* @base: base KMS object for ID tracking etc.
* @primary: primary plane for this CRTC
* @cursor: cursor plane for this CRTC
* @cursor_x: current x position of the cursor, used for universal cursor planes
* @cursor_y: current y position of the cursor, used for universal cursor planes
* @enabled: is this CRTC enabled?
* @mode: current mode timings
* @hwmode: mode timings as programmed to hw regs
@@ -313,10 +376,13 @@ struct drm_crtc_funcs {
* @gamma_size: size of gamma ramp
* @gamma_store: gamma ramp values
* @framedur_ns: precise frame timing
* @framedur_ns: precise line timing
* @linedur_ns: precise line timing
* @pixeldur_ns: precise pixel timing
* @helper_private: mid-layer private data
* @properties: property tracking for this CRTC
* @state: current atomic state for this CRTC
* @acquire_ctx: per-CRTC implicit acquire context used by atomic drivers for
* legacy ioctls
*
* Each CRTC may have one or more connectors associated with it. This structure
* allows the CRTC to be controlled.
@@ -326,7 +392,7 @@ struct drm_crtc {
struct device_node *port;
struct list_head head;
/**
/*
* crtc mutex
*
* This provides a read lock for the overall crtc state (mode, dpms
@@ -345,10 +411,6 @@ struct drm_crtc {
int cursor_x;
int cursor_y;
/* Temporary tracking of the old fb while a modeset is ongoing. Used
* by drm_mode_set_config_internal to implement correct refcounting. */
struct drm_framebuffer *old_fb;
bool enabled;
/* Requested mode from modesetting. */
@@ -375,11 +437,32 @@ struct drm_crtc {
void *helper_private;
struct drm_object_properties properties;
struct drm_crtc_state *state;
/*
* For legacy crtc ioctls so that atomic drivers can get at the locking
* acquire context.
*/
struct drm_modeset_acquire_ctx *acquire_ctx;
};
/**
* struct drm_connector_state - mutable connector state
* @crtc: CRTC to connect connector to, NULL if disabled
* @best_encoder: can be used by helpers and drivers to select the encoder
* @state: backpointer to global drm_atomic_state
*/
struct drm_connector_state {
struct drm_crtc *crtc; /* do not write directly, use drm_atomic_set_crtc_for_connector() */
struct drm_encoder *best_encoder;
struct drm_atomic_state *state;
};
/**
* drm_connector_funcs - control connectors on a given device
* struct drm_connector_funcs - control connectors on a given device
* @dpms: set power state (see drm_crtc_funcs above)
* @save: save connector state
* @restore: restore connector state
@@ -389,6 +472,9 @@ struct drm_crtc {
* @set_property: property for this connector may need an update
* @destroy: make object go away
* @force: notify the driver that the connector is forced on
* @atomic_duplicate_state: duplicate the atomic state for this connector
* @atomic_destroy_state: destroy an atomic state for this connector
* @atomic_set_property: set a property on an atomic state for this connector
*
* Each CRTC may have one or more connectors attached to it. The functions
* below allow the core DRM code to control connectors, enumerate available modes,
@@ -413,10 +499,19 @@ struct drm_connector_funcs {
uint64_t val);
void (*destroy)(struct drm_connector *connector);
void (*force)(struct drm_connector *connector);
/* atomic update handling */
struct drm_connector_state *(*atomic_duplicate_state)(struct drm_connector *connector);
void (*atomic_destroy_state)(struct drm_connector *connector,
struct drm_connector_state *state);
int (*atomic_set_property)(struct drm_connector *connector,
struct drm_connector_state *state,
struct drm_property *property,
uint64_t val);
};
/**
* drm_encoder_funcs - encoder controls
* struct drm_encoder_funcs - encoder controls
* @reset: reset state (e.g. at init or resume time)
* @destroy: cleanup and free associated data
*
@@ -430,7 +525,7 @@ struct drm_encoder_funcs {
#define DRM_CONNECTOR_MAX_ENCODER 3
/**
* drm_encoder - central DRM encoder structure
* struct drm_encoder - central DRM encoder structure
* @dev: parent DRM device
* @head: list management
* @base: base KMS object
@@ -474,7 +569,7 @@ struct drm_encoder {
#define MAX_ELD_BYTES 128
/**
* drm_connector - central DRM connector control structure
* struct drm_connector - central DRM connector control structure
* @dev: parent DRM device
* @kdev: kernel device for sysfs attributes
* @attr: sysfs attributes
@@ -485,6 +580,7 @@ struct drm_encoder {
* @connector_type_id: index into connector type enum
* @interlace_allowed: can this connector handle interlaced modes?
* @doublescan_allowed: can this connector handle doublescan?
* @stereo_allowed: can this connector handle stereo modes?
* @modes: modes available on this connector (from fill_modes() + user)
* @status: one of the drm_connector_status enums (connected, not, or unknown)
* @probed_modes: list of modes derived directly from the display
@@ -492,10 +588,13 @@ struct drm_encoder {
* @funcs: connector control functions
* @edid_blob_ptr: DRM property containing EDID if present
* @properties: property tracking for this connector
* @path_blob_ptr: DRM blob property data for the DP MST path property
* @polled: a %DRM_CONNECTOR_POLL_<foo> value for core driven polling
* @dpms: current dpms state
* @helper_private: mid-layer private data
* @cmdline_mode: mode line parsed from the kernel cmdline for this connector
* @force: a %DRM_FORCE_<foo> state for forced mode sets
* @override_edid: has the EDID been overwritten through debugfs for testing?
* @encoder_ids: valid encoders for this connector
* @encoder: encoder driving this connector, if any
* @eld: EDID-like data, if present
@@ -505,6 +604,18 @@ struct drm_encoder {
* @video_latency: video latency info from ELD, if found
* @audio_latency: audio latency info from ELD, if found
* @null_edid_counter: track sinks that give us all zeros for the EDID
* @bad_edid_counter: track sinks that give us an EDID with invalid checksum
* @debugfs_entry: debugfs directory for this connector
* @state: current atomic state for this connector
* @has_tile: is this connector connected to a tiled monitor
* @tile_group: tile group for the connected monitor
* @tile_is_single_monitor: whether the tile is one monitor housing
* @num_h_tile: number of horizontal tiles in the tile group
* @num_v_tile: number of vertical tiles in the tile group
* @tile_h_loc: horizontal location of this tile
* @tile_v_loc: vertical location of this tile
* @tile_h_size: horizontal size of this tile.
* @tile_v_size: vertical size of this tile.
*
* Each connector may be connected to one or more CRTCs, or may be clonable by
* another connector if they can share a CRTC. Each connector also has a specific
@@ -540,6 +651,8 @@ struct drm_connector {
struct drm_property_blob *path_blob_ptr;
struct drm_property_blob *tile_blob_ptr;
uint8_t polled; /* DRM_CONNECTOR_POLL_* */
/* requested DPMS state */
@@ -548,6 +661,7 @@ struct drm_connector {
void *helper_private;
/* forced on connector */
struct drm_cmdline_mode cmdline_mode;
enum drm_connector_force force;
bool override_edid;
uint32_t encoder_ids[DRM_CONNECTOR_MAX_ENCODER];
@@ -564,14 +678,63 @@ struct drm_connector {
unsigned bad_edid_counter;
struct dentry *debugfs_entry;
struct drm_connector_state *state;
/* DisplayID bits */
bool has_tile;
struct drm_tile_group *tile_group;
bool tile_is_single_monitor;
uint8_t num_h_tile, num_v_tile;
uint8_t tile_h_loc, tile_v_loc;
uint16_t tile_h_size, tile_v_size;
};
/**
* drm_plane_funcs - driver plane control functions
* struct drm_plane_state - mutable plane state
* @crtc: currently bound CRTC, NULL if disabled
* @fb: currently bound framebuffer
* @fence: optional fence to wait for before scanning out @fb
* @crtc_x: left position of visible portion of plane on crtc
* @crtc_y: upper position of visible portion of plane on crtc
* @crtc_w: width of visible portion of plane on crtc
* @crtc_h: height of visible portion of plane on crtc
* @src_x: left position of visible portion of plane within
* plane (in 16.16)
* @src_y: upper position of visible portion of plane within
* plane (in 16.16)
* @src_w: width of visible portion of plane (in 16.16)
* @src_h: height of visible portion of plane (in 16.16)
* @state: backpointer to global drm_atomic_state
*/
struct drm_plane_state {
struct drm_crtc *crtc; /* do not write directly, use drm_atomic_set_crtc_for_plane() */
struct drm_framebuffer *fb; /* do not write directly, use drm_atomic_set_fb_for_plane() */
struct fence *fence;
/* Signed dest location allows it to be partially off screen */
int32_t crtc_x, crtc_y;
uint32_t crtc_w, crtc_h;
/* Source values are 16.16 fixed point */
uint32_t src_x, src_y;
uint32_t src_h, src_w;
struct drm_atomic_state *state;
};
/**
* struct drm_plane_funcs - driver plane control functions
* @update_plane: update the plane configuration
* @disable_plane: shut down the plane
* @destroy: clean up plane resources
* @reset: reset plane after state has been invalidated (e.g. resume)
* @set_property: called when a property is changed
* @atomic_duplicate_state: duplicate the atomic state for this plane
* @atomic_destroy_state: destroy an atomic state for this plane
* @atomic_set_property: set a property on an atomic state for this plane
*/
struct drm_plane_funcs {
int (*update_plane)(struct drm_plane *plane,
@@ -582,9 +745,19 @@ struct drm_plane_funcs {
uint32_t src_w, uint32_t src_h);
int (*disable_plane)(struct drm_plane *plane);
void (*destroy)(struct drm_plane *plane);
void (*reset)(struct drm_plane *plane);
int (*set_property)(struct drm_plane *plane,
struct drm_property *property, uint64_t val);
/* atomic update handling */
struct drm_plane_state *(*atomic_duplicate_state)(struct drm_plane *plane);
void (*atomic_destroy_state)(struct drm_plane *plane,
struct drm_plane_state *state);
int (*atomic_set_property)(struct drm_plane *plane,
struct drm_plane_state *state,
struct drm_property *property,
uint64_t val);
};
enum drm_plane_type {
@@ -594,7 +767,7 @@ enum drm_plane_type {
};
/**
* drm_plane - central DRM plane control structure
* struct drm_plane - central DRM plane control structure
* @dev: DRM device this plane belongs to
* @head: for list management
* @base: base mode object
@@ -603,14 +776,19 @@ enum drm_plane_type {
* @format_count: number of formats supported
* @crtc: currently bound CRTC
* @fb: currently bound fb
* @old_fb: Temporary tracking of the old fb while a modeset is ongoing. Used by
* drm_mode_set_config_internal() to implement correct refcounting.
* @funcs: helper functions
* @properties: property tracking for this plane
* @type: type of plane (overlay, primary, cursor)
* @state: current atomic state for this plane
*/
struct drm_plane {
struct drm_device *dev;
struct list_head head;
struct drm_modeset_lock mutex;
struct drm_mode_object base;
uint32_t possible_crtcs;
@@ -620,15 +798,21 @@ struct drm_plane {
struct drm_crtc *crtc;
struct drm_framebuffer *fb;
struct drm_framebuffer *old_fb;
const struct drm_plane_funcs *funcs;
struct drm_object_properties properties;
enum drm_plane_type type;
void *helper_private;
struct drm_plane_state *state;
};
/**
* drm_bridge_funcs - drm_bridge control functions
* struct drm_bridge_funcs - drm_bridge control functions
* @mode_fixup: Try to fixup (or reject entirely) proposed mode for this bridge
* @disable: Called right before encoder prepare, disables the bridge
* @post_disable: Called right after encoder prepare, for lockstepped disable
@@ -652,7 +836,7 @@ struct drm_bridge_funcs {
};
/**
* drm_bridge - central DRM bridge control structure
* struct drm_bridge - central DRM bridge control structure
* @dev: DRM device this bridge belongs to
* @head: list management
* @base: base mode object
@@ -670,8 +854,35 @@ struct drm_bridge {
};
/**
* drm_mode_set - new values for a CRTC config change
* @head: list management
* struct struct drm_atomic_state - the global state object for atomic updates
* @dev: parent DRM device
* @flags: state flags like async update
* @planes: pointer to array of plane pointers
* @plane_states: pointer to array of plane states pointers
* @crtcs: pointer to array of CRTC pointers
* @crtc_states: pointer to array of CRTC states pointers
* @num_connector: size of the @connectors and @connector_states arrays
* @connectors: pointer to array of connector pointers
* @connector_states: pointer to array of connector states pointers
* @acquire_ctx: acquire context for this atomic modeset state update
*/
struct drm_atomic_state {
struct drm_device *dev;
uint32_t flags;
struct drm_plane **planes;
struct drm_plane_state **plane_states;
struct drm_crtc **crtcs;
struct drm_crtc_state **crtc_states;
int num_connector;
struct drm_connector **connectors;
struct drm_connector_state **connector_states;
struct drm_modeset_acquire_ctx *acquire_ctx;
};
/**
* struct drm_mode_set - new values for a CRTC config change
* @fb: framebuffer to use for new config
* @crtc: CRTC whose configuration we're about to change
* @mode: mode timings to use
@@ -701,6 +912,9 @@ struct drm_mode_set {
* struct drm_mode_config_funcs - basic driver provided mode setting functions
* @fb_create: create a new framebuffer object
* @output_poll_changed: function to handle output configuration changes
* @atomic_check: check whether a give atomic state update is possible
* @atomic_commit: commit an atomic state update previously verified with
* atomic_check()
*
* Some global (i.e. not per-CRTC, connector, etc) mode setting functions that
* involve drivers.
@@ -710,13 +924,20 @@ struct drm_mode_config_funcs {
struct drm_file *file_priv,
struct drm_mode_fb_cmd2 *mode_cmd);
void (*output_poll_changed)(struct drm_device *dev);
int (*atomic_check)(struct drm_device *dev,
struct drm_atomic_state *a);
int (*atomic_commit)(struct drm_device *dev,
struct drm_atomic_state *a,
bool async);
};
/**
* drm_mode_group - group of mode setting resources for potential sub-grouping
* struct drm_mode_group - group of mode setting resources for potential sub-grouping
* @num_crtcs: CRTC count
* @num_encoders: encoder count
* @num_connectors: connector count
* @num_bridges: bridge count
* @id_list: list of KMS object IDs in this group
*
* Currently this simply tracks the global mode setting state. But in the
@@ -736,10 +957,14 @@ struct drm_mode_group {
};
/**
* drm_mode_config - Mode configuration control structure
* struct drm_mode_config - Mode configuration control structure
* @mutex: mutex protecting KMS related lists and structures
* @connection_mutex: ww mutex protecting connector state and routing
* @acquire_ctx: global implicit acquire context used by atomic drivers for
* legacy ioctls
* @idr_mutex: mutex for KMS ID allocation and management
* @crtc_idr: main KMS ID tracking object
* @fb_lock: mutex to protect fb state and lists
* @num_fb: number of fbs available
* @fb_list: list of framebuffers available
* @num_connector: number of connectors on this device
@@ -748,17 +973,28 @@ struct drm_mode_group {
* @bridge_list: list of bridge objects
* @num_encoder: number of encoders on this device
* @encoder_list: list of encoder objects
* @num_overlay_plane: number of overlay planes on this device
* @num_total_plane: number of universal (i.e. with primary/curso) planes on this device
* @plane_list: list of plane objects
* @num_crtc: number of CRTCs on this device
* @crtc_list: list of CRTC objects
* @property_list: list of property objects
* @min_width: minimum pixel width on this device
* @min_height: minimum pixel height on this device
* @max_width: maximum pixel width on this device
* @max_height: maximum pixel height on this device
* @funcs: core driver provided mode setting functions
* @fb_base: base address of the framebuffer
* @poll_enabled: track polling status for this device
* @poll_enabled: track polling support for this device
* @poll_running: track polling status for this device
* @output_poll_work: delayed work for polling in process context
* @property_blob_list: list of all the blob property objects
* @*_property: core property tracking
* @preferred_depth: preferred RBG pixel depth, used by fb helpers
* @prefer_shadow: hint to userspace to prefer shadow-fb rendering
* @async_page_flip: does this device support async flips on the primary plane?
* @cursor_width: hint to userspace for max cursor width
* @cursor_height: hint to userspace for max cursor height
*
* Core mode resource tracking structure. All CRTC, encoders, and connectors
* enumerated by the driver are added here, as are global properties. Some
@@ -770,16 +1006,10 @@ struct drm_mode_config {
struct drm_modeset_acquire_ctx *acquire_ctx; /* for legacy _lock_all() / _unlock_all() */
struct mutex idr_mutex; /* for IDR management */
struct idr crtc_idr; /* use this idr for all IDs, fb, crtc, connector, modes - just makes life easier */
struct idr tile_idr; /* use this idr for all IDs, fb, crtc, connector, modes - just makes life easier */
/* this is limited to one for now */
/**
* fb_lock - mutex to protect fb state
*
* Besides the global fb list his also protects the fbs list in the
* file_priv
*/
struct mutex fb_lock;
struct mutex fb_lock; /* proctects global and per-file fb lists */
int num_fb;
struct list_head fb_list;
@@ -820,7 +1050,9 @@ struct drm_mode_config {
struct drm_property *edid_property;
struct drm_property *dpms_property;
struct drm_property *path_property;
struct drm_property *tile_property;
struct drm_property *plane_type_property;
struct drm_property *rotation_property;
/* DVI-I properties */
struct drm_property *dvi_i_subconnector_property;
@@ -846,6 +1078,10 @@ struct drm_mode_config {
struct drm_property *aspect_ratio_property;
struct drm_property *dirty_info_property;
/* properties for virtual machine layout */
struct drm_property *suggested_x_property;
struct drm_property *suggested_y_property;
/* dumb ioctl parameters */
uint32_t preferred_depth, prefer_shadow;
@@ -856,6 +1092,19 @@ struct drm_mode_config {
uint32_t cursor_width, cursor_height;
};
/**
* drm_for_each_plane_mask - iterate over planes specified by bitmask
* @plane: the loop cursor
* @dev: the DRM device
* @plane_mask: bitmask of plane indices
*
* Iterate over all planes specified by bitmask.
*/
#define drm_for_each_plane_mask(plane, dev, plane_mask) \
list_for_each_entry((plane), &(dev)->mode_config.plane_list, head) \
if ((plane_mask) & (1 << drm_plane_index(plane)))
#define obj_to_crtc(x) container_of(x, struct drm_crtc, base)
#define obj_to_connector(x) container_of(x, struct drm_connector, base)
#define obj_to_encoder(x) container_of(x, struct drm_encoder, base)
@@ -875,9 +1124,6 @@ extern int drm_crtc_init_with_planes(struct drm_device *dev,
struct drm_plane *primary,
struct drm_plane *cursor,
const struct drm_crtc_funcs *funcs);
extern int drm_crtc_init(struct drm_device *dev,
struct drm_crtc *crtc,
const struct drm_crtc_funcs *funcs);
extern void drm_crtc_cleanup(struct drm_crtc *crtc);
extern unsigned int drm_crtc_index(struct drm_crtc *crtc);
@@ -903,6 +1149,7 @@ int drm_connector_register(struct drm_connector *connector);
void drm_connector_unregister(struct drm_connector *connector);
extern void drm_connector_cleanup(struct drm_connector *connector);
extern unsigned int drm_connector_index(struct drm_connector *connector);
/* helper to unplug all connectors from sysfs for device */
extern void drm_connector_unplug_all(struct drm_device *dev);
@@ -942,6 +1189,7 @@ extern int drm_plane_init(struct drm_device *dev,
const uint32_t *formats, uint32_t format_count,
bool is_primary);
extern void drm_plane_cleanup(struct drm_plane *plane);
extern unsigned int drm_plane_index(struct drm_plane *plane);
extern void drm_plane_force_disable(struct drm_plane *plane);
extern int drm_crtc_check_viewport(const struct drm_crtc *crtc,
int x, int y,
@@ -971,9 +1219,10 @@ extern void drm_mode_config_reset(struct drm_device *dev);
extern void drm_mode_config_cleanup(struct drm_device *dev);
extern int drm_mode_connector_set_path_property(struct drm_connector *connector,
char *path);
const char *path);
int drm_mode_connector_set_tile_property(struct drm_connector *connector);
extern int drm_mode_connector_update_edid_property(struct drm_connector *connector,
struct edid *edid);
const struct edid *edid);
static inline bool drm_property_type_is(struct drm_property *property,
uint32_t type)
@@ -1034,11 +1283,13 @@ extern void drm_property_destroy(struct drm_device *dev, struct drm_property *pr
extern int drm_property_add_enum(struct drm_property *property, int index,
uint64_t value, const char *name);
extern int drm_mode_create_dvi_i_properties(struct drm_device *dev);
extern int drm_mode_create_tv_properties(struct drm_device *dev, int num_formats,
char *formats[]);
extern int drm_mode_create_tv_properties(struct drm_device *dev,
unsigned int num_modes,
char *modes[]);
extern int drm_mode_create_scaling_mode_property(struct drm_device *dev);
extern int drm_mode_create_aspect_ratio_property(struct drm_device *dev);
extern int drm_mode_create_dirty_info_property(struct drm_device *dev);
extern int drm_mode_create_suggested_offset_properties(struct drm_device *dev);
extern int drm_mode_connector_attach_encoder(struct drm_connector *connector,
struct drm_encoder *encoder);
@@ -1106,6 +1357,13 @@ extern void drm_set_preferred_mode(struct drm_connector *connector,
extern int drm_edid_header_is_valid(const u8 *raw_edid);
extern bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid);
extern bool drm_edid_is_valid(struct edid *edid);
extern struct drm_tile_group *drm_mode_create_tile_group(struct drm_device *dev,
char topology[8]);
extern struct drm_tile_group *drm_mode_get_tile_group(struct drm_device *dev,
char topology[8]);
extern void drm_mode_put_tile_group(struct drm_device *dev,
struct drm_tile_group *tg);
struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
int hsize, int vsize, int fresh,
bool rb);
@@ -1120,6 +1378,9 @@ extern int drm_mode_obj_get_properties_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int drm_mode_obj_set_property_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int drm_mode_plane_set_obj_prop(struct drm_plane *plane,
struct drm_property *property,
uint64_t value);
extern void drm_fb_get_bpp_depth(uint32_t format, unsigned int *depth,
int *bpp);

13
include/drm/drm_crtc_helper.h
View File

@@ -68,6 +68,7 @@ struct drm_crtc_helper_funcs {
int (*mode_set)(struct drm_crtc *crtc, struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode, int x, int y,
struct drm_framebuffer *old_fb);
void (*mode_set_nofb)(struct drm_crtc *crtc);
/* Move the crtc on the current fb to the given position *optional* */
int (*mode_set_base)(struct drm_crtc *crtc, int x, int y,
@@ -81,6 +82,12 @@ struct drm_crtc_helper_funcs {
/* disable crtc when not in use - more explicit than dpms off */
void (*disable)(struct drm_crtc *crtc);
/* atomic helpers */
int (*atomic_check)(struct drm_crtc *crtc,
struct drm_crtc_state *state);
void (*atomic_begin)(struct drm_crtc *crtc);
void (*atomic_flush)(struct drm_crtc *crtc);
};
/**
@@ -161,6 +168,12 @@ static inline void drm_connector_helper_add(struct drm_connector *connector,
extern void drm_helper_resume_force_mode(struct drm_device *dev);
int drm_helper_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode, int x, int y,
struct drm_framebuffer *old_fb);
int drm_helper_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
struct drm_framebuffer *old_fb);
/* drm_probe_helper.c */
extern int drm_helper_probe_single_connector_modes(struct drm_connector
*connector, uint32_t maxX,

76
include/drm/drm_displayid.h Normal file
View File

@@ -0,0 +1,76 @@
/*
* Copyright © 2014 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef DRM_DISPLAYID_H
#define DRM_DISPLAYID_H
#define DATA_BLOCK_PRODUCT_ID 0x00
#define DATA_BLOCK_DISPLAY_PARAMETERS 0x01
#define DATA_BLOCK_COLOR_CHARACTERISTICS 0x02
#define DATA_BLOCK_TYPE_1_DETAILED_TIMING 0x03
#define DATA_BLOCK_TYPE_2_DETAILED_TIMING 0x04
#define DATA_BLOCK_TYPE_3_SHORT_TIMING 0x05
#define DATA_BLOCK_TYPE_4_DMT_TIMING 0x06
#define DATA_BLOCK_VESA_TIMING 0x07
#define DATA_BLOCK_CEA_TIMING 0x08
#define DATA_BLOCK_VIDEO_TIMING_RANGE 0x09
#define DATA_BLOCK_PRODUCT_SERIAL_NUMBER 0x0a
#define DATA_BLOCK_GP_ASCII_STRING 0x0b
#define DATA_BLOCK_DISPLAY_DEVICE_DATA 0x0c
#define DATA_BLOCK_INTERFACE_POWER_SEQUENCING 0x0d
#define DATA_BLOCK_TRANSFER_CHARACTERISTICS 0x0e
#define DATA_BLOCK_DISPLAY_INTERFACE 0x0f
#define DATA_BLOCK_STEREO_DISPLAY_INTERFACE 0x10
#define DATA_BLOCK_TILED_DISPLAY 0x12
#define DATA_BLOCK_VENDOR_SPECIFIC 0x7f
#define PRODUCT_TYPE_EXTENSION 0
#define PRODUCT_TYPE_TEST 1
#define PRODUCT_TYPE_PANEL 2
#define PRODUCT_TYPE_MONITOR 3
#define PRODUCT_TYPE_TV 4
#define PRODUCT_TYPE_REPEATER 5
#define PRODUCT_TYPE_DIRECT_DRIVE 6
struct displayid_hdr {
u8 rev;
u8 bytes;
u8 prod_id;
u8 ext_count;
} __packed;
struct displayid_block {
u8 tag;
u8 rev;
u8 num_bytes;
} __packed;
struct displayid_tiled_block {
struct displayid_block base;
u8 tile_cap;
u8 topo[3];
u8 tile_size[4];
u8 tile_pixel_bezel[5];
u8 topology_id[8];
} __packed;
#endif

42
include/drm/drm_dp_helper.h
View File

@@ -190,16 +190,16 @@
# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
@@ -303,7 +303,8 @@
#define DP_TEST_CRC_B_CB 0x244
#define DP_TEST_SINK_MISC 0x246
#define DP_TEST_CRC_SUPPORTED (1 << 5)
# define DP_TEST_CRC_SUPPORTED (1 << 5)
# define DP_TEST_COUNT_MASK 0x7
#define DP_TEST_RESPONSE 0x260
# define DP_TEST_ACK (1 << 0)
@@ -313,7 +314,7 @@
#define DP_TEST_EDID_CHECKSUM 0x261
#define DP_TEST_SINK 0x270
#define DP_TEST_SINK_START (1 << 0)
# define DP_TEST_SINK_START (1 << 0)
#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
@@ -404,26 +405,6 @@
#define MODE_I2C_READ 4
#define MODE_I2C_STOP 8
/**
* struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
* aux algorithm
* @running: set by the algo indicating whether an i2c is ongoing or whether
* the i2c bus is quiescent
* @address: i2c target address for the currently ongoing transfer
* @aux_ch: driver callback to transfer a single byte of the i2c payload
*/
struct i2c_algo_dp_aux_data {
bool running;
u16 address;
int (*aux_ch) (struct i2c_adapter *adapter,
int mode, uint8_t write_byte,
uint8_t *read_byte);
};
int
i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
#define DP_LINK_STATUS_SIZE 6
bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
int lane_count);
@@ -550,6 +531,7 @@ struct drm_dp_aux {
struct mutex hw_mutex;
ssize_t (*transfer)(struct drm_dp_aux *aux,
struct drm_dp_aux_msg *msg);
unsigned i2c_nack_count, i2c_defer_count;
};
ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,

10
include/drm/drm_dp_mst_helper.h
View File

@@ -28,7 +28,7 @@
struct drm_dp_mst_branch;
/**
* struct drm_dp_vcpi - Virtual Channel Payload Identifer
* struct drm_dp_vcpi - Virtual Channel Payload Identifier
* @vcpi: Virtual channel ID.
* @pbn: Payload Bandwidth Number for this channel
* @aligned_pbn: PBN aligned with slot size
@@ -92,6 +92,8 @@ struct drm_dp_mst_port {
struct drm_dp_vcpi vcpi;
struct drm_connector *connector;
struct drm_dp_mst_topology_mgr *mgr;
struct edid *cached_edid; /* for DP logical ports - make tiling work */
};
/**
@@ -371,7 +373,7 @@ struct drm_dp_sideband_msg_tx {
struct drm_dp_mst_topology_mgr;
struct drm_dp_mst_topology_cbs {
/* create a connector for a port */
struct drm_connector *(*add_connector)(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, char *path);
struct drm_connector *(*add_connector)(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *path);
void (*destroy_connector)(struct drm_dp_mst_topology_mgr *mgr,
struct drm_connector *connector);
void (*hotplug)(struct drm_dp_mst_topology_mgr *mgr);
@@ -388,6 +390,7 @@ struct drm_dp_payload {
int payload_state;
int start_slot;
int num_slots;
int vcpi;
};
/**
@@ -454,6 +457,7 @@ struct drm_dp_mst_topology_mgr {
struct drm_dp_vcpi **proposed_vcpis;
struct drm_dp_payload *payloads;
unsigned long payload_mask;
unsigned long vcpi_mask;
wait_queue_head_t tx_waitq;
struct work_struct work;
@@ -472,7 +476,7 @@ int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool ms
int drm_dp_mst_hpd_irq(struct drm_dp_mst_topology_mgr *mgr, u8 *esi, bool *handled);
enum drm_connector_status drm_dp_mst_detect_port(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
enum drm_connector_status drm_dp_mst_detect_port(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);
struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port);

109
include/drm/drm_edid.h
View File

@@ -27,12 +27,14 @@
#define EDID_LENGTH 128
#define DDC_ADDR 0x50
#define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */
#define CEA_EXT 0x02
#define VTB_EXT 0x10
#define DI_EXT 0x40
#define LS_EXT 0x50
#define MI_EXT 0x60
#define DISPLAYID_EXT 0x70
struct est_timings {
u8 t1;
@@ -207,6 +209,61 @@ struct detailed_timing {
#define DRM_EDID_HDMI_DC_30 (1 << 4)
#define DRM_EDID_HDMI_DC_Y444 (1 << 3)
/* ELD Header Block */
#define DRM_ELD_HEADER_BLOCK_SIZE 4
#define DRM_ELD_VER 0
# define DRM_ELD_VER_SHIFT 3
# define DRM_ELD_VER_MASK (0x1f << 3)
#define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */
/* ELD Baseline Block for ELD_Ver == 2 */
#define DRM_ELD_CEA_EDID_VER_MNL 4
# define DRM_ELD_CEA_EDID_VER_SHIFT 5
# define DRM_ELD_CEA_EDID_VER_MASK (7 << 5)
# define DRM_ELD_CEA_EDID_VER_NONE (0 << 5)
# define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5)
# define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5)
# define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5)
# define DRM_ELD_MNL_SHIFT 0
# define DRM_ELD_MNL_MASK (0x1f << 0)
#define DRM_ELD_SAD_COUNT_CONN_TYPE 5
# define DRM_ELD_SAD_COUNT_SHIFT 4
# define DRM_ELD_SAD_COUNT_MASK (0xf << 4)
# define DRM_ELD_CONN_TYPE_SHIFT 2
# define DRM_ELD_CONN_TYPE_MASK (3 << 2)
# define DRM_ELD_CONN_TYPE_HDMI (0 << 2)
# define DRM_ELD_CONN_TYPE_DP (1 << 2)
# define DRM_ELD_SUPPORTS_AI (1 << 1)
# define DRM_ELD_SUPPORTS_HDCP (1 << 0)
#define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */
# define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */
#define DRM_ELD_SPEAKER 7
# define DRM_ELD_SPEAKER_RLRC (1 << 6)
# define DRM_ELD_SPEAKER_FLRC (1 << 5)
# define DRM_ELD_SPEAKER_RC (1 << 4)
# define DRM_ELD_SPEAKER_RLR (1 << 3)
# define DRM_ELD_SPEAKER_FC (1 << 2)
# define DRM_ELD_SPEAKER_LFE (1 << 1)
# define DRM_ELD_SPEAKER_FLR (1 << 0)
#define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */
# define DRM_ELD_PORT_ID_LEN 8
#define DRM_ELD_MANUFACTURER_NAME0 16
#define DRM_ELD_MANUFACTURER_NAME1 17
#define DRM_ELD_PRODUCT_CODE0 18
#define DRM_ELD_PRODUCT_CODE1 19
#define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */
#define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad))
struct edid {
u8 header[8];
/* Vendor & product info */
@@ -279,4 +336,56 @@ int
drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
const struct drm_display_mode *mode);
/**
* drm_eld_mnl - Get ELD monitor name length in bytes.
* @eld: pointer to an eld memory structure with mnl set
*/
static inline int drm_eld_mnl(const uint8_t *eld)
{
return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT;
}
/**
* drm_eld_sad_count - Get ELD SAD count.
* @eld: pointer to an eld memory structure with sad_count set
*/
static inline int drm_eld_sad_count(const uint8_t *eld)
{
return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >>
DRM_ELD_SAD_COUNT_SHIFT;
}
/**
* drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes
* @eld: pointer to an eld memory structure with mnl and sad_count set
*
* This is a helper for determining the payload size of the baseline block, in
* bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block.
*/
static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld)
{
return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE +
drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3;
}
/**
* drm_eld_size - Get ELD size in bytes
* @eld: pointer to a complete eld memory structure
*
* The returned value does not include the vendor block. It's vendor specific,
* and comprises of the remaining bytes in the ELD memory buffer after
* drm_eld_size() bytes of header and baseline block.
*
* The returned value is guaranteed to be a multiple of 4.
*/
static inline int drm_eld_size(const uint8_t *eld)
{
return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4;
}
struct edid *drm_do_get_edid(struct drm_connector *connector,
int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
size_t len),
void *data);
#endif /* __DRM_EDID_H__ */

7
include/drm/drm_fb_helper.h
View File

@@ -34,9 +34,14 @@ struct drm_fb_helper;
#include <linux/kgdb.h>
struct drm_fb_offset {
int x, y;
};
struct drm_fb_helper_crtc {
struct drm_mode_set mode_set;
struct drm_display_mode *desired_mode;
int x, y;
};
struct drm_fb_helper_surface_size {
@@ -72,12 +77,12 @@ struct drm_fb_helper_funcs {
bool (*initial_config)(struct drm_fb_helper *fb_helper,
struct drm_fb_helper_crtc **crtcs,
struct drm_display_mode **modes,
struct drm_fb_offset *offsets,
bool *enabled, int width, int height);
};
struct drm_fb_helper_connector {
struct drm_connector *connector;
struct drm_cmdline_mode cmdline_mode;
};
struct drm_fb_helper {

33
include/drm/drm_flip_work.h
View File

@@ -25,6 +25,7 @@
#define DRM_FLIP_WORK_H
#include <linux/kfifo.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
/**
@@ -32,9 +33,9 @@
*
* Util to queue up work to run from work-queue context after flip/vblank.
* Typically this can be used to defer unref of framebuffer's, cursor
* bo's, etc until after vblank. The APIs are all safe (and lockless)
* for up to one producer and once consumer at a time. The single-consumer
* aspect is ensured by committing the queued work to a single work-queue.
* bo's, etc until after vblank. The APIs are all thread-safe.
* Moreover, drm_flip_work_queue_task and drm_flip_work_queue can be called
* in atomic context.
*/
struct drm_flip_work;
@@ -50,27 +51,41 @@ struct drm_flip_work;
*/
typedef void (*drm_flip_func_t)(struct drm_flip_work *work, void *val);
/**
* struct drm_flip_task - flip work task
* @node: list entry element
* @data: data to pass to work->func
*/
struct drm_flip_task {
struct list_head node;
void *data;
};
/**
* struct drm_flip_work - flip work queue
* @name: debug name
* @pending: number of queued but not committed items
* @count: number of committed items
* @func: callback fxn called for each committed item
* @worker: worker which calls @func
* @fifo: queue of committed items
* @queued: queued tasks
* @commited: commited tasks
* @lock: lock to access queued and commited lists
*/
struct drm_flip_work {
const char *name;
atomic_t pending, count;
drm_flip_func_t func;
struct work_struct worker;
DECLARE_KFIFO_PTR(fifo, void *);
struct list_head queued;
struct list_head commited;
spinlock_t lock;
};
struct drm_flip_task *drm_flip_work_allocate_task(void *data, gfp_t flags);
void drm_flip_work_queue_task(struct drm_flip_work *work,
struct drm_flip_task *task);
void drm_flip_work_queue(struct drm_flip_work *work, void *val);
void drm_flip_work_commit(struct drm_flip_work *work,
struct workqueue_struct *wq);
int drm_flip_work_init(struct drm_flip_work *work, int size,
void drm_flip_work_init(struct drm_flip_work *work,
const char *name, drm_flip_func_t func);
void drm_flip_work_cleanup(struct drm_flip_work *work);

183
include/drm/drm_gem.h Normal file
View File

@@ -0,0 +1,183 @@
#ifndef __DRM_GEM_H__
#define __DRM_GEM_H__
/*
* GEM Graphics Execution Manager Driver Interfaces
*
* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
* Copyright (c) 2009-2010, Code Aurora Forum.
* All rights reserved.
* Copyright © 2014 Intel Corporation
* Daniel Vetter <daniel.vetter@ffwll.ch>
*
* Author: Rickard E. (Rik) Faith <faith@valinux.com>
* Author: Gareth Hughes <gareth@valinux.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/**
* This structure defines the drm_mm memory object, which will be used by the
* DRM for its buffer objects.
*/
struct drm_gem_object {
/** Reference count of this object */
struct kref refcount;
/**
* handle_count - gem file_priv handle count of this object
*
* Each handle also holds a reference. Note that when the handle_count
* drops to 0 any global names (e.g. the id in the flink namespace) will
* be cleared.
*
* Protected by dev->object_name_lock.
* */
unsigned handle_count;
/** Related drm device */
struct drm_device *dev;
/** File representing the shmem storage */
struct file *filp;
/* Mapping info for this object */
struct drm_vma_offset_node vma_node;
/**
* Size of the object, in bytes. Immutable over the object's
* lifetime.
*/
size_t size;
/**
* Global name for this object, starts at 1. 0 means unnamed.
* Access is covered by the object_name_lock in the related drm_device
*/
int name;
/**
* Memory domains. These monitor which caches contain read/write data
* related to the object. When transitioning from one set of domains
* to another, the driver is called to ensure that caches are suitably
* flushed and invalidated
*/
uint32_t read_domains;
uint32_t write_domain;
/**
* While validating an exec operation, the
* new read/write domain values are computed here.
* They will be transferred to the above values
* at the point that any cache flushing occurs
*/
uint32_t pending_read_domains;
uint32_t pending_write_domain;
/**
* dma_buf - dma buf associated with this GEM object
*
* Pointer to the dma-buf associated with this gem object (either
* through importing or exporting). We break the resulting reference
* loop when the last gem handle for this object is released.
*
* Protected by obj->object_name_lock
*/
struct dma_buf *dma_buf;
/**
* import_attach - dma buf attachment backing this object
*
* Any foreign dma_buf imported as a gem object has this set to the
* attachment point for the device. This is invariant over the lifetime
* of a gem object.
*
* The driver's ->gem_free_object callback is responsible for cleaning
* up the dma_buf attachment and references acquired at import time.
*
* Note that the drm gem/prime core does not depend upon drivers setting
* this field any more. So for drivers where this doesn't make sense
* (e.g. virtual devices or a displaylink behind an usb bus) they can
* simply leave it as NULL.
*/
struct dma_buf_attachment *import_attach;
};
void drm_gem_object_release(struct drm_gem_object *obj);
void drm_gem_object_free(struct kref *kref);
int drm_gem_object_init(struct drm_device *dev,
struct drm_gem_object *obj, size_t size);
void drm_gem_private_object_init(struct drm_device *dev,
struct drm_gem_object *obj, size_t size);
void drm_gem_vm_open(struct vm_area_struct *vma);
void drm_gem_vm_close(struct vm_area_struct *vma);
int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size,
struct vm_area_struct *vma);
int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
static inline void
drm_gem_object_reference(struct drm_gem_object *obj)
{
kref_get(&obj->refcount);
}
static inline void
drm_gem_object_unreference(struct drm_gem_object *obj)
{
if (obj != NULL)
kref_put(&obj->refcount, drm_gem_object_free);
}
static inline void
drm_gem_object_unreference_unlocked(struct drm_gem_object *obj)
{
if (obj && !atomic_add_unless(&obj->refcount.refcount, -1, 1)) {
struct drm_device *dev = obj->dev;
mutex_lock(&dev->struct_mutex);
if (likely(atomic_dec_and_test(&obj->refcount.refcount)))
drm_gem_object_free(&obj->refcount);
mutex_unlock(&dev->struct_mutex);
}
}
int drm_gem_handle_create(struct drm_file *file_priv,
struct drm_gem_object *obj,
u32 *handlep);
int drm_gem_handle_delete(struct drm_file *filp, u32 handle);
void drm_gem_free_mmap_offset(struct drm_gem_object *obj);
int drm_gem_create_mmap_offset(struct drm_gem_object *obj);
int drm_gem_create_mmap_offset_size(struct drm_gem_object *obj, size_t size);
struct page **drm_gem_get_pages(struct drm_gem_object *obj);
void drm_gem_put_pages(struct drm_gem_object *obj, struct page **pages,
bool dirty, bool accessed);
struct drm_gem_object *drm_gem_object_lookup(struct drm_device *dev,
struct drm_file *filp,
u32 handle);
int drm_gem_dumb_destroy(struct drm_file *file,
struct drm_device *dev,
uint32_t handle);
#endif /* __DRM_GEM_H__ */

34
include/drm/drm_gem_cma_helper.h
View File

@@ -2,7 +2,15 @@
#define __DRM_GEM_CMA_HELPER_H__
#include <drm/drmP.h>
#include <drm/drm_gem.h>
/**
* struct drm_gem_cma_object - GEM object backed by CMA memory allocations
* @base: base GEM object
* @paddr: physical address of the backing memory
* @sgt: scatter/gather table for imported PRIME buffers
* @vaddr: kernel virtual address of the backing memory
*/
struct drm_gem_cma_object {
struct drm_gem_object base;
dma_addr_t paddr;
@@ -18,23 +26,30 @@ to_drm_gem_cma_obj(struct drm_gem_object *gem_obj)
return container_of(gem_obj, struct drm_gem_cma_object, base);
}
/* free gem object. */
/* free GEM object */
void drm_gem_cma_free_object(struct drm_gem_object *gem_obj);
/* create memory region for drm framebuffer. */
/* create memory region for DRM framebuffer */
int drm_gem_cma_dumb_create_internal(struct drm_file *file_priv,
struct drm_device *drm,
struct drm_mode_create_dumb *args);
/* create memory region for DRM framebuffer */
int drm_gem_cma_dumb_create(struct drm_file *file_priv,
struct drm_device *drm, struct drm_mode_create_dumb *args);
struct drm_device *drm,
struct drm_mode_create_dumb *args);
/* map memory region for drm framebuffer to user space. */
/* map memory region for DRM framebuffer to user space */
int drm_gem_cma_dumb_map_offset(struct drm_file *file_priv,
struct drm_device *drm, uint32_t handle, uint64_t *offset);
struct drm_device *drm, u32 handle,
u64 *offset);
/* set vm_flags and we can change the vm attribute to other one at here. */
/* set vm_flags and we can change the VM attribute to other one at here */
int drm_gem_cma_mmap(struct file *filp, struct vm_area_struct *vma);
/* allocate physical memory. */
/* allocate physical memory */
struct drm_gem_cma_object *drm_gem_cma_create(struct drm_device *drm,
unsigned int size);
size_t size);
extern const struct vm_operations_struct drm_gem_cma_vm_ops;
@@ -44,7 +59,8 @@ void drm_gem_cma_describe(struct drm_gem_cma_object *obj, struct seq_file *m);
struct sg_table *drm_gem_cma_prime_get_sg_table(struct drm_gem_object *obj);
struct drm_gem_object *
drm_gem_cma_prime_import_sg_table(struct drm_device *dev, size_t size,
drm_gem_cma_prime_import_sg_table(struct drm_device *dev,
struct dma_buf_attachment *attach,
struct sg_table *sgt);
int drm_gem_cma_prime_mmap(struct drm_gem_object *obj,
struct vm_area_struct *vma);

203
include/drm/drm_legacy.h Normal file
View File

@@ -0,0 +1,203 @@
#ifndef __DRM_DRM_LEGACY_H__
#define __DRM_DRM_LEGACY_H__
/*
* Legacy driver interfaces for the Direct Rendering Manager
*
* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
* Copyright (c) 2009-2010, Code Aurora Forum.
* All rights reserved.
* Copyright © 2014 Intel Corporation
* Daniel Vetter <daniel.vetter@ffwll.ch>
*
* Author: Rickard E. (Rik) Faith <faith@valinux.com>
* Author: Gareth Hughes <gareth@valinux.com>
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Legacy Support for palateontologic DRM drivers
*
* If you add a new driver and it uses any of these functions or structures,
* you're doing it terribly wrong.
*/
/**
* DMA buffer.
*/
struct drm_buf {
int idx; /**< Index into master buflist */
int total; /**< Buffer size */
int order; /**< log-base-2(total) */
int used; /**< Amount of buffer in use (for DMA) */
unsigned long offset; /**< Byte offset (used internally) */
void *address; /**< Address of buffer */
unsigned long bus_address; /**< Bus address of buffer */
struct drm_buf *next; /**< Kernel-only: used for free list */
__volatile__ int waiting; /**< On kernel DMA queue */
__volatile__ int pending; /**< On hardware DMA queue */
struct drm_file *file_priv; /**< Private of holding file descr */
int context; /**< Kernel queue for this buffer */
int while_locked; /**< Dispatch this buffer while locked */
enum {
DRM_LIST_NONE = 0,
DRM_LIST_FREE = 1,
DRM_LIST_WAIT = 2,
DRM_LIST_PEND = 3,
DRM_LIST_PRIO = 4,
DRM_LIST_RECLAIM = 5
} list; /**< Which list we're on */
int dev_priv_size; /**< Size of buffer private storage */
void *dev_private; /**< Per-buffer private storage */
};
typedef struct drm_dma_handle {
dma_addr_t busaddr;
void *vaddr;
size_t size;
} drm_dma_handle_t;
/**
* Buffer entry. There is one of this for each buffer size order.
*/
struct drm_buf_entry {
int buf_size; /**< size */
int buf_count; /**< number of buffers */
struct drm_buf *buflist; /**< buffer list */
int seg_count;
int page_order;
struct drm_dma_handle **seglist;
int low_mark; /**< Low water mark */
int high_mark; /**< High water mark */
};
/**
* DMA data.
*/
struct drm_device_dma {
struct drm_buf_entry bufs[DRM_MAX_ORDER + 1]; /**< buffers, grouped by their size order */
int buf_count; /**< total number of buffers */
struct drm_buf **buflist; /**< Vector of pointers into drm_device_dma::bufs */
int seg_count;
int page_count; /**< number of pages */
unsigned long *pagelist; /**< page list */
unsigned long byte_count;
enum {
_DRM_DMA_USE_AGP = 0x01,
_DRM_DMA_USE_SG = 0x02,
_DRM_DMA_USE_FB = 0x04,
_DRM_DMA_USE_PCI_RO = 0x08
} flags;
};
/**
* Scatter-gather memory.
*/
struct drm_sg_mem {
unsigned long handle;
void *virtual;
int pages;
struct page **pagelist;
dma_addr_t *busaddr;
};
/**
* Kernel side of a mapping
*/
struct drm_local_map {
resource_size_t offset; /**< Requested physical address (0 for SAREA)*/
unsigned long size; /**< Requested physical size (bytes) */
enum drm_map_type type; /**< Type of memory to map */
enum drm_map_flags flags; /**< Flags */
void *handle; /**< User-space: "Handle" to pass to mmap() */
/**< Kernel-space: kernel-virtual address */
int mtrr; /**< MTRR slot used */
};
typedef struct drm_local_map drm_local_map_t;
/**
* Mappings list
*/
struct drm_map_list {
struct list_head head; /**< list head */
struct drm_hash_item hash;
struct drm_local_map *map; /**< mapping */
uint64_t user_token;
struct drm_master *master;
};
int drm_legacy_addmap(struct drm_device *d, resource_size_t offset,
unsigned int size, enum drm_map_type type,
enum drm_map_flags flags, struct drm_local_map **map_p);
int drm_legacy_rmmap(struct drm_device *d, struct drm_local_map *map);
int drm_legacy_rmmap_locked(struct drm_device *d, struct drm_local_map *map);
struct drm_local_map *drm_legacy_getsarea(struct drm_device *dev);
int drm_legacy_mmap(struct file *filp, struct vm_area_struct *vma);
int drm_legacy_addbufs_agp(struct drm_device *d, struct drm_buf_desc *req);
int drm_legacy_addbufs_pci(struct drm_device *d, struct drm_buf_desc *req);
/**
* Test that the hardware lock is held by the caller, returning otherwise.
*
* \param dev DRM device.
* \param filp file pointer of the caller.
*/
#define LOCK_TEST_WITH_RETURN( dev, _file_priv ) \
do { \
if (!_DRM_LOCK_IS_HELD(_file_priv->master->lock.hw_lock->lock) || \
_file_priv->master->lock.file_priv != _file_priv) { \
DRM_ERROR( "%s called without lock held, held %d owner %p %p\n",\
__func__, _DRM_LOCK_IS_HELD(_file_priv->master->lock.hw_lock->lock),\
_file_priv->master->lock.file_priv, _file_priv); \
return -EINVAL; \
} \
} while (0)
void drm_legacy_idlelock_take(struct drm_lock_data *lock);
void drm_legacy_idlelock_release(struct drm_lock_data *lock);
/* drm_pci.c dma alloc wrappers */
void __drm_legacy_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah);
/* drm_memory.c */
void drm_legacy_ioremap(struct drm_local_map *map, struct drm_device *dev);
void drm_legacy_ioremap_wc(struct drm_local_map *map, struct drm_device *dev);
void drm_legacy_ioremapfree(struct drm_local_map *map, struct drm_device *dev);
static __inline__ struct drm_local_map *drm_legacy_findmap(struct drm_device *dev,
unsigned int token)
{
struct drm_map_list *_entry;
list_for_each_entry(_entry, &dev->maplist, head)
if (_entry->user_token == token)
return _entry->map;
return NULL;
}
#endif /* __DRM_DRM_LEGACY_H__ */

59
include/drm/drm_memory.h
View File

@@ -1,59 +0,0 @@
/**
* \file drm_memory.h
* Memory management wrappers for DRM
*
* \author Rickard E. (Rik) Faith <faith@valinux.com>
* \author Gareth Hughes <gareth@valinux.com>
*/
/*
* Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com
*
* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <linux/highmem.h>
#include <linux/vmalloc.h>
#include <drm/drmP.h>
/**
* Cut down version of drm_memory_debug.h, which used to be called
* drm_memory.h.
*/
#if __OS_HAS_AGP
#ifdef HAVE_PAGE_AGP
#include <asm/agp.h>
#else
# ifdef __powerpc__
# define PAGE_AGP __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
# else
# define PAGE_AGP PAGE_KERNEL
# endif
#endif
#else /* __OS_HAS_AGP */
#endif

96
include/drm/drm_mipi_dsi.h
View File

@@ -26,6 +26,7 @@ struct mipi_dsi_device;
* struct mipi_dsi_msg - read/write DSI buffer
* @channel: virtual channel id
* @type: payload data type
* @flags: flags controlling this message transmission
* @tx_len: length of @tx_buf
* @tx_buf: data to be written
* @rx_len: length of @rx_buf
@@ -43,12 +44,44 @@ struct mipi_dsi_msg {
void *rx_buf;
};
bool mipi_dsi_packet_format_is_short(u8 type);
bool mipi_dsi_packet_format_is_long(u8 type);
/**
* struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format
* @size: size (in bytes) of the packet
* @header: the four bytes that make up the header (Data ID, Word Count or
* Packet Data, and ECC)
* @payload_length: number of bytes in the payload
* @payload: a pointer to a buffer containing the payload, if any
*/
struct mipi_dsi_packet {
size_t size;
u8 header[4];
size_t payload_length;
const u8 *payload;
};
int mipi_dsi_create_packet(struct mipi_dsi_packet *packet,
const struct mipi_dsi_msg *msg);
/**
* struct mipi_dsi_host_ops - DSI bus operations
* @attach: attach DSI device to DSI host
* @detach: detach DSI device from DSI host
* @transfer: send and/or receive DSI packet, return number of received bytes,
* or error
* @transfer: transmit a DSI packet
*
* DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg
* structures. This structure contains information about the type of packet
* being transmitted as well as the transmit and receive buffers. When an
* error is encountered during transmission, this function will return a
* negative error code. On success it shall return the number of bytes
* transmitted for write packets or the number of bytes received for read
* packets.
*
* Note that typically DSI packet transmission is atomic, so the .transfer()
* function will seldomly return anything other than the number of bytes
* contained in the transmit buffer on success.
*/
struct mipi_dsi_host_ops {
int (*attach)(struct mipi_dsi_host *host,
@@ -56,7 +89,7 @@ struct mipi_dsi_host_ops {
int (*detach)(struct mipi_dsi_host *host,
struct mipi_dsi_device *dsi);
ssize_t (*transfer)(struct mipi_dsi_host *host,
struct mipi_dsi_msg *msg);
const struct mipi_dsi_msg *msg);
};
/**
@@ -96,6 +129,8 @@ void mipi_dsi_host_unregister(struct mipi_dsi_host *host);
#define MIPI_DSI_MODE_EOT_PACKET BIT(9)
/* device supports non-continuous clock behavior (DSI spec 5.6.1) */
#define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10)
/* transmit data in low power */
#define MIPI_DSI_MODE_LPM BIT(11)
enum mipi_dsi_pixel_format {
MIPI_DSI_FMT_RGB888,
@@ -128,12 +163,57 @@ static inline struct mipi_dsi_device *to_mipi_dsi_device(struct device *dev)
return container_of(dev, struct mipi_dsi_device, dev);
}
struct mipi_dsi_device *of_find_mipi_dsi_device_by_node(struct device_node *np);
int mipi_dsi_attach(struct mipi_dsi_device *dsi);
int mipi_dsi_detach(struct mipi_dsi_device *dsi);
ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, const void *data,
size_t len);
int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
u16 value);
ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *payload,
size_t size);
ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, const void *params,
size_t num_params, void *data, size_t size);
/**
* enum mipi_dsi_dcs_tear_mode - Tearing Effect Output Line mode
* @MIPI_DSI_DCS_TEAR_MODE_VBLANK: the TE output line consists of V-Blanking
* information only
* @MIPI_DSI_DCS_TEAR_MODE_VHBLANK : the TE output line consists of both
* V-Blanking and H-Blanking information
*/
enum mipi_dsi_dcs_tear_mode {
MIPI_DSI_DCS_TEAR_MODE_VBLANK,
MIPI_DSI_DCS_TEAR_MODE_VHBLANK,
};
#define MIPI_DSI_DCS_POWER_MODE_DISPLAY (1 << 2)
#define MIPI_DSI_DCS_POWER_MODE_NORMAL (1 << 3)
#define MIPI_DSI_DCS_POWER_MODE_SLEEP (1 << 4)
#define MIPI_DSI_DCS_POWER_MODE_PARTIAL (1 << 5)
#define MIPI_DSI_DCS_POWER_MODE_IDLE (1 << 6)
ssize_t mipi_dsi_dcs_write_buffer(struct mipi_dsi_device *dsi,
const void *data, size_t len);
ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd,
const void *data, size_t len);
ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, u8 cmd, void *data,
size_t len);
int mipi_dsi_dcs_nop(struct mipi_dsi_device *dsi);
int mipi_dsi_dcs_soft_reset(struct mipi_dsi_device *dsi);
int mipi_dsi_dcs_get_power_mode(struct mipi_dsi_device *dsi, u8 *mode);
int mipi_dsi_dcs_get_pixel_format(struct mipi_dsi_device *dsi, u8 *format);
int mipi_dsi_dcs_enter_sleep_mode(struct mipi_dsi_device *dsi);
int mipi_dsi_dcs_exit_sleep_mode(struct mipi_dsi_device *dsi);
int mipi_dsi_dcs_set_display_off(struct mipi_dsi_device *dsi);
int mipi_dsi_dcs_set_display_on(struct mipi_dsi_device *dsi);
int mipi_dsi_dcs_set_column_address(struct mipi_dsi_device *dsi, u16 start,
u16 end);
int mipi_dsi_dcs_set_page_address(struct mipi_dsi_device *dsi, u16 start,
u16 end);
int mipi_dsi_dcs_set_tear_off(struct mipi_dsi_device *dsi);
int mipi_dsi_dcs_set_tear_on(struct mipi_dsi_device *dsi,
enum mipi_dsi_dcs_tear_mode mode);
int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format);
/**
* struct mipi_dsi_driver - DSI driver
@@ -165,9 +245,13 @@ static inline void mipi_dsi_set_drvdata(struct mipi_dsi_device *dsi, void *data)
dev_set_drvdata(&dsi->dev, data);
}
int mipi_dsi_driver_register(struct mipi_dsi_driver *driver);
int mipi_dsi_driver_register_full(struct mipi_dsi_driver *driver,
struct module *owner);
void mipi_dsi_driver_unregister(struct mipi_dsi_driver *driver);
#define mipi_dsi_driver_register(driver) \
mipi_dsi_driver_register_full(driver, THIS_MODULE)
#define module_mipi_dsi_driver(__mipi_dsi_driver) \
module_driver(__mipi_dsi_driver, mipi_dsi_driver_register, \
mipi_dsi_driver_unregister)

23
include/drm/drm_modeset_lock.h
View File

@@ -29,10 +29,11 @@
struct drm_modeset_lock;
/**
* drm_modeset_acquire_ctx - locking context (see ww_acquire_ctx)
* struct drm_modeset_acquire_ctx - locking context (see ww_acquire_ctx)
* @ww_ctx: base acquire ctx
* @contended: used internally for -EDEADLK handling
* @locked: list of held locks
* @trylock_only: trylock mode used in atomic contexts/panic notifiers
*
* Each thread competing for a set of locks must use one acquire
* ctx. And if any lock fxn returns -EDEADLK, it must backoff and
@@ -53,10 +54,15 @@ struct drm_modeset_acquire_ctx {
* list of held locks (drm_modeset_lock)
*/
struct list_head locked;
/**
* Trylock mode, use only for panic handlers!
*/
bool trylock_only;
};
/**
* drm_modeset_lock - used for locking modeset resources.
* struct drm_modeset_lock - used for locking modeset resources.
* @mutex: resource locking
* @head: used to hold it's place on state->locked list when
* part of an atomic update
@@ -120,6 +126,19 @@ int drm_modeset_lock_interruptible(struct drm_modeset_lock *lock,
void drm_modeset_unlock(struct drm_modeset_lock *lock);
struct drm_device;
struct drm_crtc;
struct drm_plane;
void drm_modeset_lock_all(struct drm_device *dev);
int __drm_modeset_lock_all(struct drm_device *dev, bool trylock);
void drm_modeset_unlock_all(struct drm_device *dev);
void drm_modeset_lock_crtc(struct drm_crtc *crtc,
struct drm_plane *plane);
void drm_modeset_unlock_crtc(struct drm_crtc *crtc);
void drm_warn_on_modeset_not_all_locked(struct drm_device *dev);
struct drm_modeset_acquire_ctx *
drm_modeset_legacy_acquire_ctx(struct drm_crtc *crtc);
int drm_modeset_lock_all_crtcs(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx);

1
include/drm/drm_pciids.h
View File

@@ -74,7 +74,6 @@
{0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
{0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
{0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
{0x1002, 0x4C6E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
{0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
{0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
{0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \

44
include/drm/drm_plane_helper.h
View File

@@ -25,6 +25,7 @@
#define DRM_PLANE_HELPER_H
#include <drm/drm_rect.h>
#include <drm/drm_crtc.h>
/*
* Drivers that don't allow primary plane scaling may pass this macro in place
@@ -42,6 +43,37 @@
* planes.
*/
extern int drm_crtc_init(struct drm_device *dev,
struct drm_crtc *crtc,
const struct drm_crtc_funcs *funcs);
/**
* drm_plane_helper_funcs - helper operations for CRTCs
* @prepare_fb: prepare a framebuffer for use by the plane
* @cleanup_fb: cleanup a framebuffer when it's no longer used by the plane
* @atomic_check: check that a given atomic state is valid and can be applied
* @atomic_update: apply an atomic state to the plane
*
* The helper operations are called by the mid-layer CRTC helper.
*/
struct drm_plane_helper_funcs {
int (*prepare_fb)(struct drm_plane *plane,
struct drm_framebuffer *fb);
void (*cleanup_fb)(struct drm_plane *plane,
struct drm_framebuffer *fb);
int (*atomic_check)(struct drm_plane *plane,
struct drm_plane_state *state);
void (*atomic_update)(struct drm_plane *plane,
struct drm_plane_state *old_state);
};
static inline void drm_plane_helper_add(struct drm_plane *plane,
const struct drm_plane_helper_funcs *funcs)
{
plane->helper_private = (void *)funcs;
}
extern int drm_plane_helper_check_update(struct drm_plane *plane,
struct drm_crtc *crtc,
struct drm_framebuffer *fb,
@@ -68,4 +100,16 @@ extern struct drm_plane *drm_primary_helper_create_plane(struct drm_device *dev,
int num_formats);
int drm_plane_helper_update(struct drm_plane *plane, struct drm_crtc *crtc,
struct drm_framebuffer *fb,
int crtc_x, int crtc_y,
unsigned int crtc_w, unsigned int crtc_h,
uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h);
int drm_plane_helper_disable(struct drm_plane *plane);
/* For use by drm_crtc_helper.c */
int drm_plane_helper_commit(struct drm_plane *plane,
struct drm_plane_state *plane_state,
struct drm_framebuffer *old_fb);
#endif

15
include/drm/drm_usb.h
View File

@@ -1,15 +0,0 @@
#ifndef DRM_USB_H
#define DRM_USB_H
#include <drmP.h>
#include <linux/usb.h>
extern int drm_usb_init(struct drm_driver *driver, struct usb_driver *udriver);
extern void drm_usb_exit(struct drm_driver *driver, struct usb_driver *udriver);
int drm_get_usb_dev(struct usb_interface *interface,
const struct usb_device_id *id,
struct drm_driver *driver);
#endif

17
include/drm/i915_pciids.h
View File

@@ -259,4 +259,21 @@
INTEL_VGA_DEVICE(0x22b2, info), \
INTEL_VGA_DEVICE(0x22b3, info)
#define INTEL_SKL_IDS(info) \
INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \
INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \
INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \
INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \
INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \
INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \
INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \
INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \
INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \
INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \
INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \
INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \
INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \
INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \
INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */
#endif /* _I915_PCIIDS_H */

49
include/drm/ttm/ttm_bo_api.h
View File

@@ -45,12 +45,24 @@ struct ttm_bo_device;
struct drm_mm_node;
/**
* struct ttm_place
*
* @fpfn: first valid page frame number to put the object
* @lpfn: last valid page frame number to put the object
* @flags: memory domain and caching flags for the object
*
* Structure indicating a possible place to put an object.
*/
struct ttm_place {
unsigned fpfn;
unsigned lpfn;
uint32_t flags;
};
/**
* struct ttm_placement
*
* @fpfn: first valid page frame number to put the object
* @lpfn: last valid page frame number to put the object
* @num_placement: number of preferred placements
* @placement: preferred placements
* @num_busy_placement: number of preferred placements when need to evict buffer
@@ -59,12 +71,10 @@ struct drm_mm_node;
* Structure indicating the placement you request for an object.
*/
struct ttm_placement {
unsigned fpfn;
unsigned lpfn;
unsigned num_placement;
const uint32_t *placement;
unsigned num_busy_placement;
const uint32_t *busy_placement;
unsigned num_placement;
const struct ttm_place *placement;
unsigned num_busy_placement;
const struct ttm_place *busy_placement;
};
/**
@@ -163,7 +173,6 @@ struct ttm_tt;
* @lru: List head for the lru list.
* @ddestroy: List head for the delayed destroy list.
* @swap: List head for swap LRU list.
* @sync_obj: Pointer to a synchronization object.
* @priv_flags: Flags describing buffer object internal state.
* @vma_node: Address space manager node.
* @offset: The current GPU offset, which can have different meanings
@@ -227,13 +236,9 @@ struct ttm_buffer_object {
struct list_head io_reserve_lru;
/**
* Members protected by struct buffer_object_device::fence_lock
* In addition, setting sync_obj to anything else
* than NULL requires bo::reserved to be held. This allows for
* checking NULL while reserved but not holding the mentioned lock.
* Members protected by a bo reservation.
*/
void *sync_obj;
unsigned long priv_flags;
struct drm_vma_offset_node vma_node;
@@ -455,6 +460,7 @@ size_t ttm_bo_dma_acc_size(struct ttm_bo_device *bdev,
* point to the shmem object backing a GEM object if TTM is used to back a
* GEM user interface.
* @acc_size: Accounted size for this object.
* @resv: Pointer to a reservation_object, or NULL to let ttm allocate one.
* @destroy: Destroy function. Use NULL for kfree().
*
* This function initializes a pre-allocated struct ttm_buffer_object.
@@ -482,6 +488,7 @@ extern int ttm_bo_init(struct ttm_bo_device *bdev,
struct file *persistent_swap_storage,
size_t acc_size,
struct sg_table *sg,
struct reservation_object *resv,
void (*destroy) (struct ttm_buffer_object *));
/**
@@ -518,20 +525,6 @@ extern int ttm_bo_create(struct ttm_bo_device *bdev,
struct file *persistent_swap_storage,
struct ttm_buffer_object **p_bo);
/**
* ttm_bo_check_placement
*
* @bo: the buffer object.
* @placement: placements
*
* Performs minimal validity checking on an intended change of
* placement flags.
* Returns
* -EINVAL: Intended change is invalid or not allowed.
*/
extern int ttm_bo_check_placement(struct ttm_buffer_object *bo,
struct ttm_placement *placement);
/**
* ttm_bo_init_mm
*

32
include/drm/ttm/ttm_bo_driver.h
View File

@@ -208,8 +208,7 @@ struct ttm_mem_type_manager_func {
*/
int (*get_node)(struct ttm_mem_type_manager *man,
struct ttm_buffer_object *bo,
struct ttm_placement *placement,
uint32_t flags,
const struct ttm_place *place,
struct ttm_mem_reg *mem);
/**
@@ -313,11 +312,6 @@ struct ttm_mem_type_manager {
* @move: Callback for a driver to hook in accelerated functions to
* move a buffer.
* If set to NULL, a potentially slow memcpy() move is used.
* @sync_obj_signaled: See ttm_fence_api.h
* @sync_obj_wait: See ttm_fence_api.h
* @sync_obj_flush: See ttm_fence_api.h
* @sync_obj_unref: See ttm_fence_api.h
* @sync_obj_ref: See ttm_fence_api.h
*/
struct ttm_bo_driver {
@@ -419,23 +413,6 @@ struct ttm_bo_driver {
int (*verify_access) (struct ttm_buffer_object *bo,
struct file *filp);
/**
* In case a driver writer dislikes the TTM fence objects,
* the driver writer can replace those with sync objects of
* his / her own. If it turns out that no driver writer is
* using these. I suggest we remove these hooks and plug in
* fences directly. The bo driver needs the following functionality:
* See the corresponding functions in the fence object API
* documentation.
*/
bool (*sync_obj_signaled) (void *sync_obj);
int (*sync_obj_wait) (void *sync_obj,
bool lazy, bool interruptible);
int (*sync_obj_flush) (void *sync_obj);
void (*sync_obj_unref) (void **sync_obj);
void *(*sync_obj_ref) (void *sync_obj);
/* hook to notify driver about a driver move so it
* can do tiling things */
void (*move_notify)(struct ttm_buffer_object *bo,
@@ -522,8 +499,6 @@ struct ttm_bo_global {
*
* @driver: Pointer to a struct ttm_bo_driver struct setup by the driver.
* @man: An array of mem_type_managers.
* @fence_lock: Protects the synchronizing members on *all* bos belonging
* to this device.
* @vma_manager: Address space manager
* lru_lock: Spinlock that protects the buffer+device lru lists and
* ddestroy lists.
@@ -543,7 +518,6 @@ struct ttm_bo_device {
struct ttm_bo_global *glob;
struct ttm_bo_driver *driver;
struct ttm_mem_type_manager man[TTM_NUM_MEM_TYPES];
spinlock_t fence_lock;
/*
* Protected by internal locks.
@@ -1026,7 +1000,7 @@ extern void ttm_bo_free_old_node(struct ttm_buffer_object *bo);
* ttm_bo_move_accel_cleanup.
*
* @bo: A pointer to a struct ttm_buffer_object.
* @sync_obj: A sync object that signals when moving is complete.
* @fence: A fence object that signals when moving is complete.
* @evict: This is an evict move. Don't return until the buffer is idle.
* @no_wait_gpu: Return immediately if the GPU is busy.
* @new_mem: struct ttm_mem_reg indicating where to move.
@@ -1040,7 +1014,7 @@ extern void ttm_bo_free_old_node(struct ttm_buffer_object *bo);
*/
extern int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
void *sync_obj,
struct fence *fence,
bool evict, bool no_wait_gpu,
struct ttm_mem_reg *new_mem);
/**

31
include/drm/ttm/ttm_execbuf_util.h
View File

@@ -39,19 +39,13 @@
*
* @head: list head for thread-private list.
* @bo: refcounted buffer object pointer.
* @reserved: Indicates whether @bo has been reserved for validation.
* @removed: Indicates whether @bo has been removed from lru lists.
* @put_count: Number of outstanding references on bo::list_kref.
* @old_sync_obj: Pointer to a sync object about to be unreferenced
* @shared: should the fence be added shared?
*/
struct ttm_validate_buffer {
struct list_head head;
struct ttm_buffer_object *bo;
bool reserved;
bool removed;
int put_count;
void *old_sync_obj;
bool shared;
};
/**
@@ -73,6 +67,8 @@ extern void ttm_eu_backoff_reservation(struct ww_acquire_ctx *ticket,
* @ticket: [out] ww_acquire_ctx filled in by call, or NULL if only
* non-blocking reserves should be tried.
* @list: thread private list of ttm_validate_buffer structs.
* @intr: should the wait be interruptible
* @dups: [out] optional list of duplicates.
*
* Tries to reserve bos pointed to by the list entries for validation.
* If the function returns 0, all buffers are marked as "unfenced",
@@ -84,9 +80,14 @@ extern void ttm_eu_backoff_reservation(struct ww_acquire_ctx *ticket,
* CPU write reservations to be cleared, and for other threads to
* unreserve their buffers.
*
* This function may return -ERESTART or -EAGAIN if the calling process
* receives a signal while waiting. In that case, no buffers on the list
* will be reserved upon return.
* If intr is set to true, this function may return -ERESTARTSYS if the
* calling process receives a signal while waiting. In that case, no
* buffers on the list will be reserved upon return.
*
* If dups is non NULL all buffers already reserved by the current thread
* (e.g. duplicates) are added to this list, otherwise -EALREADY is returned
* on the first already reserved buffer and all buffers from the list are
* unreserved again.
*
* Buffers reserved by this function should be unreserved by
* a call to either ttm_eu_backoff_reservation() or
@@ -95,14 +96,15 @@ extern void ttm_eu_backoff_reservation(struct ww_acquire_ctx *ticket,
*/
extern int ttm_eu_reserve_buffers(struct ww_acquire_ctx *ticket,
struct list_head *list);
struct list_head *list, bool intr,
struct list_head *dups);
/**
* function ttm_eu_fence_buffer_objects.
*
* @ticket: ww_acquire_ctx from reserve call
* @list: thread private list of ttm_validate_buffer structs.
* @sync_obj: The new sync object for the buffers.
* @fence: The new exclusive fence for the buffers.
*
* This function should be called when command submission is complete, and
* it will add a new sync object to bos pointed to by entries on @list.
@@ -111,6 +113,7 @@ extern int ttm_eu_reserve_buffers(struct ww_acquire_ctx *ticket,
*/
extern void ttm_eu_fence_buffer_objects(struct ww_acquire_ctx *ticket,
struct list_head *list, void *sync_obj);
struct list_head *list,
struct fence *fence);
#endif

15
include/dt-bindings/arm/ux500_pm_domains.h Normal file
View File

@@ -0,0 +1,15 @@
/*
* Copyright (C) 2014 Linaro Ltd.
*
* Author: Ulf Hansson <ulf.hansson@linaro.org>
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H
#define _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H
#define DOMAIN_VAPE 0
/* Number of PM domains. */
#define NR_DOMAINS (DOMAIN_VAPE + 1)
#endif

27
include/dt-bindings/clock/exynos3250.h
View File

@@ -255,4 +255,31 @@
*/
#define CLK_NR_CLKS 248
/*
* CMU DMC
*/
#define CLK_FOUT_BPLL 1
#define CLK_FOUT_EPLL 2
/* Muxes */
#define CLK_MOUT_MPLL_MIF 8
#define CLK_MOUT_BPLL 9
#define CLK_MOUT_DPHY 10
#define CLK_MOUT_DMC_BUS 11
#define CLK_MOUT_EPLL 12
/* Dividers */
#define CLK_DIV_DMC 16
#define CLK_DIV_DPHY 17
#define CLK_DIV_DMC_PRE 18
#define CLK_DIV_DMCP 19
#define CLK_DIV_DMCD 20
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
#define NR_CLKS_DMC 21
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */

12
include/dt-bindings/clock/exynos4.h
View File

@@ -115,11 +115,11 @@
#define CLK_SMMU_MFCR 275
#define CLK_G3D 276
#define CLK_G2D 277
#define CLK_ROTATOR 278 /* Exynos4210 only */
#define CLK_MDMA 279 /* Exynos4210 only */
#define CLK_SMMU_G2D 280 /* Exynos4210 only */
#define CLK_SMMU_ROTATOR 281 /* Exynos4210 only */
#define CLK_SMMU_MDMA 282 /* Exynos4210 only */
#define CLK_ROTATOR 278
#define CLK_MDMA 279
#define CLK_SMMU_G2D 280
#define CLK_SMMU_ROTATOR 281
#define CLK_SMMU_MDMA 282
#define CLK_FIMD0 283
#define CLK_MIE0 284
#define CLK_MDNIE0 285 /* Exynos4412 only */
@@ -234,6 +234,8 @@
#define CLK_MOUT_G3D1 393
#define CLK_MOUT_G3D 394
#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
#define CLK_MOUT_HDMI 396
#define CLK_MOUT_MIXER 397
/* gate clocks - ppmu */
#define CLK_PPMULEFT 400

360
include/dt-bindings/clock/exynos4415.h Normal file
View File

@@ -0,0 +1,360 @@
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Chanwoo Choi <cw00.choi@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants for Samsung Exynos4415 clock controllers.
*/
#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
/*
* Let each exported clock get a unique index, which is used on DT-enabled
* platforms to lookup the clock from a clock specifier. These indices are
* therefore considered an ABI and so must not be changed. This implies
* that new clocks should be added either in free spaces between clock groups
* or at the end.
*/
/*
* Main CMU
*/
#define CLK_OSCSEL 1
#define CLK_FIN_PLL 2
#define CLK_FOUT_APLL 3
#define CLK_FOUT_MPLL 4
#define CLK_FOUT_EPLL 5
#define CLK_FOUT_G3D_PLL 6
#define CLK_FOUT_ISP_PLL 7
#define CLK_FOUT_DISP_PLL 8
/* Muxes */
#define CLK_MOUT_MPLL_USER_L 16
#define CLK_MOUT_GDL 17
#define CLK_MOUT_MPLL_USER_R 18
#define CLK_MOUT_GDR 19
#define CLK_MOUT_EBI 20
#define CLK_MOUT_ACLK_200 21
#define CLK_MOUT_ACLK_160 22
#define CLK_MOUT_ACLK_100 23
#define CLK_MOUT_ACLK_266 24
#define CLK_MOUT_G3D_PLL 25
#define CLK_MOUT_EPLL 26
#define CLK_MOUT_EBI_1 27
#define CLK_MOUT_ISP_PLL 28
#define CLK_MOUT_DISP_PLL 29
#define CLK_MOUT_MPLL_USER_T 30
#define CLK_MOUT_ACLK_400_MCUISP 31
#define CLK_MOUT_G3D_PLLSRC 32
#define CLK_MOUT_CSIS1 33
#define CLK_MOUT_CSIS0 34
#define CLK_MOUT_CAM1 35
#define CLK_MOUT_FIMC3_LCLK 36
#define CLK_MOUT_FIMC2_LCLK 37
#define CLK_MOUT_FIMC1_LCLK 38
#define CLK_MOUT_FIMC0_LCLK 39
#define CLK_MOUT_MFC 40
#define CLK_MOUT_MFC_1 41
#define CLK_MOUT_MFC_0 42
#define CLK_MOUT_G3D 43
#define CLK_MOUT_G3D_1 44
#define CLK_MOUT_G3D_0 45
#define CLK_MOUT_MIPI0 46
#define CLK_MOUT_FIMD0 47
#define CLK_MOUT_TSADC_ISP 48
#define CLK_MOUT_UART_ISP 49
#define CLK_MOUT_SPI1_ISP 50
#define CLK_MOUT_SPI0_ISP 51
#define CLK_MOUT_PWM_ISP 52
#define CLK_MOUT_AUDIO0 53
#define CLK_MOUT_TSADC 54
#define CLK_MOUT_MMC2 55
#define CLK_MOUT_MMC1 56
#define CLK_MOUT_MMC0 57
#define CLK_MOUT_UART3 58
#define CLK_MOUT_UART2 59
#define CLK_MOUT_UART1 60
#define CLK_MOUT_UART0 61
#define CLK_MOUT_SPI2 62
#define CLK_MOUT_SPI1 63
#define CLK_MOUT_SPI0 64
#define CLK_MOUT_SPDIF 65
#define CLK_MOUT_AUDIO2 66
#define CLK_MOUT_AUDIO1 67
#define CLK_MOUT_MPLL_USER_C 68
#define CLK_MOUT_HPM 69
#define CLK_MOUT_CORE 70
#define CLK_MOUT_APLL 71
#define CLK_MOUT_PXLASYNC_CSIS1_FIMC 72
#define CLK_MOUT_PXLASYNC_CSIS0_FIMC 73
#define CLK_MOUT_JPEG 74
#define CLK_MOUT_JPEG1 75
#define CLK_MOUT_JPEG0 76
#define CLK_MOUT_ACLK_ISP0_300 77
#define CLK_MOUT_ACLK_ISP0_400 78
#define CLK_MOUT_ACLK_ISP0_300_USER 79
#define CLK_MOUT_ACLK_ISP1_300 80
#define CLK_MOUT_ACLK_ISP1_300_USER 81
#define CLK_MOUT_HDMI 82
/* Dividers */
#define CLK_DIV_GPL 90
#define CLK_DIV_GDL 91
#define CLK_DIV_GPR 92
#define CLK_DIV_GDR 93
#define CLK_DIV_ACLK_400_MCUISP 94
#define CLK_DIV_EBI 95
#define CLK_DIV_ACLK_200 96
#define CLK_DIV_ACLK_160 97
#define CLK_DIV_ACLK_100 98
#define CLK_DIV_ACLK_266 99
#define CLK_DIV_CSIS1 100
#define CLK_DIV_CSIS0 101
#define CLK_DIV_CAM1 102
#define CLK_DIV_FIMC3_LCLK 103
#define CLK_DIV_FIMC2_LCLK 104
#define CLK_DIV_FIMC1_LCLK 105
#define CLK_DIV_FIMC0_LCLK 106
#define CLK_DIV_TV_BLK 107
#define CLK_DIV_MFC 108
#define CLK_DIV_G3D 109
#define CLK_DIV_MIPI0_PRE 110
#define CLK_DIV_MIPI0 111
#define CLK_DIV_FIMD0 112
#define CLK_DIV_UART_ISP 113
#define CLK_DIV_SPI1_ISP_PRE 114
#define CLK_DIV_SPI1_ISP 115
#define CLK_DIV_SPI0_ISP_PRE 116
#define CLK_DIV_SPI0_ISP 117
#define CLK_DIV_PWM_ISP 118
#define CLK_DIV_PCM0 119
#define CLK_DIV_AUDIO0 120
#define CLK_DIV_TSADC_PRE 121
#define CLK_DIV_TSADC 122
#define CLK_DIV_MMC1_PRE 123
#define CLK_DIV_MMC1 124
#define CLK_DIV_MMC0_PRE 125
#define CLK_DIV_MMC0 126
#define CLK_DIV_MMC2_PRE 127
#define CLK_DIV_MMC2 128
#define CLK_DIV_UART3 129
#define CLK_DIV_UART2 130
#define CLK_DIV_UART1 131
#define CLK_DIV_UART0 132
#define CLK_DIV_SPI1_PRE 133
#define CLK_DIV_SPI1 134
#define CLK_DIV_SPI0_PRE 135
#define CLK_DIV_SPI0 136
#define CLK_DIV_SPI2_PRE 137
#define CLK_DIV_SPI2 138
#define CLK_DIV_PCM2 139
#define CLK_DIV_AUDIO2 140
#define CLK_DIV_PCM1 141
#define CLK_DIV_AUDIO1 142
#define CLK_DIV_I2S1 143
#define CLK_DIV_PXLASYNC_CSIS1_FIMC 144
#define CLK_DIV_PXLASYNC_CSIS0_FIMC 145
#define CLK_DIV_JPEG 146
#define CLK_DIV_CORE2 147
#define CLK_DIV_APLL 148
#define CLK_DIV_PCLK_DBG 149
#define CLK_DIV_ATB 150
#define CLK_DIV_PERIPH 151
#define CLK_DIV_COREM1 152
#define CLK_DIV_COREM0 153
#define CLK_DIV_CORE 154
#define CLK_DIV_HPM 155
#define CLK_DIV_COPY 156
/* Gates */
#define CLK_ASYNC_G3D 180
#define CLK_ASYNC_MFCL 181
#define CLK_ASYNC_TVX 182
#define CLK_PPMULEFT 183
#define CLK_GPIO_LEFT 184
#define CLK_PPMUIMAGE 185
#define CLK_QEMDMA2 186
#define CLK_QEROTATOR 187
#define CLK_SMMUMDMA2 188
#define CLK_SMMUROTATOR 189
#define CLK_MDMA2 190
#define CLK_ROTATOR 191
#define CLK_ASYNC_ISPMX 192
#define CLK_ASYNC_MAUDIOX 193
#define CLK_ASYNC_MFCR 194
#define CLK_ASYNC_FSYSD 195
#define CLK_ASYNC_LCD0X 196
#define CLK_ASYNC_CAMX 197
#define CLK_PPMURIGHT 198
#define CLK_GPIO_RIGHT 199
#define CLK_ANTIRBK_APBIF 200
#define CLK_EFUSE_WRITER_APBIF 201
#define CLK_MONOCNT 202
#define CLK_TZPC6 203
#define CLK_PROVISIONKEY1 204
#define CLK_PROVISIONKEY0 205
#define CLK_CMU_ISPPART 206
#define CLK_TMU_APBIF 207
#define CLK_KEYIF 208
#define CLK_RTC 209
#define CLK_WDT 210
#define CLK_MCT 211
#define CLK_SECKEY 212
#define CLK_HDMI_CEC 213
#define CLK_TZPC5 214
#define CLK_TZPC4 215
#define CLK_TZPC3 216
#define CLK_TZPC2 217
#define CLK_TZPC1 218
#define CLK_TZPC0 219
#define CLK_CMU_COREPART 220
#define CLK_CMU_TOPPART 221
#define CLK_PMU_APBIF 222
#define CLK_SYSREG 223
#define CLK_CHIP_ID 224
#define CLK_SMMUFIMC_LITE2 225
#define CLK_FIMC_LITE2 226
#define CLK_PIXELASYNCM1 227
#define CLK_PIXELASYNCM0 228
#define CLK_PPMUCAMIF 229
#define CLK_SMMUJPEG 230
#define CLK_SMMUFIMC3 231
#define CLK_SMMUFIMC2 232
#define CLK_SMMUFIMC1 233
#define CLK_SMMUFIMC0 234
#define CLK_JPEG 235
#define CLK_CSIS1 236
#define CLK_CSIS0 237
#define CLK_FIMC3 238
#define CLK_FIMC2 239
#define CLK_FIMC1 240
#define CLK_FIMC0 241
#define CLK_PPMUTV 242
#define CLK_SMMUTV 243
#define CLK_HDMI 244
#define CLK_MIXER 245
#define CLK_VP 246
#define CLK_PPMUMFC_R 247
#define CLK_PPMUMFC_L 248
#define CLK_SMMUMFC_R 249
#define CLK_SMMUMFC_L 250
#define CLK_MFC 251
#define CLK_PPMUG3D 252
#define CLK_G3D 253
#define CLK_PPMULCD0 254
#define CLK_SMMUFIMD0 255
#define CLK_DSIM0 256
#define CLK_SMIES 257
#define CLK_MIE0 258
#define CLK_FIMD0 259
#define CLK_TSADC 260
#define CLK_PPMUFILE 261
#define CLK_NFCON 262
#define CLK_USBDEVICE 263
#define CLK_USBHOST 264
#define CLK_SROMC 265
#define CLK_SDMMC2 266
#define CLK_SDMMC1 267
#define CLK_SDMMC0 268
#define CLK_PDMA1 269
#define CLK_PDMA0 270
#define CLK_SPDIF 271
#define CLK_PWM 272
#define CLK_PCM2 273
#define CLK_PCM1 274
#define CLK_I2S1 275
#define CLK_SPI2 276
#define CLK_SPI1 277
#define CLK_SPI0 278
#define CLK_I2CHDMI 279
#define CLK_I2C7 280
#define CLK_I2C6 281
#define CLK_I2C5 282
#define CLK_I2C4 283
#define CLK_I2C3 284
#define CLK_I2C2 285
#define CLK_I2C1 286
#define CLK_I2C0 287
#define CLK_UART3 288
#define CLK_UART2 289
#define CLK_UART1 290
#define CLK_UART0 291
/* Special clocks */
#define CLK_SCLK_PXLAYSNC_CSIS1_FIMC 330
#define CLK_SCLK_PXLAYSNC_CSIS0_FIMC 331
#define CLK_SCLK_JPEG 332
#define CLK_SCLK_CSIS1 333
#define CLK_SCLK_CSIS0 334
#define CLK_SCLK_CAM1 335
#define CLK_SCLK_FIMC3_LCLK 336
#define CLK_SCLK_FIMC2_LCLK 337
#define CLK_SCLK_FIMC1_LCLK 338
#define CLK_SCLK_FIMC0_LCLK 339
#define CLK_SCLK_PIXEL 340
#define CLK_SCLK_HDMI 341
#define CLK_SCLK_MIXER 342
#define CLK_SCLK_MFC 343
#define CLK_SCLK_G3D 344
#define CLK_SCLK_MIPIDPHY4L 345
#define CLK_SCLK_MIPI0 346
#define CLK_SCLK_MDNIE0 347
#define CLK_SCLK_FIMD0 348
#define CLK_SCLK_PCM0 349
#define CLK_SCLK_AUDIO0 350
#define CLK_SCLK_TSADC 351
#define CLK_SCLK_EBI 352
#define CLK_SCLK_MMC2 353
#define CLK_SCLK_MMC1 354
#define CLK_SCLK_MMC0 355
#define CLK_SCLK_I2S 356
#define CLK_SCLK_PCM2 357
#define CLK_SCLK_PCM1 358
#define CLK_SCLK_AUDIO2 359
#define CLK_SCLK_AUDIO1 360
#define CLK_SCLK_SPDIF 361
#define CLK_SCLK_SPI2 362
#define CLK_SCLK_SPI1 363
#define CLK_SCLK_SPI0 364
#define CLK_SCLK_UART3 365
#define CLK_SCLK_UART2 366
#define CLK_SCLK_UART1 367
#define CLK_SCLK_UART0 368
#define CLK_SCLK_HDMIPHY 369
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
#define CLK_NR_CLKS 370
/*
* CMU DMC
*/
#define CLK_DMC_FOUT_MPLL 1
#define CLK_DMC_FOUT_BPLL 2
#define CLK_DMC_MOUT_MPLL 3
#define CLK_DMC_MOUT_BPLL 4
#define CLK_DMC_MOUT_DPHY 5
#define CLK_DMC_MOUT_DMC_BUS 6
#define CLK_DMC_DIV_DMC 7
#define CLK_DMC_DIV_DPHY 8
#define CLK_DMC_DIV_DMC_PRE 9
#define CLK_DMC_DIV_DMCP 10
#define CLK_DMC_DIV_DMCD 11
#define CLK_DMC_DIV_MPLL_PRE 12
/*
* Total number of clocks of CMU_DMC.
* NOTE: Must be equal to highest clock ID increased by one.
*/
#define NR_CLKS_DMC 13
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H */

92
include/dt-bindings/clock/exynos7-clk.h Normal file
View File

@@ -0,0 +1,92 @@
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
#define _DT_BINDINGS_CLOCK_EXYNOS7_H
/* TOPC */
#define DOUT_ACLK_PERIS 1
#define DOUT_SCLK_BUS0_PLL 2
#define DOUT_SCLK_BUS1_PLL 3
#define DOUT_SCLK_CC_PLL 4
#define DOUT_SCLK_MFC_PLL 5
#define DOUT_ACLK_CCORE_133 6
#define TOPC_NR_CLK 7
/* TOP0 */
#define DOUT_ACLK_PERIC1 1
#define DOUT_ACLK_PERIC0 2
#define CLK_SCLK_UART0 3
#define CLK_SCLK_UART1 4
#define CLK_SCLK_UART2 5
#define CLK_SCLK_UART3 6
#define TOP0_NR_CLK 7
/* TOP1 */
#define DOUT_ACLK_FSYS1_200 1
#define DOUT_ACLK_FSYS0_200 2
#define DOUT_SCLK_MMC2 3
#define DOUT_SCLK_MMC1 4
#define DOUT_SCLK_MMC0 5
#define CLK_SCLK_MMC2 6
#define CLK_SCLK_MMC1 7
#define CLK_SCLK_MMC0 8
#define TOP1_NR_CLK 9
/* CCORE */
#define PCLK_RTC 1
#define CCORE_NR_CLK 2
/* PERIC0 */
#define PCLK_UART0 1
#define SCLK_UART0 2
#define PCLK_HSI2C0 3
#define PCLK_HSI2C1 4
#define PCLK_HSI2C4 5
#define PCLK_HSI2C5 6
#define PCLK_HSI2C9 7
#define PCLK_HSI2C10 8
#define PCLK_HSI2C11 9
#define PCLK_PWM 10
#define SCLK_PWM 11
#define PCLK_ADCIF 12
#define PERIC0_NR_CLK 13
/* PERIC1 */
#define PCLK_UART1 1
#define PCLK_UART2 2
#define PCLK_UART3 3
#define SCLK_UART1 4
#define SCLK_UART2 5
#define SCLK_UART3 6
#define PCLK_HSI2C2 7
#define PCLK_HSI2C3 8
#define PCLK_HSI2C6 9
#define PCLK_HSI2C7 10
#define PCLK_HSI2C8 11
#define PERIC1_NR_CLK 12
/* PERIS */
#define PCLK_CHIPID 1
#define SCLK_CHIPID 2
#define PCLK_WDT 3
#define PCLK_TMU 4
#define SCLK_TMU 5
#define PERIS_NR_CLK 6
/* FSYS0 */
#define ACLK_MMC2 1
#define FSYS0_NR_CLK 2
/* FSYS1 */
#define ACLK_MMC1 1
#define ACLK_MMC0 2
#define FSYS1_NR_CLK 3
#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */

27
include/dt-bindings/clock/hix5hd2-clock.h
View File

@@ -46,6 +46,7 @@
#define HIX5HD2_SFC_MUX 64
#define HIX5HD2_MMC_MUX 65
#define HIX5HD2_FEPHY_MUX 66
#define HIX5HD2_SD_MUX 67
/* gate clocks */
#define HIX5HD2_SFC_RST 128
@@ -53,6 +54,32 @@
#define HIX5HD2_MMC_CIU_CLK 130
#define HIX5HD2_MMC_BIU_CLK 131
#define HIX5HD2_MMC_CIU_RST 132
#define HIX5HD2_FWD_BUS_CLK 133
#define HIX5HD2_FWD_SYS_CLK 134
#define HIX5HD2_MAC0_PHY_CLK 135
#define HIX5HD2_SD_CIU_CLK 136
#define HIX5HD2_SD_BIU_CLK 137
#define HIX5HD2_SD_CIU_RST 138
#define HIX5HD2_WDG0_CLK 139
#define HIX5HD2_WDG0_RST 140
#define HIX5HD2_I2C0_CLK 141
#define HIX5HD2_I2C0_RST 142
#define HIX5HD2_I2C1_CLK 143
#define HIX5HD2_I2C1_RST 144
#define HIX5HD2_I2C2_CLK 145
#define HIX5HD2_I2C2_RST 146
#define HIX5HD2_I2C3_CLK 147
#define HIX5HD2_I2C3_RST 148
#define HIX5HD2_I2C4_CLK 149
#define HIX5HD2_I2C4_RST 150
#define HIX5HD2_I2C5_CLK 151
#define HIX5HD2_I2C5_RST 152
/* complex */
#define HIX5HD2_MAC0_CLK 192
#define HIX5HD2_MAC1_CLK 193
#define HIX5HD2_SATA_CLK 194
#define HIX5HD2_USB_CLK 195
#define HIX5HD2_NR_CLKS 256
#endif /* __DTS_HIX5HD2_CLOCK_H */

5
include/dt-bindings/clock/imx5-clock.h
View File

@@ -198,6 +198,9 @@
#define IMX5_CLK_OCRAM 186
#define IMX5_CLK_SAHARA_IPG_GATE 187
#define IMX5_CLK_SATA_REF 188
#define IMX5_CLK_END 189
#define IMX5_CLK_STEP_SEL 189
#define IMX5_CLK_CPU_PODF_SEL 190
#define IMX5_CLK_ARM 191
#define IMX5_CLK_END 192
#endif /* __DT_BINDINGS_CLOCK_IMX5_H */

43
include/dt-bindings/clock/imx6qdl-clock.h
View File

@@ -62,8 +62,8 @@
#define IMX6QDL_CLK_USDHC3_SEL 50
#define IMX6QDL_CLK_USDHC4_SEL 51
#define IMX6QDL_CLK_ENFC_SEL 52
#define IMX6QDL_CLK_EMI_SEL 53
#define IMX6QDL_CLK_EMI_SLOW_SEL 54
#define IMX6QDL_CLK_EIM_SEL 53
#define IMX6QDL_CLK_EIM_SLOW_SEL 54
#define IMX6QDL_CLK_VDO_AXI_SEL 55
#define IMX6QDL_CLK_VPU_AXI_SEL 56
#define IMX6QDL_CLK_CKO1_SEL 57
@@ -106,8 +106,8 @@
#define IMX6QDL_CLK_USDHC4_PODF 94
#define IMX6QDL_CLK_ENFC_PRED 95
#define IMX6QDL_CLK_ENFC_PODF 96
#define IMX6QDL_CLK_EMI_PODF 97
#define IMX6QDL_CLK_EMI_SLOW_PODF 98
#define IMX6QDL_CLK_EIM_PODF 97
#define IMX6QDL_CLK_EIM_SLOW_PODF 98
#define IMX6QDL_CLK_VPU_AXI_PODF 99
#define IMX6QDL_CLK_CKO1_PODF 100
#define IMX6QDL_CLK_AXI 101
@@ -128,7 +128,7 @@
#define IMX6Q_CLK_ECSPI5 116
#define IMX6DL_CLK_I2C4 116
#define IMX6QDL_CLK_ENET 117
#define IMX6QDL_CLK_ESAI 118
#define IMX6QDL_CLK_ESAI_EXTAL 118
#define IMX6QDL_CLK_GPT_IPG 119
#define IMX6QDL_CLK_GPT_IPG_PER 120
#define IMX6QDL_CLK_GPU2D_CORE 121
@@ -218,7 +218,36 @@
#define IMX6QDL_CLK_LVDS2_SEL 205
#define IMX6QDL_CLK_LVDS1_GATE 206
#define IMX6QDL_CLK_LVDS2_GATE 207
#define IMX6QDL_CLK_ESAI_AHB 208
#define IMX6QDL_CLK_END 209
#define IMX6QDL_CLK_ESAI_IPG 208
#define IMX6QDL_CLK_ESAI_MEM 209
#define IMX6QDL_CLK_ASRC_IPG 210
#define IMX6QDL_CLK_ASRC_MEM 211
#define IMX6QDL_CLK_LVDS1_IN 212
#define IMX6QDL_CLK_LVDS2_IN 213
#define IMX6QDL_CLK_ANACLK1 214
#define IMX6QDL_CLK_ANACLK2 215
#define IMX6QDL_PLL1_BYPASS_SRC 216
#define IMX6QDL_PLL2_BYPASS_SRC 217
#define IMX6QDL_PLL3_BYPASS_SRC 218
#define IMX6QDL_PLL4_BYPASS_SRC 219
#define IMX6QDL_PLL5_BYPASS_SRC 220
#define IMX6QDL_PLL6_BYPASS_SRC 221
#define IMX6QDL_PLL7_BYPASS_SRC 222
#define IMX6QDL_CLK_PLL1 223
#define IMX6QDL_CLK_PLL2 224
#define IMX6QDL_CLK_PLL3 225
#define IMX6QDL_CLK_PLL4 226
#define IMX6QDL_CLK_PLL5 227
#define IMX6QDL_CLK_PLL6 228
#define IMX6QDL_CLK_PLL7 229
#define IMX6QDL_PLL1_BYPASS 230
#define IMX6QDL_PLL2_BYPASS 231
#define IMX6QDL_PLL3_BYPASS 232
#define IMX6QDL_PLL4_BYPASS 233
#define IMX6QDL_PLL5_BYPASS 234
#define IMX6QDL_PLL6_BYPASS 235
#define IMX6QDL_PLL7_BYPASS 236
#define IMX6QDL_CLK_GPT_3M 237
#define IMX6QDL_CLK_END 238
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */

30
include/dt-bindings/clock/imx6sl-clock.h
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@@ -146,6 +146,34 @@
#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
#define IMX6SL_CLK_SPBA 134
#define IMX6SL_CLK_ENET 135
#define IMX6SL_CLK_END 136
#define IMX6SL_CLK_LVDS1_SEL 136
#define IMX6SL_CLK_LVDS1_OUT 137
#define IMX6SL_CLK_LVDS1_IN 138
#define IMX6SL_CLK_ANACLK1 139
#define IMX6SL_PLL1_BYPASS_SRC 140
#define IMX6SL_PLL2_BYPASS_SRC 141
#define IMX6SL_PLL3_BYPASS_SRC 142
#define IMX6SL_PLL4_BYPASS_SRC 143
#define IMX6SL_PLL5_BYPASS_SRC 144
#define IMX6SL_PLL6_BYPASS_SRC 145
#define IMX6SL_PLL7_BYPASS_SRC 146
#define IMX6SL_CLK_PLL1 147
#define IMX6SL_CLK_PLL2 148
#define IMX6SL_CLK_PLL3 149
#define IMX6SL_CLK_PLL4 150
#define IMX6SL_CLK_PLL5 151
#define IMX6SL_CLK_PLL6 152
#define IMX6SL_CLK_PLL7 153
#define IMX6SL_PLL1_BYPASS 154
#define IMX6SL_PLL2_BYPASS 155
#define IMX6SL_PLL3_BYPASS 156
#define IMX6SL_PLL4_BYPASS 157
#define IMX6SL_PLL5_BYPASS 158
#define IMX6SL_PLL6_BYPASS 159
#define IMX6SL_PLL7_BYPASS 160
#define IMX6SL_CLK_SSI1_IPG 161
#define IMX6SL_CLK_SSI2_IPG 162
#define IMX6SL_CLK_SSI3_IPG 163
#define IMX6SL_CLK_END 164
#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */

25
include/dt-bindings/clock/imx6sx-clock.h
View File

@@ -251,6 +251,29 @@
#define IMX6SX_CLK_SAI2_IPG 238
#define IMX6SX_CLK_ESAI_IPG 239
#define IMX6SX_CLK_ESAI_MEM 240
#define IMX6SX_CLK_CLK_END 241
#define IMX6SX_CLK_LVDS1_IN 241
#define IMX6SX_CLK_ANACLK1 242
#define IMX6SX_PLL1_BYPASS_SRC 243
#define IMX6SX_PLL2_BYPASS_SRC 244
#define IMX6SX_PLL3_BYPASS_SRC 245
#define IMX6SX_PLL4_BYPASS_SRC 246
#define IMX6SX_PLL5_BYPASS_SRC 247
#define IMX6SX_PLL6_BYPASS_SRC 248
#define IMX6SX_PLL7_BYPASS_SRC 249
#define IMX6SX_CLK_PLL1 250
#define IMX6SX_CLK_PLL2 251
#define IMX6SX_CLK_PLL3 252
#define IMX6SX_CLK_PLL4 253
#define IMX6SX_CLK_PLL5 254
#define IMX6SX_CLK_PLL6 255
#define IMX6SX_CLK_PLL7 256
#define IMX6SX_PLL1_BYPASS 257
#define IMX6SX_PLL2_BYPASS 258
#define IMX6SX_PLL3_BYPASS 259
#define IMX6SX_PLL4_BYPASS 260
#define IMX6SX_PLL5_BYPASS 261
#define IMX6SX_PLL6_BYPASS 262
#define IMX6SX_PLL7_BYPASS 263
#define IMX6SX_CLK_CLK_END 264
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */

74
include/dt-bindings/clock/marvell,mmp2.h Normal file
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@@ -0,0 +1,74 @@
#ifndef __DTS_MARVELL_MMP2_CLOCK_H
#define __DTS_MARVELL_MMP2_CLOCK_H
/* fixed clocks and plls */
#define MMP2_CLK_CLK32 1
#define MMP2_CLK_VCTCXO 2
#define MMP2_CLK_PLL1 3
#define MMP2_CLK_PLL1_2 8
#define MMP2_CLK_PLL1_4 9
#define MMP2_CLK_PLL1_8 10
#define MMP2_CLK_PLL1_16 11
#define MMP2_CLK_PLL1_3 12
#define MMP2_CLK_PLL1_6 13
#define MMP2_CLK_PLL1_12 14
#define MMP2_CLK_PLL1_20 15
#define MMP2_CLK_PLL2 16
#define MMP2_CLK_PLL2_2 17
#define MMP2_CLK_PLL2_4 18
#define MMP2_CLK_PLL2_8 19
#define MMP2_CLK_PLL2_16 20
#define MMP2_CLK_PLL2_3 21
#define MMP2_CLK_PLL2_6 22
#define MMP2_CLK_PLL2_12 23
#define MMP2_CLK_VCTCXO_2 24
#define MMP2_CLK_VCTCXO_4 25
#define MMP2_CLK_UART_PLL 26
#define MMP2_CLK_USB_PLL 27
/* apb periphrals */
#define MMP2_CLK_TWSI0 60
#define MMP2_CLK_TWSI1 61
#define MMP2_CLK_TWSI2 62
#define MMP2_CLK_TWSI3 63
#define MMP2_CLK_TWSI4 64
#define MMP2_CLK_TWSI5 65
#define MMP2_CLK_GPIO 66
#define MMP2_CLK_KPC 67
#define MMP2_CLK_RTC 68
#define MMP2_CLK_PWM0 69
#define MMP2_CLK_PWM1 70
#define MMP2_CLK_PWM2 71
#define MMP2_CLK_PWM3 72
#define MMP2_CLK_UART0 73
#define MMP2_CLK_UART1 74
#define MMP2_CLK_UART2 75
#define MMP2_CLK_UART3 76
#define MMP2_CLK_SSP0 77
#define MMP2_CLK_SSP1 78
#define MMP2_CLK_SSP2 79
#define MMP2_CLK_SSP3 80
/* axi periphrals */
#define MMP2_CLK_SDH0 101
#define MMP2_CLK_SDH1 102
#define MMP2_CLK_SDH2 103
#define MMP2_CLK_SDH3 104
#define MMP2_CLK_USB 105
#define MMP2_CLK_DISP0 106
#define MMP2_CLK_DISP0_MUX 107
#define MMP2_CLK_DISP0_SPHY 108
#define MMP2_CLK_DISP1 109
#define MMP2_CLK_DISP1_MUX 110
#define MMP2_CLK_CCIC_ARBITER 111
#define MMP2_CLK_CCIC0 112
#define MMP2_CLK_CCIC0_MIX 113
#define MMP2_CLK_CCIC0_PHY 114
#define MMP2_CLK_CCIC0_SPHY 115
#define MMP2_CLK_CCIC1 116
#define MMP2_CLK_CCIC1_MIX 117
#define MMP2_CLK_CCIC1_PHY 118
#define MMP2_CLK_CCIC1_SPHY 119
#define MMP2_NR_CLKS 200
#endif

57
include/dt-bindings/clock/marvell,pxa168.h Normal file
View File

@@ -0,0 +1,57 @@
#ifndef __DTS_MARVELL_PXA168_CLOCK_H
#define __DTS_MARVELL_PXA168_CLOCK_H
/* fixed clocks and plls */
#define PXA168_CLK_CLK32 1
#define PXA168_CLK_VCTCXO 2
#define PXA168_CLK_PLL1 3
#define PXA168_CLK_PLL1_2 8
#define PXA168_CLK_PLL1_4 9
#define PXA168_CLK_PLL1_8 10
#define PXA168_CLK_PLL1_16 11
#define PXA168_CLK_PLL1_6 12
#define PXA168_CLK_PLL1_12 13
#define PXA168_CLK_PLL1_24 14
#define PXA168_CLK_PLL1_48 15
#define PXA168_CLK_PLL1_96 16
#define PXA168_CLK_PLL1_13 17
#define PXA168_CLK_PLL1_13_1_5 18
#define PXA168_CLK_PLL1_2_1_5 19
#define PXA168_CLK_PLL1_3_16 20
#define PXA168_CLK_UART_PLL 27
/* apb periphrals */
#define PXA168_CLK_TWSI0 60
#define PXA168_CLK_TWSI1 61
#define PXA168_CLK_TWSI2 62
#define PXA168_CLK_TWSI3 63
#define PXA168_CLK_GPIO 64
#define PXA168_CLK_KPC 65
#define PXA168_CLK_RTC 66
#define PXA168_CLK_PWM0 67
#define PXA168_CLK_PWM1 68
#define PXA168_CLK_PWM2 69
#define PXA168_CLK_PWM3 70
#define PXA168_CLK_UART0 71
#define PXA168_CLK_UART1 72
#define PXA168_CLK_UART2 73
#define PXA168_CLK_SSP0 74
#define PXA168_CLK_SSP1 75
#define PXA168_CLK_SSP2 76
#define PXA168_CLK_SSP3 77
#define PXA168_CLK_SSP4 78
/* axi periphrals */
#define PXA168_CLK_DFC 100
#define PXA168_CLK_SDH0 101
#define PXA168_CLK_SDH1 102
#define PXA168_CLK_SDH2 103
#define PXA168_CLK_USB 104
#define PXA168_CLK_SPH 105
#define PXA168_CLK_DISP0 106
#define PXA168_CLK_CCIC0 107
#define PXA168_CLK_CCIC0_PHY 108
#define PXA168_CLK_CCIC0_SPHY 109
#define PXA168_NR_CLKS 200
#endif

54
include/dt-bindings/clock/marvell,pxa910.h Normal file
View File

@@ -0,0 +1,54 @@
#ifndef __DTS_MARVELL_PXA910_CLOCK_H
#define __DTS_MARVELL_PXA910_CLOCK_H
/* fixed clocks and plls */
#define PXA910_CLK_CLK32 1
#define PXA910_CLK_VCTCXO 2
#define PXA910_CLK_PLL1 3
#define PXA910_CLK_PLL1_2 8
#define PXA910_CLK_PLL1_4 9
#define PXA910_CLK_PLL1_8 10
#define PXA910_CLK_PLL1_16 11
#define PXA910_CLK_PLL1_6 12
#define PXA910_CLK_PLL1_12 13
#define PXA910_CLK_PLL1_24 14
#define PXA910_CLK_PLL1_48 15
#define PXA910_CLK_PLL1_96 16
#define PXA910_CLK_PLL1_13 17
#define PXA910_CLK_PLL1_13_1_5 18
#define PXA910_CLK_PLL1_2_1_5 19
#define PXA910_CLK_PLL1_3_16 20
#define PXA910_CLK_UART_PLL 27
/* apb periphrals */
#define PXA910_CLK_TWSI0 60
#define PXA910_CLK_TWSI1 61
#define PXA910_CLK_TWSI2 62
#define PXA910_CLK_TWSI3 63
#define PXA910_CLK_GPIO 64
#define PXA910_CLK_KPC 65
#define PXA910_CLK_RTC 66
#define PXA910_CLK_PWM0 67
#define PXA910_CLK_PWM1 68
#define PXA910_CLK_PWM2 69
#define PXA910_CLK_PWM3 70
#define PXA910_CLK_UART0 71
#define PXA910_CLK_UART1 72
#define PXA910_CLK_UART2 73
#define PXA910_CLK_SSP0 74
#define PXA910_CLK_SSP1 75
/* axi periphrals */
#define PXA910_CLK_DFC 100
#define PXA910_CLK_SDH0 101
#define PXA910_CLK_SDH1 102
#define PXA910_CLK_SDH2 103
#define PXA910_CLK_USB 104
#define PXA910_CLK_SPH 105
#define PXA910_CLK_DISP0 106
#define PXA910_CLK_CCIC0 107
#define PXA910_CLK_CCIC0_PHY 108
#define PXA910_CLK_CCIC0_SPHY 109
#define PXA910_NR_CLKS 200
#endif

23
include/dt-bindings/clock/maxim,max77686.h Normal file
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@@ -0,0 +1,23 @@
/*
* Copyright (C) 2014 Google, Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants clocks for the Maxim 77686 PMIC.
*/
#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
#define _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H
/* Fixed rate clocks. */
#define MAX77686_CLK_AP 0
#define MAX77686_CLK_CP 1
#define MAX77686_CLK_PMIC 2
/* Total number of clocks. */
#define MAX77686_CLKS_NUM (MAX77686_CLK_PMIC + 1)
#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77686_CLOCK_H */

22
include/dt-bindings/clock/maxim,max77802.h Normal file
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@@ -0,0 +1,22 @@
/*
* Copyright (C) 2014 Google, Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants clocks for the Maxim 77802 PMIC.
*/
#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
/* Fixed rate clocks. */
#define MAX77802_CLK_32K_AP 0
#define MAX77802_CLK_32K_CP 1
/* Total number of clocks. */
#define MAX77802_CLKS_NUM (MAX77802_CLK_32K_CP + 1)
#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */

77
include/dt-bindings/clock/pxa-clock.h Normal file
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@@ -0,0 +1,77 @@
/*
* Inspired by original work from pxa2xx-regs.h by Nicolas Pitre
* Copyright (C) 2014 Robert Jarzmik
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__
#define __DT_BINDINGS_CLOCK_PXA2XX_H__
#define CLK_NONE 0
#define CLK_1WIRE 1
#define CLK_AC97 2
#define CLK_AC97CONF 3
#define CLK_ASSP 4
#define CLK_BOOT 5
#define CLK_BTUART 6
#define CLK_CAMERA 7
#define CLK_CIR 8
#define CLK_CORE 9
#define CLK_DMC 10
#define CLK_FFUART 11
#define CLK_FICP 12
#define CLK_GPIO 13
#define CLK_HSIO2 14
#define CLK_HWUART 15
#define CLK_I2C 16
#define CLK_I2S 17
#define CLK_IM 18
#define CLK_INC 19
#define CLK_ISC 20
#define CLK_KEYPAD 21
#define CLK_LCD 22
#define CLK_MEMC 23
#define CLK_MEMSTK 24
#define CLK_MINI_IM 25
#define CLK_MINI_LCD 26
#define CLK_MMC 27
#define CLK_MMC1 28
#define CLK_MMC2 29
#define CLK_MMC3 30
#define CLK_MSL 31
#define CLK_MSL0 32
#define CLK_MVED 33
#define CLK_NAND 34
#define CLK_NSSP 35
#define CLK_OSTIMER 36
#define CLK_PWM0 37
#define CLK_PWM1 38
#define CLK_PWM2 39
#define CLK_PWM3 40
#define CLK_PWRI2C 41
#define CLK_PXA300_GCU 42
#define CLK_PXA320_GCU 43
#define CLK_SMC 44
#define CLK_SSP 45
#define CLK_SSP1 46
#define CLK_SSP2 47
#define CLK_SSP3 48
#define CLK_SSP4 49
#define CLK_STUART 50
#define CLK_TOUCH 51
#define CLK_TPM 52
#define CLK_UDC 53
#define CLK_USB 54
#define CLK_USB2 55
#define CLK_USBH 56
#define CLK_USBHOST 57
#define CLK_USIM 58
#define CLK_USIM1 59
#define CLK_USMI0 60
#define CLK_MAX 61
#endif

2
include/dt-bindings/clock/qcom,mmcc-apq8084.h
View File

@@ -60,7 +60,7 @@
#define ESC1_CLK_SRC 43
#define HDMI_CLK_SRC 44
#define VSYNC_CLK_SRC 45
#define RBCPR_CLK_SRC 46
#define MMSS_RBCPR_CLK_SRC 46
#define RBBMTIMER_CLK_SRC 47
#define MAPLE_CLK_SRC 48
#define VDP_CLK_SRC 49

78
include/dt-bindings/clock/r8a7740-clock.h Normal file
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@@ -0,0 +1,78 @@
/*
* Copyright 2014 Ulrich Hecht
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7740_H__
#define __DT_BINDINGS_CLOCK_R8A7740_H__
/* CPG */
#define R8A7740_CLK_SYSTEM 0
#define R8A7740_CLK_PLLC0 1
#define R8A7740_CLK_PLLC1 2
#define R8A7740_CLK_PLLC2 3
#define R8A7740_CLK_R 4
#define R8A7740_CLK_USB24S 5
#define R8A7740_CLK_I 6
#define R8A7740_CLK_ZG 7
#define R8A7740_CLK_B 8
#define R8A7740_CLK_M1 9
#define R8A7740_CLK_HP 10
#define R8A7740_CLK_HPP 11
#define R8A7740_CLK_USBP 12
#define R8A7740_CLK_S 13
#define R8A7740_CLK_ZB 14
#define R8A7740_CLK_M3 15
#define R8A7740_CLK_CP 16
/* MSTP1 */
#define R8A7740_CLK_CEU21 28
#define R8A7740_CLK_CEU20 27
#define R8A7740_CLK_TMU0 25
#define R8A7740_CLK_LCDC1 17
#define R8A7740_CLK_IIC0 16
#define R8A7740_CLK_TMU1 11
#define R8A7740_CLK_LCDC0 0
/* MSTP2 */
#define R8A7740_CLK_SCIFA6 30
#define R8A7740_CLK_INTCA 29
#define R8A7740_CLK_SCIFA7 22
#define R8A7740_CLK_DMAC1 18
#define R8A7740_CLK_DMAC2 17
#define R8A7740_CLK_DMAC3 16
#define R8A7740_CLK_USBDMAC 14
#define R8A7740_CLK_SCIFA5 7
#define R8A7740_CLK_SCIFB 6
#define R8A7740_CLK_SCIFA0 4
#define R8A7740_CLK_SCIFA1 3
#define R8A7740_CLK_SCIFA2 2
#define R8A7740_CLK_SCIFA3 1
#define R8A7740_CLK_SCIFA4 0
/* MSTP3 */
#define R8A7740_CLK_CMT1 29
#define R8A7740_CLK_FSI 28
#define R8A7740_CLK_IIC1 23
#define R8A7740_CLK_USBF 20
#define R8A7740_CLK_SDHI0 14
#define R8A7740_CLK_SDHI1 13
#define R8A7740_CLK_MMC 12
#define R8A7740_CLK_GETHER 9
#define R8A7740_CLK_TPU0 4
/* MSTP4 */
#define R8A7740_CLK_USBH 16
#define R8A7740_CLK_SDHI2 15
#define R8A7740_CLK_USBFUNC 7
#define R8A7740_CLK_USBPHY 6
/* SUBCK* */
#define R8A7740_CLK_SUBCK 9
#define R8A7740_CLK_SUBCK2 10
#endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */

13
include/dt-bindings/clock/r8a7790-clock.h
View File

@@ -26,7 +26,18 @@
#define R8A7790_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7790_CLK_VCP1 0
#define R8A7790_CLK_VCP0 1
#define R8A7790_CLK_VPC1 2
#define R8A7790_CLK_VPC0 3
#define R8A7790_CLK_JPU 6
#define R8A7790_CLK_SSP1 9
#define R8A7790_CLK_TMU1 11
#define R8A7790_CLK_3DG 12
#define R8A7790_CLK_2DDMAC 15
#define R8A7790_CLK_FDP1_2 17
#define R8A7790_CLK_FDP1_1 18
#define R8A7790_CLK_FDP1_0 19
#define R8A7790_CLK_TMU3 21
#define R8A7790_CLK_TMU2 22
#define R8A7790_CLK_CMT0 24
@@ -67,6 +78,8 @@
#define R8A7790_CLK_USBDMAC1 31
/* MSTP5 */
#define R8A7790_CLK_AUDIO_DMAC1 1
#define R8A7790_CLK_AUDIO_DMAC0 2
#define R8A7790_CLK_THERMAL 22
#define R8A7790_CLK_PWM 23

10
include/dt-bindings/clock/r8a7791-clock.h
View File

@@ -25,7 +25,15 @@
#define R8A7791_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7791_CLK_VCP0 1
#define R8A7791_CLK_VPC0 3
#define R8A7791_CLK_JPU 6
#define R8A7791_CLK_SSP1 9
#define R8A7791_CLK_TMU1 11
#define R8A7791_CLK_3DG 12
#define R8A7791_CLK_2DDMAC 15
#define R8A7791_CLK_FDP1_1 18
#define R8A7791_CLK_FDP1_0 19
#define R8A7791_CLK_TMU3 21
#define R8A7791_CLK_TMU2 22
#define R8A7791_CLK_CMT0 24
@@ -61,6 +69,8 @@
#define R8A7791_CLK_USBDMAC1 31
/* MSTP5 */
#define R8A7791_CLK_AUDIO_DMAC1 1
#define R8A7791_CLK_AUDIO_DMAC0 2
#define R8A7791_CLK_THERMAL 22
#define R8A7791_CLK_PWM 23

89
include/dt-bindings/clock/r8a7794-clock.h Normal file
View File

@@ -0,0 +1,89 @@
/*
* Copyright (C) 2014 Renesas Electronics Corporation
* Copyright 2013 Ideas On Board SPRL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
#define __DT_BINDINGS_CLOCK_R8A7794_H__
/* CPG */
#define R8A7794_CLK_MAIN 0
#define R8A7794_CLK_PLL0 1
#define R8A7794_CLK_PLL1 2
#define R8A7794_CLK_PLL3 3
#define R8A7794_CLK_LB 4
#define R8A7794_CLK_QSPI 5
#define R8A7794_CLK_SDH 6
#define R8A7794_CLK_SD0 7
#define R8A7794_CLK_Z 8
/* MSTP0 */
#define R8A7794_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7794_CLK_VCP0 1
#define R8A7794_CLK_VPC0 3
#define R8A7794_CLK_TMU1 11
#define R8A7794_CLK_3DG 12
#define R8A7794_CLK_2DDMAC 15
#define R8A7794_CLK_FDP1_0 19
#define R8A7794_CLK_TMU3 21
#define R8A7794_CLK_TMU2 22
#define R8A7794_CLK_CMT0 24
#define R8A7794_CLK_TMU0 25
#define R8A7794_CLK_VSP1_DU0 28
#define R8A7794_CLK_VSP1_S 31
/* MSTP2 */
#define R8A7794_CLK_SCIFA2 2
#define R8A7794_CLK_SCIFA1 3
#define R8A7794_CLK_SCIFA0 4
#define R8A7794_CLK_MSIOF2 5
#define R8A7794_CLK_SCIFB0 6
#define R8A7794_CLK_SCIFB1 7
#define R8A7794_CLK_MSIOF1 8
#define R8A7794_CLK_SCIFB2 16
/* MSTP3 */
#define R8A7794_CLK_CMT1 29
/* MSTP5 */
#define R8A7794_CLK_THERMAL 22
#define R8A7794_CLK_PWM 23
/* MSTP7 */
#define R8A7794_CLK_HSCIF2 13
#define R8A7794_CLK_SCIF5 14
#define R8A7794_CLK_SCIF4 15
#define R8A7794_CLK_HSCIF1 16
#define R8A7794_CLK_HSCIF0 17
#define R8A7794_CLK_SCIF3 18
#define R8A7794_CLK_SCIF2 19
#define R8A7794_CLK_SCIF1 20
#define R8A7794_CLK_SCIF0 21
/* MSTP8 */
#define R8A7794_CLK_VIN1 10
#define R8A7794_CLK_VIN0 11
#define R8A7794_CLK_ETHER 13
/* MSTP9 */
#define R8A7794_CLK_GPIO6 5
#define R8A7794_CLK_GPIO5 7
#define R8A7794_CLK_GPIO4 8
#define R8A7794_CLK_GPIO3 9
#define R8A7794_CLK_GPIO2 10
#define R8A7794_CLK_GPIO1 11
#define R8A7794_CLK_GPIO0 12
/* MSTP11 */
#define R8A7794_CLK_SCIFA3 6
#define R8A7794_CLK_SCIFA4 7
#define R8A7794_CLK_SCIFA5 8
#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */

1
include/dt-bindings/clock/rk3188-cru-common.h
View File

@@ -20,6 +20,7 @@
#define PLL_GPLL 4
#define CORE_PERI 5
#define CORE_L2C 6
#define ARMCLK 7
/* sclk gates (special clocks) */
#define SCLK_UART0 64

95
include/dt-bindings/clock/rk3288-cru.h
View File

@@ -19,6 +19,7 @@
#define PLL_CPLL 3
#define PLL_GPLL 4
#define PLL_NPLL 5
#define ARMCLK 6
/* sclk gates (special clocks) */
#define SCLK_GPU 64
@@ -61,6 +62,24 @@
#define SCLK_LCDC_PWM1 101
#define SCLK_MAC_RX 102
#define SCLK_MAC_TX 103
#define SCLK_EDP_24M 104
#define SCLK_EDP 105
#define SCLK_RGA 106
#define SCLK_ISP 107
#define SCLK_ISP_JPE 108
#define SCLK_HDMI_HDCP 109
#define SCLK_HDMI_CEC 110
#define SCLK_HEVC_CABAC 111
#define SCLK_HEVC_CORE 112
#define SCLK_I2S0_OUT 113
#define SCLK_SDMMC_DRV 114
#define SCLK_SDIO0_DRV 115
#define SCLK_SDIO1_DRV 116
#define SCLK_EMMC_DRV 117
#define SCLK_SDMMC_SAMPLE 118
#define SCLK_SDIO0_SAMPLE 119
#define SCLK_SDIO1_SAMPLE 120
#define SCLK_EMMC_SAMPLE 121
#define DCLK_VOP0 190
#define DCLK_VOP1 191
@@ -75,6 +94,16 @@
#define ACLK_VOP1 198
#define ACLK_CRYPTO 199
#define ACLK_RGA 200
#define ACLK_RGA_NIU 201
#define ACLK_IEP 202
#define ACLK_VIO0_NIU 203
#define ACLK_VIP 204
#define ACLK_ISP 205
#define ACLK_VIO1_NIU 206
#define ACLK_HEVC 207
#define ACLK_VCODEC 208
#define ACLK_CPU 209
#define ACLK_PERI 210
/* pclk gates */
#define PCLK_GPIO0 320
@@ -112,6 +141,19 @@
#define PCLK_PS2C 352
#define PCLK_TIMER 353
#define PCLK_TZPC 354
#define PCLK_EDP_CTRL 355
#define PCLK_MIPI_DSI0 356
#define PCLK_MIPI_DSI1 357
#define PCLK_MIPI_CSI 358
#define PCLK_LVDS_PHY 359
#define PCLK_HDMI_CTRL 360
#define PCLK_VIO2_H2P 361
#define PCLK_CPU 362
#define PCLK_PERI 363
#define PCLK_DDRUPCTL0 364
#define PCLK_PUBL0 365
#define PCLK_DDRUPCTL1 366
#define PCLK_PUBL1 367
/* hclk gates */
#define HCLK_GPS 448
@@ -137,8 +179,16 @@
#define HCLK_IEP 468
#define HCLK_ISP 469
#define HCLK_RGA 470
#define HCLK_VIO_AHB_ARBI 471
#define HCLK_VIO_NIU 472
#define HCLK_VIP 473
#define HCLK_VIO2_H2P 474
#define HCLK_HEVC 475
#define HCLK_VCODEC 476
#define HCLK_CPU 477
#define HCLK_PERI 478
#define CLK_NR_CLKS (HCLK_RGA + 1)
#define CLK_NR_CLKS (HCLK_PERI + 1)
/* soft-reset indices */
#define SRST_CORE0 0
@@ -276,3 +326,46 @@
#define SRST_USBHOST1_CON 140
#define SRST_USB_ADP 141
#define SRST_ACC_EFUSE 142
#define SRST_CORESIGHT 144
#define SRST_PD_CORE_AHB_NOC 145
#define SRST_PD_CORE_APB_NOC 146
#define SRST_PD_CORE_MP_AXI 147
#define SRST_GIC 148
#define SRST_LCDC_PWM0 149
#define SRST_LCDC_PWM1 150
#define SRST_VIO0_H2P_BRG 151
#define SRST_VIO1_H2P_BRG 152
#define SRST_RGA_H2P_BRG 153
#define SRST_HEVC 154
#define SRST_TSADC 159
#define SRST_DDRPHY0 160
#define SRST_DDRPHY0_APB 161
#define SRST_DDRCTRL0 162
#define SRST_DDRCTRL0_APB 163
#define SRST_DDRPHY0_CTRL 164
#define SRST_DDRPHY1 165
#define SRST_DDRPHY1_APB 166
#define SRST_DDRCTRL1 167
#define SRST_DDRCTRL1_APB 168
#define SRST_DDRPHY1_CTRL 169
#define SRST_DDRMSCH0 170
#define SRST_DDRMSCH1 171
#define SRST_CRYPTO 174
#define SRST_C2C_HOST 175
#define SRST_LCDC1_AXI 176
#define SRST_LCDC1_AHB 177
#define SRST_LCDC1_DCLK 178
#define SRST_UART0 179
#define SRST_UART1 180
#define SRST_UART2 181
#define SRST_UART3 182
#define SRST_UART4 183
#define SRST_SIMC 186
#define SRST_PS2C 187
#define SRST_TSP 188
#define SRST_TSP_CLKIN0 189
#define SRST_TSP_CLKIN1 190
#define SRST_TSP_27M 191

11
include/dt-bindings/clock/rockchip,rk808.h Normal file
View File

@@ -0,0 +1,11 @@
/*
* This header provides constants clk index RK808 pmic clkout
*/
#ifndef _CLK_ROCKCHIP_RK808
#define _CLK_ROCKCHIP_RK808
/* CLOCKOUT index */
#define RK808_CLKOUT0 0
#define RK808_CLKOUT1 1
#endif

86
include/dt-bindings/clock/stih407-clks.h Normal file
View File

@@ -0,0 +1,86 @@
/*
* This header provides constants clk index STMicroelectronics
* STiH407 SoC.
*/
#ifndef _DT_BINDINGS_CLK_STIH407
#define _DT_BINDINGS_CLK_STIH407
/* CLOCKGEN C0 */
#define CLK_ICN_GPU 0
#define CLK_FDMA 1
#define CLK_NAND 2
#define CLK_HVA 3
#define CLK_PROC_STFE 4
#define CLK_PROC_TP 5
#define CLK_RX_ICN_DMU 6
#define CLK_RX_ICN_DISP_0 6
#define CLK_RX_ICN_DISP_1 6
#define CLK_RX_ICN_HVA 7
#define CLK_RX_ICN_TS 7
#define CLK_ICN_CPU 8
#define CLK_TX_ICN_DMU 9
#define CLK_TX_ICN_HVA 9
#define CLK_TX_ICN_TS 9
#define CLK_ICN_COMPO 9
#define CLK_MMC_0 10
#define CLK_MMC_1 11
#define CLK_JPEGDEC 12
#define CLK_ICN_REG 13
#define CLK_TRACE_A9 13
#define CLK_PTI_STM 13
#define CLK_EXT2F_A9 13
#define CLK_IC_BDISP_0 14
#define CLK_IC_BDISP_1 15
#define CLK_PP_DMU 16
#define CLK_VID_DMU 17
#define CLK_DSS_LPC 18
#define CLK_ST231_AUD_0 19
#define CLK_ST231_GP_0 19
#define CLK_ST231_GP_1 20
#define CLK_ST231_DMU 21
#define CLK_ICN_LMI 22
#define CLK_TX_ICN_DISP_0 23
#define CLK_TX_ICN_DISP_1 23
#define CLK_ICN_SBC 24
#define CLK_STFE_FRC2 25
#define CLK_ETH_PHY 26
#define CLK_ETH_REF_PHYCLK 27
#define CLK_FLASH_PROMIP 28
#define CLK_MAIN_DISP 29
#define CLK_AUX_DISP 30
#define CLK_COMPO_DVP 31
/* CLOCKGEN D0 */
#define CLK_PCM_0 0
#define CLK_PCM_1 1
#define CLK_PCM_2 2
#define CLK_SPDIFF 3
/* CLOCKGEN D2 */
#define CLK_PIX_MAIN_DISP 0
#define CLK_PIX_PIP 1
#define CLK_PIX_GDP1 2
#define CLK_PIX_GDP2 3
#define CLK_PIX_GDP3 4
#define CLK_PIX_GDP4 5
#define CLK_PIX_AUX_DISP 6
#define CLK_DENC 7
#define CLK_PIX_HDDAC 8
#define CLK_HDDAC 9
#define CLK_SDDAC 10
#define CLK_PIX_DVO 11
#define CLK_DVO 12
#define CLK_PIX_HDMI 13
#define CLK_TMDS_HDMI 14
#define CLK_REF_HDMIPHY 15
/* CLOCKGEN D3 */
#define CLK_STFE_FRC1 0
#define CLK_TSOUT_0 1
#define CLK_TSOUT_1 2
#define CLK_MCHI 3
#define CLK_VSENS_COMPO 4
#define CLK_FRC1_REMOTE 5
#define CLK_LPC_0 6
#define CLK_LPC_1 7
#endif

25
include/dt-bindings/clock/stih410-clks.h Normal file
View File

@@ -0,0 +1,25 @@
/*
* This header provides constants clk index STMicroelectronics
* STiH410 SoC.
*/
#ifndef _DT_BINDINGS_CLK_STIH410
#define _DT_BINDINGS_CLK_STIH410
#include "stih407-clks.h"
/* STiH410 introduces new clock outputs compared to STiH407 */
/* CLOCKGEN C0 */
#define CLK_TX_ICN_HADES 32
#define CLK_RX_ICN_HADES 33
#define CLK_ICN_REG_16 34
#define CLK_PP_HADES 35
#define CLK_CLUST_HADES 36
#define CLK_HWPE_HADES 37
#define CLK_FC_HADES 38
/* CLOCKGEN D0 */
#define CLK_PCMR10_MASTER 4
#define CLK_USB2_PHY 5
#endif

2
include/dt-bindings/clock/tegra114-car.h
View File

@@ -49,7 +49,7 @@
#define TEGRA114_CLK_I2S0 30
/* 31 */
/* 32 */
#define TEGRA114_CLK_MC 32
/* 33 */
#define TEGRA114_CLK_APBDMA 34
/* 35 */

8
include/dt-bindings/clock/tegra124-car.h
View File

@@ -48,7 +48,7 @@
#define TEGRA124_CLK_I2S0 30
/* 31 */
/* 32 */
#define TEGRA124_CLK_MC 32
/* 33 */
#define TEGRA124_CLK_APBDMA 34
/* 35 */
@@ -337,6 +337,10 @@
#define TEGRA124_CLK_DSIB_MUX 310
#define TEGRA124_CLK_SOR0_LVDS 311
#define TEGRA124_CLK_XUSB_SS_DIV2 312
#define TEGRA124_CLK_CLK_MAX 313
#define TEGRA124_CLK_PLL_M_UD 313
#define TEGRA124_CLK_PLL_C_UD 314
#define TEGRA124_CLK_CLK_MAX 315
#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */

2
include/dt-bindings/clock/tegra20-car.h
View File

@@ -49,7 +49,7 @@
/* 30 */
#define TEGRA20_CLK_CACHE2 31
#define TEGRA20_CLK_MEM 32
#define TEGRA20_CLK_MC 32
#define TEGRA20_CLK_AHBDMA 33
#define TEGRA20_CLK_APBDMA 34
/* 35 */

40
include/dt-bindings/clock/vf610-clock.h
View File

@@ -21,24 +21,24 @@
#define VF610_CLK_FASK_CLK_SEL 8
#define VF610_CLK_AUDIO_EXT 9
#define VF610_CLK_ENET_EXT 10
#define VF610_CLK_PLL1_MAIN 11
#define VF610_CLK_PLL1_SYS 11
#define VF610_CLK_PLL1_PFD1 12
#define VF610_CLK_PLL1_PFD2 13
#define VF610_CLK_PLL1_PFD3 14
#define VF610_CLK_PLL1_PFD4 15
#define VF610_CLK_PLL2_MAIN 16
#define VF610_CLK_PLL2_BUS 16
#define VF610_CLK_PLL2_PFD1 17
#define VF610_CLK_PLL2_PFD2 18
#define VF610_CLK_PLL2_PFD3 19
#define VF610_CLK_PLL2_PFD4 20
#define VF610_CLK_PLL3_MAIN 21
#define VF610_CLK_PLL3_USB_OTG 21
#define VF610_CLK_PLL3_PFD1 22
#define VF610_CLK_PLL3_PFD2 23
#define VF610_CLK_PLL3_PFD3 24
#define VF610_CLK_PLL3_PFD4 25
#define VF610_CLK_PLL4_MAIN 26
#define VF610_CLK_PLL5_MAIN 27
#define VF610_CLK_PLL6_MAIN 28
#define VF610_CLK_PLL4_AUDIO 26
#define VF610_CLK_PLL5_ENET 27
#define VF610_CLK_PLL6_VIDEO 28
#define VF610_CLK_PLL3_MAIN_DIV 29
#define VF610_CLK_PLL4_MAIN_DIV 30
#define VF610_CLK_PLL6_MAIN_DIV 31
@@ -166,6 +166,32 @@
#define VF610_CLK_DMAMUX3 153
#define VF610_CLK_FLEXCAN0_EN 154
#define VF610_CLK_FLEXCAN1_EN 155
#define VF610_CLK_END 156
#define VF610_CLK_PLL7_USB_HOST 156
#define VF610_CLK_USBPHY0 157
#define VF610_CLK_USBPHY1 158
#define VF610_CLK_LVDS1_IN 159
#define VF610_CLK_ANACLK1 160
#define VF610_CLK_PLL1_BYPASS_SRC 161
#define VF610_CLK_PLL2_BYPASS_SRC 162
#define VF610_CLK_PLL3_BYPASS_SRC 163
#define VF610_CLK_PLL4_BYPASS_SRC 164
#define VF610_CLK_PLL5_BYPASS_SRC 165
#define VF610_CLK_PLL6_BYPASS_SRC 166
#define VF610_CLK_PLL7_BYPASS_SRC 167
#define VF610_CLK_PLL1 168
#define VF610_CLK_PLL2 169
#define VF610_CLK_PLL3 170
#define VF610_CLK_PLL4 171
#define VF610_CLK_PLL5 172
#define VF610_CLK_PLL6 173
#define VF610_CLK_PLL7 174
#define VF610_PLL1_BYPASS 175
#define VF610_PLL2_BYPASS 176
#define VF610_PLL3_BYPASS 177
#define VF610_PLL4_BYPASS 178
#define VF610_PLL5_BYPASS 179
#define VF610_PLL6_BYPASS 180
#define VF610_PLL7_BYPASS 181
#define VF610_CLK_END 182
#endif /* __DT_BINDINGS_CLOCK_VF610_H */

25
include/dt-bindings/dma/at91.h
View File

@@ -9,6 +9,8 @@
#ifndef __DT_BINDINGS_AT91_DMA_H__
#define __DT_BINDINGS_AT91_DMA_H__
/* ---------- HDMAC ---------- */
/*
* Source and/or destination peripheral ID
*/
@@ -24,4 +26,27 @@
#define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */
#define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */
/* ---------- XDMAC ---------- */
#define AT91_XDMAC_DT_MEM_IF_MASK (0x1)
#define AT91_XDMAC_DT_MEM_IF_OFFSET (13)
#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \
<< AT91_XDMAC_DT_MEM_IF_OFFSET)
#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
& AT91_XDMAC_DT_MEM_IF_MASK)
#define AT91_XDMAC_DT_PER_IF_MASK (0x1)
#define AT91_XDMAC_DT_PER_IF_OFFSET (14)
#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \
<< AT91_XDMAC_DT_PER_IF_OFFSET)
#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
& AT91_XDMAC_DT_PER_IF_MASK)
#define AT91_XDMAC_DT_PERID_MASK (0x7f)
#define AT91_XDMAC_DT_PERID_OFFSET (24)
#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \
<< AT91_XDMAC_DT_PERID_OFFSET)
#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
& AT91_XDMAC_DT_PERID_MASK)
#endif /* __DT_BINDINGS_AT91_DMA_H__ */

9
include/dt-bindings/interrupt-controller/mips-gic.h Normal file
View File

@@ -0,0 +1,9 @@
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H
#include <dt-bindings/interrupt-controller/irq.h>
#define GIC_SHARED 0
#define GIC_LOCAL 1
#endif

25
include/dt-bindings/memory/tegra114-mc.h Normal file
View File

@@ -0,0 +1,25 @@
#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H
#define DT_BINDINGS_MEMORY_TEGRA114_MC_H
#define TEGRA_SWGROUP_PTC 0
#define TEGRA_SWGROUP_DC 1
#define TEGRA_SWGROUP_DCB 2
#define TEGRA_SWGROUP_EPP 3
#define TEGRA_SWGROUP_G2 4
#define TEGRA_SWGROUP_AVPC 5
#define TEGRA_SWGROUP_NV 6
#define TEGRA_SWGROUP_HDA 7
#define TEGRA_SWGROUP_HC 8
#define TEGRA_SWGROUP_MSENC 9
#define TEGRA_SWGROUP_PPCS 10
#define TEGRA_SWGROUP_VDE 11
#define TEGRA_SWGROUP_MPCORELP 12
#define TEGRA_SWGROUP_MPCORE 13
#define TEGRA_SWGROUP_VI 14
#define TEGRA_SWGROUP_ISP 15
#define TEGRA_SWGROUP_XUSB_HOST 16
#define TEGRA_SWGROUP_XUSB_DEV 17
#define TEGRA_SWGROUP_EMUCIF 18
#define TEGRA_SWGROUP_TSEC 19
#endif

31
include/dt-bindings/memory/tegra124-mc.h Normal file
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#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H
#define DT_BINDINGS_MEMORY_TEGRA124_MC_H
#define TEGRA_SWGROUP_PTC 0
#define TEGRA_SWGROUP_DC 1
#define TEGRA_SWGROUP_DCB 2
#define TEGRA_SWGROUP_AFI 3
#define TEGRA_SWGROUP_AVPC 4
#define TEGRA_SWGROUP_HDA 5
#define TEGRA_SWGROUP_HC 6
#define TEGRA_SWGROUP_MSENC 7
#define TEGRA_SWGROUP_PPCS 8
#define TEGRA_SWGROUP_SATA 9
#define TEGRA_SWGROUP_VDE 10
#define TEGRA_SWGROUP_MPCORELP 11
#define TEGRA_SWGROUP_MPCORE 12
#define TEGRA_SWGROUP_ISP2 13
#define TEGRA_SWGROUP_XUSB_HOST 14
#define TEGRA_SWGROUP_XUSB_DEV 15
#define TEGRA_SWGROUP_ISP2B 16
#define TEGRA_SWGROUP_TSEC 17
#define TEGRA_SWGROUP_A9AVP 18
#define TEGRA_SWGROUP_GPU 19
#define TEGRA_SWGROUP_SDMMC1A 20
#define TEGRA_SWGROUP_SDMMC2A 21
#define TEGRA_SWGROUP_SDMMC3A 22
#define TEGRA_SWGROUP_SDMMC4A 23
#define TEGRA_SWGROUP_VIC 24
#define TEGRA_SWGROUP_VI 25
#endif

24
include/dt-bindings/memory/tegra30-mc.h Normal file
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#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
#define DT_BINDINGS_MEMORY_TEGRA30_MC_H
#define TEGRA_SWGROUP_PTC 0
#define TEGRA_SWGROUP_DC 1
#define TEGRA_SWGROUP_DCB 2
#define TEGRA_SWGROUP_EPP 3
#define TEGRA_SWGROUP_G2 4
#define TEGRA_SWGROUP_MPE 5
#define TEGRA_SWGROUP_VI 6
#define TEGRA_SWGROUP_AFI 7
#define TEGRA_SWGROUP_AVPC 8
#define TEGRA_SWGROUP_NV 9
#define TEGRA_SWGROUP_NV2 10
#define TEGRA_SWGROUP_HDA 11
#define TEGRA_SWGROUP_HC 12
#define TEGRA_SWGROUP_PPCS 13
#define TEGRA_SWGROUP_SATA 14
#define TEGRA_SWGROUP_VDE 15
#define TEGRA_SWGROUP_MPCORELP 16
#define TEGRA_SWGROUP_MPCORE 17
#define TEGRA_SWGROUP_ISP 18
#endif

19
include/dt-bindings/phy/phy.h Normal file
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/*
*
* This header provides constants for the phy framework
*
* Copyright (C) 2014 STMicroelectronics
* Author: Gabriel Fernandez <gabriel.fernandez@st.com>
* License terms: GNU General Public License (GPL), version 2
*/
#ifndef _DT_BINDINGS_PHY
#define _DT_BINDINGS_PHY
#define PHY_NONE 0
#define PHY_TYPE_SATA 1
#define PHY_TYPE_PCIE 2
#define PHY_TYPE_USB2 3
#define PHY_TYPE_USB3 4
#endif /* _DT_BINDINGS_PHY */

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