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Merge tag 'riscv-for-linus-6.19-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Browse Source 
Pull RISC-V updates from Paul Walmsley:

 - Enable parallel hotplug for RISC-V

 - Optimize vector regset allocation for ptrace()

 - Add a kernel selftest for the vector ptrace interface

 - Enable the userspace RAID6 test to build and run using RISC-V vectors

 - Add initial support for the Zalasr RISC-V ratified ISA extension

 - For the Zicbop RISC-V ratified ISA extension to userspace, expose
   hardware and kernel support to userspace and add a kselftest for
   Zicbop

 - Convert open-coded instances of 'asm goto's that are controlled by
   runtime ALTERNATIVEs to use riscv_has_extension_{un,}likely(),
   following arm64's alternative_has_cap_{un,}likely()

 - Remove an unnecessary mask in the GFP flags used in some calls to
   pagetable_alloc()

* tag 'riscv-for-linus-6.19-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  selftests/riscv: Add Zicbop prefetch test
  riscv: hwprobe: Expose Zicbop extension and its block size
  riscv: Introduce Zalasr instructions
  riscv: hwprobe: Export Zalasr extension
  dt-bindings: riscv: Add Zalasr ISA extension description
  riscv: Add ISA extension parsing for Zalasr
  selftests: riscv: Add test for the Vector ptrace interface
  riscv: ptrace: Optimize the allocation of vector regset
  raid6: test: Add support for RISC-V
  raid6: riscv: Allow code to be compiled in userspace
  raid6: riscv: Prevent compiler from breaking inline vector assembly code
  riscv: cmpxchg: Use riscv_has_extension_likely
  riscv: bitops: Use riscv_has_extension_likely
  riscv: hweight: Use riscv_has_extension_likely
  riscv: checksum: Use riscv_has_extension_likely
  riscv: pgtable: Use riscv_has_extension_unlikely
  riscv: Remove __GFP_HIGHMEM masking
  RISC-V: Enable HOTPLUG_PARALLEL for secondary CPUs
This commit is contained in:
Linus Torvalds
2025-12-05 16:26:57 -08:00
parent ad952db4a8 a131fd6079
commit 07025b51c1
28 changed files with 656 additions and 305 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
lib/raid6/recov_rvv.c
View File

@@ -4,13 +4,8 @@
* Author: Chunyan Zhang <zhangchunyan@iscas.ac.cn>
*/
#include <asm/vector.h>
#include <linux/raid/pq.h>
static int rvv_has_vector(void)
{
return has_vector();
}
#include "rvv.h"
static void __raid6_2data_recov_rvv(int bytes, u8 *p, u8 *q, u8 *dp,
u8 *dq, const u8 *pbmul,

299
lib/raid6/rvv.c
View File

@@ -9,22 +9,17 @@
* Copyright 2002-2004 H. Peter Anvin
*/
#include <asm/vector.h>
#include <linux/raid/pq.h>
#include "rvv.h"
#define NSIZE (riscv_v_vsize / 32) /* NSIZE = vlenb */
static int rvv_has_vector(void)
{
return has_vector();
}
#ifdef __riscv_vector
#error "This code must be built without compiler support for vector"
#endif
static void raid6_rvv1_gen_syndrome_real(int disks, unsigned long bytes, void **ptrs)
{
u8 **dptr = (u8 **)ptrs;
u8 *p, *q;
unsigned long vl, d;
unsigned long vl, d, nsize;
int z, z0;
z0 = disks - 3; /* Highest data disk */
@@ -38,8 +33,10 @@ static void raid6_rvv1_gen_syndrome_real(int disks, unsigned long bytes, void **
: "=&r" (vl)
);
nsize = vl;
/* v0:wp0, v1:wq0, v2:wd0/w20, v3:w10 */
for (d = 0; d < bytes; d += NSIZE * 1) {
for (d = 0; d < bytes; d += nsize * 1) {
/* wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE]; */
asm volatile (".option push\n"
".option arch,+v\n"
@@ -47,7 +44,7 @@ static void raid6_rvv1_gen_syndrome_real(int disks, unsigned long bytes, void **
"vmv.v.v v1, v0\n"
".option pop\n"
: :
[wp0]"r"(&dptr[z0][d + 0 * NSIZE])
[wp0]"r"(&dptr[z0][d + 0 * nsize])
);
for (z = z0 - 1 ; z >= 0 ; z--) {
@@ -71,7 +68,7 @@ static void raid6_rvv1_gen_syndrome_real(int disks, unsigned long bytes, void **
"vxor.vv v0, v0, v2\n"
".option pop\n"
: :
[wd0]"r"(&dptr[z][d + 0 * NSIZE]),
[wd0]"r"(&dptr[z][d + 0 * nsize]),
[x1d]"r"(0x1d)
);
}
@@ -86,8 +83,8 @@ static void raid6_rvv1_gen_syndrome_real(int disks, unsigned long bytes, void **
"vse8.v v1, (%[wq0])\n"
".option pop\n"
: :
[wp0]"r"(&p[d + NSIZE * 0]),
[wq0]"r"(&q[d + NSIZE * 0])
[wp0]"r"(&p[d + nsize * 0]),
[wq0]"r"(&q[d + nsize * 0])
);
}
}
@@ -97,7 +94,7 @@ static void raid6_rvv1_xor_syndrome_real(int disks, int start, int stop,
{
u8 **dptr = (u8 **)ptrs;
u8 *p, *q;
unsigned long vl, d;
unsigned long vl, d, nsize;
int z, z0;
z0 = stop; /* P/Q right side optimization */
@@ -111,8 +108,10 @@ static void raid6_rvv1_xor_syndrome_real(int disks, int start, int stop,
: "=&r" (vl)
);
nsize = vl;
/* v0:wp0, v1:wq0, v2:wd0/w20, v3:w10 */
for (d = 0 ; d < bytes ; d += NSIZE * 1) {
for (d = 0 ; d < bytes ; d += nsize * 1) {
/* wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE]; */
asm volatile (".option push\n"
".option arch,+v\n"
@@ -120,7 +119,7 @@ static void raid6_rvv1_xor_syndrome_real(int disks, int start, int stop,
"vmv.v.v v1, v0\n"
".option pop\n"
: :
[wp0]"r"(&dptr[z0][d + 0 * NSIZE])
[wp0]"r"(&dptr[z0][d + 0 * nsize])
);
/* P/Q data pages */
@@ -145,7 +144,7 @@ static void raid6_rvv1_xor_syndrome_real(int disks, int start, int stop,
"vxor.vv v0, v0, v2\n"
".option pop\n"
: :
[wd0]"r"(&dptr[z][d + 0 * NSIZE]),
[wd0]"r"(&dptr[z][d + 0 * nsize]),
[x1d]"r"(0x1d)
);
}
@@ -185,8 +184,8 @@ static void raid6_rvv1_xor_syndrome_real(int disks, int start, int stop,
"vse8.v v3, (%[wq0])\n"
".option pop\n"
: :
[wp0]"r"(&p[d + NSIZE * 0]),
[wq0]"r"(&q[d + NSIZE * 0])
[wp0]"r"(&p[d + nsize * 0]),
[wq0]"r"(&q[d + nsize * 0])
);
}
}
@@ -195,7 +194,7 @@ static void raid6_rvv2_gen_syndrome_real(int disks, unsigned long bytes, void **
{
u8 **dptr = (u8 **)ptrs;
u8 *p, *q;
unsigned long vl, d;
unsigned long vl, d, nsize;
int z, z0;
z0 = disks - 3; /* Highest data disk */
@@ -209,11 +208,13 @@ static void raid6_rvv2_gen_syndrome_real(int disks, unsigned long bytes, void **
: "=&r" (vl)
);
nsize = vl;
/*
* v0:wp0, v1:wq0, v2:wd0/w20, v3:w10
* v4:wp1, v5:wq1, v6:wd1/w21, v7:w11
*/
for (d = 0; d < bytes; d += NSIZE * 2) {
for (d = 0; d < bytes; d += nsize * 2) {
/* wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE]; */
asm volatile (".option push\n"
".option arch,+v\n"
@@ -223,8 +224,8 @@ static void raid6_rvv2_gen_syndrome_real(int disks, unsigned long bytes, void **
"vmv.v.v v5, v4\n"
".option pop\n"
: :
[wp0]"r"(&dptr[z0][d + 0 * NSIZE]),
[wp1]"r"(&dptr[z0][d + 1 * NSIZE])
[wp0]"r"(&dptr[z0][d + 0 * nsize]),
[wp1]"r"(&dptr[z0][d + 1 * nsize])
);
for (z = z0 - 1; z >= 0; z--) {
@@ -256,8 +257,8 @@ static void raid6_rvv2_gen_syndrome_real(int disks, unsigned long bytes, void **
"vxor.vv v4, v4, v6\n"
".option pop\n"
: :
[wd0]"r"(&dptr[z][d + 0 * NSIZE]),
[wd1]"r"(&dptr[z][d + 1 * NSIZE]),
[wd0]"r"(&dptr[z][d + 0 * nsize]),
[wd1]"r"(&dptr[z][d + 1 * nsize]),
[x1d]"r"(0x1d)
);
}
@@ -274,10 +275,10 @@ static void raid6_rvv2_gen_syndrome_real(int disks, unsigned long bytes, void **
"vse8.v v5, (%[wq1])\n"
".option pop\n"
: :
[wp0]"r"(&p[d + NSIZE * 0]),
[wq0]"r"(&q[d + NSIZE * 0]),
[wp1]"r"(&p[d + NSIZE * 1]),
[wq1]"r"(&q[d + NSIZE * 1])
[wp0]"r"(&p[d + nsize * 0]),
[wq0]"r"(&q[d + nsize * 0]),
[wp1]"r"(&p[d + nsize * 1]),
[wq1]"r"(&q[d + nsize * 1])
);
}
}
@@ -287,7 +288,7 @@ static void raid6_rvv2_xor_syndrome_real(int disks, int start, int stop,
{
u8 **dptr = (u8 **)ptrs;
u8 *p, *q;
unsigned long vl, d;
unsigned long vl, d, nsize;
int z, z0;
z0 = stop; /* P/Q right side optimization */
@@ -301,11 +302,13 @@ static void raid6_rvv2_xor_syndrome_real(int disks, int start, int stop,
: "=&r" (vl)
);
nsize = vl;
/*
* v0:wp0, v1:wq0, v2:wd0/w20, v3:w10
* v4:wp1, v5:wq1, v6:wd1/w21, v7:w11
*/
for (d = 0; d < bytes; d += NSIZE * 2) {
for (d = 0; d < bytes; d += nsize * 2) {
/* wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE]; */
asm volatile (".option push\n"
".option arch,+v\n"
@@ -315,8 +318,8 @@ static void raid6_rvv2_xor_syndrome_real(int disks, int start, int stop,
"vmv.v.v v5, v4\n"
".option pop\n"
: :
[wp0]"r"(&dptr[z0][d + 0 * NSIZE]),
[wp1]"r"(&dptr[z0][d + 1 * NSIZE])
[wp0]"r"(&dptr[z0][d + 0 * nsize]),
[wp1]"r"(&dptr[z0][d + 1 * nsize])
);
/* P/Q data pages */
@@ -349,8 +352,8 @@ static void raid6_rvv2_xor_syndrome_real(int disks, int start, int stop,
"vxor.vv v4, v4, v6\n"
".option pop\n"
: :
[wd0]"r"(&dptr[z][d + 0 * NSIZE]),
[wd1]"r"(&dptr[z][d + 1 * NSIZE]),
[wd0]"r"(&dptr[z][d + 0 * nsize]),
[wd1]"r"(&dptr[z][d + 1 * nsize]),
[x1d]"r"(0x1d)
);
}
@@ -403,10 +406,10 @@ static void raid6_rvv2_xor_syndrome_real(int disks, int start, int stop,
"vse8.v v7, (%[wq1])\n"
".option pop\n"
: :
[wp0]"r"(&p[d + NSIZE * 0]),
[wq0]"r"(&q[d + NSIZE * 0]),
[wp1]"r"(&p[d + NSIZE * 1]),
[wq1]"r"(&q[d + NSIZE * 1])
[wp0]"r"(&p[d + nsize * 0]),
[wq0]"r"(&q[d + nsize * 0]),
[wp1]"r"(&p[d + nsize * 1]),
[wq1]"r"(&q[d + nsize * 1])
);
}
}
@@ -415,7 +418,7 @@ static void raid6_rvv4_gen_syndrome_real(int disks, unsigned long bytes, void **
{
u8 **dptr = (u8 **)ptrs;
u8 *p, *q;
unsigned long vl, d;
unsigned long vl, d, nsize;
int z, z0;
z0 = disks - 3; /* Highest data disk */
@@ -429,13 +432,15 @@ static void raid6_rvv4_gen_syndrome_real(int disks, unsigned long bytes, void **
: "=&r" (vl)
);
nsize = vl;
/*
* v0:wp0, v1:wq0, v2:wd0/w20, v3:w10
* v4:wp1, v5:wq1, v6:wd1/w21, v7:w11
* v8:wp2, v9:wq2, v10:wd2/w22, v11:w12
* v12:wp3, v13:wq3, v14:wd3/w23, v15:w13
*/
for (d = 0; d < bytes; d += NSIZE * 4) {
for (d = 0; d < bytes; d += nsize * 4) {
/* wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE]; */
asm volatile (".option push\n"
".option arch,+v\n"
@@ -449,10 +454,10 @@ static void raid6_rvv4_gen_syndrome_real(int disks, unsigned long bytes, void **
"vmv.v.v v13, v12\n"
".option pop\n"
: :
[wp0]"r"(&dptr[z0][d + 0 * NSIZE]),
[wp1]"r"(&dptr[z0][d + 1 * NSIZE]),
[wp2]"r"(&dptr[z0][d + 2 * NSIZE]),
[wp3]"r"(&dptr[z0][d + 3 * NSIZE])
[wp0]"r"(&dptr[z0][d + 0 * nsize]),
[wp1]"r"(&dptr[z0][d + 1 * nsize]),
[wp2]"r"(&dptr[z0][d + 2 * nsize]),
[wp3]"r"(&dptr[z0][d + 3 * nsize])
);
for (z = z0 - 1; z >= 0; z--) {
@@ -500,10 +505,10 @@ static void raid6_rvv4_gen_syndrome_real(int disks, unsigned long bytes, void **
"vxor.vv v12, v12, v14\n"
".option pop\n"
: :
[wd0]"r"(&dptr[z][d + 0 * NSIZE]),
[wd1]"r"(&dptr[z][d + 1 * NSIZE]),
[wd2]"r"(&dptr[z][d + 2 * NSIZE]),
[wd3]"r"(&dptr[z][d + 3 * NSIZE]),
[wd0]"r"(&dptr[z][d + 0 * nsize]),
[wd1]"r"(&dptr[z][d + 1 * nsize]),
[wd2]"r"(&dptr[z][d + 2 * nsize]),
[wd3]"r"(&dptr[z][d + 3 * nsize]),
[x1d]"r"(0x1d)
);
}
@@ -524,14 +529,14 @@ static void raid6_rvv4_gen_syndrome_real(int disks, unsigned long bytes, void **
"vse8.v v13, (%[wq3])\n"
".option pop\n"
: :
[wp0]"r"(&p[d + NSIZE * 0]),
[wq0]"r"(&q[d + NSIZE * 0]),
[wp1]"r"(&p[d + NSIZE * 1]),
[wq1]"r"(&q[d + NSIZE * 1]),
[wp2]"r"(&p[d + NSIZE * 2]),
[wq2]"r"(&q[d + NSIZE * 2]),
[wp3]"r"(&p[d + NSIZE * 3]),
[wq3]"r"(&q[d + NSIZE * 3])
[wp0]"r"(&p[d + nsize * 0]),
[wq0]"r"(&q[d + nsize * 0]),
[wp1]"r"(&p[d + nsize * 1]),
[wq1]"r"(&q[d + nsize * 1]),
[wp2]"r"(&p[d + nsize * 2]),
[wq2]"r"(&q[d + nsize * 2]),
[wp3]"r"(&p[d + nsize * 3]),
[wq3]"r"(&q[d + nsize * 3])
);
}
}
@@ -541,7 +546,7 @@ static void raid6_rvv4_xor_syndrome_real(int disks, int start, int stop,
{
u8 **dptr = (u8 **)ptrs;
u8 *p, *q;
unsigned long vl, d;
unsigned long vl, d, nsize;
int z, z0;
z0 = stop; /* P/Q right side optimization */
@@ -555,13 +560,15 @@ static void raid6_rvv4_xor_syndrome_real(int disks, int start, int stop,
: "=&r" (vl)
);
nsize = vl;
/*
* v0:wp0, v1:wq0, v2:wd0/w20, v3:w10
* v4:wp1, v5:wq1, v6:wd1/w21, v7:w11
* v8:wp2, v9:wq2, v10:wd2/w22, v11:w12
* v12:wp3, v13:wq3, v14:wd3/w23, v15:w13
*/
for (d = 0; d < bytes; d += NSIZE * 4) {
for (d = 0; d < bytes; d += nsize * 4) {
/* wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE]; */
asm volatile (".option push\n"
".option arch,+v\n"
@@ -575,10 +582,10 @@ static void raid6_rvv4_xor_syndrome_real(int disks, int start, int stop,
"vmv.v.v v13, v12\n"
".option pop\n"
: :
[wp0]"r"(&dptr[z0][d + 0 * NSIZE]),
[wp1]"r"(&dptr[z0][d + 1 * NSIZE]),
[wp2]"r"(&dptr[z0][d + 2 * NSIZE]),
[wp3]"r"(&dptr[z0][d + 3 * NSIZE])
[wp0]"r"(&dptr[z0][d + 0 * nsize]),
[wp1]"r"(&dptr[z0][d + 1 * nsize]),
[wp2]"r"(&dptr[z0][d + 2 * nsize]),
[wp3]"r"(&dptr[z0][d + 3 * nsize])
);
/* P/Q data pages */
@@ -627,10 +634,10 @@ static void raid6_rvv4_xor_syndrome_real(int disks, int start, int stop,
"vxor.vv v12, v12, v14\n"
".option pop\n"
: :
[wd0]"r"(&dptr[z][d + 0 * NSIZE]),
[wd1]"r"(&dptr[z][d + 1 * NSIZE]),
[wd2]"r"(&dptr[z][d + 2 * NSIZE]),
[wd3]"r"(&dptr[z][d + 3 * NSIZE]),
[wd0]"r"(&dptr[z][d + 0 * nsize]),
[wd1]"r"(&dptr[z][d + 1 * nsize]),
[wd2]"r"(&dptr[z][d + 2 * nsize]),
[wd3]"r"(&dptr[z][d + 3 * nsize]),
[x1d]"r"(0x1d)
);
}
@@ -709,14 +716,14 @@ static void raid6_rvv4_xor_syndrome_real(int disks, int start, int stop,
"vse8.v v15, (%[wq3])\n"
".option pop\n"
: :
[wp0]"r"(&p[d + NSIZE * 0]),
[wq0]"r"(&q[d + NSIZE * 0]),
[wp1]"r"(&p[d + NSIZE * 1]),
[wq1]"r"(&q[d + NSIZE * 1]),
[wp2]"r"(&p[d + NSIZE * 2]),
[wq2]"r"(&q[d + NSIZE * 2]),
[wp3]"r"(&p[d + NSIZE * 3]),
[wq3]"r"(&q[d + NSIZE * 3])
[wp0]"r"(&p[d + nsize * 0]),
[wq0]"r"(&q[d + nsize * 0]),
[wp1]"r"(&p[d + nsize * 1]),
[wq1]"r"(&q[d + nsize * 1]),
[wp2]"r"(&p[d + nsize * 2]),
[wq2]"r"(&q[d + nsize * 2]),
[wp3]"r"(&p[d + nsize * 3]),
[wq3]"r"(&q[d + nsize * 3])
);
}
}
@@ -725,7 +732,7 @@ static void raid6_rvv8_gen_syndrome_real(int disks, unsigned long bytes, void **
{
u8 **dptr = (u8 **)ptrs;
u8 *p, *q;
unsigned long vl, d;
unsigned long vl, d, nsize;
int z, z0;
z0 = disks - 3; /* Highest data disk */
@@ -739,6 +746,8 @@ static void raid6_rvv8_gen_syndrome_real(int disks, unsigned long bytes, void **
: "=&r" (vl)
);
nsize = vl;
/*
* v0:wp0, v1:wq0, v2:wd0/w20, v3:w10
* v4:wp1, v5:wq1, v6:wd1/w21, v7:w11
@@ -749,7 +758,7 @@ static void raid6_rvv8_gen_syndrome_real(int disks, unsigned long bytes, void **
* v24:wp6, v25:wq6, v26:wd6/w26, v27:w16
* v28:wp7, v29:wq7, v30:wd7/w27, v31:w17
*/
for (d = 0; d < bytes; d += NSIZE * 8) {
for (d = 0; d < bytes; d += nsize * 8) {
/* wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE]; */
asm volatile (".option push\n"
".option arch,+v\n"
@@ -771,14 +780,14 @@ static void raid6_rvv8_gen_syndrome_real(int disks, unsigned long bytes, void **
"vmv.v.v v29, v28\n"
".option pop\n"
: :
[wp0]"r"(&dptr[z0][d + 0 * NSIZE]),
[wp1]"r"(&dptr[z0][d + 1 * NSIZE]),
[wp2]"r"(&dptr[z0][d + 2 * NSIZE]),
[wp3]"r"(&dptr[z0][d + 3 * NSIZE]),
[wp4]"r"(&dptr[z0][d + 4 * NSIZE]),
[wp5]"r"(&dptr[z0][d + 5 * NSIZE]),
[wp6]"r"(&dptr[z0][d + 6 * NSIZE]),
[wp7]"r"(&dptr[z0][d + 7 * NSIZE])
[wp0]"r"(&dptr[z0][d + 0 * nsize]),
[wp1]"r"(&dptr[z0][d + 1 * nsize]),
[wp2]"r"(&dptr[z0][d + 2 * nsize]),
[wp3]"r"(&dptr[z0][d + 3 * nsize]),
[wp4]"r"(&dptr[z0][d + 4 * nsize]),
[wp5]"r"(&dptr[z0][d + 5 * nsize]),
[wp6]"r"(&dptr[z0][d + 6 * nsize]),
[wp7]"r"(&dptr[z0][d + 7 * nsize])
);
for (z = z0 - 1; z >= 0; z--) {
@@ -858,14 +867,14 @@ static void raid6_rvv8_gen_syndrome_real(int disks, unsigned long bytes, void **
"vxor.vv v28, v28, v30\n"
".option pop\n"
: :
[wd0]"r"(&dptr[z][d + 0 * NSIZE]),
[wd1]"r"(&dptr[z][d + 1 * NSIZE]),
[wd2]"r"(&dptr[z][d + 2 * NSIZE]),
[wd3]"r"(&dptr[z][d + 3 * NSIZE]),
[wd4]"r"(&dptr[z][d + 4 * NSIZE]),
[wd5]"r"(&dptr[z][d + 5 * NSIZE]),
[wd6]"r"(&dptr[z][d + 6 * NSIZE]),
[wd7]"r"(&dptr[z][d + 7 * NSIZE]),
[wd0]"r"(&dptr[z][d + 0 * nsize]),
[wd1]"r"(&dptr[z][d + 1 * nsize]),
[wd2]"r"(&dptr[z][d + 2 * nsize]),
[wd3]"r"(&dptr[z][d + 3 * nsize]),
[wd4]"r"(&dptr[z][d + 4 * nsize]),
[wd5]"r"(&dptr[z][d + 5 * nsize]),
[wd6]"r"(&dptr[z][d + 6 * nsize]),
[wd7]"r"(&dptr[z][d + 7 * nsize]),
[x1d]"r"(0x1d)
);
}
@@ -894,22 +903,22 @@ static void raid6_rvv8_gen_syndrome_real(int disks, unsigned long bytes, void **
"vse8.v v29, (%[wq7])\n"
".option pop\n"
: :
[wp0]"r"(&p[d + NSIZE * 0]),
[wq0]"r"(&q[d + NSIZE * 0]),
[wp1]"r"(&p[d + NSIZE * 1]),
[wq1]"r"(&q[d + NSIZE * 1]),
[wp2]"r"(&p[d + NSIZE * 2]),
[wq2]"r"(&q[d + NSIZE * 2]),
[wp3]"r"(&p[d + NSIZE * 3]),
[wq3]"r"(&q[d + NSIZE * 3]),
[wp4]"r"(&p[d + NSIZE * 4]),
[wq4]"r"(&q[d + NSIZE * 4]),
[wp5]"r"(&p[d + NSIZE * 5]),
[wq5]"r"(&q[d + NSIZE * 5]),
[wp6]"r"(&p[d + NSIZE * 6]),
[wq6]"r"(&q[d + NSIZE * 6]),
[wp7]"r"(&p[d + NSIZE * 7]),
[wq7]"r"(&q[d + NSIZE * 7])
[wp0]"r"(&p[d + nsize * 0]),
[wq0]"r"(&q[d + nsize * 0]),
[wp1]"r"(&p[d + nsize * 1]),
[wq1]"r"(&q[d + nsize * 1]),
[wp2]"r"(&p[d + nsize * 2]),
[wq2]"r"(&q[d + nsize * 2]),
[wp3]"r"(&p[d + nsize * 3]),
[wq3]"r"(&q[d + nsize * 3]),
[wp4]"r"(&p[d + nsize * 4]),
[wq4]"r"(&q[d + nsize * 4]),
[wp5]"r"(&p[d + nsize * 5]),
[wq5]"r"(&q[d + nsize * 5]),
[wp6]"r"(&p[d + nsize * 6]),
[wq6]"r"(&q[d + nsize * 6]),
[wp7]"r"(&p[d + nsize * 7]),
[wq7]"r"(&q[d + nsize * 7])
);
}
}
@@ -919,7 +928,7 @@ static void raid6_rvv8_xor_syndrome_real(int disks, int start, int stop,
{
u8 **dptr = (u8 **)ptrs;
u8 *p, *q;
unsigned long vl, d;
unsigned long vl, d, nsize;
int z, z0;
z0 = stop; /* P/Q right side optimization */
@@ -933,6 +942,8 @@ static void raid6_rvv8_xor_syndrome_real(int disks, int start, int stop,
: "=&r" (vl)
);
nsize = vl;
/*
* v0:wp0, v1:wq0, v2:wd0/w20, v3:w10
* v4:wp1, v5:wq1, v6:wd1/w21, v7:w11
@@ -943,7 +954,7 @@ static void raid6_rvv8_xor_syndrome_real(int disks, int start, int stop,
* v24:wp6, v25:wq6, v26:wd6/w26, v27:w16
* v28:wp7, v29:wq7, v30:wd7/w27, v31:w17
*/
for (d = 0; d < bytes; d += NSIZE * 8) {
for (d = 0; d < bytes; d += nsize * 8) {
/* wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE]; */
asm volatile (".option push\n"
".option arch,+v\n"
@@ -965,14 +976,14 @@ static void raid6_rvv8_xor_syndrome_real(int disks, int start, int stop,
"vmv.v.v v29, v28\n"
".option pop\n"
: :
[wp0]"r"(&dptr[z0][d + 0 * NSIZE]),
[wp1]"r"(&dptr[z0][d + 1 * NSIZE]),
[wp2]"r"(&dptr[z0][d + 2 * NSIZE]),
[wp3]"r"(&dptr[z0][d + 3 * NSIZE]),
[wp4]"r"(&dptr[z0][d + 4 * NSIZE]),
[wp5]"r"(&dptr[z0][d + 5 * NSIZE]),
[wp6]"r"(&dptr[z0][d + 6 * NSIZE]),
[wp7]"r"(&dptr[z0][d + 7 * NSIZE])
[wp0]"r"(&dptr[z0][d + 0 * nsize]),
[wp1]"r"(&dptr[z0][d + 1 * nsize]),
[wp2]"r"(&dptr[z0][d + 2 * nsize]),
[wp3]"r"(&dptr[z0][d + 3 * nsize]),
[wp4]"r"(&dptr[z0][d + 4 * nsize]),
[wp5]"r"(&dptr[z0][d + 5 * nsize]),
[wp6]"r"(&dptr[z0][d + 6 * nsize]),
[wp7]"r"(&dptr[z0][d + 7 * nsize])
);
/* P/Q data pages */
@@ -1053,14 +1064,14 @@ static void raid6_rvv8_xor_syndrome_real(int disks, int start, int stop,
"vxor.vv v28, v28, v30\n"
".option pop\n"
: :
[wd0]"r"(&dptr[z][d + 0 * NSIZE]),
[wd1]"r"(&dptr[z][d + 1 * NSIZE]),
[wd2]"r"(&dptr[z][d + 2 * NSIZE]),
[wd3]"r"(&dptr[z][d + 3 * NSIZE]),
[wd4]"r"(&dptr[z][d + 4 * NSIZE]),
[wd5]"r"(&dptr[z][d + 5 * NSIZE]),
[wd6]"r"(&dptr[z][d + 6 * NSIZE]),
[wd7]"r"(&dptr[z][d + 7 * NSIZE]),
[wd0]"r"(&dptr[z][d + 0 * nsize]),
[wd1]"r"(&dptr[z][d + 1 * nsize]),
[wd2]"r"(&dptr[z][d + 2 * nsize]),
[wd3]"r"(&dptr[z][d + 3 * nsize]),
[wd4]"r"(&dptr[z][d + 4 * nsize]),
[wd5]"r"(&dptr[z][d + 5 * nsize]),
[wd6]"r"(&dptr[z][d + 6 * nsize]),
[wd7]"r"(&dptr[z][d + 7 * nsize]),
[x1d]"r"(0x1d)
);
}
@@ -1191,22 +1202,22 @@ static void raid6_rvv8_xor_syndrome_real(int disks, int start, int stop,
"vse8.v v31, (%[wq7])\n"
".option pop\n"
: :
[wp0]"r"(&p[d + NSIZE * 0]),
[wq0]"r"(&q[d + NSIZE * 0]),
[wp1]"r"(&p[d + NSIZE * 1]),
[wq1]"r"(&q[d + NSIZE * 1]),
[wp2]"r"(&p[d + NSIZE * 2]),
[wq2]"r"(&q[d + NSIZE * 2]),
[wp3]"r"(&p[d + NSIZE * 3]),
[wq3]"r"(&q[d + NSIZE * 3]),
[wp4]"r"(&p[d + NSIZE * 4]),
[wq4]"r"(&q[d + NSIZE * 4]),
[wp5]"r"(&p[d + NSIZE * 5]),
[wq5]"r"(&q[d + NSIZE * 5]),
[wp6]"r"(&p[d + NSIZE * 6]),
[wq6]"r"(&q[d + NSIZE * 6]),
[wp7]"r"(&p[d + NSIZE * 7]),
[wq7]"r"(&q[d + NSIZE * 7])
[wp0]"r"(&p[d + nsize * 0]),
[wq0]"r"(&q[d + nsize * 0]),
[wp1]"r"(&p[d + nsize * 1]),
[wq1]"r"(&q[d + nsize * 1]),
[wp2]"r"(&p[d + nsize * 2]),
[wq2]"r"(&q[d + nsize * 2]),
[wp3]"r"(&p[d + nsize * 3]),
[wq3]"r"(&q[d + nsize * 3]),
[wp4]"r"(&p[d + nsize * 4]),
[wq4]"r"(&q[d + nsize * 4]),
[wp5]"r"(&p[d + nsize * 5]),
[wq5]"r"(&q[d + nsize * 5]),
[wp6]"r"(&p[d + nsize * 6]),
[wq6]"r"(&q[d + nsize * 6]),
[wp7]"r"(&p[d + nsize * 7]),
[wq7]"r"(&q[d + nsize * 7])
);
}
}

17
lib/raid6/rvv.h
View File

@@ -7,6 +7,23 @@
* Definitions for RISC-V RAID-6 code
*/
#ifdef __KERNEL__
#include <asm/vector.h>
#else
#define kernel_vector_begin()
#define kernel_vector_end()
#include <sys/auxv.h>
#include <asm/hwcap.h>
#define has_vector() (getauxval(AT_HWCAP) & COMPAT_HWCAP_ISA_V)
#endif
#include <linux/raid/pq.h>
static int rvv_has_vector(void)
{
return has_vector();
}
#define RAID6_RVV_WRAPPER(_n) \
static void raid6_rvv ## _n ## _gen_syndrome(int disks, \
size_t bytes, void **ptrs) \

8
lib/raid6/test/Makefile
View File

@@ -35,6 +35,11 @@ ifeq ($(ARCH),aarch64)
HAS_NEON = yes
endif
ifeq ($(findstring riscv,$(ARCH)),riscv)
CFLAGS += -I../../../arch/riscv/include -DCONFIG_RISCV=1
HAS_RVV = yes
endif
ifeq ($(findstring ppc,$(ARCH)),ppc)
CFLAGS += -I../../../arch/powerpc/include
HAS_ALTIVEC := $(shell printf '$(pound)include <altivec.h>\nvector int a;\n' |\
@@ -63,6 +68,9 @@ else ifeq ($(HAS_ALTIVEC),yes)
vpermxor1.o vpermxor2.o vpermxor4.o vpermxor8.o
else ifeq ($(ARCH),loongarch64)
OBJS += loongarch_simd.o recov_loongarch_simd.o
else ifeq ($(HAS_RVV),yes)
OBJS += rvv.o recov_rvv.o
CFLAGS += -DCONFIG_RISCV_ISA_V=1
endif
.c.o: