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platform/x86/amd/pmc: Add PMC driver support for AMD 1Ah M80H SoC
The 1Ah M80H SoC uses a different set of SMU mailbox register offsets compared to the existing 1Ah variants: message at 0xA10, argument at 0xA18, and response at 0xA14. Add amd_1ah_m80_cpu_info with these offsets, wire it into the PCI ID table via PCI_DEVICE_DATA(), populate scratch_reg field with AMD_PMC_SCRATCH_REG_1AH and add the corresponding ACPI ID AMDI000C. Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com> Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Link: https://patch.msgid.link/20260609143952.2999707-3-Shyam-sundar.S-k@amd.com Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
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committed by
Ilpo Järvinen
parent
c3a2521bcc
commit
043af31c8d
@@ -154,6 +154,16 @@ static const struct amd_pmc_cpu_info amd_1ah_m70_cpu_info = {
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.os_hint = MSG_OS_HINT_RN,
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};
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static const struct amd_pmc_cpu_info amd_1ah_m80_cpu_info = {
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.smu_msg = AMD_PMC_REGISTER_MSG_1AH_80H,
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.smu_arg = AMD_PMC_REGISTER_ARG_1AH_80H,
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.smu_rsp = AMD_PMC_REGISTER_RSP_1AH_80H,
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.num_ips = ARRAY_SIZE(soc15_ip_blk),
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.scratch_reg = AMD_PMC_SCRATCH_REG_1AH,
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.ips_ptr = soc15_ip_blk,
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.os_hint = MSG_OS_HINT_RN,
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};
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static const struct pci_device_id pmc_pci_ids[] = {
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{ PCI_DEVICE_DATA(AMD, CPU_ID_PCO, &amd_pco_cpu_info) },
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{ PCI_DEVICE_DATA(AMD, CPU_ID_CZN, &amd_czn_cpu_info) },
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@@ -165,6 +175,7 @@ static const struct pci_device_id pmc_pci_ids[] = {
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{ PCI_DEVICE_DATA(AMD, CPU_ID_SHP, NULL) },
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{ PCI_DEVICE_DATA(AMD, 1AH_M20H_ROOT, NULL) },
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{ PCI_DEVICE_DATA(AMD, 1AH_M60H_ROOT, NULL) },
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{ PCI_DEVICE_DATA(AMD, 1AH_M80H_ROOT, &amd_1ah_m80_cpu_info) },
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{ }
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};
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@@ -860,6 +871,7 @@ static const struct acpi_device_id amd_pmc_acpi_ids[] = {
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{"AMDI0009", 0},
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{"AMDI000A", 0},
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{"AMDI000B", 0},
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{"AMDI000C", 0},
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{"AMD0004", 0},
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{"AMD0005", 0},
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{ }
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@@ -22,6 +22,11 @@
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/* SMU communication registers for 1Ah 20h SoC */
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#define AMD_PMC_REGISTER_MSG_1AH_20H 0x938
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/* SMU communication registers for 1Ah 80h SoC */
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#define AMD_PMC_REGISTER_MSG_1AH_80H 0xA10
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#define AMD_PMC_REGISTER_ARG_1AH_80H 0xA18
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#define AMD_PMC_REGISTER_RSP_1AH_80H 0xA14
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/* PMC Scratch Registers */
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#define AMD_PMC_SCRATCH_REG_CZN 0x94
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#define AMD_PMC_SCRATCH_REG_YC 0xD14
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@@ -186,6 +191,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
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#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
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#define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122
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#define PCI_DEVICE_ID_AMD_1AH_M80H_ROOT 0x115b
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#define PCI_DEVICE_ID_AMD_MP2_STB 0x172c
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int amd_stb_s2d_init(struct amd_pmc_dev *dev);
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