From 4fbf92d51cbc8c5d2d4ea1fcfad4cd8365047f4d Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Tue, 21 May 2024 10:01:31 +0200 Subject: [PATCH 01/31] arm64: dts: st: OP-TEE async notif on PPI 15 for stm32mp25 Define GIC PPI 15 (aka GIC interrupt line 31) for OP-TEE asynchronous notification. Signed-off-by: Etienne Carriere Signed-off-by: Pascal Paillet Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 4 +++- arch/arm64/boot/dts/st/stm32mp253.dtsi | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index dcd0656d67a8..22a5379ea1c9 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -51,9 +51,11 @@ clk_rcbsec: clk-rcbsec { }; firmware { - optee { + optee: optee { compatible = "linaro,optee-tz"; method = "smc"; + interrupt-parent = <&intc>; + interrupts = ; }; scmi { diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi index 029f88981961..69001f924d17 100644 --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -28,3 +28,7 @@ timer { ; }; }; + +&optee { + interrupts = ; +}; From 6e043ff6350267bb39de01499a8ad0035c729393 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Wed, 29 May 2024 15:13:10 +0200 Subject: [PATCH 02/31] arm64: dts: st: enable STM32 access controller for RCC Use an STM32 access controller to filter the registration of clocks. Signed-off-by: Gabriel Fernandez Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 22a5379ea1c9..7454e615350c 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -443,6 +443,7 @@ rcc: clock-controller@44200000 { <&scmi_clk CK_SCMI_TIMG2>, <&scmi_clk CK_SCMI_PLL3>, <&clk_dsi_txbyte>; + access-controllers = <&rifsc 156>; }; exti1: interrupt-controller@44220000 { From c3aa0dccf0ccbdd2c2ad556382bbae95344e4992 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Mon, 20 May 2024 16:00:22 +0200 Subject: [PATCH 03/31] arm64: dts: st: add usart nodes on stm32mp25 Update device-tree stm32mp251.dtsi to add some USART features. Add u(s)art 1, 3, 4, 5, 6, 7, 8, 9 nodes and compatible, interrupts, clocks, access-controllers properties. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 72 ++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 7454e615350c..2013f391f4b9 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -150,6 +150,33 @@ usart2: serial@400e0000 { status = "disabled"; }; + usart3: serial@400f0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400f0000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_USART3>; + access-controllers = <&rifsc 33>; + status = "disabled"; + }; + + uart4: serial@40100000 { + compatible = "st,stm32h7-uart"; + reg = <0x40100000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART4>; + access-controllers = <&rifsc 34>; + status = "disabled"; + }; + + uart5: serial@40110000 { + compatible = "st,stm32h7-uart"; + reg = <0x40110000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART5>; + access-controllers = <&rifsc 35>; + status = "disabled"; + }; + i2c1: i2c@40120000 { compatible = "st,stm32mp25-i2c"; reg = <0x40120000 0x400>; @@ -241,6 +268,15 @@ i2c7: i2c@40180000 { status = "disabled"; }; + usart6: serial@40220000 { + compatible = "st,stm32h7-uart"; + reg = <0x40220000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_USART6>; + access-controllers = <&rifsc 36>; + status = "disabled"; + }; + spi1: spi@40230000 { #address-cells = <1>; #size-cells = <0>; @@ -277,6 +313,24 @@ spi5: spi@40280000 { status = "disabled"; }; + uart9: serial@402c0000 { + compatible = "st,stm32h7-uart"; + reg = <0x402c0000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART9>; + access-controllers = <&rifsc 39>; + status = "disabled"; + }; + + usart1: serial@40330000 { + compatible = "st,stm32h7-uart"; + reg = <0x40330000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_USART1>; + access-controllers = <&rifsc 31>; + status = "disabled"; + }; + spi6: spi@40350000 { #address-cells = <1>; #size-cells = <0>; @@ -301,6 +355,24 @@ spi7: spi@40360000 { status = "disabled"; }; + uart7: serial@40370000 { + compatible = "st,stm32h7-uart"; + reg = <0x40370000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART7>; + access-controllers = <&rifsc 37>; + status = "disabled"; + }; + + uart8: serial@40380000 { + compatible = "st,stm32h7-uart"; + reg = <0x40380000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART8>; + access-controllers = <&rifsc 38>; + status = "disabled"; + }; + spi8: spi@46020000 { #address-cells = <1>; #size-cells = <0>; From 066cfdcd75a6844c6a09751637261c9f1d5baad7 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Mon, 20 May 2024 16:00:23 +0200 Subject: [PATCH 04/31] arm64: dts: st: add usart6 pinctrl used on stm32mp257f-ev1 board Add pins for USART6 on GPIO connector on stm32mp257f-ev1 board. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 7a82896dcbf6..4e677e64c406 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -128,6 +128,47 @@ pins { ; /* USART2_RX */ }; }; + + usart6_pins_a: usart6-0 { + pins1 { + pinmux = , /* USART6_TX */ + ; /* USART6_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART6_RX */ + ; /* USART6_CTS_NSS */ + bias-pull-up; + }; + }; + + usart6_idle_pins_a: usart6-idle-0 { + pins1 { + pinmux = , /* USART6_TX */ + ; /* USART6_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART6_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART6_RX */ + bias-pull-up; + }; + }; + + usart6_sleep_pins_a: usart6-sleep-0 { + pins { + pinmux = , /* USART6_TX */ + , /* USART6_RTS */ + , /* USART6_CTS_NSS */ + ; /* USART6_RX */ + }; + }; }; &pinctrl_z { From 624aa659afbc902cd279ae719a2f58a22dca88c0 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Mon, 20 May 2024 16:00:24 +0200 Subject: [PATCH 05/31] arm64: dts: st: add usart6 on stm32mp257f-ev1 board Add node for USART6 on stm32mp257f-ev1 board. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 27b7360e5dba..18c6266532b2 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -18,6 +18,7 @@ / { aliases { serial0 = &usart2; + serial1 = &usart6; }; chosen { @@ -109,3 +110,12 @@ &usart2 { pinctrl-2 = <&usart2_sleep_pins_a>; status = "okay"; }; + +&usart6 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart6_pins_a>; + pinctrl-1 = <&usart6_idle_pins_a>; + pinctrl-2 = <&usart6_sleep_pins_a>; + uart-has-rtscts; + status = "disabled"; +}; From 9c8d852dabbd49f4894d5d998ede8b98eb091921 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 25 Apr 2024 17:45:55 +0200 Subject: [PATCH 06/31] arm64: dts: st: add power domain on stm32mp25 Add power domains on STM32MP25x SoC for supported low power modes: - CPU_PD0/1: domain for idle of each core Cortex A35 (CStop) - CLUSTER_PD: D1 domain with Stop1 and LP-Stop1 modes support when the Cortex A35 cluster and each device assigned to CPU1=CA35 are deactivated - RET_PD: D1 domain retention (VDDCore is reduced) to support the LPLV-Stop1 mode Signed-off-by: Patrick Delaunay Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/st/stm32mp253.dtsi | 9 +++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 2013f391f4b9..96d6de29c14c 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -20,6 +20,8 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0>; enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; }; }; @@ -90,6 +92,20 @@ intc: interrupt-controller@4ac00000 { psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + power-domains = <&RET_PD>; + }; + + RET_PD: power-domain-retention { + #power-domain-cells = <0>; + }; }; timer { diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi index 69001f924d17..652e41facb35 100644 --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -12,6 +12,8 @@ cpu1: cpu@1 { device_type = "cpu"; reg = <1>; enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; }; }; @@ -21,6 +23,13 @@ arm-pmu { interrupt-affinity = <&cpu0>, <&cpu1>; }; + psci { + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + }; + timer { interrupts = , , From 0948424cd5e77c1f16ec64837dc1d51f71db7dd5 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 26 Apr 2024 17:05:24 +0200 Subject: [PATCH 07/31] ARM: dts: stm32: add DCMIPP pinctrl on STM32MP13x SoC family Adds DCMIPP pinctrl support and assigns dedicated GPIO pins. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 33 +++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index 32c5d8a1e06a..b423d182aefd 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -13,6 +13,39 @@ pins { }; }; + dcmipp_pins_a: dcmi-0 { + pins1 { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ;/* DCMI_D7 */ + bias-disable; + }; + }; + + dcmipp_sleep_pins_a: dcmi-sleep-0 { + pins1 { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ;/* DCMI_D7 */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ From 26c7b370eba6127431c82d1cbf5081f6b5674db6 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 26 Apr 2024 17:05:25 +0200 Subject: [PATCH 08/31] ARM: dts: stm32: enable camera support on stm32mp135f-dk board On STM32MP135F-DK board the camera support is made of the CSI based GC2145 sensor, connected to the ST-MIPID02 CSI to parallel bridge, connected to the DCMIPP parallel input. Signed-off-by: Alain Volmat Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 87 +++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 567e53ad285f..e43bb9b74b87 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -29,6 +29,20 @@ chosen { stdout-path = "serial0:115200n8"; }; + clocks { + clk_ext_camera: clk-ext-camera { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_mco1: clk-mco1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + memory@c0000000 { device_type = "memory"; reg = <0xc0000000 0x20000000>; @@ -141,6 +155,23 @@ &cryp { status = "okay"; }; +&dcmipp { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcmipp_pins_a>; + pinctrl-1 = <&dcmipp_sleep_pins_a>; + status = "okay"; + + port { + dcmipp_0: endpoint { + remote-endpoint = <&mipid02_2>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; + }; + }; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; @@ -201,6 +232,62 @@ &i2c5 { /* spare dmas for other usage */ /delete-property/dmas; /delete-property/dma-names; + + stmipi: csi2rx@14 { + compatible = "st,st-mipid02"; + reg = <0x14>; + clocks = <&clk_mco1>; + clock-names = "xclk"; + VDDE-supply = <&scmi_v1v8_periph>; + VDDIN-supply = <&scmi_v1v8_periph>; + reset-gpios = <&mcp23017 2 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + mipid02_0: endpoint { + data-lanes = <1 2>; + lane-polarities = <0 0 0>; + remote-endpoint = <&gc2145_ep>; + }; + }; + port@2 { + reg = <2>; + + mipid02_2: endpoint { + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; + remote-endpoint = <&dcmipp_0>; + }; + }; + }; + }; + + gc2145: camera@3c { + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + clocks = <&clk_ext_camera>; + iovdd-supply = <&scmi_v3v3_sw>; + avdd-supply = <&scmi_v3v3_sw>; + dvdd-supply = <&scmi_v3v3_sw>; + powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; + reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; + status = "okay"; + + port { + gc2145_ep: endpoint { + remote-endpoint = <&mipid02_0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <120000000 192000000 240000000>; + }; + }; + }; }; &iwdg2 { From 3d058df954ebdb592fd421e0005f6d0c25da21ed Mon Sep 17 00:00:00 2001 From: Yannick Fertre Date: Mon, 6 May 2024 16:49:45 +0200 Subject: [PATCH 09/31] ARM: dts: stm32: add goodix touchscreen on stm32mp135f-dk Touchscreen reset needs to be configured via the pinctrl not the driver (a pull-down resistor has been soldered onto the reset line which forces the touchscreen to reset state). Interrupt line must have a pull-down resistor in order to freeze the i2c address at 0x5D. Signed-off-by: Yannick Fertre Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 22 +++++++++++++++++++++ arch/arm/boot/dts/st/stm32mp135f-dk.dts | 14 +++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index b423d182aefd..66efef93251f 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -46,6 +46,28 @@ pins1 { }; }; + goodix_pins_a: goodix-0 { + /* + * touchscreen reset needs to be configured + * via the pinctrl not the driver (a pull-down resistor + * has been soldered onto the reset line which forces + * the touchscreen to reset state). + */ + pins1 { + pinmux = ; + output-high; + bias-pull-up; + }; + /* + * Interrupt line must have a pull-down resistor + * in order to freeze the i2c address at 0x5D + */ + pins2 { + pinmux = ; + bias-pull-down; + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index e43bb9b74b87..970de441fbaa 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -288,6 +288,20 @@ gc2145_ep: endpoint { }; }; }; + + goodix: goodix-ts@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&goodix_pins_a>; + interrupt-parent = <&gpiof>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + AVDD28-supply = <&scmi_v3v3_sw>; + VDDIO-supply = <&scmi_v3v3_sw>; + touchscreen-size-x = <480>; + touchscreen-size-y = <272>; + status = "okay" ; + }; }; &iwdg2 { From 4306c047415a227bc72f0e7ba9bde1ccdac10435 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 13 May 2024 23:58:15 +0200 Subject: [PATCH 10/31] ARM: dts: stm32: Add arm,no-tick-in-suspend to STM32MP15xx STGEN timer STM32MP15xx RM0436 Rev 6 section 46.3 System timer generator (STGEN) states " Arm recommends that the system counter is in an always-on power domain. This is not supported in the current implementation, therefore STGEN should be saved and restored before Standby mode entry, and restored at Standby exit by secure software. ... " Instead of piling up workarounds in the firmware which is difficult to update, add "arm,no-tick-in-suspend" DT property into the timer node to indicate the timer is stopped in suspend, and let the kernel fix the timer up. Fixes: 8471a20253eb ("ARM: dts: stm32: add stm32mp157c initial support") Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp151.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index 90c5c72c87ab..4f878ec102c1 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -50,6 +50,7 @@ timer { , ; interrupt-parent = <&intc>; + arm,no-tick-in-suspend; }; clocks { From 7010a17fb12a0febd6002d5bae8c4bf14039ae8c Mon Sep 17 00:00:00 2001 From: Sean Nyekjaer Date: Wed, 22 May 2024 10:23:29 +0200 Subject: [PATCH 11/31] ARM: dts: stm32: osd32: move usb phy power to common According to the OSD32MP1 Power System overview[1] usb phy power is hard-wired internally in the SIP module to ldo4. [1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections Signed-off-by: Sean Nyekjaer Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts | 8 -------- arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi | 8 -------- arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi | 8 ++++++++ 3 files changed, 8 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts index 527c33be66cc..854dfecd801f 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts @@ -211,11 +211,3 @@ &usbotg_hs { &usbphyc { status = "okay"; }; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi index cfaf8adde319..aa28043c30fb 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi @@ -590,14 +590,6 @@ &usbphyc { status = "okay"; }; -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; - &vrefbuf { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi index aeb71c41a734..ae01e7a5339e 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi @@ -214,3 +214,11 @@ &m4_rproc { &rng1 { status = "okay"; }; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; From f37c8d3ba5262dc4aee83c58958817c8360f1455 Mon Sep 17 00:00:00 2001 From: Sean Nyekjaer Date: Wed, 22 May 2024 10:23:30 +0200 Subject: [PATCH 12/31] ARM: dts: stm32: osd32: move pwr_regulators to common According to the OSD32MP1 Power System overview[1] pwr_regulators; vdd-supply and vdd_3v3_usbfs-supply are hard-wired internally in the SIP module to vdd and ldo4. [1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections Signed-off-by: Sean Nyekjaer Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts | 5 ----- arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi | 5 ----- arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi | 5 +++++ 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts index 854dfecd801f..36e6055b5665 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts @@ -147,11 +147,6 @@ &m_can1 { status = "okay"; }; -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - &rtc { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi index aa28043c30fb..c87fd96cbd91 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi @@ -379,11 +379,6 @@ regulators { }; }; -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - &rtc { status = "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi index ae01e7a5339e..2022a1fa31ca 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi @@ -215,6 +215,11 @@ &rng1 { status = "okay"; }; +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + &usbphyc_port0 { phy-supply = <&vdd_usb>; }; From f97e8c040e2c1130a8cc91861590510d5d40a878 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 28 Apr 2024 00:10:10 +0200 Subject: [PATCH 13/31] dt-bindings: arm: stm32: Add compatible string for DH electronics STM32MP13xx DHCOR DHSBC board Add DT compatible string for DH electronics STM32MP13xx DHCOR SoM and DHSBC carrier board. This stm32mp135f-dhcor-dhsbc board is a stack of DHCOR SoM based on STM32MP135F SoC (900MHz / crypto capabilities) populated on DHSBC carrier board. The SoM contains the following peripherals: - STPMIC (power delivery) - 512MB DDR3L memory - eMMC and SDIO WiFi module The DHSBC carrier board contains the following peripherals: - Two RGMII Ethernet ports - USB-A Host port, USB-C peripheral port, USB-C power supply plug - Expansion connector Signed-off-by: Marek Vasut Acked-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index bc2f43330ae4..58099949e8f3 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -59,6 +59,12 @@ properties: - prt,prtt1s # Protonic PRTT1S - const: st,stm32mp151 + - description: DH STM32MP135 DHCOR SoM based Boards + items: + - const: dh,stm32mp135f-dhcor-dhsbc + - const: dh,stm32mp135f-dhcor-som + - const: st,stm32mp135 + - description: DH STM32MP151 DHCOR SoM based Boards items: - const: dh,stm32mp151a-dhcor-testbench From 690c66656e99ebc962451afbc1f15d074646773a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 28 Apr 2024 00:10:11 +0200 Subject: [PATCH 14/31] ARM: dts: stm32: Add pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board Add new pinmux nodes for DH electronics STM32MP13xx DHCOR SoM and DHSBC board. The following pinmux nodes are added: - ADC pins - ADC CC pins - ETH1 pins - ETH2 pins - I2C5 pins - MCAN1 pins - MCAN2 pins - PWM13 pins - PWM5 pins - QSPI pins - SAI1 pins - SDMMC2 D4..D7 pins - SPI2 pins - SPI3 pins - UART4 pins - UART7 pins - USART1 pins - USART2 pins Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 483 ++++++++++++++++++++ 1 file changed, 483 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index 66efef93251f..22cd07196499 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -6,6 +6,12 @@ #include &pinctrl { + adc1_pins_a: adc1-pins-0 { + pins { + pinmux = ; /* ADC1 in12 */ + }; + }; + adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { pins { pinmux = , /* ADC1 in6 */ @@ -68,6 +74,104 @@ pins2 { }; }; + adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 { + pins { + pinmux = , /* ADC1_INP2 */ + ; /* ADC1_INP11 */ + }; + }; + + eth1_rgmii_pins_a: eth1-rgmii-0 { + pins1 { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CTL */ + ; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + + }; + + eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RX_CTL */ + ; /* ETH_RGMII_RX_CLK */ + }; + }; + + eth2_rgmii_pins_a: eth2-rgmii-0 { + pins1 { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CTL */ + ; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CTL */ + ; /* ETH_RGMII_RX_CLK */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ @@ -102,6 +206,23 @@ pins { }; }; + i2c5_pins_b: i2c5-1 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_b: i2c5-sleep-1 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + }; + }; + ltdc_pins_a: ltdc-0 { pins { pinmux = , /* LCD_CLK */ @@ -159,6 +280,46 @@ pins { }; }; + m_can1_pins_a: m-can1-0 { + pins1 { + pinmux = ; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can1_sleep_pins_a: m_can1-sleep-0 { + pins { + pinmux = , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + + m_can2_pins_a: m-can2-0 { + pins1 { + pinmux = ; /* CAN2_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-disable; + }; + }; + + m_can2_sleep_pins_a: m_can2-sleep-0 { + pins { + pinmux = , /* CAN2_TX */ + ; /* CAN2_RX */ + }; + }; + mcp23017_pins_a: mcp23017-0 { pins { pinmux = ; @@ -196,6 +357,21 @@ pins { }; }; + pwm5_pins_a: pwm5-0 { + pins { + pinmux = ; /* TIM5_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm5_sleep_pins_a: pwm5-sleep-0 { + pins { + pinmux = ; /* TIM5_CH3 */ + }; + }; + pwm8_pins_a: pwm8-0 { pins { pinmux = ; /* TIM8_CH3 */ @@ -211,6 +387,21 @@ pins { }; }; + pwm13_pins_a: pwm13-0 { + pins { + pinmux = ; /* TIM13_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm13_sleep_pins_a: pwm13-sleep-0 { + pins { + pinmux = ; /* TIM13_CH1 */ + }; + }; + pwm14_pins_a: pwm14-0 { pins { pinmux = ; /* TIM14_CH1 */ @@ -226,6 +417,89 @@ pins { }; }; + qspi_clk_pins_a: qspi-clk-0 { + pins { + pinmux = ; /* QSPI_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { + pins { + pinmux = ; /* QSPI_CLK */ + }; + }; + + qspi_bk1_pins_a: qspi-bk1-0 { + pins { + pinmux = , /* QSPI_BK1_IO0 */ + , /* QSPI_BK1_IO1 */ + , /* QSPI_BK1_IO2 */ + ; /* QSPI_BK1_IO3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { + pins { + pinmux = , /* QSPI_BK1_IO0 */ + , /* QSPI_BK1_IO1 */ + , /* QSPI_BK1_IO2 */ + ; /* QSPI_BK1_IO3 */ + }; + }; + + qspi_cs1_pins_a: qspi-cs1-0 { + pins { + pinmux = ; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { + pins { + pinmux = ; /* QSPI_BK1_NCS */ + }; + }; + + sai1a_pins_a: sai1a-0 { + pins { + pinmux = , /* SAI1_SCK_A */ + , /* SAI1_SD_A */ + ; /* SAI1_FS_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai1a_sleep_pins_a: sai1a-sleep-0 { + pins { + pinmux = , /* SAI1_SCK_A */ + , /* SAI1_SD_A */ + ; /* SAI1_FS_A */ + }; + }; + + sai1b_pins_a: sai1b-0 { + pins { + pinmux = ; /* SAI1_SD_B */ + bias-disable; + }; + }; + + sai1b_sleep_pins_a: sai1b-sleep-0 { + pins { + pinmux = ; /* SAI1_SD_B */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = , /* SDMMC1_D0 */ @@ -328,6 +602,73 @@ pins { }; }; + sdmmc2_d47_pins_a: sdmmc2-d47-0 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + + spi2_pins_a: spi2-0 { + pins1 { + pinmux = , /* SPI2_SCK */ + ; /* SPI2_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI2_MISO */ + bias-disable; + }; + }; + + spi2_sleep_pins_a: spi2-sleep-0 { + pins { + pinmux = , /* SPI2_SCK */ + , /* SPI2_MISO */ + ; /* SPI2_MOSI */ + }; + }; + + spi3_pins_a: spi3-0 { + pins1 { + pinmux = , /* SPI3_SCK */ + ; /* SPI3_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI3_MISO */ + bias-disable; + }; + }; + + spi3_sleep_pins_a: spi3-sleep-0 { + pins { + pinmux = , /* SPI3_SCK */ + , /* SPI3_MISO */ + ; /* SPI3_MOSI */ + }; + }; + spi5_pins_a: spi5-0 { pins1 { pinmux = , /* SPI5_SCK */ @@ -388,6 +729,77 @@ pins { }; }; + uart4_pins_b: uart4-1 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-pull-up; + }; + }; + + uart4_idle_pins_b: uart4-idle-1 { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-pull-up; + }; + }; + + uart4_sleep_pins_b: uart4-sleep-1 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + + uart7_pins_a: uart7-0 { + pins1 { + pinmux = , /* UART7_TX */ + ; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* UART7_RX */ + ; /* UART7_CTS_NSS */ + bias-disable; + }; + }; + + uart7_idle_pins_a: uart7-idle-0 { + pins1 { + pinmux = , /* UART7_TX */ + ; /* UART7_CTS_NSS */ + }; + pins2 { + pinmux = ; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* UART7_RX */ + bias-disable; + }; + }; + + uart7_sleep_pins_a: uart7-sleep-0 { + pins { + pinmux = , /* UART7_TX */ + , /* UART7_RTS */ + , /* UART7_RX */ + ; /* UART7_CTS_NSS */ + }; + }; + uart8_pins_a: uart8-0 { pins1 { pinmux = ; /* UART8_TX */ @@ -459,6 +871,36 @@ pins { }; }; + usart1_pins_b: usart1-1 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-pull-up; + }; + }; + + usart1_idle_pins_b: usart1-idle-1 { + pins1 { + pinmux = ; /* USART1_TX */ + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-pull-up; + }; + }; + + usart1_sleep_pins_b: usart1-sleep-1 { + pins { + pinmux = , /* USART1_TX */ + ; /* USART1_RX */ + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = , /* USART2_TX */ @@ -499,4 +941,45 @@ pins { ; /* USART2_CTS_NSS */ }; }; + + usart2_pins_b: usart2-1 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_idle_pins_b: usart2-idle-1 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_b: usart2-sleep-1 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; }; From 6331bddce649829afb2c2e462df812f8e8657a61 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 28 Apr 2024 00:10:12 +0200 Subject: [PATCH 15/31] ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC board This stm32mp135f-dhcor-dhsbc board is a stack of DHCOR SoM based on STM32MP135F SoC (900MHz / crypto capabilities) populated on DHSBC carrier board. The SoM contains the following peripherals: - STPMIC (power delivery) - 512MB DDR3L memory - eMMC and SDIO WiFi module The DHSBC carrier board contains the following peripherals: - Two RGMII Ethernet ports - USB-A Host port, USB-C peripheral port, USB-C power supply plug - Expansion connector Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/Makefile | 1 + .../boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 321 ++++++++++++++++++ .../boot/dts/st/stm32mp13xx-dhcor-som.dtsi | 308 +++++++++++++++++ 3 files changed, 630 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts create mode 100644 arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index 9fedd6776208..015903d09323 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ stm32h750i-art-pi.dtb \ + stm32mp135f-dhcor-dhsbc.dtb \ stm32mp135f-dk.dtb \ stm32mp151a-prtt1a.dtb \ stm32mp151a-prtt1c.dtb \ diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts new file mode 100644 index 000000000000..5f4f6b6e427a --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2024 Marek Vasut + * + * DHCOR STM32MP13 variant: + * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG + * DHCOR PCB number: 718-100 or newer + * DHSBC PCB number: 719-100 or newer + */ + +/dts-v1/; + +#include +#include "stm32mp135.dtsi" +#include "stm32mp13xf.dtsi" +#include "stm32mp13xx-dhcor-som.dtsi" + +/ { + model = "DH electronics STM32MP135F DHCOR DHSBC"; + compatible = "dh,stm32mp135f-dhcor-dhsbc", + "dh,stm32mp135f-dhcor-som", + "st,stm32mp135"; + + aliases { + serial2 = &usart1; + serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&adc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_pins_a &adc1_usb_cc_pins_b>; + vdda-supply = <&vdd_adc>; + vref-supply = <&vdd_adc>; + status = "okay"; + + adc1: adc@0 { + status = "okay"; + + /* + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11. + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: + * 5 * (5.1 + 47kOhms) * 5pF => 1.3us. + * Use arbitrary margin here (e.g. 5us). + * + * The pinmux pins must be set as ANALOG, use datasheet + * DS13483 Table 7. STM32MP135C/F ball definitions to + * find out which 'pin name' maps to which 'additional + * functions', which lists the mapping between pin and + * ADC channel. In this case, PA5 maps to ADC1_INP2 and + * PF13 maps to ADC1_INP11 . + */ + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; + }; + + channel@11 { + reg = <11>; + st,min-sample-time-ns = <5000>; + }; + + /* Expansion connector: INP12:pin29 */ + channel@12 { + reg = <12>; + st,min-sample-time-ns = <5000>; + }; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", + "", "DHSBC_USB_PWR_CC1", "", "", + "", "", "", "DHSBC_nETH1_RST", + "", "DHCOR_HW-CODING_0", "", ""; +}; + +&gpiob { + gpio-line-names = "", "", "", "", + "", "", "", "DHCOR_BT_HOST_WAKE", + "", "", "", "", + "", "DHSBC_nTPM_CS", "", ""; +}; + +&gpioc { + gpio-line-names = "", "", "", "DHSBC_USB_5V_MEAS", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "DHCOR_RAM-CODING_0", "", "", + "", "DHCOR_RAM-CODING_1", "", "", + "", "", "", ""; +}; + +&gpioe { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "DHSBC_nTPM_RST", "", "", + "DHSBC_nTPM_PIRQ", "", "DHCOR_WL_HOST_WAKE", ""; +}; + +&gpiof { + gpio-line-names = "", "", "DHSBC_USB_PWR_nFLT", "", + "", "", "", "", + "", "", "", "", + "DHCOR_WL_REG_ON", "DHSBC_USB_PWR_CC2", "", ""; +}; + +&gpiog { + gpio-line-names = "", "", "", "", + "", "", "", "", + "DHSBC_nETH2_RST", "DHCOR_BT_DEV_WAKE", "", "", + "DHSBC_ETH1_INTB", "", "", "DHSBC_ETH2_INTB"; +}; + +&gpioi { + gpio-line-names = "DHCOR_RTC_nINT", "DHCOR_HW-CODING_1", + "DHCOR_BT_REG_ON", "DHCOR_PMIC_nINT", + "DHSBC_BOOT0", "DHSBC_BOOT1", + "DHSBC_BOOT2", "DHSBC_USB-C_DATA_VBUS"; +}; + +&i2c1 { /* Expansion connector: SDA:pin27 SCL:pin28 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c5 { /* Expansion connector: SDA:pin3 SCL:pin5 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_b>; + pinctrl-1 = <&i2c5_sleep_pins_b>; + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&m_can1 { /* Expansion connector: TX:pin16 RX:pin18 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; + status = "okay"; +}; + +&m_can2 { /* Expansion connector: TX:pin22 RX:pin26 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; + status = "okay"; +}; + +&sai1 { /* Expansion connector: SCK-A:pin12 FS-A:pin35 SD-A:pin38 SD-B:pin40 */ + clocks = <&rcc SAI1>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai1a_pins_a &sai1b_pins_a>; + pinctrl-1 = <&sai1a_sleep_pins_a &sai1b_sleep_pins_a>; +}; + +&scmi_voltd { + status = "disabled"; +}; + +&spi2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi2_pins_a>; + pinctrl-1 = <&spi2_sleep_pins_a>; + cs-gpios = <&gpiob 13 0>; + status = "okay"; + + st33htph: tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <24000000>; + }; +}; + +&spi3 { /* Expansion connector: MOSI:pin19 MISO:pin21 SCK:pin22 nCS:pin24 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi3_pins_a>; + pinctrl-1 = <&spi3_sleep_pins_a>; + cs-gpios = <&gpiof 3 0>; + status = "disabled"; +}; + +&timers5 { /* Expansion connector: CH3:pin31 */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@4 { + status = "okay"; + }; +}; + +&timers13 { /* Expansion connector: CH1:pin32 */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + pwm { + pinctrl-0 = <&pwm13_pins_a>; + pinctrl-1 = <&pwm13_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@12 { + status = "okay"; + }; +}; + +&usart1 { /* Expansion connector: RX:pin33 TX:pin37 */ + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_b>; + pinctrl-1 = <&usart1_sleep_pins_b>; + pinctrl-2 = <&usart1_idle_pins_b>; + status = "okay"; +}; + +&usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */ + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_b>; + pinctrl-1 = <&usart2_sleep_pins_b>; + pinctrl-2 = <&usart2_idle_pins_b>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + usb33d-supply = <&usb33>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; + connector { + compatible = "usb-a-connector"; + vbus-supply = <&vbus_sw>; + }; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + vbus-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>; + label = "Type-C"; + self-powered; + type = "micro"; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi new file mode 100644 index 000000000000..ddad6497775b --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2024 Marek Vasut + */ + +#include +#include +#include +#include +#include +#include "stm32mp13-pinctrl.dtsi" + +/ { + model = "DH electronics STM32MP13xx DHCOR SoM"; + compatible = "dh,stm32mp131a-dhcor-som", + "st,stm32mp131"; + + aliases { + mmc0 = &sdmmc2; + mmc1 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + rtc0 = &rv3032; + spi0 = &qspi; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@dd000000 { + reg = <0xdd000000 0x3000000>; + no-map; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>; + }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioi 3 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&vin>; + ldo2-supply = <&vin>; + ldo3-supply = <&vin>; + ldo4-supply = <&vin>; + ldo5-supply = <&vin>; + ldo6-supply = <&vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcpu: buck1 { /* VDD_CPU_1V2 */ + regulator-name = "vddcpu"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { /* VDD_DDR_1V35 */ + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { /* VDD_3V3_1V8 */ + regulator-name = "vdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vddcore: buck4 { /* VDD_CORE_1V2 */ + regulator-name = "vddcore"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_adc: ldo1 { /* VDD_ADC_1V8 */ + regulator-name = "vdd_adc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + }; + + vdd_ldo2: ldo2 { /* LDO2_OUT_1V8 */ + regulator-name = "vdd_ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + }; + + vdd_ldo3: ldo3 { /* LDO3_OUT */ + regulator-name = "vdd_ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + }; + + vdd_usb: ldo4 { /* VDD_USB_3V3 */ + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdd_sd: ldo5 { /* VDD_SD_3V3_1V8 */ + regulator-name = "vdd_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdd_sd2: ldo6 { /* VDD_SD2_3V3_1V8 */ + regulator-name = "vdd_sd2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vref_ddr: vref_ddr { /* VREF_DDR_0V675 */ + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { /* BST_OUT_5V2 */ + regulator-name = "bst_out"; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + eeprom0: eeprom@50 { + compatible = "atmel,24c256"; /* ST M24256 */ + reg = <0x50>; + pagesize = <64>; + }; + + rv3032: rtc@51 { + compatible = "microcrystal,rv3032"; + reg = <0x51>; + interrupts-extended = <&gpioi 0 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +/* Console UART */ +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_b>; + pinctrl-1 = <&uart4_sleep_pins_b>; + pinctrl-2 = <&uart4_idle_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +/* Bluetooth */ +&uart7 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart7_pins_a>; + pinctrl-1 = <&uart7_sleep_pins_a>; + pinctrl-2 = <&uart7_idle_pins_a>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + max-speed = <3000000>; + device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; + }; +}; + +/* SDIO WiFi */ +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + non-removable; + st,neg-edge; + vmmc-supply = <&vdd>; + mmc-pwrseq = <&sdio_pwrseq>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { /* muRata 1YN */ + reg = <1>; + compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac"; + interrupt-parent = <&gpioe>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +/* eMMC */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + bus-width = <8>; + mmc-ddr-3_3v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&vdd>; + vqmmc-supply = <&vdd>; + status = "okay"; +}; From 0fc78aa67b3f9a7cc6b67ddbc511e4a5022cfd01 Mon Sep 17 00:00:00 2001 From: Yanjun Yang Date: Fri, 14 Jun 2024 09:00:12 +0800 Subject: [PATCH 16/31] ARM: dts: stm32: Missing clocks for stm32f429's syscfg. Without clock definition, SYSCFG will not work, EXTI interrupt for port other than GPIOA will fail to operate. Signed-off-by: Yanjun Yang Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32f429.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/st/stm32f429.dtsi b/arch/arm/boot/dts/st/stm32f429.dtsi index 8efcda9ef8ae..ad91b74ddd0d 100644 --- a/arch/arm/boot/dts/st/stm32f429.dtsi +++ b/arch/arm/boot/dts/st/stm32f429.dtsi @@ -579,6 +579,7 @@ spi4: spi@40013400 { syscfg: syscon@40013800 { compatible = "st,stm32-syscfg", "syscon"; reg = <0x40013800 0x400>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SYSCFG)>; }; exti: interrupt-controller@40013c00 { From 3333d21af6fade5215bf0803fd8ef3c4c9d46fd4 Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Mon, 17 Jun 2024 11:14:18 +0200 Subject: [PATCH 17/31] ARM: dts: stm32: OP-TEE async notif interrupt for ST STM32MP15x boards Define the GIC interrupt (PPI 15) to be used on ST STM32MP15x boards for OP-TEE async notif. Signed-off-by: Etienne Carriere Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 5 +++++ arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 5 +++++ arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 5 +++++ arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 5 +++++ 4 files changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts index 306e1bc2a514..847b360f02fc 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts @@ -62,6 +62,11 @@ &m4_rproc { reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = ; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts index 956da5f26c1c..43280289759d 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts @@ -68,6 +68,11 @@ &m4_rproc { reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = ; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts index 8e4b0db198c2..6f27d794d270 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts @@ -67,6 +67,11 @@ &m4_rproc { reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = ; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts index 72b9cab2d990..6ae391bffee5 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts @@ -72,6 +72,11 @@ &m4_rproc { reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = ; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi"; From 710d4f79bd430aec8c2b1edbd54b4370ac0b5f1b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 13 Jun 2024 10:02:28 +0200 Subject: [PATCH 18/31] ARM: dts: stm32: Document output pins for PWMs on stm32mp135f-dk MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To simplify identifying the pins where the PWM output is routed to, add a comment to each PWM device about the respective pin on the expansion connector. Signed-off-by: Uwe Kleine-König Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 970de441fbaa..faccdda588e5 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -374,6 +374,7 @@ &timers3 { /delete-property/dma-names; status = "disabled"; pwm { + /* PWM output on pin 7 of the expansion connector (CN8.7) using TIM3_CH4 func */ pinctrl-0 = <&pwm3_pins_a>; pinctrl-1 = <&pwm3_sleep_pins_a>; pinctrl-names = "default", "sleep"; @@ -389,6 +390,7 @@ &timers4 { /delete-property/dma-names; status = "disabled"; pwm { + /* PWM output on pin 31 of the expansion connector (CN8.31) using TIM4_CH2 func */ pinctrl-0 = <&pwm4_pins_a>; pinctrl-1 = <&pwm4_sleep_pins_a>; pinctrl-names = "default", "sleep"; @@ -404,6 +406,7 @@ &timers8 { /delete-property/dma-names; status = "disabled"; pwm { + /* PWM output on pin 32 of the expansion connector (CN8.32) using TIM8_CH3 func */ pinctrl-0 = <&pwm8_pins_a>; pinctrl-1 = <&pwm8_sleep_pins_a>; pinctrl-names = "default", "sleep"; @@ -417,6 +420,7 @@ timer@7 { &timers14 { status = "disabled"; pwm { + /* PWM output on pin 33 of the expansion connector (CN8.33) using TIM14_CH1 func */ pinctrl-0 = <&pwm14_pins_a>; pinctrl-1 = <&pwm14_sleep_pins_a>; pinctrl-names = "default", "sleep"; From 0872f840edc9a163a9be46760f81631a8c7efa0f Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Mon, 10 Jun 2024 10:03:07 +0200 Subject: [PATCH 19/31] ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13 Both instances ethernet based on GMAC SNPS IP on stm32mp13. GMAC IP version is SNPS 4.20. Signed-off-by: Christophe Roullier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp131.dtsi | 38 ++++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32mp133.dtsi | 31 +++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 6704ceef284d..e1a764d269d2 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -979,6 +979,12 @@ ts_cal1: calib@5c { ts_cal2: calib@5e { reg = <0x5e 0x2>; }; + ethernet_mac1_address: mac1@e4 { + reg = <0xe4 0x6>; + }; + ethernet_mac2_address: mac2@ea { + reg = <0xea 0x6>; + }; }; etzpc: bus@5c007000 { @@ -1505,6 +1511,38 @@ sdmmc2: mmc@58007000 { status = "disabled"; }; + ethernet1: ethernet@5800a000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <&exti 68 1>; + interrupt-names = "macirq", "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH1MAC>, + <&rcc ETH1TX>, + <&rcc ETH1RX>, + <&rcc ETH1STP>, + <&rcc ETH1CK_K>; + st,syscon = <&syscfg 0x4 0xff0000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,tso; + access-controllers = <&etzpc 48>; + status = "disabled"; + + stmmac_axi_config_1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; + usbphyc: usbphyc@5a006000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index 3e394c8e58b9..73e470019ce4 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -68,4 +68,35 @@ channel@18 { }; }; }; + + ethernet2: ethernet@5800e000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800e000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH2MAC>, + <&rcc ETH2TX>, + <&rcc ETH2RX>, + <&rcc ETH2STP>, + <&rcc ETH2CK_K>; + st,syscon = <&syscfg 0x4 0xff000000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_2>; + snps,tso; + access-controllers = <&etzpc 49>; + status = "disabled"; + + stmmac_axi_config_2: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; }; From fbbfbdfe03522c72f22cb79b7bd920b99bc7c674 Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Mon, 10 Jun 2024 10:03:08 +0200 Subject: [PATCH 20/31] ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board Those pins are used for Ethernet 1 and 2 on STM32MP13F-DK board. ethernet1: RMII with crystal. ethernet2: RMII without crystal. Add analog gpio pin configuration ("sleep") to manage power mode on stm32mp13. Signed-off-by: Christophe Roullier Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 71 +++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index 22cd07196499..fc56be60cfcd 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -172,6 +172,77 @@ pins1 { }; }; + eth1_rmii_pins_a: eth1-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + + }; + + eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + + eth2_rmii_pins_a: eth2-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_ETHCK */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + }; + + eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_ETHCK */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ From e9442f1fa4d2545dd6c0aaf7cb7a125cb04f8f2f Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Mon, 10 Jun 2024 10:03:09 +0200 Subject: [PATCH 21/31] ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board Ethernet1: RMII with crystal Ethernet2: RMII with no cristal, need "phy-supply" property to work, today this property was managed by Ethernet glue, but should be present and managed in PHY node. So I will push second Ethernet in next step. PHYs used are SMSC (LAN8742A) Signed-off-by: Christophe Roullier Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index faccdda588e5..1af335a39993 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -19,6 +19,7 @@ / { compatible = "st,stm32mp135f-dk", "st,stm32mp135"; aliases { + ethernet0 = ðernet1; serial0 = &uart4; serial1 = &usart1; serial2 = &uart8; @@ -172,6 +173,28 @@ dcmipp_0: endpoint { }; }; +ðernet1 { + status = "okay"; + pinctrl-0 = <ð1_rmii_pins_a>; + pinctrl-1 = <ð1_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + phy-handle = <&phy0_eth1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0_eth1: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c131"; + reg = <0>; + reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; From bf016e1db918ae5574b1f0e6d1fe844f9f125498 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 27 Jun 2024 14:27:49 +0200 Subject: [PATCH 22/31] ARM: dts: stm32: order stm32mp13-pinctrl nodes Keep alphabetic order for pins definition nodes for a better read. Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 130 ++++++++++---------- 1 file changed, 65 insertions(+), 65 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index fc56be60cfcd..0f3b752620bb 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -19,6 +19,13 @@ pins { }; }; + adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 { + pins { + pinmux = , /* ADC1_INP2 */ + ; /* ADC1_INP11 */ + }; + }; + dcmipp_pins_a: dcmi-0 { pins1 { pinmux = ,/* DCMI_HSYNC */ @@ -52,35 +59,6 @@ pins1 { }; }; - goodix_pins_a: goodix-0 { - /* - * touchscreen reset needs to be configured - * via the pinctrl not the driver (a pull-down resistor - * has been soldered onto the reset line which forces - * the touchscreen to reset state). - */ - pins1 { - pinmux = ; - output-high; - bias-pull-up; - }; - /* - * Interrupt line must have a pull-down resistor - * in order to freeze the i2c address at 0x5D - */ - pins2 { - pinmux = ; - bias-pull-down; - }; - }; - - adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 { - pins { - pinmux = , /* ADC1_INP2 */ - ; /* ADC1_INP11 */ - }; - }; - eth1_rgmii_pins_a: eth1-rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -127,6 +105,42 @@ pins1 { }; }; + eth1_rmii_pins_a: eth1-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + + }; + + eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + eth2_rgmii_pins_a: eth2-rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -172,42 +186,6 @@ pins1 { }; }; - eth1_rmii_pins_a: eth1-rmii-0 { - pins1 { - pinmux = , /* ETH_RMII_TXD0 */ - , /* ETH_RMII_TXD1 */ - , /* ETH_RMII_TX_EN */ - , /* ETH_RMII_REF_CLK */ - , /* ETH_MDIO */ - ; /* ETH_MDC */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = , /* ETH_RMII_RXD0 */ - , /* ETH_RMII_RXD1 */ - ; /* ETH_RMII_CRS_DV */ - bias-disable; - }; - - }; - - eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { - pins1 { - pinmux = , /* ETH_RMII_TXD0 */ - , /* ETH_RMII_TXD1 */ - , /* ETH_RMII_TX_EN */ - , /* ETH_RMII_REF_CLK */ - , /* ETH_MDIO */ - , /* ETH_MDC */ - , /* ETH_RMII_RXD0 */ - , /* ETH_RMII_RXD1 */ - ; /* ETH_RMII_CRS_DV */ - }; - }; - eth2_rmii_pins_a: eth2-rmii-0 { pins1 { pinmux = , /* ETH_RMII_TXD0 */ @@ -243,6 +221,28 @@ pins1 { }; }; + goodix_pins_a: goodix-0 { + /* + * touchscreen reset needs to be configured + * via the pinctrl not the driver (a pull-down resistor + * has been soldered onto the reset line which forces + * the touchscreen to reset state). + */ + pins1 { + pinmux = ; + output-high; + bias-pull-up; + }; + /* + * Interrupt line must have a pull-down resistor + * in order to freeze the i2c address at 0x5D + */ + pins2 { + pinmux = ; + bias-pull-down; + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ From 1b02383c385b16b4b275e30a3dd5860c0fd95c4a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 23 Jun 2024 21:51:56 +0200 Subject: [PATCH 23/31] ARM: dts: stm32: Add ethernet support for DH STM32MP13xx DHCOR DHSBC board Add ethernet support for the DH STM32MP13xx DHCOR DHSBC carrier board. This carrier board is populated with two gigabit ethernet ports and two Realtek RTL8211F PHYs, both are described in this DT patch. Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- .../boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts index 5f4f6b6e427a..bacb70b4256b 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -22,6 +22,8 @@ / { "st,stm32mp135"; aliases { + ethernet0 = ðernet1; + ethernet1 = ðernet2; serial2 = &usart1; serial3 = &usart2; }; @@ -72,6 +74,60 @@ channel@12 { }; }; +ðernet1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <ð1_rgmii_pins_a>; + pinctrl-1 = <ð1_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + st,ext-phyclk; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + ethphy1: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + interrupt-parent = <&gpiog>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + reset-assert-us = <15000>; + reset-deassert-us = <55000>; + reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ðernet2 { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + pinctrl-0 = <ð2_rgmii_pins_a>; + pinctrl-1 = <ð2_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + st,ext-phyclk; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + ethphy2: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + interrupt-parent = <&gpiog>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + reset-assert-us = <15000>; + reset-deassert-us = <55000>; + reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>; + }; + }; +}; + &gpioa { gpio-line-names = "", "", "", "", "", "DHSBC_USB_PWR_CC1", "", "", From 7253ddc6a38d39951d3f06cbf80bbfe236dae3e8 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Fri, 31 May 2024 17:07:12 +0200 Subject: [PATCH 24/31] arm64: dts: st: add HPDMA nodes on stm32mp251 The High Performance Direct Memory Access (HPDMA) controller is used to perform programmable data transfers between memory-mapped peripherals and memories (or between memories) via linked-lists. There are 3 instances of HPDMA on stm32mp251, using stm32-dma3 driver, with 16 channels per instance and with one interrupt per channel. Channels 0 to 7 are implemented with a FIFO of 8 bytes. Channels 8 to 11 are implemented with a FIFO of 32 bytes. Channels 12 to 15 are implemented with a FIFO of 128 bytes. Thanks to stm32-dma3 bindings, the user can ask for a channel with specific FIFO size. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 69 ++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 96d6de29c14c..2fe1c2bc2c2e 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -125,6 +125,75 @@ soc@0 { interrupt-parent = <&intc>; ranges = <0x0 0x0 0x0 0x80000000>; + hpdma: dma-controller@40400000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40400000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&scmi_clk CK_SCMI_HPDMA1>; + #dma-cells = <3>; + }; + + hpdma2: dma-controller@40410000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40410000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&scmi_clk CK_SCMI_HPDMA2>; + #dma-cells = <3>; + }; + + hpdma3: dma-controller@40420000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40420000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&scmi_clk CK_SCMI_HPDMA3>; + #dma-cells = <3>; + }; + rifsc: bus@42080000 { compatible = "st,stm32mp25-rifsc", "simple-bus"; reg = <0x42080000 0x1000>; From ed4dd5b795738a14ceb58299b6456c84b0ad6c5e Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Wed, 19 Jun 2024 14:58:13 +0200 Subject: [PATCH 25/31] arm64: dts: st: add ethernet1 and ethernet2 support on stm32mp25 Both instances ethernet based on GMAC SNPS IP on stm32mp25. GMAC IP version is SNPS 5.3 Signed-off-by: Christophe Roullier Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 49 +++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp253.dtsi | 51 ++++++++++++++++++++++++++ 2 files changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 2fe1c2bc2c2e..16e95f76bd95 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -497,6 +497,55 @@ sdmmc1: mmc@48220000 { access-controllers = <&rifsc 76>; status = "disabled"; }; + + ethernet1: ethernet@482c0000 { + compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; + reg = <0x482c0000 0x4000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ptp_ref", + "ethstp", + "eth-ck"; + clocks = <&rcc CK_ETH1_MAC>, + <&rcc CK_ETH1_TX>, + <&rcc CK_ETH1_RX>, + <&rcc CK_KER_ETH1PTP>, + <&rcc CK_ETH1_STP>, + <&rcc CK_KER_ETH1>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,mixed-burst; + snps,mtl-rx-config = <&mtl_rx_setup_1>; + snps,mtl-tx-config = <&mtl_tx_setup_1>; + snps,pbl = <2>; + snps,tso; + st,syscon = <&syscfg 0x3000>; + access-controllers = <&rifsc 60>; + status = "disabled"; + + mtl_rx_setup_1: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + mtl_tx_setup_1: tx-queues-config { + snps,tx-queues-to-use = <4>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + }; + + stmmac_axi_config_1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; }; bsec: efuse@44000000 { diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi index 652e41facb35..eeceb086252b 100644 --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -41,3 +41,54 @@ timer { &optee { interrupts = ; }; + +&rifsc { + ethernet2: ethernet@482d0000 { + compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; + reg = <0x482d0000 0x4000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ptp_ref", + "ethstp", + "eth-ck"; + clocks = <&rcc CK_ETH2_MAC>, + <&rcc CK_ETH2_TX>, + <&rcc CK_ETH2_RX>, + <&rcc CK_KER_ETH2PTP>, + <&rcc CK_ETH2_STP>, + <&rcc CK_KER_ETH2>; + snps,axi-config = <&stmmac_axi_config_2>; + snps,mixed-burst; + snps,mtl-rx-config = <&mtl_rx_setup_2>; + snps,mtl-tx-config = <&mtl_tx_setup_2>; + snps,pbl = <2>; + snps,tso; + st,syscon = <&syscfg 0x3400>; + access-controllers = <&rifsc 61>; + status = "disabled"; + + mtl_rx_setup_2: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + mtl_tx_setup_2: tx-queues-config { + snps,tx-queues-to-use = <4>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + }; + + stmmac_axi_config_2: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; +}; From b4c354b1b226af0855b43cdae8fbb0361995e407 Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Wed, 19 Jun 2024 14:58:14 +0200 Subject: [PATCH 26/31] arm64: dts: st: add eth2 pinctrl entries in stm32mp25-pinctrl.dtsi Add pinctrl entry related to ETH2 in stm32mp25-pinctrl.dtsi ethernet2: RGMII with crystal. Signed-off-by: Christophe Roullier Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 4e677e64c406..8fdd5f020425 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -6,6 +6,65 @@ #include &pinctrl { + eth2_rgmii_pins_a: eth2-rgmii-0 { + pins1 { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + ; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins4 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + pins5 { + pinmux = ; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { + pins { + pinmux = , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_MDC */ + , /* ETH_MDIO */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CTL */ + ; /* ETH_RGMII_RX_CLK */ + }; + }; + i2c2_pins_a: i2c2-0 { pins { pinmux = , /* I2C2_SCL */ From e0fc47d897fbf89bd556a898624490e7171f3adb Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Wed, 19 Jun 2024 14:58:15 +0200 Subject: [PATCH 27/31] arm64: dts: st: enable Ethernet2 on stm32mp257f-ev1 board ETHERNET2 instance is connected to Realtek PHY in RGMII mode Ethernet is SNSP IP with GMAC5 version. Signed-off-by: Christophe Roullier Reviewed-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 18c6266532b2..68c8cb25d5a1 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -17,6 +17,7 @@ / { compatible = "st,stm32mp257f-ev1", "st,stm32mp257"; aliases { + ethernet0 = ðernet2; serial0 = &usart2; serial1 = &usart6; }; @@ -56,6 +57,29 @@ &arm_wdt { status = "okay"; }; +ðernet2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð2_rgmii_pins_a>; + pinctrl-1 = <ð2_rgmii_sleep_pins_a>; + max-speed = <1000>; + phy-handle = <&phy0_eth2>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0_eth2: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + reset-gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + &i2c2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c2_pins_a>; From 81e7b432f144155d791ae4ed8cb0ef78ddb532cf Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Fri, 5 Jul 2024 11:36:35 +0200 Subject: [PATCH 28/31] ARM: dts: stm32: omit unused pinctrl groups from stm32mp13 dtb files stm32mp13-pinctrl.dtsi contains nearly all pinctrl groups collected from all boards. Most of them end up unused by a board and only waste binary space. Add /omit-if-no-ref/ to the groups to scrub the unused groups from the dtbs. Use the following regex to update the file and drop two useless newlines too: s@^\t[^:]\+: [^ ]\+ {$@\t/omit-if-no-ref/\r&@ Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 92 ++++++++++++++++++++- 1 file changed, 90 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index 0f3b752620bb..c9f588a65094 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -6,12 +6,14 @@ #include &pinctrl { + /omit-if-no-ref/ adc1_pins_a: adc1-pins-0 { pins { pinmux = ; /* ADC1 in12 */ }; }; + /omit-if-no-ref/ adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { pins { pinmux = , /* ADC1 in6 */ @@ -19,6 +21,7 @@ pins { }; }; + /omit-if-no-ref/ adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 { pins { pinmux = , /* ADC1_INP2 */ @@ -26,6 +29,7 @@ pins { }; }; + /omit-if-no-ref/ dcmipp_pins_a: dcmi-0 { pins1 { pinmux = ,/* DCMI_HSYNC */ @@ -43,6 +47,7 @@ pins1 { }; }; + /omit-if-no-ref/ dcmipp_sleep_pins_a: dcmi-sleep-0 { pins1 { pinmux = ,/* DCMI_HSYNC */ @@ -59,6 +64,7 @@ pins1 { }; }; + /omit-if-no-ref/ eth1_rgmii_pins_a: eth1-rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -83,9 +89,9 @@ pins2 { ; /* ETH_RGMII_RX_CLK */ bias-disable; }; - }; + /omit-if-no-ref/ eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -105,6 +111,7 @@ pins1 { }; }; + /omit-if-no-ref/ eth1_rmii_pins_a: eth1-rmii-0 { pins1 { pinmux = , /* ETH_RMII_TXD0 */ @@ -124,9 +131,9 @@ pins2 { ; /* ETH_RMII_CRS_DV */ bias-disable; }; - }; + /omit-if-no-ref/ eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { pins1 { pinmux = , /* ETH_RMII_TXD0 */ @@ -141,6 +148,7 @@ pins1 { }; }; + /omit-if-no-ref/ eth2_rgmii_pins_a: eth2-rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -167,6 +175,7 @@ pins2 { }; }; + /omit-if-no-ref/ eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { pins1 { pinmux = , /* ETH_RGMII_TXD0 */ @@ -186,6 +195,7 @@ pins1 { }; }; + /omit-if-no-ref/ eth2_rmii_pins_a: eth2-rmii-0 { pins1 { pinmux = , /* ETH_RMII_TXD0 */ @@ -207,6 +217,7 @@ pins2 { }; }; + /omit-if-no-ref/ eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 { pins1 { pinmux = , /* ETH_RMII_TXD0 */ @@ -221,6 +232,7 @@ pins1 { }; }; + /omit-if-no-ref/ goodix_pins_a: goodix-0 { /* * touchscreen reset needs to be configured @@ -243,6 +255,7 @@ pins2 { }; }; + /omit-if-no-ref/ i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ @@ -253,6 +266,7 @@ pins { }; }; + /omit-if-no-ref/ i2c1_sleep_pins_a: i2c1-sleep-0 { pins { pinmux = , /* I2C1_SCL */ @@ -260,6 +274,7 @@ pins { }; }; + /omit-if-no-ref/ i2c5_pins_a: i2c5-0 { pins { pinmux = , /* I2C5_SCL */ @@ -270,6 +285,7 @@ pins { }; }; + /omit-if-no-ref/ i2c5_sleep_pins_a: i2c5-sleep-0 { pins { pinmux = , /* I2C5_SCL */ @@ -277,6 +293,7 @@ pins { }; }; + /omit-if-no-ref/ i2c5_pins_b: i2c5-1 { pins { pinmux = , /* I2C5_SCL */ @@ -287,6 +304,7 @@ pins { }; }; + /omit-if-no-ref/ i2c5_sleep_pins_b: i2c5-sleep-1 { pins { pinmux = , /* I2C5_SCL */ @@ -294,6 +312,7 @@ pins { }; }; + /omit-if-no-ref/ ltdc_pins_a: ltdc-0 { pins { pinmux = , /* LCD_CLK */ @@ -324,6 +343,7 @@ pins { }; }; + /omit-if-no-ref/ ltdc_sleep_pins_a: ltdc-sleep-0 { pins { pinmux = , /* LCD_CLK */ @@ -351,6 +371,7 @@ pins { }; }; + /omit-if-no-ref/ m_can1_pins_a: m-can1-0 { pins1 { pinmux = ; /* CAN1_TX */ @@ -364,6 +385,7 @@ pins2 { }; }; + /omit-if-no-ref/ m_can1_sleep_pins_a: m_can1-sleep-0 { pins { pinmux = , /* CAN1_TX */ @@ -371,6 +393,7 @@ pins { }; }; + /omit-if-no-ref/ m_can2_pins_a: m-can2-0 { pins1 { pinmux = ; /* CAN2_TX */ @@ -384,6 +407,7 @@ pins2 { }; }; + /omit-if-no-ref/ m_can2_sleep_pins_a: m_can2-sleep-0 { pins { pinmux = , /* CAN2_TX */ @@ -391,6 +415,7 @@ pins { }; }; + /omit-if-no-ref/ mcp23017_pins_a: mcp23017-0 { pins { pinmux = ; @@ -398,6 +423,7 @@ pins { }; }; + /omit-if-no-ref/ pwm3_pins_a: pwm3-0 { pins { pinmux = ; /* TIM3_CH4 */ @@ -407,12 +433,14 @@ pins { }; }; + /omit-if-no-ref/ pwm3_sleep_pins_a: pwm3-sleep-0 { pins { pinmux = ; /* TIM3_CH4 */ }; }; + /omit-if-no-ref/ pwm4_pins_a: pwm4-0 { pins { pinmux = ; /* TIM4_CH2 */ @@ -422,12 +450,14 @@ pins { }; }; + /omit-if-no-ref/ pwm4_sleep_pins_a: pwm4-sleep-0 { pins { pinmux = ; /* TIM4_CH2 */ }; }; + /omit-if-no-ref/ pwm5_pins_a: pwm5-0 { pins { pinmux = ; /* TIM5_CH3 */ @@ -437,12 +467,14 @@ pins { }; }; + /omit-if-no-ref/ pwm5_sleep_pins_a: pwm5-sleep-0 { pins { pinmux = ; /* TIM5_CH3 */ }; }; + /omit-if-no-ref/ pwm8_pins_a: pwm8-0 { pins { pinmux = ; /* TIM8_CH3 */ @@ -452,12 +484,14 @@ pins { }; }; + /omit-if-no-ref/ pwm8_sleep_pins_a: pwm8-sleep-0 { pins { pinmux = ; /* TIM8_CH3 */ }; }; + /omit-if-no-ref/ pwm13_pins_a: pwm13-0 { pins { pinmux = ; /* TIM13_CH1 */ @@ -467,12 +501,14 @@ pins { }; }; + /omit-if-no-ref/ pwm13_sleep_pins_a: pwm13-sleep-0 { pins { pinmux = ; /* TIM13_CH1 */ }; }; + /omit-if-no-ref/ pwm14_pins_a: pwm14-0 { pins { pinmux = ; /* TIM14_CH1 */ @@ -482,12 +518,14 @@ pins { }; }; + /omit-if-no-ref/ pwm14_sleep_pins_a: pwm14-sleep-0 { pins { pinmux = ; /* TIM14_CH1 */ }; }; + /omit-if-no-ref/ qspi_clk_pins_a: qspi-clk-0 { pins { pinmux = ; /* QSPI_CLK */ @@ -497,12 +535,14 @@ pins { }; }; + /omit-if-no-ref/ qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { pins { pinmux = ; /* QSPI_CLK */ }; }; + /omit-if-no-ref/ qspi_bk1_pins_a: qspi-bk1-0 { pins { pinmux = , /* QSPI_BK1_IO0 */ @@ -515,6 +555,7 @@ pins { }; }; + /omit-if-no-ref/ qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { pins { pinmux = , /* QSPI_BK1_IO0 */ @@ -524,6 +565,7 @@ pins { }; }; + /omit-if-no-ref/ qspi_cs1_pins_a: qspi-cs1-0 { pins { pinmux = ; /* QSPI_BK1_NCS */ @@ -533,12 +575,14 @@ pins { }; }; + /omit-if-no-ref/ qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { pins { pinmux = ; /* QSPI_BK1_NCS */ }; }; + /omit-if-no-ref/ sai1a_pins_a: sai1a-0 { pins { pinmux = , /* SAI1_SCK_A */ @@ -550,6 +594,7 @@ pins { }; }; + /omit-if-no-ref/ sai1a_sleep_pins_a: sai1a-sleep-0 { pins { pinmux = , /* SAI1_SCK_A */ @@ -558,6 +603,7 @@ pins { }; }; + /omit-if-no-ref/ sai1b_pins_a: sai1b-0 { pins { pinmux = ; /* SAI1_SD_B */ @@ -565,12 +611,14 @@ pins { }; }; + /omit-if-no-ref/ sai1b_sleep_pins_a: sai1b-sleep-0 { pins { pinmux = ; /* SAI1_SD_B */ }; }; + /omit-if-no-ref/ sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = , /* SDMMC1_D0 */ @@ -584,6 +632,7 @@ pins { }; }; + /omit-if-no-ref/ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { pins1 { pinmux = , /* SDMMC1_D0 */ @@ -602,6 +651,7 @@ pins2 { }; }; + /omit-if-no-ref/ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { pins { pinmux = , /* SDMMC1_D0 */ @@ -613,6 +663,7 @@ pins { }; }; + /omit-if-no-ref/ sdmmc1_clk_pins_a: sdmmc1-clk-0 { pins { pinmux = ; /* SDMMC1_CK */ @@ -622,6 +673,7 @@ pins { }; }; + /omit-if-no-ref/ sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins { pinmux = , /* SDMMC2_D0 */ @@ -635,6 +687,7 @@ pins { }; }; + /omit-if-no-ref/ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { pins1 { pinmux = , /* SDMMC2_D0 */ @@ -653,6 +706,7 @@ pins2 { }; }; + /omit-if-no-ref/ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { pins { pinmux = , /* SDMMC2_D0 */ @@ -664,6 +718,7 @@ pins { }; }; + /omit-if-no-ref/ sdmmc2_clk_pins_a: sdmmc2-clk-0 { pins { pinmux = ; /* SDMMC2_CK */ @@ -673,6 +728,7 @@ pins { }; }; + /omit-if-no-ref/ sdmmc2_d47_pins_a: sdmmc2-d47-0 { pins { pinmux = , /* SDMMC2_D4 */ @@ -685,6 +741,7 @@ pins { }; }; + /omit-if-no-ref/ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { pins { pinmux = , /* SDMMC2_D4 */ @@ -694,6 +751,7 @@ pins { }; }; + /omit-if-no-ref/ spi2_pins_a: spi2-0 { pins1 { pinmux = , /* SPI2_SCK */ @@ -709,6 +767,7 @@ pins2 { }; }; + /omit-if-no-ref/ spi2_sleep_pins_a: spi2-sleep-0 { pins { pinmux = , /* SPI2_SCK */ @@ -717,6 +776,7 @@ pins { }; }; + /omit-if-no-ref/ spi3_pins_a: spi3-0 { pins1 { pinmux = , /* SPI3_SCK */ @@ -732,6 +792,7 @@ pins2 { }; }; + /omit-if-no-ref/ spi3_sleep_pins_a: spi3-sleep-0 { pins { pinmux = , /* SPI3_SCK */ @@ -740,6 +801,7 @@ pins { }; }; + /omit-if-no-ref/ spi5_pins_a: spi5-0 { pins1 { pinmux = , /* SPI5_SCK */ @@ -755,6 +817,7 @@ pins2 { }; }; + /omit-if-no-ref/ spi5_sleep_pins_a: spi5-sleep-0 { pins { pinmux = , /* SPI5_SCK */ @@ -763,6 +826,7 @@ pins { }; }; + /omit-if-no-ref/ stm32g0_intn_pins_a: stm32g0-intn-0 { pins { pinmux = ; @@ -770,6 +834,7 @@ pins { }; }; + /omit-if-no-ref/ uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ @@ -783,6 +848,7 @@ pins2 { }; }; + /omit-if-no-ref/ uart4_idle_pins_a: uart4-idle-0 { pins1 { pinmux = ; /* UART4_TX */ @@ -793,6 +859,7 @@ pins2 { }; }; + /omit-if-no-ref/ uart4_sleep_pins_a: uart4-sleep-0 { pins { pinmux = , /* UART4_TX */ @@ -800,6 +867,7 @@ pins { }; }; + /omit-if-no-ref/ uart4_pins_b: uart4-1 { pins1 { pinmux = ; /* UART4_TX */ @@ -813,6 +881,7 @@ pins2 { }; }; + /omit-if-no-ref/ uart4_idle_pins_b: uart4-idle-1 { pins1 { pinmux = ; /* UART4_TX */ @@ -823,6 +892,7 @@ pins2 { }; }; + /omit-if-no-ref/ uart4_sleep_pins_b: uart4-sleep-1 { pins { pinmux = , /* UART4_TX */ @@ -830,6 +900,7 @@ pins { }; }; + /omit-if-no-ref/ uart7_pins_a: uart7-0 { pins1 { pinmux = , /* UART7_TX */ @@ -845,6 +916,7 @@ pins2 { }; }; + /omit-if-no-ref/ uart7_idle_pins_a: uart7-idle-0 { pins1 { pinmux = , /* UART7_TX */ @@ -862,6 +934,7 @@ pins3 { }; }; + /omit-if-no-ref/ uart7_sleep_pins_a: uart7-sleep-0 { pins { pinmux = , /* UART7_TX */ @@ -871,6 +944,7 @@ pins { }; }; + /omit-if-no-ref/ uart8_pins_a: uart8-0 { pins1 { pinmux = ; /* UART8_TX */ @@ -884,6 +958,7 @@ pins2 { }; }; + /omit-if-no-ref/ uart8_idle_pins_a: uart8-idle-0 { pins1 { pinmux = ; /* UART8_TX */ @@ -894,6 +969,7 @@ pins2 { }; }; + /omit-if-no-ref/ uart8_sleep_pins_a: uart8-sleep-0 { pins { pinmux = , /* UART8_TX */ @@ -901,6 +977,7 @@ pins { }; }; + /omit-if-no-ref/ usart1_pins_a: usart1-0 { pins1 { pinmux = , /* USART1_TX */ @@ -916,6 +993,7 @@ pins2 { }; }; + /omit-if-no-ref/ usart1_idle_pins_a: usart1-idle-0 { pins1 { pinmux = , /* USART1_TX */ @@ -933,6 +1011,7 @@ pins3 { }; }; + /omit-if-no-ref/ usart1_sleep_pins_a: usart1-sleep-0 { pins { pinmux = , /* USART1_TX */ @@ -942,6 +1021,7 @@ pins { }; }; + /omit-if-no-ref/ usart1_pins_b: usart1-1 { pins1 { pinmux = ; /* USART1_TX */ @@ -955,6 +1035,7 @@ pins2 { }; }; + /omit-if-no-ref/ usart1_idle_pins_b: usart1-idle-1 { pins1 { pinmux = ; /* USART1_TX */ @@ -965,6 +1046,7 @@ pins2 { }; }; + /omit-if-no-ref/ usart1_sleep_pins_b: usart1-sleep-1 { pins { pinmux = , /* USART1_TX */ @@ -972,6 +1054,7 @@ pins { }; }; + /omit-if-no-ref/ usart2_pins_a: usart2-0 { pins1 { pinmux = , /* USART2_TX */ @@ -987,6 +1070,7 @@ pins2 { }; }; + /omit-if-no-ref/ usart2_idle_pins_a: usart2-idle-0 { pins1 { pinmux = , /* USART2_TX */ @@ -1004,6 +1088,7 @@ pins3 { }; }; + /omit-if-no-ref/ usart2_sleep_pins_a: usart2-sleep-0 { pins { pinmux = , /* USART2_TX */ @@ -1013,6 +1098,7 @@ pins { }; }; + /omit-if-no-ref/ usart2_pins_b: usart2-1 { pins1 { pinmux = , /* USART2_TX */ @@ -1028,6 +1114,7 @@ pins2 { }; }; + /omit-if-no-ref/ usart2_idle_pins_b: usart2-idle-1 { pins1 { pinmux = , /* USART2_TX */ @@ -1045,6 +1132,7 @@ pins3 { }; }; + /omit-if-no-ref/ usart2_sleep_pins_b: usart2-sleep-1 { pins { pinmux = , /* USART2_TX */ From 87b6426ab92efd91a17aed1f5b1d94f36938e28f Mon Sep 17 00:00:00 2001 From: Pascal Paillet Date: Fri, 28 Jun 2024 10:58:11 +0200 Subject: [PATCH 29/31] regulator: Add STM32MP25 regulator bindings These bindings will be used for the SCMI voltage domain. Signed-off-by: Pascal Paillet Acked-by: Krzysztof Kozlowski Acked-by: Mark Brown Signed-off-by: Alexandre Torgue --- .../regulator/st,stm32mp25-regulator.h | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 include/dt-bindings/regulator/st,stm32mp25-regulator.h diff --git a/include/dt-bindings/regulator/st,stm32mp25-regulator.h b/include/dt-bindings/regulator/st,stm32mp25-regulator.h new file mode 100644 index 000000000000..3c3d30911dd0 --- /dev/null +++ b/include/dt-bindings/regulator/st,stm32mp25-regulator.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2024, STMicroelectronics - All Rights Reserved + */ + +#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP25_REGULATOR_H +#define __DT_BINDINGS_REGULATOR_ST_STM32MP25_REGULATOR_H + +/* SCMI voltage domains identifiers */ + +/* SOC Internal regulators */ +#define VOLTD_SCMI_VDDIO1 0 +#define VOLTD_SCMI_VDDIO2 1 +#define VOLTD_SCMI_VDDIO3 2 +#define VOLTD_SCMI_VDDIO4 3 +#define VOLTD_SCMI_VDDIO 4 +#define VOLTD_SCMI_UCPD 5 +#define VOLTD_SCMI_USB33 6 +#define VOLTD_SCMI_ADC 7 +#define VOLTD_SCMI_GPU 8 +#define VOLTD_SCMI_VREFBUF 9 + +/* STPMIC2 regulators */ +#define VOLTD_SCMI_STPMIC2_BUCK1 10 +#define VOLTD_SCMI_STPMIC2_BUCK2 11 +#define VOLTD_SCMI_STPMIC2_BUCK3 12 +#define VOLTD_SCMI_STPMIC2_BUCK4 13 +#define VOLTD_SCMI_STPMIC2_BUCK5 14 +#define VOLTD_SCMI_STPMIC2_BUCK6 15 +#define VOLTD_SCMI_STPMIC2_BUCK7 16 +#define VOLTD_SCMI_STPMIC2_LDO1 17 +#define VOLTD_SCMI_STPMIC2_LDO2 18 +#define VOLTD_SCMI_STPMIC2_LDO3 19 +#define VOLTD_SCMI_STPMIC2_LDO4 20 +#define VOLTD_SCMI_STPMIC2_LDO5 21 +#define VOLTD_SCMI_STPMIC2_LDO6 22 +#define VOLTD_SCMI_STPMIC2_LDO7 23 +#define VOLTD_SCMI_STPMIC2_LDO8 24 +#define VOLTD_SCMI_STPMIC2_REFDDR 25 + +/* External regulators */ +#define VOLTD_SCMI_REGU0 26 +#define VOLTD_SCMI_REGU1 27 +#define VOLTD_SCMI_REGU2 28 +#define VOLTD_SCMI_REGU3 29 +#define VOLTD_SCMI_REGU4 30 + +#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP25_REGULATOR_H */ From 387abbb94535a74dbbd37fcfb33094daa0c56129 Mon Sep 17 00:00:00 2001 From: Pascal Paillet Date: Fri, 28 Jun 2024 10:58:12 +0200 Subject: [PATCH 30/31] arm64: dts: st: add scmi regulators on stm32mp25 Add SCMI regulators description on STM32MP25. Signed-off-by: Pascal Paillet Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 35 ++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 16e95f76bd95..1167cf63d7e8 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { #address-cells = <2>; @@ -75,6 +76,40 @@ scmi_reset: protocol@16 { reg = <0x16>; #reset-cells = <1>; }; + + scmi_voltd: protocol@17 { + reg = <0x17>; + + scmi_regu: regulators { + #address-cells = <1>; + #size-cells = <0>; + + scmi_vddio1: regulator@0 { + reg = ; + regulator-name = "vddio1"; + }; + scmi_vddio2: regulator@1 { + reg = ; + regulator-name = "vddio2"; + }; + scmi_vddio3: regulator@2 { + reg = ; + regulator-name = "vddio3"; + }; + scmi_vddio4: regulator@3 { + reg = ; + regulator-name = "vddio4"; + }; + scmi_vdd33ucpd: regulator@5 { + reg = ; + regulator-name = "vdd33ucpd"; + }; + scmi_vdda18adc: regulator@7 { + reg = ; + regulator-name = "vdda18adc"; + }; + }; + }; }; }; From 419ed754a3b6279f748909dd552fe425c7fce4a2 Mon Sep 17 00:00:00 2001 From: Pascal Paillet Date: Fri, 28 Jun 2024 10:58:13 +0200 Subject: [PATCH 31/31] arm64: dts: st: describe power supplies for stm32mp257f-ev1 board Describe power supplies for stm32mp257f-ev1 board. Signed-off-by: Pascal Paillet Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 43 +++++++++++++++++----- 1 file changed, 34 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 68c8cb25d5a1..214191a8322b 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include "stm32mp257.dtsi" #include "stm32mp25xf.dtsi" #include "stm32mp25-pinctrl.dtsi" @@ -42,14 +43,6 @@ fw@80000000 { no-map; }; }; - - vdd_sdcard: vdd-sdcard { - compatible = "regulator-fixed"; - regulator-name = "vdd_sdcard"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; }; &arm_wdt { @@ -100,6 +93,37 @@ &i2c8 { status = "disabled"; }; +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + scmi_vddcore: regulator@11 { + reg = ; + regulator-name = "vddcore"; + }; + scmi_v1v8: regulator@14 { + reg = ; + regulator-name = "v1v8"; + }; + scmi_v3v3: regulator@16 { + reg = ; + regulator-name = "v3v3"; + }; + scmi_vdd_emmc: regulator@18 { + reg = ; + regulator-name = "vdd_emmc"; + }; + scmi_vdd3v3_usb: regulator@20 { + reg = ; + regulator-name = "vdd3v3_usb"; + }; + scmi_vdd_sdcard: regulator@23 { + reg = ; + regulator-name = "vdd_sdcard"; + }; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>; @@ -109,7 +133,8 @@ &sdmmc1 { disable-wp; st,neg-edge; bus-width = <4>; - vmmc-supply = <&vdd_sdcard>; + vmmc-supply = <&scmi_vdd_sdcard>; + vqmmc-supply = <&scmi_vddio1>; status = "okay"; };