From 14628e4444ea8b5ea058e1bd663ff62f2e731feb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sat, 26 Dec 2015 00:40:12 +0100 Subject: [PATCH 01/38] ARM: dts: n900: Include adp1653 device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds adp1653 device into n900 DT structure. DT support in adp1653 driver is there since v4.2-rc1 version. Signed-off-by: Pali Rohár Acked-by: Pavel Machek Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-n900.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 74d8f7eb5563..20603f3f9bd0 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -522,6 +522,21 @@ tsl2563: tsl2563@29 { amstaos,cover-comp-gain = <16>; }; + adp1653: led-controller@30 { + compatible = "adi,adp1653"; + reg = <0x30>; + enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* 88 */ + + flash { + flash-timeout-us = <500000>; + flash-max-microamp = <320000>; + led-max-microamp = <50000>; + }; + indicator { + led-max-microamp = <17500>; + }; + }; + lp5523: lp5523@32 { compatible = "national,lp5523"; reg = <0x32>; From 12e47442c2a1322c2762072fd6ea07462f1b04ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sat, 26 Dec 2015 00:32:25 +0100 Subject: [PATCH 02/38] ARM: dts: omap3: Include missing bandgap data for ti-soc-thermal driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Driver for omap3 with documentation is there since v4.4-rc1. Signed-off-by: Pali Rohár Acked-by: Pavel Machek Tested-by: Pavel Machek [tony@atomide.com: added thermal-sensor-cells as suggested by Roger] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap34xx.dtsi | 6 ++++++ arch/arm/boot/dts/omap36xx.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index 4f6b2d5b1902..387dc31822fe 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -54,6 +54,12 @@ ports { #size-cells = <0>; }; }; + + bandgap { + reg = <0x48002524 0x4>; + compatible = "ti,omap34xx-bandgap"; + #thermal-sensor-cells = <0>; + }; }; }; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 86253de5a97a..f19c87bd6bf3 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -86,6 +86,12 @@ ports { #size-cells = <0>; }; }; + + bandgap { + reg = <0x48002524 0x4>; + compatible = "ti,omap36xx-bandgap"; + #thermal-sensor-cells = <0>; + }; }; }; From 2ac6e66ed6dbd5bf167d994a78a041ed4c2db654 Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Wed, 30 Dec 2015 13:41:33 +0200 Subject: [PATCH 03/38] ARM: dts: cm-t335: Add support for CAN bus Add CAN bus pinmux. Enable D_CAN bus controllers 0 and 1 The pinmux of uart1 node contradicts the pinmux of dcan0 and dcan1 nodes. U-Boot should delete the uart1 or dcan0/1 nodes. Signed-off-by: Uri Mashiach Acked-by: Igor Grinberg Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-cm-t335.dts | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index 42e9b665582a..93997a2da8c1 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -134,6 +134,24 @@ AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) >; }; + dcan0_pins: pinmux_dcan0_pins { + pinctrl-single,pins = < + /* uart1_ctsn.dcan0_tx */ + AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) + /* uart1_rtsn.dcan0_rx */ + AM33XX_IOPAD(0x97C, PIN_INPUT | MUX_MODE2) + >; + }; + + dcan1_pins: pinmux_dcan1_pins { + pinctrl-single,pins = < + /* uart1_rxd.dcan1_tx */ + AM33XX_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) + /* uart1_txd.dcan1_rx */ + AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE2) + >; + }; + ecap0_pins: pinmux_ecap0_pins { pinctrl-single,pins = < /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ @@ -394,3 +412,15 @@ &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; }; + +&dcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dcan0_pins>; +}; + +&dcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins>; +}; From 511fc6d85b6bc6c28b830d082ebeeb5dcea4563b Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Wed, 30 Dec 2015 13:41:34 +0200 Subject: [PATCH 04/38] ARM: dts: cm-t335: add touchscreen support Touchscreen and analog digital converter configurations. Signed-off-by: Uri Mashiach Acked-by: Igor Grinberg Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-cm-t335.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index 93997a2da8c1..f0c880ff33a6 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -424,3 +424,20 @@ &dcan1 { pinctrl-names = "default"; pinctrl-0 = <&dcan1_pins>; }; + +/* Touschscreen and analog digital converter */ +&tscadc { + status = "okay"; + tsc { + ti,wires = <4>; + ti,x-plate-resistance = <200>; + ti,coordinate-readouts = <5>; + ti,wire-config = <0x01 0x10 0x23 0x32>; + ti,charge-delay = <0x400>; + }; + + adc { + ti,adc-channels = <4 5 6 7>; + }; +}; + From 48ab364478e77ab36798eb8fff385edb3eddc357 Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Wed, 30 Dec 2015 13:41:35 +0200 Subject: [PATCH 05/38] ARM: dts: cm-t335: add audio support The TLV320AIC23B codec is connected to the CPU by McASP controller 1 for data and I2C0 for control. Modifications: - Enable and configure McASP controller 1. - Add TLV320AIC23B codec pinmux. - Add TLV320AIC23B codec configurations. - Use simple-audio-card as CPU to codec glue. Signed-off-by: Uri Mashiach Acked-by: Igor Grinberg Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-cm-t335.dts | 69 ++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index f0c880ff33a6..af6dbba093f3 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -46,6 +46,36 @@ backlight { brightness-levels = <0 51 53 56 62 75 101 152 255>; default-brightness-level = <8>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "cm-t335"; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Headphone", "Headphone Jack"; + + simple-audio-card,routing = + "Headphone Jack", "LHPOUT", + "Headphone Jack", "RHPOUT", + "LLINEIN", "Line In", + "RLINEIN", "Line In", + "MICIN", "Mic Jack"; + + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic23>; + system-clock-frequency = <12000000>; + }; + }; }; &am33xx_pinmux { @@ -248,6 +278,20 @@ bluetooth_pins: pinmux_bluetooth_pins { AM33XX_IOPAD(0x9b0, PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; + + /* TLV320AIC23B codec */ + mcasp1_pins: pinmux_mcasp1_pins { + pinctrl-single,pins = < + /* MII1_CRS.mcasp1_aclkx */ + AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) + /* MII1_RX_ER.mcasp1_fsx */ + AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) + /* MII1_COL.mcasp1_axr2 */ + AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE4) + /* RMII1_REF_CLK.mcasp1_axr3 */ + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) + >; + }; }; &uart0 { @@ -282,6 +326,13 @@ ext_rtc: em3027@56 { compatible = "emmicro,em3027"; reg = <0x56>; }; + /* Audio codec */ + tlv320aic23: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + #sound-dai-cells= <0>; + status = "okay"; + }; }; &usb { @@ -441,3 +492,21 @@ adc { }; }; +/* CPU audio */ +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcasp1_pins>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 16 serializers */ + num-serializer = <16>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 + >; + tx-num-evt = <1>; + rx-num-evt = <1>; + + #sound-dai-cells= <0>; + status = "okay"; +}; From 444d66fafab89195a75752bbefb48b030bd24740 Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Wed, 30 Dec 2015 15:35:33 +0200 Subject: [PATCH 06/38] ARM: dts: add spi wifi support to cm-t335 Device tree modifications: - Pinmux for SPI0 and WiFi GPIOs. - SPI0 node with wlcore as a child node. Signed-off-by: Uri Mashiach Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-cm-t335.dts | 55 ++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index af6dbba093f3..5d5fb62d8fbe 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "am33xx.dtsi" +#include / { model = "CompuLab CM-T335"; @@ -40,6 +41,15 @@ vmmc_fixed: fixedregulator@0 { regulator-max-microvolt = <3300000>; }; + /* Regulator for WiFi */ + vwlan_fixed: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vwlan_fixed"; + gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; /* gpio0_20 */ + enable-active-high; + regulator-boot-off; + }; + backlight { compatible = "pwm-backlight"; pwms = <&ecap0 0 50000 0>; @@ -271,6 +281,21 @@ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) >; }; + spi0_pins: pinmux_spi0_pins { + pinctrl-single,pins = < + /* spi0_sclk.spi0_sclk */ + AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE0) + /* spi0_d0.spi0_d0 */ + AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) + /* spi0_d1.spi0_d1 */ + AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE0) + /* spi0_cs0.spi0_cs0 */ + AM33XX_IOPAD(0x95C, PIN_OUTPUT | MUX_MODE0) + /* spi0_cs1.spi0_cs1 */ + AM33XX_IOPAD(0x960, PIN_OUTPUT | MUX_MODE0) + >; + }; + /* wl1271 bluetooth */ bluetooth_pins: pinmux_bluetooth_pins { pinctrl-single,pins = < @@ -292,6 +317,16 @@ AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE4) AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) >; }; + + /* wl1271 WiFi */ + wifi_pins: pinmux_wifi_pins { + pinctrl-single,pins = < + /* EMU1.gpio3_8 - WiFi IRQ */ + AM33XX_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE7) + /* XDMA_EVENT_INTR1.gpio0_20 - WiFi enable */ + AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) + >; + }; }; &uart0 { @@ -510,3 +545,23 @@ &mcasp1 { #sound-dai-cells= <0>; status = "okay"; }; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + ti,pindir-d0-out-d1-in = <1>; + /* WLS1271 WiFi */ + wlcore: wlcore@1 { + compatible = "ti,wl1271"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pins>; + reg = <1>; + spi-max-frequency = <48000000>; + clock-xtal; + ref-clock-frequency = <38400000>; + interrupt-parent = <&gpio3>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + vwlan-supply = <&vwlan_fixed>; + }; +}; From 96d3bb1a0e0059d12d6ffb05fadeb3361b04b21e Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Sat, 9 Jan 2016 04:19:34 +0100 Subject: [PATCH 07/38] ARM: dts: N950: Add wlan support Add support for the wl1271 wlan chip. As far as I can see N9 uses the same chip with the same enable and irq gpio, but they use the mmc interface instead of the spi interface. Signed-off-by: Sebastian Reichel Acked-by: Igor Grinberg Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-n950-n9.dtsi | 15 ++++++++++++++ arch/arm/boot/dts/omap3-n950.dts | 29 ++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index a2c2b8d8dd2c..ab1174bb409e 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -31,6 +31,14 @@ vemmc: fixedregulator@0 { startup-delay-us = <150>; enable-active-high; }; + + vwlan_fixed: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "VWLAN"; + gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; /* gpio 35 */ + enable-active-high; + regulator-boot-off; + }; }; &omap3_pmx_core { @@ -44,6 +52,13 @@ OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2 */ OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3 */ >; }; + + wlan_pins: pinmux_wlan_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE4) /* gpio 35 - wlan enable */ + OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 - wlan irq */ + >; + }; }; &i2c1 { diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts index 0885b34d5d7d..e5967262f28b 100644 --- a/arch/arm/boot/dts/omap3-n950.dts +++ b/arch/arm/boot/dts/omap3-n950.dts @@ -17,6 +17,17 @@ / { compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3"; }; +&omap3_pmx_core { + spi4_pins: pinmux_spi4_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x218c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */ + OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */ + OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */ + OMAP3_CORE1_IOPAD(0x2196, PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */ + >; + }; +}; + &i2c2 { smia_1: camera@10 { compatible = "nokia,smia"; @@ -53,3 +64,21 @@ csi2a_ep: endpoint { }; }; }; + +&mcspi4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins>; + + wlcore: wlcore@0 { + compatible = "ti,wl1271"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_pins>; + reg = <0>; + spi-max-frequency = <48000000>; + clock-xtal; + ref-clock-frequency = <38400000>; + interrupts-extended = <&gpio2 10 IRQ_TYPE_LEVEL_HIGH>; /* gpio 42 */ + vwlan-supply = <&vwlan_fixed>; + }; +}; From 6dc73964fa09d86267ba459ca76e911d7319cc75 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 12 Feb 2016 13:25:14 -0800 Subject: [PATCH 08/38] ARM: dts: The rate for auxclk is 22.59792 by default The rate for auxclk is 22.59792 by default. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x-clocks.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/dm814x-clocks.dtsi b/arch/arm/boot/dts/dm814x-clocks.dtsi index 26001585673a..e0ea6a93a22e 100644 --- a/arch/arm/boot/dts/dm814x-clocks.dtsi +++ b/arch/arm/boot/dts/dm814x-clocks.dtsi @@ -41,11 +41,11 @@ devosc_ck: devosc_ck { reg = <0x0040>; }; - /* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */ + /* Optional auxosc, 20 - 30 MHz range, assume 22.5729 MHz by default */ auxosc_ck: auxosc_ck { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <27000000>; + clock-frequency = <22572900>; }; /* Optional 32768Hz crystal or clock on RTCOSC pins */ From 003fb0aede7dc779809a4d7a64b35c67ba23ac7a Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 12 Feb 2016 13:25:14 -0800 Subject: [PATCH 09/38] ARM: dts: Add support for GPMC for dm814x and dra62x Add support for GPMC for dm814x and dra62x Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index a25cd51e39ab..3fe68b1385fd 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -548,6 +548,18 @@ phy_sel: cpsw-phy-sel@48140650 { reg-names = "gmii-sel"; }; }; + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + ti,no-idle-on-init; + reg = <0x50000000 0x2000>; + interrupts = <100>; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + }; }; }; From 100be58aa847a09563d44f3f56239975e45ac6dc Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 12 Feb 2016 13:25:14 -0800 Subject: [PATCH 10/38] ARM: dts: Add NAND support for j5-eco evm Add NAND support for j5-eco evm. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra62x-j5eco-evm.dts | 56 ++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/dra62x-j5eco-evm.dts index 79008069020d..3937a589d331 100644 --- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts +++ b/arch/arm/boot/dts/dra62x-j5eco-evm.dts @@ -35,6 +35,62 @@ &cpsw_emac1 { phy-mode = "rgmii"; }; +&gpmc { + ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + linux,mtd-name= "micron,mt29f2g16aadwp"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + #address-cells = <1>; + #size-cells = <1>; + ti,nand-ecc-opt = "bch8"; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + partition@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + partition@0x80000 { + label = "U-Boot"; + reg = <0x80000 0x1c0000>; + }; + partition@0x1c0000 { + label = "Environment"; + reg = <0x240000 0x40000>; + }; + partition@0x280000 { + label = "Kernel"; + reg = <0x280000 0x500000>; + }; + partition@0x780000 { + label = "Filesystem"; + reg = <0x780000 0xf880000>; + }; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&sd1_pins>; From 0589df6a9fe8676050d45557ee0b0a8cc8a2d5e1 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 12 Feb 2016 13:25:14 -0800 Subject: [PATCH 11/38] ARM: dts: Add NAND support for dm8148-evm Add NAND support for dm8148-evm. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm8148-evm.dts | 56 ++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts index e070862b1038..862977f5a22a 100644 --- a/arch/arm/boot/dts/dm8148-evm.dts +++ b/arch/arm/boot/dts/dm8148-evm.dts @@ -35,6 +35,62 @@ &cpsw_emac1 { phy-mode = "rgmii"; }; +&gpmc { + ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + linux,mtd-name= "micron,mt29f2g16aadwp"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + #address-cells = <1>; + #size-cells = <1>; + ti,nand-ecc-opt = "bch8"; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + partition@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + partition@0x80000 { + label = "U-Boot"; + reg = <0x80000 0x1c0000>; + }; + partition@0x1c0000 { + label = "Environment"; + reg = <0x240000 0x40000>; + }; + partition@0x280000 { + label = "Kernel"; + reg = <0x280000 0x500000>; + }; + partition@0x780000 { + label = "Filesystem"; + reg = <0x780000 0xf880000>; + }; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&sd1_pins>; From 43acf16947bb4f33c9a3c9abc602cdae13292815 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 21 Dec 2015 14:43:18 +0530 Subject: [PATCH 12/38] ARM: dts: dra7: Add dt node for the sycon pcie Add new device tree node for the control module register space where PCIe registers are present. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c4d9175b90dc..e1b14ad7af38 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -156,6 +156,11 @@ scm_conf1: scm_conf@1c04 { compatible = "syscon"; reg = <0x1c04 0x0020>; }; + + scm_conf_pcie: scm_conf@1c24 { + compatible = "syscon"; + reg = <0x1c24 0x0024>; + }; }; cm_core_aon: cm_core_aon@5000 { From 6921e58b8457ce32165da9d4dc6936735a43c140 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 21 Dec 2015 14:43:19 +0530 Subject: [PATCH 13/38] ARM: dts: dra7: Use "syscon-phy-power" and "syscon-pcs" in PCIe PHY node Add "syscon-phy-power" property and "syscon-pcs" property which can be used to perform the control module initializations and remove the deprecated "ctrl-module" property from PCIe PHY dt nodes. Phandle to "sysclk" clock node is also added to the PCIe PHY node since some of the syscon initializations is based on system clock frequency. Since "omap_control_pcie1phy" and "omap_control_pcie2phy" devicetree nodes are no longer used, remove it. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 33 ++++++++++----------------------- 1 file changed, 10 insertions(+), 23 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index e1b14ad7af38..214d7845ab82 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1207,16 +1207,18 @@ pcie1_phy: pciephy@4a094000 { reg = <0x4a094000 0x80>, /* phy_rx */ <0x4a094400 0x64>; /* phy_tx */ reg-names = "phy_rx", "phy_tx"; - ctrl-module = <&omap_control_pcie1phy>; + syscon-phy-power = <&scm_conf_pcie 0x1c>; + syscon-pcs = <&scm_conf_pcie 0x10>; clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_m2ldo_ck>, <&optfclk_pciephy1_32khz>, <&optfclk_pciephy1_clk>, <&optfclk_pciephy1_div_clk>, - <&optfclk_pciephy_div>; + <&optfclk_pciephy_div>, + <&sys_clkin1>; clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", - "div-clk", "phy-div"; + "div-clk", "phy-div", "sysclk"; #phy-cells = <0>; }; @@ -1225,16 +1227,18 @@ pcie2_phy: pciephy@4a095000 { reg = <0x4a095000 0x80>, /* phy_rx */ <0x4a095400 0x64>; /* phy_tx */ reg-names = "phy_rx", "phy_tx"; - ctrl-module = <&omap_control_pcie2phy>; + syscon-phy-power = <&scm_conf_pcie 0x20>; + syscon-pcs = <&scm_conf_pcie 0x10>; clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_m2ldo_ck>, <&optfclk_pciephy2_32khz>, <&optfclk_pciephy2_clk>, <&optfclk_pciephy2_div_clk>, - <&optfclk_pciephy_div>; + <&optfclk_pciephy_div>, + <&sys_clkin1>; clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", - "div-clk", "phy-div"; + "div-clk", "phy-div", "sysclk"; #phy-cells = <0>; status = "disabled"; }; @@ -1250,23 +1254,6 @@ sata: sata@4a141100 { ti,hwmods = "sata"; }; - omap_control_pcie1phy: control-phy@0x4a003c40 { - compatible = "ti,control-phy-pcie"; - reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; - reg-names = "power", "control_sma", "pcie_pcs"; - clocks = <&sys_clkin1>; - clock-names = "sysclk"; - }; - - omap_control_pcie2phy: control-pcie@0x4a003c44 { - compatible = "ti,control-phy-pcie"; - reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; - reg-names = "power", "control_sma", "pcie_pcs"; - clocks = <&sys_clkin1>; - clock-names = "sysclk"; - status = "disabled"; - }; - rtc: rtc@48838000 { compatible = "ti,am3352-rtc"; reg = <0x48838000 0x100>; From 4b4f52ed9125604467e5feb6f8cd3a99d6ba1e25 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 21 Dec 2015 14:43:20 +0530 Subject: [PATCH 14/38] ARM: dts: dra7: Use "ti,dra7x-usb2-phy2" compatible string for USB2 PHY2 The USB2 PHY2 has a different register map compared to USB2 PHY1 to power on/off the PHY. In order to handle it, use the new compatible string "ti,dra7x-usb2-phy2" for the second instance of USB2 PHY. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 214d7845ab82..4ea90321d62c 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1302,7 +1302,8 @@ usb2_phy1: phy@4a084000 { }; usb2_phy2: phy@4a085000 { - compatible = "ti,omap-usb2"; + compatible = "ti,dra7x-usb2-phy2", + "ti,omap-usb2"; reg = <0x4a085000 0x400>; ctrl-module = <&omap_control_usb2phy2>; clocks = <&usb_phy2_always_on_clk32k>, From 2338c76a4345ab3ea21c3e54ef438f274aee457c Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Mon, 21 Dec 2015 14:43:21 +0530 Subject: [PATCH 15/38] ARM: dts: am4372/dra7/omap5: Use "syscon-phy-power" instead of "ctrl-module" Add "syscon-phy-power" property and remove the deprecated "ctrl-module" property from SATA and USB PHY node. Also remove the unused control module dt nodes. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 16 ++-------------- arch/arm/boot/dts/dra7.dtsi | 34 ++++------------------------------ arch/arm/boot/dts/omap5.dtsi | 26 +++----------------------- 3 files changed, 9 insertions(+), 67 deletions(-) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index df955ba4dc62..38790a32aa14 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -896,18 +896,6 @@ gpmc: gpmc@50000000 { status = "disabled"; }; - am43xx_control_usb2phy1: control-phy@44e10620 { - compatible = "ti,control-phy-usb2-am437"; - reg = <0x44e10620 0x4>; - reg-names = "power"; - }; - - am43xx_control_usb2phy2: control-phy@0x44e10628 { - compatible = "ti,control-phy-usb2-am437"; - reg = <0x44e10628 0x4>; - reg-names = "power"; - }; - ocp2scp0: ocp2scp@483a8000 { compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; #address-cells = <1>; @@ -918,7 +906,7 @@ ocp2scp0: ocp2scp@483a8000 { usb2_phy1: phy@483a8000 { compatible = "ti,am437x-usb2"; reg = <0x483a8000 0x8000>; - ctrl-module = <&am43xx_control_usb2phy1>; + syscon-phy-power = <&scm_conf 0x620>; clocks = <&usb_phy0_always_on_clk32k>, <&usb_otg_ss0_refclk960m>; clock-names = "wkupclk", "refclk"; @@ -937,7 +925,7 @@ ocp2scp1: ocp2scp@483e8000 { usb2_phy2: phy@483e8000 { compatible = "ti,am437x-usb2"; reg = <0x483e8000 0x8000>; - ctrl-module = <&am43xx_control_usb2phy2>; + syscon-phy-power = <&scm_conf 0x628>; clocks = <&usb_phy1_always_on_clk32k>, <&usb_otg_ss1_refclk960m>; clock-names = "wkupclk", "refclk"; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 4ea90321d62c..3d1426b799c2 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1173,14 +1173,6 @@ qspi: qspi@4b300000 { status = "disabled"; }; - omap_control_sata: control-phy@4a002374 { - compatible = "ti,control-phy-pipe3"; - reg = <0x4a002374 0x4>; - reg-names = "power"; - clocks = <&sys_clkin1>; - clock-names = "sysclk"; - }; - /* OCP2SCP3 */ ocp2scp@4a090000 { compatible = "ti,omap-ocp2scp"; @@ -1195,7 +1187,7 @@ sata_phy: phy@4A096000 { <0x4A096400 0x64>, /* phy_tx */ <0x4A096800 0x40>; /* pll_ctrl */ reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - ctrl-module = <&omap_control_sata>; + syscon-phy-power = <&scm_conf 0x374>; clocks = <&sys_clkin1>, <&sata_ref_clk>; clock-names = "sysclk", "refclk"; syscon-pllreset = <&scm_conf 0x3fc>; @@ -1263,24 +1255,6 @@ rtc: rtc@48838000 { clocks = <&sys_32k_ck>; }; - omap_control_usb2phy1: control-phy@4a002300 { - compatible = "ti,control-phy-usb2"; - reg = <0x4a002300 0x4>; - reg-names = "power"; - }; - - omap_control_usb3phy1: control-phy@4a002370 { - compatible = "ti,control-phy-pipe3"; - reg = <0x4a002370 0x4>; - reg-names = "power"; - }; - - omap_control_usb2phy2: control-phy@0x4a002e74 { - compatible = "ti,control-phy-usb2-dra7"; - reg = <0x4a002e74 0x4>; - reg-names = "power"; - }; - /* OCP2SCP1 */ ocp2scp@4a080000 { compatible = "ti,omap-ocp2scp"; @@ -1293,7 +1267,7 @@ ocp2scp@4a080000 { usb2_phy1: phy@4a084000 { compatible = "ti,omap-usb2"; reg = <0x4a084000 0x400>; - ctrl-module = <&omap_control_usb2phy1>; + syscon-phy-power = <&scm_conf 0x300>; clocks = <&usb_phy1_always_on_clk32k>, <&usb_otg_ss1_refclk960m>; clock-names = "wkupclk", @@ -1305,7 +1279,7 @@ usb2_phy2: phy@4a085000 { compatible = "ti,dra7x-usb2-phy2", "ti,omap-usb2"; reg = <0x4a085000 0x400>; - ctrl-module = <&omap_control_usb2phy2>; + syscon-phy-power = <&scm_conf 0xe74>; clocks = <&usb_phy2_always_on_clk32k>, <&usb_otg_ss2_refclk960m>; clock-names = "wkupclk", @@ -1319,7 +1293,7 @@ usb3_phy1: phy@4a084400 { <0x4a084800 0x64>, <0x4a084c00 0x40>; reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - ctrl-module = <&omap_control_usb3phy1>; + syscon-phy-power = <&scm_conf 0x370>; clocks = <&usb_phy3_always_on_clk32k>, <&sys_clkin1>, <&usb_otg_ss1_refclk960m>; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index ca3c17fde5a0..b24f37e4003c 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -852,18 +852,6 @@ emif2: emif@4d000000 { hw-caps-temp-alert; }; - omap_control_usb2phy: control-phy@4a002300 { - compatible = "ti,control-phy-usb2"; - reg = <0x4a002300 0x4>; - reg-names = "power"; - }; - - omap_control_usb3phy: control-phy@4a002370 { - compatible = "ti,control-phy-pipe3"; - reg = <0x4a002370 0x4>; - reg-names = "power"; - }; - usb3: omap_dwc3@4a020000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss"; @@ -899,7 +887,7 @@ ocp2scp@4a080000 { usb2_phy: usb2phy@4a084000 { compatible = "ti,omap-usb2"; reg = <0x4a084000 0x7c>; - ctrl-module = <&omap_control_usb2phy>; + syscon-phy-power = <&scm_conf 0x300>; clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; clock-names = "wkupclk", "refclk"; #phy-cells = <0>; @@ -911,7 +899,7 @@ usb3_phy: usb3phy@4a084400 { <0x4a084800 0x64>, <0x4a084c00 0x40>; reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - ctrl-module = <&omap_control_usb3phy>; + syscon-phy-power = <&scm_conf 0x370>; clocks = <&usb_phy_cm_clk32k>, <&sys_clkin>, <&usb_otg_ss_refclk960m>; @@ -967,14 +955,6 @@ bandgap: bandgap@4a0021e0 { #thermal-sensor-cells = <1>; }; - omap_control_sata: control-phy@4a002374 { - compatible = "ti,control-phy-pipe3"; - reg = <0x4a002374 0x4>; - reg-names = "power"; - clocks = <&sys_clkin>; - clock-names = "sysclk"; - }; - /* OCP2SCP3 */ ocp2scp@4a090000 { compatible = "ti,omap-ocp2scp"; @@ -989,7 +969,7 @@ sata_phy: phy@4a096000 { <0x4A096400 0x64>, /* phy_tx */ <0x4A096800 0x40>; /* pll_ctrl */ reg-names = "phy_rx", "phy_tx", "pll_ctrl"; - ctrl-module = <&omap_control_sata>; + syscon-phy-power = <&scm_conf 0x374>; clocks = <&sys_clkin>, <&sata_ref_clk>; clock-names = "sysclk", "refclk"; #phy-cells = <0>; From 05c4ffc3a266f9124d22f8c7af4c747b1539edfc Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 8 Jan 2016 23:50:12 -0600 Subject: [PATCH 16/38] ARM: dts: LogicPD Torpedo: Add MT9P031 Support The Logic PD Torpedo standard kits come with a SOM populated to us an 8-bit parallel camera interface. This patch pin muxes the omap3-isp pins, sets the MT9P031 clicks, and configures the i2c2 bus to communicate with the mt9p031 on address 0x48. I have not done a lot of testing, but when modprobing mt9p031, then omap3-isp, the board responds with MT9P031 detected at address 0x48. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- .../boot/dts/logicpd-torpedo-37xx-devkit.dts | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts index fb13f18c08cc..60831b8973f9 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts @@ -217,6 +217,24 @@ OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* mcbsp4_dx.gpio_154 */ >; }; + isp_pins: pinmux_isp_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x210c, PIN_INPUT | MUX_MODE0) /* cam_hs.cam_hs */ + OMAP3_CORE1_IOPAD(0x210e, PIN_INPUT | MUX_MODE0) /* cam_vs.cam_vs */ + OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0) /* cam_xclka.cam_xclka */ + OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0) /* cam_pclk.cam_pclk */ + + OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE0) /* cam_d0.cam_d0 */ + OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0) /* cam_d1.cam_d1 */ + OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0) /* cam_d2.cam_d2 */ + OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0) /* cam_d3.cam_d3 */ + OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0) /* cam_d4.cam_d4 */ + OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0) /* cam_d5.cam_d5 */ + OMAP3_CORE1_IOPAD(0x2122, PIN_INPUT | MUX_MODE0) /* cam_d6.cam_d6 */ + OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7.cam_d7 */ + >; + }; + dss_dpi_pins1: pinmux_dss_dpi_pins1 { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ @@ -268,6 +286,24 @@ OMAP3_WKUP_IOPAD(0x2a54, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_127 */ }; }; +&i2c2 { + mt9p031@48 { + compatible = "aptina,mt9p031"; + reg = <0x48>; + clocks = <&isp 0>; + vaa-supply = <&vaux4>; + vdd-supply = <&vaux4>; + vdd_io-supply = <&vaux4>; + port { + mt9p031_out: endpoint { + input-clock-frequency = <24000000>; + pixel-clock-frequency = <72000000>; + remote-endpoint = <&ccdc_ep>; + }; + }; + }; +}; + &i2c3 { touchscreen: tsc2004@48 { compatible = "ti,tsc2004"; @@ -289,6 +325,23 @@ touchscreen: tsc2004@48 { }; }; +&isp { + pinctrl-names = "default"; + pinctrl-0 = <&isp_pins>; + ports { + port@0 { + reg = <0>; + ccdc_ep: endpoint { + remote-endpoint = <&mt9p031_out>; + bus-width = <8>; + hsync-active = <1>; + vsync-active = <1>; + pclk-sample = <0>; + }; + }; + }; +}; + &uart1 { interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; }; From 5e3447a29a3811c4eba677c0cc559ce81ae6f0d7 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 9 Jan 2016 11:01:11 -0600 Subject: [PATCH 17/38] ARM: dts: LogicPD Torpedo: Add AT24 EEPROM Support The Wireless version of the SOM uses an AT24 EEPROM to store product ID. The EEPROM is readonly. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/logicpd-torpedo-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi index 7fed0bd4f3de..2e4fe3f182c2 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi @@ -118,6 +118,11 @@ &i2c2 { &i2c3 { clock-frequency = <400000>; + at24@50 { + compatible = "at24,24c02"; + readonly; + reg = <0x50>; + }; }; /* From 59d2c40c45dfb89686940480eb9efb05e7556fe5 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 11 Jan 2016 17:07:11 -0600 Subject: [PATCH 18/38] ARM: dts: LogicPD Torpedo: Fix Panel Sleep Setup regulator and fix pin muxing to allow Panel to sleep and wake from sleep for some low power improvements. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- .../boot/dts/logicpd-torpedo-37xx-devkit.dts | 70 ++++++++++++------- 1 file changed, 43 insertions(+), 27 deletions(-) diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts index 60831b8973f9..f926eaa990d6 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts @@ -111,6 +111,7 @@ &vpll2 { &dss { status = "ok"; vdds_dsi-supply = <&vpll2>; + vdda_video-supply = <&video_reg>; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins1>; port { @@ -126,13 +127,22 @@ aliases { display0 = &lcd0; }; + video_reg: video_reg { + pinctrl-names = "default"; + pinctrl-0 = <&panel_pwr_pins>; + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd INI */ + }; + lcd0: display@0 { compatible = "panel-dpi"; label = "15"; status = "okay"; /* default-on; */ pinctrl-names = "default"; - enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd INI */ port { lcd_in: endpoint { @@ -162,8 +172,8 @@ bl: backlight { pinctrl-names = "default"; pinctrl-0 = <&backlight_pins>; - gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>, /* gpio_56 */ - <&gpio5 26 GPIO_ACTIVE_HIGH>; /* gpio_154 */ + gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>, /* gpio_154 */ + <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio_56 */ default-on; }; }; @@ -212,8 +222,8 @@ OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ backlight_pins: pinmux_backlight_pins { pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs5.gpio_56 */ - OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* mcbsp4_dx.gpio_154 */ + OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* gpmc_ncs5.gpio_56 */ + OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_dx.gpio_154 */ >; }; @@ -235,32 +245,38 @@ OMAP3_CORE1_IOPAD(0x2124, PIN_INPUT | MUX_MODE0) /* cam_d7.cam_d7 */ >; }; + panel_pwr_pins: pinmux_panel_pwr_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ + >; + }; + dss_dpi_pins1: pinmux_dss_dpi_pins1 { pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ - OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data17.dss_data17 */ - OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ - OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ - OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ - OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ - OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ - OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data18.dss_data0 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data19.dss_data1 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data20.dss_data2 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data21.dss_data3 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data22.dss_data4 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* dss_data23.dss_data5 */ >; }; }; From 40d5cb207e69718ef25f4463c53a1332d7663ce8 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 11 Jan 2016 22:57:58 -0600 Subject: [PATCH 19/38] ARM: dts: LogicPD Torpedo: Add SPI EEPROM The devkit has an AT25 EEPROM on MCSPI1. Enable this with default parameters. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts | 14 ++++++++++++++ arch/arm/boot/dts/logicpd-torpedo-som.dtsi | 14 ++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts index f926eaa990d6..703ced2adcca 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts @@ -341,6 +341,20 @@ touchscreen: tsc2004@48 { }; }; +&mcspi1 { + at25@0 { + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpha; + spi-cpol; + + pagesize = <64>; + size = <32768>; + address-width = <16>; + }; +}; + &isp { pinctrl-names = "default"; pinctrl-0 = <&isp_pins>; diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi index 2e4fe3f182c2..8b157bedf570 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi @@ -179,6 +179,15 @@ OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ >; }; + mcspi1_pins: pinmux_mcspi1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + >; + }; + }; &uart2 { @@ -187,6 +196,11 @@ &uart2 { pinctrl-0 = <&uart2_pins>; }; +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; +}; + &omap3_pmx_core2 { mmc3_core2_pins: pinmux_mmc3_core2_pins { pinctrl-single,pins = < From 3bec8c81fc8e9dfb74c1c4ec7499013fdeb80c76 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Sun, 17 Jan 2016 16:49:06 +0100 Subject: [PATCH 20/38] ARM: dts: OMAP3-N950-N9: Enable SSI module The Nokia N950 and Nokia N9 have a modem attached to their first ssi port. This change adds all necessary information to initialize the SSI module, but does not yet add the modem information. Signed-off-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-n950-n9.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index ab1174bb409e..e89a40e10948 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -59,6 +59,19 @@ OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE4) /* gpio 35 - wlan enable */ OMAP3_CORE1_IOPAD(0x208a, PIN_INPUT | MUX_MODE4) /* gpio 42 - wlan irq */ >; }; + + ssi_pins: pinmux_ssi_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE1) /* ssi1_dat_tx */ + OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE1) /* ssi1_flag_tx */ + OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE1) /* ssi1_rdy_tx */ + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */ + OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE1) /* ssi1_dat_rx */ + OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE1) /* ssi1_flag_rx */ + OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ + OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ + >; + }; }; &i2c1 { @@ -206,3 +219,14 @@ partition@6 { }; }; }; + +&ssi_port1 { + pinctrl-names = "default"; + pinctrl-0 = <&ssi_pins>; + + ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ +}; + +&ssi_port2 { + status = "disabled"; +}; From f21b98739311b50d908681d192ed506e1224ada1 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Sun, 17 Jan 2016 16:49:09 +0100 Subject: [PATCH 21/38] ARM: dts: OMAP3-N950-N9: Enable modem The Nokia N950 and Nokia N9 have a modem attached to their first ssi port. This change adds the modem to the SSI port. Signed-off-by: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-n9.dts | 4 +++ arch/arm/boot/dts/omap3-n950-n9.dtsi | 40 ++++++++++++++++++++++++++++ arch/arm/boot/dts/omap3-n950.dts | 4 +++ 3 files changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts index f2e213931e09..5c67429a4da7 100644 --- a/arch/arm/boot/dts/omap3-n9.dts +++ b/arch/arm/boot/dts/omap3-n9.dts @@ -53,3 +53,7 @@ csi2a_ep: endpoint { }; }; }; + +&modem { + compatible = "nokia,n9-modem"; +}; diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index e89a40e10948..702062e88e14 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -72,6 +72,22 @@ OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE1) /* ssi1_rdy_rx */ OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ >; }; + + modem_pins1: pinmux_modem_core1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio_34 (ape_rst_rq) */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE4) /* gpio_88 (cmt_rst_rq) */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE4) /* gpio_93 (cmt_apeslpx) */ + >; + }; +}; + +&omap3_pmx_core2 { + modem_pins2: pinmux_modem_core2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25ec, PIN_OUTPUT | MUX_MODE4) /* gpio_23 (cmt_en) */ + >; + }; }; &i2c1 { @@ -225,6 +241,30 @@ &ssi_port1 { pinctrl-0 = <&ssi_pins>; ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ + + modem: hsi-client { + pinctrl-names = "default"; + pinctrl-0 = <&modem_pins1 &modem_pins2>; + + hsi-channel-ids = <0>, <1>, <2>, <3>; + hsi-channel-names = "mcsaab-control", + "speech-control", + "speech-data", + "mcsaab-data"; + hsi-speed-kbps = <96000>; + hsi-mode = "frame"; + hsi-flow = "synchronized"; + hsi-arb-mode = "round-robin"; + + interrupts-extended = <&gpio2 2 IRQ_TYPE_EDGE_RISING>; /* gpio 34 */ + + gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>, /* gpio 93 */ + <&gpio3 24 GPIO_ACTIVE_HIGH>, /* gpio 88 */ + <&gpio1 23 GPIO_ACTIVE_HIGH>; /* gpio 23 */ + gpio-names = "cmt_apeslpx", + "cmt_rst_rq", + "cmt_en"; + }; }; &ssi_port2 { diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts index e5967262f28b..7f219a9dc5be 100644 --- a/arch/arm/boot/dts/omap3-n950.dts +++ b/arch/arm/boot/dts/omap3-n950.dts @@ -82,3 +82,7 @@ wlcore: wlcore@0 { vwlan-supply = <&vwlan_fixed>; }; }; + +&modem { + compatible = "nokia,n950-modem"; +}; From b4cc2b75ed1d4cf71c74c23d49e8d75d77a96405 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 17 Jan 2016 17:53:48 -0600 Subject: [PATCH 22/38] ARM: dts: LogicPD Torpedo: Set HSUSB0 Pin Mux This patch defines the pin muxing to configure the hsusb0 through the twl4030 PMIC, because we can't always assume the bootloader will do it correctly. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- .../arm/boot/dts/logicpd-torpedo-37xx-devkit.dts | 2 ++ arch/arm/boot/dts/logicpd-torpedo-som.dtsi | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts index 703ced2adcca..874ce46cdc0a 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts @@ -378,6 +378,8 @@ &uart1 { /* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ &usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb_otg_pins>; interface-type = <0>; usb-phy = <&usb2_phy>; phys = <&usb2_phy>; diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi index 8b157bedf570..2eca34c5239e 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi @@ -187,7 +187,23 @@ OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_so OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ >; }; + hsusb_otg_pins: pinmux_hsusb_otg_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ + OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ + OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ + OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ + OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ + OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ + OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ + OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ + OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ + OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ + OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ + OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ + >; + }; }; &uart2 { From 8d289cc6237449bb9c26774893fc2cfcb1455fa3 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Sat, 16 Jan 2016 11:51:10 +0100 Subject: [PATCH 23/38] ARM: dts: igep00x0: Specify the device to be used for boot console output. UART3 device is the device to be used for boot console output. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-igep.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index 3caf062f882c..4fc7e0f74e76 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi @@ -18,6 +18,10 @@ memory { reg = <0x80000000 0x20000000>; /* 512 MB */ }; + chosen { + stdout-path = &uart3; + }; + sound { compatible = "ti,omap-twl4030"; ti,model = "igep2"; From 7911fc439b5e77f054e5280e5a2f015931bb0293 Mon Sep 17 00:00:00 2001 From: Pau Pajuel Date: Sat, 16 Jan 2016 11:51:11 +0100 Subject: [PATCH 24/38] ARM: dts: omap3-igep0030-common: Add USB Host support Provide RESET GPIO for the USB PHY, the USB Host port mode and the PHY device for the controller. Also provides pin multiplexer information for USB host pins. Signed-off-by: Pau Pajuel Signed-off-by: Enric Balletbo i Serra Reviewed-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-igep0030-common.dtsi | 41 ++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/omap3-igep0030-common.dtsi index 640f06603966..63f8b9a2f3af 100644 --- a/arch/arm/boot/dts/omap3-igep0030-common.dtsi +++ b/arch/arm/boot/dts/omap3-igep0030-common.dtsi @@ -33,9 +33,28 @@ user2 { default-state = "off"; }; }; + + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ + }; }; &omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_pins>; + + hsusb2_pins: pinmux_hsusb2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; + uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ @@ -47,6 +66,20 @@ OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ }; &omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_core2_pins>; + + hsusb2_core2_pins: pinmux_hsusb2_core2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; + leds_core2_pins: pinmux_leds_core2_pins { pinctrl-single,pins = < OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ @@ -54,6 +87,14 @@ OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ }; }; +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; From 01c37be40fc35137a8b97e5176017958d57e401c Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Sat, 16 Jan 2016 11:51:12 +0100 Subject: [PATCH 25/38] ARM: dts: am335x-sl50: Specify the device to be used for boot console output. UART0 device is the device to be used for boot console output. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sl50.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index d38edfa53bb9..9e1dac639fad 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -19,6 +19,10 @@ cpu@0 { }; }; + chosen { + stdout-path = &uart0; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; From b328d9b86d5d22274a48b597f3226a8a21188cbc Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Sat, 16 Jan 2016 11:51:13 +0100 Subject: [PATCH 26/38] ARM: dts: am335x-sl50: Fix audio codec setup. The MCLK is provided by an external clock of 24.576MHz. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sl50.dts | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index 9e1dac639fad..a676869536bc 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -67,12 +67,28 @@ backlight1: disp1 { default-brightness-level = <6>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + /* audio external oscillator */ + tlv320aic3x_mclk: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; /* 24.576MHz */ + }; + }; + sound { compatible = "ti,da830-evm-audio"; ti,model = "AM335x-SL50"; ti,audio-codec = <&audio_codec>; ti,mcasp-controller = <&mcasp0>; - ti,codec-clock-rate = <12000000>; + + clocks = <&tlv320aic3x_mclk>; + clock-names = "mclk"; + ti,audio-routing = "Headphone Jack", "HPLOUT", "Headphone Jack", "HPROUT", @@ -230,7 +246,7 @@ AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahcl AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ - AM33XX_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ + AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2 */ >; }; From 60fca6b2fdac8d8463799b2c9b0d36845864ed99 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Sun, 31 Jan 2016 01:52:37 +0100 Subject: [PATCH 27/38] ARM: dts: OMAP3-N950-N9: Add ssi idle pinctrl state This adds an idle pinctrl state, which will be used by the driver to avoid incoming data during clock rate changes or data flushing. Signed-off-By: Sebastian Reichel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-n950-n9.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index 702062e88e14..858a25048102 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -73,6 +73,19 @@ OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE1) /* ssi1_wake */ >; }; + ssi_pins_idle: pinmux_ssi_pins_idle { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE7) /* ssi1_dat_tx */ + OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE7) /* ssi1_flag_tx */ + OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLDOWN | MUX_MODE7) /* ssi1_rdy_tx */ + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */ + OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT | MUX_MODE7) /* ssi1_dat_rx */ + OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE7) /* ssi1_flag_rx */ + OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | MUX_MODE4) /* ssi1_rdy_rx */ + OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | MUX_MODE7) /* ssi1_wake */ + >; + }; + modem_pins1: pinmux_modem_core1_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x207a, PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio_34 (ape_rst_rq) */ @@ -237,8 +250,9 @@ partition@6 { }; &ssi_port1 { - pinctrl-names = "default"; + pinctrl-names = "default", "idle"; pinctrl-0 = <&ssi_pins>; + pinctrl-1 = <&ssi_pins_idle>; ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */ From 61bd7896520df15bc6bb57fe861f35cc6ad0e075 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Thu, 4 Feb 2016 14:18:02 +0200 Subject: [PATCH 28/38] ARM: dts: remove deprecated property dwc3 DWC3's tx-fifo-resize property has been deprecated because of it being unnecessary to any HW other than OMAP5 ES1.0. Signed-off-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 3 --- arch/arm/boot/dts/dra74x.dtsi | 1 - arch/arm/boot/dts/omap5.dtsi | 1 - 3 files changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 3d1426b799c2..e2a90aa78e14 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1324,7 +1324,6 @@ usb1: usb@48890000 { "otg"; phys = <&usb2_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; - tx-fifo-resize; maximum-speed = "super-speed"; dr_mode = "otg"; snps,dis_u3_susphy_quirk; @@ -1352,7 +1351,6 @@ usb2: usb@488d0000 { "otg"; phys = <&usb2_phy2>; phy-names = "usb2-phy"; - tx-fifo-resize; maximum-speed = "high-speed"; dr_mode = "otg"; snps,dis_u3_susphy_quirk; @@ -1380,7 +1378,6 @@ usb3: usb@48910000 { interrupt-names = "peripheral", "host", "otg"; - tx-fifo-resize; maximum-speed = "high-speed"; dr_mode = "otg"; snps,dis_u3_susphy_quirk; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 8bcc47db1cd1..4220eeffc65a 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -76,7 +76,6 @@ usb4: usb@48950000 { interrupt-names = "peripheral", "host", "otg"; - tx-fifo-resize; maximum-speed = "high-speed"; dr_mode = "otg"; }; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index b24f37e4003c..38805ebbe2ba 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -873,7 +873,6 @@ dwc3@4a030000 { phys = <&usb2_phy>, <&usb3_phy>; phy-names = "usb2-phy", "usb3-phy"; dr_mode = "peripheral"; - tx-fifo-resize; }; }; From 97749fecef39e80fa2d42f949b2ee3d025e738a5 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 8 Feb 2016 14:46:28 +0530 Subject: [PATCH 29/38] ARM: dts: DRA7: Add DSPEVE thermal data This patch changes a dtsi file to contain the thermal data for DSPEVE domain. This data will enable a thermal shutdown at 125C. Signed-off-by: Keerthy Acked-by: Eduardo Valentin Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-dspeve-thermal.dtsi | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 arch/arm/boot/dts/dra7-dspeve-thermal.dtsi diff --git a/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi b/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi new file mode 100644 index 000000000000..1c39a8459b39 --- /dev/null +++ b/arch/arm/boot/dts/dra7-dspeve-thermal.dtsi @@ -0,0 +1,27 @@ +/* + * Device Tree Source for DRA7x SoC DSPEVE thermal + * + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include + +dspeve_thermal: dspeve_thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&bandgap 3>; + + trips { + dspeve_crit: dspeve_crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; From 7a28936cdcb8ebc0150e564a3bf67b6bfdfd1e6c Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 8 Feb 2016 14:46:29 +0530 Subject: [PATCH 30/38] ARM: dts: DRA7: Add IVA thermal data This patch changes a dtsi file to contain the thermal data for IVA domain. This data will enable a thermal shutdown at 125C. Signed-off-by: Keerthy Acked-by: Eduardo Valentin Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-iva-thermal.dtsi | 27 +++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 arch/arm/boot/dts/dra7-iva-thermal.dtsi diff --git a/arch/arm/boot/dts/dra7-iva-thermal.dtsi b/arch/arm/boot/dts/dra7-iva-thermal.dtsi new file mode 100644 index 000000000000..dd74a5337d1f --- /dev/null +++ b/arch/arm/boot/dts/dra7-iva-thermal.dtsi @@ -0,0 +1,27 @@ +/* + * Device Tree Source for DRA7x SoC IVA thermal + * + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include + +iva_thermal: iva_thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&bandgap 4>; + + trips { + iva_crit: iva_crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; From 667f259951c2877a1fe45c0bf569f13b83f118e6 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 8 Feb 2016 14:46:30 +0530 Subject: [PATCH 31/38] ARM: dts: DRA7: Add missing IVA and DSPEVE thermal domain data OMAP5 has 3 thermal zones cpu, core and multimedia. On the other hand DRA7 has 5 thermal zones cpu, gpu, core, dspeve and iva. Currently cpu, core and multimedia are being added via device tree and the other 2 are getting added via kernel. Add the missing thermal domains in device tree so we can create the zones with the appropriate trip numbers, type and temperatures. Signed-off-by: Keerthy Acked-by: Eduardo Valentin Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index e2a90aa78e14..8ea153aa46f6 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1567,6 +1567,8 @@ thermal_zones: thermal-zones { #include "omap4-cpu-thermal.dtsi" #include "omap5-gpu-thermal.dtsi" #include "omap5-core-thermal.dtsi" + #include "dra7-dspeve-thermal.dtsi" + #include "dra7-iva-thermal.dtsi" }; }; From 69101b203590adb9a39ecad7b6789cca5eed2638 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Fri, 19 Feb 2016 10:08:54 +0530 Subject: [PATCH 32/38] ARM: dts: am43x-epos-evm: Add the am438 compatible string The SoCs on am43x-epos-evm are named am438x. Hence add the compatibility string and remove the am4372 string. Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/arm/omap/omap.txt | 2 +- arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index a2bd593881ca..739bc48aa255 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -154,7 +154,7 @@ Boards: compatible = "compulab,am437x-sbc-t43", "compulab,am437x-cm-t43", "ti,am4372", "ti,am43" - AM43x EPOS EVM - compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43" + compatible = "ti,am43x-epos-evm", "ti,am43", "ti,am438x" - AM437x GP EVM compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43" diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 746fd2b17958..a67cfc108819 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -18,7 +18,7 @@ / { model = "TI AM43x EPOS EVM"; - compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43"; + compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43"; aliases { display0 = &lcd0; From 05cf1e030b7860f2e8b729d8197c5992ce12977e Mon Sep 17 00:00:00 2001 From: Ivaylo Dimitrov Date: Mon, 22 Feb 2016 16:42:59 +0200 Subject: [PATCH 33/38] ARM: dts: omap3-n900: Allow gpio keys to be disabled Add linux,can-disable; to all gpios exported from gpio-keys driver, so userspace can disable them Signed-off-by: Ivaylo Dimitrov Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-n900.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 20603f3f9bd0..2ae38dfea61e 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -68,6 +68,7 @@ camera_lens_cover { linux,input-type = <5>; /* EV_SW */ linux,code = <0x09>; /* SW_CAMERA_LENS_COVER */ wakeup-source; + linux,can-disable; }; camera_focus { @@ -75,6 +76,7 @@ camera_focus { gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */ linux,code = <0x210>; /* KEY_CAMERA_FOCUS */ wakeup-source; + linux,can-disable; }; camera_capture { @@ -82,6 +84,7 @@ camera_capture { gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */ linux,code = <0xd4>; /* KEY_CAMERA */ wakeup-source; + linux,can-disable; }; lock_button { @@ -89,6 +92,7 @@ lock_button { gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */ linux,code = <0x98>; /* KEY_SCREENLOCK */ wakeup-source; + linux,can-disable; }; keypad_slide { @@ -97,6 +101,7 @@ keypad_slide { linux,input-type = <5>; /* EV_SW */ linux,code = <0x0a>; /* SW_KEYPAD_SLIDE */ wakeup-source; + linux,can-disable; }; proximity_sensor { @@ -104,6 +109,7 @@ proximity_sensor { gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */ linux,input-type = <5>; /* EV_SW */ linux,code = <0x0b>; /* SW_FRONT_PROXIMITY */ + linux,can-disable; }; }; From 730d7dcf03c0f276fc6435e69df75dacd57b55c7 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 17 Feb 2016 18:30:12 -0600 Subject: [PATCH 34/38] ARM: dts: omap3logic: Add PWM-Backlight The backlight pin is shared with Timer 10 PWM. This patch allows the pwm_bl driver to enable the pwm run by this timer to dim the backlight. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- .../boot/dts/logicpd-torpedo-37xx-devkit.dts | 26 ++++++++++++++----- 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts index 874ce46cdc0a..6cbcce26eaca 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts @@ -71,6 +71,15 @@ led2 { linux,default-trigger = "none"; }; }; + + pwm10: dmtimer-pwm@10 { + compatible = "ti,omap-dmtimer-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + ti,timers = <&timer10>; + #pwm-cells = <3>; + }; + }; &vaux1 { @@ -168,13 +177,13 @@ panel-timing { }; bl: backlight { - compatible = "gpio-backlight"; + compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&backlight_pins>; - - gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>, /* gpio_154 */ - <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio_56 */ - default-on; + pwms = <&pwm10 0 5000000 0>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <7>; + enable-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; /* gpio_154 */ }; }; @@ -196,6 +205,12 @@ OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLUP | MUX_MODE4) /* mcspi2_cs0.gpio_181 * >; }; + pwm_pins: pinmux_pwm_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE3) /* gpmc_ncs5.gpt_10_pwm_evt */ + >; + }; + led_pins: pinmux_led_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21d8, PIN_OUTPUT | MUX_MODE4) /* gpio_179 */ @@ -222,7 +237,6 @@ OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ backlight_pins: pinmux_backlight_pins { pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x20B8, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* gpmc_ncs5.gpio_56 */ OMAP3_CORE1_IOPAD(0x2188, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_dx.gpio_154 */ >; }; From ab8dd3aed01130c4e08313276d09b47e3eb40e4b Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 20 Feb 2016 01:27:52 -0600 Subject: [PATCH 35/38] ARM: DTS: Add minimal Support for Logic PD DM3730 SOM-LV The Logic PD DM37xx SOM-LV devkit consists of a base board and a SOM. While the SOM (System on Module) supports Bluetooth and WiFi, LPD did not obtain an FCC ID, so anyone who uses it will have to go through certification. I have only tested the Type 28 Display, SMSC9211 Ethernet, SD/MMC and basic power management, however the overall current seems high. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- .../boot/dts/logicpd-som-lv-37xx-devkit.dts | 268 ++++++++++++++++++ arch/arm/boot/dts/logicpd-som-lv.dtsi | 208 ++++++++++++++ 2 files changed, 476 insertions(+) create mode 100644 arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts create mode 100644 arch/arm/boot/dts/logicpd-som-lv.dtsi diff --git a/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts new file mode 100644 index 000000000000..da8598402ab8 --- /dev/null +++ b/arch/arm/boot/dts/logicpd-som-lv-37xx-devkit.dts @@ -0,0 +1,268 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "omap36xx.dtsi" +#include "logicpd-som-lv.dtsi" +#include "omap-gpmc-smsc9221.dtsi" + +/ { + model = "LogicPD Zoom DM3730 SOM-LV Development Kit"; + compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_pins>; + + sysboot2 { + label = "gpio3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* gpio_111 / uP_GPIO_3 */ + linux,code = ; + wakeup-source; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3logic"; + ti,mcbsp = <&mcbsp2>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins &led_pins_wkup>; + + led1 { + label = "led1"; + gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; /* gpio133 */ + linux,default-trigger = "cpu0"; + }; + + led2 { + label = "led2"; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* gpio11 */ + linux,default-trigger = "none"; + }; + }; +}; + +&vaux1 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +&vaux4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&mcbsp2 { + status = "okay"; +}; + +&charger { + ti,bb-uvolt = <3200000>; + ti,bb-uamp = <150>; +}; + +&gpmc { + ranges = <1 0 0x08000000 0x1000000>; /* CS1: 16MB for LAN9221 */ + + ethernet@gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&lan9221_pins>; + interrupt-parent = <&gpio5>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; /* gpio_152 */ + reg = <1 0 0xff>; + }; +}; + +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "ok"; + vdds_dsi-supply = <&vpll2>; + vdda_video-supply = <&video_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins1>; + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <16>; + }; + }; +}; + +/ { + aliases { + display0 = &lcd0; + }; + + video_reg: video_reg { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + lcd0: display@0 { + compatible = "panel-dpi"; + label = "28"; + status = "okay"; + /* default-on; */ + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_pin>; + enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd INI */ + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + panel-timing { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <3>; + hback-porch = <2>; + hsync-len = <42>; + vback-porch = <3>; + vfront-porch = <2>; + vsync-len = <11>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + + bl: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + pwms = <&twl_pwm 0 5000000>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <7>; + enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* gpio_8 */ + }; +}; + +&mmc1 { + interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins &mmc1_cd>; + wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ + cd-gpios = <&gpio4 14 IRQ_TYPE_LEVEL_LOW>; /* gpio_110 */ + vmmc-supply = <&vmmc1>; + bus-width = <4>; + cap-power-off-card; +}; + +&omap3_pmx_core { + gpio_key_pins: pinmux_gpio_key_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x212e, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_xclkb.gpio_111 / uP_GPIO_3*/ + >; + }; + + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x215e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* sdmmc2_dat1.gpio_133 / uP_GPIO_0 */ + >; + }; + + lan9221_pins: pinmux_lan9221_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + OMAP3_CORE1_IOPAD(0x2132, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_strobe.gpio_126 sdmmc1_wp*/ + >; + }; + + lcd_enable_pin: pinmux_lcd_enable_pin { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x218a, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* mcbsp4_fs.gpio_155 */ + >; + }; + + dss_dpi_pins1: pinmux_dss_dpi_pins1 { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_acbias.dss_acbias */ + + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT_PULLDOWN | PIN_OFF_OUTPUT_LOW | MUX_MODE0) /* dss_data15.dss_data15 */ + >; + }; +}; + +&omap3_pmx_wkup { + led_pins_wkup: pinmux_led_pins_wkup { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a24, PIN_OUTPUT_PULLUP | MUX_MODE4) /* jtag_emu0.gpio_11 / uP_GPIO_1 */ + >; + }; + + backlight_pins: pinmux_backlight_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | PIN_OFF_OUTPUT_LOW | MUX_MODE4) /* sys_boot6.gpio_8 */ + >; + }; + + mmc1_cd: pinmux_mmc1_cd { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x212c, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d11.gpio_110 */ + >; + }; +}; + + +&uart1 { + interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; +}; + +/* Wired to the tps65950 on the SOM, only the USB connector is on the devkit */ +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb_otg_pins>; + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi new file mode 100644 index 000000000000..aa9572bd930a --- /dev/null +++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi @@ -0,0 +1,208 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + wl12xx_vmmc: wl12xx_vmmc { + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 3 0>; /* gpio_3 */ + startup-delay-us = <70000>; + enable-active-high; + vin-supply = <&vmmc2>; + }; +}; + +&gpmc { + ranges = <0 0 0x00000000 0x1000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + linux,mtd-name = "micron,mt29f4g16abbda3w"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + nand-bus-width = <16>; + ti,nand-ecc-opt = "bch8"; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,device-width = <2>; + + gpmc,page-burst-access-ns = <5>; + gpmc,cycle2cycle-delay-ns = <50>; + + #address-cells = <1>; + #size-cells = <1>; + + /* u-boot uses mtdparts=omap2-nand.0:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs) */ + + x-loader@0 { + label = "x-loader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "u-boot"; + reg = <0x80000 0x1e0000>; + }; + + bootloaders_env@260000 { + label = "u-boot-env"; + reg = <0x260000 0x20000>; + }; + + kernel@280000 { + label = "kernel"; + reg = <0x280000 0x400000>; + }; + + filesystem@680000 { + label = "fs"; + reg = <0x680000 0>; /* 0 = MTDPART_SIZ_FULL */ + }; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; +}; + +&mmc3 { + interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>; + pinctrl-0 = <&mmc3_pins>; + pinctrl-names = "default"; + vmmc-supply = <&wl12xx_vmmc>; + non-removable; + bus-width = <4>; + cap-power-off-card; + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1273"; + reg = <2>; + interrupt-parent = <&gpio5>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */ + ref-clock-frequency = <26000000>; + }; +}; + +&omap3_pmx_core { + mmc3_pins: pinmux_mm3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */ + OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */ + OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */ + OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */ + OMAP3_CORE1_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ + OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */ + OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */ + >; + }; + mcbsp2_pins: pinmux_mcbsp2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ + OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ + OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ + OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ + >; + }; + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */ + >; + }; + mcspi1_pins: pinmux_mcspi1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + >; + }; + hsusb_otg_pins: pinmux_hsusb_otg_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ + OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ + OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */ + OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */ + OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */ + OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */ + OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */ + OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */ + OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */ + OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */ + OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ + OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ + >; + }; +}; + +&uart2 { + interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&twl { + twl_power: power { + compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle"; + ti,use_poweroff; + }; +}; + +&twl_gpio { + ti,use-leds; +}; From 97d7f2ff38f54896ff38e468bd2b77c8a5a38761 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 21 Feb 2016 12:06:48 +0100 Subject: [PATCH 36/38] ARM: dts: n900: Use linux input defines instead hardcoded constants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes DTS structure more readable. Signed-off-by: Pali Rohár Acked-By: Sebastian Reichel Acked-by: Pavel Machek Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-n900.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 74d8f7eb5563..e2a629f06a05 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -65,45 +65,45 @@ gpio_keys { camera_lens_cover { label = "Camera Lens Cover"; gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* 110 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0x09>; /* SW_CAMERA_LENS_COVER */ + linux,input-type = ; + linux,code = ; wakeup-source; }; camera_focus { label = "Camera Focus"; gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* 68 */ - linux,code = <0x210>; /* KEY_CAMERA_FOCUS */ + linux,code = ; wakeup-source; }; camera_capture { label = "Camera Capture"; gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; /* 69 */ - linux,code = <0xd4>; /* KEY_CAMERA */ + linux,code = ; wakeup-source; }; lock_button { label = "Lock Button"; gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* 113 */ - linux,code = <0x98>; /* KEY_SCREENLOCK */ + linux,code = ; wakeup-source; }; keypad_slide { label = "Keypad Slide"; gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; /* 71 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0x0a>; /* SW_KEYPAD_SLIDE */ + linux,input-type = ; + linux,code = ; wakeup-source; }; proximity_sensor { label = "Proximity Sensor"; gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; /* 89 */ - linux,input-type = <5>; /* EV_SW */ - linux,code = <0x0b>; /* SW_FRONT_PROXIMITY */ + linux,input-type = ; + linux,code = ; }; }; From 89077c7145c377ce2f90000607bfb41b6e416e7a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 21 Feb 2016 08:01:04 -0600 Subject: [PATCH 37/38] ARM: dts: Add HSUSB2 EHCI Support to Logic PD DM37xx SOM-LV The Logic PD SOM-LV has a USB Host Controller connected to 3-port hub. This enables the pin muxing for the host controller and ehci-phy. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/logicpd-som-lv.dtsi | 57 +++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm/boot/dts/logicpd-som-lv.dtsi b/arch/arm/boot/dts/logicpd-som-lv.dtsi index aa9572bd930a..365f39ff58bb 100644 --- a/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi @@ -23,6 +23,12 @@ wl12xx_vmmc: wl12xx_vmmc { enable-active-high; vin-supply = <&vmmc2>; }; + + /* HS USB Host PHY on PORT 1 */ + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */ + }; }; &gpmc { @@ -126,7 +132,19 @@ wlcore: wlcore@2 { }; }; +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + + &omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_pins>; + mmc3_pins: pinmux_mm3_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */ @@ -164,6 +182,18 @@ OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_so OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ >; }; + + hsusb2_pins: pinmux_hsusb2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; + hsusb_otg_pins: pinmux_hsusb_otg_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ @@ -180,6 +210,33 @@ OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */ OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */ >; }; + + +}; + +&omap3_pmx_wkup { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_reset_pin>; + hsusb2_reset_pin: pinmux_hsusb1_reset_pin { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb2_2_pins>; + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; }; &uart2 { From b9d3ec1d98c658226606e66e55c940491447e617 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 22 Feb 2016 10:51:07 -0600 Subject: [PATCH 38/38] ARM: dts: am57xx-beagle-x15: Add eeprom information Add EEPROM at 0x50 that describes the board configuration. This is useful for userspace programs that may need to check board revision and other similar information. Signed-off-by: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am57xx-beagle-x15.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts index 36c0fa6c362a..50312f80b972 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts @@ -591,6 +591,11 @@ tlv320aic3104: tlv320aic3104@18 { DRVDD-supply = <&vdd_3v3>; DVDD-supply = <&aic_dvdd>; }; + + eeprom: eeprom@50 { + compatible = "at,24c32"; + reg = <0x50>; + }; }; &i2c3 {