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Hi ! This PR adds the [scale nvcc compiler](https://docs.scale-lang.com/stable/) to the CE live site for both AMD and Nvidia backends It works locally and shows host asm, device LLVMIR and: - PTX ans SASS for Nvidia backend, - AMDGPU code for AMD backend. There is a bug in scale 1.7.1 that prevents the compilation with both `-S, -o` flags. As a result I had to make some temp workarounds. For Nvidia backend, PTX is written in the device `.s` file. I run it through `ptax` and `nvidasm` to get the SASS. To get the LLVMIR, I decode the device `.bc` file with `llvm-dis`. For AMD backend, the `.s` file is the AMDGPU code, and the LLVMIR is obtained the same way. I plan to make the `.ts` script closer to say `nvcc.ts` once the flag bugs are fixed in scale. Let me know if there is anything I missed for the live site integration. infra PR: https://github.com/compiler-explorer/infra/pull/2191 Issue: https://github.com/compiler-explorer/compiler-explorer/issues/8865 I acknowledge the use of generative AI to help drafting the code of this PR. --------- Co-authored-by: mattgodbolt-molty <mattgodbolt-molty@users.noreply.github.com> Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
285 lines
12 KiB
TypeScript
285 lines
12 KiB
TypeScript
// Copyright (c) 2026, Compiler Explorer Authors
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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import * as fs from 'node:fs/promises';
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import Path from 'node:path';
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import _ from 'underscore';
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import type {CompilationInfo, CompilationResult} from '../../types/compilation/compilation.interfaces.js';
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import type {PreliminaryCompilerInfo} from '../../types/compiler.interfaces.js';
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import type {ParseFiltersAndOutputOptions} from '../../types/features/filters.interfaces.js';
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import {unwrap} from '../assert.js';
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import {BaseCompiler} from '../base-compiler.js';
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import {CompilationEnvironment} from '../compilation-env.js';
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import {logger} from '../logger.js';
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import {AmdgpuAsmParser} from '../parsers/asm-parser-amdgpu.js';
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import {ClangParser} from './argument-parsers.js';
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interface ExecResult {
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code: number;
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stdout: string;
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stderr: string;
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}
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export class ScaleNvccAMDCompiler extends BaseCompiler {
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static get key() {
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return 'scale-nvcc-amd';
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}
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amdgpuAsmParser: AmdgpuAsmParser;
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constructor(info: PreliminaryCompilerInfo, env: CompilationEnvironment) {
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super(info, env);
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this.compiler.supportsOptOutput = true;
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this.compiler.supportsDeviceAsmView = true;
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this.amdgpuAsmParser = new AmdgpuAsmParser();
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}
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override optionsForFilter(filters: ParseFiltersAndOutputOptions, outputFilename: string) {
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const opts = ['-g', '-lineinfo', '--keep-device-functions'];
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if (!filters.execute) {
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opts.push('-keep', '-keep-dir', Path.dirname(outputFilename));
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if (!filters.binary) {
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opts.push('-Xcompiler=-S');
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}
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}
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return opts;
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}
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override getArgumentParserClass() {
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return ClangParser;
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}
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override optOutputRequested(options: string[]) {
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return (
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super.optOutputRequested(options) ||
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options.includes('--optimization-info') ||
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options.includes('-opt-info')
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);
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}
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//Helpers to get device cpdes (bc and .s)
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private static readonly scaleDeviceFileRe = /-cuda-amdgcn-amd-amdhsa-scale-(gfx[^./]+)\.s$/;
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private static readonly scaleDeviceBcFileRe = /-cuda-amdgcn-amd-amdhsa-scale-(gfx[^./]+)\.bc$/;
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// Temp workaround since -o -S does not work in scale-1.7.1
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// Side effect: it works only if one device file is present.
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// will be cleaned when scale's bug is fixed
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private async findHostAsmFile(dirPath: string): Promise<string | null> {
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try {
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const files = await fs.readdir(dirPath);
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const hostFiles = files.filter(f => f.endsWith('.s') && !ScaleNvccAMDCompiler.scaleDeviceFileRe.test(f));
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if (hostFiles.length !== 1) {
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return null;
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}
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return Path.join(dirPath, hostFiles[0]);
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} catch {
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return null;
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}
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}
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override async postProcess(result, outputFilename: string, filters: ParseFiltersAndOutputOptions) {
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// TEMP (scale support): outputFilename as originally computed may not
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// exist since we no longer pass `-o`. Try to recover the real file.
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if (!filters.binary && result.dirPath) {
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try {
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await fs.stat(outputFilename);
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} catch {
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const hostAsm = await this.findHostAsmFile(result.dirPath);
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if (hostAsm) {
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try {
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result.asmSize = (await fs.stat(hostAsm)).size;
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} catch {
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// leave asmSize as-is; base behaviour reports "no output" below
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}
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outputFilename = hostAsm;
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}
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}
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}
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const maxSize = this.env.ceProps('max-asm-size', 64 * 1024 * 1024);
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const optPromise = result.optPath ? this.processOptOutput(result.optPath) : Promise.resolve([]);
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const postProcess = _.compact(this.compiler.postProcess);
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const asmPromise = (
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filters.binary
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? this.objdump(outputFilename, {}, maxSize, !!filters.intel, !!filters.demangle, false, false, filters)
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: (async () => {
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if (result.asmSize === undefined) {
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result.asm = '<No output file>';
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return result;
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}
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if (result.asmSize >= maxSize) {
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result.asm =
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'<No output: generated assembly was too large' +
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` (${result.asmSize} > ${maxSize} bytes)>`;
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return result;
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}
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if (postProcess.length > 0) {
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return await this.execPostProcess(result, postProcess, outputFilename, maxSize);
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}
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const contents = await fs.readFile(outputFilename, {encoding: 'utf8'});
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result.asm = contents.toString();
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return result;
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})()
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).then(asm => {
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result.asm = typeof asm === 'string' ? asm : asm.asm;
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return result;
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});
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return Promise.all([asmPromise, optPromise, []]);
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}
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// ---- device-code extraction helpers -------------------------------------------------
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/** Pulls the captured arch (e.g. `gfx1100`) out of a scale per-target device filename. */
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private static archFromDeviceFileName(name: string, re: RegExp): string {
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return unwrap(name.match(re))[1];
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}
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private async runLlvmDis(bcPath: string, dirPath: string): Promise<ExecResult> {
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const result = await this.exec(unwrap(this.compiler.llvmDisassembler), [bcPath], {customCwd: dirPath});
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return result;
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}
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private static llvmIrOptions(demangle: boolean) {
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return {
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demangle,
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filterDebugInfo: false,
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filterIRMetadata: false,
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filterAttributes: false,
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filterComments: false,
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};
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}
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/**
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* Handles a single scale/nvcc device `.bc` (LLVM bitcode) file: runs
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* `llvm-dis` to get readable LLVM IR text
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*/
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private async processBcDeviceFile(
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name: string,
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dirPath: string,
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filters: ParseFiltersAndOutputOptions,
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demangle: boolean,
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devices: Record<string, CompilationResult>,
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): Promise<void> {
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const archAndCode = ScaleNvccAMDCompiler.archFromDeviceFileName(name, ScaleNvccAMDCompiler.scaleDeviceBcFileRe);
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const irNameAndArch = `Device LLVM IR (${archAndCode.toLowerCase()})`;
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if (!this.compiler.llvmDisassembler) {
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Object.assign(devices, {
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[irNameAndArch]: await this.postProcessAsm(
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{
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okToCache: false,
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...(await this.llvmIr.process(
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'<error: no llvm-dis found to disassemble bitcode>',
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ScaleNvccAMDCompiler.llvmIrOptions(demangle),
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)),
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},
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{...filters, binary: false},
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),
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});
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return;
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}
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const bcPath = Path.join(dirPath, name);
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const llPath = Path.join(dirPath, `${Path.basename(name, '.bc')}.ll`);
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let irText: string;
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try {
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const disResult = await this.runLlvmDis(bcPath, dirPath);
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irText =
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disResult.code === 0
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? await fs.readFile(llPath, 'utf8')
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: `<llvm-dis failed with code ${disResult.code}>`;
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} catch (err) {
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irText = `<llvm-dis failed: ${err}>`;
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}
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Object.assign(devices, {
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[irNameAndArch]: await this.postProcessAsm(
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{
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okToCache: demangle,
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...(await this.llvmIr.process(irText, ScaleNvccAMDCompiler.llvmIrOptions(demangle))),
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},
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{...filters, binary: false},
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),
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});
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}
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//Get the .s an display it as AMDGPU code, get the .bc and extract llvmir with llvmdis
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override async extractDeviceCode(
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result: CompilationResult,
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filters: ParseFiltersAndOutputOptions,
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compilationInfo: CompilationInfo,
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) {
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const {dirPath} = result;
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const {demangle} = filters;
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const devices: Record<string, CompilationResult> = {...result.devices};
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if (dirPath) {
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const files = await fs.readdir(dirPath);
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const asmDeviceFiles = files.filter(f => ScaleNvccAMDCompiler.scaleDeviceFileRe.test(f));
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const bcDeviceFiles = files.filter(f => ScaleNvccAMDCompiler.scaleDeviceBcFileRe.test(f));
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await Promise.all([
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...asmDeviceFiles.map(async name => {
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try {
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const archAndCode = unwrap(name.match(ScaleNvccAMDCompiler.scaleDeviceFileRe))[1];
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const asm = await fs.readFile(Path.join(dirPath, name), 'utf8');
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const nameAndArch = `AMDGPU (${archAndCode.toLowerCase()})`;
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Object.assign(devices, {
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[nameAndArch]: await this.postProcessAsm(
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{
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okToCache: demangle,
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...this.amdgpuAsmParser.process(asm, {...filters, binary: false}),
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},
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{...filters, binary: false},
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),
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});
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} catch (err) {
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logger.error('[extractDeviceCode]: exception running postProcessAsm for', name, err);
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// Never let a single device-asm failure take down the whole result.
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}
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}),
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...bcDeviceFiles.map(async name => {
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try {
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await this.processBcDeviceFile(name, dirPath, filters, !!demangle, devices);
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} catch (err) {
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logger.error('[extractDeviceCode]: exception running processBcDeviceFile for', name, err);
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// Never let a single device-IR failure take down the whole result.
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}
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}),
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]);
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result.devices = devices;
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}
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return result;
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}
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}
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