Commit Graph

3 Commits

Author SHA1 Message Date
Matt Godbolt
9e9e035b28 Rephrase frontend imports (#7824)
- Removes `rootDirs` so all imports will be relative in the frontend
- Updates (and unifies) imports to be `../types/...` etc instead of
relying on "types" being in the rootDir for the frontend.
- Fixes one type that was being picked up from `lib` in the frontend.
- Adds a precommit hook to check in future

Paves the way to writing _unit_ tests for the frontend for the subset of
the frontend code we can import from `node` (which might be a lot of
it!)
2025-06-18 09:04:23 -05:00
Rupert Tombs
afccba613e Quash some warnings in tests (#7415)
- Prevent some warnings in the `test-and-deploy` action; see, for
example, `Run checks` at
https://github.com/compiler-explorer/compiler-explorer/actions/runs/13421609790/job/37495341332:
  - Await a result to avoid:
```text
Promise returned by `expect(actual).toMatchFileSnapshot(expected)` was not awaited. Vitest currently auto-awaits hanging assertions at the end of the test, but this will cause the test to fail in Vitest 3. Please remember to await the assertion.
    at it.timeout(/home/runner/work/compiler-explorer/compiler-explorer/test/filter-tests.ts:91:50)
```
- Remove duplicated `AVRrc` entries in
`lib/asm-docs/generated/asm-docs-avr.ts`. `AVRrc` is a [reduced core
AVR](https://ww1.microchip.com/downloads/en/DeviceDoc/AVR-InstructionSet-Manual-DS40002198.pdf#page=18),
not an opcode. This avoids a warning beginning `[vite] warning: This
case clause will never be evaluated because it duplicates an earlier
case clause`.
    - Update generator script to also filter `AVRe`.
- Deduplicate `RLDICL` in `lib/asm-docs/generated/asm-docs-power.ts`.
IBM document this instruction both
[here](https://www.ibm.com/docs/en/aix/7.3?topic=is-rldicl-rotate-left-double-word-immediate-then-clear-left-instruction)
and
[here](https://www.ibm.com/docs/en/aix/7.3?topic=is-rldicl-rotate-left-double-word-immediate-then-clear-left-instruction-1).
I choose the neater-looking one, which is also more similar to their
[`RLDICR`](https://www.ibm.com/docs/en/aix/7.3?topic=is-rldicr-rotate-left-double-word-immediate-then-clear-right-instruction)
documentation. This avoids warnings beginning `[vite] warning: This case
clause will never be evaluated because it duplicates an earlier case
clause`.
2025-02-24 10:05:31 -06:00
Nicholas Hubbard
a9257430f3 Add assembly documentation for PowerPC platform (#6665)
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Hello all, I've added assembly documentation for the PowerPC platform
with this PR.

There's a couple of notes to keep in mind, mostly regarding automatic
processing:

1. Unfortunately, IBM made their documentation site very difficult to
automatically scrape. It uses dynamic rendering with a documentation API
that's protected by cookies, requiring the use of Selenium to scrape it.
2. While it is possible to scrape the documentation pages, it's
maddeningly difficult to do so, because the structure of the pages is
not guaranteed.
- Some pages have invisible elements in their headers that make matching
elements very difficult.
     - Some pages are missing entire sections.
- Some pages are written without an introduction for the instruction
mnemonic, making the resulting documentation impossible to understand.
- Some pages, specifically for instructions without arguments, are
missing the table that lists the mnemonics out in order.
- I could go on, but I abandoned trying to do automatic processing after
running into this many roadblocks.
3. The automatic processing script is available in the docenizers
directory, but since it's not complete, feel free to ask to remove it.
4. I couldn't test the actual mnemonics appearing the editor, because my
local test setup kept trying to map the PowerPC instructions into AMD64
documentation, with predictably unusual results.
5. I didn't include AltiVec instructions, because there isn't any
webpage that documents them; they are only documented in a PDF file
provided by NXP.

Please let me know if there's anything else I need to do for this to
work. Thank you so much for your wonderful service!
2024-07-01 14:52:10 +02:00